WO2021159588A1 - 一种键合结构及其制造方法 - Google Patents

一种键合结构及其制造方法 Download PDF

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Publication number
WO2021159588A1
WO2021159588A1 PCT/CN2020/080805 CN2020080805W WO2021159588A1 WO 2021159588 A1 WO2021159588 A1 WO 2021159588A1 CN 2020080805 W CN2020080805 W CN 2020080805W WO 2021159588 A1 WO2021159588 A1 WO 2021159588A1
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wafer
bonding
pad
layer
hybrid
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PCT/CN2020/080805
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English (en)
French (fr)
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胡杏
刘天建
胡胜
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武汉新芯集成电路制造有限公司
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Priority to US17/797,603 priority Critical patent/US20230053721A1/en
Publication of WO2021159588A1 publication Critical patent/WO2021159588A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L24/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L24/09—Structure, shape, material or disposition of the bonding areas after the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/09—Structure, shape, material or disposition of the bonding areas after the connecting process of a plurality of bonding areas
    • H01L2224/091—Disposition
    • H01L2224/0912—Layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/09—Structure, shape, material or disposition of the bonding areas after the connecting process of a plurality of bonding areas
    • H01L2224/091—Disposition
    • H01L2224/0912—Layout
    • H01L2224/0913—Square or rectangular array
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/808—Bonding techniques
    • H01L2224/8085—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/80885—Combinations of two or more hardening methods provided for in at least two different groups from H01L2224/80855 - H01L2224/8088, e.g. for hybrid thermoplastic-thermosetting adhesives
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/808—Bonding techniques
    • H01L2224/80894—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
    • H01L2224/80895—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces between electrically conductive surfaces, e.g. copper-copper direct bonding, surface activated bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area

Definitions

  • the invention relates to the field of semiconductor devices and their manufacturing, in particular to a bonding structure and a manufacturing method thereof.
  • Hybrid bonding is an application of wafer-level bonding.
  • the wafers are connected together through a bonding pad and a dielectric layer.
  • an aluminum pad is formed from the back of the wafer.
  • the aluminum pad usually has a larger area. For example, in a region above 40 ⁇ m ⁇ 40 ⁇ m, a large area of metal is prone to dents during the manufacturing process. In severe cases, defects may occur, which may lead to device failure.
  • the purpose of the present invention is to provide a bonding structure and a manufacturing method thereof, so as to avoid the failure of the device caused by the depression.
  • the present invention has the following technical solutions:
  • a bonding structure including:
  • a second wafer bonded to the front surface of the first wafer, an interconnect structure and a second hybrid bonding structure on the interconnect structure are formed on the front surface of the second wafer, and the second hybrid bond
  • the bonding structure includes a second dielectric bonding layer and a second conductive bonding pad, and the first wafer and the second wafer are bonded to each other through the first hybrid bonding structure and the second hybrid bonding structure;
  • a pad electrically connected to the interconnect structure is formed from the back of the second wafer, wherein, under the pad, the interconnect structure and the second conductive bonding pad are in a horizontal direction Stagger the settings.
  • the slots in the interconnection layers of adjacent layers in the interconnection structure are staggeredly distributed.
  • vias in adjacent layers of the interconnect structure are staggered.
  • the liner is formed in the opening of the substrate where the second wafer is located.
  • the liner is formed in the opening of the substrate where the second wafer is located, and covers a part of the back surface of the second wafer.
  • a method for manufacturing a bonding structure includes:
  • a first wafer is provided on which a first hybrid bonding structure is formed, and the first hybrid bonding structure includes a first dielectric bonding layer and a first conductive bonding pad;
  • a second wafer is provided, an interconnection structure and a second hybrid bonding structure on the interconnection structure are formed on the front surface of the second wafer, the second hybrid bonding structure including a second dielectric bonding layer and Second conductive bonding pad;
  • the slots in the interconnection layers of adjacent layers in the interconnection structure are staggeredly distributed.
  • vias in adjacent layers in the interconnect structure are staggered.
  • the pad formed from the back surface of the second wafer and electrically connected to the interconnection structure includes:
  • a pad electrically connected to the interconnect structure is formed in the opening.
  • the pad formed from the back surface of the second wafer and electrically connected to the interconnection structure includes:
  • a pad electrically connected to the interconnect structure is formed in the opening, and the pad covers a part of the back surface of the second wafer.
  • An embodiment of the present invention provides a bonding structure and a manufacturing method thereof.
  • a first hybrid bonding structure is formed on a first wafer, and an interconnection structure and a second hybrid bonding structure are formed on the front surface of the second wafer.
  • the first wafer and the second wafer are bonded through the first hybrid bonding structure and the second hybrid bonding structure, and a gasket that is electrically connected to the interconnection structure is formed from the back of the second wafer.
  • the second conductive bonding pads in the interconnect structure and the second hybrid bonding structure are staggered in the horizontal direction. In this solution, by staggering the arrangement of the conductive bonding pads in the interconnect structure and the hybrid bonding structure, the recesses caused by the structure stacking are avoided, and thus the device failure caused by the recesses is avoided.
  • Fig. 1 shows a schematic flow chart of a method for manufacturing a bonding structure according to an embodiment of the present invention
  • 2-8 show schematic diagrams of the structure in the process of forming the bonding structure according to the manufacturing method of the embodiment of the present invention
  • FIG. 9 shows a schematic top view of the interconnect structure in the bonding structure of the embodiment of the present invention.
  • hybrid bonding uses bonding pads and dielectric layers to connect the wafers together. Then, an aluminum pad is formed from the backside of the wafer.
  • the aluminum pad usually has a larger area and a large area of metal In the manufacturing process, it is easy to produce depressions, and in severe cases, defects may occur, which may lead to failure of the device.
  • the present application provides a bonding structure, referring to FIG. 7 and FIG. 8, including:
  • a second wafer 20 bonded to the front surface of the first wafer 10, an interconnect structure 211 and a second hybrid bonding structure on the interconnect structure 211 are formed on the front surface of the second wafer 20, so
  • the second hybrid bonding structure includes a second dielectric bonding layer 230 and a second conductive bonding pad 233.
  • the first wafer 10 and the second wafer 20 pass through the first hybrid bonding structure and the second hybrid bonding layer.
  • the bonding structure is mutually bonded;
  • the pads 233 are staggered in the horizontal direction.
  • the first wafer 10 and the second wafer 20 described above may have completed device processing on a substrate and formed a hybrid bonding structure, and the substrate may have formed a device structure and a device structure.
  • Electrically connected interconnection structure The device structure is covered by a dielectric layer.
  • the dielectric layer may include multiple layers, for example, an interlayer dielectric layer and an intermetal dielectric layer.
  • the interconnection structure is formed in a dielectric material.
  • the device structure may be a MOS device, For sensor devices, storage devices and/or other passive devices, the interconnection structure may include multiple layers.
  • the interconnection structures of different layers may be interconnected through contact plugs, wiring layers, vias, etc., and the interconnection structure may be made of metal materials. , For example, tungsten, aluminum, copper, etc.
  • the hybrid bonding structure is continued to be formed on the surface of the wafer.
  • This surface is the surface on which the device structure is formed. It can also be referred to as the front side of the wafer.
  • the hybrid bonding structure includes a dielectric bonding layer and a conductive bonding pad.
  • the conductive bonding pad is formed in the dielectric bonding layer and is electrically connected to the interconnect structure in the wafer.
  • conductive bonding pads are formed on the top-level interconnection lines in the wafer, and are electrically connected to the top-level interconnection lines to realize the electrical extraction of the interconnection structure in the wafer.
  • the dielectric bonding layer can be a dielectric material for bonding, and can be a single-layer or stacked-layer structure, for example, silicon oxide (bonding oxide), silicon nitride, NDC (Nitrogen doped Silicon Carbide, nitrogen-doped silicon carbide) or their The combination.
  • the conductive bonding pad is a bonding conductive material, for example, it may be a bonding metal material, and the bonding metal material may be, for example, copper.
  • the first wafer 10 includes a substrate 100, and the substrate 100 may be a semiconductor substrate, for example, a Si substrate, a Ge substrate, a SiGe substrate, SOI (silicon on insulator) , Silicon On Insulator) or GOI (Germanium On Insulator), etc.
  • a first dielectric layer 110 is formed on the substrate 100, and a device structure and an interconnection structure (not shown) are formed in the first dielectric layer 110. Only the top-level interconnection layer 111 and the first dielectric layer 110 are shown in the figure. To protect the device structure and the interconnection structure from damage, the first dielectric layer 110 may be silicon oxide.
  • a first etch stop layer 120 may be formed between the first dielectric layer 110 and the first dielectric bonding layer 130.
  • the first etch stop layer 120 is an etch stop layer when the first conductive bonding pad 133 is formed.
  • the material of an etch stop layer 120 may be silicon nitride, which has a diffusion barrier function.
  • a first dielectric bonding layer 130 is formed above the first etch stop layer 120.
  • the first dielectric bonding layer 130 and the first conductive bonding pad 133 therein form a first hybrid bonding structure, and the first conductive bonding pad 133 is electrically connected to the top-level interconnection layer 111 to lead out the interconnection structure.
  • the second wafer 20 and the first wafer 10 may be the same wafer or different wafers.
  • the second wafer 20 includes a substrate 200 on which a second dielectric layer 210 is formed, and a device structure (not shown) and an interconnection structure 211 are formed in the second dielectric layer 210.
  • the second dielectric layer 210 is located on the substrate 200, and an interconnect structure 211 is formed in the second dielectric layer 210, that is, an interconnect structure 211 is formed on the front surface of the second wafer 20, and the second dielectric layer 210 is bonded to the second dielectric
  • a second etch stop layer 220 may be formed between the bonding layers 230.
  • the second etch stop layer 220 is an etch stop layer when the second conductive bonding pad 233 is formed.
  • the second etch stop layer 220 may have The same structure or material of an etch stop layer 120 may also be of different structures or materials.
  • the second dielectric bonding layer 230 and the second conductive bonding pad 233 therein form a second hybrid bonding structure, and the second hybrid bonding structure is electrically connected to the interconnect structure 211.
  • the first wafer 10 and the second wafer 20 are bonded through the first hybrid bonding structure and the second hybrid bonding structure.
  • the second wafer after bonding is shown in FIG.
  • a pad 212 electrically connected to the interconnect structure 211 is formed on the back of the 20 to lead out the interconnect structure 211.
  • the pad 212 may be a metal material, such as aluminum, and the area of the pad 212 is, for example, 50 ⁇ m ⁇ 50 ⁇ m.
  • the interconnect structure 211 and the second hybrid bonding structure are located in different areas.
  • the interconnect structure 211 may be located on the right side of the bonded wafer
  • the second hybrid bonding structure may be located on the bonded wafer.
  • the staggered arrangement of the interconnect structure 211 and the second conductive bonding pad 233 in the second hybrid bonding structure prevents the local depression of the multilayer structure stack from affecting subsequent bonding.
  • FIG. 9 is a schematic diagram of the top structure of the interconnect structure 211.
  • the slots in the interconnection layer do not overlap in the vertical direction.
  • the slots 1 in one interconnection layer are staggered with the slots 2 in the adjacent interconnection layer.
  • the subsequent chemical mechanical polishing planarizes the dielectric layer to form a liner, it can effectively alleviate the accumulation of sags caused by the direct distribution of multiple slots, and avoid the occurrence of sags on the device. Performance impact.
  • FIG. 9 is a schematic diagram of the top structure of the interconnect structure 211.
  • the slots in the interconnection layer do not overlap in the vertical direction.
  • the slots 1 in one interconnection layer are staggered with the slots 2 in the adjacent interconnection layer.
  • the vias of adjacent layers in the interconnect structure 211 are staggered, and the vias connect the interconnection layer and the vias that connect the adjacent layers do not overlap in the vertical direction.
  • the via 3 may be a via connecting the first interconnection layer and the second interconnection layer in the interconnection structure
  • the via 4 may be a via connecting the second interconnection layer and the third interconnection layer in the interconnection structure.
  • the holes, the vias 3 and the vias 4 are arranged staggered in the vertical direction to avoid the structure stacking to generate more dents and reduce the formation of the dents before bonding.
  • the pad 212 is formed in the opening of the substrate 200 where the second wafer 20 is located, and electrically connects the interconnect structure 211 in the dielectric layer 210, and connects the interconnect structure 211.
  • the formation of recesses is avoided without increasing the area of the pad 212 and affecting the contact resistance.
  • chemical mechanical polishing may be performed after the interconnection structure 211 is formed. The chemical mechanical polishing process is likely to produce depressions, and the formation of depressions can be effectively avoided by the staggered structure.
  • an opening 201 is formed in the substrate 200 where the second wafer 20 is located, and the spacer 212 is formed in the opening 201 of the substrate 200 where the second wafer 20 is located, and covers Part of the back of the second wafer 20.
  • the size of the opening in this embodiment is smaller than that in the previous embodiment. For example, the size of the opening only needs to occupy 20% of the size of the opening in the above embodiment.
  • the spacer 212 is formed on the back of the substrate 200 and the opening 201 to reduce the area of the wafer occupied by the spacer 212 structure, and reduce the consumption of the spacer 212 on the substrate during the bonding process.
  • the conductive The bonding pad 233 and the interconnect structure 211 are formed in different areas, and the pad 212 is formed on the back of the second wafer 20, which greatly saves the area of the pad on the bonding wafer.
  • the area of the liner saved can reach 50%.
  • step S01 a first wafer 10 is provided, and a first hybrid bonding structure is formed on the first wafer 10, and the first hybrid bonding structure includes a first dielectric bonding layer Refer to FIG. 2 for reference 130 and the first conductive bonding pad 133.
  • the first wafer 10 may have formed a device structure and an interconnection structure electrically connected to the device structure on the substrate 100.
  • the figure only shows the top interconnection layer 111 in the interconnection structure.
  • the substrate 100 may be a semiconductor substrate, for example, a Si substrate, a Ge substrate, a SiGe substrate, SOI (Silicon On Insulator) or GOI (Germanium On Insulator), etc.
  • the device structure is defined by the first Covered by a dielectric layer 110, the top interconnect layer 111 is formed in the dielectric material, and the top interconnect layer 111 may be a metal material, such as tungsten, aluminum, copper, or the like.
  • a first hybrid bonding structure is formed on the first wafer 10, and the first hybrid bonding structure can be formed on the front surface of the first wafer 10.
  • the front surface of the first wafer structure 10 is the surface on which the device structure is formed.
  • the hybrid bonding structure includes a first dielectric bonding layer 130 and a first conductive bonding pad 133.
  • the first conductive bonding pad 133 is formed in the dielectric bonding layer 130 and is connected to the top interconnect layer in the wafer. 111 is electrically connected.
  • the first conductive bonding pad 133 is formed on the top-level interconnection layer 111 of the wafer, and is electrically connected to the top-level interconnection layer 111, so as to realize the interconnection layer in the wafer. Electric lead.
  • the first conductive bonding pad 133 may have a suitable structure. In one example, it may include a wiring hole at the bottom and a via hole thereon.
  • the method of forming the first conductive bonding pad 133 may include forming a photoresist layer on the first dielectric bonding layer 130, and using photolithography technology to transfer the pattern of the connection hole 131 to the photoresist layer Above, the first dielectric bonding layer 130 is etched under the cover of the photoresist layer. During the etching process, the etch stop layer 120 can be used as a stop layer to avoid causing a large impact on the first dielectric layer 120.
  • the first dielectric bonding layer 130 and the etching stop layer 120 can be further etched through the first dielectric layer 110, thereby forming a connection hole 131 in the first dielectric bonding layer 130, and then the photoresist layer is removed , Refer to Figure 2, and then fill the connection hole 131 with a metal material.
  • a metal layer will be formed on the first dielectric bonding layer 130 at the same time, and a mask layer will be formed above the metal layer.
  • the metal layer and part of the first dielectric bonding layer 130 are etched to form a via 132 above the connection hole 131 in the first dielectric bonding layer 130, and the filling material in the connection hole 131 is removed, so that the A bonding hole composed of a connecting hole 131 and a via 132 is formed in a dielectric bonding layer 130, as shown in FIG. 3, and then a metal material is filled in the bonding hole, and a planarization process is performed to remove the first dielectric bonding layer 130
  • the upper metal material forms the first conductive bonding pad 133 in the first dielectric bonding layer 130, as shown in FIG. 4.
  • step S02 a second wafer 20 is provided.
  • An interconnect structure 211 and a second hybrid bonding structure on the interconnect structure 211 are formed on the front surface of the second wafer 20.
  • the bonding structure includes a second dielectric bonding layer 230 and a second conductive bonding pad 233, as shown in FIG. 5.
  • the second wafer 20 and the first wafer 10 may be the same wafer or different wafers.
  • the second wafer 20 may also have a device structure and an interconnection structure 211 electrically connected to the device structure.
  • the interconnect structure 211 is formed on the front surface of the second wafer 20, that is, on the surface where the device structure is formed. As shown in FIG. 5, the interconnect structure 211 is formed in the second dielectric layer 210.
  • the material of the dielectric layer 110 is the same, for example, silicon oxide.
  • the interconnect structure 211 is electrically connected to the second conductive bonding pad 233 in the second hybrid bonding structure, so that the second conductive bonding pad 233 electrically connects the interconnect structure 211. Lead out.
  • the slots in the interconnect layers of adjacent layers in the interconnect structure 211 are staggered. As shown in FIG. 9, the slots in the interconnect layers of adjacent layers do not overlap in the vertical direction. Alleviate the accumulation of recesses in the planarization process of subsequent chemical mechanical polishing, and avoid the influence of the formation of recesses on bonding.
  • the vias of adjacent layers in the interconnect structure 211 are staggered, and the vias connecting the adjacent layers do not overlap in the vertical direction, which further avoids the formation of recesses.
  • step S03 the front side of the second wafer 20 is bonded to the first wafer 10 through the first hybrid bonding structure and the second hybrid bonding structure, as shown in FIG. 6.
  • the front side of the second wafer 20 is bonded to the first wafer 10 through the first hybrid bonding structure in the first wafer 10 and the second hybrid bonding structure in the second wafer 20.
  • the first conductive bonding pad 133 of the second wafer 20 is aligned with the second conductive bonding pad 233 of the second wafer 20, and the bonding force between the hybrid bonding structure is used to realize the bonding of the first wafer 10 and the second wafer 20 Bonded connection.
  • step S04 a pad 212 formed from the backside of the second wafer 20 and electrically connected to the interconnect structure 211, wherein, under the pad 212, the interconnect structure 211 is connected to the
  • the second conductive bonding pads 233 in the second hybrid bonding structure are located in different regions, as shown in FIG. 7 and FIG. 8.
  • the pad 212 formed on the back of the second wafer 20 is electrically connected to the interconnect structure 211, thereby leading the interconnect structure 211, and the interconnect structure 211 is connected to the second conductive structure in the second hybrid bonding structure.
  • the bonding pad 233 is formed under the pad 212 and is located in a different area.
  • the interconnect structure 211 is located in the right area of the pad 212
  • the second hybrid bonding structure is located in the left area of the pad 212
  • the interconnect structure The staggered arrangement of the 211 and the second conductive bonding pad 233 in the second hybrid bonding structure avoids the depression caused by the structure stacking, thereby avoiding the influence of the depression on the bonding.
  • an opening 201 is formed in the substrate 200 where the second wafer 20 is located.
  • the size of the opening is, for example, greater than 50 ⁇ m ⁇ 50 ⁇ m.
  • the method of forming the opening may include forming a mask layer on the back of the substrate 200 Then, the substrate 200 is etched with the mask layer as a shield, thereby forming an opening 201 on the substrate 200, and then the mask layer is removed.
  • a pad 212 electrically connected to the interconnect structure 211 is formed in the opening. Specifically, after the opening 201 is formed, the opening 201 exposes the material of the second dielectric layer 210.
  • An insulating layer 240 is formed in the opening 201 to isolate the liner 212 from the substrate 200 to avoid the influence of the diffusion of metal materials on the substrate 200.
  • the material of the insulating layer 240 may be the same as that of the second dielectric layer 210, for example, silicon oxide. , It can also be different, the material of the insulating layer 240 can be a photoresist material, or a photoresist layer can be formed on the insulating layer 240 at the bottom of the opening 201, and a pattern of connecting holes can be formed on the photoresist layer by processes such as exposure and development.
  • the second dielectric layer 210 is etched with the photoresist layer as a shield, thereby forming a connection hole in the second dielectric layer 210.
  • connection hole is a small hole that opens the interconnect structure 211, and the connection hole and the opening are filled with metal material , And then remove the sidewalls of the opening 201 and the metal material above the substrate 200, thereby forming a gasket 212 in the opening 201.
  • the gasket 212 leads out the interconnect structure in the bonded wafer.
  • the area of the liner 212 does not affect the contact resistance while effectively avoiding the influence of the depression caused by the process of chemical mechanical polishing of the interconnect structure 211 on the bonding.
  • step S4201 an opening 201 is formed in the substrate 200 where the second wafer 20 is located, and the size of the opening 201 only needs to occupy 20% of the opening size of the foregoing embodiment, for example, it may be 10 ⁇ m ⁇ 10 ⁇ m.
  • the method of forming the opening is the same as step S4101 in the above embodiment.
  • step S4202 after the opening 201 is formed on the back of the substrate 200, a covering insulating layer 240 is deposited in the opening 201 to protect the substrate 200 from the diffusion of metal materials, and then the insulating layer 240 at the bottom of the opening 201 is etched And the second dielectric layer 210 until the interconnect structure 211 is exposed to form a connection hole, the connection hole and the opening are filled with metal material, and then a part of the metal material above the substrate 200 is removed to form a liner 212.
  • the liner 212 is formed in the first
  • the second wafer 20 is located in the opening of the substrate 200 and covers a part of the back surface of the second wafer 20. As shown in FIG.
  • the spacer 212 leads out the interconnect structure 211 in the bonded wafer.
  • the metal material is deposited on the back of the substrate 200 at the same time, and a part of the metal material on the back of the substrate 200 is removed, so that a liner 212 is formed in the opening 201 and the back of the second wafer 20, without the need for liner A larger opening is formed on the bottom 200 to reduce the loss of the substrate.
  • part of the substrate 200 needs to be removed, so that the height of the pad 212 is higher than or equal to the height of the substrate 200, so that the pad 212 is used in the subsequent process.
  • the top metal on the substrate 200 that is, the metal on the back of the second wafer 20 with the pad 212 can be directly used as the rewiring layer.
  • the pad on the bonding wafer can be greatly saved.
  • the area of the pad In a specific embodiment, the area of the liner saved can reach 50%.

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Abstract

本发明提供一种键合结构及其制造方法，在第一晶圆上形成有第一混合键合结构，第二晶圆正面上形成有互连结构以及第二混合键合结构，第一晶圆和第二晶圆通过第一混合键合结构和第二混合键合结构实现键合，从第二晶圆的背面形成与互连结构电连接的衬垫，在衬垫下方的互连结构和第二混合键合结构中的第二导电键合垫在水平方向上错开设置。该方案中，通过将互连结构以及第二导电键合垫错开排布，避免结构堆叠产生的凹陷，进而避免凹陷导致的器件失效。

Description

一种键合结构及其制造方法
本申请要求于2020年02月12日提交中国专利局、申请号为202010088771.6、发明名称为“一种键合结构及其制造方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及半导体器件及其制造领域，特别涉及一种键合结构及其制造方法。
背景技术
随着半导体技术进入后摩尔时代，为满足高集成度和高性能的需求，芯片结构向着三维方向发展，而晶圆级键合技术得到了广泛的应用。混合键合是晶圆级键合的一个应用，在键合时通过键合垫和介质层使得晶圆连接在一起，而后，从晶圆的背面形成铝垫，铝垫通常具有较大的面积，例如40μm×40μm以上的区域，大片面积的金属在制造过程中容易产生凹陷，严重时会产生缺陷，进而导致器件的失效。
发明内容
有鉴于此，本发明的目的在于提供一种键合结构及其制造方法，避免凹陷导致器件的失效。
为实现上述目的，本发明有如下技术方案：
一种键合结构，包括：
第一晶圆，所述第一晶圆上形成有第一混合键合结构，所述第一混合键合结构包括第一介质键合层以及第一导电键合垫；
与所述第一晶圆正面键合的第二晶圆，所述第二晶圆正面上形成有互连结构和所述互连结构上的第二混合键合结构，所述第二混合键合结构包括第二介质键合层以及第二导电键合垫，所述第一晶圆和第二晶圆通过所述第一混合键合结构和第二混合键合结构相互键合；
从所述第二晶圆的背面形成有与所述互连结构电连接的衬垫，其中，在所述衬垫下方，所述互连结构与所述第二导电键合垫在水平方向上错开设置。
可选的，所述互连结构中相邻层的互连层中的槽孔交错分布。
可选的，所述互连结构相邻层的过孔交错分布。
可选的，所述衬垫形成于所述第二晶圆所在衬底的开口中。
可选的，所述衬垫形成于第二晶圆所在衬底的开口中，并覆盖第二晶圆的部分背面。
一种键合结构的制造方法，包括：
提供第一晶圆，所述第一晶圆上形成有第一混合键合结构，所述第一混合键合结构包括第一介质键合层以及第一导电键合垫；
提供第二晶圆，所述第二晶圆正面上形成有互连结构和所述互连结构上的第二混合键合结构，所述第二混合键合结构包括第二介质键合层以及第二导电键合垫；
通过所述第一混合键合结构和第二混合键合结构，将所述第二晶圆正面键合至所述第一晶圆；
从所述第二晶圆的背面形成且与所述互连结构电连接的衬垫，其中，在所述衬垫下方，所述互连结构与所述第二导电键合垫在水平方向上错开设置。
可选的，所述互连结构中相邻层的互连层中的槽孔交错分布。
可选的，所述互连结构中相邻层的过孔交错分布。
可选的，从所述第二晶圆的背面形成且与所述互连结构电连接的衬垫，包括：
从所述第二晶圆所在衬底中形成开口；
在所述开口中形成与所述互连结构电连接的衬垫。
可选的，从所述第二晶圆的背面形成且与所述互连结构电连接的衬垫，包括：
从所述第二晶圆所在衬底中形成开口；
在所述开口中形成与所述互连结构电连接的衬垫，所述衬垫并覆盖第二晶 圆的部分背面。
本发明实施例提供的一种键合结构及其制造方法，在第一晶圆上形成有第一混合键合结构，第二晶圆正面上形成有互连结构以及第二混合键合结构，第一晶圆和第二晶圆通过第一混合键合结构和第二混合键合结构实现键合，从第二晶圆的背面形成与互连结构电连接的衬垫，在衬垫下方的互连结构和第二混合键合结构中的第二导电键合垫在水平方向上错开设置。该方案中，通过将互连结构以及混合键合结构中的导电键合垫错开排布，避免结构堆叠产生的凹陷，进而避免凹陷导致的器件失效。
附图说明
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其它的附图。
图1示出了根据本发明实施例键合结构的制造方法的流程示意图；
图2-8示出了根据本发明实施例的制造方法形成键合结构过程中的结构示意图；
图9示出了本发明实施例键合结构中的互连结构的俯视结构示意图。
具体实施方式
为使本发明的上述目的、特征和优点能够更加明显易懂，下面结合附图对本发明的具体实施方式做详细的说明。
在下面的描述中阐述了很多具体细节以便于充分理解本发明，但是本发明还可以采用其它不同于在此描述的其它方式来实施，本领域技术人员可以在不违背本发明内涵的情况下做类似推广，因此本发明不受下面公开的具体实施例的限制。
其次，本发明结合示意图进行详细描述，在详述本发明实施例时，为便于说明，表示器件结构的剖面图会不依一般比例作局部放大，而且所述示意图只是示例，其在此不应限制本发明保护的范围。此外，在实际制作中应包含长度、 宽度及深度的三维空间尺寸。
正如背景技术中的描述，混合键合是通过键合垫和介质层使得晶圆连接在一起，而后，从晶圆的背面形成铝垫，铝垫通常具有较大的面积，大片面积的金属在制造过程中容易产生凹陷，严重时会产生缺陷，进而导致器件的失效。
为此，本申请提供一种键合结构，参考图7和图8，包括：
第一晶圆10，所述第一晶圆10上形成有第一混合键合结构，所述第一混合键合结构包括第一介质键合层130以及第一导电键合垫133；
与所述第一晶圆10正面键合的第二晶圆20，所述第二晶圆20正面上形成有互连结构211和所述互连结构211上的第二混合键合结构，所述第二混合键合结构包括第二介质键合层230以及第二导电键合垫233，所述第一晶圆10和第二晶圆20通过所述第一混合键合结构和第二混合键合结构相互键合；
从所述第二晶圆20的背面形成且与所述互连结构211电连接的衬垫212，其中，在所述衬垫212下方，所述互连结构211与所述第二导电键合垫233在水平方向上错开设置。
在本申请实施例中，上述第一晶圆10和第二晶圆20可以已在衬底上完成器件的加工并形成有混合键合结构，衬底上可以已经形成有器件结构以及与器件结构电连接的互连结构，器件结构由介质层覆盖，介质层可以包括多层，例如可以包括层间介质层和金属间介质层，互连结构形成于介质材料中，器件结构可以为MOS器件、传感器件、存储器件和/或其他无源器件，互连结构可以包括多层，不同层的互连结构可以通过接触塞、连线层、过孔等实现互连，互连结构可以为金属材料，例如可以为钨、铝、铜等。
在完成器件加工之后，在晶圆的表面上继续形成混合键合结构，该表面为形成有器件结构的表面，也可以称作晶圆的正面，混合键合结构是指键合界面由不同的材质的键合材料形成，在本申请中，该混合键合结构包括介质键合层和导电键合垫，导电键合垫形成于介质键合层中，且与晶圆中的互连结构电连接，通常地，导电键合垫形成于晶圆中的顶层互连线上，与顶层互连线电连接，实现晶圆中互连结构的电引出。其中，介质键合层可以为键合用介质材料，可 以为单层或叠层结构，例如可以为氧化硅(bonding oxide)、氮化硅、NDC(Nitrogen doped Silicon Carbide，掺氮碳化硅)或他们的组合。导电键合垫为键合导电材料，例如可以为键合金属材料，键合金属材料例如可以为铜。
本实施例中，参考图4所示，第一晶圆10包括衬底100，衬底100可以为半导体衬底，例如可以为Si衬底、Ge衬底、SiGe衬底、SOI(绝缘体上硅，Silicon On Insulator)或GOI(绝缘体上锗，Germanium On Insulator)等。衬底100上形成有第一介质层110，第一介质层110中形成有器件结构以及互连结构(图未示出)，图中仅示出了顶层互连层111，第一介质层110保护器件结构以及互连结构不受损伤，第一介质层110可以为氧化硅。在第一介质层110和第一介质键合层130之间可以形成第一刻蚀停止层120，第一刻蚀停止层120为形成第一导电键合垫133时的刻蚀停止层，第一刻蚀停止层120的材料可以为氮化硅，具有扩散阻挡的作用。在第一刻蚀停止层120的上方形成第一介质键合层130，第一介质键合层130以及其中的第一导电键合垫133形成第一混合键合结构，第一导电键合垫133与顶层互连层111电连接，将互连结构引出。
第二晶圆20与第一晶圆10可以为相同的晶圆，可以为不同的晶圆。参考图5所示，第二晶圆20包括衬底200，衬底200上形成有第二介质层210，第二介质层210中形成有器件结构(图未示出)以及互连结构211，第二介质层210位于衬底200上，在第二介质层210中形成互连结构211，即在第二晶圆20的正面形成有互连结构211，第二介质层210与第二介质键合层230之间可以形成有第二刻蚀停止层220，第二刻蚀停止层220为形成第二导电键合垫233时的刻蚀停止层，第二刻蚀停止层220可以具有与第一刻蚀停止层120相同的结构或材料，也可以为不同的结构或材料。第二介质键合层230以及其中的第二导电键合垫233形成第二混合键合结构，第二混合键合结构与互连结构211电连接。
参考图6所示，第一晶圆10和第二晶圆20通过第一混合键合结构和第二混合键合结构实现键合，参考图7所示，在键合后的第二晶圆20的背面形成 与互连结构211电连接的衬垫212，从而将互连结构211引出，衬垫212可以为金属材料，例如可以为铝，衬垫212的面积例如为50μm×50μm。在衬垫212的下方，互连结构211与第二混合键合结构位于不同的区域，例如互连结构211可以位于键合晶圆的右侧，第二混合键合结构可以位于键合晶圆的左侧，互连结构211与第二混合键合结构中的第二导电键合垫233的错开排布，避免多层结构堆叠产生局部凹陷对后续键合产生影响。
本实施例中，参考图9所示，图9为互连结构211的俯视结构示意图，互连结构211中相邻层的互连层中的槽孔(slot)交错分布，相邻层的互连层中的槽孔在垂直方向上不产生交叠，参考图9所示，其中一层互连层中的槽孔1与相邻的另一层互连层中的槽孔2错开排布，通过互连层中槽孔的错开排布，在后续进行化学机械研磨平坦化介质层以形成衬垫时，有效缓解多个槽孔正对分布所造成的凹陷积累，避免凹陷的产生对器件性能的影响。在另一些实施例中，参考图9所示，互连结构211中相邻层的过孔交错分布，过孔连接互连层并且连接相邻层的过孔在垂直方向上不产生交叠，例如，过孔3可以是连接互连结构中第一互连层与第二互连层的通孔，过孔4可以是连接互连结构中第二互连层与第三互连层的通孔，过孔3与过孔4在垂直方向上错开排布，避免结构堆叠产生较多的凹陷，减少键合前凹陷的形成。
在一个实施例中，参考图7所示，衬垫212形成于第二晶圆20所在衬底200的开口中，电连接介质层210中的互连结构211，将互连结构211接出，通过将衬垫212下方的互连结构211与第二混合键合结构中的第二导电键合垫233错开排布，在不增加衬垫212面积、不影响接触电阻的同时避免凹陷的形成，为了后续键合的稳定性可以在形成互连结构211之后进行化学机械研磨，化学机械研磨的过程中容易产生凹陷，通过错排结构有效避免凹陷的形成。
在另一个实施例中，参考图8所示，在第二晶圆20所在衬底200中形成有开口201，衬垫212形成于第二晶圆20所在衬底200的开口201中，并覆盖第二晶圆20的部分背面。与图7所示实施例相比，本实施例中的开口尺寸小于上一实施例中的开口尺寸，例如，开口的尺寸只需要占用上述实施例的开 口尺寸的20％，本实施例中，在衬底200背面和开口201中形成衬垫212，减小衬垫212结构占用的晶圆的面积，减少键合工艺过程中衬垫212对衬底的消耗，本实施例中，通过将导电键合垫233与互连结构211形成于不同的区域，以及在第二晶圆20的背面形成衬垫212，大幅度节省键合晶圆上的衬垫的面积。在具体的实施例中，节省的衬垫的面积可以达到百分之五十。
在键合晶圆上形成衬垫之后，可以进一步进行后续的封装等操作。
以上对键合结构进行了详细的描述，此外本申请还提供了键合结构的制造方法，以下将结合附图进行详细的说明。
参考图1所示，在步骤S01中，提供第一晶圆10，所述第一晶圆10上形成有第一混合键合结构，所述第一混合键合结构包括第一介质键合层130以及第一导电键合垫133，参考图2所示。
本申请实施例中，第一晶圆10可以已在衬底100上形成有器件结构以及电连接器件结构的互连结构，图中仅示出了互连结构中的顶层互连层111，衬底100可以为半导体衬底，例如可以为Si衬底、Ge衬底、SiGe衬底、SOI(绝缘体上硅，Silicon On Insulator)或GOI(绝缘体上锗，Germanium On Insulator)等，器件结构由第一介质层110覆盖，顶层互连层111形成于介质材料中，顶层互连层111可以为金属材料，例如可以为钨、铝、铜等。
第一晶圆10上形成有第一混合键合结构，可以在第一晶圆10的正面形成第一混合键合结构，第一晶圆结构10的正面为形成有器件结构的表面，本申请中，该混合键合结构包括第一介质键合层130以及第一导电键合垫133，第一导电键合垫133形成于介质键合层130中，且与晶圆中的顶层互连层111电连接，参考图4所示，通常地，第一导电键合垫133形成于晶圆的顶层互连层111上，与顶层互连层111电连接，从而实现晶圆中互连层的电引出。第一导电键合垫133可以具有合适的结构，在一个示例中，可以包括底部的连线孔和其上的过孔。
本实施例中，形成第一导电键合垫133的方法可以包括，在第一介质键合层130上方形成光刻胶层，利用光刻技术，将连接孔131的图案转移至光刻胶 层上，在光刻胶层的遮蔽下，刻蚀第一介质键合层130，在刻蚀的过程中，可以以刻蚀停止层120为停止层，避免对第一介质层120造成较大的损耗，而后可以进一步刻蚀贯通第一介质键合层130以及刻蚀停止层120，直至第一介质层110，从而在第一介质键合层130中形成连接孔131，而后去除光刻胶层，参考图2所示，而后在连接孔131内填充金属材料，在填充的过程中会同时在第一介质键合层130上形成金属层，在金属层上方形成掩膜层，以掩膜层为遮蔽，刻蚀金属层以及部分第一介质键合层130，从而在第一介质键合层130内的连接孔131的上方形成过孔132，去除连接孔131内的填充材料，从而在第一介质键合层130内形成连接孔131和过孔132组成的键合孔，参考图3所示，而后在键合孔内填充金属材料，并进行平坦化工艺去除第一介质键合层130上方的金属材料，从而在第一介质键合层130内形成第一导电键合垫133，参考图4所示。
在步骤S02中，提供第二晶圆20，所述第二晶圆20正面上形成有互连结构211和与所述互连结构211上的第二混合键合结构，所述第二混合键合结构包括第二介质键合层230以及第二导电键合垫233，参考图5所示。
第二晶圆20与第一晶圆10可以为相同的晶圆，可以为不同的晶圆，第二晶圆20上也可以已经形成有器件结构以及与器件结构电连接的互连结构211。互连结构211形成于第二晶圆20的正面即形成有器件结构的表面上，参考图5所示，互连结构211形成于第二介质层210中，第二介质层210可以与第一介质层110的材料相同，例如可以为氧化硅，互连结构211与第二混合键合结构中的第二导电键合垫233电连接，从而第二导电键合垫233将互连结构211电引出。
本实施例中，互连结构211中相邻层的互连层中的槽孔交错分布，参考图9所示，相邻层的互连层中的槽孔在垂直方向上不产生交叠，缓解后续化学机械研磨进行平坦化过程的凹陷的积累，避免凹陷的形成对键合的影响。在具体的实施例中，互连结构211中相邻层的过孔交错分布，连接相邻层的过孔在垂直方向上不产生交叠，进一步避免凹陷的形成。
在步骤S03中，通过所述第一混合键合结构和第二混合键合结构，将所述第二晶圆20正面键合至所述第一晶圆10，参考图6所示。
通过第一晶圆10中的第一混合键合结构与第二晶圆20中的第二混合键合结构将第二晶圆20正面键合至第一晶圆10，第一晶圆10中的第一导电键合垫133与第二晶圆20中的第二导电键合垫233对准，利用混合键合结构之间的键合力，实现第一晶圆10和第二晶圆20的键合连接。
在步骤S04中，从所述第二晶圆20的背面形成且与所述互连结构211电连接的衬垫212，其中，在所述衬垫212下方，所述互连结构211与所述第二混合键合结构中的第二导电键合垫233位于不同的区域，参考图7和图8所示。
本申请实施例中，在第二晶圆20背面形成的衬垫212与互连结构211电连接，从而将互连结构211引出，互连结构211与第二混合键合结构中的第二导电键合垫233形成于衬垫212的下方，并且位于不同的区域，例如互连结构211位于衬垫212的右侧区域，第二混合键合结构位于衬垫212的左侧区域，互连结构211与第二混合键合结构中的第二导电键合垫233的错开排布，避免结构堆叠产生的凹陷，从而避免凹陷对键合的影响。
本实施例中，在步骤S4101中，在第二晶圆20所在衬底200中形成开口201，开口的尺寸例如大于50μm×50μm，形成开口的方法可以包括，在衬底200背面形成掩膜层，以掩膜层为遮蔽刻蚀衬底200，从而在衬底200上形成开口201，随后去除掩膜层。在步骤S4102中，在所述开口中形成与所述互连结构211电连接的衬垫212，具体的，可以为，在形成开口201之后，开口201暴露第二介质层210材料，在所述开口201内形成绝缘层240，将衬垫212与衬底200隔离开，避免金属材料的扩散对衬底200的影响，绝缘层240材料可以与第二介质层210的材料相同，例如为氧化硅，也可以不同，绝缘层240的材料可以为光刻胶材料，也可以在开口201底部的绝缘层240上方形成光刻胶层，采用曝光、显影等工艺光刻胶层上形成连接孔的图案，以光刻胶层为遮蔽刻蚀第二介质层210，从而在第二介质层210中形成连接孔，该连接孔为打开互连结构211的小孔，在连接孔和开口内填充金属材料，然后去除开口201侧壁以 及衬底200上方的金属材料，从而在开口201内形成衬垫212，参考图7所示，衬垫212将键合晶圆中的互连结构引出，在没有增加衬垫212面积，不影响接触电阻的同时有效避免化学机械研磨互连结构211的过程造成的凹陷对键合的影响。
在另一个实施例中，在步骤S4201中，在第二晶圆20所在衬底200中形成开口201，开口201的尺寸只需要占用上述实施例的开口尺寸的20％，例如可以为10μm×10μm，形成开口的方法同上述实施例中的步骤S4101。在步骤S4202中，在衬底200背面形成开口201之后，在所述开口201内沉积覆盖绝缘层240，保护衬底200不受金属材料扩散造成的影响，而后刻蚀开口201底部的绝缘层240以及第二介质层210，直至露出互连结构211形成连接孔，在连接孔和开口内填充金属材料，然后去除衬底200上方的一部分金属材料，从而形成衬垫212，衬垫212形成于第二晶圆20所在衬底200的开口中，并覆盖第二晶圆20的部分背面，参考图8所示，衬垫212将键合晶圆中的互连结构211引出。在开口201填充金属材料的过程中同时在衬底200背面沉积金属材料，去除部分衬底200背面的金属材料，从而在开口201内和第二晶圆20背面形成衬垫212，不需要在衬底200上形成较大的开口，减少衬底的损耗。同时，在图7所示实施例中，若需要形成再布线层，需要去除部分衬底200，使得衬垫212的高度高于或等于衬底200的高度，从而使得衬垫212作为后续工艺中的再布线层，而在本实施例中，位于衬底200上的顶层金属，即衬垫212位于第二晶圆20背面的那部分金属可直接作为再布线层。通过将混合键合结构中的第二导电键合垫233与互连结构211形成于不同的区域，以及在第二晶圆20的背面形成衬垫212，大幅度节省键合晶圆上的衬垫的面积。在具体的实施例中，节省的衬垫的面积可以达到百分之五十。在键合晶圆上形成衬垫之后，可以进一步进行后续的封装等操作。
本说明书中的各个实施例均采用递进的方式描述，各个实施例之间相同相似的部分互相参见即可，每个实施例重点说明的都是与其它实施例的不同之处。
以上所述仅是本发明的优选实施方式，虽然本发明已以较佳实施例披露如上，然而并非用以限定本发明。任何熟悉本领域的技术人员，在不脱离本发明技术方案范围情况下，都可利用上述揭示的方法和技术内容对本发明技术方案做出许多可能的变动和修饰，或修改为等同变化的等效实施例。因此，凡是未脱离本发明技术方案的内容，依据本发明的技术实质对以上实施例所做的任何的简单修改、等同变化及修饰，均仍属于本发明技术方案保护的范围内。

Claims (10)

  1. 一种键合结构，其特征在于，包括：
    第一晶圆，所述第一晶圆上形成有第一混合键合结构，所述第一混合键合结构包括第一介质键合层以及第一导电键合垫；
    与所述第一晶圆正面键合的第二晶圆，所述第二晶圆正面上形成有互连结构和所述互连结构上的第二混合键合结构，所述第二混合键合结构包括第二介质键合层以及第二导电键合垫，所述第一晶圆和第二晶圆通过所述第一混合键合结构和第二混合键合结构相互键合；
    从所述第二晶圆的背面形成与所述互连结构电连接的衬垫，其中，在所述衬垫下方，所述互连结构与所述第二导电键合垫在水平方向上错开设置。
  2. 根据权利要求1所述的键合结构，其特征在于，所述互连结构中相邻层的互连层中的槽孔交错分布。
  3. 根据权利要求2所述的键合结构，其特征在于，所述互连结构中相邻层的过孔交错分布。
  4. 根据权利要求1-3中任一项所述的键合结构，其特征在于，所述衬垫形成于所述第二晶圆所在衬底的开口中。
  5. 根据权利要求1-3中任一项所述的键合结构，其特征在于，所述衬垫形成于第二晶圆所在衬底的开口中，并覆盖第二晶圆的部分背面。
  6. 一种键合结构的制造方法，其特征在于，包括：
    提供第一晶圆，所述第一晶圆上形成有第一混合键合结构，所述第一混合键合结构包括第一介质键合层以及第一导电键合垫；
    提供第二晶圆，所述第二晶圆正面上形成有互连结构和所述互连结构上的第二混合键合结构，所述第二混合键合结构包括第二介质键合层以及第二导电键合垫；
    通过所述第一混合键合结构和第二混合键合结构，将所述第二晶圆正面键合至所述第一晶圆；
    从所述第二晶圆的背面形成且与所述互连结构电连接的衬垫，其中，在所 述衬垫下方，所述互连结构与所述第二导电键合垫在水平方向上错开设置。
  7. 根据权利要求6所述的制造方法，其特征在于，所述互连结构中相邻层的互连层中的槽孔交错分布。
  8. 根据权利要求7所述的制造方法，其特征在于，所述互连结构中相邻层的过孔交错分布。
  9. 根据权利要求6-8中任一项所述的制造方法，其特征在于，从所述第二晶圆的背面形成且与所述互连结构电连接的衬垫，包括：
    从所述第二晶圆所在衬底中形成开口；
    在所述开口中形成与所述互连结构电连接的衬垫。
  10. 根据权利要求6-8中任一项所述的制造方法，其特征在于，从所述第二晶圆的背面形成且与所述互连结构电连接的衬垫，包括：从所述第二晶圆所在衬底中形成开口；在所述开口中形成与所述互连结构电连接的衬垫，所述衬垫并覆盖第二晶圆的部分背面。
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