TWI579968B - 半導體裝置之製造方法及半導體裝置 - Google Patents
半導體裝置之製造方法及半導體裝置 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims description 90
- 238000004519 manufacturing process Methods 0.000 title claims description 12
- 229910052751 metal Inorganic materials 0.000 claims description 74
- 239000002184 metal Substances 0.000 claims description 74
- 239000000758 substrate Substances 0.000 claims description 65
- 229910000449 hafnium oxide Inorganic materials 0.000 claims description 15
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 claims description 15
- 230000000149 penetrating effect Effects 0.000 claims description 6
- 238000001312 dry etching Methods 0.000 claims description 3
- 239000010410 layer Substances 0.000 description 141
- 230000004888 barrier function Effects 0.000 description 27
- 239000000463 material Substances 0.000 description 20
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 15
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 15
- 239000010949 copper Substances 0.000 description 14
- 230000015572 biosynthetic process Effects 0.000 description 10
- SIWVEOZUMHYXCS-UHFFFAOYSA-N oxo(oxoyttriooxy)yttrium Chemical compound O=[Y]O[Y]=O SIWVEOZUMHYXCS-UHFFFAOYSA-N 0.000 description 10
- 229910001925 ruthenium oxide Inorganic materials 0.000 description 9
- WOCIAKWEIIZHES-UHFFFAOYSA-N ruthenium(iv) oxide Chemical compound O=[Ru]=O WOCIAKWEIIZHES-UHFFFAOYSA-N 0.000 description 9
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 7
- 229910052802 copper Inorganic materials 0.000 description 7
- 238000005530 etching Methods 0.000 description 7
- 239000011229 interlayer Substances 0.000 description 7
- 238000000034 method Methods 0.000 description 7
- 238000002161 passivation Methods 0.000 description 7
- 239000010931 gold Substances 0.000 description 6
- 239000012044 organic layer Substances 0.000 description 6
- 239000010936 titanium Substances 0.000 description 6
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 229910052759 nickel Inorganic materials 0.000 description 5
- 238000009413 insulation Methods 0.000 description 4
- 150000004767 nitrides Chemical class 0.000 description 4
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 229910001936 tantalum oxide Inorganic materials 0.000 description 4
- 229910004298 SiO 2 Inorganic materials 0.000 description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- 229910052735 hafnium Inorganic materials 0.000 description 3
- 229910052719 titanium Inorganic materials 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 2
- 229910007637 SnAg Inorganic materials 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- QCEUXSAXTBNJGO-UHFFFAOYSA-N [Ag].[Sn] Chemical compound [Ag].[Sn] QCEUXSAXTBNJGO-UHFFFAOYSA-N 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- KUNSUQLRTQLHQQ-UHFFFAOYSA-N copper tin Chemical compound [Cu].[Sn] KUNSUQLRTQLHQQ-UHFFFAOYSA-N 0.000 description 2
- JVPLOXQKFGYFMN-UHFFFAOYSA-N gold tin Chemical compound [Sn].[Au] JVPLOXQKFGYFMN-UHFFFAOYSA-N 0.000 description 2
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- 229910052715 tantalum Inorganic materials 0.000 description 2
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 229910000420 cerium oxide Inorganic materials 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- -1 hafnium nitride Chemical class 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- BMMGVYCKOGBVEV-UHFFFAOYSA-N oxo(oxoceriooxy)cerium Chemical compound [Ce]=O.O=[Ce]=O BMMGVYCKOGBVEV-UHFFFAOYSA-N 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 229910052707 ruthenium Inorganic materials 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3081—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their composition, e.g. multilayer masks, materials
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
Description
本申請案享有以日本專利申請2015-110789號(申請日:2015年5月29日)為基礎申請案之優先權。本申請案藉由參照該基礎申請案而包含基礎申請案之全部內容。
本實施形態係關於一種半導體裝置之製造方法及半導體裝置。
近年來,自高功能化等觀點而言,使用TSV(Through-Silicon Via,矽穿孔)之半導體裝置之積體技術受到關注。
於使用TSV之積體技術中,形成於TSV中之貫通電極(以下稱為TSV電極)之穩定性非常重要。但是,由於TSV為高縱橫比,因此難以將金屬等埋設於TSV內。
本發明之實施形態提供一種能夠將金屬等穩定地埋設於TSV內之半導體裝置之製造方法及半導體裝置。
根據實施形態,半導體裝置具備:半導體基板,其設置有自第1面貫通至與上述第1面為相反側之第2面之貫通孔;器件層,其位於上述半導體基板之上述第1面,且包含配線;絕緣層,其覆蓋上述器件層;第1貫通電極,其貫通上述絕緣層;第1絕緣膜,其位於上述半導體基板之上述第2面上,設置有與上述半導體基板之上述貫通孔之開
口徑實質上相同或較大徑之開口;第2絕緣膜,其位於自上述第1絕緣膜上至上述半導體基板之上述貫通孔之內側面;及第2貫通電極,其自上述第2絕緣膜上經由上述半導體基板之上述貫通孔內與上述器件層中之上述配線電連接。
1‧‧‧半導體裝置
11‧‧‧半導體基板
12‧‧‧器件層
13‧‧‧絕緣層
14‧‧‧第2貫通電極
16‧‧‧支持基板
17‧‧‧絕緣層
18‧‧‧第1貫通電極
19‧‧‧接合材
120‧‧‧配線層
121‧‧‧上層配線
122‧‧‧下層配線
141‧‧‧障壁金屬層
142‧‧‧籽晶金屬層
143‧‧‧貫通電極
144‧‧‧材料膜
171‧‧‧氧化矽膜
171A‧‧‧氧化矽膜
171B‧‧‧氧化矽膜
172‧‧‧氮化矽膜
172A‧‧‧氮化矽膜
173‧‧‧氧化矽膜
180H‧‧‧貫通孔
180M‧‧‧感光性光阻劑
181‧‧‧障壁金屬層
181A‧‧‧障壁金屬層
182‧‧‧籽晶金屬層
182A‧‧‧籽晶金屬層
183‧‧‧貫通電極
183M‧‧‧遮罩
圖1係表示實施形態之半導體裝置之概略構成例之剖視圖。
圖2~圖10係表示實施形態之半導體裝置之製造方法之製程剖視圖。
以下,參照隨附圖式,詳細地說明實施形態之半導體裝置及半導體裝置之製造方法。再者,本發明並不受該實施形態限定。又,於以下之說明中,將元件形成對象之半導體基板中之元件形成面設為第1面,將與該第1面為相反側之面設為第2面。
圖1係表示實施形態之半導體裝置之概略構成例之剖視圖。如圖1所示,半導體裝置1具備半導體基板11、器件層12、絕緣層13、第1貫通電極14、絕緣層17、第2貫通電極18及接合材19。
半導體基板11例如為矽基板。該半導體基板11之厚度可被薄化至50μm(微米)以下、例如30±5μm左右。
器件層12包含形成於作為半導體基板11之元件形成面之第1面側之元件構造、及填埋元件構造之層間絕緣膜。層間絕緣膜可為氧化矽膜(SiO2)。元件構造中包含配線層120。該配線層120中包含形成於上層之上層配線121、及形成於下層之下層配線122。再者,所謂器件層12之上層及下層,亦可為以半導體基板11之元件形成面為基準之上層及下層。
絕緣層13覆蓋器件層12,以保護器件層12。該絕緣層13中可包含遮蓋器件層12之鈍化膜、及覆蓋於鈍化膜上之有機層。鈍化膜可為
氮化矽膜(SiN)、氧化矽膜(SiO2)或氮氧化矽膜(SiON)之單層膜、或該等膜中之2層以上之積層膜。有機層可使用感光性聚醯亞胺等樹脂材料。
第1貫通電極14藉由設置於自絕緣層13貫通至器件層12中之上層配線121之貫通孔內並與上層配線121接觸,而將上層配線121電引出至絕緣層13上。該第1貫通電極14可包含至少覆蓋貫通孔內表面之障壁金屬層141、障壁金屬層141上之籽晶金屬層142及籽晶金屬層142上之貫通電極143。亦可省略障壁金屬層141。亦可於貫通電極143上設置半導體裝置1之縱向積體化時發揮功能之材料膜144。
障壁金屬層141中可使用鈦(Ti)、鉭(Ta)、釕(Ru)等。籽晶金屬層142中可使用銅(Cu)或鎳與銅之積層膜(Ni/Cu)等。貫通電極143中可使用鎳(Ni)等。材料膜144中可使用金(Au)、錫(Sn)、銅(Cu)、錫-銅(SnCu)、錫-金(SnAu)、錫-銀(SnAg)等。但是,第1貫通電極14之層構造及材料可根據目的而適當變更。例如可根據用於貫通電極143之導電性材料或形成方法而適當變更障壁金屬層141/籽晶金屬層142或者材料膜144之層構造或材料。
第2貫通電極18藉由設置於自半導體基板11到達至器件層12中之下層配線122之貫通孔(TSV)內並與下層配線122接觸,而將下層配線122電引出至半導體基板11之第2面上。
第2貫通電極18與第1貫通電極14同樣地可包含至少覆蓋貫通孔內表面之障壁金屬層(第1金屬層)181、障壁金屬層181上之籽晶金屬層(第2金屬層)182及籽晶金屬層182上之貫通電極(第3金屬層)183。分別所使用之金屬材料亦可與第1貫通電極14之障壁金屬層141、籽晶金屬層142及貫通電極143相同。亦可於貫通電極183之內部形成空隙。
又,亦可於貫通電極183上設置用以於將複數個半導體裝置1向縱向(半導體基板11之厚度方向)積體時將半導體裝置1間接合之接合材
19。該接合材19中可使用錫(Sn)、銅(Cu)、錫-銅(SnCu)、錫-金(SnAu)、錫-銀(SnAg)等焊料。
於自形成於半導體基板11中之貫通孔內之內側面至半導體基板11之第2面,設置用以防止第2貫通電極18與半導體基板11短路之絕緣層17。該絕緣層17中可包含位於半導體基板11之第2面上之氧化矽膜(SiO2)171、位於氧化矽膜171上之氮化矽膜(SiN)172、及位於氮化矽膜172上至貫通孔(TSV)內側面之氧化矽膜173。氧化矽膜171及/或氮化矽膜172有時被稱為第1絕緣膜。又,氧化矽膜173有時被稱為第2絕緣膜。
此處,絕緣層17中之氧化矽膜171及氮化矽膜172之至少一者與障壁金屬層181及/或籽晶金屬層182於半導體基板11之厚度方向上重疊。藉由該構成,減少作為第2貫通電極18等之材料之鎳(Ni)、銅(Cu)及金(Au)向半導體基板11內擴散。
接下來,以下參照圖式,詳細地說明實施形態之半導體裝置1之製造方法。圖2~圖10係表示實施形態之半導體裝置之製造方法之製程剖視圖。再者,於圖2~圖10中,使用與圖1相同之剖面進行說明。但是,於圖2中,為方便說明,剖面之上下關係與圖1及圖3~圖10之上下關係相反。
首先,於實施形態中,於半導體基板11之元件形成面(第1面)形成元件構造,以層間絕緣膜覆蓋已形成之元件構造。由此,形成器件層12。再者,該層間絕緣膜中可包含所謂之元件分離絕緣膜等各種絕緣膜或配線層等各種層。且,於器件層12上形成絕緣層13。如上所述,絕緣層13中可包含遮蓋器件層12之鈍化膜、及覆蓋於鈍化膜上之有機層。有機層使用感光性聚醯亞胺等,對該有機層轉印用以形成第1貫通電極14之開口圖案。開口圖案之開口徑可為例如10μm左右。
繼而,例如藉由將有機層作為遮罩對絕緣層13之鈍化膜及器件
層12之層間絕緣膜上層部分進行蝕刻,而使器件層12之上層配線121露出。鈍化膜及層間絕緣膜之蝕刻可使用反應性離子蝕刻(RIE)等。繼而,於包含貫通孔內部之絕緣層13上整體,依次積層使用鈦(Ti)之障壁金屬層及使用銅(Cu)之籽晶金屬層。障壁金屬層與籽晶金屬層之成膜可分別使用濺鍍法或化學氣相沈積(CVD)法等。籽晶金屬層之膜厚可為例如500nm左右。
繼而,於籽晶金屬層上使用例如PEP(Photo Engraving Process,光刻工藝)技術形成用以形成貫通電極143之遮罩。於該遮罩之與形成於絕緣層13之貫通孔對應之位置形成開口。繼而,於自遮罩之開口露出之籽晶金屬層上形成使用鎳(Ni)之貫通電極143。貫通電極143之形成可使用保形鍍敷等。
繼而,於去除遮罩之後,去除露出之籽晶金屬層與障壁金屬層。由此,將貫通電極143下之籽晶金屬層142與障壁金屬層141圖案化。再者,籽晶金屬層142與障壁金屬層141之圖案化可使用濕式蝕刻。
繼而,於已形成之貫通電極143之上表面上形成使用金(Au)之材料膜144。材料膜144之形成可使用掀離法等形成方法。其結果,如圖2所示,於半導體基板11之元件形成面(第1面)側形成將器件層12之上層配線121引出至絕緣層13上之第1貫通電極14。
繼而,藉由在形成有第1貫通電極14之絕緣層13上塗佈接著劑,並將支持基板16貼合於該接著劑上,而如圖3所示,將支持基板16接著於半導體裝置1之元件形成面側。繼而,藉由在將支持基板16固定於載台之狀態下自與元件形成面(第1面)為相反側之第2面將半導體基板11進行研磨,而將半導體基板11之厚度薄化為例如30±5μm左右。
繼而,如圖4所示,於半導體基板11之第2面上依次成膜氧化矽膜171A與氮化矽膜172A。氧化矽膜171A可為藉由氧氣環境中之熱處理
而形成之熱氧化膜或藉由CVD法而形成之成長膜等各種氧化膜。又,氮化矽膜172A可為藉由CVD法而形成之成長膜等各種氮化膜。
繼而,於氮化矽膜172A上塗佈感光性光阻劑180M,對該光阻劑180M轉印用以形成第2貫通電極18之開口圖案。再者,開口圖案之開口徑可為例如10μm左右。繼而,藉由將轉印有開口圖案之光阻劑180M作為遮罩自第2面側雕刻半導體基板11,而形成到達至器件層12之貫通孔(TSV)180H。半導體基板11之雕刻可使用能獲得高縱橫比之各向異性乾式蝕刻等。
此時,若於作為刻蝕對象之半導體基板11上存在例如氧化矽膜171A等對半導體基板11之蝕刻選擇比相對較大之膜,則會於形成於該膜之開口附近,較該膜更多地磨削半導體基板11。例如,若如圖5所示般於半導體基板11上存在氧化矽膜171B,則可於貫通孔(TSV)180H之開口端附近半導體基板11被旁側蝕刻,而成為半導體基板11之開口端附近被底切之形狀。其結果,貫通孔(TSV)180H之開口端附近之形狀可成為於該部分氧化矽膜171B較半導體基板11突出之所謂之懸突(overhang)之形狀。
因此,於實施形態中,如圖6所示,去除氧化矽膜171B中之較半導體基板11懸突之部分。去除氧化矽膜171B中之懸突之部分可使用稀氫氟酸等。其結果,於貫通孔(TSV)180H之開口端,可使氧化矽膜171自半導體基板11之開口端之突出後退。再者,後退後之氧化矽膜171能以於以後之氧化矽膜173之形成中不會產生影響之程度自半導體基板11之開口端突出。即,形成於氧化矽膜171中之貫通孔180H之開口徑可與形成於半導體基板11中之貫通孔180H之開口徑實質上相同或者較該開口徑大。又,氧化矽膜171A上之氮化矽膜172A之電漿耐性較氧化矽膜171A低,而難以成為懸突之形狀,因此可省略使貫通孔(TSV)180H之開口端附近之氮化矽膜172後退之步驟。
繼而,如圖7所示,於包含貫通孔(TSV)180H之內部之半導體基板11之第2面上整體成膜氧化矽膜173B。氧化矽膜173B之成膜可使用CVD法等。如上所述,於成膜氧化矽膜173B時,已減少或消除於貫通孔(TSV)180H之開口端氧化矽膜171自半導體基板11突出之懸突,因此能夠於貫通孔(TSV)180H之內側面穩定地形成氧化矽膜173。
繼而,藉由對已成膜之氧化矽膜173B進行蝕刻,而去除形成於貫通孔(TSV)180H之底部之氧化矽膜173B。該蝕刻進行至器件層12之絕緣膜(可包含層間絕緣膜;有時將其稱為第3絕緣膜)被去除而露出下層配線122為止。其結果,如圖8所示,於半導體基板11之第2面上形成具有氧化矽膜171、氮化矽膜172及氧化矽膜173之3層絕緣層17,貫通孔(TSV)180H之內側面被氧化矽膜173覆蓋,並且於貫通孔(TSV)180H之底部露出器件層12之下層配線122。再者,氧化矽膜173B之蝕刻可使用各向異性乾式蝕刻等。
繼而,與障壁金屬層141A及籽晶金屬層142A之形成同樣地,藉由在包含貫通孔內部之絕緣層17上整體依次積層使用鈦(Ti)之障壁金屬層181A及使用銅(Cu)之籽晶金屬層182A,而獲得圖9所示之剖面構造。障壁金屬層181A及籽晶金屬層182A有時被簡稱為金屬層。籽晶金屬層182A之膜厚可較籽晶金屬層142A厚。於該步驟中,因已減少或消除於貫通孔(TSV)180H之開口端氧化矽膜171自半導體基板11突出之懸突,因此能夠於貫通孔(TSV)180H之內側面穩定地形成障壁金屬層141A及籽晶金屬層142A。
繼而,於籽晶金屬層182A上,使用例如PEP技術,形成用以形成貫通電極183之遮罩183M。於該遮罩183M之與形成於半導體基板11中之貫通孔(TSV)180H對應之位置形成開口。繼而,如圖10所示,於自遮罩183M之開口露出之籽晶金屬層182A上形成鎳(Ni)之貫通電極183。貫通電極183之形成可使用保形鍍敷等。
繼而,於去除遮罩183M之後,去除露出之籽晶金屬層182A及障壁金屬層181A。籽晶金屬層182A與障壁金屬層181A之去除可使用濕式蝕刻。此時,使用例如未被蝕刻而殘留之籽晶金屬層182與障壁金屬層181中之至少一者與絕緣層17中之氧化矽膜171及氮化矽膜172之至少一者重疊之蝕刻條件即可。
繼而,於自絕緣層17突出之貫通電極183之上表面上附著接合材19。接合材19之形成可使用電解鍍敷法或無電解鍍敷法等。經過以上步驟,於半導體基板11之第2面側形成將器件層12之下層配線122引出至絕緣層17上之第2貫通電極18,而製造具備圖1所示之剖面構造之半導體裝置1。
如上所述,根據實施形態,能夠於形成防止半導體基板11與第2貫通電極18短路之絕緣層17時,減少或者消除於貫通孔(TSV)180H之開口端氧化矽膜171自半導體基板11突出之懸突。由此,能夠於貫通孔(TSV)180H之內側面,穩定地形成氧化矽膜173、障壁金屬層141及籽晶金屬層142。即,能夠將絕緣體或金屬等穩定地埋設於貫通孔(TSV)180H內。
再者,於以上之說明中,作為絕緣層17,例示了氧化矽膜171、氮化矽膜172與氧化矽膜173之積層膜,但並不限定於該等材料及層構造。即,於絕緣層17中之氧化矽膜171及氮化矽膜172之至少一者使用相對於半導體基板11具有相對較大之蝕刻選擇比之絕緣材料之情形時,可應用本實施形態。例如,於代替絕緣層17中之氧化矽膜171與氮化矽膜172,而使用氧化矽膜、氮化矽膜或氮氧化矽(SiON)膜之單層膜或者該等膜中之2層以上之積層膜等之情形時,亦可應用本實施形態。
已對本發明之實施形態進行了說明,但該實施形態係作為示例而提出,並非意圖限定發明之範圍。該新穎之實施形態能以其他各種
方式實施,並且能夠於不脫離發明之主旨之範圍內進行各種省略、置換、變更。該實施形態或其變化包含於發明之範圍或主旨內,並且包含於申請專利範圍所記載之發明及其均等之範圍內。
1‧‧‧半導體裝置
11‧‧‧半導體基板
12‧‧‧器件層
13‧‧‧絕緣層
14‧‧‧第2貫通電極
17‧‧‧絕緣層
18‧‧‧第1貫通電極
19‧‧‧接合材
120‧‧‧配線層
121‧‧‧上層配線
122‧‧‧下層配線
141‧‧‧障壁金屬層
142‧‧‧籽晶金屬層
143‧‧‧貫通電極
144‧‧‧材料膜
171‧‧‧氧化矽膜
172‧‧‧氮化矽膜
173‧‧‧氧化矽膜
181‧‧‧障壁金屬層
182‧‧‧籽晶金屬層
183‧‧‧貫通電極
Claims (6)
- 一種半導體裝置之製造方法,其特徵在於包含如下步驟:於形成有於第1面包含配線之器件層、覆蓋上述器件層之絕緣層及貫通上述絕緣層之第1貫通電極之半導體基板之與上述第1面為相反側之第2面上,形成第1絕緣膜;藉由對形成有上述第1絕緣膜之上述半導體基板自上述第2面側進行各向異性乾式蝕刻,而形成使上述器件層露出之貫通孔;去除上述貫通孔之開口端部分之上述第1絕緣膜;於上述第1絕緣膜上、上述貫通孔之內側面及自上述貫通孔露出之上述器件層之表面形成第2絕緣膜;藉由去除形成於自上述貫通孔露出之上述器件層之表面之上述第2絕緣膜及上述器件層中之第3絕緣膜,而使上述器件層之上述配線露出;及形成第2貫通電極,該第2貫通電極自上述第2絕緣膜上經由上述貫通孔內與上述器件層中之上述配線電連接。
- 如請求項1之半導體裝置之製造方法,其中上述第1絕緣膜包含位於上述半導體基板之上述第2面上之氧化矽膜。
- 如請求項1之半導體裝置之製造方法,其中上述第2貫通電極包含:第1金屬層,其自上述第2絕緣膜上經由上述貫通孔內側面與上述器件層中之上述配線接觸;第2金屬層,其形成於上述第1金屬層上;及第3金屬層,其形成於上述第2金屬層上。
- 如請求項3之半導體裝置之製造方法,其進而包含如下步驟:以 於上述半導體基板之厚度方向上殘留與上述第1絕緣膜重疊之區域之方式將上述1金屬層與上述第2金屬層圖案化。
- 如請求項1之半導體裝置之製造方法,其進而包含如下步驟:於形成上述第1絕緣膜之前將上述半導體基板形成為50微米以下。
- 一種半導體裝置,其特徵在於具備:半導體基板,其設置有自第1面貫通至與上述第1面為相反側之第2面之貫通孔;器件層,其位於上述半導體基板之上述第1面,且包含配線;絕緣層,其覆蓋上述器件層;第1貫通電極,其貫通上述絕緣層;第1絕緣膜,其位於上述半導體基板之上述第2面上,設置有與上述半導體基板之上述貫通孔之開口徑實質上相同或較大徑之開口;第2絕緣膜,其位於自上述第1絕緣膜上至上述半導體基板之上述貫通孔之內側面;及第2貫通電極,其自上述第2絕緣膜上經由上述半導體基板之上述貫通孔內與上述器件層中之上述配線電連接。
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- 2015-11-25 TW TW104139211A patent/TWI579968B/zh active
- 2015-11-27 CN CN201510848888.9A patent/CN106206416B/zh active Active
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2016
- 2016-03-04 US US15/061,659 patent/US10204862B2/en active Active
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US20090108464A1 (en) * | 2007-10-29 | 2009-04-30 | Elpida Memory, Inc. | Semiconductor device and method for manufacturing the same |
TW201508889A (zh) * | 2013-08-21 | 2015-03-01 | Toshiba Kk | 半導體裝置及半導體裝置之製造方法 |
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CN110880487A (zh) * | 2018-09-05 | 2020-03-13 | 东芝存储器株式会社 | 半导体装置及其制造方法 |
TWI690023B (zh) * | 2018-09-05 | 2020-04-01 | 日商東芝記憶體股份有限公司 | 半導體裝置及其製造方法 |
US11043419B2 (en) | 2018-09-05 | 2021-06-22 | Toshiba Memory Corporation | Semiconductor device and manufacturing method thereof |
CN110880487B (zh) * | 2018-09-05 | 2023-10-03 | 铠侠股份有限公司 | 半导体装置及其制造方法 |
Also Published As
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TW201642391A (zh) | 2016-12-01 |
JP6479578B2 (ja) | 2019-03-06 |
US20160351503A1 (en) | 2016-12-01 |
JP2016225474A (ja) | 2016-12-28 |
US10204862B2 (en) | 2019-02-12 |
CN106206416A (zh) | 2016-12-07 |
CN106206416B (zh) | 2019-05-10 |
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