CN105895614B - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

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CN105895614B
CN105895614B CN201610090985.0A CN201610090985A CN105895614B CN 105895614 B CN105895614 B CN 105895614B CN 201610090985 A CN201610090985 A CN 201610090985A CN 105895614 B CN105895614 B CN 105895614B
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pad electrode
wiring
pad
mounting portion
film
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CN105895614A (zh
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山田健太郎
都丸成树
福岛武利
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Renesas Electronics Corp
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Renesas Electronics Corp
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Abstract

本发明涉及一种半导体装置及其制造方法，能够提高半导体装置的可靠性。半导体装置(1)具有：多个配线层(5、7、9)，形成于半导体基板(1P)上；焊盘(9a)，形成于多个配线层(5、7、9)的最上层；表面保护膜(10)，由无机绝缘膜构成且在焊盘上具有开口；再设配线(12)，形成于表面保护膜(10)上；焊盘电极(13)，形成于再设配线(12)上；以及与焊盘电极(13)连接的导线(20)。并且，再设配线(12)由搭载有焊盘电极(13)的焊盘电极搭载部、与焊盘连接的连接部以及将焊盘电极搭载部与连接部连结的延长配线部构成，在俯视时，焊盘电极搭载部(13)是长方形。

Description

半导体装置及其制造方法
技术领域
本发明涉及一种半导体装置及其制造方法，特别涉及有效地应用于在形成于半导体基板的主面上的多个配线层的上部具有由金属膜构成的再设配线的半导体装置及其制造方法的技术。
背景技术
在半导体装置中，例如在形成有CMIS(Complementary Metal InsulatorSemiconductor，互补式金属绝缘体半导体)晶体管等半导体元件的半导体基板的上部形成有多层由例如以Cu(铜)或者Al(铝)作为主成分的金属膜构成的配线，在多层配线中的最上层的配线的一部分形成有接合焊盘(焊盘)。并且，在接合焊盘连接有接合导线等。
在日本特开2001-210668号公报(专利文献1)中，公开了在半导体芯片2的表面排列有多个长方形的焊盘2a的半导体装置。长方形的焊盘2a分别相对于排列方向而在横向上延伸，在焊盘2a连接有导线7。
在日本特开平6-333974号公报(专利文献2)的摘要中，公开了将沿着集成电路的边缘设置的接合焊盘形成为在导线接合时的超声波振动方向上具有长边的长方形形状。
现有技术文献
专利文献
专利文献1：日本特开2001-210668号公报
专利文献2：日本特开平6-333974号公报
发明内容
本申请发明人研究的具有再设配线的半导体装置具有半导体芯片、连接于半导体芯片的导线以及对半导体芯片以及导线进行密封的密封体。半导体芯片具有半导体元件、与半导体元件电连接的配线以及电阻显著地低于与半导体元件连接的配线的再设配线，密封体具有多个外部端子。并且，多个外部端子通过导线而与半导体芯片的再设配线电连接。
本申请发明人在研究半导体芯片(芯片尺寸)的小型化的阶段，认识到导线从半导体芯片剥离这样的课题。即，明确了半导体装置的可靠性降低的情况。
因此，寻求在具有再设配线的半导体装置中提高半导体装置的可靠性的技术。
其他课题和新的特征将根据本说明书的叙述以及附图而变得明确。
作为一种实施方式的半导体装置具有：多个配线层，形成于半导体基板上；焊盘，形成于多个配线层的最上层；表面保护膜，由无机绝缘膜构成且在焊盘上具有开口；再设配线，形成于表面保护膜上；焊盘电极，形成于再设配线上；以及与焊盘电极连接的导向。并且，再设配线由搭载有焊盘电极的焊盘电极搭载部、与焊盘连接的连接部以及将焊盘电极搭载部与连接部连结的延长配线部构成，在俯视时，焊盘电极搭载部是长方形。
根据一种实施方式，能够提高具有再设配线的半导体装置的可靠性。
附图说明
图1是形成有作为本发明的实施方式的半导体装置的半导体芯片的整体俯视图。
图2是放大地示出图1的一部分的俯视图。
图3是沿着图2的A-A线的剖面图。
图4是本实施方式的半导体装置的制造工序的工艺流程图。
图5是本实施方式的半导体装置的制造工序中的剖面图。
图6是接着图5的半导体装置的制造工序中的剖面图。
图7是接着图6的半导体装置的制造工序中的剖面图。
图8是接着图7的半导体装置的制造工序中的剖面图。
图9是接着图8的半导体装置的制造工序中的剖面图。
图10是本实施方式的半导体装置的制造工序中的俯视图。
图11是接着图9的半导体装置的制造工序中的剖面图。
图12是作为变形例的半导体装置的主要部分俯视图。
具体实施方式
在以下的实施方式中，虽然在有便利上的需要时分割成多个部分或者实施方式来进行说明，但除了在特别地明确说明的情况下，它们并非彼此无关，而是存在着其中一方是另一方的一部分或者全部的变形例、应用例、详细说明、补充说明等关系。另外，在以下的实施方式中，在提及要素的数量等(包括个数、数值、量、范围等)的情况下，除了在特别地明确说明的情况以及从原理上明确地限定于特定的数量的情况等之下，并非限定于该特定的数量，也可以是特定的数量以上或以下。
进而，在以下的实施方式中，关于其结构要素(也包括要素步骤等)，除了在特别地明确说明的情况以及从原理上显然是必需的情况等之下，不一定是必需的。同样地，在以下的实施方式中，在提及结构要素等的形状、位置关系等时，除了在特别地明确说明的情况以及从原理上显然并非这样的情况下等，设为包括实质上与该形状等近似或者类似的形状等。这对于上述数量等(包括个数、数值、量、范围等)来说也一样。
以下，根据附图，详细说明本发明的实施方式。此外，在用于说明实施方式的全部附图中，对具有相同的功能的部件附加相同或者相关联的标号，并省略其重复的说明。另外，在存在多个类似的部件(部位)的情况下，有时对总称的标号追加记号而表示单独或者特定的部位。另外，在以下的实施方式中，除了特别需要的时候以外，原则上不重复对相同或者同样的部分的说明。
另外，在实施方式所使用的附图中，即使是剖面图，为了容易观察附图，也有时省略剖面线。另外，即使是俯视图，为了容易观察附图，也有时附加剖面线。
另外，在剖面图以及俯视图中，各部位的大小并非对应于实际器件，为了容易理解附图，有时相对放大地显示特定的部位。另外，在俯视图与剖面图对应的情况下，也有时改变各部位的大小而进行显示。
(实施方式)
首先，说明本申请发明人研究的具有再设配线的半导体装置。
本申请发明人研究的半导体装置具有半导体芯片、与半导体芯片连接的导线以及对半导体芯片和导线进行密封的密封体。在半导体芯片形成有多个半导体元件、由将多个半导体元件电连接的多层配线层构成的配线、以及与配线电连接并且以电阻显著低于配线的Cu作为主成分的再设配线。进而，再设配线与在多层配线层的最上层的配线层形成的作为配线的一部分的焊盘连接。在最上层的配线层形成的配线与再设配线由覆盖最上层的配线层的表面保护膜电分离，但经由被设置成使焊盘露出的表面保护膜的开口，再设配线与配线的焊盘电连接。在再设配线上，为了提高与导线的连接可靠性，形成有包含镀Au层的焊盘电极。在俯视时，再设配线具有用于搭载焊盘电极的焊盘电极搭载部、从焊盘电极搭载部延伸的延长配线部以及与作为配线的一部分的焊盘连接的连接部，焊盘电极搭载部是正方形。
另外，在密封体形成有多个外部端子(外引线或者焊球等)，外部端子与密封体内的内部端子(内引线或者设置于封装基板的导体层)连接。并且，在导线接合工序中，导线的一端与设置在再设配线上的焊盘电极连接，导线的另一端与密封体的内部端子连接。在导线接合工序中，在导线前端形成球状的焊球，对导线(即，焊球)施加超声波振动，使焊球与焊盘电极磨擦并且连接。
焊盘电极覆盖再设配线的焊盘电极搭载部，延伸至再设配线的侧壁。在俯视时，焊盘电极也为正方形，其一边形成为比焊球直径稍大的尺寸，但将焊盘电极与焊盘电极搭载部设为尽可能小到导线的连接部不从焊盘电极突出的程度。这是由于，在半导体芯片内，存在大量的焊盘电极，所以缩小焊盘电极对于半导体芯片的小型化有效果。
另外，在现有结构中，表面保护膜是氮化硅膜等无机绝缘膜与聚酰亚胺膜等有机绝缘膜的层叠结构，在无机绝缘膜与再设配线之间介设有有机绝缘膜。然而，如果存在有机绝缘膜，则需要从表面保护膜的焊盘开口隔开预定的距离地配置焊盘电极，在实现半导体芯片的小型化方面成为障碍。即，这是由于，有机绝缘膜的膜厚比无机绝缘膜的膜厚更厚，焊盘开口的侧壁为锥形形状，所以在俯视时的焊盘开口尺寸扩大。因此，在本申请发明人研究的半导体装置中，将表面保护膜仅设为无机绝缘膜。
然而，在由无机绝缘膜构成的表面保护膜上形成再设配线并且对再设配线上的焊盘电极实施导线接合之后，产生了焊盘电极下的再设配线从表面保护膜剥离这样的问题。
关于该问题，本申请发明人进行如下推测。在导线接合工序中，实施超声波球焊。即，对导线前端的焊球施加与半导体芯片的表面垂直的方向的按压力(称为垂直应力)以及与表面平行的方向的按压力(称为水平应力)。这些垂直应力以及水平应力经由再设配线传递到表面保护膜与再设配线的界面，所以对导线连接部的表面保护膜的表面造成损伤，再设配线与表面保护膜的粘接力降低。另外，在导线接合工序中，在完成对焊盘电极进行的导线连接之后，使支撑导线的毛细管朝向内部端子移动，但此时，导线在毛细管的移动方向上受到拉伸应力。由于该拉伸应力，以导线连接部的下方为起点，再设配线与导线一体地从表面保护膜剥离。
另外，还确认了在导线连接部从焊盘电极的中心偏移的情况下，特别是在向与延长配线部反方向偏移并且偏移到直至焊盘电极的端部的位置的情况下，剥离的频度变高。在焊盘电极的端部，再设配线与表面保护膜的粘接力降低，该部分在卷起的方向上受到拉伸应力，所以推测为再设配线(以及焊盘电极)从表面保护膜剥离。
本实施方式是为了防止上述问题而完成的，上述的本申请发明人所研究的半导体装置的结构与本实施方式的半导体装置的结构相同，也能够兼用其说明，所以在有些地方也省略说明。在改进后的本实施方式中，主要是焊盘电极的形状以及再设配线的焊盘电极搭载部的形状不同。
本实施方式以及以下的实施方式的半导体装置(半导体集成电路装置)例如构成为包括具有多个半导体元件、在多个半导体元件的上部形成的多层的配线(多层配线)以及与多层中的最上层的配线连接的多个再设配线的半导体芯片，通过上述多层配线以及多个再设配线来连接多个半导体元件。
<关于半导体装置>
图1是示出半导体芯片1的一例的整体俯视图，图2是图1的以虚线X包围的区域的放大俯视图，图3是沿着图2的A-A线的剖面图。
图1示出了在具有四边1a、1b、1c以及1d的正方形(或者长方形)的半导体芯片1的器件面上形成的再设配线12、12d、12G以及12S的布局的一例。与半导体芯片1的多层配线(图3所示的第1层Al配线5、第2层Al配线7、第3层Al配线9)相比，再设配线12、12d、12G以及12S的膜厚以及配线宽度都较大，所以与多层配线相比，再设配线12、12d、12G以及12S的阻抗非常低。再设配线12、12d、12G以及12S例如被用作信号输入输出用的再设配线12、电源(Vcc、GND)供给用的再设配线12d和12G以及内部电路之间的连接用的再设配线12S。
如图1所示，在半导体芯片1的周边部配置有构成半导体装置的外部连接端子的多个再设配线12，在再设配线12各自的一端形成有焊盘电极13，另一端如图2、3所示地与形成于最上层的配线的焊盘9a连接。焊盘电极13没有特别限定，沿着半导体芯片1的各边1a、1b、1c以及1d配置成一列。此外，焊盘电极13当然也可以沿着半导体芯片1的各边1a、1b、1c以及1d交错状地配置或者配置成3列以上的列。如图1所示，存在焊盘9a相对于焊盘电极13位于半导体芯片1的内侧的情况、以及焊盘9a相对于焊盘电极13位于半导体芯片1的外侧(焊盘电极13接近的边1a、1b、1c以及1d这一侧)的情况。
另外，图1所示的再设配线12d以及12G是电源(Vcc、GND)供给用的再设配线。在再设配线12d以及12G的一端形成有焊盘电极13，另一端与形成于半导体芯片1内的电源配线的焊盘9a连接，所以能够将从半导体芯片1的外部供给的电源(Vcc、GND)电压以低阻抗供给到半导体芯片1内的多个电源配线。
另外，图1所示的再设配线12S被用作将形成于半导体芯片1的电路之间或者元件之间连接的配线。因此，在再设配线12S未形成焊盘电极13。再设配线12S的两端与形成于最上层的配线的焊盘9a连接。
在再设配线12、12d、12G以及12S上配置的焊盘电极13是具有短边与长边的长方形，被配置成长边的方向与后述的导线接合工序中的超声波的施加方向(在图1中，记为US方向)一致。如图1所示，沿着四边1a、1b、1c以及1d配置的所有焊盘电极13的长边都与US方向一致。
图2示出信号输入输出用的再设配线12的放大俯视图。再设配线12由焊盘电极搭载部121、延长配线部122以及连接部123构成。焊盘电极搭载部121是搭载长方形的焊盘电极13的部分，具有由长边121x与短边121y构成的长方形。焊盘电极搭载部121是大致长方形即可，长边121x与短边121y的交叉部也可以实施倒角或者圆角。连接部123是再设配线12与作为配线9的一部分的焊盘9a连接的部分，延长配线部122连结焊盘电极搭载部121与连接部123，具有配线宽度W1。延长配线部122从短边121y向与短边121y正交的方向延伸，延长配线部122的配线宽度W1比短边121y的长度窄(小)。
连接部123通过由预定的宽度W2构成的正方形来构成。在图2中，延长配线部122的配线宽度W1小于连接部123的宽度W2，但也可以相等。连接部123的宽度W2小于焊盘电极搭载部121的短边121y的长度。
焊盘电极13的平面形状与焊盘电极搭载部121的形状相似，具有焊盘电极搭载部121的扩大图案。焊盘电极13覆盖焊盘电极搭载部121的上表面(表面)整体，连续地延伸到侧面，还覆盖侧面的一部分。在连接部123，与再设配线12连接的配线9朝向半导体芯片1的内部延伸。
如图3所示，在例如由p型的单晶硅构成的半导体基板1P形成有p型阱2以及元件分离槽3，在元件分离槽3的内部埋入有例如由氧化硅膜构成的元件分离绝缘膜3a。
在上述P型阱2内形成有n沟道型MIS晶体管(Qn)。n沟道型MIS晶体管(Qn)形成在由元件分离槽3规定的活性区域中，具有在P型阱2内形成的源极区域ns和漏极区域nd以及在P型阱2上隔着栅极绝缘膜ni而形成的栅极电极ng。另外，虽然未图示，但在半导体基板1P形成有n型阱，在n型阱内形成有p沟道型MIS晶体管，具有源极区域和漏极区域以及在n型阱上隔着栅极绝缘膜而形成的栅极电极。
在上述n沟道型MIS晶体管(Qn)以及P沟道型MIS晶体管的上部形成有将半导体元件(例如，n沟道型MIS晶体管Qn或者P沟道型MIS晶体管)之间连接的由金属膜构成的配线。将半导体元件间连接的配线通常具有3层～10层左右的多层配线结构，在图3中，作为多层配线的一例，示出了由以Al合金为主体的金属膜构成的3层配线层(第1层Al配线5、第2层Al配线7、第3层Al配线9)。“配线层”在统一表示以各配线层形成的多个配线的情况下使用。关于配线层的膜厚，第2层配线层比第1层配线层厚，第3层配线层比第2层配线层厚。
在n沟道型MIS晶体管(Qn)与第1层Al配线5之间、第1层Al配线5与第2层Al配线7之间以及第2层Al配线7与第3层Al配线9之间，分别形成有由氧化硅膜等构成的层间绝缘膜4、6、8以及将3层配线之间电连接的插头p1、p2、p3。
上述层间绝缘膜4例如以覆盖半导体元件的方式形成于半导体基板上1P上，第1层Al配线5形成于该层间绝缘膜4上。第1层Al配线5例如经由形成于层间绝缘膜4的插头p1而与作为半导体元件的n沟道型MIS晶体管(Qn)的源极区域ns、漏极区域nd电连接。栅极电极ng与第1层Al配线5的连接未图示。
第2层Al配线7例如经由形成于层间绝缘膜6的插头p2而与第1层Al配线5电连接。第3层Al配线9例如经由形成于层间绝缘膜8的插头p3而与第2层Al配线7电连接。插头p1、p2、p3由金属膜例如W(钨)膜构成。
此外，在利用化学机械研磨法(CMP法)通过以Cu为主体的金属膜来形成多层配线(3层配线)的情况下，当然也可以通过一体地形成配线与插头的双镶嵌(Dual damascene)法来形成。另外，层间绝缘膜4、6、8由氧化硅膜(SiO2)构成，但当然也可以由包含碳的氧化硅膜(SiOC膜)、包含氮和碳的氧化硅膜(SiCON膜)、包含氟的氧化硅膜(SiOF膜)的单层膜或者层叠膜构成。另外，也可以由以Cu为主体的金属膜来形成多层配线的第1层与第2层，由Al配线来形成多层配线的最上层的配线层即第3层。
作为最终钝化膜，在多层配线的最上层的配线层即上述第3层Al配线9的上部形成有例如由氧化硅膜或者氮化硅膜等单层膜或者在氧化硅膜上设置氮化硅膜而成的层叠膜构成的表面保护膜(保护膜、绝缘膜)10。并且，在形成于该表面保护膜10的焊盘开口(开口)10a的底部露出的最上层的配线层即第3层Al配线9构成作为Al焊盘的焊盘(电极焊盘、第1电极焊盘)9a。作为表面保护膜10，使用无机绝缘膜是很重要的。在使用有机绝缘膜作为表面保护膜10的情况下，焊盘开口10a变大，不适合于微型化。通过将表面保护膜10设为无机绝缘膜，能够实现微型化。
不限于焊盘9a，上述第3层Al配线9例如构成一体地形成于焊盘9a的配线、与焊盘9a未连接的配线等。与焊盘9a未连接的配线被用作将半导体元件之间或者电路之间电连接而构成半导体集成电路的配线。
在上述表面保护膜10的上方形成有穿过表面保护膜10的焊盘开口10a而与焊盘9a电连接的再设配线12。再设配线12以完全掩埋焊盘开口10a的方式形成于焊盘开口10a的内部，进而，在表面保护膜10的上方延伸。
在焊盘9a与再设配线12之间介设有基底金属膜11。基底金属膜11与焊盘9a接触并电连接，在表面保护膜10的焊盘开口10a沿表面保护膜10的侧面(侧壁)以及上表面形成。基底金属膜11具有上表面与下表面，上表面与再设配线12相接，下表面与焊盘9a以及表面保护膜10相接。基底金属膜11由下层的铬膜与上层的铜种子膜的层叠膜构成。
另外，再设配线12具有上表面、下表面以及侧面，再设配线12的下表面与基底金属膜11的上表面相接。再设配线12由以铜(Cu)作为主成分的镀铜膜12a与镀铜膜12a上的镀镍膜12b的层叠结构构成。另外，也有时包括基底金属膜11在内地称为再设配线12。另外，再设配线12也可以仅由镀铜膜12a构成。因此，再设配线12的下表面是指镀铜膜的下表面或者基底金属膜11的下表面，上表面是指镀镍膜的上表面或者镀铜膜的上表面。另外，再设配线12的侧面(侧壁)是指镀铜膜12a与镀镍膜12b的层叠结构的侧面或者基底金属膜11、镀铜膜12a以及镀镍膜12b的层叠结构的侧面。基底金属膜11以及镀铜膜的膜厚分别是250nm以及6μm，镀镍膜12b是3μm左右。另外，第3层Al配线9的膜厚是400nm～600nm，因此，再设配线12是具有第3层Al配线9的10倍以上的膜厚的低电阻的配线，换句话说，是具有形成有焊盘9a的配线9的10倍以上的膜厚的低电阻的配线。即，再设配线12的膜厚大于形成有焊盘9a的配线9的膜厚。优选的是，再设配线12的膜厚是形成有焊盘9a的配线9的膜厚的5倍以上，更优选的是10倍以上。
基底金属膜11中的铜种子膜是用于通过电镀法形成镀铜膜12a的膜，铬膜是用于防止镀铜膜12a中包含的铜扩散到表面保护膜10中的膜。镀镍膜12b是为了防止镀铜膜12a的表面(上表面)的氧化而设置的。
焊盘电极13形成为与再设配线12的上表面以及侧面相接并且完全覆盖再设配线12的焊盘电极搭载部121。焊盘电极13由镍薄膜13a和镍薄膜13a上的金薄膜13b的层叠结构构成。镍薄膜13a是为了提高再设配线12与焊盘电极13的粘接性而设置的，其膜厚是0.5μm左右，金薄膜13b是为了提高后述的导线20与焊盘电极13的粘接性而设置的，其膜厚是2μm左右。
<半导体装置的制造方法>
接下来，说明本实施方式的半导体装置的制造方法，以作为本实施方式的特征的再设配线的制造方法为中心进行说明。再设配线的制造方法对应于图3所示的剖面。
图4是示出本实施方式的半导体装置的制造工序的一部分的工艺流程图。图5～图9以及图11是本实施方式的半导体装置的制造工序中的剖面图。图10是本实施方式的半导体装置的制造工序中的俯视图。
图5是说明图4所示的工艺流程图的“准备半导体基板”工序(步骤S1)的附图，示出了准备形成有多个配线层与焊盘9a的半导体基板1P的工序。在半导体基板1P形成n沟道型MIS晶体管(Qn)之后，形成由多个配线层构成的配线。具体地说，如在图3中说明地，形成有3层配线层(第1层Al配线5、第2层Al配线7、第3层Al配线9)。然后，在第3层Al配线9的上部形成有表面保护膜10，表面保护膜10具有焊盘开口10a，从最上层的配线层即第3层Al配线9的焊盘开口10a露出的部分成为焊盘9a。图5所示的剖面结构如图3中说明所述。
图6是说明图4所示的工艺流程图的“形成基底金属膜”工序(步骤S2)、“光刻1(再设配线)”工序(步骤S3)以及“镀铜、镀镍”工序(步骤S4)的附图。首先，在“形成基底金属膜”工序(步骤S2)中，在表面保护膜10上通过溅镀法形成(沉积)经由焊盘开口10a而与焊盘9a电连接的基底金属膜11。构成基底金属膜11的铬膜的膜厚设为50nm，铜种子膜设为200nm。接下来，在“光刻1(再设配线)”工序(步骤S3)中，在基底金属膜11上形成具有在形成再设配线12的区域开口且被覆除此以外的区域的图案的抗蚀剂膜PR1。当然，焊盘9a位于抗蚀剂膜PR1的开口部。进而，在“镀铜、镀镍”工序(步骤S4)中，通过将基底金属膜11设为种子电极的电镀法，在抗蚀剂膜PR1的开口部依次形成镀铜膜12a以及镀镍膜12b。
图7是说明图4所示的工艺流程图的“光刻2(焊盘电极)”工序(步骤S5)的附图。在抗蚀剂膜PR1上形成具有在形成焊盘电极13的区域开口且被覆除此以外的区域的图案的抗蚀剂膜PR2。抗蚀剂膜PR2具有使再设配线12的侧壁露出的图案，所以在步骤S3中覆盖再设配线12的侧壁的抗蚀剂膜PR1被去除一部分。
图8是说明图4所示的工艺流程图的“镀镍、镀金”工序(步骤S6)以及“蚀刻基底金属膜”工序(步骤S7)的附图。在“镀镍、镀金”工序(步骤S6)中，通过电镀法，在抗蚀剂膜PR1以及PR2的开口部依次形成镍薄膜13a以及金薄膜13b。然后，在去除抗蚀剂膜PR1以及PR2之后，去除从再设配线12露出的区域的基底金属膜11，仅在再设配线12的下部选择性地留下基底金属膜11。换言之，从再设配线12露出的区域是指再设配线12的外侧的区域、未形成再设配线12的区域。由此，完成焊盘电极13以及再设配线12。
图9是说明图4所示的工艺流程图的“导线接合”工序(步骤S8)的附图。在“导线接合”工序(步骤S8)中，在焊盘电极13的表面(即，金薄膜13b的表面)通过超声波球焊法来连接导线20。在导线20的前端形成焊球，针对焊球在图9的纸面的横向上施加超声波振动并且在与焊盘电极13的主面垂直的方向上施加按压力，并同时将焊球连接到焊盘电极13。导线20也可以以铜为主成分而包含微量的添加物等。另外，也可以使用通过钯膜等被覆铜线的表面而成的被覆导线。
如图10所示，连接于各焊盘电极13的导线20与供各焊盘电极13并列设置的边1a、1b、1c以及1d交叉并延伸到半导体芯片1的外侧。
图11是说明图4所示的工艺流程图的“树脂密封”工序(步骤S9)的附图。如图11所示，具有多个再设配线12的半导体芯片1搭载于管芯焊盘部25D，并利用导线20而电连接到多根引线25L。例如用热硬化性环氧树脂等密封引线25L的一部分(内引线部)、管芯焊盘部25D、半导体芯片1以及导线20，形成密封体(密封树脂)26。引线25L具有从由密封体26覆盖的内引线部(上述的内部端子)延伸到密封体26外侧的外引线部(上述的外部端子)。这样一来，也有时将用密封体26密封半导体芯片1而成的结构称为半导体装置(半导体集成电路装置)。在本实施方式中，再设配线12以及焊盘电极13直接与密封体26接触，但也可以使聚酰亚胺树脂等介设于再设配线12以及焊盘电极13与密封体26之间。
<半导体装置及其制造方法的特征>
以下，说明本实施方式的半导体装置及其制造方法的主要特征。
将焊盘电极13以及再设配线12的焊盘电极搭载部121设为长方形，通过增大焊盘电极13以及焊盘电极搭载部121，从而在“导线接合”工序中，表面保护膜10受到的应力被缓和，所以能够降低表面保护膜10的表面的损伤，能够防止再设配线12从表面保护膜10剥离。即，能够提高半导体装置的可靠性。
在本实施方式中，当在俯视时焊盘电极搭载部121与焊盘电极13大致相等的情况下，将焊盘电极13以及焊盘电极搭载部121设为长方形是很重要的。另外，在焊盘电极搭载部121比焊盘电极13宽(大)的情况下，不需要将焊盘电极13设为长方形，设为正方形即可。即，也可以仅将焊盘电极搭载部121设为长方形，通过比焊盘电极13更宽(大)的焊盘电极搭载部121来承受作用于焊盘电极13的按压力，从而能够降低每单位面积的按压力，能够防止再设配线12从表面保护膜10剥离。
在本实施方式中，使长方形的焊盘电极搭载部121的长边121x与超声波的施加方向(US方向)一致，但也可以将所有的长方形的焊盘电极搭载部121的长边121x配置在与US方向正交的方向上。另外，也可以使一部分的焊盘电极搭载部121的长边121x与US方向一致，将其他焊盘电极搭载部121的长边121x配置在与US方向正交的方向上。例如，也可以是，形成有沿半导体芯片1的边1a以及1c配置的焊盘电极13的焊盘电极搭载部121使其长边121x与US方向一致，将形成有沿着边1b以及1d配置的焊盘电极13的焊盘电极搭载部121的长边121x配置在与US方向正交的方向上。通过该构成，能够增加沿着边1b以及1d配置的再设配线12的数量。
通过将焊盘电极13以及再设配线12的焊盘电极搭载部121设为长方形，即使导线连接部从焊盘电极13的中心稍微偏移，导线连接部也不会偏移到直至焊盘电极13的端部的位置。因此，在导线连接部的周围牢固地保持再设配线12与表面保护膜10的粘接力，所以即使导线20受到拉伸应力，也能够防止再设配线12的剥离。
在不使用有机绝缘膜而由无机绝缘膜构成的表面保护膜10上直接形成有再设配线12，所以能够实现半导体装置的小型化。
<变形例>
图12是作为上述实施方式的变形例的半导体装置的主要部分俯视图。
变形例是在上述实施方式的图2中所说明的再设配线12的长边以及短边设置有翅片部的例子。
如图12所示，在再设配线12的构成长方形的两个长边121x以及两个短边121y中的连接有延长配线部122的短边121y以外的3边形成有翅片部124。翅片部124从焊盘电极搭载部121的长边121x以及短边121y向焊盘电极搭载部121的外侧突出。翅片部124是再设配线12的一部分，翅片部124的一部分被长方形的焊盘电极13覆盖，但其他部分从焊盘电极13露出。在焊盘电极搭载部121中的连接有延长配线部122以及翅片部124的部分以外，焊盘电极13与上述实施方式同样地覆盖再设配线12的侧面的一部分。
在翅片部124的下方未配置下层的配线9的焊盘电极9a，翅片部124整个区域与表面保护膜10接触。
翅片部124不限定于设置于3边的情况，既可以仅设置于焊盘电极搭载部121的1个长边121x或者1个短边121y，也可以仅设置于1个长边121x与1个短边121y。
根据变形例，通过在焊盘电极搭载部121设置翅片部124，能够增加再设配线12与表面保护膜10的粘接区域。另外，在导线接合时，利用比焊盘电极13宽(大)的焊盘电极搭载部121来承受作用于焊盘电极13的按压力，从而能够降低每单位面积的按压力，能够防止再设配线12从表面保护膜10剥离。
在变形例的情况下，也可以是将焊盘电极搭载部121设为正方形并在该处设置翅片部124的结构。
另外，也可以在长方形的焊盘电极搭载部121设置翅片部124，正方形的焊盘电极13配置在焊盘电极搭载部121的中央部。在这种情况下，焊盘电极13小于焊盘电极搭载部121，未到达再设配线12的侧壁。
以上，根据实施方式具体地说明了由本发明人完成的发明，但本发明不限定于上述实施方式，在不脱离其主旨的范围内当然能够进行各种变更。
标号说明
nd 漏极区域
ng 栅极电极
ns 源极区域
p1、p2、p3 插头
Qn n沟道型MIS晶体管
1 半导体装置(半导体芯片)
2 p型阱
3 元件分离槽
3a 元件分离绝缘膜
4、6、8 层间绝缘膜
5、7、9 配线层(配线、Al配线)
9a 焊盘
10 表面保护膜
10a 焊盘开口
11 基底金属膜
12、12d、12G、12S 再设配线
121 焊盘电极搭载部
122 延长配线部
123 连接部
124 翅片部
12a 镀铜膜
12b 镀镍膜
13 焊盘电极
13a 镍薄膜
13b 金薄膜
20 导线
25D 管芯焊盘部
25L 引线
26 密封体。

Claims (13)

1.一种半导体装置，其特征在于，
具有：半导体基板；
多个配线层，形成于所述半导体基板上；
焊盘，形成于所述多个配线层的最上层；
表面保护膜，由无机绝缘膜构成且在所述焊盘上具有开口；
再设配线，形成于所述表面保护膜上；以及
焊盘电极，是用于连接导线的区域，并且形成于所述再设配线上，
所述再设配线由搭载有所述焊盘电极的焊盘电极搭载部、与所述焊盘连接的连接部以及将所述焊盘电极搭载部与所述连接部连结的延长配线部构成，
在俯视时，所述焊盘电极搭载部是长方形，
所述焊盘电极搭载部具有两个短边和两个长边，
所述延长配线部与所述两个短边中的一个边连接，
所述延长配线部的配线宽度小于所述短边的长度，
在所述两个短边中的另一个边连接有第1翅片部，
所述第1翅片部延伸到所述焊盘电极搭载部的外侧，
所述第1翅片部从所述焊盘电极搭载部的所述短边向所述焊盘电极搭载部的外侧突出。
2.根据权利要求1所述的半导体装置，其特征在于，
所述焊盘电极覆盖所述焊盘电极搭载部的侧面以及整个上表面。
3.根据权利要求1所述的半导体装置，其特征在于，
所述再设配线的膜厚是形成有所述焊盘的最上层配线层的膜厚的5倍以上。
4.根据权利要求3所述的半导体装置，其特征在于，
所述再设配线由铜膜构成。
5.根据权利要求1所述的半导体装置，其特征在于，
所述导线形成于所述焊盘电极上，
所述导线在所述再设配线的上部从所述焊盘电极搭载部朝向所述连接部延伸。
6.根据权利要求1所述的半导体装置，其特征在于，
在所述两个长边中的一个边连接有第2翅片部，
所述第2翅片部延伸到所述焊盘电极搭载部的外侧，
所述第2翅片部从所述焊盘电极搭载部的所述长边向所述焊盘电极搭载部的外侧突出。
7.根据权利要求1所述的半导体装置，其特征在于，
所述表面保护膜由氮化硅膜构成，
所述再设配线与所述氮化硅膜的上表面接触。
8.根据权利要求1所述的半导体装置，其特征在于，
所述焊盘电极由金膜构成，
所述导线形成于所述焊盘电极上且与所述金膜连接。
9.一种半导体装置的制造方法，其特征在于，
包括如下工序：(a)准备具有焊盘以及多个配线层的半导体基板的工序，所述焊盘形成于所述多个配线层的最上层；
(b)形成在所述焊盘上具有开口的由无机绝缘膜构成的表面保护膜的工序；
(c)在所述表面保护膜上形成经由所述开口而与所述焊盘电连接的再设配线的工序；
(d)在所述再设配线上形成焊盘电极的工序；以及
(e)在导线的前端形成焊球，并在对所述焊球施加第1方向的超声波振动的同时将所述焊球连接到所述焊盘电极的工序，
所述再设配线由搭载有所述焊盘电极的焊盘电极搭载部、与所述焊盘连接的连接部以及将所述焊盘电极搭载部与所述连接部连结的延长配线部构成，
所述焊盘电极搭载部是具有长边与短边的长方形，
所述焊盘电极搭载部具有两个短边和两个长边，
所述延长配线部与所述两个短边中的一个边连接，
所述延长配线部的配线宽度小于所述短边的长度，
在所述两个短边中的另一个边连接有第1翅片部，
所述第1翅片部延伸到所述焊盘电极搭载部的外侧，
所述第1翅片部从所述焊盘电极搭载部的所述短边向所述焊盘电极搭载部的外侧突出。
10.根据权利要求9所述的半导体装置的制造方法，其特征在于，
所述第1方向是沿着所述长边的方向。
11.根据权利要求10所述的半导体装置的制造方法，其特征在于，
所述焊盘电极覆盖所述焊盘电极搭载部的表面，并延伸到所述焊盘电极搭载部的侧壁。
12.根据权利要求9所述的半导体装置的制造方法，其特征在于，
所述第1方向是沿着所述短边的方向。
13.根据权利要求9所述的半导体装置的制造方法，其特征在于，
所述焊盘电极搭载部具有从所述长边或者所述短边延伸到所述焊盘电极搭载部的外侧的翅片部，
所述翅片部从所述焊盘电极搭载部的所述长边或者所述短边向所述焊盘电极搭载部的外侧突出。
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