TW202036853A - 半導體記憶裝置及其製造方法 - Google Patents

半導體記憶裝置及其製造方法 Download PDF

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TW202036853A
TW202036853A TW108124051A TW108124051A TW202036853A TW 202036853 A TW202036853 A TW 202036853A TW 108124051 A TW108124051 A TW 108124051A TW 108124051 A TW108124051 A TW 108124051A TW 202036853 A TW202036853 A TW 202036853A
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chip
pad
bonding
semiconductor
bonding pad
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TW108124051A
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TWI712159B (zh
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鈴木和貴
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日商東芝記憶體股份有限公司
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Abstract

實施形態提供一種可削減作為非記憶區域之無效區域之半導體記憶裝置及其製造方法。  一實施形態之半導體記憶裝置具有第1晶片與第2晶片，上述第1晶片具有：複數個電極層，其等於第1方向上積層；半導體膜，其於複數個電極層內於第1方向上延伸；及記憶體膜，其配置於複數個電極層與半導體膜之間；上述第2晶片將半導體基板朝上接合於第1晶片上，且具有：MOS電晶體，其設置於半導體基板之下表面；配線，其設置於MOS電晶體之下方，且電性連接於MOS電晶體；接合墊，其設置於MOS電晶體之下方，且於其上表面進行接合；及導通孔，其以接合墊之上表面為底貫通半導體基板，且朝上方開口。

Description

半導體記憶裝置及其製造方法
本發明之實施形態係關於一種半導體記憶裝置及其製造方法。
於作為半導體記憶裝置之一之三維半導體記憶體中，已知有將記憶胞陣列之陣列晶片與包含驅動記憶胞陣列之電路之電路晶片貼合而成之構造。
於具有上述構造之三維半導體記憶體中，通常將接合墊設置於陣列晶片。因此，必須於陣列晶片中，確保與記憶胞陣列之形成區域分開之接合墊之形成區域。於陣列晶片中，接合墊之形成區域係作為非記憶區域之無效區域。
本發明之實施形態提供一種可削減無效區域之半導體記憶裝置及其製造方法。
一實施形態之半導體記憶裝置具有第1晶片與第2晶片，上述第1晶片具有：複數個電極層，其等於第1方向上積層；半導體膜，其於複數個電極層內於第1方向上延伸；及記憶體膜，其配置於複數個電極層與半導體膜之間；上述第2晶片將半導體基板朝上接合於第1晶片上，且具有：MOS電晶體，其設置於半導體基板之下表面；配線，其設置於MOS電晶體之下方，且電性連接至MOS電晶體；接合墊，其設置於MOS電晶體之下方，且於其上表面進行接合；及導通孔，其以接合墊之上表面為底貫通半導體基板，且朝上方開口。
以下，參照附圖對本發明之實施形態進行說明。本實施形態並不限定本發明。
(第1實施形態)  圖1(a)係第1實施形態之半導體記憶裝置之陣列晶片之概略俯視圖。圖1(b)係第1實施形態之半導體記憶裝置之電路晶片之概略俯視圖。圖2係切取圖1(a)、(b)之陣列晶片及電路晶片之一部分，並將其主要部分之構造放大表示所得之剖視圖。
本實施形態之半導體記憶裝置係將圖1(a)、(b)所示之陣列晶片1(第1晶片)與電路晶片2(第2晶片)貼合，以整體構成三維型構造之半導體記憶晶片。繼而，使用圖2之放大剖視圖對記憶晶片1及電路晶片2之主要部分之構成進行說明。首先，陣列晶片1如圖2所示，具有基板10、積層體11、記憶柱12、接觸插塞13a~13d、配線層14a~14c、及墊15(第1墊)。
基板10例如為矽基板。於基板10上，於與基板10平行之X方向及Y方向上設置複數個電極層與複數個絕緣層交替積層而成之積層體11。積層體11中，於基板10上之X方向及X方向以陣列狀排列有於與基板10正交之Z方向(第1方向)上貫通積層體11之複數個記憶柱12。於本實施形態中，將包含積層體11之主要部分、設置於積層體11中之複數個記憶柱12、及設置於該等上方之接觸插塞13a~13d、及配線層14a~14c之區域稱為單元陣列區域R1。
再者，於圖2中，將配線層14a~14c簡化後一體示出，但實際上各配線層14a~14c分別包含被層間絕緣膜16絕緣分離之複數條配線(例如位元線)。同樣地，亦將墊15簡化後一體示出，但實際上包含被層間絕緣膜16絕緣分離之複數個墊。
又，將包含單元陣列區域R1之周圍之單元陣列區域R1以外之區域稱為周邊區域R2。於圖1(a)中示出了2個單元陣列區域R1，但單元陣列區域R1實際上陣列狀地排列於X方向、及Y方向。
此處，使用圖3之將包含記憶體膜之記憶柱之一部分放大所得之剖視圖，對記憶柱12之構成進行說明。圖3圖示了積層體11之一部分、及於積層體11內於Z方向上延伸之記憶柱12中包含之2個記憶元件。與電極層111對向之記憶體膜(電荷阻擋膜121、電荷累積層122、穿隧絕緣膜123)及半導體膜124之部分對應於1個記憶胞。
記憶柱12成為於Z方向上包含串聯連接之複數個記憶元件及連接於該等複數個記憶元件之兩端之選擇電晶體(未圖示)之構造。各電極層111係作為與該等記憶元件分別電性連接之字元線或用以選擇該等記憶元件之選擇電晶體之閘極電極發揮功能。
如圖3所示，記憶柱12具有電荷阻擋膜121、電荷累積層122、穿隧絕緣膜123、半導體膜124、及芯膜125。
電荷阻擋膜121、穿隧絕緣膜123及芯膜125例如為氧化矽膜。電荷累積層122例如為氮化矽膜(SiN)。半導體膜124例如為多晶矽膜等膜，且作為通道發揮功能。複數個記憶柱12中之各半導體膜124之上端經由圖2所示之接觸插塞13a連接至配線層14a。
配線層14a中設置有個別連接至半導體膜124之複數條位元線。各位元線經由接觸插塞13b連接至配線層14b。配線層14b經由接觸插塞13c連接至配線層14c。配線層14c經由接觸插塞13d連接至墊15之面15a。於本實施形態中，接觸插塞13a~13d及配線層14a~14c之材料為鋁。墊15之材料為銅。
於積層體11中，複數個電極層111與複數個絕緣層112於與基板10正交之Z方向(第1方向)上交替地積層。再者，圖2及圖3中雖未示出，但積層體11之端部為了將各電極層111電性連接至電路晶片2而形成為階梯狀。該階梯狀形成之端部包含於周邊區域R2中。
各電極層111例如為鎢(W)等金屬層。各絕緣層112積層於電極層111之上下，將各電極層111絕緣分離。各絕緣層112例如為氧化矽層(SiO2 )。
繼而，返回圖2，對電路晶片2之構成進行說明。電路晶片2具有基板20、保護膜21、MOS電晶體22、接觸插塞23a~23f、配線層24a~24c、墊25(第2墊)、接合墊26、虛設墊27、及層間絕緣膜28。
再者，於圖2中，將配線層24a~24c簡化後一體示出，但實際上包含被層間絕緣膜28絕緣分離之複數條配線。同樣地，墊25亦係簡化後一體示出，但實際上包含被層間絕緣膜28絕緣分離之複數個墊。
基板20例如為矽基板。基板20之單面由保護膜21覆蓋。保護膜21例如為聚醯亞胺膜。於基板20之相反側之單面設置有用以驅動陣列晶片1之MOS(Metal-Oxide-Semiconductor，金屬氧化物半導體)電晶體22。
MOS電晶體22例如係具有閘極電極22a、及擴散層22b之MOSFET(Metal-Oxide-Semiconductor Field Effect Transistor，金屬氧化物半導體場效應電晶體)。擴散層22b係源極區域或汲極區域。閘極電極22a經由接觸插塞23a連接至設置於配線層24a之配線。擴散層22b經由接觸插塞23b連接至設置於配線層24a且與上述配線絕緣之另一配線。
配線層24a經由接觸插塞23c連接至配線層24b。配線層24b經由接觸插塞23d連接至配線層24c。於與配線層24c相同之層設置有接合墊26。配線層24c經由接觸插塞23e連接至墊25之面25a。墊25以與面25a為相反側之面25b接合於設置於陣列晶片1之墊15之與面15a為相反側之面15b。接合墊26經由接觸插塞23f連接至虛設墊27。虛設墊27接合於陣列晶片1之墊15。
於本實施形態中，接觸插塞23a~23f、配線層24a~24c、及接合墊26之材料為鋁。墊25及虛設墊27之材料為銅。
接合墊26藉由形成於層間絕緣膜28之導通孔29露出。接合線30接合於接合墊26。電路晶片2經由接合線30連接至安裝基板或其他晶片。於本實施形態中，如圖1(b)所示，複數個接合墊26與作為記憶柱12之形成區域之單元陣列區域R1對向地形成。
以下，對如上所述般構成之半導體記憶裝置之製造步驟進行說明。此處，參照圖4~圖7對電路晶片2之主要製造步驟進行說明。
首先，如圖4所示，於晶圓基板20上形成MOS電晶體22、接觸插塞23a~23f、配線層24a~24c、墊25、接合墊26、虛設墊27、及層間絕緣膜28。
繼而，如圖5所示，將基板20之一部分去除。具體而言，對與接合墊26對向之部分進行刻蝕。
繼而，如圖6所示，形成導通孔29。導通孔29自藉由將基板20之一部分去除而露出之層間絕緣膜28之表面到達接合墊26。
繼而，如圖7所示，將保護膜21成膜。至此，電路晶片2完成。之後，使電路晶片2上下翻轉(旋轉180度)後貼合於陣列晶片1。藉此，將墊25及虛設墊27接合於陣列晶片1之墊15。
根據以上說明之本實施形態，先前，將形成於陣列晶片1之接合墊26形成於電路晶片2。因此，陣列晶片1中不需要接合墊26之形成區域，故而可將不直接有助於記憶功能之無效區域削減。藉此，可使陣列晶片1之面積縮小。
進而，根據本實施形態，電路晶片2於接合墊26之下具有虛設墊27。因此，可利用虛設墊27緩和將接合線30接合時接合墊26中產生之衝擊。
(變化例1)  圖8係表示變化例之電路晶片之概略構造之剖視圖。對與上述第1實施形態之電路晶片2相同之構成要素標註相同符號，並省略詳細說明。
於第1實施形態之電路晶片2中，接合墊26與配線層24c配置於同一層。即，接合墊26配置於墊25之正下方之層。
另一方面，於本變化例之電路晶片2a中，如圖8所示，接合墊26與中間之配線層24b配置於同一層。因此，與配線層24c為同一層之配線層24d設置於接合墊26與虛設墊27之間。配線層24d經由接觸插塞23f連接至虛設墊27，並且經由接觸插塞23g連接至接合墊26。
即便於以上說明之本變化例中，亦與第1實施形態同樣地將接合墊26形成於電路晶片2a，因此可削減陣列晶片1之無效區域。進而，根據本變化例，可利用配線層24d及虛設墊27緩和將接合線30接合時接合墊26中產生之衝擊。
再者，於上述第1實施形態及本變化例中，電路晶片2包含三層配線層，但配線層數並無特別限制。又，接合墊26之位置亦不限於最上層、中間層、及最下層，只要與複數個配線層之其中任一層為同一層即可。
(第2實施形態)  圖9(a)係第2實施形態之半導體記憶裝置之陣列晶片之概略俯視圖。圖9(b)係第2實施形態之半導體記憶裝置之電路晶片之概略俯視圖。對與上述第1實施形態之電路晶片2相同之構成要素標註相同符號，並省略詳細之說明。又，於本實施形態中，僅接合墊26之配置與第1實施形態不同，因此省略剖視圖。
於本實施形態中，如圖9(b)所示，於電路晶片2b中，複數個接合墊26與陣列晶片1之周邊區域R2對向地配置。具體來說，各接合墊26配置於X方向上相互對向之單元陣列區域R1之間或設置於陣列晶片1之積層體11之階梯狀之端部、即連接(hookup)區域。
因此，根據本實施形態，例如當於電路晶片2b中，因空間情況而難以將接合墊26與單元陣列區域R1對向地配置時，可確保接合墊26之形成部位。即便於此情形時，亦因接合墊26形成於電路晶片2而可削減陣列晶片1之無效區域，而使之縮小。
(第3實施形態)  圖10係第3實施形態之半導體記憶裝置之電路晶片之概略剖視圖。對與上述第1實施形態之電路晶片2相同之構成要素標註相同符號，並省略詳細之說明。
於圖10所示之電路晶片2c中，接合墊26與最靠近基板20之配線層24a配置於同一層。因此，配線層24d及配線層24e設置於接合墊26與虛設墊27之間。
配線層24d與配線層24c配置於同一層，且經由接觸插塞23f連接至虛設墊27，並且經由接觸插塞23g連接至配線層24e。另一方面，配線層24e與配線層24b配置於同一層，且經由接觸插塞23h連接至接合墊26。
於本實施形態中，接合墊26之材料為鎢。另一方面，接合線30之材料為鋁。因此，於接合步驟中可能無法將兩者接合。
因此，於本實施形態中，以覆蓋接合墊26及基板20之方式形成鋁層31。藉此，可經由鋁層31將接合線30與接合墊26接合。
即便於以上說明之本實施形態中，亦因接合墊26形成於電路晶片2而可削減陣列晶片1之無效區域，使其縮小。進而，於本實施形態中，即便接合墊26之材料與接合線30之材料不同，亦可將兩者接合。
已對本發明之若干實施形態進行了說明，但該等實施形態係作為例而提出，並無意圖限定發明範圍。該等實施形態可以其他各種方式實施，且可於不脫離發明主旨之範圍內進行各種省略、替換、變更。該等實施形態或其變化包含於發明之範圍或主旨中，並且包含於申請專利範圍所記載之發明及其均等之範圍內。
[相關申請案]  本案享有以日本專利申請案2019-50331號(申請日：2019年3月18日)為基礎申請案之優先權。本案藉由參照該基礎申請案而包含基礎申請案之全部內容。
1:陣列晶片(第1晶片) 2:電路晶片(第2晶片) 10:基板 11:積層體 12:記憶柱 13a:接觸插塞 13b:接觸插塞 13c:接觸插塞 13d:接觸插塞 14a:配線層 14b:配線層 14c:配線層 15:第1墊 15a:面 15b:面 16:層間絕緣膜 20:基板 21:保護膜 22:MOS電晶體 22a:閘極電極 22b:擴散層 23a:接觸插塞 23b:接觸插塞 23c:接觸插塞 23d:接觸插塞 23e:接觸插塞 23f:接觸插塞 24a:配線層 24b:配線層 24c:配線層 25:第2墊 25a:面 25b:面 26:接合墊 27:虛設墊 28:層間絕緣膜 29:導通孔 30:接合線 31:鋁層 111:電極層 112:絕緣層 121:電荷阻擋膜 122:電荷累積層 123:穿隧絕緣膜 124:半導體膜 125:芯膜 R1:單元陣列區域 R2:周邊區域
圖1(a)係第1實施形態之半導體記憶裝置之陣列晶片之概略俯視圖，(b)係第1實施形態之半導體記憶裝置之電路晶片之概略俯視圖。  圖2係切取圖1(a)、(b)之陣列晶片及電路晶片之一部分，並將其主要部分之構造放大表示所得之剖視圖。  圖3係將積層體之一部分及記憶柱之一部分放大所得之剖視圖。  圖4係表示第2晶片之成膜步驟之剖視圖。  圖5係表示基板之刻蝕步驟之剖視圖。  圖6係表示導通孔之形成步驟之剖視圖。  圖7係表示保護膜之成膜步驟之剖視圖。  圖8係表示變化例之電路晶片之概略構造之剖視圖。  圖9(a)係第2實施形態之半導體記憶裝置之陣列晶片之概略俯視圖，(b)係第2實施形態之半導體記憶裝置之電路晶片之概略俯視圖。  圖10係第3實施形態之半導體記憶裝置之電路晶片之概略剖視圖。
1:陣列晶片(第1晶片)
2:電路晶片(第2晶片)
10:基板
11:積層體
12:記憶柱
13a:接觸插塞
13b:接觸插塞
13c:接觸插塞
13d:接觸插塞
14a:配線層
14b:配線層
14c:配線層
15:第1墊
15a:面
15b:面
16:層間絕緣膜
20:基板
21:保護膜
22:MOS電晶體
22a:閘極電極
22b:擴散層
23a:接觸插塞
23b:接觸插塞
23c:接觸插塞
23d:接觸插塞
23e:接觸插塞
23f:接觸插塞
24a:配線層
24b:配線層
24c:配線層
25:第2墊
25a:面
25b:面
26:接合墊
27:虛設墊
28:層間絕緣膜
29:導通孔
30:接合線
R1:單元陣列區域
R2:周邊區域

Claims (8)

  1. 一種半導體記憶裝置，其包括第1晶片與第2晶片，  上述第1晶片具有：  複數個電極層，其於第1方向上積層；  半導體膜，其於上述複數個電極層內於上述第1方向上延伸；及  記憶體膜，其配置於上述複數個電極層與上述半導體膜之間；  上述第2晶片將半導體基板朝上接合於上述第1晶片上，且具有：  MOS電晶體，其設置於上述半導體基板之下表面；  配線，其設置於上述MOS電晶體之下方，且電性連接至上述MOS電晶體；  接合墊，其設置於上述MOS電晶體之下方，且於其上表面進行接合；及  導通孔，其以上述接合墊之上表面為底貫通上述半導體基板，且朝上方開口。
  2. 如請求項1之半導體記憶裝置，其具有：  第1墊，其設置於上述第1晶片與上述第2晶片之貼合面，且將上述半導體膜之上端電性連接於上述配線；及  第2墊，其設置於上述第1晶片與上述第2晶片之貼合面，且於上述第1方向上至少一部分與上述接合墊重疊。
  3. 如請求項1之半導體記憶裝置，其中上述接合墊與至少包含上述複數個記憶柱之單元陣列區域對向地設置。
  4. 如請求項1之半導體記憶裝置，其中上述接合墊與包括至少包含上述複數個記憶柱之單元陣列區域之周圍之周邊區域對向地設置。
  5. 如請求項2之半導體記憶裝置，其中上述第2晶片進而具有設置於上述接合墊與上述第1墊之間之虛設墊。
  6. 如請求項1至5中任一項之半導體記憶裝置，其中上述接合墊與上述配線設置於同一層。
  7. 如請求項1至5中任一項之半導體記憶裝置，其中上述接合墊包含鎢，且接合於上述接合墊之接合線包含鋁，  於上述接合墊與上述接合線之間設置有鋁層。
  8. 一種半導體記憶裝置之製造方法，其將半導體基板朝上地將第2晶片接合於第1晶片上，上述第1晶片具有：複數個電極層，其等於第1方向上積層；半導體膜，其於上述複數個電極層內於上述第1方向上延伸；及記憶體膜，其配置於上述複數個電極層與上述半導體膜之間；  於上述第2晶片形成：MOS電晶體，其設置於上述半導體基板之下表面；配線，其設置於上述MOS電晶體之下方，且電性連接於上述MOS電晶體；接合墊，其設置於上述MOS電晶體之下方，且於其上表面進行接合；及導通孔，其以上述接合墊之上表面為底貫通上述半導體基板，且朝上方開口。
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