CN108336074B - 一种多层芯片及其集成方法 - Google Patents

一种多层芯片及其集成方法 Download PDF

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CN108336074B
CN108336074B CN201810045173.3A CN201810045173A CN108336074B CN 108336074 B CN108336074 B CN 108336074B CN 201810045173 A CN201810045173 A CN 201810045173A CN 108336074 B CN108336074 B CN 108336074B
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chip
metal
layer
lead wire
oxide layer
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CN108336074A (zh
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曹静
胡胜
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Wuhan Xinxin Semiconductor Manufacturing Co Ltd
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Abstract

本发明提供一种多层芯片及其集成方法。所述方法包括：将具有第一金属层的第一芯片和具有第二金属层的第二芯片进行混合键合；在所述第二芯片中设置第一金属引线，所述第一金属引线连接到所述第二金属层；在所述第二芯片上进行氧化物沉积，获得第一氧化层；将所述第一氧化层与第三芯片的第二氧化层进行键合；制作穿过所述第一氧化层、所述第二氧化层的第二金属引线，通过所述第二金属引线连接所述第一金属引线和所述第三芯片中的第三金属层。本发明在两层芯片混合键合的基础上进行第三层芯片的键合，并且三层芯片之间实现了金属互联，填补了目前三层芯片集成的空白，能够满足对器件性能和集成度高的求。

Description

一种多层芯片及其集成方法
技术领域
本发明涉及芯片集成领域，更具体地，涉及一种多层芯片及其集成方法。
背景技术
三维集成3D-IC是在保持现有技术节点的同时提高芯片性能的解决方案，其具有诸多优点，如保持芯片体积的同时，大规模提高芯片的功能，不受单个芯片制造工艺的限制；大幅度缩短功能芯片之间的金属互联，减小发热、功耗、延迟；大幅度提高功能模块之间的带宽，例如将处理器芯片和内存芯片三维集成，可使处理器具有超高速缓冲存储器等。
目前的3D-IC技术是通过硅穿孔或混合键合将两个不同的芯片进行集成，虽然达到了集成和器件性能的提高，但是随着科技的发展，对器件性能和集成度要求越来越高，两层芯片集成已经不能满足需求，需要开发三个或多个芯片进行集成。
发明内容
本发明提供一种克服上述问题或者至少部分地解决上述问题的多层芯片及其集成方法。
根据本发明的一个方面，提供一种多层芯片，包括：第一芯片，所述第一芯片具有第一金属层；
与所述第一芯片键合的第二芯片,所述第二芯片具有第二金属层，且所述第二金属层与所述第一金属层金属键合；
所述第二芯片上的第一氧化层；
具有第二氧化层和第三金属层的第三芯片，所述第二氧化层与所述第一氧化层键合，且所述第三金属层与所述第二金属层金属互联；以及
覆盖设置在所述第三芯片上的SiN掩蔽层。
进一步，所述第二芯片中设置有第一金属引线，所述第一金属引线连接到所述第二金属层，并与所述第三金属层金属互联。
进一步，所述第三芯片中设置有第二金属引线，所述第二金属引线连接所述第三金属层与所述第一金属引线。
具体的，所述第二芯片的厚度范围为2.3-3微米；所述第三芯片的厚度范围为2.3-3微米。
根据本发明的另一个方面，还提供一种多层芯片集成方法，包括：
将具有第一金属层的第一芯片和具有第二金属层的第二芯片进行混合键合；
在所述第二芯片中设置第一金属引线，所述第一金属引线连接到所述第二金属层；
在所述第二芯片上进行氧化物沉积，获得第一氧化层；
将所述第一氧化层与第三芯片的第二氧化层进行键合；
制作穿过所述第一氧化层、所述第二氧化层的第二金属引线，通过所述第二金属引线连接所述第一金属引线和所述第三芯片中的第三金属层。
进一步，所述在所述第二芯片中设置第一金属引线，所述第一金属引线连接到所述第二金属层，之前包括：
将所述第二芯片进行硅减薄。
进一步，所述制作穿过所述第一氧化层、所述第二氧化层的第二金属引线，通过所述第二金属引线连接所述第一金属引线和所述第三芯片中的第三金属层，具体包括：
刻蚀穿过所述第一氧化层、所述第二氧化层以及所述第三芯片至少部分基底的过孔和/或沟槽；
在所述过孔和/或沟槽中设置第二金属引线，以连接所述第一金属引线和所述第三芯片中的第三金属层。
进一步，所述制作穿过所述第一氧化层、所述第二氧化层的第二金属引线，通过所述第二金属引线连接所述第一金属引线和所述第三芯片中的第三金属层，之前还包括：
将所述第三芯片进行硅减薄。
进一步，减薄后的第二芯片硅的厚度范围为2.3-3微米；减薄后的第三芯片硅的厚度范围为2.3-3微米。
进一步，所述制作穿过所述第一氧化层、所述第二氧化层的第二金属引线，通过所述第二金属引线连接所述第一金属引线和所述第三芯片中的第三金属层，之后还包括：
在所述第三芯片上设置SiN掩蔽层。
本发明提出一种多层芯片及其集成方法，所述方法在两层芯片混合键合的基础上进行第三层芯片的氧化键合，并设置金属引线，通过金属引线对所述第二芯片与第三芯片的进行金属互联，以实现三层芯片集成，填补了目前三层芯片集成的空白，能够满足对器件性能和集成度的越来越高的要求。
附图说明
图1为本发明实施例一种多层芯片的结构示意图；
图2为本发明实施例一种多层芯片的集成方法流程示意图；
图3a为本发明实施例多层芯片的集成方法的两层芯片键合的工艺示意图；
图3b为本发明实施例多层芯片的集成方法的两层芯片键合后硅减薄的工艺示意图；
图3c为本发明实施例多层芯片的集成方法的金属线引出的工艺示意图；
图3d为本发明实施例多层芯片的集成方法的三层芯片OX键合的工艺示意图；
图3e为本发明实施例多层芯片的集成方法的第三层芯片硅减薄的工艺示意图；
图3f为本发明实施例多层芯片的集成方法的TSV金属互联的工艺示意图；
其中，1、第一芯片，2、第二芯片，3、第三芯片，41、第一氧化层，42、第二氧化层，5、SiN掩蔽层，11、第一金属层，21、第二金属层，22、第一金属引线，31、第三金属层，32、第二金属引线。
具体实施方式
下面结合附图和实施例，对本发明的具体实施方式作进一步详细描述。以下实施例用于说明本发明，但不用来限制本发明的范围。
图1为本发明实施例一种多层芯片的结构示意图，如图1所示的多层芯片，其特征在于，包括：第一芯片1，所述第一芯片1具有第一金属层11；
与所述第一芯片1键合的第二芯片2,所述第二芯片1具有第二金属层21，且所述第二金属层21与所述第一金属层11金属键合；
所述第二芯片2上的第一氧化层41；
具有第二氧化层42和第三金属层31的第三芯片3，所述第二氧化层42与所述第一氧化层41键合，且所述第三金属层31与所述第二金属层21金属互联；以及
覆盖设置在所述第三芯片上的SiN掩蔽层5。
在一个可选的实施例中，所述第二芯片2中设置有第一金属引线22，所述第一金属引线22连接到所述第二金属层21，并与所述第三金属层31金属互联。
在一个可选的实施例中，所述第三芯片3中设置有第二金属引线32，所述第二金属引线32连接所述第三金属层31与所述第一金属引线22。
本发明实施例通过第一金属引线22和第二金属引线32进行第二芯片2和第三芯片3的金属互联，从而实现三层芯片的电路连通。
具体的，所述第二芯片2的厚度范围为2.3-3微米；所述第三芯片3的厚度范围为2.3-3微米。
在一个可选的实施例中，所述多层芯片还包括：覆盖设置在所述第三芯片上3的SiN掩蔽层5。
本发明实施例在两层芯片混合键合的基础上进行第三层芯片的键合，并且三层芯片之间实现了金属互联，填补了目前三层芯片集成的空白，能够满足对器件性能和集成度高的求。所述多层芯片尺寸小，集成度高，在满足电气性能的前提下可以更方便的适用于各种性能要求的场合，具有良好的有益效果。
图2为本发明实施例一种多层芯片的集成方法流程示意图，如图2所示的多层芯片集成方法，包括：
S1，将具有第一金属层的第一芯片和具有第二金属层的第二芯片进行混合键合；
S2，在所述第二芯片中设置第一金属引线，所述第一金属引线连接到所述第二金属层；具体的，可以根据设计需要设置金属线引出，一般可以采用Via技术设置金属线
S3，在所述第二芯片上进行氧化物沉积，获得第一氧化层；
S4，将所述第一氧化层与第三芯片的第二氧化层进行键合；
S5，制作穿过所述第一氧化层、所述第二氧化层的第二金属引线，通过所述第二金属引线连接所述第一金属引线和所述第三芯片中的第三金属层。
本发明实施例所述多层芯片的集成方法，进行第三层芯片的氧化键合，并设置金属引线，通过金属引线对所述第二芯片与第三芯片的进行金属互联，以实现三层芯片集成，填补了目前三层芯片集成的空白，能够满足对器件性能和集成度的越来越高的要求。
本发明实施例所述多层芯片的集成方法，也可以适用于多余三层芯片集成的多层芯片集成方法，在第三芯片集成的基础上，按照步骤S3-S5所述的方法进行后续的芯片集成即可，在此不再赘述。
在一个可选的实施例中，步骤S2，所述在所述第二芯片中设置第一金属引线，所述第一金属引线连接到所述第二金属层，之前包括：
将所述第二芯片进行硅减薄。
具体的，硅减薄后的所述第二芯片的厚度范围为2.3-3微米。
本发明实施例对第二芯片进行硅减薄，是为了在满足电气性能要求的情况下，减小集成芯片的尺寸。具体的，硅减薄后的所述第二芯片的厚度为2.3微米；或者硅减薄后的所述第二芯片的厚度为3微米。
在一个可选的实施例中，步骤S5，所述制作穿过所述第一氧化层、所述第二氧化层的第二金属引线，通过所述第二金属引线连接所述第一金属引线和所述第三芯片中的第三金属层，具体包括：
刻蚀穿过所述第一氧化层、所述第二氧化层以及所述第三芯片至少部分基底的过孔和/或沟槽；
在所述过孔和/或沟槽中设置第二金属引线，以连接所述第一金属引线和所述第三芯片中的第三金属层。
具体的，本发明实施例可以采用TSV技术协助进行过孔和/或沟槽的制作，具体实施的温度、控制时间等可根据芯片集成的基本条件而确定，本发明实施例可以对此不作特殊要求。所述过孔和/或沟槽的作用是为了金属线能够穿过所述第一氧化层、所述第二氧化层的第二金属引线进而连接第二芯片与第三芯片。
在一个可选的实施例中，步骤S5，所述制作穿过所述第一氧化层、所述第二氧化层的第二金属引线，通过所述第二金属引线连接所述第一金属引线和所述第三芯片中的第三金属层，之前还包括：
将所述第三芯片进行硅减薄。具体的，减薄后的第三芯片的厚度范围为2.3-3微米。
本发明实施例对第三芯片进行硅减薄，也可以在满足电气性能要求的情况下，减小集成芯片的尺寸。具体的，硅减薄后的所述第三芯片的厚度为2.3微米；或者硅减薄后的所述第三芯片的厚度为3微米。
在一个可选的实施例中，所述制作穿过所述第一氧化层、所述第二氧化层的第二金属引线，通过所述第二金属引线连接所述第一金属引线和所述第三芯片中的第三金属层，之后还包括：
S6，在所述第三芯片上设置SiN掩蔽层。
本发明实施例通过TSV技术协助进行过孔和沟槽的制作，具体的过孔和沟槽的位置和形状可根据电路设计要求而定。在制作好的过孔和沟槽中设置铜线，通过铜线第二芯片和第三芯片的金属线连通，从而将三层芯片的电路联通。最后一步，在实现了三层芯片的电路联通之后，在所述第三芯片的非键合面覆盖SIN掩蔽层，至此就完成了三层芯片的集成。
图3a-图3f为本发明实施例多层芯片的集成方法的TSV金属互联的工艺示意图。请参考图3a至图3f，所述基于TSV与混合键合的三维集成方法工艺流程包括：
(1)对两层芯片进行混合键合，如图3a；
(2)对键合的一侧芯片进行硅减薄，如图3b；
(3)将金属线向硅减薄的方向引出，即设置第一金属引线，如图3c；
(4)通过氧化技术在硅减薄后的芯片上键合第三层芯片，如图3d；
(5)对第三层芯片进行硅减薄，如图3e；需要说明的是，第二层和第三层芯片硅减薄后的厚度范围要求是相同的，但并不限制第二层和第三层芯片减薄后的厚度必须相等，第二层和第三层芯片减薄后的厚度可以相等，也可以不相等。
(6)通过TSV技术协助制作过孔和沟槽，设置第二金属引线，通过第二金属引线将第二芯片与第三芯片的金属互联从而实现电路连通，如图3f，这个尺寸也是根据DESIGN需求来设计。
综上所述，本发明实施例所述多层芯片的集成方法，在两层芯片混合键合的基础上进行金属线引出，硅减薄；然后进行第三层芯片的键合，硅减薄；然后通过TSV技术在所述第二芯片与第三芯片之间制作过孔和沟槽，通过所制作的过孔和沟槽利用CU先对所述第二芯片与第三芯片的进行金属互联，以实现三层芯片集成，填补了目前三层芯片集成的空白，能够满足对器件性能和集成度的越来越高的要求，并且实现的三层的集成芯片尺寸小，在满足电气性能的前提下可以更方便的适用于各种性能要求的场合，具有良好的有益效果。
最后应说明的是：以上实施例仅用以说明本发明的技术方案，而非对其限制；尽管参照前述实施例对本发明进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本发明各实施例技术方案的精神和范围。

Claims (10)

1.一种多层芯片，其特征在于，包括：第一芯片，所述第一芯片具有第一金属层；
与所述第一芯片键合的第二芯片,所述第二芯片具有第二金属层，且所述第二金属层与所述第一金属层金属键合；
所述第二芯片上的第一氧化层；
具有第二氧化层和第三金属层的第三芯片，所述第二氧化层与所述第一氧化层键合，且所述第三金属层与所述第二金属层金属互联；以及
覆盖设置在所述第三芯片上的SiN掩蔽层；
所述多层芯片是通过在两层芯片混合键合的基础上进行金属线引出，硅减薄；然后进行第三层芯片的键合，硅减薄；然后通过TSV技术在所述第二芯片与第三芯片之间制作过孔和沟槽，通过所制作的过孔和沟槽利用CU先对所述第二芯片与第三芯片的进行金属互联的方式集成的。
2.根据权利要求1所述的多层芯片，其特征在于，所述第二芯片中设置有第一金属引线，所述第一金属引线连接到所述第二金属层，并与所述第三金属层金属互联。
3.根据权利要求2所述的多层芯片，其特征在于，所述第三芯片中设置有第二金属引线，所述第二金属引线连接所述第三金属层与所述第一金属引线。
4.根据权利要求1所述的多层芯片，其特征在于，所述第二芯片的厚度范围为2.3-3微米；所述第三芯片的厚度范围为2.3-3微米。
5.一种多层芯片的集成方法，其特征在于，包括：
将具有第一金属层的第一芯片和具有第二金属层的第二芯片进行混合键合；
在所述第二芯片中设置第一金属引线，所述第一金属引线连接到所述第二金属层；
在所述第二芯片上进行氧化物沉积，获得第一氧化层；
将所述第一氧化层与第三芯片的第二氧化层进行键合；
制作穿过所述第一氧化层、所述第二氧化层的第二金属引线，通过所述第二金属引线连接所述第一金属引线和所述第三芯片中的第三金属层。
6.根据权利要求5所述的方法，其特征在于，所述在所述第二芯片中设置第一金属引线，所述第一金属引线连接到所述第二金属层，之前包括：
将所述第二芯片进行硅减薄。
7.根据权利要求6所述的方法，其特征在于，所述制作穿过所述第一氧化层、所述第二氧化层的第二金属引线，通过所述第二金属引线连接所述第一金属引线和所述第三芯片中的第三金属层，具体包括：
刻蚀穿过所述第一氧化层、所述第二氧化层以及所述第三芯片至少部分基底的过孔和/或沟槽；
在所述过孔和/或沟槽中设置第二金属引线，以连接所述第一金属引线和所述第三芯片中的第三金属层。
8.根据权利要求5-7任一项所述的方法，其特征在于，所述制作穿过所述第一氧化层、所述第二氧化层的第二金属引线，通过所述第二金属引线连接所述第一金属引线和所述第三芯片中的第三金属层，之前还包括：
将所述第三芯片进行硅减薄。
9.根据权利要求5-7任一项所述的方法，其特征在于，减薄后的第二芯片硅的厚度范围为2.3-3微米；减薄后的第三芯片硅的厚度范围为2.3-3微米。
10.根据权利要求5-7任一项所述的方法，其特征在于，所述制作穿过所述第一氧化层、所述第二氧化层的第二金属引线，通过所述第二金属引线连接所述第一金属引线和所述第三芯片中的第三金属层，之后还包括：
在所述第三芯片上设置SiN掩蔽层。
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