JP2010080772A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP2010080772A JP2010080772A JP2008248902A JP2008248902A JP2010080772A JP 2010080772 A JP2010080772 A JP 2010080772A JP 2008248902 A JP2008248902 A JP 2008248902A JP 2008248902 A JP2008248902 A JP 2008248902A JP 2010080772 A JP2010080772 A JP 2010080772A
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- film
- wiring
- conduction
- opening
- metal
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- Semiconductor Integrated Circuits (AREA)
Abstract
【解決手段】第2配線13上の層間絶縁膜21には、その表面から第2配線13に達するパッド開口22が形成されている。第2配線13におけるパッド開口22に臨む部分上には、AlCu合金からなるボンディングパッド25が形成されている。また、層間絶縁膜21上には、AlCu合金からなる電磁波シールド膜27が形成されている。そして、パッド開口22の側面上には、ボンディングパッド25と電磁波シールド膜27との導通を確保するための導通確保膜24が形成されている。ボンディングパッド25と電磁波シールド膜27とが直接に接続されなくても、導通確保膜24により、ボンディングパッド25と電磁波シールド膜27との導通を確保することができる。
【選択図】図1
Description
図3は、トランスデバイスの構造を示す模式的な断面図である。
トランスデバイス101は、図示しない半導体基板上に、SiO2(酸化シリコン)からなる第1絶縁層102を備えている。
第1絶縁層102上には、第2絶縁層106が積層されている。第2絶縁層106は、拡散防止/エッチングストッパ膜107、層間絶縁膜108、エッチングストッパ膜109および絶縁膜110をこの順に積層した構造を有している。
また、第2配線溝111は、平面視で第1配線105と交差する部分を有するパターンに形成されている。そして、平面視で第1配線105と第2配線溝111とが交差する部分において、それらの間には、拡散防止/エッチングストッパ膜107および層間絶縁膜108を貫通するビアホール114が形成されている。ビアホール114には、バリアメタル115を介して、ビア116が埋設されている。これにより、第1配線105と第2配線113とは、ビア116を介して電気的に接続されている。
第2絶縁層106上には、拡散防止/エッチングストッパ膜120および層間絶縁膜121が積層されている。第2配線113は、最上層配線であり、拡散防止/エッチングストッパ膜120および層間絶縁膜121には、層間絶縁膜121の表面から第2配線113に達するパッド開口122が形成されている。パッド開口122の内面には、バリアメタル123が被着されている。パッド開口122内において、バリアメタル123上には、Al(アルミニウム)とCuとを含む合金(以下「AlCu合金」という。)からなるボンディングパッド124が設けられている。ボンディングパッド124には、外部との電気接続のためのボンディングワイヤ(図示せず)が接続される。
請求項3に記載のように、前記導通確保膜の材料は、タングステンであってもよい。
また、請求項6に記載のように、前記半導体装置は、前記配線と同一層に形成され、トランスを構成するための平面視渦巻状のコイルをさらに備えていてもよい。この場合、前記表面金属膜は、平面視で前記コイルを覆い隠し、外部からの電磁波をシールドして誤作動を防ぐための電磁波シールド膜であってもよい。
図1は、本発明の一実施形態に係る半導体装置の構造を示す模式的な断面図である。
半導体装置1は、トランスデバイスであり、図示しない半導体基板を備えている。半導体基板としては、Si(シリコン)基板、SiC(炭化珪素)基板などを例示することができる。
第1絶縁層2には、第1配線溝3が形成されている。第1配線溝3は、第1絶縁層2の上面から掘り下がった凹状をなしている。
第1配線溝3の内面(側面および底面)上には、バリアメタル4が形成されている。バリアメタル4は、たとえば、下からTa(タンタル)膜、TaN(窒化タンタル)膜およびTa膜をこの順に積層した構造を有している。そして、第1配線溝3には、バリアメタル4を介して、Cu配線材料(Cuを主成分とする金属材料)からなる第1配線5が埋設されている。第1配線5は、その表面が第1絶縁層2の表面と面一をなしている。バリアメタル4により、第1配線5のCu配線材料に含まれる成分が第1絶縁層2に拡散することが防止されている。
第2配線溝11の内面(側面および底面)上には、バリアメタル12が形成されている。バリアメタル12は、下からTa膜、TaN膜およびTa膜をこの順に積層した構造を有している。そして、第2配線溝11には、バリアメタル12を介して、Cu配線材料からなる第2配線13が埋設されている。第2配線13は、その表面が第2絶縁層6の表面と面一をなし、第2配線溝11の深さからバリアメタル12の厚さを差し引いた厚さ(たとえば、2μm)を有している。バリアメタル12により、第2配線13のCu配線材料に含まれる成分が第2絶縁層6に拡散することが防止されている。
ビアホール14の側面および第1配線5におけるビアホール14に臨む部分上には、バリアメタル15が形成されている。バリアメタル15は、下からTa膜、TaN膜およびTa膜をこの順に積層した構造を有している。そして、ビアホール14には、バリアメタル15を介して、Cu配線材料からなるビア16が埋設されている。バリアメタル15により、ビア16のCu配線材料に含まれる成分が第2絶縁層6に拡散することが防止されている。第1配線5と第2配線13とは、ビア16を介して電気的に接続されている。
コイル溝17の内面(側面および底面)上には、バリアメタル18が形成されている。バリアメタル18は、第2配線溝11の内面上に形成されているバリアメタル12と同じ積層構造を有している。すなわち、バリアメタル18は、下からTa膜、TaN膜およびTa膜をこの順に積層した構造を有している。そして、コイル溝17には、バリアメタル18を介して、第2配線13の材料と同じ材料であるCu配線材料からなるコイル19が埋設されている。コイル19は、他のコイル(図示せず)とともにトランスを構成する。コイル19は、その表面が第2絶縁層6の表面と面一をなし、第2配線13と同じ厚さを有している。バリアメタル18により、コイル19のCu配線材料に含まれる成分が第2絶縁層6に拡散することが防止されている。
層間絶縁膜21上には、コイル19の全体と対向する領域およびパッド開口22の周囲の領域に、バリアメタル26が形成されている。バリアメタル26は、導通確保膜24上にも形成されている。バリアメタル26は、下からTi膜およびTiN膜をこの順に積層した構造を有している。Ti膜およびTiN膜の厚さは、たとえば、それぞれ7nm(0.007μm)および40nm(0.04μm)である。
図2A〜2Gは、図1に示す半導体装置の製造方法を説明するための模式的な断面図である。
図2Bに示すように、PECVD(Plasma Enhanced Chemical Vapor Deposition:プラズマ化学気相成長)法により、第2絶縁層6上に、拡散防止/エッチングストッパ膜20および層間絶縁膜21が順に形成される。
その後、図2Dに示すように、スパッタ法により、パッド開口22の側面および第2配線13におけるパッド開口22に臨む部分上には、バリアメタル23の材料からなる積層膜(たとえば、Ta膜、TaN膜、Ti膜およびTiN膜)31が形成される。
そして、CMP(Chemical Mechanical Polishing:化学的機械的研磨)法により、W膜32の表面が研磨される。この研磨は、図2Fに示すように、W膜32におけるパッド開口22外の部分が完全に除去され、さらに積層膜31におけるパッド開口22外の部分が完全に除去されて、パッド開口22外において層間絶縁膜21の上面が露出するまで続けられる。これにより、パッド開口22内に、バリアメタル23および導通確保膜24が得られる。
この後、フォトリソグラフィおよびエッチングにより、積層膜33およびAlCu合金膜34がパターニングされる。その結果、図1に示すように、ボンディングパッド25、バリアメタル26および電磁波シールド膜27が形成され、これらを備える半導体装置1が得られる。
導通確保膜24は、CVD法によりW膜32が形成され、パッド開口22外からW膜32が除去されることにより形成される。CVD法により、パッド開口22の側面にW膜32を良好に付着させることができる。その結果、パッド開口22の側面に導通確保膜24を確実に形成することができる。
その他、特許請求の範囲に記載された事項の範囲で種々の設計変更を施すことが可能である。
13 第2配線(配線)
19 コイル
21 層間絶縁膜
22 パッド開口(開口)
24 導通確保膜
25 ボンディングパッド(開口内金属膜)
26 バリアメタル
27 電磁波シールド膜(表面金属膜)
Claims (6)
- 配線と、
前記配線上に形成され、その表面から前記配線に達する開口を有する層間絶縁膜と、
前記開口内において前記配線上に形成され、アルミニウムを含む金属材料からなる開口内金属膜と、
前記層間絶縁膜上に形成され、前記金属材料からなる表面金属膜と、
前記開口の側面上に形成され、前記開口内金属膜と前記表面金属膜との導通を確保するための導通確保膜とを含む、半導体装置。 - 前記導通確保膜は、CVD法により形成される、請求項1に記載の半導体装置。
- 前記導通確保膜は、タングステンからなる、請求項1または2に記載の半導体装置。
- 前記導通確保膜の厚さは、100nm以上、前記層間絶縁膜の厚さ以下である、請求項1〜3のいずれか一項に記載の半導体装置。
- 前記層間絶縁膜と前記表面金属膜との間に介在され、前記金属材料の成分が前記層間絶縁膜に拡散することを防止するためのバリアメタルをさらに含む、請求項1〜4のいずれか一項に記載の半導体装置。
- 前記配線と同一層に形成され、トランスを構成するための平面視渦巻状のコイルをさらに含み、
前記表面金属膜は、平面視で前記コイルと対向する領域を被覆し、前記コイルから発生する電磁波をシールドするための電磁波シールド膜である、請求項1〜5のいずれか一項に記載の半導体装置。
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JP2017224753A (ja) * | 2016-06-16 | 2017-12-21 | セイコーエプソン株式会社 | 半導体装置及びその製造方法 |
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JPH04369226A (ja) * | 1991-06-17 | 1992-12-22 | Hitachi Ltd | 半導体集積回路装置 |
JP2001326242A (ja) * | 2000-05-16 | 2001-11-22 | Matsushita Electric Ind Co Ltd | 半導体装置およびその製造方法 |
JP2003068740A (ja) * | 2001-08-30 | 2003-03-07 | Hitachi Ltd | 半導体集積回路装置およびその製造方法 |
JP2008084969A (ja) * | 2006-09-26 | 2008-04-10 | Seiko Epson Corp | 半導体装置 |
JP2008218566A (ja) * | 2007-03-01 | 2008-09-18 | Nec Electronics Corp | 半導体装置 |
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DE102004014752B4 (de) * | 2004-03-25 | 2008-11-20 | Infineon Technologies Ag | Halbleiterbauelement mit kernlosem Wandler und Halbbrücke |
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Publication number | Priority date | Publication date | Assignee | Title |
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JPH04369226A (ja) * | 1991-06-17 | 1992-12-22 | Hitachi Ltd | 半導体集積回路装置 |
JP2001326242A (ja) * | 2000-05-16 | 2001-11-22 | Matsushita Electric Ind Co Ltd | 半導体装置およびその製造方法 |
JP2003068740A (ja) * | 2001-08-30 | 2003-03-07 | Hitachi Ltd | 半導体集積回路装置およびその製造方法 |
JP2008084969A (ja) * | 2006-09-26 | 2008-04-10 | Seiko Epson Corp | 半導体装置 |
JP2008218566A (ja) * | 2007-03-01 | 2008-09-18 | Nec Electronics Corp | 半導体装置 |
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Publication number | Priority date | Publication date | Assignee | Title |
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JP2017224753A (ja) * | 2016-06-16 | 2017-12-21 | セイコーエプソン株式会社 | 半導体装置及びその製造方法 |
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