JP2007049089A - 半導体装置およびその製造方法 - Google Patents
半導体装置およびその製造方法 Download PDFInfo
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- JP2007049089A JP2007049089A JP2005234676A JP2005234676A JP2007049089A JP 2007049089 A JP2007049089 A JP 2007049089A JP 2005234676 A JP2005234676 A JP 2005234676A JP 2005234676 A JP2005234676 A JP 2005234676A JP 2007049089 A JP2007049089 A JP 2007049089A
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- insulating film
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
- H01L23/5223—Capacitor integral with wiring layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
【解決手段】 半導体装置1は、層間絶縁膜10、配線12a〜12c、層間絶縁膜20、および容量素子30を備えている。層間絶縁膜10および配線12a〜12d上には、拡散防止膜40を介して層間絶縁膜20が設けられている。層間絶縁膜20上には、容量素子30が設けられている。容量素子30は、MIM型容量素子であり、層間絶縁膜20上に設けられた下部電極32、下部電極32上に設けられた容量絶縁膜34、および容量絶縁膜34上に設けられた上部電極36によって構成されている。ここで、層間絶縁膜20と容量素子30との界面S1は、略平坦である。また、層間絶縁膜20の下面S2は、容量絶縁膜34に対向する位置に凹凸を有している。
【選択図】 図1
Description
10 層間絶縁膜
12a〜12d 配線
20 層間絶縁膜
30 容量素子
32 下部電極
34 容量絶縁膜
36 上部電極
40 拡散防止膜
50 層間絶縁膜
52a〜52c ビアプラグ
60 絶縁膜
70 層間絶縁膜
72a〜72c 配線
Claims (7)
- 半導体基板上に設けられた第1の絶縁膜と、
前記第1の絶縁膜中に埋め込まれた導体と、
前記第1の絶縁膜および前記導体上に設けられた第2の絶縁膜と、
前記第2の絶縁膜上に設けられた下部電極と、
前記下部電極上における前記導体の少なくとも一部に対向する領域に設けられた容量絶縁膜と、
前記容量絶縁膜上に設けられた上部電極と、を備え、
前記第2の絶縁膜と前記下部電極との界面は、略平坦であり、
前記第2の絶縁膜における前記第1の絶縁膜および前記導体側の面は、前記容量絶縁膜に対向する位置に凹凸を有することを特徴とする半導体装置。 - 請求項1に記載の半導体装置において、
前記導体の表面は、前記第1の絶縁膜の表面に対して窪んでいる半導体装置。 - 請求項1または2に記載の半導体装置において、
前記第2の絶縁膜は、拡散防止膜を介して、前記第1の絶縁膜および前記導体上に設けられている半導体装置。 - 請求項1乃至3いずれかに記載の半導体装置において、
前記導体は、電源配線である半導体装置。 - 請求項1乃至4いずれかに記載の半導体装置において、
前記導体は、銅を主成分とする金属である半導体装置。 - 半導体基板上に第1の絶縁膜を形成する工程と、
前記第1の絶縁膜中に埋め込まれるように導体を形成する工程と、
前記第1の絶縁膜および前記導体上に、第2の絶縁膜を形成する工程と、
前記第2の絶縁膜の表面を平坦化する工程と、
平坦化された前記第2の絶縁膜上に、下部電極を形成する工程と、
前記下部電極上における前記導体の少なくとも一部に対向する領域に容量絶縁膜を形成する工程と、
前記容量絶縁膜上に上部電極を形成する工程と、
を含むことを特徴とする半導体装置の製造方法。 - 請求項6に記載の半導体装置の製造方法において、
前記導体を形成する工程においては、当該導体として銅を主成分とする金属をダマシン法により形成する半導体装置の製造方法。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005234676A JP4949656B2 (ja) | 2005-08-12 | 2005-08-12 | 半導体装置およびその製造方法 |
CN200610111007.6A CN1913158B (zh) | 2005-08-12 | 2006-08-11 | 半导体器件及其制造方法 |
US11/502,429 US7633138B2 (en) | 2005-08-12 | 2006-08-11 | Semiconductor device and method of manufacturing the same |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005234676A JP4949656B2 (ja) | 2005-08-12 | 2005-08-12 | 半導体装置およびその製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2007049089A true JP2007049089A (ja) | 2007-02-22 |
JP4949656B2 JP4949656B2 (ja) | 2012-06-13 |
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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JP2005234676A Expired - Fee Related JP4949656B2 (ja) | 2005-08-12 | 2005-08-12 | 半導体装置およびその製造方法 |
Country Status (3)
Country | Link |
---|---|
US (1) | US7633138B2 (ja) |
JP (1) | JP4949656B2 (ja) |
CN (1) | CN1913158B (ja) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009038367A (ja) * | 2007-07-09 | 2009-02-19 | Nec Electronics Corp | 半導体装置およびその製造方法 |
JP2010278159A (ja) * | 2009-05-27 | 2010-12-09 | Renesas Electronics Corp | 半導体装置、下層配線設計装置、下層配線設計方法およびコンピュータプログラム |
US8351244B2 (en) | 2009-05-28 | 2013-01-08 | Panasonic Corporation | Memory cell array, nonvolatile storage device, memory cell, and method of manufacturing memory cell array |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5175059B2 (ja) | 2007-03-07 | 2013-04-03 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
KR20110064269A (ko) * | 2009-12-07 | 2011-06-15 | 삼성전자주식회사 | 반도체 소자 및 그것의 제조 방법, 및 그것을 포함하는 반도체 모듈, 전자 회로 기판 및 전자 시스템 |
KR101095724B1 (ko) * | 2010-02-05 | 2011-12-21 | 주식회사 하이닉스반도체 | 저장 캐패시터를 포함하는 반도체 장치 및 그의 형성 방법 |
US9666660B2 (en) * | 2013-08-16 | 2017-05-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor structures including metal insulator metal capacitor |
US10497773B2 (en) | 2014-03-31 | 2019-12-03 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method to improve MIM device performance |
US9257498B1 (en) | 2014-08-04 | 2016-02-09 | Taiwan Semiconductor Manufacturing Co., Ltd. | Process to improve performance for metal-insulator-metal (MIM) capacitors |
US9793339B2 (en) * | 2015-01-08 | 2017-10-17 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for preventing copper contamination in metal-insulator-metal (MIM) capacitors |
JP7284121B2 (ja) * | 2020-03-23 | 2023-05-30 | 株式会社東芝 | アイソレータ |
Citations (7)
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JPH11145288A (ja) * | 1997-09-08 | 1999-05-28 | Hitachi Ltd | 半導体集積回路装置およびその製造方法 |
JP2001313371A (ja) * | 2000-03-16 | 2001-11-09 | Internatl Business Mach Corp <Ibm> | 金属キャパシタおよびその形成方法 |
JP2002124576A (ja) * | 2000-08-31 | 2002-04-26 | Agere Systems Guardian Corp | テーパランディングを有する構造及び製造方法 |
JP2002353328A (ja) * | 2001-05-30 | 2002-12-06 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
JP2003303880A (ja) * | 2002-04-10 | 2003-10-24 | Nec Corp | 積層層間絶縁膜構造を利用した配線構造およびその製造方法 |
WO2003096420A1 (fr) * | 2002-05-07 | 2003-11-20 | Stmicroelectronics Sa | Circuit electronique comprenant un condensateur et au moins un composant semiconducteur, et procede de conception d'un tel circuit |
JP2005150237A (ja) * | 2003-11-12 | 2005-06-09 | Toshiba Corp | 半導体装置及びその製造方法 |
Family Cites Families (6)
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US6833604B2 (en) | 2000-10-03 | 2004-12-21 | Broadcom Corporation | High density metal capacitor using dual-damascene copper interconnect |
JP4349742B2 (ja) | 2000-12-27 | 2009-10-21 | 富士通マイクロエレクトロニクス株式会社 | 回路設計装置、および回路設計方法 |
US6391713B1 (en) * | 2001-05-14 | 2002-05-21 | Silicon Integrated Systems Corp. | Method for forming a dual damascene structure having capacitors |
JP2002353324A (ja) | 2001-05-24 | 2002-12-06 | Matsushita Electric Ind Co Ltd | 半導体装置およびその製造方法 |
JP2003258107A (ja) | 2002-02-28 | 2003-09-12 | Hitachi Ltd | 半導体集積回路装置およびその製造方法 |
US7433811B2 (en) * | 2003-05-06 | 2008-10-07 | The Regents Of The University Of California | Direct patterning of silicon by photoelectrochemical etching |
-
2005
- 2005-08-12 JP JP2005234676A patent/JP4949656B2/ja not_active Expired - Fee Related
-
2006
- 2006-08-11 CN CN200610111007.6A patent/CN1913158B/zh active Active
- 2006-08-11 US US11/502,429 patent/US7633138B2/en active Active
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH11145288A (ja) * | 1997-09-08 | 1999-05-28 | Hitachi Ltd | 半導体集積回路装置およびその製造方法 |
JP2001313371A (ja) * | 2000-03-16 | 2001-11-09 | Internatl Business Mach Corp <Ibm> | 金属キャパシタおよびその形成方法 |
JP2002124576A (ja) * | 2000-08-31 | 2002-04-26 | Agere Systems Guardian Corp | テーパランディングを有する構造及び製造方法 |
JP2002353328A (ja) * | 2001-05-30 | 2002-12-06 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
JP2003303880A (ja) * | 2002-04-10 | 2003-10-24 | Nec Corp | 積層層間絶縁膜構造を利用した配線構造およびその製造方法 |
WO2003096420A1 (fr) * | 2002-05-07 | 2003-11-20 | Stmicroelectronics Sa | Circuit electronique comprenant un condensateur et au moins un composant semiconducteur, et procede de conception d'un tel circuit |
JP2005150237A (ja) * | 2003-11-12 | 2005-06-09 | Toshiba Corp | 半導体装置及びその製造方法 |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009038367A (ja) * | 2007-07-09 | 2009-02-19 | Nec Electronics Corp | 半導体装置およびその製造方法 |
US8039924B2 (en) | 2007-07-09 | 2011-10-18 | Renesas Electronics Corporation | Semiconductor device including capacitor element provided above wiring layer that includes wiring with an upper surface having protruding portion |
US8481399B2 (en) | 2007-07-09 | 2013-07-09 | Renesas Electronics Corporation | Method of manufacturing semiconductor device including capacitor element provided above wiring layer that includes wiring with an upper surface having protruding portion |
JP2010278159A (ja) * | 2009-05-27 | 2010-12-09 | Renesas Electronics Corp | 半導体装置、下層配線設計装置、下層配線設計方法およびコンピュータプログラム |
US8351244B2 (en) | 2009-05-28 | 2013-01-08 | Panasonic Corporation | Memory cell array, nonvolatile storage device, memory cell, and method of manufacturing memory cell array |
Also Published As
Publication number | Publication date |
---|---|
CN1913158B (zh) | 2010-07-07 |
JP4949656B2 (ja) | 2012-06-13 |
US20070034924A1 (en) | 2007-02-15 |
US7633138B2 (en) | 2009-12-15 |
CN1913158A (zh) | 2007-02-14 |
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