JP4231055B2 - 半導体装置及びその製造方法 - Google Patents
半導体装置及びその製造方法 Download PDFInfo
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- JP4231055B2 JP4231055B2 JP2006028053A JP2006028053A JP4231055B2 JP 4231055 B2 JP4231055 B2 JP 4231055B2 JP 2006028053 A JP2006028053 A JP 2006028053A JP 2006028053 A JP2006028053 A JP 2006028053A JP 4231055 B2 JP4231055 B2 JP 4231055B2
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- wiring
- interlayer insulating
- insulating film
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76865—Selective removal of parts of the layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76885—By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
- H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
その後、図14に示すように、この配線溝T1の内壁全体に、Cu配線中のCuを第1の層間絶縁膜201中に拡散させることを防止するためのバリアメタル膜203を形成する。続いて、図15に示すように、半導体基板200上の全体に、配線溝T1の内部も含めてフォトレジスト204を堆積させた後、CMP法(Chemical Mechanical Polishing )を実行して、配線溝T1外のフォトレジスト204を除去し、配線溝T1の内部をフォトレジスト204で埋め込む。この状態において、バリアメタル203は、配線溝T1の上端部のみにおいて表面に露出している。
Claims (5)
- 層間絶縁膜に形成された配線溝に銅を埋め込んだ後平坦化して形成されたCu配線を具備する半導体装置において、
前記層間絶縁膜が、第1の層間絶縁膜と、前記第1の層間絶縁膜上に形成され銅の拡散を防止する性質を有する第2の層間絶縁膜とから構成され、
前記配線溝の内壁の第2の層間絶縁膜の中間付近より上方の部分を除く部分に形成されたバリアメタル膜を備え、
前記Cu配線は、前記配線溝の内壁に沿って前記バリアメタル膜上に形成され、前記配線溝上端部で前記バリアメタル膜の上端を覆い前記第2の層間絶縁膜と接するとともに、前記配線溝の内部に凹部を残して形成された第1のCu配線と、前記凹部を含む前記配線溝を埋め込むように形成された第2のCu配線とから構成される
ことを特徴とする半導体装置。 - 前記バリアメタル膜は、Ta、TaN、TaSiN、Ti、TiN、Mn、MnO、Nb、NbN、WN又はWSiNから構成されることを特徴とする請求項1記載の半導体装置。
- 前記第2の層間絶縁膜は、SiN、SiC又はSiCNを主成分とすることを特徴とする請求項1記載の半導体装置。
- 層間絶縁膜に配線溝を形成し、メタルを埋め込み平坦化して形成されたCu配線を有する半導体装置の製造方法において、
第1の層間絶縁膜を形成する工程と、
前記第1の層間絶縁膜上に銅の拡散を防止する性質を有する第2の層間絶縁膜を形成する工程と、
前記第2の層間絶縁膜を貫通して前記第1の層間絶縁膜に達するように配線溝を形成する工程と、
前記配線溝の内壁にバリアメタル膜を形成する工程と、
前記配線溝内にレジストを埋め込んだ後、このレジストをマスクとして前記バリアメタル膜を前記第1及び第2の層間絶縁膜の界面が露出しない程度までエッチバックする工程と、
前記レジストを剥離した後、前記配線溝内に銅を埋め込む工程と
を備えたことを特徴とした半導体装置の製造方法。 - 層間絶縁膜に配線溝を形成し、メタルを埋め込み平坦化して形成されたCu配線を有する半導体装置の製造方法において、
第1の層間絶縁膜を形成する工程と、
前記第1の層間絶縁膜に配線溝を形成する工程と、
前記配線溝の内壁にバリアメタル膜を形成する工程と、
前記バリアメタル膜上にレジストを埋め込んだ後、このレジストをマスクとして前記バリアメタル膜をエッチバックする工程と、
前記レジストを剥離した後前記Cu配線を前記配線溝に埋め込み形成する工程と、
前記第1の層間絶縁膜を前記バリアメタル膜が露出する程度までエッチバックする工程と、
前記第1の層間絶縁膜及び前記Cu配線を覆うように銅の拡散を防止する性質を有する第2の層間絶縁膜を形成する工程と
を備えたことを特徴とした半導体装置の製造方法。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006028053A JP4231055B2 (ja) | 2006-02-06 | 2006-02-06 | 半導体装置及びその製造方法 |
US11/702,135 US7553757B2 (en) | 2006-02-06 | 2007-02-05 | Semiconductor device and method of manufacturing the same |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006028053A JP4231055B2 (ja) | 2006-02-06 | 2006-02-06 | 半導体装置及びその製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2007208170A JP2007208170A (ja) | 2007-08-16 |
JP4231055B2 true JP4231055B2 (ja) | 2009-02-25 |
Family
ID=38443193
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2006028053A Expired - Fee Related JP4231055B2 (ja) | 2006-02-06 | 2006-02-06 | 半導体装置及びその製造方法 |
Country Status (2)
Country | Link |
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US (1) | US7553757B2 (ja) |
JP (1) | JP4231055B2 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11315926B2 (en) | 2020-06-09 | 2022-04-26 | Samsung Electronics Co., Ltd. | Integrated circuit devices and methods of manufacturing the same |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009194195A (ja) * | 2008-02-15 | 2009-08-27 | Panasonic Corp | 半導体装置及びその製造方法 |
JP2010040771A (ja) * | 2008-08-05 | 2010-02-18 | Rohm Co Ltd | 半導体装置の製造方法 |
US7955971B2 (en) * | 2009-06-11 | 2011-06-07 | International Business Machines Corporation | Hybrid metallic wire and methods of fabricating same |
KR101604054B1 (ko) * | 2009-09-03 | 2016-03-16 | 삼성전자주식회사 | 반도체 소자 및 그 형성방법 |
KR102274775B1 (ko) | 2014-11-13 | 2021-07-08 | 삼성전자주식회사 | 반도체 장치 및 그 제조 방법 |
US10096639B2 (en) * | 2016-10-10 | 2018-10-09 | Sensors Unlimited, Inc. | Bump structures for interconnecting focal plane arrays |
US10361120B2 (en) | 2017-11-30 | 2019-07-23 | Taiwan Semiconductor Manufacturing Co., Ltd. | Conductive feature formation and structure |
DE102018102448B4 (de) * | 2017-11-30 | 2023-06-15 | Taiwan Semiconductor Manufacturing Co., Ltd. | Bildung und Struktur leitfähiger Merkmale |
Family Cites Families (17)
Publication number | Priority date | Publication date | Assignee | Title |
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JP3373320B2 (ja) | 1995-02-10 | 2003-02-04 | 株式会社アルバック | 銅配線製造方法 |
JP3521200B2 (ja) | 1995-12-12 | 2004-04-19 | 松下電器産業株式会社 | 配線構造およびその形成方法 |
US5994220A (en) * | 1996-02-02 | 1999-11-30 | Micron Technology, Inc. | Method for forming a semiconductor connection with a top surface having an enlarged recess |
US6124203A (en) * | 1998-12-07 | 2000-09-26 | Advanced Micro Devices, Inc. | Method for forming conformal barrier layers |
JP2000323479A (ja) | 1999-05-14 | 2000-11-24 | Sony Corp | 半導体装置およびその製造方法 |
US6433429B1 (en) * | 1999-09-01 | 2002-08-13 | International Business Machines Corporation | Copper conductive line with redundant liner and method of making |
FR2802336B1 (fr) * | 1999-12-13 | 2002-03-01 | St Microelectronics Sa | Structure d'interconnexions de type damascene et son procede de realisation |
US20020081845A1 (en) * | 2000-12-27 | 2002-06-27 | Novellus Systems, Inc. | Method for the formation of diffusion barrier |
JP2003007705A (ja) | 2001-06-26 | 2003-01-10 | Mitsubishi Electric Corp | 銅配線の形成方法 |
US6734090B2 (en) * | 2002-02-20 | 2004-05-11 | International Business Machines Corporation | Method of making an edge seal for a semiconductor device |
US7687917B2 (en) * | 2002-05-08 | 2010-03-30 | Nec Electronics Corporation | Single damascene structure semiconductor device having silicon-diffused metal wiring layer |
JP4076131B2 (ja) * | 2002-06-07 | 2008-04-16 | 富士通株式会社 | 半導体装置の製造方法 |
US6964919B2 (en) * | 2002-08-12 | 2005-11-15 | Intel Corporation | Low-k dielectric film with good mechanical strength |
JP3949652B2 (ja) * | 2003-02-17 | 2007-07-25 | Necエレクトロニクス株式会社 | 半導体装置の製造方法 |
JP3647853B1 (ja) | 2003-10-24 | 2005-05-18 | 沖電気工業株式会社 | 半導体装置の配線構造及びその製造方法 |
KR100552812B1 (ko) * | 2003-12-31 | 2006-02-22 | 동부아남반도체 주식회사 | 반도체 소자의 구리 배선 형성 방법 |
US7432189B2 (en) * | 2005-11-30 | 2008-10-07 | Lam Research Corporation | Device with self aligned gaps for capacitance reduction |
-
2006
- 2006-02-06 JP JP2006028053A patent/JP4231055B2/ja not_active Expired - Fee Related
-
2007
- 2007-02-05 US US11/702,135 patent/US7553757B2/en not_active Expired - Fee Related
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11315926B2 (en) | 2020-06-09 | 2022-04-26 | Samsung Electronics Co., Ltd. | Integrated circuit devices and methods of manufacturing the same |
US11646316B2 (en) | 2020-06-09 | 2023-05-09 | Samsung Electronics Co., Ltd. | Integrated circuit devices and methods of manufacturing the same |
Also Published As
Publication number | Publication date |
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US7553757B2 (en) | 2009-06-30 |
JP2007208170A (ja) | 2007-08-16 |
US20070200237A1 (en) | 2007-08-30 |
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