CN1050935C - 提供和集成电路的电接触的引线架和集成电路封装 - Google Patents

提供和集成电路的电接触的引线架和集成电路封装 Download PDF

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CN1050935C
CN1050935C CN94108013A CN94108013A CN1050935C CN 1050935 C CN1050935 C CN 1050935C CN 94108013 A CN94108013 A CN 94108013A CN 94108013 A CN94108013 A CN 94108013A CN 1050935 C CN1050935 C CN 1050935C
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layer
palladium
thickness
nickel
lead frame
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CN1103204A (zh
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J·A·阿比斯
I·V·卡迪扎
E·J·库德拉克
J·J·梅桑诺
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Nokia Bell Labs
AT&T Corp
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AT&T Bell Laboratories Inc
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    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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    • Y10S428/922—Static electricity metal bleed-off metallic stock
    • Y10S428/9265—Special properties
    • Y10S428/929—Electrical contact feature
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/12—All metal or with adjacent metals
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    • Y10T428/12771—Transition metal-base component
    • Y10T428/12861—Group VIII or IB metal-base component
    • Y10T428/12875—Platinum group metal-base component
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
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    • Y10T428/12771—Transition metal-base component
    • Y10T428/12861—Group VIII or IB metal-base component
    • Y10T428/12889—Au-base component

Abstract

带引线架的封装器件、引线架及含基底金属及其上的镀层、镍层上的复合金属保护层的制品。复合层包括自镍层起依次为钯或软金沉积层、钯镍合金层、钯层及金层。钯或软金沉积层起接合层作用，并促进后续层减少孔隙度。Pd-Ni层对基底金属离子起陷阱作用，Pd层对来自Pd-Ni合金层的Ni离子起陷阱作用。外金层协作增强Pd层质量。软金沉积层上的Pd1～5微英寸、Pd-Ni合金层4～100微英寸、Pd层1～100微英寸、而外金层1～100微英寸。

Description

提供和集成电路的电接触的引线架和集成电路封装
本发明涉及一种用于提供和集成电路器件的电接触的引线架。
将集成电路(IC)单元和引线架密封于保护外壳中的集成电路(IC)器件被广泛用于包括消费电子设备、家用器具、计算机、汽车、电信、遥控和军用设备等各种产品中。IC单元包含集成电路芯片和在塑料或陶瓷基底上包括一个或多个IC芯片和其它电子元件的混合集成电路组件。
一种将IC单元电连接到IC器件的电路外的措施采用引线架的形式。引线架是由一种高导电的材料，诸如铜、铜合金或铁镍合金制成的，把一金属半成品冲压或刻蚀成限定着安装IC单元的中心面积的多根引线。一般的引线架包括一个安装座和多根多接近安装座的位置向外延伸的分离的引线件。在没有安装座的那些情况下，IC单元是由引线端头支撑的，在形成引线时，或使引线端紧靠IC单元，或处于IC单元隔开的位置，或使引线端与IC单元的周边相重叠。
一般来说，在引线架的表面上用常规方法镀上一层镍。这意在把镍镀层作为铜扩散以及在引线架表面形成活性铜产物，如氧化铜、硫化铜的阻挡层。可惜，厚度小于400微英寸(10.2μm)的镍层含有许多孔隙，透过孔隙会发生铜到引线架表面的迁移或扩散。然而，厚度大于400微英寸的层当引线最终弯曲时往往会断裂。
通过在镍层顶上淀积一薄层钯或钯/镍合金试图消除或至少减小铜穿过400微英寸厚的镍层的扩散效应(参见欧洲专利申请No.0250146，1987，12，23公开)。然而在引线架上不断出现的铜的锈蚀产物，包括氧化物、硫化物以及其它铜的反应物，会弄脏引线架的表面，降低其可焊性。进一步的试验是通过给铜基镀上多层，包括自铜基向上顺次镀上5微寸(127纳米)厚的的镍沉积(strike)层，3微英寸(76mm)厚的钯/镍合金层，一层镍层和一层钯层来克服这些缺点。镍沉积层和钯/镍合金层是用来作为阻挡铜向引线架表面迁移的阻挡层，以便允许使用薄(小于400微英寸)的镍层。(参见欧洲专利申请No.0335608，1989，10，4公开)。然而，这种复合层也没有生产出能得住器件封装工艺所要求的加工步骤的影响的产品。所以，需要一种能将基底金属完满覆盖起来的涂层或复合涂层。
本发明体现在用引线架封装的器件、引线架以及制造的物品，包括金属基底、在金属基底上的镍层以及在镍层上的复合金属保护层。复合层包括从镍层起按顺序是钯层、或软金沉积沉积层、钯-镍合金层、钯层以及金层。钯或软金沉积层一般当作Ni和Pd-Ni合金层的接合(bonding)(粘接)层，并当作促进后续层降低孔隙度的层，Pd-Ni合金层当作基金属离子的陷阱，Pd层对来自Pd-Ni合金层的镍离子起陷阱作用，而金层协作增强Pd层的质量。各层的厚度足以有效地完成各自根据加工和使用条件而确定的作用。Pd或Au的厚度可沉积垤1-5微英寸、Pd-Ni合金4～100微英寸、Pd1～100微米寸而外金层1～100微英寸。
因此本发明的目的是提供一种能经得住器件封装工艺所要求的加工步骤的影响的引线架。
一种用于提供和集成电路单元的电接触的引线架包括基底金属，在该基底金属上的镍层以及在镍层上沉积的复合金属层，所述复合层包括钯镍合金层，其厚度至少足以减缓基底金属向引线表面的扩散并且，其特征在于，从镍层起依次为内部钯成软金层，所述钯镍合金层镍的重量占10％-90％，外部钯层，和外部金层，其中所述内部钯或软金层的厚度至少为25nm，所述外部钯层的厚度至少为25nm并且所述外部金层的厚度至少为25nm。
图1是个典型的引线架并在其上安装一个IC单元的顶视图；
图2是封装好的器件沿图1的2-2线剖开部位的剖面图；
图3是表示本发明的复合镀层引线的一小段纵向部分剖面的放大示意图；
图4是经250℃5小时热处理之后，对本发明的复合层俄歇(Auger)深度分布分析图；
图5是经250℃ 5小时热处理之后，对无金护层的复合层Auger深度分布分析图。
图1是个典型的引线架10的顶视图，并带有一个集成电路(IC)单元11。引线架包括一个安装座12，在其上接合一个IC单元，以及引线13。挡料条14，在此阶段将引线13连在一起，将封装介质施加于虚线15所示区域上之后，挡料条14被剪掉。
为便于说明，参照一个IC的封装对本发明加以说明，封装介质是一种压塑材料，如环氧树脂。然而本发明也适用于其它的实施方案，如IC单元和引线被密封于陶瓷或陶瓷和金属混合封装之中。
图2中表示封装16的剖面示意图。封装包括IC单元11、安装座12以及多根引线13。用焊料或粘合剂17将IC单元固定在安装座上经导线或键合线18与引线电连接。IC单元11、安装座12、导线18以及靠近安装座的引线部位被密封于模压封装介质19中。引线包括一基底金属20、在基底金属上的镍层21以及在镍层上的保护复合层22。
基底金属20一般是铜或铜合金。铜合金诸如CDA No.102(99.95％的Cu，余量为Ag)，CDA No.103(99.95％的Cu，加上0.001-0.005的P和Au)，No.151(99.9％的Cu，0.1％的Zn)，No.155(97.8的Cu，0.034的Ag，0.058的P，0.11的Mg)，No.194(97.5的Cu，2.35的Fe，0.003的P，0.12的Zn)，以及KLF125(94.55的Cu，3.2的Ni，1.25的Sn，0.7的Si)都是用于引线架的代表材料。其它一些合金，诸如铁-镍合金也可用作基底材料。
上面提及的EP专利申请一般涉及金属涂层，适用于防止至少降低铜或铜制品自基底金属向引线架的引线表面的扩散。然而，在引线表面有镍和镍产物，如氧化镍存在，从可焊性观点来看，比铜和铜产物存在更为严重。在表面只有5％原子百分数或更少的镍存在对表面的可焊性有不利的影响。由于包括高温和氧化条件的各工艺步骤的作用使镍和镍产物扩散到上覆层并与上覆层的金属成分相互作用。镍产物，如氧化镍妨碍着焊接和接合工艺。此外，难以用通用的酸性物清洗去掉。
在镍层21上淀积有多层结构总厚约10微英寸的复合保护层22，能防止，至少大致减少铜和铜产物、镍和镍产物迁移到引线的外表面，使问题得以解决。图3表示的是一段引线13剖面的放大示意图。复合层22包括从镍层21向上依次为钯或软金沉积层23、钯镍合金层24、钯层25以及金层26。所淀积的复合层的总厚度从约10～300微英寸变化，以及更厚些。镍层上的复合层的厚度一般在20～200微英寸(510-5100nm)范围。
钯或软金沉积层23作为镍和钯镍合金层之间的接合(粘接)层，淀积厚度在1～5微英寸(25～102nm)的范围。薄于1微英寸的层可能不足以达到接合的目的，而5微英寸或更厚些的层不会增添任何好处。Pd或Au沉积层是低孔隙度的层，除它的键合特性外，还有助于增进后续层低孔隙度的生长，并有助于减少铜和镍向上层的潜在的扩散。最好用本文中引用的1993.1.12授予J.A.Abys等人的美国专利No.4,178,475中介绍的钯触击电镀溶液淀积Pd沉积层。淀积软金的成分和电镀的条件之实例在Frank H.Reed和WilliamGoldie合著的一本书中已有介绍(＂Gold Plating Technology＂，Electrochemical Publication Limited，8 Barns Street，Ayr，Scotland，Third printing 1987，pages 26 and 46。)
钯镍合金层24的淀积厚度在4-100微英寸(127～2540nm)范围。生长在钯或软金沉积层上的钯镍合金层是一种低孔隙度层。该层的主要目的是防止，至少减少铜、铁和镍及其产物，如氧化物扩散到引线的表面，特别是扩散到待焊接的表面。薄于4微英寸的层可能不足以阻挡铜和镍扩散穿过该层。而厚于100微英寸的层也不会增加任何额外的好处。合金是Pd-Ni合金，镍的含量为10～90％重量百分数，最好在10～30wt％范围。最好用钯电镀溶液淀积合金层，披露于1990.3.27授予J.A.Abys等人的美国专利US-4,911,798和US-4,911,799，两项专利均被本文引用。
钯层25的淀积厚度在1～100微英寸(25～2540nm)范围。该层的主要目的是进一步降低底层孔隙度的作用，并防止或至少减低镍从钯镍合金层24向待焊表面的扩散。薄于1微英寸的层可能不足以阻挡镍来自钯镍合金层的扩散，而厚于100微英寸的层也不会增添任何额外的好处。该层的厚度根据Pd-Ni合金层的厚度和Ni含量而定。合金层内的镍含量越高，Pd层应该越厚，以防止，至少减缓Ni进入和穿过Pd层的扩散。最好用钯电镀溶液淀积合金层，在1990.3.27授予J.A.Abys等人的美国专利US-4,911,799中披露，亦被本文引用。
金层26的淀积厚度在1～100微英寸(25～2540nm)的范围。薄于1微英寸的层可能不足以与复合层的其它层相结合提供所要求的扩散阻挡作用，而厚于100微英寸的层可能只增加额外的昂贵金的花费，而对于外表面的可焊性、焊料可润性以及可键合性不会增添任何额外的好处。从经济上考虑，在很多场合可将使用昂贵的金层保持尽可能的薄，如1～2微英寸(25～51nm)。用任何常规用于镀金的溶液来淀积金层。最好将金层作为一软金沉积层而淀积。用于淀积软金的成分和电镀条件之实例披露于Frank H.Reed和William Goldie合著的一书中，＂Gold Plating Technology＂，ElectrochemicalPublication Limited，8 Barns Street，Ayr，Scotland，Third printing1987，pages 26 and 46。
当采用250℃和低些的温度加工复合层时，可以淀积的厚度至少为1微英寸的Pd或Au沉积层、厚度不薄于4微英寸的Pd-Ni合金、厚度至少为1微英寸最好至少为3微英寸的Pd以及厚度至少为1微英寸的外金层。对工艺要求温度达到450C的情况，Pd或Au沉积层可在1～5微英寸的范围内，而厚度最薄的Pd-Ni合金层、Pd层以及外金层均可增加至20～30微英寸的范围。
在完成金属淀积之后，引线架经受IC单元固定工艺。用公知的方法，如焊或粘，将IC单元11固定在引线架10的安装座12上。用导线或键合线18完成IC单元与引线13之间的电连接。重要的是引线架表面对导线应是可接合的。一个没有有害的铜和/或镍的产物的可焊表面，也将适合于导线的键合。带有有害的铜和镍的产物的表面不可能适合于接合，或是接合性很差，所以不可能建立起可行的连接，即使建立了连接，在运行中也会逐渐变为断路。若在接合部位引线的外表面有一薄层氧化镍，形成的接触性能特差。在IC单元固定、导线接合和焊接之前，用清洗法去掉铜的产物，如氧化物、硫化物。然而，这种镍的副产物如氧化镍其附着力十分强，因而用一般的清洗溶液几乎去不掉。
于是，将每个组合件放在模压设备中，注入塑封材料，包围每个IC单元和毗邻的引线部分，形成外IC单元封装。从模压设备取出组合件之后，将引线端与引线架分离开，再去掉引线间的埂带，使模压好的IC封装与引线架分开。然后，将各引线弯曲成所要的形状，如鸟翼状、“J”或对接状。用酸洗净模压复合体所露出的引线部位，再把它焊到装配板上的焊点上。在一种情况下，将清洁的引线放在固定板上与焊块或焊膏接触，用回流法，将它焊在板上的焊点上。在另一种情况下，将清洁的引线浸在熔融的焊料池中，然后把它放在装配板上与涂焊剂的接线焊点接触。
为在IC单元和安装板之间获得可靠的连接，引线绝对应该有可焊的表面。这意味着，这些待固定到板上焊点上的引线部位的表面应能接收基本上连续的焊料涂层。可把被焊料涂层覆盖了95％或95％以上的待焊面积的表面看作是可焊的。另外，该表面应有以低数目孔隙/厘米2表示的焊接覆盖率，如低于28～30孔隙/厘米2，最好低于25孔隙/厘米2。
在制造封装器件的工艺中，引线架经受数道工艺操作步骤，这些步骤促进了氧化、互扩散掺杂、被蒸汽沾污、断裂以及表面损伤污染。工艺步骤包括注塑热塑材料以形成塑料框架(150℃，30分钟)，电路连接，支撑杆固定(150℃，30分钟)，修整并形成引线，氧等离子体清洗或激光H2O2清洗以去掉任何有机杂质，器件固定，包括管芯键合环氧树脂固化(165℃，1小时)外壳固定(165℃，1小时)以及老化(125℃/24小时)以便结构应力释放以及牢固性测试。这些工艺在本领域中是公知的，因而无须进一步详述。塑料模压封装的形成和焊接步骤可能需要高至250℃的温度。用低熔点玻璃的陶瓷封装工艺可能超过400℃，处于400～800℃的温度范围0.5小时或更长。这些工艺步骤及不利的热和氧化对引线架材料的综合影响导致引线架可焊质量的下降。
为了测定引线架表面是否适合于可靠的连接，对有或无封装材料的引线架作可靠性试验。试验之一是军用规格883C-方法2003，有资格用作操作方法的规范。这标准包含在95℃95％相对湿度蒸汽老化4，8或16小时。这假定了模拟储存期限至少为6个月。然后，对试样施加非活化松香焊剂涂至露出的金属引线，亦浸泡在250℃的焊料中5秒钟。然后在10×放大率下估计试样对焊料的覆盖率。可焊性合格的涂层必经有至少95％的高质量平滑焊料覆盖率，其孔隙率低于28-30孔隙/厘米2，最好低于25孔隙/厘米2。虽然开拓了典型的焊料涂覆法，在测试未涂覆焊料的衬底中，同样也可使用蒸汽老化试验方法。如果被测试的表面能接收焊料涂层，可进行该试验。用SO2蒸汽进行孔隙度测试，如ASTM B799-88(1988，11p463-465)中所述。
因许多应用包括有涂层引线架的热辐照，在热老化的情况下各层间的热扩散如果下层金属扩散到较贵重的表面层内，如镍扩入金中，会引起表面质量的下降。所以，除蒸汽老化外，还希望对电镀的表面进行热老化。目前，尚无标准化的热老化规格。为了判断在各种热条件下本发明涂层对可焊性的稳定性，将涂层置于150℃、200℃和250℃做1、2和5小时，以及在400℃做1小时的热测试。
对有20微英寸厚的镍层并涂有总厚为11微英寸的复合层的铜板进行热测试。复合层包括自镍层起依次为3微英寸的Pd沉积层，4微英寸的Pd/Ni(80/20)合金层，3微英寸Pd层以及1微英寸的软金顶层。在刚电镀后，试样具有98％以上的焊料覆盖率。当将试样置于200℃做1、2和5小时以及置于250℃做2和5小时热处理时，试样仍保持了原来的＞98％的焊料覆盖率。当将试样做蒸汽老化(95℃、95％相对湿度)8小时时，焊料覆盖率仍保持高达＞98％。
为了比较，对有厚度相同的Pd沉积层、Pd-Ni合金和Pd，但无外软金顶层的试样做测试。在电镀后，这些试样的标称的焊料覆盖率为＞98％；当置于200℃辐照1和2小时时，额定值大于98％；当置于200℃辐照5小时时，额定值大于95％；但当以250℃的温度辐照2和5小时时，下降到小于90％的不合格的值。
在图4和图5中表示一复合层的Auger深度分布分析图。该复合层有多层成分，自20微英寸的镍层起依次为3微英寸的Pd沉积层、4微英寸Pd/Ni合金(80/20)层、3微英寸Pd层以及1微英寸的软金层。使复合层在250℃经受5小时的热处理。在热处理之后以20纳米/分的速率进行溅射分析。由图4可见，在溅射3.5分钟期间在Pd层未探测到镍，这大约对应70nm(近似为3英寸)的Pd层厚度。图5展示的是当对带有Pd沉积层、Pd-Ni合金层及Pd层，其厚度与上述相同，但没有外软金层的复合层做分析时，在Pd层表面出现了Ni。这样，在250℃经5小时，镍将从Pd-Ni合金层扩散到2-3微英寸厚的Pd层表层，并影响到可焊性。然而，在Pd层顶的1微英寸金层防止了这种扩散，并提供理想的可焊性。当使有和无外金层的复合层经受再高的高温时，会出现类似的情形。例如，在另一实验中，在450℃经1小时后，镍穿透了20微英寸的Pd和3微英寸的金。在20微英寸钯层顶上施加20微英寸的金可消除这种穿透并达到完满的可焊性。作为比较，在450℃只热辐照10分钟后，在Ni层顶上元Pd沉积层、Pd-Ni合金层及Pd层，仅靠100微英寸的金本身不能防止可焊性下降。
在另一特定实施例中，在Ni层19上依次淀积复合层20的各个层。在20微英寸(约510nm)厚的Ni层上淀积总厚约12微英寸(约310nm)的复合层。
                      表I
              1          2          3
层别                  厚度(微英寸)
Pd沉积层      1          1          2
pd/Ni合金     7.5        7.5        7.5
Pd            1          2          1
Au沉积层      2          1          1
下列分层的保护层，可被看作是代表已有技术涂层的组合4，被用作对照组：
层别                厚度(微英寸)
Pd/Ni沉积层              3
镍                       20
Pd                       3对试样在电镀后和随后8小时蒸汽老化后的可焊性进行测试。在从用于可焊性测试的同一板上切下的段上实行孔隙测试。复合层的可焊性和孔隙度的特性数据列于表II。
                      表II
组合号               1      2     3      4
电镀后覆盖率％       99     99    98     97
蒸汽老化后覆盖率％   98     97    97     85
孔隙度孔/厘米2      11     13    23     7100
对于本领城的技术人员容易想到更多的优点和改型。所以，本发明从更广泛的意义上说不限于特定的细节、代表性的器件以及表明和介绍过的解释实例。因而无须脱离普通发明概念的被所附权利要求书及其等同物所限定的精神和范围，即可做出各种各样的改型。

Claims (8)

1.一种提供和集成电路器件的电接触的引线架包括基底金属，在该基底金属上的镍层以及在镍层上沉积的复合金属层，所述复合层包括钯镍合金层，其厚度至少足以减缓基底金属向引线表面的扩散并且，其特征在于，从镍层起依次为内部钯成软金层，所述钯镍合金层镍的重量占10％-90％，外部钯层，和外部金层，其中所述内部钯成软金层的厚度至少为25nm，所述外部钯层的厚度至少为25nm并且所述外部金层的厚度至少为25nm。
2.权利要求1的引线架，其中所述复合层沉积的总厚度为255到7620nm。
3.权利要求1的引线架，其中所述复合层沉积的最小厚度至少为250nm。
4.权利要求1的引线架，其中所述钯镍合金层的厚度至少为100nm。
5.权利要求1的引线架，其中为了在250℃及更低的温度下使用，所述内部钯层的厚度至少为75nm，所述钯镍合金层的厚度至少为100mm，所述外部钯层的厚度至少为75nm，并且所述外部金层的厚度至少为25nm。
6.权利要求1的引线架，其中为了在450℃及更高的温度下使用，所述内部钯或软金层在25nm-125nm的范围内，而所述钯镍合金层，所述外部钯层和所述外部金层的厚度每个在至少500-760nm的范围内。
7.权利要求1的引线架，其中所述基底金属包括铜而所述钯镍合金包括20重量百分比的镍。
8.IC封装包括至少一个IC单元，而根据权利要求1-7任意之一的引线架被封在保护封装内。
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