JP4136845B2 - 半導体モジュールの製造方法 - Google Patents
半導体モジュールの製造方法 Download PDFInfo
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- JP4136845B2 JP4136845B2 JP2003298057A JP2003298057A JP4136845B2 JP 4136845 B2 JP4136845 B2 JP 4136845B2 JP 2003298057 A JP2003298057 A JP 2003298057A JP 2003298057 A JP2003298057 A JP 2003298057A JP 4136845 B2 JP4136845 B2 JP 4136845B2
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- Prior art keywords
- melting point
- joining
- electrodes
- point metal
- low melting
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Description
前記第1接合工程、第2接合工程及び第3接合工程の少なくとも1つの工程において、金属箔の片面あるいは両面に低融点金属層をあらかじめ形成した後、接続されるべき1対の電極を対向させて、この1対の電極間に前記金属箔を介装し、前記1対の電極を少なくとも低融点金属が溶融する温度で加熱加圧し、前記低融点金属層を前記1対の電極中に固液拡散させることによって、前記1対の電極を接合することを特徴とする。
本発明の半導体モジュールの製造方法の第1及び第2において、前記低融点金属層は、融点が220℃以下の2元以上の合金を形成できる、少なくとも2種類以上の金属を2層以上に積層し、該積層した金属層を予備加熱して反応させて合金層とすることにより形成することが好ましい。
本発明の半導体モジュールの製造方法の第3は、回路基板上に形成された第1回路電極と、表裏両面に素子電極が形成された半導体素子の前記裏面側素子電極とを接合する第1接合工程と、前記半導体素子の前記表面側素子電極と、線状あるいは板状の接続部材の一端とを接合する第2接合工程と、前記接続部材の他端と、前記回路基板上に形成された第2回路電極とを接合する第3接合工程とを含む半導体モジュールの製造方法であって、前記第1接合工程、第2接合工程及び第3接合工程の少なくとも1つの工程において、接続されるべき1対の電極の少なくとも一方に、融点が220℃以下の2元以上の合金を形成できる、少なくとも2種類以上の金属を2層以上に積層し、該積層した金属層を予備加熱して反応させて合金層とすることにより、低融点金属層をあらかじめ形成した後、前記1対の電極を対向させて、少なくとも低融点金属層が溶融する温度で加熱加圧し、前記低融点金属層を前記1対の電極中に固液拡散させることによって、前記1対の電極を接合することを特徴とする。
これによれば、合金層における合金組成や供給量のバラツキがなくなるので、低温での安定した拡散接合が可能となり、信頼性の高い接合部を得ることができる。
加熱加圧の条件等は、接合される電極材料や低融点金属の材料によって適宜選択することができ、上記の第1接合工程と異なる条件であってもよい。
図1に示す工程にしたがって、以下の半導体モジュールを製造した。
参考例1において、低融点金属層を、単一金属層として、Sn層0.48μm、In層0.52μmの合計1μmとなるようにスパッタリングにより順に積層して形成し、第1〜3接合工程のそれぞれにおいて、温度120℃で10秒間の予備加熱を行い、Sn層とIn層とを固溶させてSnInの合金層を得た後、第1〜3接合工程を行った以外は、参考例1と同様の条件で半導体モジュールを製造した。
11:表面素子電極
12:裏面素子電極
20、21:低融点金属層
30:回路基板
31:第1回路電極
32:第2回路電極
35:金属箔
40:リードフレーム
50:加熱加圧装置
Claims (9)
- 回路基板上に形成された第1回路電極と、表裏両面に素子電極が形成された半導体素子の前記裏面側素子電極とを接合する第1接合工程と、前記半導体素子の前記表面側素子電極と、線状あるいは板状の接続部材の一端とを接合する第2接合工程と、前記接続部材の他端と、前記回路基板上に形成された第2回路電極とを接合する第3接合工程とを含む半導体モジュールの製造方法であって、
前記第1接合工程、第2接合工程及び第3接合工程の少なくとも1つの工程において、接続されるべき1対の電極の少なくとも一方に、低融点金属層をあらかじめ形成した後、前記1対の電極を対向させて、この1対の電極間に金属箔を介装し、少なくとも低融点金属が溶融する温度で加熱加圧し、前記低融点金属層を前記1対の電極中に固液拡散させることによって、前記1対の電極を接合することを特徴とする半導体モジュールの製造方法。 - 回路基板上に形成された第1回路電極と、表裏両面に素子電極が形成された半導体素子の前記裏面側素子電極とを接合する第1接合工程と、前記半導体素子の前記表面側素子電極と、線状あるいは板状の接続部材の一端とを接合する第2接合工程と、前記接合部材の他端と、前記回路基板上に形成された第2回路電極とを接合する第3接合工程とを含む半導体モジュールの製造方法であって、
前記第1接合工程、第2接合工程及び第3接合工程の少なくとも1つの工程において、金属箔の片面あるいは両面に低融点金属層をあらかじめ形成した後、接続されるべき1対の電極を対向させて、この1対の電極間に前記金属箔を介装し、前記1対の電極を少なくとも低融点金属が溶融する温度で加熱加圧し、前記低融点金属層を前記1対の電極中に固液拡散させることによって、前記1対の電極を接合することを特徴とする半導体モジュールの製造方法。 - 前記低融点金属層は、融点が220℃以下の2元以上の合金を形成できる、少なくとも2種類以上の金属を2層以上に積層し、該積層した金属層を予備加熱して反応させて合金層とすることにより形成する請求項1または2に記載の半導体モジュールの製造方法。
- 回路基板上に形成された第1回路電極と、表裏両面に素子電極が形成された半導体素子の前記裏面側素子電極とを接合する第1接合工程と、前記半導体素子の前記表面側素子電極と、線状あるいは板状の接続部材の一端とを接合する第2接合工程と、前記接続部材の他端と、前記回路基板上に形成された第2回路電極とを接合する第3接合工程とを含む半導体モジュールの製造方法であって、
前記第1接合工程、第2接合工程及び第3接合工程の少なくとも1つの工程において、接続されるべき1対の電極の少なくとも一方に、融点が220℃以下の2元以上の合金を形成できる、少なくとも2種類以上の金属を2層以上に積層し、該積層した金属層を予備加熱して反応させて合金層とすることにより、低融点金属層をあらかじめ形成した後、前記1対の電極を対向させて、少なくとも低融点金属層が溶融する温度で加熱加圧し、前記低融点金属層を前記1対の電極中に固液拡散させることによって、前記1対の電極を接合することを特徴とする半導体モジュールの製造方法。 - 前記低融点金属層が、SnIn又はSnBiである請求項1〜4のいずれか1つに記載の半導体モジュールの製造方法。
- 前記接合時の加熱温度が、前記低融点金属層の融点より0〜100℃高い温度である請求項5に記載の半導体モジュールの製造方法。
- 前記加熱加圧は、前記低融点金属層が、前記1対の電極間に中間合金層を形成するまで行なう請求項1〜6のいずれか1つに記載の半導体モジュールの製造方法。
- 前記接続部材がリードフレームである請求項1〜7のいずれか1つに記載の半導体モジュールの製造方法。
- 前記1対の電極表面の表面粗さRaが0.4〜10μmの粗面である請求項1〜8のいずれか1つに記載の半導体モジュールの製造方法。
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