JPS5595333A - Preparation of semiconductor device - Google Patents

Preparation of semiconductor device

Info

Publication number
JPS5595333A
JPS5595333A JP221279A JP221279A JPS5595333A JP S5595333 A JPS5595333 A JP S5595333A JP 221279 A JP221279 A JP 221279A JP 221279 A JP221279 A JP 221279A JP S5595333 A JPS5595333 A JP S5595333A
Authority
JP
Japan
Prior art keywords
layer
base
layers
brazing alloy
melted
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP221279A
Other languages
Japanese (ja)
Inventor
Tetsuo Saito
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP221279A priority Critical patent/JPS5595333A/en
Publication of JPS5595333A publication Critical patent/JPS5595333A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83193—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases

Abstract

PURPOSE: To keep a certain specified space between an element and a base without difficulty by a method wherein a brazing alloy is provided on each metal layer of one main surface of a semiconductor element and another of a base, and they are heat-pressed in such a way that the brazing alloy with a high melting temperature is sandwiched in between them.
CONSTITUTION: Ni layers 11, 21 and Sn layers 12, 22 are put one after another on the under main surface of a semiconductor element 1 and the upper surface of a base 2a, respectively. Next a brazing alloy layer 3 in the form of a plate composed of Pb-1%Sn with a melting point of 327°C is sandwiched in between these layers above. The thickness of the layer 3 is arranged so that it corresponds to a space desired. Next if heat treatment is added in a reducing atmosphere, only Sn is melted at first, and partly diffused in the Ni layer while eutectic alloys 12, 23 are produced on the boundary surface touching the layer 3, then diffused layers 211, 212 are produced. Like this, the element and the base are solidly connected, and the brazing alloy 3 with a high melting point is not melted, so that the thickness desired can be maintained.
COPYRIGHT: (C)1980,JPO&Japio
JP221279A 1979-01-16 1979-01-16 Preparation of semiconductor device Pending JPS5595333A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP221279A JPS5595333A (en) 1979-01-16 1979-01-16 Preparation of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP221279A JPS5595333A (en) 1979-01-16 1979-01-16 Preparation of semiconductor device

Publications (1)

Publication Number Publication Date
JPS5595333A true JPS5595333A (en) 1980-07-19

Family

ID=11523036

Family Applications (1)

Application Number Title Priority Date Filing Date
JP221279A Pending JPS5595333A (en) 1979-01-16 1979-01-16 Preparation of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5595333A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0574824A (en) * 1991-08-26 1993-03-26 Mitsubishi Electric Corp Manufacture of semiconductor device and semiconductor device
JPWO2005086218A1 (en) * 2004-03-02 2008-01-24 富士電機ホールディングス株式会社 Manufacturing method of semiconductor module
US7670879B2 (en) 2002-08-30 2010-03-02 Fuji Electric Holdings Co., Ltd. Manufacturing method of semiconductor module including solid-liquid diffusion joining steps

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0574824A (en) * 1991-08-26 1993-03-26 Mitsubishi Electric Corp Manufacture of semiconductor device and semiconductor device
US7670879B2 (en) 2002-08-30 2010-03-02 Fuji Electric Holdings Co., Ltd. Manufacturing method of semiconductor module including solid-liquid diffusion joining steps
JPWO2005086218A1 (en) * 2004-03-02 2008-01-24 富士電機ホールディングス株式会社 Manufacturing method of semiconductor module
JP4508189B2 (en) * 2004-03-02 2010-07-21 富士電機ホールディングス株式会社 Manufacturing method of semiconductor module

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