JPS54133071A - Manufacture for semiconductor device - Google Patents
Manufacture for semiconductor deviceInfo
- Publication number
- JPS54133071A JPS54133071A JP4098778A JP4098778A JPS54133071A JP S54133071 A JPS54133071 A JP S54133071A JP 4098778 A JP4098778 A JP 4098778A JP 4098778 A JP4098778 A JP 4098778A JP S54133071 A JPS54133071 A JP S54133071A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- split
- solder
- manufacture
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/27—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/3201—Structure
- H01L2224/32012—Structure relative to the bonding area, e.g. bond pad
- H01L2224/32014—Structure relative to the bonding area, e.g. bond pad the layer connector being smaller than the bonding area, e.g. bond pad
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Die Bonding (AREA)
Abstract
PURPOSE: To enable no wafer crack in solder welding, no working efficiency decrease in split process and to make excellent the solderability.
CONSTITUTION: At the back of the Si substrate 10, the alloy layer 4 with Ni is provided, and the layer 4 for split part is eliminated in advance. Next, the substrate 10 is dipped in the molten solder vessel and the solder 5 is selectively welded on the alloy layer. The thermal stress in case is split to each element and it is very small as the entire substrate, then the substrate is not cracked and split can completely be made because of no solder between elements.
COPYRIGHT: (C)1979,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4098778A JPS54133071A (en) | 1978-04-06 | 1978-04-06 | Manufacture for semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4098778A JPS54133071A (en) | 1978-04-06 | 1978-04-06 | Manufacture for semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS54133071A true JPS54133071A (en) | 1979-10-16 |
Family
ID=12595770
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP4098778A Pending JPS54133071A (en) | 1978-04-06 | 1978-04-06 | Manufacture for semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS54133071A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5864037A (en) * | 1981-10-13 | 1983-04-16 | Nec Home Electronics Ltd | Manufacture of semiconductor device |
-
1978
- 1978-04-06 JP JP4098778A patent/JPS54133071A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5864037A (en) * | 1981-10-13 | 1983-04-16 | Nec Home Electronics Ltd | Manufacture of semiconductor device |
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