DE4303790A1 - Verfahren zur Erzeugung einer formschlüssigen Verbindung zwischen Halbleiterbauelementen und metallischen Oberflächen von Trägerelementen - Google Patents
Verfahren zur Erzeugung einer formschlüssigen Verbindung zwischen Halbleiterbauelementen und metallischen Oberflächen von TrägerelementenInfo
- Publication number
- DE4303790A1 DE4303790A1 DE4303790A DE4303790A DE4303790A1 DE 4303790 A1 DE4303790 A1 DE 4303790A1 DE 4303790 A DE4303790 A DE 4303790A DE 4303790 A DE4303790 A DE 4303790A DE 4303790 A1 DE4303790 A1 DE 4303790A1
- Authority
- DE
- Germany
- Prior art keywords
- intermediate layer
- semiconductor
- substrate
- melting
- joining surface
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Ceased
Links
Classifications
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K20/00—Non-electric welding by applying impact or other pressure, with or without the application of heat, e.g. cladding or plating
- B23K20/16—Non-electric welding by applying impact or other pressure, with or without the application of heat, e.g. cladding or plating with interposition of special material to facilitate connection of the parts, e.g. material for absorbing or producing gas
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Description
Die Erfindung betrifft ein Verfahren zur Erzeugung einer
formschlüssigen Verbindung zwischen metallischen Oberflächen von
Halbleitern und Trägerelementen, insbesondere zur Montage von
Halbleiter-Chips auf Substraten sowie in elektronischen Bauelementen und
Schaltungen.
Es ist bekannt, Halbleiterbauelemente durch Löt- oder Klebverfahren zu
montieren. Während es bei derartigen, durch Löten hergestellten
Verbindungen von Nachteil ist, daß diese keiner hohen
Temperaturbelastung und nur relativ wenigen Temperaturwechseln
ausgesetzt werden können, ist es bei geklebten Verbindungen nachteilig,
daß diese nur eine begrenzte Wärmeleitfähigkeit sowie eine relativ
geringe Feuchtbeständigkeit aufweist.
Der Erfindung liegt daher die Aufgabe zugrunde, ein Verfahren zur
Erzeugung einer zuverlässigen formschlüssigen Montage-Verbindung für
metallische Oberflächen von Halbleiterkontakten zu schaffen, die eine
lange Lebensdauer bei hohen Temperaturen aufweist und eine große Anzahl
von Temperaturwechseln übersteht, sowie eine hohe thermische
Leitfähigkeit besitzt.
Die Aufgabe wird erfindungsgemäß durch folgende Verfahrensschritte
gelöst:
- a) zwischen einer metallischen Oberfläche eines Halbleiterbauelements und einem Substrat mit Metalloberfläche wird eine Zwischenschicht aus einem gegenüber dem Bauelement und Substrat niedrigschmelzendem Metall angeordnet;
- b) die höherschmelzende Halbleitermetallisierung, die niedrigschmelzende Zwischenschicht und die höherschmelzende Substratmetallisierung werden miteinander in Berührung gebracht und unter einem vorgegebenen Temperatur- und Anpreßduckverlauf auf bzw. über die Schmelztemperatur der Zwischenschicht derart erwärmt, daß die flüssige Zwischenschicht die Fügeoberflächen von Halbleiter und Substrat benetzt;
- c) daß durch Diffusion der verschwindenden flüssigen Zwischenschicht in die Halbleitermetallisierung und Substratmetallisierung eine interme tallische Phase vom Material der Zwischenschicht und der zu fügenden Teile gebildet wird; und
- d) daß abschließend durch Abkühlung und Erstarrung während des vorge gebenen Temperatur- und Anpreßdruckverlaufes die formschlüssige Verbindung zwischen Halbleiter und Substrat hergestellt wird, deren Schmelztemperatur höher ist, als die der ursprünglichen Zwischen schicht.
Das erfindungsgemäße Verfahren, welches als Isotherme Erstarrung
bezeichnet wird, kann als Fügeverfahren nicht eindeutig den Löt- oder
den Schweißprozessen zugeordnet werden. Verfahrensprinzip ist die
Erzeugung einer formschlüssigen Verbindung zwischen zwei Fügepartnern
aus höherschmelzenden Metallen unter Zuhilfenahme einer verschwindenden
flüssigen Zwischenschicht aus einem niedrigschmelzenden Metall.
Das erfindungsgemäße Verfahren bringt folgende Vorteile mit sich:
- - Kontaktierung bei niedrigen Temperaturen von 160 bis 450°C, die dem Löten entsprechen.
- - Hohe Temperaturstabilität der Verbindungen, da die Schmelztemperatur Ts intermetallischer Phasen um 100 bis 300 K über der Fügetemperatur liegt.
- - Große Festigkeit der Verbindungen wegen geringer Verformbarkeit der intermetallischen Phasen.
- - Geringe mechanische Belastung der Bauteile durch geringen Anpreßdruck.
Die Suche nach geeigneten binären Systemen für das obige Verfahren,
bestehend aus einem hoch- und einem niedrigschmelzenden Metall, wurde
unter den Randbedingungen der Montage von Halbleiterbauelementen
vorgenommen, wobei folgende Kriterien beachtet wurden:
- - geringster Schmelzpunkt des Systems Ts < 400°C.
- - Bildung von hochlegierten Mischkristallen bzw. intermetallischen Phasen.
- - Vollständigkeit des Systems
und führte dazu, daß gemäß Ausgestaltungen des erfindungsgemäßen
Verfahrens als niedrigschmelzende Zwischenschicht Metalle mit einem
Schmelzpunkt unter 450°C verwendet werden, wie Bi, Cd, Ga, In, Pb, Sn
oder Zn, und daß als höherschmelzende Halbleitermetallisierungen und
Substratmetallisierungen oder Kontakte Metalle wie Ag, Au, Cu, Co, Fe,
Mn, Ni, Pd, Pt, Ir, Os, Re, Rh oder Ru verwendet werden.
Weitere Ausgestaltungen des erfindungsgemäßen Verfahrens gehen dahin,
daß die Schmelztemperatur und der vorgegebene Anpreßdruck mittels einer
Druck-Heiz-Zeit-Vorrichtung aufgebracht werden, wobei eine Vorrichtung
mit einer Anpreßfläche von in der Größe des Halbleiterbauelements 0,5 ×
0,5 bis ca. 15 × 15 mm2, deren Temperaturbereich von 100 bis 500°C um
± 3K regelbar ist, verwendet werden kann, oder dahin, daß die
Schmelztemperatur in einem Ofen bei gleichzeitiger Aufbringung des
Anpreßdrucks mittels einer mechanischen Druckvorrichtung aufgebracht
wird.
Das erfindungsgemäße Verfahren mit seinen erfinderischen
Ausgestaltungen eignet sich in vorteilhafter Weise zur Herstellung
von Verbindungen zwischen Dünnschichten. Hierbei erfolgt das Wachstum
der gebildeten intermetallischen Phasen in Dünnschichtpaaren nicht in
ebener Front, sondern beispielsweise in Form noppenartiger (CuSn) oder
stengeliger (NiSn) Einkristalle. Es wird näherungsweise durch ein
parabolisches Gesetz in Form
di = k × tn
beschrieben, wobei die Werte von n für Cu6Sn5 bei n = 0,2 bis 0,4, bei
Ni3Sn4 bei ca. 0,5 liegen. Die Abweichungen vom Gesetz werden durch
überlagerte Volumen- und Korngrenzendiffusion bedingt.
Zur Herstellung von formschlüssigen Verbindungen zwischen
Halbleiterbauelementen und Substraten sind beispielsweise zwei
verschiedene Systeme verwendbar. Das erste System weist ein Substrat
mit einer metallischen Fügeoberfläche aus Silber sowie eine
Halbleiteroberfläche aus Silber und eine Zwischenschicht aus Zinn auf.
Hingegen besteht das zweite System aus einem Substrat mit einer
Fügeoberfläche aus Gold, einer Halbleiteroberfläche aus Gold sowie einer
Zwischenschicht aus Indium. Die Herstellung erfolgt nach den
obengenannten Verfahrensschritten a bis d, wobei das Substrat, die
Zwischenschicht und der Halbleiter auf eine der Löttemperatur
entsprechende Schmelztemperatur der jeweiligen Zwischenschicht in einem
Bereich von 160 bis 350°C für einen Zeitraum von 0,5 bis 5 min erwärmt
werden, und wobei für diesen Zeitraum die vorgegebenen Anpreßdrücke
zwischen Verbinder, Zwischenschicht und Kontakt zwischen 0,5 und 50
Newton pro mm2 Fügefläche betragen.
Eine Ausgestaltung der Erfindung besteht darin, daß unter der
Zwischenschicht eine dünne Diffusionssperrschicht abgeschieden wird,
welche eine Reaktion zwischen Trägermetall und der Zwischenschicht
während der Lagerung verhindert und somit eine Verbesserung der
Lagerfähigkeit erlaubt. Diese Zwischenschicht kann entweder auf dem
Substrat oder vorzugsweise auf dem Halbleiter oder auf beiden Fügeteilen
angebracht werden.
Hierbei wird als erfinderische Weiterbildung die Verwendung einer 3 bis
10 µ dicken Silberschicht auf den Oberflächen von Halbleiter sowie
Substrat sowie die Verwendung einer Schichtdicke der Zinn-
Zwischenschicht, die 1 bis 2 µ beträgt, angesehen.
Anstelle der Silberschicht auf den Oberflächen von Halbleiter und
Substrat kann auch eine Goldschicht auf den Oberflächen vorgesehen sein,
wobei eine Indium-Zwischenschicht mit 1 bis 2 µ Schichtdicke verwendet
wird.
Eine besondere Ausgestaltung der Erfindung ist dadurch gekennzeichnet,
daß die Zwischenschicht aus Zinn bzw. Indium auf die Fügeoberfläche des
Substrats aus Silber oder aus Gold (gemäß Unteranspruch 12) oder aber auf
die Fügeoberfläche des Halbleiters aus Silber oder aus Gold (gemäß
Unteranspruch 16) lokal aufgebracht wird.
So ist eine lokale Aufbringung der Zwischenschicht mittels
Photolacktechnik (Photoresisttechnik) oder durch eine Bedampfung oder
durch Galvanik mittels Maskentechnik auf die Fügeoberfläche des
Halbleiters oder des Substrats möglich.
Die Erfindung wird im folgenden anhand eines in einer Zeichnung
dargestellten Ausführungsbeispiels mit einem Cu-Su-Cu-Systern näher
beschrieben.
Es zeigen:
Fig. 1 metallische Oberflächen als Fügeflächen je eines Halbleiters
und eines Substrats im Abstand voneinander in Seitenansicht;
Fig. 2 die metallischen Oberflächen gem. Fig. 1 mit einer den Abstand
zwischen den Oberflächen ausfüllenden Lötschicht;
Fig. 3 die im Abstand voneinander angeordneten metallischen Ober
flächen gem. Fig. 1 mit intermetallischen Phasen in der
Zwischenschicht, die noch eine geschmolzene Lotschicht enthält;
Fig. 4 die im Abstand voneinander angeordneten Oberflächen gem. Fig. 1
mit fortgeschrittener metallischer Phase in der Zwischenschicht
und
Fig. 5 die im Abstand voneinander angeordneten Oberflächen gem. Fig. 1
mit einer Festkörperverbindung durch die Zwischenschicht.
Zwei metallische koplanare Oberflächen 1, 2 aus Kupfer von zwei nicht
näher dargestellten Halbleitern oder anderen Trägerelementen werden im
Abstand voneinander angeordnet. Auf eine der beiden Oberflächen wird
eine dünne Schicht 3 aus Zinn aufgebracht. Die auf den koplanaren
Oberflächen 1, 2 mit dünnen Schichten aus Zinn versehenen Kupferteilen
werden unter Druck in Kontakt miteinander gebracht und anschließend über
die Schmelztemperatur des Zinns erwärmt. Die hierdurch entstehende dünne
Schmelzschicht benetzt die Oberflächen 1, 2, im folgenden auch
Fügeflächen genannt. Aus der Schmelzschicht diffundiert Zinn in das
Kupfer der Fügeflächen. Dabei bildet sich zunächst die intermetallische
η-Phase mit Cu6Sn unter fortschreitender Aufzehrung der
schmelzflüssigen Phase. Dieser Zustand ist in Fig. 3 schematisch
dargestellt, in der die Bereiche mit Cu6Sn durch 4 bezeichnet sind. Die
intermetallische ε-Phase in der Zwischenschicht mit nahezu völlig
verschwundener schmelzflüssiger Phase zeigt Fig. 4.
Der in Fig. 4 gezeigte Zustand der Schicht 3 zwischen den Fügeflächen
entspricht einer Festkörper-Verbindung der Fügeflächen. Bei weiterer
Temperatureinwirkung, z. B. bei Verwendung der hergestellten Festkörper-
Verbindung unter erhöhten Temperaturen, wird dann die intermetallische
ε-Phase mit höherem Cu-Gehalt, nämlich Cu3Sn, gebildet. Die
entsprechenden Bereiche sind in Fig. 5 mit 5 bezeichnet.
Claims (22)
1. Verfahren zur Erzeugung einer formschlüssigen Verbindung zwischen
metallischen Oberflächen von Halbleiter- und Trägerelementen,
insbesondere zur Montage von Halbleiterchips in Bauelementen oder
auf Substraten,
gekennzeichnet durch folgende Verfahrensschritte:
- a) zwischen einem Halbleiter und einem Substrat, die jeweils mit Oberflächen aus höherschmelzenden Metallen versehen sind, wird eine Zwischenschicht aus einem gegenüber dem Halbleiter und metallischen Substrat niedrigschmelzendem Metall angeordnet;
- b) die höherschmelzende Halbleiteroberfläche, die niedrigschmelzende Zwischenschicht und die höherschmelzende Substratmetallisierung werden miteinander in Berührung gebracht und unter einem vorge gebenen Temperatur- und Anpreßduckverlauf auf bzw. über die Schmelztemperatur der Zwischenschicht derart erwärmt, daß die flüssige Zwischenschicht die Fügeoberflächen von Halbleiter und Substrat benetzt;
- c) daß durch Diffusion der verschwindenden flüssigen Zwischenschicht in die Halbleitermetallisierung und die Substratmetallisierung eine intermetallische Phase vom Material der Zwischenschicht und des zu fügenden Verbinders und Kontakts gebildet wird; und
- d) daß abschließend durch Abkühlung und Erstarrung während des vorgegebenen Temperatur- und Anpreßduckverlaufes die form schlüssige Verbindung zwischen Halbleiter und Substrat herge stellt wird, deren Schmelztemperatur höher ist, als die der ursprünglichen Zwischenschicht.
2. Verfahren nach Anspruch 1,
dadurch gekennzeichnet,
daß als niedrigschmelzende Zwischenschicht Metalle mit einem
Schmelzpunkt unter 450°C verwendet werden, wie Bi, Cd, Ga, In, Pb,
Sn oder Zn.
3. Verfahren nach Anspruch 1,
dadurch gekennzeichnet,
daß als höherschmelzende Halbleitermetallisierung und
Substratmetallisierung Metalle wie Ag, Au, Cu, Co, Fe, Mn, Ni, Pd,
Pt, Ir, Os, Re, Rh oder Ru verwendet werden.
4. Verfahren nach Anspruch 1, 2 oder 3,
dadurch gekennzeichnet,
daß die Schmelztemperatur und der vorgegebene Anpreßdruck mittels
einer Druck-Heiz-Zeit-Vorrichtung aufgebracht werden.
5. Verfahren nach Anspruch 4,
gekennzeichnet durch
die Verwendung einer Druck-Heiz-Zeit-Vorrichtung mit einer
Anpreßoberfläche in der Größe der Halbleitermetallisierung, deren
Temperaturbereich von 100 bis 500°C um ± 3K regelbar ist.
6. Verfahren nach Anspruch 1, 2 oder 3,
dadurch gekennzeichnet,
daß die Schmelztemperatur in einem Ofen bei gleichzeitiger
Aufbringung des Anpreßdrucks mittels einer mechanischen
Druckvorrichtung aufgebracht wird.
7. Verfahren nach einem der Ansprüche 1 bis 6 zur Herstellung einer
formschlüssigen Verbindung zwischen einem Halbleiterbauelement und
einem Trägerelement,
dadurch gekennzeichnet,
daß ein Halbleiter mit einer metallischen Fügeoberfläche aus Silber
bzw. Gold, ein Trägerelement mit Oberfläche aus Silber bzw. Gold und
eine Zwischenschicht aus Zinn bzw. Indium verwendet werden.
8. Verfahren nach Anspruch 7,
gekennzeichnet durch
die Verwendung eines Trägerelements aus Silizium, Keramiken wie
Al2O3, AIN, SiC, Metallen wie Molybdän, Kupfer, Kupfer-Invar-Kupfer
oder organischem Leiterplatten-Basismaterial mit einer
Fügeoberfläche aus Silber.
9. Verfahren nach Anspruch 7,
gekennzeichnet durch
die Verwendung eines Trägerelements aus Silizium, Keramiken wie
Al2O3, AIN, SiC, Metallen wie Molybdän, Kupfer, Indium oder
organischem Leiterplatten-Basismaterial mit einer Fügeoberfläche aus
Gold.
10. Verfahren nach Anspruch 7,
gekennzeichnet durch
die Verwendung einer 2 bis 10 µ dicken Silberschicht auf der
Oberfläche des Trägerelements.
11. Verfahren nach Anspruch 7,
gekennzeichnet durch
die Verwendung einer 2 bis 10 µ dicken Goldschicht auf der
Oberfläche des Trägerelements.
12. Verfahren nach Anspruch 10 oder 11,
dadurch gekennzeichnet,
daß die Schichtdicke der Zinn-Zwischenschicht auf dem Halbleiter
oder Substrat 1 bis 2 µ beträgt.
13. Verfahren nach einem oder mehreren der Ansprüche 7 bis 12,
dadurch gekennzeichnet,
daß die Zwischenschicht aus Zinn bzw. Indium auf die Fügeoberfläche
des Substrats aus Silber oder Gold lokal aufgebracht wird.
14. Verfahren nach Anspruch 13,
gekennzeichnet durch
eine lokale Aufbringung der Zwischenschicht auf die Fügeoberfläche
des Substrats mittels Photolacktechnik (Photoresisttechnik).
15. Verfahren nach Anspruch 13,
dadurch gekennzeichnet,
daß die Zwischenschicht durch eine lokale Bedampfung oder
Besputterung durch Maskentechnik auf die Fügeoberfläche des
Substrats aufgebracht wird.
16. Verfahren nach Anspruch 13,
gekennzeichnet durch
eine lokale galvanische Aufbringung der Zwischenschicht auf die
Fügeoberfläche des Substrats mittels Maskentechnik.
17. Verfahren nach einem oder mehreren der Ansprüche 7 bis 12,
dadurch gekennzeichnet,
daß die Zwischenschicht aus Zinn bzw. Indium auf die Fügeoberfläche
des Halbleiterbauelements aus Silber bzw. Gold lokal aufgebracht
wird.
18. Verfahren nach Anspruch 17,
gekennzeichnet durch
eine lokale Aufbringung der Zwischenschicht auf die Fügeoberfläche
des Halbleiterbauelements mittels Photolacktechnik
(Photoresisttechnik).
19. Verfahren nach Anspruch 17,
dadurch gekennzeichnet,
daß die Zwischenschicht durch eine lokale Bedampfung oder
Besputterung durch Maskentechnik auf die Fügeoberfläche des
Halbleiterbauelements aufgebracht wird.
20. Verfahren nach Anspruch 17,
gekennzeichnet durch
eine lokale galvanische Aufbringung der Zwischenschicht auf die
Fügeoberfläche des Halbleiterbauelements mittels Maskentechnik.
21. Verfahren nach einem der Ansprüche 8 bis 20,
dadurch gekennzeichnet,
daß das Halbleiterbauelement, die Zwischenschicht und das
Trägerelement auf eine der Löttemperatur entsprechende
Schmelztemperatur der Zwischenschicht in einem Bereich von 160 bis
350°C für einen Zeitraum von 0,5 bis 5 min erwärmt werden, daß für
diesen Zeitraum die vorgegebenen Anpreßdrücke zwischen Verbinder,
Zwischenschicht und Kontakt zwischen 0,5 und 100 Newton pro mm2
Bauelementoberfläche betragen.
22. Verfahren nach einem der Ansprüche 8 bis 21,
dadurch gekennzeichnet,
daß vor der Zwischenschicht eine dünne Diffusionssperrschicht
abgeschieden wird, welche eine Reaktion zwischen Trägermetall und
der Zwischenschicht während der Lagerung verhindert und somit eine
Verbesserung der Lagerfähigkeit erlaubt.
Priority Applications (1)
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DE4303790A DE4303790A1 (de) | 1993-02-10 | 1993-02-10 | Verfahren zur Erzeugung einer formschlüssigen Verbindung zwischen Halbleiterbauelementen und metallischen Oberflächen von Trägerelementen |
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Application Number | Priority Date | Filing Date | Title |
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DE4303790A DE4303790A1 (de) | 1993-02-10 | 1993-02-10 | Verfahren zur Erzeugung einer formschlüssigen Verbindung zwischen Halbleiterbauelementen und metallischen Oberflächen von Trägerelementen |
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Family
ID=6480014
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Cited By (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE19507547A1 (de) * | 1995-03-03 | 1996-09-05 | Siemens Ag | Verfahren zur Montage von Chips |
DE19531158A1 (de) * | 1995-08-24 | 1997-02-27 | Daimler Benz Ag | Verfahren zur Erzeugung einer temperaturstabilen Verbindung |
DE19532251A1 (de) * | 1995-09-01 | 1997-03-06 | Daimler Benz Ag | Anordnung und Verfahren zum Diffusionslöten |
DE19532250A1 (de) * | 1995-09-01 | 1997-03-06 | Daimler Benz Ag | Anordnung und Verfahren zum Diffusionslöten eines mehrschichtigen Aufbaus |
WO2004016384A1 (en) * | 2002-08-16 | 2004-02-26 | New Transducers Limited | Method of bonding a piezoelectric material and a substrate |
WO2005086218A1 (ja) | 2004-03-02 | 2005-09-15 | Fuji Electric Holdings Co., Ltd. | 半導体モジュールの製造方法 |
EP1582287A1 (de) | 2004-03-31 | 2005-10-05 | Kabushiki Kaisha Toshiba | Matériau soudé , dispositif semi-conducteur, procédé de soudage tendre et procédé pour la fabrication d'un dispositif semi-conducteur |
WO2006074165A2 (en) * | 2005-01-07 | 2006-07-13 | Teledyne Licensing, Llc | HIGH TEMPERATURE, STABLE SiC DEVICE INTERCONNECTS AND PACKAGES HAVING LOW THERMAL RESISTANCE |
EP1734570A1 (de) * | 2004-03-02 | 2006-12-20 | Fuji Electric Holdings Co., Ltd. | Verfahren zur kapselung einer elektronischen komponente |
DE102006019080B3 (de) * | 2006-04-25 | 2007-08-30 | Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. | Herstellungsverfahren für ein gehäustes Bauelement |
US7670879B2 (en) | 2002-08-30 | 2010-03-02 | Fuji Electric Holdings Co., Ltd. | Manufacturing method of semiconductor module including solid-liquid diffusion joining steps |
US7911061B2 (en) | 2007-06-25 | 2011-03-22 | Infineon Technologies Ag | Semiconductor device |
DE102022201411A1 (de) | 2022-02-11 | 2023-08-17 | Zf Friedrichshafen Ag | Verfahren zum Herstellen einer elektronischen Schaltung durch selektive Diffusionslötung mittels gerichteter Diffusion |
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Cited By (23)
Publication number | Priority date | Publication date | Assignee | Title |
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DE19507547A1 (de) * | 1995-03-03 | 1996-09-05 | Siemens Ag | Verfahren zur Montage von Chips |
DE19531158A1 (de) * | 1995-08-24 | 1997-02-27 | Daimler Benz Ag | Verfahren zur Erzeugung einer temperaturstabilen Verbindung |
DE19532251A1 (de) * | 1995-09-01 | 1997-03-06 | Daimler Benz Ag | Anordnung und Verfahren zum Diffusionslöten |
DE19532250A1 (de) * | 1995-09-01 | 1997-03-06 | Daimler Benz Ag | Anordnung und Verfahren zum Diffusionslöten eines mehrschichtigen Aufbaus |
WO2004016384A1 (en) * | 2002-08-16 | 2004-02-26 | New Transducers Limited | Method of bonding a piezoelectric material and a substrate |
US7670879B2 (en) | 2002-08-30 | 2010-03-02 | Fuji Electric Holdings Co., Ltd. | Manufacturing method of semiconductor module including solid-liquid diffusion joining steps |
EP1734569A4 (de) * | 2004-03-02 | 2008-02-27 | Fuji Electric Holdings | Prozess zur herstellung eines halbleitermoduls |
WO2005086218A1 (ja) | 2004-03-02 | 2005-09-15 | Fuji Electric Holdings Co., Ltd. | 半導体モジュールの製造方法 |
EP1734570A1 (de) * | 2004-03-02 | 2006-12-20 | Fuji Electric Holdings Co., Ltd. | Verfahren zur kapselung einer elektronischen komponente |
EP1734569A1 (de) * | 2004-03-02 | 2006-12-20 | Fuji Electric Holdings Co., Ltd. | Prozess zur herstellung eines halbleitermoduls |
EP1734570A4 (de) * | 2004-03-02 | 2008-03-05 | Fuji Electric Holdings | Verfahren zur kapselung einer elektronischen komponente |
EP1582287A1 (de) | 2004-03-31 | 2005-10-05 | Kabushiki Kaisha Toshiba | Matériau soudé , dispositif semi-conducteur, procédé de soudage tendre et procédé pour la fabrication d'un dispositif semi-conducteur |
WO2006074165A3 (en) * | 2005-01-07 | 2006-12-28 | Rockwell Scient Licensing Llc | HIGH TEMPERATURE, STABLE SiC DEVICE INTERCONNECTS AND PACKAGES HAVING LOW THERMAL RESISTANCE |
US7390735B2 (en) | 2005-01-07 | 2008-06-24 | Teledyne Licensing, Llc | High temperature, stable SiC device interconnects and packages having low thermal resistance |
US7659614B2 (en) | 2005-01-07 | 2010-02-09 | Vivek Mehrotra | High temperature, stable SiC device interconnects and packages having low thermal resistance |
WO2006074165A2 (en) * | 2005-01-07 | 2006-07-13 | Teledyne Licensing, Llc | HIGH TEMPERATURE, STABLE SiC DEVICE INTERCONNECTS AND PACKAGES HAVING LOW THERMAL RESISTANCE |
US8012865B2 (en) | 2005-01-07 | 2011-09-06 | Astriphey Applications L.L.C. | High temperature, stable SiC device interconnects and packages having low thermal resistance |
WO2007121992A1 (de) * | 2006-04-25 | 2007-11-01 | Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. | Gehäuse mit einer elektrischen schaltung |
DE102006019080B3 (de) * | 2006-04-25 | 2007-08-30 | Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. | Herstellungsverfahren für ein gehäustes Bauelement |
US8581357B2 (en) | 2006-04-25 | 2013-11-12 | Fraunhofer-Gesellschft Zur Foerderung Der Angewandten Forschung E.V. | Package comprising an electrical circuit |
US7911061B2 (en) | 2007-06-25 | 2011-03-22 | Infineon Technologies Ag | Semiconductor device |
US8156643B2 (en) | 2007-06-25 | 2012-04-17 | Infineon Technologies Ag | Semiconductor device |
DE102022201411A1 (de) | 2022-02-11 | 2023-08-17 | Zf Friedrichshafen Ag | Verfahren zum Herstellen einer elektronischen Schaltung durch selektive Diffusionslötung mittels gerichteter Diffusion |
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