TW200814213A - Chip package and method for fabricating the same - Google Patents

Chip package and method for fabricating the same Download PDF

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Publication number
TW200814213A
TW200814213A TW096133091A TW96133091A TW200814213A TW 200814213 A TW200814213 A TW 200814213A TW 096133091 A TW096133091 A TW 096133091A TW 96133091 A TW96133091 A TW 96133091A TW 200814213 A TW200814213 A TW 200814213A
Authority
TW
Taiwan
Prior art keywords
layer
package structure
wafer
micrometers
thickness
Prior art date
Application number
TW096133091A
Other languages
Chinese (zh)
Other versions
TWI395275B (en
Inventor
Mou-Shiung Lin
Original Assignee
Megica Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Megica Corp filed Critical Megica Corp
Publication of TW200814213A publication Critical patent/TW200814213A/en
Application granted granted Critical
Publication of TWI395275B publication Critical patent/TWI395275B/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

A method for fabricating chip package includes providing a semiconductor chip with a bonding pad, comprising an adhesion/barrier layer, connected to a pad through an opening in a passivation layer, next adhering the semiconductor chip to a substrate using a glue material, next bonding a wire to the bonding pad and to the substrate, forming a polymer material on the substrate, covering the semiconductor chip and the wire, next forming a lead-free solder ball on the substrate, and then cutting the substrate and polymer material to form a chip package.

Description

200814213 九、發明說明： 【發明所屬之技術領域】 本發明係有關一種結構及其製程，特別是有關一種晶 片封裝結構及其製程。 【先前技術】 打線接合（wire bonding)是用來使半導體晶片 (semiconductor chip)向外連接外部電路的技術之一，此技 術是先將半導體晶片固定於基板（例如印刷電路板）或導線 架（lead frame)上，再以細金屬線（或稱打線導線)使半導體 晶片與導線架的引腳電性連接或是使半導體晶片與基板的 線路電性連接。 請參閱第1圖所示，習知球型柵狀陣列（Ball Grid Array ’ BGA)封裝技術係利用一金線（gold wire)l 10接合一 半導體晶片II2之一紹金屬保護蓋（aluminum cap) 114與一 球型柵狀陣列基板116的一接點，其中鋁金屬保護蓋114 係位在保護層（passivation layer)118内之一開口 118a所暴 露出的一銅墊（copper pad)l20上，因此銅墊120透過金線 110電性連接球型柵狀陣列基板116的線路，進而與接合 球型柵狀陣列基板116的錫球（solder ball)122電性連接。 惟，習知金線接合鋁金屬保護蓋的打線技術，容易在 後續的組裝製程（assembly process)中以及無錯錫球 (lead-free solder ball)製程中，因高溫而使金線的金原子與 6 200814213 鋁墊或鋁金屬保護蓋的鋁金屬形成介金屬化合物 (intermetallic compound，IMC)，進而造成結構的脆化並影 響結構的可靠度。另’在產品化之後’金線與半導體晶片 亦容易在高功率的使用情況下產生高熱，進而使金線的金 原子與铭墊或紹金屬保護蓋的銘金屬形成介金屬化合物 (IMC)，以造成結構的脆化並影響結構的可靠度。 【發明内容】 本發明之一目的，係在提供一種晶片封裝結構及其製 程，其可防止金線的金原子與鋁墊或鋁金屬保護蓋的鋁金 屬形成介金屬化合物（IMC)。 為了上述之目的，本發明提出一種晶片封裝結構，其 係包括一基板；一無錯錫球（lead-free solder ball)，接合該 基板，一黏者材料’位在該基板上，一半導體晶片’位在 該黏著材料上，且該半導體晶片包括含有黏著/阻障層之一 打線接墊位在保護層之一開口所暴露出之一接墊上方；一 打線導線，接合該打線接墊與該基板；以及一聚合物材料， 位在該基板上，並覆蓋該半導體晶片與該打線導線。 為了上述之目的，本發明提出一種晶片封裝結構，其 係包括一基板；一無鉛錫球，接合該基板；一黏著材料， 位在該基板上，一半導體晶片’位在該黏者材料上’且該 半導體晶片包括含有黏著/阻障層之一打線接點；一打線導 線，接合該打線接點與該基板；以及一聚合物材料，位在 該基板上，並覆蓋該半導體晶片與該打線導線。 7 200814213 為了上述之目的，本發明提出一種晶片封裝結構，立 係包括-導線架dead frame)，包括一晶片承载座與一引 腳；一黏著材料，位在該晶片承载座上；—半導體晶片， 位在該黏著㈣上，且該半導體晶片包括含麵著^障層 之一打線接墊位在保護層之一開口所暴露出之一接墊上 方；一打線導線，接合該打線接墊與該引腳；以及一聚合 物材料’包覆該晶片承載座、該半導體晶片、該打線導線 與部份之該引腳。 為了上述之目的，本發明提出一種晶片封裝結構，其 係包括含有一晶片承載座與一引腳的一導線架；一黏著材 料，位在該晶片承載座上；一半導體晶片，位在該黏著材 料上，且該半導體晶片包括含有黏著/阻障層之一打線接 點；一打線導線，接合該打線接點與該引腳；以及一聚合 物材料，包覆該晶片承載座、該半導體晶片、該打線導線 與部份之該引腳。 為了上述之目的，本發明提出一種晶片封裝製程，其 步驟包括提供一半導體晶片，其係包括含有黏著/阻障層之 一打線接墊位在保護層之一開口所暴露出的一接墊上方； 利用一黏著材料黏著該半導體晶片至一基板的一第一表 面，形成一打線導線接合該打線接墊與該基板的一接點； 形成一聚合物材料在該第一表面上，並覆蓋該半導體晶片 與該打線導線；形成一無鉛銲料（lead_free s〇lder)在該基板 之一第一表面上，並在溫度介於23〇。〇至26〇〇c之間進行一 k 知（reflow) I 転’以形成一無船錫球（iead_free s〇ider 8 200814213 ball);以及切割基板與聚合物材料，以形成晶片封裝結構。 底下藉由具體實施例配合所附的圖式詳加說明，當更 容易瞭解本發明之目的、技術内容、特點及其所達成之功 效0 【實施方式】 請參閱第2A圖所示，一半導體基底2(或稱為積體電 路基底，IC substrate)比如是石夕基底、神化錄（GaAs)基底或 矽化鍺（SiGe)基底，另外半導體基底2也可以是一空白晶 圓（blank wafer)，而此空白晶圓比如是石夕晶圓（silicon wafer)、砷化鎵晶圓或矽化鍺晶圓。複數半導體元件4位 在半導體基底2内或上方，而這些半導體元件4包括記憶 體、邏輯元件、被動元件（例如電阻、電容或電感）或主動 元件等，其中主動元件比如是金氧半導體（MOS)元件，此 金氧半導體元件例如是p通道金氧半導體元件（p-channel MOS devices)、η通道金氧半導體元件（n-channel MOS devices)、雙載子互補式金氧半導體元件（BiCMOS devices)、雙載子連接電晶體（Bipolar Junction Transistor， BJT)或互補金屬氧化半導體（CMOS)。另，「上方」一詞在 本發明中是表示位在某物上面並與之接觸，或是表示位在 某物上面但未與之接觸。 一線路結構6位在半導體基底2上方，並連接這些半 導體元件4。線路結構6可以是由複數圖案化金屬層8(其 厚度tl比如是小於3微米，例如是介於0.2微米至2微米 9 200814213 之間）與複數金屬插塞（metal plug)10所構成。例如，這些 圖案化金屬層8與這些金屬插塞10的材質主要是銅，亦即 圖案化金屬層8可以是厚度小於3微米（比如是介於0.2微 米至2微米之間）的一銅層；或是，這些圖案化金屬層8的 材質主要是含鋁金屬（如鋁或鋁合金），而這些金屬插塞10 的材質主要是鎢，也就是說圖案化金屬層8可以是厚度小 於3微米（比如是介於0.2微米至2微米之間）的一含鋁金 屬層。此外，形成線路結構6的方式包括濺鍍製程 (sputtering process)、鑲欲製程（damascene process)或電鍍 製程（electroplating process)等。 例如以鑲嵌製程而言，形成線路結構6的方式包括利 用化學氣相沉積（Chemical Vapor Deposition，CVD)的方式 沈積一第一介電層（dielectric layer)在一第二介電層的上 表面上，其中第一介電層的材質與第二介電層的材質包括 有氮氧矽化合物與介電常數值（k)介於1.5至3之間的材 質；接著，形成一第一光阻層在第一介電層上，並利用位 在第一光阻層内的第一光阻層開口蝕刻第一介電層，以暴 露出第二介電層而形成溝渠；於形成溝渠之後，去除此第 一光阻層；繼續，形成一第二光阻層在第一介電層上與溝 渠所暴露出之苐一介電層上’且位在第二光阻層内之第二 光阻層開口暴露出苐二介電層；再來，去除第二光阻層開 口所暴露出之第二介電層而形成導通孔，並在形成導通孔 之後，去除第二光阻層。因此，由溝渠與導通孔所組成的 開口形成在第一介電層内與第二介電層内。接著，利用濺 200814213 鍍或化學氣相沉積的方式沈積一阻障層在此開口内的下表 面與側壁上以及第一介電層的上表面上，其中此阻障層的 材質係選自鈕（Ta)、氮化钽（TaN)、氮化鎢（WN)、氮化鈦（TiN) 及鈦（Ti)其中之一者或是上述材料所形成之組合，例如此 阻障層可以是濺鍍钽；繼續，利用濺鍍或化學氣相沉積的 方式沈積一層例如是銅材質之種子層在阻障層上，再來電 鍍一銅金屬在此種子層上，最後利用化學機械研磨 (Chemical Mechanical Polish，CMP)的方式去除位在此開口 / 外的銅金屬、種子層及阻障層，直到曝露出第一介電層的 上表面為止。以此種方式形成在溝渠内的金屬（其係包括阻 障層、種子層及電鍍銅）係為圖案化金屬層8，而形成在導 通孔内的金屬則為金屬插塞10,且這些圖案化金屬層8可 以透過導通孔内的金屬插塞10連通相鄰兩層之間的圖案 化金屬層8或是連接至半導體元件4。 又，形成圖案化金屬層8方式比如是先利用濺鍍製程 賤鍍一銘合金層（其係包括90 wt %以上的銘及10 wt %以 ^ 下的銅）在一介電層上，接著再透過微影蝕刻製程圖案化此 鋁合金層。也就是說，線路結構6包括濺鍍鋁。 複數介電層12位在半導體基底2的上方，且圖案化金 屬層8是位在這些介電層12之間，並透過位在這些介電層 12内的金屬插塞10連接相鄰兩層之圖案化金屬層8。介電 層12 —般是利用化學氣相沉積（CVD)的方式所形成，而介 電層12比如是氧矽化合物（例如Si02)、四乙氧基矽烷 (TEOS)之氧化物、含矽、碳、氧與氫之化合物（例如 11 200814213200814213 IX. DESCRIPTION OF THE INVENTION: TECHNICAL FIELD OF THE INVENTION The present invention relates to a structure and a process thereof, and more particularly to a wafer package structure and a process thereof. [Prior Art] Wire bonding is one of techniques for connecting a semiconductor chip to an external circuit, which is to first fix a semiconductor wafer to a substrate (such as a printed circuit board) or a lead frame ( On the lead frame, a thin metal wire (or wire bonding wire) is used to electrically connect the semiconductor chip to the lead of the lead frame or electrically connect the semiconductor chip to the circuit of the substrate. Referring to FIG. 1, a conventional Ball Grid Array 'BGA package technology uses a gold wire 10 to bond a semiconductor cap II to a metal cap 114 and A contact of a spherical grid array substrate 116, wherein the aluminum metal protective cover 114 is fastened to a copper pad l20 exposed by one of the openings 118a in the passivation layer 118, thus copper The pad 120 is electrically connected to the ball grid array substrate 116 through the gold wire 110 , and is electrically connected to the solder ball 122 of the ball grid array substrate 116 . However, the wire bonding technology of the conventional gold wire joint aluminum metal protective cover is easy to make the gold atom of the gold wire due to the high temperature in the subsequent assembly process and the lead-free solder ball process. Forming an intermetallic compound (IMC) with aluminum alloy of 6 200814213 aluminum pad or aluminum metal protective cover, which causes embrittlement of the structure and affects the reliability of the structure. In addition, after the productization, the gold wire and the semiconductor wafer are also prone to generate high heat under high power use, and the gold atom of the gold wire forms a metal intermetallic compound (IMC) with the metal of the Ming pad or the metal protective cover. To cause embrittlement of the structure and affect the reliability of the structure. SUMMARY OF THE INVENTION An object of the present invention is to provide a wafer package structure and a process thereof for preventing a gold atom of a gold wire from forming a metal intermetallic compound (IMC) with an aluminum pad of an aluminum pad or an aluminum metal protective cover. For the above purposes, the present invention provides a chip package structure including a substrate, a lead-free solder ball, a substrate bonded to the substrate, and a semiconductor wafer. Positioning on the adhesive material, and the semiconductor wafer includes a bonding pad having one of the adhesion/barrier layers positioned over one of the pads exposed by one of the openings of the protective layer; a wire bonding wire bonding the bonding wire and The substrate; and a polymer material positioned on the substrate and covering the semiconductor wafer and the wire bonding wire. For the above purposes, the present invention provides a chip package structure comprising a substrate; a lead-free solder ball bonded to the substrate; an adhesive material positioned on the substrate, and a semiconductor wafer 'on the adhesive material' And the semiconductor wafer includes a wire bonding contact including an adhesion/barrier layer; a wire bonding wire bonding the wire bonding node and the substrate; and a polymer material disposed on the substrate and covering the semiconductor wafer and the bonding wire wire. 7 200814213 For the above purposes, the present invention provides a chip package structure, the system includes a lead frame, including a wafer carrier and a pin; an adhesive material on the wafer carrier; - a semiconductor wafer Positioned on the adhesive (four), and the semiconductor wafer includes a wire bonding pad having a surface of the barrier layer over one of the pads exposed by the opening of the protective layer; a wire bonding wire bonding the wire bonding pad and The pin; and a polymer material 'covers the wafer carrier, the semiconductor wafer, the wire conductor and a portion of the pin. For the above purposes, the present invention provides a chip package structure including a lead frame including a wafer carrier and a lead; an adhesive material on the wafer carrier; and a semiconductor wafer positioned on the bond In the material, the semiconductor wafer includes a wire bonding contact including an adhesion/barrier layer; a wire bonding wire bonding the wire bonding contact and the pin; and a polymer material covering the wafer carrier and the semiconductor wafer , the wire conductor and part of the pin. For the above purposes, the present invention provides a wafer packaging process including the steps of providing a semiconductor wafer comprising a bonding pad having an adhesion/barrier layer positioned over a pad exposed by an opening in one of the protective layers Adhering the semiconductor wafer to a first surface of a substrate by using an adhesive material to form a wire bonding wire to bond the wire bonding pad to the substrate; forming a polymer material on the first surface and covering the a semiconductor wafer and the wire bonding wire; forming a lead-free solder on a first surface of the substrate at a temperature of 23 Å. Between 26 〇〇c, a reflow I 転 ' is performed to form a shipless solder ball (iead_free s〇ider 8 200814213 ball); and the substrate and the polymer material are cut to form a chip package structure. The purpose of the present invention, the technical contents, the features, and the effects achieved by the present invention will be better understood by the specific embodiments and the accompanying drawings. [Embodiment] Please refer to FIG. 2A, a semiconductor The substrate 2 (also referred to as an integrated circuit substrate, IC substrate) is, for example, a Shi Xi substrate, a Shenhua recording (GaAs) substrate or a germanium telluride (SiGe) substrate, and the semiconductor substrate 2 may also be a blank wafer. The blank wafer is, for example, a silicon wafer, a gallium arsenide wafer, or a germanium telluride wafer. The plurality of semiconductor elements 4 are located in or above the semiconductor substrate 2, and the semiconductor elements 4 include a memory, a logic element, a passive element (such as a resistor, a capacitor or an inductor) or an active element, etc., wherein the active element is, for example, a metal oxide semiconductor (MOS). The MOS device is, for example, a p-channel MOS device, an n-channel MOS device, or a bi-carrier complementary MOS device (BiCMOS devices). ), Bipolar Junction Transistor (BJT) or Complementary Metal Oxide Semiconductor (CMOS). Further, the term "above" is used in the present invention to mean that it is on or in contact with something, or that it is located on something but not in contact with it. A line structure 6 is placed over the semiconductor substrate 2 and these semiconductor elements 4 are connected. The wiring structure 6 may be formed of a plurality of patterned metal layers 8 (having a thickness t1 such as less than 3 microns, for example between 0.2 microns and 2 microns 9 200814213) and a plurality of metal plugs 10. For example, the patterned metal layer 8 and the metal plug 10 are mainly made of copper, that is, the patterned metal layer 8 may be a copper layer having a thickness of less than 3 micrometers (for example, between 0.2 micrometers and 2 micrometers). Or, the material of the patterned metal layer 8 is mainly aluminum-containing metal (such as aluminum or aluminum alloy), and the material of the metal plug 10 is mainly tungsten, that is, the patterned metal layer 8 can be less than 3 An aluminum-containing metal layer of micron (such as between 0.2 microns and 2 microns). Further, the manner of forming the wiring structure 6 includes a sputtering process, a damascene process, or an electroplating process. For example, in the case of a damascene process, the manner of forming the wiring structure 6 includes depositing a first dielectric layer on the upper surface of a second dielectric layer by means of chemical vapor deposition (CVD). The material of the first dielectric layer and the material of the second dielectric layer comprise a material having a oxynitride compound and a dielectric constant value (k) of between 1.5 and 3; then, forming a first photoresist layer Depositing a first dielectric layer on the first dielectric layer with a first photoresist layer opening in the first photoresist layer to expose the second dielectric layer to form a trench; after forming the trench, removing The first photoresist layer continues; forming a second photoresist layer on the first dielectric layer and the second photoresist layer on the first dielectric layer exposed by the trench and located in the second photoresist layer The layer opening exposes the second dielectric layer; then, the second dielectric layer exposed by the opening of the second photoresist layer is removed to form a via hole, and after the via hole is formed, the second photoresist layer is removed. Therefore, an opening composed of the trench and the via hole is formed in the first dielectric layer and in the second dielectric layer. Then, a barrier layer is deposited on the lower surface and the sidewall of the opening and the upper surface of the first dielectric layer by sputtering 200814213 plating or chemical vapor deposition, wherein the material of the barrier layer is selected from the button (Ta), tantalum nitride (TaN), tungsten nitride (WN), titanium nitride (TiN), and titanium (Ti), or a combination of the above materials, for example, the barrier layer may be splashed Plating; continuing, depositing a layer of a seed layer of, for example, copper on the barrier layer by sputtering or chemical vapor deposition, and then plating a copper metal on the seed layer, and finally using chemical mechanical polishing (Chemical Mechanical) Polish, CMP) removes the copper metal, seed layer and barrier layer located at this opening/outside until the upper surface of the first dielectric layer is exposed. The metal formed in the trench in this manner (including the barrier layer, the seed layer, and the electroplated copper) is the patterned metal layer 8, and the metal formed in the via hole is the metal plug 10, and these patterns The metal layer 8 can pass through the metal plug 10 in the via hole to communicate with the patterned metal layer 8 between the adjacent two layers or to the semiconductor element 4. Moreover, the method of forming the patterned metal layer 8 is, for example, first spraying a layer of an alloy layer (including 90 wt% or more and 10 wt% of copper) on a dielectric layer by using a sputtering process, followed by The aluminum alloy layer is patterned by a photolithography process. That is, the wiring structure 6 includes sputtered aluminum. The plurality of dielectric layers 12 are positioned above the semiconductor substrate 2, and the patterned metal layer 8 is positioned between the dielectric layers 12, and is connected to the adjacent two layers through the metal plugs 10 located in the dielectric layers 12. The patterned metal layer 8 is formed. The dielectric layer 12 is generally formed by chemical vapor deposition (CVD), and the dielectric layer 12 is, for example, an oxonium compound (for example, SiO 2 ), an oxide of tetraethoxy decane (TEOS), or a compound of carbon, oxygen and hydrogen (eg 11 200814213

SiwCxOyHz)、氮矽化合物（例如Si3N4)、氮氧矽化合物、氟 石夕玻璃（Fluorinated Silicate Glass，FSG)、絲印層（SiLK)、 黑鑽石薄膜（Black Diamond)、棚構石夕玻璃 (Borophosphosilicate Glass，BPSG)、聚芳基醋（polyarylene ether)、多孔性氧化石夕（porous silicon oxide)、聚苯β惡口坐 (polybenzoxazole，ΡΒΟ)、介電常數值（k)介於1 ·5至3之間 的材質或者是以旋塗方式形成之玻璃（Spin-On Glass， SOG;中文亦可譯為旋塗式玻璃）。另，介電層12的厚度 t2比如是小於3微米，較佳厚度則是介於0.3微米至2.5 微米之間。 一保護層14位在線路結構6與介電層12的上方，此 保護層14可以保護半導體元件4與線路結構6免於受到濕 氣與外來離子污染物（foreign ion contamination)的破壞，也 就是說保護層14可以防止移動離子（比如是鈉離子）、水氣 (moisture)、過渡金屬（比如是金、銀、銅）及其它雜質 (impurity)穿透，而損壞保護層14下方的半導體元件4(例 如電晶體、多晶碎電阻元件或多晶碎-多晶碎電容元件）或 線路結構6。另，「下方」一詞在本發明中是表示位在某物 下面並與之接觸，或是表示位在某物下面但未與之接觸； 「下」一字在本發明中則是表示位在某物下面並與之接觸。 保護層14通常是由氧矽化合物（例如Si02)、磷矽玻璃 (Phosphosilicate Glass，PSG)、氮石夕化合物（例如 Si3N4)或 氮氧矽化合物等所組成，而保護層14的厚度t3 —般係大 於〇·3微米（//m)，例如保護層14的厚度t3是介於〇·3微 12 200814213 米至1.5微米之間。又，保護層14在包括氮矽化合物層的 情況下’此氮石夕化合物層的厚度通常大於〇·3微米。接著， 將敘述保護層14的製作方式，其係約有十種不同方法，分 別說明如下。 第一種製作保護層14的方法是先利用化學氣相沉積 (CVD)形成厚度介於〇.2微米至ι·2微米之間的一氧化石夕 層’接著再利用化學氣相沉積（CVD)形成厚度介於〇.2微 米至1.2微米之間的一氮化矽層在氧化矽層上。其中，「上」 一字在本發明中是表示位在某物上面並與之接觸。 第二種製作保護層14的方法是先利用化學氣相沉積 (CVD)形成厚度介於〇·2微米至ι·2微米之間的一氧化石夕 層’繼續利用電漿加強型化學氣相沉積（Plasnia EnhancedSiwCxOyHz), nitrogen bismuth compound (such as Si3N4), oxynitride compound, Fluorinated Silicate Glass (FSG), silk screen layer (SiLK), Black Diamond film, Borophosphosilicate Glass , BPSG), polyarylene ether, porous silicon oxide, polyphenylxazole (polybenzoxazole, ΡΒΟ), dielectric constant (k) between 1 · 5 and 3 The material between them is either a spin-on glass (Spin-On Glass, SOG; Chinese can also be translated as spin-on glass). Further, the thickness t2 of the dielectric layer 12 is, for example, less than 3 μm, and preferably the thickness is between 0.3 μm and 2.5 μm. A protective layer 14 is positioned over the wiring structure 6 and the dielectric layer 12. The protective layer 14 protects the semiconductor component 4 and the wiring structure 6 from moisture and foreign ion contamination, that is, It is said that the protective layer 14 can prevent mobile ions (such as sodium ions), moisture, transition metals (such as gold, silver, copper) and other impurities from penetrating, and damage the semiconductor components under the protective layer 14. 4 (for example a transistor, a polycrystalline resistor element or a polycrystalline-polycrystalline capacitor element) or a line structure 6. In addition, the term "below" is used in the present invention to mean that it is underneath and in contact with something, or that it is below something but not in contact with it; the word "below" is used in the present invention to indicate a bit. Under and in contact with something. The protective layer 14 is usually composed of an oxonium compound (for example, SiO 2 ), Phosphosilicate Glass (PSG), a Nitrogen compound (for example, Si 3 N 4 ), or an oxynitride compound, and the protective layer 14 has a thickness t3. The thickness is greater than 〇·3 μm (//m), for example, the thickness t3 of the protective layer 14 is between 2008·3 micro 12 200814213 m to 1.5 μm. Further, in the case where the protective layer 14 includes a layer of a nitrogen-niobium compound, the thickness of the nitride compound layer is usually larger than 〇·3 μm. Next, the manner of manufacturing the protective layer 14 will be described, which is about ten different methods, which are described below. The first method of fabricating the protective layer 14 is to first form a layer of oxidized stone with a thickness between 〇.2 μm and ι·2 μm by chemical vapor deposition (CVD) followed by chemical vapor deposition (CVD). Forming a tantalum nitride layer having a thickness between 微米.2 μm and 1.2 μm on the ruthenium oxide layer. Among them, the word "upper" in the present invention means that it is placed on and in contact with something. The second method of fabricating the protective layer 14 is to first form a oxidized stone layer having a thickness between 〇·2 μm and ι·2 μm by chemical vapor deposition (CVD). Plasnia Enhanced

Chemical Vapor Deposition，PECVD)形成厚度介於 0·05 微 米至0· 15微米之間的一氮氧化矽層在氧化矽層上，接著再 利用化學氣相沉積（CVD)形成厚度介於〇·2微米至1 ·2微米 之間的一氮化矽層在氮氧化矽層上。 第二種製作保護層14的方法是先利用化學氣相沉積 (CVD)形成厚度介於〇.05微米至〇15微米之間的一氮氧化 矽層，繼續利用化學氣相沉積（CVD)形成厚度介於〇 2微 米至1·2微米之間的一氧化矽層在氮氧化矽層上，接著再 利用化學氣相沉積（CVD)形成厚度介於〇·2微米至12微米 之間的一氮化矽層在氧化矽層上。 弟四種製作保遵層14的方法是先利用化學氣相沉積 (CVD)形成厚度介於〇·2微米至〇·5微米之間的一第一氧化 13 200814213 碎層’繼績利用旋塗法（spin-coating)形成厚度介於〇·5微 米至1微米之間的一第二氧化矽層在第一氧化石夕層上，接 著利用化學氣相沉積（CVD)形成厚度介於〇·2微米至〇.5微 米之間的一第三氧化矽層在第二氧化矽層上，最後再利用 化學氣相沉積（CVD)形成厚度介於〇·2微米至ι·2微米之間 的一氮化矽層在第三氧化矽層上。 第五種製作保護層14的方法是先利用高密度電漿化 學氣相 /儿積（High Density Plasma Chemical Vapor Deposition，HDP-CVD)形成厚度介於〇·5微米至2微米之 間的一氧化矽層，接著再利用化學氣相沉積（CVD)形成厚 度介於0·2微米至1.2微米之間的一氮化矽層在氧化矽層 上。 第六種製作保護層14的方法是先形成厚度介於〇·2微 米至3微米之間的一未摻雜矽玻璃層㈠“叩以silicate glass ’ USG)，繼續形成比如是四乙氧基石夕烧、硼碗石夕玻璃 (BPSG)或磷矽玻璃（psg)等之厚度介於〇·5微米至3微米之 間的一絕緣層在未摻雜矽玻璃層上，接著再利用化學氣相 沉積（CVD)形成厚度介於〇·2微米至12微米之間的一氮化 碎層在絕緣層上。 第七種製作保護層14的方法是選擇性地先利用化學 氣相沉積（CVD)形成厚度介於〇〇5微米至〇15微米之間的 一第一氮氧化矽層，繼續利用化學氣相沉積（CVD)形成厚 度介於0.2微米至微米之間的一氧化矽層在第一氮氧 化矽層上，接著可以選擇性地利用化學氣相沉積（cvd)b 200814213 成厚度介於0.05微米至0· 15微米之間的一第二氮氧化矽 層在氧化矽層上，再來利用化學氣相沉積（CVD)形成厚度 介於0.2微米至1.2微米之間的一氮化矽層在第二氮氧化 矽層上或在氧化矽層上，接著可以選擇性地利用化學氣相 沉積（CVD)形成厚度介於0.05微米至0.15微米之間的一第 三氮氧化矽層在氮化矽層上，最後再利用化學氣相沉積 (CVD)形成厚度介於0·2微米至1.2微米之間的一氧化矽層 在第三氮氧化矽層上或在氮化矽層上。 第八種製作保護層14的方法是先利用化學氣相沉積 (CVD)形成厚度介於0.2微米至1.2微米之間的一第一氧化 矽層，繼續利用旋塗法形成厚度介於0.5微米至1微米之 間的一第二氧化矽層在第一氧化矽層上，接著利用化學氣 相沉積（CVD)形成厚度介於0.2微米至1.2微米之間的一第 三氧化矽層在第二氧化矽層上，再來利用化學氣相沉積 (CVD)形成厚度介於0.2微米至1.2微米之間的一氮化矽層 在第三氧化矽層上，最後再利用化學氣相沉積（CVD)形成 厚度介於0.2微米至1.2微米之間的一第四氧化矽層在氮 化石夕層上。 第九種製作保護層14的方法是先利用高密度電漿化 學氣相沉積（HDP-CVD)形成厚度介於0.5微米至2微米之 間的一第一氧化矽層，繼續利用化學氣相沉積（CVD)形成 厚度介於0.2微米至1.2微米之間的一氮化矽層在第一氧 化矽層上，接著再利用高密度電漿化學氣相沉積 (HDP-CVD)形成厚度介於0.5微米至2微米之間的一第二 15 200814213 氧化矽層在氮化矽層上。 苐十種製作保護層14的方法是先利用化學氣相沉積 (CVD)形成厚度介於〇·2微米至1.2微米之間的一第一氮化 矽層，繼續利用化學氣相沉積（CVD)形成厚度介於α·2微 米至1.2微米之間的一氧化矽層在第一氮化矽層上，接著 再利用化學氣相沉積（CVD)形成厚度介於〇·2微米至1.2微 米之間的一第二氮化矽層在氧化矽層上。 本發明係透過位在保護層14内的一開口 14a暴露出線 路結構6之一接墊16,此接墊16的厚度t4比如是介於〇·4 微米至3微米之間或是介於〇·2微米至2微米之間。形成 接墊Μ的方式例如是以濺鍍製程形成鋁或鋁合金作為接 墊16(其厚度例如是介於〇·2微米至2微米之間），或是以 電鍍製程形成銅作為接墊16(其厚度例如是介於G.2微米 至2微米之間）。因此，接墊16可以是厚度介於〇·2微米 至2微米之間且材質主要包括鋁的金屬層（亦稱為鋁墊， pad)，或是厚度介於〇·2微米至2微米之間且材 質主要包括銅的金屬層（亦稱為銅墊，c〇pperpad)。此外， 當接墊16包括以電鍍製程所形成之銅金屬時，在電鍍銅的 底P下與側壁外具有一阻障層（barrier layer),此阻障層的 材質比如是鈕（Ta)或氮化鈕（TaN)。 另，開口 14a的橫向尺寸d係介於〇·5微米至2〇微米 之間或是介於20微米至200微米之間，且開口 14a的形狀 可以疋圓形、正方形、長方形或五邊以上之多邊形（例如六 邊形或八邊形）。亦即，開口 14a的形狀可以是圓形，且直 200814213 徑是介於0.5微米至20微米之間或是介於20微米至200 微米之間；或是，開口 14a的形狀可以是正方形，且一邊 長是介於0.5微米至20微米之間或是介於20微米至200 微米之間；或是，開口 14a的形狀可以是長方形，且一寬 度是介於0.5微米至20微米之間或是介於20微米至200 微米之間；或是，開口 14a的形狀可以是五邊以上之多邊 形（例如六邊形或八邊形），且一寬度是介於0.5微米至20 微米之間或是介於20微米至200微米之間，例如開口 14a f 的形狀為六邊形（或稱六角形）時，其對邊寬度是介於0.5 微米至20微米之間或是介於20微米至200微米之間。 請參閱第2B圖所示，本發明可選擇形成厚度介於0.4 微米至3微米之間的一金屬保護蓋（metal cap)18在保護層 14之一開口 14a所暴露出的一接墊16上，使接墊16免於 受到氧化而侵蝕損壞。例如，金屬保護蓋18包括厚度介於 0.01微米至0.7微米之間的一阻障層（barrier layer)位在開 口 14a所暴露出之接墊16上，以及包括厚度介於0.4微米 ^ 至2微米之間的一含鋁金屬層位在此阻障層上，其中此阻 障層比如是一鈦層、一鈦鎢合金層、一氮化鈦層、一钽層、 一氮化组層、一絡（Cr)層或一财火金屬合金層等，而含铭 金屬層則比如是一銘層、一銘-銅合金（Al-Cu alloy)層或是 一鋁矽·銅合金（Al-Si-Cu alloy)層；或者，金屬保護蓋18 為厚度介於0.4微米至2微米之間的一含鋁金屬層位在開 口 14a所暴露出之接墊16(如銅墊）上，其中含鋁金屬層比 如是一銘層、一銘-銅合金（Al-Cu alloy)層或是一銘-碎-銅 17 200814213 合金（Al-Si-Cualloy)層。 例如，當接墊16的材質主要包括銅金屬時，接墊16 上通常具有金屬保護蓋18,讓主要含有銅金屬的接墊 16(或稱為銅墊）免於受到氧化而侵蝕損壞，其中此金屬保 護蓋18包括一含组金屬層（例如一组層或一氮化组層）位在 此接塾16上，以及包括一含銘金屬層（例如一銘層或一銘 合金層）位在此含组金屬層上。 本發明係以結構20代表第2A圖與第2B圖中，保護 層14與半導體基底2之間的結構，亦即以結構20包括第 2A圖與第2B圖中的半導體元件4、線路結構6(包括圖案 化金屬層8及金屬插塞10)與介電層12等。 請參閱第3圖所示，本發明可形成厚度介於1微米至 20微米之間的一打線接墊（bonding pad)22在一開口 14a所 暴露出之一接墊16(例如鋁墊或銅墊）上，其中打線接墊22 的較佳厚度是介於3微米至5微米之間，且此打線接墊22 係作為接合一打線導線（例如金線）的打線接點。有關形成 打線接墊22在開口 14a所暴露出之接墊16上的方法，請 參閱第4圖系列的說明。另，在形成打線接墊22之後，透 過切割半導體晶圓（semiconductor wafer)，以形成複數半導 體晶片23(或稱為積體電路晶片，IC chip)。 請參閱第4A圖所示，形成厚度介於0.01微米至0.7 微米之間（較佳則是介於0.03微米至0.7微米之間）的一黏 著/阻障層（adhesion/barrier layer)24在保護層14上與開口 14a所暴露出之接墊16上，其中此接墊16可以是鋁墊或 200814213 是銅墊。另，黏著/阻障層24的材質包括鈦、鈦鎢合金、 氮化鈦、鉻、鈕、氮化鈕或耐火金屬合金（aU〇y ^ refractQry metal)等。 例如，黏著/阻障層24可以是厚度介於0·01微米至〇 7 微米之間（較佳則是介於〇·03微米至〇·7微米之間）的一鈦 層濺鍍在保護層14上與開口 14a所暴露出之主要材質包括 鋁的接墊16(即鋁墊）上；或者，黏著/阻障層24可以是厚 度介於0.01微米至0.7微米之間（較佳則是介於〇 〇3微米 至〇·7微米之間）的一鈦鎢合金層濺鍍在保護層14上與開 口 14a所暴露出之主要材質包括鋁的接墊16上；或者，黏 著/阻障層24可以是厚度介於〇·〇1微米至0.7微米之間（較 佳則是介於0·03微米至0.7微米之間）的一氮化鈦層濺鍍在 保護層14上與開口 14a所暴露出之主要材質包括鋁的接塾 16上；或者，黏著/阻障層24可以是厚度介於0 01微米至 0.7微米之間（較佳則是介於〇·〇3微米至〇·7微米之間）的一 絡層錢鑛在保濩層14上與開口 14a所暴露出之主要材質包 括鋁的接墊16上；或者，黏著/阻障層24可以是厚度介於 0.01微米至0.7微米之間（較佳則是介於〇· 〇3微米至〇·7微 米之間）的一氮化鈕層濺鍍在保護層14上與開口 1乜所暴 露出之主要材質包括鋁的接墊16上；或者，黏著/阻障層 24可以是厚度介於0.01微米至〇·7微米之間（較佳則是介 於0.03微米至0·7微米之間）的一组層濺鍍在保護層14上 與開口 14a所暴硌出之主要材質包括銘的接墊Μ上；或 者，黏著/阻障層24可以是厚度介於0·01微米至〇.7微米 200814213 之間（較佳則是介於〇 〇3微米至〇·7微米之間）的一耐火金 屬合金層濺鍍在保護層14上與開口 14a所暴露出之主要材 質包括鋁的接墊16上。 例如，黏著/阻障層24可以是厚度介於〇 〇1微米至〇.7 微米之間（較佳則是介於0·03微米至0.7微米之間）的一鈦 層濺鍍在保護層14上與開口 14a所暴露出之主要材質包括 銅的接墊16(即銅墊）上；或者，黏著/阻障層24可以是厚 度介於0.01微米至〇·7微米之間（較佳則是介於〇 〇3微米 至0.7微米之間）的一鈦鎢合金層濺鍍在保護層14上與開 口 14a所暴露出之主要材質包括銅的接墊16上；或者，黏 著/阻障層24可以是厚度介於〇 〇1微米至〇 7微米之間（較 佳則是介於0.03微米至〇·7微米之間）的一氮化鈦層濺鍍在 保護層14上與開口 14a所暴露出之主要材質包括銅的接墊 16上；或者，黏著/阻障層24可以是厚度介於〇 〇1微米至 0.7微米之間（較佳則是介於0 03微米至〇·7微米之間）的一 鉻層濺鍍在保護層14上與開口 14a所暴露出之主要材質包 括銅的接墊16上；或者，黏著/阻障層24可以是厚度介於 0.01微米至0·7微米之間（較佳則是介於〇 〇3微米至〇·7微 米之間）的一氮化组層濺鍍在保護層14上與開口 14a所暴 露出之主要材質包括銅的接墊16上；或者，黏著/阻障層 24可以是厚度介於0·01微米至〇·7微米之間（較佳則是介 於0·03微米至0.7微米之間）的一组層減鑛在保護層μ上 與開口 14a所暴露出之主要材質包括銅的接墊ι6上；咬 者，黏著/阻障層24可以是厚度介於0·01微米至〇·7微米 20 200814213 之間（較佳則是介於〇·〇3微米至〇·7微米之間）的一耐火金 屬合金層濺鍍在保護層14上與開口 14a所暴露出之主要材 質包括銅的接墊16上。 請參閱第4B圖所示，濺鍍厚度介於0 03微米至1微 米之間（較佳則是介於〇·〇3微米至〇·7微米之間）的一種子 層26在黏著/阻障層24上。另，種子層26亦可利用蒸鑛、 物理氣相沉積或無電電鍍（electr〇less plating)等方式形 成。由於種子層26可以有利於後續金屬層的形成，因此種 子層26的材質會隨後續金屬層的材質而有所變化，如當材 質為金(Au)的金屬層電鍍形成在種子層26上時，種子層 26的材質係以金為佳；或者，當材質為銅（cu)的金屬層電 鍍形成在種子層26上時，種子層26的材質係以銅為佳； 或者’當材質為把(palladium，Pd)的金屬層電鍍形成在種 子層26上時，種子層26的材質係以鈀為佳。 例如，當黏著/阻障層24是以濺鍍方式所形成之厚度 介於0·01微米至〇·7微米之間（較佳則是介於〇·〇3微米至 〇·7微米之間）的一鈦層時，種子層26可以是厚度介於0 〇3 微米至1微米之間（較佳則是介於〇·〇3微米至0.7微米之間） 的一金層濺鍍在此鈦層上；或是，當黏著/阻障層24是以 濺鍍方式所形成之厚度介於〇·〇 1微米至0·7微米之間（較佳 則是介於0·03微米至0·7微米之間）的一鈦鎢合金層時，種 子層24可以是厚度介於〇·〇3微米至1微米之間（較佳則是 介於0·03微米至〇·7微米之間）的一金層濺鍍在此鈦嫣合金 層上；或是，當黏著/阻障層26是以濺鍍方式所形成之厚 21 200814213 度介於〇·〇1微米至0·7微米之間（較佳則是介於〇 〇3微米 至〇·7微米之間）的一氮化鈦層時，種子層24可以是厚度 介於0.03微米至1微米之間（較佳則是介於〇 〇3微米至 微米之間）的一金層濺鍍在此氮化鈦層上；或是，當黏著/ 阻障層24是以濺鍍方式所形成之厚度介於〇 〇1微米至〇.7 微米之間（較佳則是介於0.03 微米至0.7微米之間）的一鉻 層時，種子層26可以是厚度介於〇.〇3微米至1微米之間（較 佳則是介於0.03微米至〇·7微米之間）的一金層濺鍍在此鉻 層上；或是，當黏著/阻障層24是以濺鍍方式所形成之厚 度介於（UH微米至0.7微米之間（較佳則是介於〇〇3微米 至〇·7微米之間）的一氮化鈕層時，種子層％可以是厚度 介於0.03微米至1微米之間（較佳則是介於〇 〇3微米至 微米之間）的一金層濺鍍在此氮化鈕層上；或是，當黏著/ 阻障層24是以濺鍍方式所形成之厚度介於〇 〇1微=至〇.7 微米之間(較佳則是介於0·03微米至〇·7微米之間)的一鈕 層時，種子層26可以是厚度介於〇·〇3微米至⑽米之間（較 佳則是介於0.03微米至〇·7微米之間)的一金層濺鍍在此鈕 層上；或是’當黏著/阻障層24 ^:以祕方式所形成之厚 度介於0·01微米至G.7微米之間（較佳則是介於請微米 至〇·7微米之間）的一耐火金屬合金層時，種子層％可以 是厚度介於0.03微米至！微米之間（㈣則是介於⑽微 米至0.7微米之間)的一金層濺鍍在此耐火金屬合金層上。 例如，當黏著/阻障層24是⑽鍍方式所形成之厚产 介於㈣微米至G.7微米之間（較佳則是介於㈣微^ 22 200814213 〇·7微米之間)的一鈦層時，種子層％可以是厚度介於㈣3 微米至1微米之間（較佳則是介於〇 〇3微米i 〇·7微米之間） 的一銅層雜在此鈦層上；或是，當黏著/阻障層24是以 濺鍍方式所形成之厚度介於0·01微米至〇·7微求之間（較佳 則是介於0·03微米至〇·7微米之間）的一鈦鎢合金層時，種 子層24可以是厚度介於0·03微米至1微米之間（較佳則是 ;丨於0.03微米至〇·7微米之間）的一銅層濺鍍在此鈦鎢合金 層上，或是，當黏著/阻障層26是以濺鍍方式所形成之厚 度介於0.01微米至〇·7微米之間（較佳則是介於〇 〇3微米 至〇·7微米之間）的一氮化鈦層時，種子層24可以是厚度 介於0.03微米至1微米之間（較佳則是介於〇 〇3微米至〇.7 微米之間）的一銅層濺鍍在此氮化鈦層上；或是，當黏著/ 阻障層24是以濺鍍方式所形成之厚度介於〇 〇1微米至〇 7 微米之間（較佳則是介於〇·〇3微米至0.7微米之間）的一絡 層時’種子層26可以是厚度介於0 03微米至1微米之間（較 佳則是介於〇·〇3微米至〇·7微米之間）的一銅層濺鍍在此鉻 層上；或是，當黏著/阻障層24是以濺鍍方式所形成之厚 度介於0.01微米至〇·7微米之間（較佳則是介於〇·〇3微米 至〇·7微米之間）的一氮化组層時，種子層26可以是厚度 介於0.03微米至1微米之間（較佳則是介於0·03微米至〇.7 微米之間）的一銅層濺鍍在此氮化钽層上；或是，當黏著/ 阻障層24是以濺鍍方式所形成之厚度介於〇·〇ι微米至0/7 微米之間（較佳則是介於0.03微米至0·7微米之間）的一鈕 層時，種子層26可以是厚度介於〇.〇3微米至1微米之間（較 23 200814213 =則是介於⑽微米至G7微米之間）的—銅層織錢 曰上’或是’當黏著/阻障層24是以濺鑛方式所 i 度介於0.01微米至〇 7供止> /成之厚 卞主〇.7微未之間（較佳則是介於〇 至〇.7微米之間）的一耐火金屬合金層時，種子層26 = 是厚度介於0.03微来至！微米之間（較佳則是介於〇 ^ 米至0.7微米之間）的—銅層騎在此耐火金屬合金層 例如，當黏著/阻障層24是以濺財式所形成^声 ( 介於〇.01微米至〇.7微米之間（較佳則是介於0.03微^ 〇.7微米之間)的一鈦層時’種子層26可以是厚度介於㈣3 微米至1微米之間（較佳則是介於〇〇3微米至〇7微米之 的-把層濺鍍在此鈦層上；或是，當黏著/阻障層Μ是= 減鑛方式所形成之厚度介於〇 〇1微米至〇 7微米之間（較佳 則是介於0.03微米至〇.7微米之間）的一鈦鎢合金層時，種 子層24可以是厚度介於〇 〇3微米至1微米之間（較佳則是 介於0.03微米至G.7微米之⑷的—⑽雜在此鈦鶴合金 層上，或是，當黏著/阻障層26是以濺鍍方式所形成之厚 度介於0.01微米至0.7微米之間（較佳則是介於〇〇3微米 至0.7微米之間）的一氮化鈦層時，種子層24可以是厚度 介於0.03微米至1微米之間（較佳則是介於〇 〇3微米至 微米之間）的一鈀層濺鍍在此氮化鈦層上；或是，當黏著/ 阻障層24是以濺鍍方式所形成之厚度介於0.01微米至0.7 微米之間（較佳則是介於0.03微米至〇·7微米之間）的一鉻 層時，種子層26可以是厚度介於〇.〇3微米至！微米之間（較 佳則是介於0.03微米至0.7微米之間）的一鈀層濺鍍在此鉻 24 200814213 層上；或是，當黏著/阻障層24是以濺鍍方式所形成之厚 度介於0.01微米至0.7微米之間（較佳則是介於0.03微米 至0.7微米之間）的一氮化鈕層時，種子層26可以是厚度 介於0.03微米至1微米之間（較佳則是介於0.03微米至0.7 微米之間）的一鈀層濺鍍在此氮化钽層上；或是，當黏著/ 阻障層24是以濺鍍方式所形成之厚度介於0.01微米至0.7 微米之間（較佳則是介於〇.〇3微米至0.7微米之間）的一钽 層時，種子層26可以是厚度介於0.03微米至1微米之間（較 / 佳則是介於〇.〇3微米至0.7微米之間）的一鈀層濺鍍在此鈕 層上；或是，當黏著/阻障層24是以濺鍍方式所形成之厚 度介於0.01微米至0.7微米之間（較佳則是介於0.03微米 至0.7微米之間）的一耐火金屬合金層時，種子層26可以 是厚度介於0.03微米至1微米之間（較佳則是介於0.03微 米至0.7微米之間）的一鈀層濺鍍在此耐火金屬合金層上。 請參閱第4C圖所示，旋塗（spin-on coating)厚度介於 1微米至25微米之間的一光阻層28在種子層26上，其中 、 光阻層28的較佳厚度係介於3微米至10微米之間，且光 阻層28比如是一正型（positive-type)光阻層。接著，請參 閱第4D圖所示，透過曝光（exposure)與顯影（development) 等製程圖案化光阻層28，以形成一光阻層開口 28a在光阻 層28内並暴露出位在接墊16上方的種子層26,其中在圖 案化光阻層28的過程中比如是利用一倍（IX)之曝光機 (stepper)或是一倍（IX)之對準曝光機（contact aligner)進行 曝光。此外，在顯影後可先利用電漿（例如含有氧離子之電 25 200814213 與氧離子之電漿）清 26 ,藉以去除種子層 漿或是含有氟離子濃度小於200PPM 洗光阻層開口 28a所暴露出之種子層 26上表面之光阻殘留物或其它異物。 請參閱帛4E圖所示，形成厚度介於⑽米至微米 之間的-金制30在光阻層開口 28a所暴露出之種子層 26上，其中此金屬層3〇的較佳厚度係介於3微米至^ 米之間’且金屬層30的材質包括金、鋼、錄或把。 例如’金屬層30可以是厚度介於1微米至2()微米之 間（較佳厚度則是介於3微米至5微米之間或是介於i微米 至4微米之間）的一金層電鑛在光阻層開口 28a所暴露出之 材質為金的種子層26上；或者，金屬層3〇可以是厚度介 於1微米至2G微米之間（較佳厚度則是介於3微米至5微 米之間或是介於！微米至4微米之間）的—把層電鑛在光阻 層開口 28a所暴露出之材質為㈣種子層％上；或者，金 屬層30可以是厚度介於！微米至1〇微米之間的一銅層電 鑛在光阻層開π 28a所暴露出之材f為銅的種子層％上、 厚度’丨於1微米至5微米之間的一鎳層電鍍在此銅層上以 及厚度介於1微米至5微米之間的一金層電鍍在此鎳層 上，其中銅層、鎳層與金層三者的總厚度係介於i微米至 2〇微米之間’而較佳厚度則是介於3微米至5微米之間； 或者，金屬層30可以是厚度介於1微米至13微米之間的 一銅層電鍍在光阻層開口 28a所暴露出之材質為銅的種子 層26上、厚度介於1微米至5微米之間的一鎳層電鍵在此 銅層上以及厚度介於〇.〇5微米至2微米之間的一金層無電 26 200814213 電鍍在此鎳層上，並中柏Μ /、鋼層、鎳層與金層三者的總厚 介於1微米至20微半夕„ 与又係 <做丄 未之間，而較佳厚度則是介於3微米至 5微米之間；或者，金屬展μ _ 儆木至 微乎之_ Μ 是厚度介於1微米至！〇 =間的一銅層電錢在光阻層開口、所暴露出之材質 2的種子層26上、厚度介於1微米至5微米之間的一鎳 層電鍍在此銅層上以及厘疮人 ’、 厚度；丨於1微米至5微米之間的— 鈀層電鍍在此鎳層上，甘 ^ . 其中鋼層、鎳層與鈀層三者的總厚 度係介於1微米至2〇料卓+ μ 微未之間，而較佳厚度則是介於3 微米至5微米之間；戍者 飞考金屬層30可以是厚度介於工 微米至13微米之間的一銅声 、 』層電鍍在光阻層開口 28a所暴露 出之材質為銅的種子層μ 卞層26上、厚度介於1微米至5微米之 間的一鎳層電鍍在此銅層上以及厚度介於〇〇5微米至2微 米之間的一把層無電電鑛在此鎳層上，其中銅層、鎳層與 把層三者的總厚度係介於1微米至2G微米之間，而較佳厚 度則是介於3微米至5微米之間。 請參閱第4F圖所示，在形成金屬層3〇之後，接著去 除光阻層28’而去除方式比如是利用含有氨基化合物 (amide)之有機溶劑去除光阻層28。此夕卜，在去除光阻層 28之後，可以先利用電漿（例如含有氧離子之電漿或是含 有氟離子濃度小於·ΡΡΜ純離子之㈣）清洗金屬層 3〇與種子層26，藉以去除金屬層3〇上表面與種子層％ 上表面之光阻殘留物。 繼績請參閱第4G圖所示，依序去除未在金屬層3〇下 方的種子層26與黏著/阻障層24。其中，去除未在金屬層 27 200814213 30下方的種子層26與黏著/阻障層24之方式比如是以蝕 刻方式去除，而蝕刻方式又可分為乾蝕刻與濕蝕刻兩種方 式，另乾蝕刻包括化學電漿蝕刻、濺擊蝕刻與化學氣體蝕 刻。例如在濕餘刻方面，當黏著/阻障層24為鈦鶴合金時， 可使用含有雙氧水之溶液蝕刻去除，而當黏著/阻障層24 為鈦時，可使用含氰氟酸的溶液蝕刻去除，另當種子層26 為金時，可利用含有碘之蝕刻液（例如含有碘化鉀之蝕刻液） 蝕刻去除，而當種子層26為銅時，可利用含有氫氧化銨 (NH4OH)之蝕刻液蝕刻去除；在乾蝕刻方面，當黏著/阻障 層24為鈦或鈦鎢合金時，可使用含氯的電漿蝕刻去除或是 利用反應性離子蝕刻（RIE)製程蝕刻去除，另當種子層26 為金時，可使用離子研磨（ion milling)製程蝕刻去除或是利 用氬氣濺擊餘刻（Ar sputtering etching)製程餘刻去除。 因此，本發明可形成一打線接墊22在一開口 14a所暴 露出之一接墊16上，且打線接墊22是由一黏著/阻障層 24、位在黏著/阻障層24上的一種子層26與位在種子層 26上的一金屬層30所構成。又，打線接墊22的材質包括 鈦、鈦鶴合金、氮化鈦、鉻、钽、氮化组、金、銅、鎳或 把等。因此，透過上述形成打線接墊22的方式，本發明之 打線接墊22可以是下列所述之形式。 例如，打線接墊22包括厚度介於0.01微米至0.7微 米之間（較佳則是介於0.03微米至0.7微米之間）的一含鈦 金屬層（如一鈦層、一氮化鈦層或一鈦鶴合金層）位在開口 14a所暴露出之材質主要包括銅的接墊16(或稱為銅墊） 28 200814213 上、厚度介於0.03微米至1微米之間（較佳則是介於0·03 微米至0.7微米之間）且材質為金的一種子層位在此含鈦金 屬層（如一鈦層、一氮化鈦層或一鈦嫣合金層）上以及厚度 介於1微米至20微米之間（較佳厚度則是介於3微米至5 微米之間或是介於1微米至4微米之間）的一金層位在此種 子層上；或者，打線接墊22包括厚度介於0.01微米至0.7 微米之間（較佳則是介於0.03微米至0.7微米之間）的一含 鈦金屬層（如一鈦層、一氮化鈦層或一鈦鎢合金層）位在開 f 口 14a所暴露出之材質主要包括銅的接墊16(或稱為銅墊） 上、厚度介於0.03微米至1微米之間（較佳則是介於0.03 微米至0.7微米之間）且材質為鈀的一種子層位在此含鈦金 屬層（如一鈦層、一氮化鈦層或一鈦嫣合金層）上以及厚度 介於1微米至20微米之間（較佳厚度則是介於3微米至5 微米之間或是介於1微米至4微米之間）的一鈀層位在此種 子層上；或者，打線接墊22包括厚度介於0.01微米至0.7 微米之間（較佳則是介於〇.〇3微米至0.7微米之間）的一含 i 鈦金屬層（如一鈦層、一氮化鈦層或一鈦嫣合金層)位在開 口 14a所暴露出之材質主要包括銅的接墊16(或稱為銅墊） 上、厚度介於0.03微米至1微米之間（較佳則是介於0.03 微米至0.7微米之間）且材質為銅的一種子層位在此含鈦金 屬層（如一鈦層、一氮化鈦層或一鈦鎢合金層）上、厚度介 於1微米至10微米之間的一銅層位在此種子層上、厚度介 於1微米至5微米之間的一鎳層位在此銅層上以及厚度介 於1微米至5微米之間的一金層位在此鎳層上，且鎳層、 29 200814213 銅層與金層三者的總厚度係介於！微米至2〇微米之間，而 較佳厚度則是介於3微米至5微米之間；或者，打線接塾 22包括厚度介於0.01微米至〇·7微米之間（較佳則是介於 〇·〇3微米至0.7微米之間）的一含鈦金屬層（如一鈦層、一 氮化鈦層或一鈦鎢合金層）位在開口 14a所暴露出之材質 主要包括銅的接塾16(或稱為銅墊）上、厚度介於划3微米 至1微米之間（較佳則是介於〇·〇3微米至〇 7微米之間）且 材質為銅的一種子層位在此含鈦金屬層（如一鈦層、一氮化 鈦層或一鈦鎢合金層）上、厚度介於丨微米至1〇微米之間 的一銅層位在此種子層上、厚度介於丨微米至5微米之間 的一鎳層位在此銅層上以及厚度介於丨微米至5微米之^ 的一鈀層位在此鎳層上，且鎳層、銅層與鈀層三者的總厚 度係介於1微米至2G微米之間，而較佳厚度則是介於3 微米至5微米之間。 例如，打線接墊22包括厚度介於〇·〇1微米至〇·7微 米之間(較佳則是介於〇·03微米至〇·7微米之間)的一鉻層 位在開口 14a所暴露出之材質主要包括銅的接墊16心 為銅墊）上、厚度介於〇·03微米至！微米之間（較佳則是介 於0.03微米至〇·7微米之間）且材質為金的一種子層位在此 鉻層上以及厚度介於i微米至2()微米之間（較佳厚度則是 介於3微米至5微米之間或是介於i微米至4微米之間） 的一金層位在此種子層上；或者，打線接墊22包括厚度介 於〇·〇 1微米至0·7微米之間（較佳則是介於〇 〇3微米至^.7 微米之間）的一鉻層位在開口 14a所暴露出之材質主要包 30 200814213 括銅的接塾16(或稱為銅墊）上、厚度介於〇·〇3微米至丨微 米之間（較佳則是介於0.03微米至〇·7微米之間）且材質為 把的一種子層位在此鉻層上以及厚度介於1微米至微米 之間（較佳厚度則是介於3微米至5微米之間或是介於！微 米至4微米之間）的一把層位在此種子層上；或者，打線接 墊22包括厚度介於〇·01微米至0·7微米之間（較佳則是介 於〇· 03微米至〇·7微米之間）的一絡層位在開口 i4a所暴露 出之材質主要包括銅的接墊16(或稱為銅整）上、厚度介於 〇·〇3微米至1微米之間（較佳則是介於〇 〇3微米至〇·7微米 之間）且材質為銅的一種子層位在此鉻層上、厚度介於1微 米至10微米之間的一銅層位在此種子層上、厚度介於1 微米至5微米之間的一錄層位在此銅層上以及厚度介於1 微米至5微米之間的一金層位在此錄層上，且鎳層、銅層 與金層三者的總厚度係介於1微米至2〇微米之間，而較佳 厚度則是介於3微米至5微米之間；或者，打線接墊22 包括厚度介於0.01微米至0·7微米之間（較佳則是介於〇 〇3 微米至0.7微米之間）的一鉻層位在開口 i4a所暴露出之材 質主要包括銅的接墊16(或稱為銅墊）上、厚度介於0 03微 米至1微米之間（較佳則是介於〇·〇3微米至〇·7微米之間） 且材質為銅的一種子層位在此鉻層上、厚度介於1微米至 1〇微米之間的一銅層位在此種子層上、厚度介於1微米至 5微米之間的一鎳層位在此銅層上以及厚度介於1微米至$ 微米之間的一把層位在此鎳層上，且鎳層、銅層與把層三 者的總厚度係介於1微米至20微米之間，而較佳厚度則是 31 200814213 介於3微米至5微米之間。 例如，打線接墊22包括厚度介於〇〇1微米至〇7微 米之間（較佳則是介於〇 〇3微米至〇 7微米之間）的一含组 金屬層（如一鈕層或一氮化鈕層）位在開口丨物所暴露出之 材質主要包括銅的接塾16(或稱為銅塾）上、厚度介於〇 〇3 微米至1微米之間(較佳則是介於〇 〇3微米至0.7微米之間) 且材質為金的一種子層位在此含鈕金屬層（如一钽層或一 乱化组層）上以及厚度介於！微米i 2〇微米之間(較佳厚度 則是介於3微米至5微米之間或是介於i微米至4微米之 間）的-金層位在此種子層上；或者，打線接墊22包括厚 度介於0.01微米至〇.7微米之間（較佳則是介於〇 〇3微米 至0.7微米之間）的一含叙金屬層（如_组層或一氮化叙層） 位在開口 14a所暴露出之材質主要包括銅的接墊16(或稱 為銅墊）上、厚度介於〇.03微米至i微米之間（較佳則是介 於〇.〇3微米至0.7微米之間）且材質為㈣一種子層位在此 含组金屬層（如-㈢或—氮化组層）上以及厚度介於i微 米至20微米之間（較佳厚度則是介於3微米至5微米之間 或是介们微米至4微米之間）的—銘層位在此種子層上. 或者’打線接墊22包括厚度介於〇.〇1微米至〇 7微米之 間(較佳則是介於0.03微米至〇·7微米之間)的一含鈕金屬 層（如-组層或一氮化组層）位在開口 W所暴露出之材質 主要包括銅的接墊16(或稱為銅幻上、厚度介於〇 〇3微米 至1微米之間（較佳則是介於0 03微米至〇7微米之間）且 材質為銅的-種子層位在此含组金屬層（如一组層或一氮 32 200814213 化鈕層）上、厚度介於1微米至1〇微米之間的一銅層位在 此種子層上、厚度介於1微米至5微米之間的一鎳層位在 此銅層上以及厚度介於1微米至5微米之間的一金層位在 此鎳層上，且鎳層、銅層與金層三者的總厚度係介於i微 米至20微米之間，而較佳厚度則是介於3微米至5微米之 間；或者，打線接墊22包括厚度介於〇 〇1微米至〇·7微 米之間（杈佳則是介於〇·〇3微米至〇·7微米之間）的一含鈕 金屬層（如一鈕層或一氮化鈕層）位在開口 14a所暴露出之 材質主要包括銅的接墊16(或稱為銅墊）上、厚度介於〇 〇3 微米至1微米之間（較佳則是介於0 03微米至〇 7微米之間） 且材質為銅的一種子層位在此含鈕金屬層（如一鈕層或一 氮化鈕層）上、厚度介於丨微米至1〇微米之間的一銅層位 在此種子層上、厚度介於i微米至5微米之間的一鎳層位 在此銅層上以及厚度介於i微米至5微米之間的一把層位 在此錄層上，且㈣、銅層與把層三者的總厚度係介於i 微米至2G微米之間，而較佳厚度則是介於3微米至$微米 之間。 例如’打線接墊22包括厚度介於〇 〇1微米至〇 7微 米之間（較佳則是介於0.03微米至Q7微米之間）的一含欽 金屬層(如-鈦層、一氮化鈦層或一鈦鎢合金層)位在開口 …所《出之材質主要包㈣的接f 16(或稱為銘塾） 上、厚度介於G.G3微米至丨㈣之間（較佳則是介於〇 〇3 微米至0.7微米之間）且材f為金的—種子層位在此含欽金 屬層（如—鈦層、—氮化鈦層或—鈦鎢合金層）上以及厚度 33 200814213 ^於1微米至2G微米之間（較佳厚度則是介於3微米至5 微米之間或疋介於！微米至4微米之間）的一金層位在此種 子層上；或者，打線接墊22包括厚度介於〇 〇1微米至Q.7 微米之間(較佳則是介於〇〇3微求至〇·7微米之間)的一含 鈦金屬層（如-鈦層、_氮化鈦層或―鈦嫣合金層）位在開 所暴硌出之材質主要包括銘的接墊16(或稱為銘墊） 上、'厚度介於G·03微米至1微米之間（較佳則是介於0·03 微米至G.7微米之間）且材f為㈣—種子層位在此含欽金 屬日(如鈦層、一氮化鈦層或一鈦嫣合金層）上以及厚度 "於1微米至2G微米之間（較佳厚度則是介於3微米至5 微米之間或疋介於丨微米至4微米之間）的一鈀層位在此種 子層上；或者，打線接墊22包括厚度介於〇.〇1微米至〇·7 微米之間（較佳則是介於〇·〇3微米至〇·7微米之間）的一含 鈦金屬層（如一鈦層、一氮化鈦層或一鈦嫣合金層）位在開 口 Ha所暴露出之材質主要包括鋁的接墊ΐό(或稱為銘塾） 上、厚度介於〇·〇3微米至丨微米之間（較佳則是介於〇•们 微米至0.7微米之間）且材質為銅的一種子層位在此含鈦金 屬層（如一鈦層、一氮化鈦層或一鈦鎢合金層）上、厚度介 於1微米至10微米之間的一銅層位在此種子層上、厚度介 於1微米至5微米之間的一鎳層位在此鋼層上以及厚度介 於1微米至5微米之間的一金層位在此鎳層上，且鎳層、 銅層與金層三者的總厚度係介於丨微米至2〇微米之間，而 較佳厚度則是介於3微米至5微米之間；或者，打線接墊 22包括厚度介於〇 〇1微米至〇·7微米之間（較佳則是介於 34 200814213 〇·〇3微米至0.7微米之間）的一含鈦金屬層（如一鈦層、一 氮化鈦層或一鈦鎢合金層）位在開口 14a所暴露出之材質 主要包括銘的接墊16(或稱為鋁墊）上、厚度介於〇 〇3微米 至1微米之間（較佳則是介於〇·〇3微米至〇·7微米之間）且 材質為銅的一種子層位在此含鈦金屬層（如一鈦層、一氮化 鈦層或一鈦鎢合金層）上、厚度介於丨微米至1〇微米之間 的一銅層位在此種子層上、厚度介於丨微米至5微米之間 的一鎳層位在此銅層上以及厚度介於丨微米至5微米之間 的一鈀層位在此鎳層上，且鎳層、銅層與鈀層三者的總厚 度係介於1微米至20微米之間，而較佳厚度則是介於3 微米至5微米之間。 ' 例如，打線接墊22包括厚度介於〇·〇1微米至〇7微 米之間（較佳則疋介於〇·〇3微米至〇·7微米之間）的一鉻層 位在開口 14a所暴露出之材質主要包括紹的接塾叫或稱 為銘墊）上、厚度介於〇.03微米至以米之間（較佳則是介 於〇.〇3微米至〇.7㈣之間）且㈣為金的—種子層位在此 鉻層上以及厚度介於i微米至2G微米之間（較佳厚度則是 "於3微米至5微米之間或是介於i微米至4微米之間） 的-金層位在此種子層上；或者，打線接墊22包括厚产介 於〇.〇1微米至〇.7微米之間（較佳則是介於0.03微来至0.7 微米之間）的-鉻層位在開σ…所暴露出之材質主要包 括銘的接塾16(或稱為紹塾）上、厚度介於0.03微米至i微 米之間（較佳則是介於〇.〇3微米至G 7微米之間）且材質為 纪的-種子層位在此鉻層上以及厚度介於m米至微米 35 200814213 之間（較佳厚度則是介於3微米至5微米之間或是介於1微 米至4微米之間）的一鈀層位在此種子層上；或者，打線接 墊22包括厚度介於0·01微米至〇 7微米之間（較佳則是介 於〇·〇3微米至〇·7微米之間）的一鉻層位在開口 所暴露 出之材質主要包括鋁的接墊16(或稱為鋁墊）上、厚度介於 0·03微米至1微米之間（較佳則是介於〇〇3微米至〇·7微米 之間）且材質為銅的一種子層位在此鉻層上、厚度介於i微 米至10微米之間的一銅層位在此種子層上、厚度介於工 微米至5微米之間的一鎳層位在此銅層上以及厚度介於^ 微米至5微米之間的—金層位在此鎳層上，且錄層、銅層 與金層三者的總厚度係介於1微米至20微米之間，而較^ 厚度則是介於3微米至5微米之間；或者，打線接塾^ 包括厚度介於0·01微米至〇.7微米之間（較佳則是介於〇〇3 微米至0.7微米之間）的一鉻層位在開口 W所暴露出之材 貝主要匕括|呂的接墊16(或稱為銘塾）上、厚度介於〇〇3微 米至1微米之間（較佳則是介於0·03微米至0·7微米之間） 且材質為銅的-種子層位在此鉻層上、厚度介於i微米至 微米之間的一銅層位在此種子層上、厚度介於i微米至 5微米之間的-鎳層位在此銅層上以及厚度介於丨微米至5 微米之間的一鈀層位在此鎳層上，且鎳層、銅層與鈀層三 者的總厚度係介於i微米至2G微米之間，而較佳厚度則是 介於3微米至5微米之間。 ,如打線接墊22包括厚度介於〇 〇1微米至ο·?微 米之間（較佳則是介於0.〇3微米至0.7微米之間）的一含鈕 36 200814213 金屬層（如一鈕層或一氮化鈕層）位在開口 14a所暴露出之 材質主要包括鋁的接墊16(或稱為鋁墊）上、厚度介於〇·们 微米至1微米之間（較佳則是介於G G3微米至^微米之間） ，材質為金的一種子層位在此含鈕金屬層（如一鈕層或一 氮化鈕層）上以及厚度介於i微米至2〇微米之間（較佳厚度 則是介於3微米至5微米之間或是介於心米^微米Z 間）的-金層位在此種子層上；或者，打線接墊22包括厚 度介於0.01微米至〇·7微米之間（較佳則是介於〇 〇3微米 至〇·7微米之間）的一含组金屬層（如一組層或一氮化组層） 位在開口 14a所暴露出之材質主要包括銘的接塾16(或稱 為銘墊）上、#度介於0·03微米i !微米之間（較佳則是介 於〇·〇3微米至〇·7微米之間）且材質為把的一種子層位在此 含艇金屬層（如-㈣或—氮化纽層）上以及厚度介於i微 米至20微米之間（較佳厚度則是介於3微米纟5微米之間 或是介於1微米至4微米之間）的一鈀層位在此種子層上； 或者，打線触22 &括厚度介於〇·〇1微米至〇·7微曰米之 間（較佳則疋介於〇 〇3微米至〇·7微米之間）的一含鈕金屬 層（如一钽層或一氮化鈕層）位在開口 14a所暴露出之材質 主要包括㈣接墊16(或稱為銘墊）上、厚度介於G.03微米 至1微米之間（較佳則是介於〇·〇3微米至0.7微米之間）且 材質為銅的一種子層位在此含鈕金屬層（如一鈕層或一氮 化组層）上、厚度介於i微米至1〇微米之間的一銅層位在 此種子層上、厚度介於！微米至5微米之間的一鎳層位在 此銅層上以及厚度介於！微米至5微米之間的一金層位在 37 200814213 、鎳€上且錄層、銅層與金層三者的總厚度係、介於1微 米至2〇«之間’而較佳厚度則是介於3微米至5微米之 間；或者，打線接墊22包括厚度介於〇.〇1微米至〇·7微 米之間（較佳則是介於0.03微米至〇7微米之間）的一含组 金屬層（如-组層或-氮化组層）位在開口 W所暴露出之 材質主要包括銘的接墊16(或稱為紹墊）上、厚度介於〇 〇3 微米至1微米之間(較佳則是介於0 03微米至〇 7微米之間) 且材質為銅的一種子層位在此含鈕金屬層（如一钽層或一 氮化钽層）上、厚度介於〗微米至1〇微米之間的一銅層位 在此種子層上、厚度介於i微米至5微米之間的一錄層位 在此銅層上以及厚度介於丨微米至5微米之間的一鈀層位 在此鎳層上，且鎳層、銅層與鈀層三者的總厚度係介於丄 微米至20微米之間’而較佳厚度則是介於3微米至5微米 之間。 接著，於完成打線接墊22之後，即完成由上述步驟所 形成之一半導體晶圓。再來，透過切割半導體晶圓，以形 成複數半導體晶片23，如第3圖所示。 請參閲第5A圖與第5B圖所示，本發明可形成厚度介 於1微米至20微米之間（較佳厚度則是介於3微米至5微 米之間）的一打線接墊22在一金屬保護蓋18上，且此打線 接墊22係作為接合一打線導線的打線接點，其中金屬保護 蓋18係位在一開口 14a所暴露出之一接墊16(例如銅墊） 上，且此金屬保護蓋18比如包括一含鈕金屬層（例如一鈕 層或一氮化鈕層）位在接墊16(例如銅墊）上，以及一含鋁金 38 200814213 屬層（例如一鋁層或一鋁合金層）位在此含钽金屬層上；或 者，此金屬保護蓋18包括一含|呂金屬層（例如一銘層或一 鋁合金層）位在接墊16(例如銅墊）上。有關形成打線接墊 22在金屬保護蓋18上的方法，請參閱第6圖系列的敘述。 另’在第5A圖中，打線接墊22係位在金屬保護蓋18的 全部上表面上以及位在金屬保護蓋18周圍之保護層8上； 在第5B圖中，打線接墊22係位在金屬保護蓋18的部份 上表面上。本發明在第6圖系列的說明係以「打線接墊22 位在金屬保護蓋18的全部上表面上以及位在金屬保護蓋 18周圍之保護層8上」的内容進行敘述，然熟習該技術者 當可藉由第6圖系列的說明，以「打線接墊22位在金屬保 護蓋18的部份上表面上」的方式來據以實施。此外，在形 成打線接墊22之後，透過切割半導體晶圓，以形成複數半 導體晶片31，如第5A圖與第5B圖所示。 請參閱第6A圖所示，形成厚度介於ο."微米至〇.7 微米之間（較佳則是介於0.03微米至〇·7微米之間）的一黏 著/阻障層24在保護層14上與金屬保護蓋ι8上，其中金 屬保護蓋18係位在材質主要包括銅的接墊ι6(即銅墊） 上，且此金屬保護蓋18比如包括一含组金屬層（例如一组 層或一氮化钽層）位在此材質主要包括銅的接墊16上以及 包括一含鋁金屬層（例如一鋁層或一鋁合金層）位在此含鈕 金屬層上’或者金屬保遵盡18為一含銘金屬層（例如一銘 層或一鋁合金層）位在此材質主要包括銅的接墊16上，而 黏著/阻障層24係位在含銘金屬層（例如一銘層或一銘合金 39 200814213 層）上。另，黏著/阻障層24的材質包括鈦、鈦鎢合金、氮 化欽、絡、纽、氮化组或财火金屬合金（alloy of refractory metal)等。 例如，黏著/阻障層24可以是厚度介於0.01微米至〇·7 微米之間（較佳則是介於〇·〇3微米至〇·7微米之間）的一鈦 層濺鍍在保護層14上與金屬保護蓋18上，其中金屬保護 蓋18包括一含钽金屬層（例如一钽層或一氮化鈕層）位在材 質主要包括銅的接墊16上以及一含鋁金屬層（例如一鋁層 或一鋁合金層）位在此含鈕金屬層上，或者金屬保護蓋18 為一含鋁金屬層（例如一鋁層或一鋁合金層）位在此材質主 要包括銅的接墊16上，而此鈦層係濺鍍在含鋁金屬層（例 如一銘層或一鋁合金層）上；或者，黏著/阻障層24可以是 厚度介於0·01微米至〇·7微米之間（較佳則是介於〇.〇3微 米至0.7微米之間）的一鈦嫣合金層濺鍍在保護層μ上與 金屬保護蓋18上，其中金屬保護蓋18包括一含鈕金屬層 (例如一鈕層或一氮化鈕層）位在材質主要包括銅的接墊16 上以及一含鋁金屬層（例如一鋁層或一鋁合金層）位在此含 叙金屬層上，或者金屬保護蓋18為一含鋁金屬層（例如一 鋁層或一鋁合金層）位在此材質主要包括銅的接墊16上， 而此鈦鎢合金層係濺鍍在含鋁金屬層（例如一鋁層或一鋁 合金層）上；或者，黏著/阻障層24可以是厚度介於〇〇1 微米至0.7微米之間（較佳則是介於〇 〇3微米至〇·7微米之 間）的一氮化鈦層濺鍍在保護層14上與金屬保護蓋18上， /、中金屬保護蓋18包括一含鈕金屬層（例如一鈕層或一氮 200814213 化鈕層）位在材質主要包括銅的接墊16上以及一含銘金屬 層（例如一銘層或一紹合金層）位在此含鈕金屬層上，或者 金屬保護蓋18為一含銘金屬層（例如一銘層或一紹合金層） 位在此材質主要包括銅的接墊16上，而此氮化鈦層係濺鍍 在含鋁金屬層（例如一鋁層或一鋁合金層）上；或者，黏著/ 阻障層24可以是厚度介於〇·〇1微米至〇·7徵米之間（較佳 則是介於〇·〇3微米至0.7微米之間）的一氮化钽層濺鍍在保 護層14上與金屬保護蓋18上，其中金屬保護蓋18包括一 ， 含组金屬層（例如一組層或一氮化组層）位在材質主要包括 銅的接墊16上以及一含銘金屬層（例如一銘層或一銘合金 層）位在此含钽金屬層上，或者金屬保護蓋18為一含鋁金 屬層（例如一鋁層或一鋁合金層）位在此材質主要包括銅的 接墊16上，而此氮化鈕層係濺鍍在的含鋁金屬層（例如一 鋁層或一鋁合金層）上；或者，黏著/阻障層24可以是厚度 介於0.01微米至0.7微米之間（較佳則是介於003微米至 0·7微米之間）的一组層賤鍍在保護層ι4上與金屬保護蓋 I 18上’其中金屬保遵蓋18包括一含鈕金屬層（例如一组層 或一氮化钽層）位在材質主要包括銅的接塾16上以及一含 鋁金屬層（例如一鋁層或一鋁合金層）位在此含钽金屬層 上，或者金屬保護蓋18為一含銘金屬層（例如一紹層或一 鋁合金層）位在此材質主要包括銅的接墊16上，而此钽層 係濺鍍在含鋁金屬層（例如一鋁層或一鋁合金層）上；或 者，黏著/阻障層24可以是厚度介於〇〇1微米至〇.7微米 之間（較佳則是介於0.03微米至0.7微米之間）的一耐火金 200814213 屬合金層濺鍍在保護層14上與金屬保護蓋18上，其中金 屬保護蓋18包括一含组金屬層（例如一组層或一氮化组層） 位在材質主要包括銅的接墊16上以及一含紹金屬層（例如 一鋁層或一鋁合金層）位在此含鈕金屬層上，或者金屬保護 蓋18為一含铭金屬層（例如一銘層或一紹合金層）位在此材 質主要包括銅的接墊16上，而此耐火金屬合金層係濺鍍在 含鋁金屬層（例如一鋁層或一鋁合金層）上。 請參閱第6B圖所示，濺鍍厚度介於〇·〇3微米至1微 米之間（較佳則是介於〇·〇3微米至〇·7微米之間）的一種子 層26在黏著/阻障層24上。另，種子層26亦可利用蒸鍍、 物理氣相沉積或無電電鍍（electroless plating)等方式形 成。由於種子層26可以有利於後續金屬層的形成，因此種 子層26的材質會隨後續金屬層的材質而有所變化，如當材 質為金(Au)的金屬層電鍍形成在種子層26上時，種子層 26的材質係以金為佳；或者，當材質為銅（Cu)的金屬層電 鍍幵成在種子層26上時，種子層26的材質係以銅為佳； 或者，當材質為鈀(palladium，Pd)的金屬層電鍍形成在種 子層26上時’種子層26的材質係以把為佳。 例如，當黏著/阻障層24是以濺鍍方式所形成之厚度 ^ 、〇1微米至〇·7微米之間（較佳則是介於〇 微米至 〇·7微米之間）的一鈦層時，種子I 26可以是厚度介於〇 〇3 微米至1微米之間（較佳則是介於0.03微米至〇·7微米之 的一金層錢鍍在此鈦層上；或是，當黏著/阻障層24 θ、 崎方切形成之厚度介於G.G1微米至G.7微米之間 42 200814213 則是介於0·03微米至0·7微米之間）的一鈦鎢合金層時，種 子層24可以是厚度介於0.03微米至1微米之間（較佳則是 介於0.03微米至0.7微米之間）的一金層濺鍍在此鈦鎢合金 層上；或是，當黏著/阻障層26是以濺鍍方式所形成之厚 度介於0·01微米至0.7微米之間（較佳則是介於〇· 〇3微米 至0.7微米之間）的一氮化鈦層時，種子層24可以是厚度 介於0.03微米至1微米之間（較佳則是介於〇· 〇3微米至ο.? 微米之間）的一金層濺鍍在此氮化鈦層上；或是，當黏著/ 阻障層24是以濺鍍方式所形成之厚度介於o oi微米至〇.7 微米之間（較佳則是介於0.03微米至〇·7微米之間）的一鉻 層時，種子層26可以是厚度介於〇·03微米至1微米之間（較 佳則疋介於0·03微米至0.7微米之間）的一金層錢鑛在此鉻 層上；或是，當黏著/阻障層24是以濺鍍方式所形成之厚 度介於0.01微米至0.7微米之間（較佳則是介於〇· 〇3微米 至0.7微米之間）的一氮化鈕層時，種子層26可以是厚度 介於0.03微米至1微米之間（較佳則是介於〇·〇3微米至ο.? 微米之間）的一金層錢鍛在此氮化鈕層上；或是，當黏著/ 阻障層24是以激鐘方式所形成之厚度介於〇〇1微米至ο.? 微米之間（較佳則是介於0.03微米至〇·7微米之間）的一组 層時，種子層26可以是厚度介於〇·〇3微米至1微米之間（較 仏則疋介於0.03微米至0.7微米之間）的一金層激鍵在此组 層上；或是，當黏著/阻障層24是以濺鍍方式所形成之厚 度介於0.01微米至0.7微米之間（較佳則是介於微米 至〇·7微米之間）的一财火金屬合金層時，種子層26可以 43 200814213 是厚度介於0.03微米至丨微米之間（較佳則是介於〇•们微 米至〇·7微米之間）的一金層濺鍍在此耐火金屬合金層上。 例如，當黏著/阻障層24是以濺鍍方式所形成之厚度 介於〇·〇1微綠〇·7微米之間（較佳則是介於〇 〇3微米至 〇·7微米之間）的一鈦層時，種子層％可以是厚度介於〇·们 微米至1微米之間（較佳則是介於〇 〇3微米至〇·7微米之間） 的一銅層濺鍍在此鈦層上；或是，當黏著/阻障層24是以 濺鍍方式所形成之厚度介於〇 〇1微米至〇·7微米之間（較佳 則是介於0.03微米至〇·7微米之間）的一鈦鎢合金層時，種 子層24可以是厚度介於0 〇3微米至丨微米之間（較佳則是 介於0.03微米至0.7微米之間）的一銅層濺鍍在此鈦鎢合金 層上；或是，當黏著/阻障層26是以濺鍍方式所形成之厚 度介於0.01微米至0.7微米之間（較佳則是介於〇 〇3微米 至〇·7微米之間）的一氮化鈦層時，種子層24可以是厚度 介於0.03微米至1微米之間（較佳則是介於〇 〇3微米至〇 7 微米之間）的一銅層濺鍍在此氮化鈦層上；或是，當黏著/ 阻障層24是以錢鍵方式所形成之厚度介於〇.〇丨微米至ο.? 微米之間（較佳則是介於0.03微米至0.7微米之間）的一鉻 層時，種子層26可以是厚度介於〇·〇3微米至1微米之間（較 佳則是介於〇·〇3微米至0.7微米之間）的一銅層濺鍍在此鉻 層上；或是，當黏著/阻障層24是以濺鍍方式所形成之厚 度介於0·01微米至0.7微米之間（較佳則是介於〇·〇3微米 至0·7微米之間）的一氮化鈕層時，種子層26可以是厚度 介於0.03微米至1微米之間（較佳則是介於〇.〇3微米至0.7 44 200814213 微米之間）的一銅層濺鍍在此氮化鈕層上；或是，當黏著/ 阻障層24是以濺鍍方式所形成之厚度介於〇 〇1微米至〇 7 微米之間（較佳則是介於0.03微米至〇·7微米之間）的一鈕 層時，種子層26可以是厚度介於0·03微米至！微米之間（較 佳則是介於0.03微米至0.7微米之間）的一銅層濺鍍在此鈕 層上；或是，當黏著/阻障層24是以濺鍍方式所形成之厚 度介於〇·〇1微米至0.7微米之間（較佳則是介於〇 〇3微米 至0.7微米之間）的一耐火金屬合金層時，種子層26可以 是厚度介於0·03微米至1微米之間（較佳則是介於〇 〇3微 米至0·7微米之間）的一銅層濺鍍在此耐火金屬合金層上。 例如，當黏著/阻障層24是以濺鍍方式所形成之厚度 介於0.01微米至0.7微米之間（較佳則是介於〇 〇3微米2 0.7微米之間）的一鈦層時，種子層26可以是厚度介於〇•们 微米至1微米之間（較佳則是介於0 03微米至〇 7微米之間） 的一鈀層濺鍍在此鈦層上；或是，當黏著/阻障層24是^ 激鍍方式所形成之厚度介於〇·〇1微米至〇·7微米之間（較佳 則是介於0.03微米至〇·7微米之間）的一鈦鎢合金層時，種 子層24可料厚度介於⑽微米至w米之間（較佳則是 介於0·03微米至〇·7微米之間）的一把層濺鍍在此鈦鶴合金 層上；或是’當黏著/阻障層26是以濺鍍方式所形成之厚 度介於〇·〇1微米至〇·7微米之間（較佳則是介於〇 〇3微米 至0·7微米之間）的一氮化鈦層時，種子層24可以是厚度 介於0.03微米i 1微#之間（較佳則是介於〇 〇3微米至〇 微米之間）的一鈀層濺鍍在此氮化鈦層上；或是，當黏著/ 45 200814213 阻障層24是以濺鍍方式所形成之厚度介於0.01微米至0.7 微米之間（較佳則是介於〇.〇3微米至0.7微米之間）的一鉻 層時，種子層26可以是厚度介於0.03微米至1微米之間（較 佳則是介於0.03微米至0.7微米之間）的一鈀層濺鍍在此鉻 層上；或是，當黏著/阻障層24是以濺鍍方式所形成之厚 度介於0.01微米至0.7微米之間（較佳則是介於0.03微米 至0.7微米之間）的一氮化鈕層時，種子層26可以是厚度 介於0.03微米至1微米之間（較佳則是介於0.03微米至0.7 / 微米之間）的一鈀層濺鍍在此氮化钽層上；或是，當黏著/ 阻障層24是以濺鍍方式所形成之厚度介於0.01微米至0.7 微米之間（較佳則是介於〇.〇3微米至0.7微米之間）的一鈕 層時，種子層26可以是厚度介於0.03微米至1微米之間（較 佳則是介於〇.〇3微米至0.7微米之間）的一鈀層濺鍍在此鈕 層上；或是，當黏著/阻障層24是以濺鍍方式所形成之厚 度介於0.01微米至0.7微米之間（較佳則是介於0.03微米 至0.7微米之間）的一耐火金屬合金層時，種子層26可以 L 是厚度介於〇.〇3微米至1微米之間（較佳則是介於0.03微 米至0.7微米之間）的一 I巴層錢鑛在此财火金屬合金層上。 請參閱第6C圖所示，旋塗（spin-on coating)厚度介於 1微米至25微米之間的一光阻層28在種子層26上，其中 光阻層28的較佳厚度係介於3微米至10微米之間，且光 阻層28比如是一正型（positive-type)光阻層。接著，請參 閱第6D圖所示，透過曝光（exposure)與顯影（development) 等製程圖案化光阻層28，以形成一光阻層開口 28a在光阻 46 200814213 層28内並暴露出位在金屬保護蓋18上方的種子層％，其 中在圖案化光阻層28的過程中比如是利用—倍⑽)之曝 光機（卿㈣或是-倍⑽之對準曝光機（c〇mact吨㈣ 進行曝光jtb外’在顯影後可先利用電漿（例如含有氧離子 之電漿或疋含有氟離子濃度小於200PPM與氧離子之電漿） 清洗光阻層開口 28a所暴露出之種子層％，藉財除種子 層26上表面之光阻殘留物或其它異物。 請參㈣6E圖所示，形成厚度介於1微米至20微米 之間的—金屬I 30在光阻層開口 28a所暴露出之種子層 26上’其中此金屬層30的較佳厚度係介於3微米至5微 米之間，且金屬層3〇的材質包括金、銅、錄或把。 例如，金屬層30可以是厚度介於丨微米至2〇微米之 間（較佳厚度収介於3微米至5微米之間或是介於i微米 至4微米之間）的一金層電鍍在光阻層開口 28&所暴露出之 材質為金的種子層26上；或者，金屬層3〇可以是厚度介 於1微米至20微米之間（較佳厚度則是介於3微米至5微 米之間或是介於丨微米至4微米之間）的一鈀層電鍍在光阻 層開口 28a所暴露出之材質為鈀的種子層％上；或者，金 屬層30可以是厚度介於！微米至1〇微米之間的一銅層電 鍍在光阻層開口 28a所暴露出之材質為銅的種子層26上、 厚度介於1微米至5微米之間的一鎳層電鍍在此銅層上以 及厚度介於1微米至5微米之間的一金層電鍍在此鎳層 上，其中銅層、鎳層與金層三者的總厚度係介於丨微米至 20微米之間，而較佳厚度則是介於3微米至5微米之間； 47 200814213 或=金屬層3〇可以是厚度介於1微米至13微米之間的 ^6上、尽度介於i微米至5微米之間的_鎳層電 :層上以及厚度介於_微米至2微米之間的—金層盖電 介上，Λ中銅層、錄層與金層三者的總厚度係 ;Ι/ ρ ^至2G微米之間’而較佳厚度則是介於3微米至 ^微米之間，或者’金屬層3()可以是厚度介於！微米至 微米之間的一銅層電鍍在光阻層開口 I所暴露出之材質 為銅的種子層26上、厚度介於1微米至5微米之間的一鎳 層電鍍在此銅層上以及厚度介於i微米至5微米之間的一 把層電鑛在此鎳層上，其中銅層、鎳層與把層三者的總厚 度係’丨於1微米至2G微米之間，而較佳厚度則是介於3 微米至5微米之間；或者，金屬層3〇可以是厚度介於1 微米至13微米之間的一鋼層電鍍在光阻層開口 28&所暴露 出之材質為銅的種子層26上、厚度介於i微米至5微米之 間的一鎳層電鍍在此銅層上以及厚度介於〇 〇5微米至2微 “之門的把層無電電錄在此鎳層上，其中銅層、錄層與 鈀層三者的總厚度係介於1微米至20微米之間，而較佳厚 度則是介於3微米至5微米之間。 晴參閱第6F圖所示，在形成金屬層3〇之後，接著去 除光阻層28’而去除方式比如是利用含有氨基化合物 (arrnde)之有機溶劑去除光阻層28。此外，在去除光阻層 28之後，可以先利用電漿（例如含有氧離子之電漿或是含 有氟離子濃度小於200PPM與氧離子之電漿）清洗金屬層 48 200814213 30與種子層26,藉以去除金屬層30上表面與種子層26 上表面之光阻殘留物。 繼續請參閱第6G圖所示，依序去除未在金屬層30下 方的種子層26與黏著/阻障層24。其中，去除未在金屬層 30下方的種子層26與黏著/阻障層24之方式比如是以蝕 刻方式去除，而蝕刻方式又可分為乾蝕刻與濕蝕刻兩種方 式，另乾蝕刻包括化學電漿蝕刻、濺擊蝕刻與化學氣體蝕 刻。例如在濕餘刻方面，當黏著/阻障層24為鈦鶴合金時， 可使用含有雙氧水之溶液蝕刻去除，而當黏著/阻障層24 為鈦時，可使用含氰氟酸的溶液蝕刻去除，另當種子層26 為金時，可利用含有碘之蝕刻液（例如含有碘化鉀之蝕刻液） 蝕刻去除，而當種子層26為銅時，可利用含有氫氧化銨 (NH4OH)之蝕刻液蝕刻去除；在乾蝕刻方面，當黏著/阻障 層24為鈦或鈦鎢合金時，可使用含氣的電漿蝕刻去除或是 利用反應性離子蝕刻（RIE)製程蝕刻去除，另當種子層26 為金時，可使用離子研磨（ion milling)製程蝕刻去除或是利 用氬氣賤擊钱刻（Ar sputtering etching)製程餘刻去除。 因此，本發明可形成一打線接墊22在一金屬保護蓋 18上，且打線接墊22是由一黏著/阻障層24、位在黏著/ 阻障層24上的一種子層26與位在種子層26上的一金屬層 30所構成。又，打線接墊22的材質包括鈦、鈦鎢合金、 氮化鈦、鉻、氮化组、金、銅、鎳或Ιε等。因此，透過上 述形成打線接墊22的方式，本發明之打線接墊22可以是 下列所述之形式。 49 200814213 例如’打線接墊22包括厚度介於0.01微米至〇·7微 米之間（較佳則是介於〇·〇3微米至0.7微米之間）的一含鈦 金屬層（如一鈦層、一氮化鈦層或一鈦鎢合金層）位在金屬 保濩盍18上、厚度介於〇·〇3微米至1微米之間（較佳則是 介於0·03微米至〇·7微米之間）且材質為金的一種子層位在 此含鈦金屬層（如一鈦層、一氮化鈦層或一鈦鎢合金層）上 以及厚度介於1微米至2〇微米之間（較佳厚度則是介於3 微米至5微米之間或是介於1微米至4微米之間）的一金層 位在此種子層上，其中金屬保護蓋18係位在開口所暴 露出之材質主要包括銅的接墊16(或稱為銅墊）上；或者， 打線接墊22包括厚度介於〇〇1微米至〇7微米之間（較佳 則是介於G.G3微米至〇.7微米之間）的一含鈦金屬層 鈦層、一氮化鈦層或一鈦鎢合金層）位在金屬保護蓋a 上、厚度介於G.G3微米至1微米之間（較佳則是介於〇.03 微米至0.7微米之間）且材質為她的—種子層位在此含欽金 屬層（如-鈦層、-氮化鈦層或_鈦鶴合金層）上以及厚度 介於1微米至20微米之間（較佳厚度則是介於3微来至$ 微米之間或是介於i微米至4微米之間）的—把層位在此種 子層上，其中金屬保護蓋18係位在開口 W所暴露出之材 質主要包括銅的接塾16(或稱為銅塾）上；或者，打線接塾 22包括厚度介於0·01微米至〇·7微米之間後佳則是介於 〇·〇3微米至0.7微米之間）的一含欽金屬層（如一欽層、一 氮化鈦層或-鈦嫣合金層）位在金屬保護蓋Μ上、:产入 於請微米至i微米之間（較佳則是介於〇〇3微米至^7 50 200814213 微米之間以材質為銅的-種子層位在此含鈦金屬層（如-曰减欽層或—鈦鎢合金層）上、厚度介於^微米至 1〇微米之間的―銅層位在此種子層上、厚度介於丨微米至 5間的—鎳層位在此銅層上以及厚度介於1微米至5 微未之間的-金層位在此錄層上，且錄層、銅層與金層三 者的〜厚度係介於！微米至2()微米之間’而較佳厚度則是 介於3微米至5微米之間’其中金屬保護蓋係位在開口 1 a所暴路出之材質主要包括銅的接墊叫或稱為銅墊） 上；或者’打線接墊22包括厚度介於〇·〇1微米至0.7微 米之間（較佳則是介於G.G3微綠〇·7微米之間）的一含鈦 金屬=(如欽層、一氮化鈦層或一鈦鶴合金層）位在金屬 呆蒦蓋上厚度介於〇 〇3微米至i微米之間（較佳則是 介於〇.〇3微米至〇.7微米之間）且材f為銅的—種子層位在 此含鈦金屬層(如-鈦層、-氮化鈦層或-鈦鎢合曰金層） 上、厚度介於！微米至1α微米之間的—銅層位在此種子層 上、厚度介於i微米至5微米之間的—鎳層位在此銅層I 以及厚度介於i微米至5微米之間的層位在此^層 上，且鎳層、銅層與鈀層三者的總厚度係介於丨微米至2〇 微米之間，而較佳厚度則是介於3微米至5微米之間，其 中金屬保護蓋18係位在開口 14a所暴露出之材質主要包括 銅的接墊16(或稱為銅墊）上。 匕 例如，打線接墊22包括厚度介於〇.〇1微米至〇7微 米之間（較佳則是介於0.03微米至0.7微米之間）的一絡層 位在金屬保護蓋18上、厚度介於㈣3微米至W米之間（較 51 200814213 佳則是介於G.G3微米至G.7微米之間）且材質為金的一種子 層位在此鉻層上以及厚度介於j微米至2〇微米之間（較佳 厚度則是介於3微米至5微米之間或是介於頂米至憎 米之間)的-金層位在此種子層上，其中金屬保護蓋㈣ 位在開口 14a所暴露出之材質主要包括銅的接塾16(或稱 為銅塾）上；或者，打線接墊22包括厚度介於〇 〇1微米至 〇·7微米之間（較佳則是介於〇 〇3微米至〇·7微米之間）的一 鉻層位在金屬保護蓋18上、厚度介於0 ()3微米至！微米 之間（較佳収介於〇·()3微米至^微米之間）且材質為纪 的一種子層位在此鉻層上以及厚度介於丨微米至2〇微米之 間（較佳厚度則是介於3微米至5微米之間或是介於i微米 至4微米之間)的一鈀層位在此種子層上，其中金屬保護蓋 18係位在開口 14a所暴露出之材質主要包括銅的接墊 16(或稱為銅墊）上；或者，打線接墊22包括厚度介於〇 〇ι 微米至〇·7微米之間（較佳則是介於〇·〇3微米至0.7微米之 間）的鉻層位在金屬保護蓋18上、厚度介於0 03微米至 1 所微米之間（較佳則是介於0·03微米至〇·7微米之間）且材 貝為銅的一種子層位在此鉻層上、厚度介於丨微米至⑺ 微米之間的-銅層位在此種子層上、厚度介於i微米至5 微米之間的—錄層位在此銅層上以及厚度介於1微米至5 微米之間的-金層位在此鎳層上，且錄層、銅層與金層三 者的總厚度係介於i微米至2〇微米之間，而較佳厚度則是 介於3微米至5微米之間，其中金屬保護蓋18係位在開口 14a所暴路出之材質主要包括銅的接墊16(或稱為銅墊） 52 200814213 上；或者，打線接墊22包括厚度介於〇 〇1微米至〇·7微 米之間（較佳則是介於0.03微米至〇·7微米之間）的一鉻層 位在金屬保護蓋18上、厚度介於〇 〇3微米至丨微米之間（車^ 佳則是介於0.03微米至〇·7微米之間）且材質為銅的一種子 層位在此鉻層上、厚度介於丨微米至1〇微米之間的一鋼層 位在此種子層上、厚度介於i微米至5微米之間的一錄層 位在此銅層上以及厚度介於丨微米至5微米之間的—把層 位在此鎳層上’且鎳層、銅層與把層三者的總厚度係介於 1微米至2G微米之間，而較佳厚度則是介於3微米至$微 米之間’其中金屬保護蓋18係位在開口丨乜所暴露出之材 質主要包括銅的接墊16(或稱為鋼墊）上。 例如，打線接墊22包括厚度介於〇·〇1微米至〇·7微 米之間(較佳則是介於〇 〇3微米至〇·7微米之間)的一含鈕 金屬層（例如-组層或_氮化组層）位在金屬保護蓋Μ上、 厚度介於0.03微米至！微米之間（較佳則是介於〇〇3微米 至〇·7微米之間）且材f為金的—種子層位在此含组金屬層 (例如纽層或一氮化组層）上以及厚度介於1微米至20微 米之間（較佳厚度則是介於3微米至5微米之間或是介於^ =至4微米之間）的-金層位在此種子層上，其中金屬保 ~ 8係位在開口 14a所暴露出之材質主要包括銅的接墊 /(或稱為銅塾）上；或者，打線接塾22包括厚度介於〇.〇1 ，米、至〇·7微米之間（較佳則是介於〇·〇3微米至0.7微米之 )的3鈕金屬層（例如一鈕層或一氮化鈕層）位在金屬 保護蓋18上、厚度介於〇·〇3微米至⑽米之間（較佳則是 53 200814213 "於0·03微米至〇·7微米之間）且材質為把的一種子層位在 此含鈕金屬層（例如一鈕層或一氮化鈕層）上以及厚度介於 1微米至20微米之間（較佳厚度則是介於3微米至$微米 之間或是介於1微米至4微米之間）的一鈀層位在此種子層 上，其中金屬保護蓋18係位在開口 14a所暴露出之材質主 要包括銅的接墊16(或稱為銅墊）上；或者，打線接墊22 包括厚度介於〇·〇1微米至〇·7微米之間（較佳則是介於〇〇3 微米至0·7微米之間）的一含鈕金屬層（例如一鈕層或一氮 化鈕層）位在金屬保護蓋18上、厚度介於〇〇3微米至丨微 米之間（較佳則是介於〇·03微米至〇·7微米之間）且材質為 銅的一種子層位在此含鈕金屬層（例如一鈕層或一氮化鈕 層）上、厚度介於1微米至10微米之間的一銅層位在此種 子層上、厚度介於i微米至5微米之間的—鎳層位在此銅 層上以及厚度介於1微米至5微米之間的-金層位在此鎳 層上’且錄層、銅層與金層三者的總厚度係介於1微米至 2〇微米之間’而較佳厚度則是介於3微米至5微米之間， 其中金屬保護蓋18係位在開口 14a所暴露出之材質主要包 括銅的接墊16(或稱為銅塾）上；或者，打線接墊22包括厚 度介於0.01微米至0.7微米之間（較佳則是介於〇 微米 至〇·7微米之間)的一含鈕金屬層(例如一鈕層或一氮化鈕 層)位在金屬保護蓋18上、厚度介於〇 〇3微米至i微米之 間（較佳収介於0.03微米至0·7微米之_材質為銅的 -種子層位在此含鈕金屬層(例如一钽層或一氮化鈕層） 上、厚度介於1微米至1G微米之間的-銅層位在此種子曰層 54 200814213 上、厚度介於1微米至5微米之間的一鎳層位在此銅層上 以及厚度介於1微米至5微米之間的—㈣位在此二層 上，且鎳層、銅層與鈀層三者的總厚度係介於丨微米至^ 微米之間，而較佳厚度則是介於3微米至5微米之間，其 中金屬保護蓋18係位在開口 14a所暴露出之材質主^包括 銅的接墊16(或稱為銅墊）上。 接著，於完成打線接墊22之後，即完成由上述步驟所 形成之一半導體晶圓。再來，透過切割半導體晶圓，以形 成複數半導體晶片31，如第5 A圖所示。Chemical Vapor Deposition (PECVD) forms a layer of bismuth oxynitride between 0.05 microns and 0.15 microns on the yttrium oxide layer, followed by chemical vapor deposition (CVD) to form a thickness of 〇·2 A layer of tantalum nitride between micrometers and 1⁄2 micrometer is on the hafnium oxynitride layer. The second method of fabricating the protective layer 14 is to first form a layer of niobium oxynitride having a thickness between 〇.05 μm and 〇15 μm by chemical vapor deposition (CVD), and continue to form by chemical vapor deposition (CVD). A layer of tantalum oxide having a thickness between 〇2 μm and 1.2 μm is deposited on the hafnium oxynitride layer, followed by chemical vapor deposition (CVD) to form a thickness between 〇·2 μm and 12 μm. The tantalum nitride layer is on the tantalum oxide layer. The four methods of making the compliant layer 14 are to first form a first oxidized layer with a thickness between 〇·2 μm and 〇·5 μm by chemical vapor deposition (CVD). 200814213 Spin-coating forms a second layer of tantalum oxide between 〇·5 μm and 1 μm on the first layer of oxidized stone, followed by chemical vapor deposition (CVD) to form a thickness of 〇· A third ruthenium oxide layer between 2 microns and 〇5 microns is on the second ruthenium oxide layer and finally formed by chemical vapor deposition (CVD) to a thickness between 〇·2 μm and ι·2 μm. A layer of tantalum nitride is on the third layer of tantalum oxide. The fifth method for forming the protective layer 14 is to first form a oxidized thickness between 5·5 μm and 2 μm by using High Density Plasma Chemical Vapor Deposition (HDP-CVD). The tantalum layer is then chemically vapor deposited (CVD) to form a tantalum nitride layer having a thickness between 0. 2 microns and 1.2 microns on the tantalum oxide layer. A sixth method of forming the protective layer 14 is to first form an undoped bismuth glass layer (a) having a thickness of between 微米 2 μm and 3 μm (ie, silicate glass 'USG), and continue to form, for example, tetraethoxy stone. An insulating layer having a thickness of between 5·5 μm and 3 μm, such as shochu, boron bowl, or bismuth glass (psg), on the undoped yttrium glass layer, followed by chemical gas Phase deposition (CVD) forms a nitride layer with a thickness between 2 μm and 12 μm on the insulating layer. The seventh method of forming the protective layer 14 is to selectively utilize chemical vapor deposition (CVD). Forming a first layer of bismuth oxynitride having a thickness between 〇〇5 μm and 〇15 μm, and continuing to form a ruthenium oxide layer having a thickness of between 0.2 μm and μm by chemical vapor deposition (CVD). On the niobium oxynitride layer, a second layer of bismuth oxynitride having a thickness of between 0.05 μm and 0·15 μm can be selectively applied to the ruthenium oxide layer by chemical vapor deposition (cvd)b 200814213. To form a thickness between 0.2 microns and 1.2 microns using chemical vapor deposition (CVD) An intervening layer of tantalum nitride on the second layer of niobium oxynitride or on the layer of tantalum oxide, followed by selective chemical vapor deposition (CVD) to form a third thickness between 0.05 microns and 0.15 microns The ruthenium oxynitride layer is on the tantalum nitride layer, and finally a chemical vapor deposition (CVD) is used to form a ruthenium oxide layer having a thickness of between 0.2 μm and 1.2 μm on the third ruthenium oxynitride layer or on the nitrogen layer. The eighth method for forming the protective layer 14 is to first form a first ruthenium oxide layer having a thickness of between 0.2 μm and 1.2 μm by chemical vapor deposition (CVD), and continue to form a thickness by spin coating. a second ruthenium oxide layer between 0.5 micrometers and 1 micrometer on the first ruthenium oxide layer, followed by chemical vapor deposition (CVD) to form a third ruthenium oxide having a thickness between 0.2 micrometers and 1.2 micrometers The layer is on the second ruthenium oxide layer, and then a ruthenium nitride layer having a thickness of between 0.2 μm and 1.2 μm is formed on the third ruthenium oxide layer by chemical vapor deposition (CVD), and finally the chemical vapor phase is used. Deposition (CVD) to form a thickness between 0.2 microns and 1.2 microns The yttrium oxide layer is on the nitriding layer. The ninth method for forming the protective layer 14 is to first form a first thickness between 0.5 micrometers and 2 micrometers by high density plasma chemical vapor deposition (HDP-CVD). The ruthenium oxide layer continues to form a tantalum nitride layer having a thickness between 0.2 μm and 1.2 μm on the first ruthenium oxide layer by chemical vapor deposition (CVD), followed by high-density plasma chemical vapor deposition ( HDP-CVD) forms a second 15 200814213 yttria layer with a thickness between 0.5 μm and 2 μm on the tantalum nitride layer. Ten methods for making the protective layer 14 are first using chemical vapor deposition (CVD). Forming a first tantalum nitride layer having a thickness between 22 μm and 1.2 μm, and continuing to form a ruthenium oxide layer having a thickness between α·2 μm and 1.2 μm by chemical vapor deposition (CVD). On the first tantalum nitride layer, a second tantalum nitride layer having a thickness of between 2 μm and 1.2 μm is formed on the tantalum oxide layer by chemical vapor deposition (CVD). The present invention exposes one of the pads 16 of the line structure 6 through an opening 14a in the protective layer 14. The thickness t4 of the pad 16 is, for example, between 〇4 μm and 3 μm or between 〇 • Between 2 microns and 2 microns. The method of forming the pad is, for example, forming a metal or aluminum alloy as a pad 16 (having a thickness of, for example, between 2 μm and 2 μm) by a sputtering process, or forming copper as a pad 16 by an electroplating process. (The thickness is, for example, between G. 2 microns and 2 microns). Therefore, the pad 16 may be a metal layer (also referred to as an aluminum pad) having a thickness of between 2 μm and 2 μm and a material mainly comprising aluminum, or a thickness of between 2 μm and 2 μm. The material mainly consists of a copper metal layer (also known as a copper pad, c〇pperpad). In addition, when the pad 16 includes copper metal formed by an electroplating process, a barrier layer is disposed under the bottom P of the electroplated copper and outside the sidewall, and the material of the barrier layer is, for example, a button (Ta) or Nitride button (TaN). In addition, the lateral dimension d of the opening 14a is between 5·5 μm and 2 μm or between 20 μm and 200 μm, and the shape of the opening 14a can be round, square, rectangular or more than five sides. A polygon (such as a hexagon or an octagon). That is, the shape of the opening 14a may be circular, and the diameter of the straight 200814213 is between 0.5 micrometers and 20 micrometers or between 20 micrometers and 200 micrometers; or the shape of the opening 14a may be square, and One side is between 0.5 micrometers and 20 micrometers or between 20 micrometers and 200 micrometers; or the opening 14a may be rectangular in shape and a width of between 0.5 micrometers and 20 micrometers or Between 20 micrometers and 200 micrometers; or the shape of the opening 14a may be a polygon of five or more sides (for example, a hexagon or an octagon), and a width of between 0.5 micrometers and 20 micrometers or Between 20 micrometers and 200 micrometers, for example, when the shape of the opening 14a f is hexagonal (or hexagonal), the width of the opposite side is between 0.5 micrometers and 20 micrometers or between 20 micrometers and 200 micrometers. Between microns. Referring to FIG. 2B, the present invention can optionally form a metal cap 18 having a thickness between 0.4 micrometers and 3 micrometers on a pad 16 exposed by one of the openings 14a of the protective layer 14. The pad 16 is protected from oxidation and damage. For example, the metal protective cover 18 includes a barrier layer having a thickness between 0.01 micrometers and 0.7 micrometers on the pads 16 exposed by the openings 14a, and including a thickness between 0.4 micrometers and 2 micrometers. An aluminum-containing metal layer is disposed on the barrier layer, wherein the barrier layer is, for example, a titanium layer, a titanium-tungsten alloy layer, a titanium nitride layer, a tantalum layer, a nitride layer, and a layer. a layer of (Cr) or a metal alloy layer, and a layer containing a metal such as a layer, an Al-Cu alloy or an aluminum-copper alloy (Al-Si) a layer of -Cu alloy; or, the metal protective cover 18 is an aluminum-containing metal layer having a thickness of between 0.4 μm and 2 μm on the pad 16 (such as a copper pad) exposed by the opening 14a, wherein the aluminum layer is contained therein. The metal layer is, for example, a layer of inscription, an Al-Cu alloy layer or a layer of Al-Si-Cualloy. For example, when the material of the pad 16 mainly includes copper metal, the pad 16 usually has a metal protective cover 18, so that the pad 16 (or copper pad) mainly containing copper metal is protected from oxidation and erosion. The metal protective cover 18 includes a metal layer (for example, a set of layers or a nitride layer) on the interface 16, and includes a layer containing a metal layer (for example, a layer of a layer or an alloy layer). Here, the metal layer is included. In the present invention, the structure 20 represents the structure between the protective layer 14 and the semiconductor substrate 2 in FIGS. 2A and 2B, that is, the structure 20 includes the semiconductor element 4 and the line structure 6 in FIGS. 2A and 2B. (including patterned metal layer 8 and metal plug 10) and dielectric layer 12 and the like. Referring to FIG. 3, the present invention can form a bonding pad 22 having a thickness between 1 micrometer and 20 micrometers, and a pad 16 (for example, an aluminum pad or copper) exposed in an opening 14a. The pad has a preferred thickness of between 3 micrometers and 5 micrometers, and the wire bonding pad 22 serves as a wire bonding junction for bonding a wire conductor such as a gold wire. For a method of forming the wire bonding pad 22 on the pad 16 exposed by the opening 14a, refer to the description of the series of Fig. 4. Further, after the wire bonding pads 22 are formed, a semiconductor wafer is cut to form a plurality of semiconductor wafers 23 (or IC chips). Referring to FIG. 4A, an adhesion/barrier layer 24 having a thickness between 0.01 micrometers and 0.7 micrometers (preferably between 0.03 micrometers and 0.7 micrometers) is formed on the protective layer. 14 is on the pad 16 exposed by the opening 14a, wherein the pad 16 may be an aluminum pad or 200814213 is a copper pad. In addition, the material of the adhesion/barrier layer 24 includes titanium, titanium tungsten alloy, titanium nitride, chromium, a button, a nitride button or a refractory metal alloy (aU〇y ^ refractQry metal). For example, the adhesion/barrier layer 24 can be a titanium layer having a thickness between 0. 01 microns and 〇 7 microns (preferably between 〇·03 microns and 〇·7 microns). The main material exposed on the opening 14a 14 includes an aluminum pad 16 (ie, an aluminum pad); or the adhesion/barrier layer 24 may have a thickness between 0.01 micrometers and 0.7 micrometers (preferably between A titanium-tungsten alloy layer between 〇〇3 μm and 〇·7 μm is sputtered on the protective layer 14 and the main material exposed by the opening 14a includes the pad 16 of aluminum; or, the adhesion/barrier layer 24 A titanium nitride layer having a thickness of between 1 micrometer and 0.7 micrometer (preferably between 0. 03 micrometers and 0.7 micrometers) may be sputtered on the protective layer 14 and exposed by the opening 14a. The main material includes the aluminum interface 16; or the adhesion/barrier layer 24 may have a thickness between 0 01 μm and 0.7 μm (preferably between 〇·〇3 μm and 〇·7 μm). a layer of money deposit on the protective layer 14 and the opening 14a exposed to the main material comprising the aluminum pad 16; or, sticky The barrier layer 24 may be a nitride button layer having a thickness between 0.01 micrometers and 0.7 micrometers (preferably between 〇·〇3 micrometers to 〇·7 micrometers) sputtered on the protective layer 14 and The main material exposed by the opening 1 包括 includes the aluminum pad 16; or the adhesive/barrier layer 24 may have a thickness of between 0.01 μm and 〇·7 μm (preferably between 0.03 μm and 0·· A set of layers sputtered between the layers of 7 microns on the protective layer 14 and the main material blasted out of the opening 14a include the pad pads of the cover; or the adhesive/barrier layer 24 may have a thickness of 0·01 A refractory metal alloy layer between micron to 〇.7 microns 200814213 (preferably between 〇〇3 microns and 〇7 microns) is sputtered onto the protective layer 14 and the main material exposed by the opening 14a includes Aluminum pads 16 are provided. For example, the adhesion/barrier layer 24 can be a titanium layer having a thickness between 〇〇1 μm and 〇.7 μm (preferably between 0.03 μm and 0.7 μm) sputtered over the protective layer 14 The main material exposed on the upper surface and the opening 14a includes a copper pad 16 (ie, a copper pad); or the adhesion/barrier layer 24 may have a thickness between 0.01 micrometers and 〇7 micrometers (preferably a titanium-tungsten alloy layer between 3 micrometers and 0.7 micrometers is sputtered on the protective layer 14 and the main material exposed by the opening 14a comprises copper pads 16; or the adhesion/barrier layer 24 may a titanium nitride layer having a thickness between 〇〇1 μm and 〇7 μm (preferably between 0.03 μm and 〇·7 μm) is sputtered on the protective layer 14 and exposed by the opening 14a. The main material comprises copper pads 16; alternatively, the adhesion/barrier layer 24 may have a thickness between 〇〇1 μm and 0.7 μm (preferably between 0 03 μm and 〇·7 μm). a chrome layer is sputtered on the protective layer 14 and the main material exposed by the opening 14a comprises a copper pad 16; or, a sticky The barrier layer 24 may be a nitride layer deposited on the protective layer 14 having a thickness of between 0.01 micrometers and 0.7 micrometers (preferably between 〇〇3 micrometers and 〇7 micrometers). The main material exposed to the opening 14a includes a copper pad 16; or the adhesion/barrier layer 24 may have a thickness between 0. 01 micrometers and 〇 7 micrometers (preferably between 0 and 03). A layer of layer of ore reduction between micrometers and 0.7 micrometers is exposed on the protective layer μ and the main material exposed by the opening 14a includes a copper pad ι6; the bite, the adhesion/barrier layer 24 may have a thickness of 0 A refractory metal alloy layer is sputtered onto the protective layer 14 and exposed by the opening 14a between 01 micrometers to 〇7 micrometers 20 200814213 (preferably between 〇·〇3 micrometers to 〇·7 micrometers) The main material includes copper pads 16. Referring to Figure 4B, a sub-layer 26 of sputter thickness between 0 03 microns and 1 micron (preferably between 〇·〇3 microns and 〇·7 microns) is in the adhesion/barrier On layer 24. Alternatively, the seed layer 26 may be formed by means of steaming, physical vapor deposition or electroless plating. Since the seed layer 26 can facilitate the formation of the subsequent metal layer, the material of the seed layer 26 may vary depending on the material of the subsequent metal layer, such as when a metal layer of gold (Au) is electroplated on the seed layer 26. The material of the seed layer 26 is preferably gold; or when the metal layer of copper (cu) is plated on the seed layer 26, the material of the seed layer 26 is preferably copper; or 'when the material is When the metal layer of (palladium, Pd) is electroplated on the seed layer 26, the material of the seed layer 26 is preferably palladium. For example, when the adhesion/barrier layer 24 is formed by sputtering, the thickness is between 0. 01 micrometers and 〇 7 micrometers (preferably between 〇·〇3 micrometers to 〇·7 micrometers). In the case of a titanium layer, the seed layer 26 may be a gold layer having a thickness between 0 〇 3 μm and 1 μm (preferably between 微米·〇3 μm and 0.7 μm). Or; when the adhesion/barrier layer 24 is formed by sputtering, the thickness is between 1 micrometer and 0. 7 micrometers (preferably between 0. 03 micrometers and 0. 7 micrometers). When a titanium-tungsten alloy layer is interposed, the seed layer 24 may be a gold having a thickness between 3 μm and 1 μm (preferably between 0·03 μm and 〇·7 μm). The layer is sputtered on the titanium-bismuth alloy layer; or, when the adhesion/barrier layer 26 is formed by sputtering, the thickness is between 21,142,113 degrees and between 1 micrometer and 0. 7 micrometers (preferably When a titanium nitride layer is between 〇〇3 μm and 7·7 μm, the seed layer 24 may have a thickness of between 0.03 μm and 1 μm (preferably between 〇〇3 μm and A gold layer between the meters is sputtered on the titanium nitride layer; or, when the adhesion/barrier layer 24 is formed by sputtering, the thickness is between 〇〇1 μm and 〇.7 μm. When a chrome layer (preferably between 0.03 microns and 0.7 microns) is used, the seed layer 26 may have a thickness between 〇3 至 and 1 μm (preferably between 0.03 μm and 〇·7). A gold layer between the micrometers is sputtered onto the chrome layer; or, when the adhesion/barrier layer 24 is formed by sputtering, the thickness is between (UH micron to 0.7 micron) (preferably When the nitride layer is between 3 micrometers and 7 micrometers, the seed layer % may be between 0.03 micrometers and 1 micrometer in thickness (preferably between 3 micrometers and micrometers). a gold layer is sputtered on the nitride button layer; or, when the adhesion/barrier layer 24 is formed by sputtering, the thickness is between 〇〇1 micrometer and 〇.7 micrometer (more) Preferably, the seed layer 26 may have a thickness between 3 micrometers and (10) meters (preferably between 0.03 micrometers). a gold layer between 7·7 microns) is sputtered on the button layer; or 'When the adhesion/barrier layer 24^: the thickness formed by the secret method is between 0. 01 micron and G. 7 micron. When a refractory metal alloy layer is between (preferably between micrometers and 77 micrometers), the seed layer % may be between 0.03 micrometers and ! micrometers ((4) is between (10) micrometers to A gold layer between 0.7 microns is sputtered onto the refractory metal alloy layer. For example, when the adhesion/barrier layer 24 is (10) plated, the thickness is between (4) and G.7 microns (more) Preferably, the thickness of the seed layer may be between (4) and 3 micrometers to 1 micrometer (preferably between 〇〇3 micrometers and ii) when a titanium layer is between (four) micro 22 22142142 and 7 micrometers. A copper layer between 7 microns) is interspersed on the titanium layer; or, when the adhesion/barrier layer 24 is formed by sputtering, the thickness is between 0. 01 micrometers and 〇·7 micro-between ( Preferably, when a titanium-tungsten alloy layer is between 0. 03 microns and 〇 7 microns, the seed layer 24 may have a thickness between 0. 03 microns and 1 micron (preferably a copper layer of between 0.03 μm and 7·7 μm is sputtered on the titanium-tungsten alloy layer, or when the adhesion/barrier layer 26 is formed by sputtering to a thickness of 0.01 μm For a titanium nitride layer between 7 microns (preferably between 〇〇3 microns and 〇7 microns), the seed layer 24 may have a thickness between 0.03 microns and 1 micron (more) a copper layer between 〇〇3 μm and 〇.7 μm is sputtered on the titanium nitride layer; or when the adhesion/barrier layer 24 is formed by sputtering. The seed layer 26 may have a thickness between 0 03 microns and 1 micron when the layer is between 1 micrometer and 7 micrometers (preferably between 3 micrometers and 0.7 micrometers). A copper layer (preferably between 微米·〇3 μm and 〇·7 μm) is sputtered onto the chrome layer; or, when the adhesion/barrier layer 24 is formed by sputtering The seed layer 26 may have a thickness of 0 when it is between 0.01 μm and 〇·7 μm (preferably between 〇·〇3 μm and 〇·7 μm). A copper layer between .03 microns and 1 micron (preferably between 0. 03 microns and 〇.7 microns) is sputtered onto the tantalum nitride layer; or, when the adhesion/barrier layer 24 is present When a thickness of 〇·〇ι μm to 0/7 μm (preferably between 0.03 μm and 0.7 μm) is formed by sputtering, the seed layer 26 may be The thickness is between 微米.〇3 μm and 1 μm (between 23 200814213 = then between (10) micron and G7 micron) - on the copper layer weaving money 'or' when the adhesive/barrier layer 24 is A refractory metal with a degree of splashing in the range of 0.01 micron to 〇7 for the & 供 成 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 For the alloy layer, the seed layer 26 = is 0.03 micron thick! The copper layer between the micrometers (preferably between 〇^ and 0.7 micrometers) rides on the refractory metal alloy layer, for example, when the adhesion/barrier layer 24 is formed by a splashing pattern (between The seed layer 26 may have a thickness between (4) and 3 microns to 1 micron when a titanium layer of between 0.1 micrometers and 〇.7 micrometers (preferably between 0.03 micrometers and 7 micrometers) is used. Preferably, it is between 〇〇3 μm and 〇7 μm - the layer is sputtered onto the titanium layer; or, when the adhesion/barrier layer is = the method of reducing the thickness is formed by 〇〇1 μm For a titanium-tungsten alloy layer between 7 microns (preferably between 0.03 microns and 〇.7 microns), the seed layer 24 may have a thickness between 〇〇3 microns and 1 micron (preferably It is between 0.03 micrometers and G.7 micrometers (4) - (10) is mixed on the titanium alloy layer, or when the adhesion/barrier layer 26 is formed by sputtering, the thickness is between 0.01 micrometers and 0.7 micrometers. When a titanium nitride layer is interposed (preferably between 〇〇3 μm and 0.7 μm), the seed layer 24 may have a thickness of between 0.03 μm and 1 μm ( a palladium layer is preferably sputtered on the titanium nitride layer between 〇〇3 micrometers to micrometers; or, when the adhesion/barrier layer 24 is formed by sputtering, the thickness is 0.01 micrometers. When a chrome layer is between 0.7 microns (preferably between 0.03 microns and 〇7 microns), the seed layer 26 may have a thickness between 〇3 ! and 3 μm (preferably a palladium layer between 0.03 micrometers and 0.7 micrometers is sputtered onto the layer of chrome 24 200814213; or, when the adhesion/barrier layer 24 is formed by sputtering, the thickness is between 0.01 micrometers and 0.7 micrometers. The seed layer 26 may have a thickness between 0.03 micrometers and 1 micrometer (preferably between 0.03 micrometers and 0.7 micrometers) when a nitride button layer is preferred (between 0.03 micrometers and 0.7 micrometers). a palladium layer is sputtered onto the tantalum nitride layer; or, when the adhesion/barrier layer 24 is sputtered, the thickness is between 0.01 micrometers and 0.7 micrometers (preferably between When a layer of between 3 micrometers and 0.7 micrometers is used, the seed layer 26 may have a thickness of between 0.03 micrometers and 1 micrometer. A palladium layer (more preferably between 3 microns and 0.7 microns) is sputtered onto the button layer; or, when the adhesion/barrier layer 24 is formed by sputtering, the thickness is When a refractory metal alloy layer is between 0.01 micrometers and 0.7 micrometers (preferably between 0.03 micrometers and 0.7 micrometers), the seed layer 26 may have a thickness of between 0.03 micrometers and 1 micrometer (preferably A palladium layer between 0.03 microns and 0.7 microns is sputtered onto the refractory metal alloy layer. See Figure 4C for a spin-on coating thickness between 1 and 25 microns. A photoresist layer 28 is on the seed layer 26, wherein the photoresist layer 28 preferably has a thickness between 3 micrometers and 10 micrometers, and the photoresist layer 28 is, for example, a positive-type photoresist layer. . Next, referring to FIG. 4D, the photoresist layer 28 is patterned by exposure and development processes to form a photoresist layer opening 28a in the photoresist layer 28 and exposed to the pads. The seed layer 26 above the 16 is exposed during the process of patterning the photoresist layer 28, for example, by using a double (IX) stepper or a double (IX) contact aligner. . In addition, after development, the plasma (for example, the plasma containing oxygen ions of 20081421313 and the plasma of oxygen ions) may be used to remove the seed layer slurry or expose the photoresist layer opening 28a containing a fluoride ion concentration of less than 200 PPM. A photoresist residue or other foreign matter on the upper surface of the seed layer 26 is formed. Referring to FIG. 4E, a gold layer 30 having a thickness between (10) meters and micrometers is formed on the seed layer 26 exposed by the photoresist layer opening 28a, wherein the preferred thickness of the metal layer 3 is Between 3 microns and ^m' and the material of the metal layer 30 comprises gold, steel, record or handle. For example, the metal layer 30 may be a gold layer having a thickness between 1 micrometer and 2 micrometers (preferably a thickness of between 3 micrometers to 5 micrometers or between 1 micrometer and 4 micrometers). The electric ore is on the gold seed layer 26 exposed by the photoresist layer opening 28a; or the metal layer 3〇 may be between 1 micrometer and 2 micrometers in thickness (preferably, the thickness is between 3 micrometers and The material exposed to the photoresist layer opening 28a is (4) the seed layer %; or the metal layer 30 may have a thickness of between 5 micrometers or between micrometers and 4 micrometers. ! A copper layer of electro-mine between micron and 1 〇 micron is plated on the photoresist layer π 28a exposed material f is a copper seed layer %, and the thickness is between 1 micrometer and 5 micrometers. A gold layer on the copper layer and between 1 micrometer and 5 micrometers is electroplated on the nickel layer, wherein the total thickness of the copper layer, the nickel layer and the gold layer is between i micrometers and 2 micrometers. The preferred thickness is between 3 micrometers and 5 micrometers; or the metal layer 30 may be a copper layer having a thickness between 1 micrometer and 13 micrometers. The plating is exposed in the photoresist layer opening 28a. a nickel layer of a copper seed layer 26 having a thickness between 1 micrometer and 5 micrometers on the copper layer and a gold layer having a thickness between 5 and 2 micrometers. 200814213 Electroplated on this nickel layer, and the total thickness of the three layers of the cypress / steel layer, the nickel layer and the gold layer is between 1 micrometer and 20 microseconds. <Do not be between, and the preferred thickness is between 3 microns and 5 microns; or, the metal spread μ _ 儆 至 微 微 Μ Μ is the thickness of 1 micron to! A copper layer of electricity between the 〇=between the photoresist layer opening, the exposed seed layer 26 of the material 2, and a nickel layer having a thickness between 1 μm and 5 μm is electroplated on the copper layer and the sore The thickness of the person's thickness, between 1 micrometer and 5 micrometers, is electroplated on the nickel layer.  The total thickness of the steel layer, the nickel layer and the palladium layer is between 1 micrometer and 2 micrometers, and the preferred thickness is between 3 micrometers and 5 micrometers; The test metal layer 30 may be a copper sound having a thickness of between micrometers and 13 micrometers. The layer is plated on the seed layer μ layer 26 of the copper material exposed by the photoresist layer opening 28a, and has a thickness of 1 A nickel layer between microns and 5 microns is electroplated on the copper layer and a layer of electroless ore having a thickness between 〇〇5 microns and 2 microns is on the nickel layer, wherein the copper layer, the nickel layer and the The total thickness of the layers is between 1 micrometer and 2 micrometers, and the preferred thickness is between 3 micrometers and 5 micrometers. Referring to Fig. 4F, after the metal layer 3 is formed, the photoresist layer 28' is removed, and the photoresist layer 28 is removed by, for example, using an organic solvent containing an amide. Further, after removing the photoresist layer 28, the metal layer 3 and the seed layer 26 may be cleaned by using a plasma (for example, a plasma containing oxygen ions or a silicon ion having a concentration of less than ΡΡΜ pure ions). The photoresist residue on the upper surface of the metal layer 3 and the upper surface of the seed layer is removed. For the succession, as shown in Fig. 4G, the seed layer 26 and the adhesion/barrier layer 24 which are not under the metal layer 3 are sequentially removed. The manner of removing the seed layer 26 and the adhesion/barrier layer 24 under the metal layer 27 200814213 30 is removed by etching, for example, and the etching method can be further divided into dry etching and wet etching, and dry etching is further performed. These include chemical plasma etching, splash etching, and chemical gas etching. For example, in the case of wet residual, when the adhesion/barrier layer 24 is a titanium alloy, it can be removed by etching with a solution containing hydrogen peroxide, and when the adhesion/barrier layer 24 is titanium, it can be etched using a solution containing cyanofluoric acid. When the seed layer 26 is gold, it can be removed by etching using an iodine-containing etching solution (for example, an etchant containing potassium iodide), and when the seed layer 26 is copper, an etching solution containing ammonium hydroxide (NH4OH) can be used. Etching removal; in dry etching, when the adhesion/barrier layer 24 is titanium or titanium tungsten alloy, it can be removed by plasma etching using chlorine or by reactive ion etching (RIE) process etching, and the seed layer is additionally used. When 26 is gold, it can be removed by ion milling or by argon etching. Therefore, the present invention can form a wire bonding pad 22 on one of the pads 16 exposed by the opening 14a, and the wire bonding pad 22 is formed by an adhesion/barrier layer 24 on the adhesion/barrier layer 24. A sub-layer 26 is formed with a metal layer 30 positioned on the seed layer 26. Further, the material of the wire bonding pad 22 includes titanium, titanium alloy, titanium nitride, chromium, niobium, nitride, gold, copper, nickel or the like. Therefore, the wire bonding pad 22 of the present invention can be in the form described below by the above-described manner of forming the wire bonding pads 22. For example, the wire bonding pad 22 includes a thickness of 0. 01 micron to 0. Between 7 micrometers (preferably between 0. 03 microns to 0. A titanium-containing metal layer (such as a titanium layer, a titanium nitride layer or a titanium alloy layer) between 7 microns) is exposed to the opening 14a. The material mainly comprises copper pads 16 (or copper pads). 28 200814213 The upper and the thickness are between 0. Between 0 microns and 1 micron (preferably between 0. 03 microns and 0. a sub-layer of between 7 microns and made of gold on the titanium-containing metal layer (such as a titanium layer, a titanium nitride layer or a titanium-niobium alloy layer) and a thickness between 1 micrometer and 20 micrometers ( Preferably, a gold layer is between 3 micrometers and 5 micrometers or between 1 micrometer and 4 micrometers on the seed layer; or the wire bonding pad 22 comprises a thickness of 0. 01 micron to 0. Between 7 microns (preferably between 0. 03 microns to 0. A titanium-containing metal layer (such as a titanium layer, a titanium nitride layer or a titanium-tungsten alloy layer) located at 7 micrometers is exposed at the opening 14a. The material mainly comprises copper pads 16 (or called Copper pad), the thickness is between 0. Between 0 microns and 1 micron (preferably between 0. 03 micron to 0. a sub-layer of between 7 microns and made of palladium on the titanium-containing metal layer (such as a titanium layer, a titanium nitride layer or a titanium-niobium alloy layer) and a thickness between 1 micrometer and 20 micrometers ( A palladium layer having a preferred thickness of between 3 micrometers and 5 micrometers or between 1 micrometer and 4 micrometers is on the seed layer; or the wire bonding pad 22 comprises a thickness of 0. 01 micron to 0. Between 7 microns (preferably between 〇. 〇 3 microns to 0. A layer of i-containing titanium metal (such as a titanium layer, a titanium nitride layer or a titanium-niobium alloy layer) of 7 μm) is exposed in the opening 14a. The material mainly comprises a copper pad 16 (or copper). Pad), the thickness is between 0. Between 0 microns and 1 micron (preferably between 0. 03 micron to 0. a sub-layer of between 7 microns and made of copper on the titanium-containing metal layer (such as a titanium layer, a titanium nitride layer or a titanium-tungsten alloy layer) having a thickness between 1 micrometer and 10 micrometers. a layer of copper on the seed layer having a thickness between 1 micrometer and 5 micrometers on the copper layer and a gold layer having a thickness between 1 micrometer and 5 micrometers in the nickel layer Upper, and the nickel layer, 29 200814213 The total thickness of the copper layer and the gold layer is between! The micron is between 2 micrometers and the thickness is preferably between 3 micrometers and 5 micrometers; or the wire bonding interface 22 comprises a thickness of 0. 01 μm to 〇·7 μm (preferably between 〇·〇3 μm to 0. A titanium-containing metal layer (such as a titanium layer, a titanium nitride layer or a titanium-tungsten alloy layer) at 7 micrometers is exposed to the opening 14a. The material mainly comprises a copper interface 16 (or a copper pad). a sub-layer having a thickness between 3 micrometers and 1 micrometer (preferably between 〇·〇3 micrometers and 〇7 micrometers) and having a material of copper containing a titanium metal layer (such as a titanium) a copper layer having a thickness between 丨 micrometers and 1 〇 micron on the layer, a titanium nitride layer or a titanium-tungsten alloy layer on the seed layer and having a thickness between 丨 micrometers and 5 micrometers A nickel layer is on the copper layer and a palladium layer having a thickness of between 丨 micrometers and 5 micrometers is on the nickel layer, and the total thickness of the nickel layer, the copper layer and the palladium layer is between 1 micrometer and Between 2G micrometers, and the preferred thickness is between 3 microns and 5 microns. For example, the wire bonding pad 22 includes a chrome layer having a thickness between 〇·〇1 μm and 〇·7 μm (preferably between 〇·03 μm and 〇·7 μm) exposed at the opening 14a. The material is mainly composed of the copper pad 16 core is copper pad), the thickness is between 〇·03 micron to! Between microns (preferably between 0. a sub-layer of gold between 0 micrometers and 〇·7 micrometers and having a material of gold on the chrome layer and having a thickness between i micrometers and 2 micrometers (preferably a thickness of between 3 micrometers and 5 micrometers) A gold layer between or between i micrometers and 4 micrometers is on the seed layer; or, the wire bonding pad 22 includes a thickness between 1 micrometer and 0. 7 micrometers (preferably It is between 〇〇3 microns to ^. A chrome layer between 7 microns) is exposed in the opening 14a. The material is mainly composed of 30,142,142 copper-bonded joints 16 (or copper pads) with a thickness between 3 μm and 丨 micron. (It is preferably between 0. Between 03 microns and 〇·7 microns) and a sub-layer of material on the chrome layer and between 1 micron and micron (preferably thickness between 3 microns and 5 microns or A layer of between (micron and 4 micrometers) is on the seed layer; or, the wire bonding pad 22 includes a thickness between 〇·01 micrometers and 0. 7 micrometers (preferably between · A layer of between 03 micrometers and 〇·7 micrometers is exposed on the opening i4a. The material mainly includes copper pads 16 (or copper), and the thickness is between 微米·〇3 μm to 1 a copper layer between the micrometers (preferably between 〇〇3 micrometers and 〇7 micrometers) and having a sub-layer of copper on the chromium layer and having a thickness between 1 micrometer and 10 micrometers a layer of gold on the seed layer having a thickness between 1 micrometer and 5 micrometers on the copper layer and a gold layer having a thickness between 1 micrometer and 5 micrometers on the recording layer, and The total thickness of the nickel layer, the copper layer and the gold layer is between 1 micrometer and 2 micrometers, and the preferred thickness is between 3 micrometers and 5 micrometers; or The wire bonding pad 22 includes a thickness of 0. 01 μm to 0·7 μm (preferably between 〇 3 μm and 0. A chrome layer between 7 microns) is exposed on the opening i4a. The material consists mainly of copper pads 16 (or copper pads) with a thickness between 0 03 microns and 1 micron (preferably a layer of copper on the chrome layer and having a thickness between 1 micrometer and 1 〇 micrometer on the seed layer a layer of nickel having a thickness between 1 micrometer and 5 micrometers on the copper layer and a layer between 1 micrometer and micrometer in thickness on the nickel layer, and the nickel layer and the copper layer The total thickness of the three layers is between 1 micrometer and 20 micrometers, and the preferred thickness is 31 200814213 between 3 micrometers and 5 micrometers. For example, the wire bonding pad 22 includes a metal containing layer (such as a button layer or a nitrogen layer) having a thickness of between 〇〇1 μm and 〇7 μm (preferably between 〇〇3 μm and 〇7 μm). The material of the button layer is exposed on the interface of the open material, which mainly includes the copper joint 16 (or copper enamel), and the thickness is between 〇〇3 μm and 1 μm (preferably between 〇〇) 3 microns to 0. A sub-layer of gold between the 7 micron) and the gold layer on the button (such as a layer of a layer or a layer of chaos) and thickness is! a gold layer between the micrometers i 2 〇 micrometers (preferably having a thickness between 3 micrometers to 5 micrometers or between i micrometers to 4 micrometers) on the seed layer; or, a wire bonding pad 22 includes a thickness of 0. 01 micron to 〇. Between 7 microns (preferably between 〇 3 microns and 0. a 7-micron layer of a metal layer (such as a layer or a nitride layer) is exposed on the opening 14a. The material mainly includes copper pads 16 (or copper pads). Yu Yu. Between 03 microns and 1 micron (preferably between 〇. 〇 3 microns to 0. Between 7 microns) and the material is (4) a sub-layer on the metal layer (such as - (three) or - nitride layer) and the thickness between i microns and 20 microns (better thickness is between The layer of inscription between 3 micrometers to 5 micrometers or between micrometers and 4 micrometers is on this seed layer.  Or 'wire pad 22' includes a thickness of 〇. 〇 1 μm to 〇 7 μm (preferably 0. A metal layer containing a button (between 03 micrometers and 7 micrometers) (such as a group layer or a nitride layer) is exposed at the opening W. The material mainly includes a copper pad 16 (or copper illusion). a seed layer having a thickness of between 〇〇3 μm and 1 μm (preferably between 0 03 μm and 〇7 μm) and having a material of copper, such as a set of layers or a layer of copper on the seed layer and having a thickness between 1 micrometer and 5 micrometers, and a layer of nickel on the seed layer, between 1 micrometer and 5 micrometers. A gold layer on the layer and between 1 micrometer and 5 micrometers in thickness is on the nickel layer, and the total thickness of the nickel layer, the copper layer and the gold layer is between i micrometers and 20 micrometers, and The preferred thickness is between 3 micrometers and 5 micrometers; or, the wire bonding pad 22 comprises a thickness between 〇〇1 micrometer and 〇·7 micrometer (or preferably 〇·〇3 micron to 〇· A button metal layer (such as a button layer or a nitride button layer) between 7 microns) is exposed in the opening 14a. The material mainly includes copper pads 16 (or copper). a sub-layer of copper having a thickness of between 〇〇3 μm and 1 μm (preferably between 0 03 μm and 〇7 μm) and having a copper layer (such as a button layer) Or a layer of copper having a thickness between 丨 micrometer and 1 〇 micron on the seed layer, and a nickel layer having a thickness between i micrometers and 5 micrometers is located on the copper layer. And a layer having a thickness between i micrometers and 5 micrometers is on the recording layer, and (4), the copper layer and the total thickness of the layer are between i micrometers and 2 micrometers, and preferably The thickness is between 3 microns and $ microns. For example, the wire bond pad 22 comprises a thickness between 〇〇1 μm and 〇7 μm (preferably between 0. A metal-containing layer (such as a titanium layer, a titanium nitride layer or a titanium-tungsten alloy layer) between 03 micrometers and Q7 micrometers is located at the opening of the material (the main material package (4) is connected to f 16 (or Called Ming 塾), the thickness is between G. G3 micron to 丨 (four) (preferably between 〇 〇 3 microns to 0. Between 7 microns) and the material f is gold - the seed layer is on the metal layer (such as - titanium layer, titanium nitride layer or titanium titanium alloy layer) and the thickness is 33 200814213 ^ at 1 micron to 2G A gold layer between the micrometers (preferably having a thickness of between 3 micrometers and 5 micrometers or between 10,000 micrometers and 4 micrometers) is on the seed layer; or the wire bonding pad 22 comprises a thickness layer. 〇〇 1 micron to Q. A titanium-containing metal layer (such as a titanium layer, a titanium nitride layer or a "titanium-niobium alloy layer" between 7 microns (preferably between 〇〇3 and 〇7 microns) is located at the opening The material of the storm is mainly composed of the pad 16 (or the inscription pad), and the thickness is between G·03 μm and 1 μm (preferably between 0·03 μm and G. Between 7 microns) and the material f is (4) - the seed layer is on the metal-containing day (such as titanium layer, titanium nitride layer or titanium-titanium alloy layer) and the thickness is between 1 micrometer and 2G micrometer. (a preferred thickness is between 3 microns and 5 microns or between 丨 and 4 microns) of a palladium layer on the seed layer; or, the wire bond pad 22 comprises a thickness of between 〇. a titanium-containing metal layer (such as a titanium layer, a titanium nitride layer or a titanium-niobium alloy) between 1 micrometer and 〇7 micrometer (preferably between 〇·〇3 micrometers and 〇7 micrometers) The material exposed in the opening Ha mainly consists of a pad ΐό (or inscription) of aluminum, and the thickness is between 微米·〇3 micrometers to 丨micrometers (preferably between 〇•micron) To 0. a sub-layer of between 7 microns and made of copper on the titanium-containing metal layer (such as a titanium layer, a titanium nitride layer or a titanium-tungsten alloy layer) having a thickness between 1 micrometer and 10 micrometers. a layer of nickel on the seed layer having a thickness between 1 micrometer and 5 micrometers on the steel layer and a gold layer having a thickness between 1 micrometer and 5 micrometers. The total thickness of the nickel layer, the copper layer and the gold layer is between 丨 micrometer and 2 〇 micrometer, and the preferred thickness is between 3 micrometers and 5 micrometers; or, the wire bonding pad 22 Including thickness between 〇〇1 μm and 〇·7 μm (preferably between 34 200814213 〇·〇3 μm to 0. A titanium-containing metal layer (such as a titanium layer, a titanium nitride layer or a titanium-tungsten alloy layer) is exposed in the opening 14a. The material mainly includes the pad 16 (or aluminum pad). a sub-layer having a thickness of between 〇〇3 μm and 1 μm (preferably between 〇·〇3 μm and 〇·7 μm) and having a material of copper containing a titanium metal layer ( a copper layer having a thickness between 丨 micron and 1 〇 micron on a titanium layer, a titanium nitride layer or a titanium tungsten alloy layer on the seed layer and having a thickness between 丨 micrometers and 5 micrometers a layer of nickel on the copper layer and a palladium layer having a thickness between 丨 micrometers and 5 micrometers on the nickel layer, and the total thickness of the nickel layer, the copper layer and the palladium layer is between 1 The micron is between 20 microns and the preferred thickness is between 3 microns and 5 microns. For example, the wire bonding pad 22 includes a chrome layer having a thickness between 〇·〇1 μm and 〇7 μm (preferably between 〇·〇3 μm and 〇·7 μm) in the opening 14a. The exposed material mainly includes the squeaking or squeaking of the material, and the thickness is between 〇. From 03 microns to meters (preferably in 〇. 〇 3 microns to 〇. Between 7 (4) and (4) is gold - the seed layer is on the chrome layer and the thickness is between i microns and 2G microns (the preferred thickness is " between 3 microns and 5 microns or between The gold layer between micrometers and 4 micrometers is on this seed layer; or, the wire bonding pad 22 includes a thick yield of 〇. 〇 1 micron to 〇. Between 7 microns (preferably between 0. 03 micro to 0. The material exposed between the chrome layer and the chrome layer at 7 μm is mainly composed of the interface 16 (or 塾 塾) of the mark, and the thickness is between 0. Between 03 micrometers and i micrometers (preferably between 〇. 〇3 μm to G 7 μm) and the material-- seed layer is on the chromium layer and the thickness is between m meters and micrometers 35 200814213 (the preferred thickness is between 3 micrometers and 5 micrometers) A palladium layer between (between 1 micrometer and 4 micrometers) is on the seed layer; or, the wire bonding pad 22 includes a thickness between 0. 01 micrometers and 〇 7 micrometers (preferably between A chrome layer of 〇·〇3 μm to 〇·7 μm) is exposed on the opening mainly including aluminum pad 16 (or aluminum pad) and has a thickness of 0·03 μm to 1 a copper layer between the micrometers (preferably between 〇〇3 micrometers and 〇7 micrometers) and having a sub-layer of copper on the chromium layer and having a thickness between i microns and 10 micrometers a layer of nickel on the seed layer having a thickness between micrometers and 5 micrometers on the copper layer and a gold layer having a thickness between 2 micrometers and 5 micrometers on the nickel layer, and The total thickness of the recording layer, the copper layer and the gold layer is between 1 micrometer and 20 micrometers, and the thickness is between 3 micrometers and 5 micrometers; or Sook contact comprises ^ a thickness between 0.5 to 01 micrometers square. Between 7 microns (preferably between 〇〇3 microns and 0. A chrome layer between 7 microns) is exposed on the opening W. The main layer of the material is 接3 μm to 1 μm. Preferably, it is between 0. 03 micrometers and 0. 7 micrometers and the material is copper. The seed layer is on the chromium layer, and a copper layer having a thickness between i micrometers to micrometers is in the seed layer. a nickel layer having a thickness between i microns and 5 microns on the copper layer and a palladium layer having a thickness between 丨 micrometers and 5 micrometers on the nickel layer, and a nickel layer and a copper layer The total thickness of the palladium layer is between i microns and 2 g microns, and the preferred thickness is between 3 microns and 5 microns. For example, the wire bonding pad 22 includes a thickness ranging from 〇 1 μm to ο·? micrometer (preferably between 0. 〇 3 microns to 0. Between the 7 micrometers) a button 36 200814213 metal layer (such as a button layer or a nitride button layer) is exposed on the opening 14a material mainly includes aluminum pad 16 (or called aluminum pad), thickness Between the micron and 1 micron (preferably between G G3 and ^ micron), a sub-layer of gold is included in the button metal layer (such as a button layer or a nitride button) a layer of gold on the layer and between -1 μm and 2 μm in thickness (preferably between 3 μm and 5 μm or between the core and μ μm) Or; the wire bonding pad 22 includes a thickness of 0. A group-containing metal layer (such as a set of layers or a nitride layer) between 01 μm and 〇·7 μm (preferably between 〇〇3 μm and 〇·7 μm) is exposed at the opening 14a The material is mainly composed of the connector 16 (or called the insole), and the # degree is between 0·03 μm and μm (preferably between 〇·〇3 μm to 〇·7 μm). And a sub-layer of material is included on the boat metal layer (such as - (four) or - nitride layer) and the thickness is between i microns and 20 microns (preferably, the thickness is between 3 microns) A palladium layer between 5 microns or between 1 micron and 4 microns is on the seed layer; or, the wire touch 22 & thickness ranges from 〇·〇1 μm to 〇·7 μm A metal layer containing a button (preferably between 〇〇3 μm and 〇7 μm) is exposed in the opening 14a. The material mainly includes (4) Pad 16 (or called the inscription pad), the thickness is between G. Between 03 microns and 1 micron (preferably between 〇·〇3 microns to 0. a sub-layer of copper between 7 microns) and having a copper layer on the button metal layer (such as a button layer or a nitride layer) having a thickness between i microns and 1 μm The thickness of this seed layer is between! A layer of nickel between microns and 5 microns is on this copper layer and is thicker! A gold layer between micrometers and 5 micrometers is at 37 200814213, nickel and the total thickness of the recording layer, the copper layer and the gold layer, between 1 micrometer and 2 〇 « and the preferred thickness is Is between 3 microns and 5 microns; or, the wire bond pad 22 includes a thickness of between 〇. 〇1 μm to 〇·7 μm (preferably between 0. A metal-containing layer (eg, a layer or a nitride layer) between 03 micrometers and 〇7 micrometers is exposed at the opening W. The material mainly includes the pad 16 (or the pad). a sub-layer of copper having a thickness of between 〇〇3 μm and 1 μm (preferably between 0 03 μm and 〇7 μm) and having a copper layer (such as a layer of germanium or a layer of copper on the tantalum nitride layer having a thickness between 〖micron and 1 〇 micron on the seed layer, and a recorded layer having a thickness between i micrometers and 5 micrometers on the copper layer And a palladium layer having a thickness between 丨 micrometers and 5 micrometers is on the nickel layer, and the total thickness of the nickel layer, the copper layer and the palladium layer is between 丄 micrometers and 20 micrometers, and preferably. The thickness is between 3 microns and 5 microns. Then, after the wire bonding pad 22 is completed, one of the semiconductor wafers formed by the above steps is completed. Further, the semiconductor wafer is cut by cutting the semiconductor wafer 23 as shown in Fig. 3. Referring to FIGS. 5A and 5B, the present invention can form a wire bonding pad 22 having a thickness of between 1 micrometer and 20 micrometers (preferably, a thickness of between 3 micrometers and 5 micrometers). a metal protection cover 18, and the wire bonding pad 22 is used as a wire bonding joint for bonding a wire bonding wire, wherein the metal protection cover 18 is fastened to a pad 16 (for example, a copper pad) exposed by an opening 14a. The metal protective cover 18 includes, for example, a button metal layer (for example, a button layer or a nitride button layer) on the pad 16 (for example, a copper pad), and an aluminum-containing gold 38 200814213 layer (for example, an aluminum layer). a layer or an aluminum alloy layer is disposed on the base metal layer; or the metal protective cover 18 includes a layer containing a metal layer (eg, a layer of a layer or an aluminum alloy layer) on the pad 16 (eg, a copper pad) )on. For the method of forming the wire bonding pad 22 on the metal protective cover 18, please refer to the description of the series of Fig. 6. In addition, in FIG. 5A, the wire bonding pads 22 are fastened on the entire upper surface of the metal protective cover 18 and on the protective layer 8 around the metal protective cover 18; in FIG. 5B, the wire bonding pads 22 are tied. On the upper surface of a portion of the metal protective cover 18. The description of the series of Fig. 6 of the present invention is described in the section "The wire bonding pad 22 is located on the entire upper surface of the metal protective cover 18 and the protective layer 8 located around the metal protective cover 18", and the technique is familiar with the technology. It can be implemented by means of the description of the series of Fig. 6, "the wire pad 22 is placed on the upper surface of the metal protection cover 18". Further, after the wire bonding pads 22 are formed, the semiconductor wafers are diced to form a plurality of semiconductor wafers 31 as shown in Figs. 5A and 5B. Please refer to Figure 6A to form a thickness of ο. "Micron to 〇. Between 7 microns (preferably between 0. An adhesive/barrier layer 24 between 03 micrometers and 77 micrometers is on the protective layer 14 and the metal protective cover ι8, wherein the metal protective cover 18 is tied to a pad ι6 (ie, a copper pad) mainly comprising copper. And the metal protective cover 18 includes, for example, a metal containing layer (for example, a layer of a layer or a layer of tantalum nitride) on the pad 16 mainly comprising copper and comprising an aluminum-containing metal layer (for example, An aluminum layer or an aluminum alloy layer is located on the button metal layer. 'Or the metal is 18 as a metal layer containing a metal layer (such as a layer of a layer or an aluminum alloy layer). The material mainly includes copper pads. On the 16th, the adhesion/barrier layer 24 is on the layer containing the metal layer (for example, a layer of a layer or a layer of alloy 39 200814213). In addition, the material of the adhesion/barrier layer 24 includes titanium, titanium tungsten alloy, nitriding, lanthanum, neon, nitriding or alloy of refractory metal. For example, the adhesion/barrier layer 24 can have a thickness of between 0. A layer of titanium between 01 μm and 〇·7 μm (preferably between 3 μm and 〇 7 μm) is sputtered onto the protective layer 14 and the metal protective cover 18, wherein the metal protective cover 18 includes a ruthenium-containing metal layer (eg, a tantalum layer or a nitride button layer) on the pad 16 of the material mainly comprising copper and an aluminum-containing metal layer (eg, an aluminum layer or an aluminum alloy layer). The metal layer on the button-containing metal layer or the metal protective cover 18 is an aluminum-containing metal layer (for example, an aluminum layer or an aluminum alloy layer) on which the material mainly includes the copper pad 16, and the titanium layer is sputtered in the An aluminum metal layer (for example, a layer of a layer or an aluminum alloy layer); or, the adhesion/barrier layer 24 may have a thickness between 0. 01 micrometers and 〇 7 micrometers (preferably between 〇. 〇3 micrometers to 0. A titanium-niobium alloy layer between 7 microns is sputtered on the protective layer μ and the metal protective cover 18, wherein the metal protective cover 18 includes a button metal layer (for example, a button layer or a nitride button layer). The material mainly includes a copper pad 16 and an aluminum-containing metal layer (for example, an aluminum layer or an aluminum alloy layer) on the metal layer, or the metal protective cover 18 is an aluminum-containing metal layer (for example, an aluminum layer). a layer or an aluminum alloy layer) on the material mainly comprising a copper pad 16, and the titanium tungsten alloy layer is sputtered on the aluminum-containing metal layer (for example, an aluminum layer or an aluminum alloy layer); or, The barrier layer 24 can have a thickness of between 〇〇1 μm and 0. A titanium nitride layer between 7 microns (preferably between 〇〇3 microns and 〇7 microns) is sputtered onto the protective layer 14 and the metal protective cover 18, and the medium metal protective cover 18 comprises A metal layer containing a button (for example, a button layer or a layer of Nitrogen 200814213) is located on the pad 16 mainly comprising copper and a layer containing a metal layer (for example, a layer of a layer or a layer of a layer of alloy). The metal layer of the button, or the metal protective cover 18 is a layer containing a metal layer (for example, a layer of a layer or a layer of a layer of alloy). The material is mainly composed of a copper pad 16, and the titanium nitride layer is sputtered. An aluminum-containing metal layer (for example, an aluminum layer or an aluminum alloy layer); or, the adhesion/barrier layer 24 may have a thickness between 〇·〇1 micrometer to 〇·7 lemma (preferably between 〇) ·〇3 microns to 0. A layer of tantalum nitride between 7 microns is sputtered onto the protective layer 14 and the metal protective cover 18, wherein the metal protective cover 18 comprises a metal layer (for example, a set of layers or a nitride layer). The pad 16 having a material mainly comprising copper and a layer containing a metal layer (for example, a layer of a layer or an alloy layer) are disposed on the base metal layer, or the metal cover 18 is an aluminum-containing metal layer (for example, An aluminum layer or an aluminum alloy layer) is disposed on the copper pad 16 and the nitride button layer is sputtered on the aluminum-containing metal layer (eg, an aluminum layer or an aluminum alloy layer); or The adhesion/barrier layer 24 can have a thickness of 0. 01 micron to 0. A set of layers between 7 microns (preferably between 003 microns and 0. 7 microns) is plated on the protective layer ι4 and on the metal protective cover I 18 'where the metal compliant cover 18 comprises a button metal a layer (for example, a set of layers or a tantalum nitride layer) is disposed on the interface 16 of the material mainly comprising copper and an aluminum-containing metal layer (for example, an aluminum layer or an aluminum alloy layer) is disposed on the base metal layer. Or the metal protective cover 18 is a layer containing a metal layer (for example, a layer or an aluminum alloy layer) on the pad 16 mainly comprising copper, and the layer is sputtered on the aluminum-containing metal layer (for example, On the aluminum layer or an aluminum alloy layer; or, the adhesion/barrier layer 24 may have a thickness of between 微米1 μm and 〇. Between 7 microns (preferably between 0. 03 microns to 0. A refractory gold 200814213 alloy layer between 7 microns) is sputtered onto the protective layer 14 and the metal protective cover 18, wherein the metal protective cover 18 comprises a metal containing layer (eg, a set of layers or a nitride layer) Positioned on the pad 16 of the material mainly comprising copper and a metal layer (for example, an aluminum layer or an aluminum alloy layer) on the button metal layer, or the metal protection cover 18 is a metal layer containing a metal (for example) An inscription layer or a layer of alloy is located on the substrate 16 which mainly comprises copper, and the refractory metal alloy layer is sputtered on the aluminum-containing metal layer (for example, an aluminum layer or an aluminum alloy layer). Referring to Figure 6B, a sub-layer 26 of sputter thickness between 3 μm and 1 μm (preferably between 3 μm and 7 μm) is adhered/ On the barrier layer 24. Alternatively, the seed layer 26 may be formed by evaporation, physical vapor deposition, or electroless plating. Since the seed layer 26 can facilitate the formation of the subsequent metal layer, the material of the seed layer 26 may vary depending on the material of the subsequent metal layer, such as when a metal layer of gold (Au) is electroplated on the seed layer 26. The material of the seed layer 26 is preferably gold; or, when the metal layer of copper (Cu) is electroplated onto the seed layer 26, the material of the seed layer 26 is preferably copper; or, when the material is When the metal layer of palladium (Pd) is electroplated on the seed layer 26, the material of the seed layer 26 is preferably selected. For example, when the adhesion/barrier layer 24 is formed by sputtering, a thickness of ^1 μm to 〇·7 μm (preferably between 〇μm and 〇·7 μm) When the seed I 26 may have a thickness of between 〇〇3 μm and 1 μm (preferably between 0. A layer of gold from 03 micrometers to 7 micrometers is plated on the titanium layer; or, when the adhesion/barrier layer is 24 θ, the thickness of the sacrificial layer is between G. G1 micron to G. When a titanium-titanium alloy layer between 7 microns and 42 200814213 is between 0. 03 microns and 0.7 microns, the seed layer 24 may have a thickness of 0. Between 0 microns and 1 micron (preferably between 0. 03 microns to 0. A gold layer between 7 microns is sputtered on the titanium-tungsten alloy layer; or, when the adhesion/barrier layer 26 is formed by sputtering, the thickness is between 0. 01 micrometers and 0. Between 7 microns (preferably between 〇· 〇3 microns to 0. When a titanium nitride layer is between 7 microns, the seed layer 24 may have a thickness of 0. Between 03 microns and 1 micron (preferably between 〇· 〇3 microns to ο. A gold layer between the micrometers is sputtered on the titanium nitride layer; or, when the adhesion/barrier layer 24 is formed by sputtering, the thickness is between o oi micrometers to 〇. Between 7 microns (preferably between 0. The seed layer 26 may have a thickness between 〇·03 μm and 1 μm (between 03 μm and 〇·7 μm). The thickness is preferably between 0.03 μm and 0. A gold layer of minerals between 7 microns) is on the chrome layer; or, when the adhesion/barrier layer 24 is formed by sputtering, the thickness is between 0. 01 micron to 0. Between 7 microns (preferably between 〇· 〇3 microns to 0. When a nitride button layer is between 7 microns, the seed layer 26 may have a thickness of 0. Between 03 microns and 1 micron (preferably between 〇·〇3 microns to ο. A gold layer between the micrometers is forged on the nitride button layer; or, when the adhesion/barrier layer 24 is formed by a bell, the thickness is between 〇〇1 μm and ο. Between microns (preferably between 0. When a set of layers is between 03 micrometers and 〇7 micrometers, the seed layer 26 may have a thickness between 3 micrometers and 1 micrometer (compared to 仏 疋 between 0. 03 microns to 0. A gold layer of a bond between 7 microns is on the layer; or, when the adhesion/barrier layer 24 is formed by sputtering, the thickness is between 0. 01 micron to 0. When a metal alloy layer of between 7 microns (preferably between microns and 〇·7 microns) is used, the seed layer 26 can be 43. A gold layer between 03 microns and 丨 microns (preferably between 微•micrometers to 〇·7 microns) is sputtered onto the refractory metal alloy layer. For example, when the adhesion/barrier layer 24 is formed by sputtering, the thickness is between 〇·〇1 micro green 〇·7 μm (preferably between 〇〇3 μm and 〇·7 μm) When a titanium layer is used, the seed layer % may be a copper layer having a thickness between 微米·μm and 1 μm (preferably between 〇〇3 μm and 〇·7 μm). On the layer; or, when the adhesion/barrier layer 24 is formed by sputtering, the thickness is between 〇〇1 μm and 〇·7 μm (preferably between 0. The seed layer 24 may have a thickness between 0 〇 3 μm and 丨 μm (preferably between 0 and 0.3 μm). 03 microns to 0. A copper layer between 7 microns is sputtered onto the titanium-tungsten alloy layer; or, when the adhesion/barrier layer 26 is formed by sputtering, the thickness is between 0. 01 micron to 0. When a titanium nitride layer is between 7 microns (preferably between 〇3 microns and 〇7 microns), the seed layer 24 may have a thickness of 0. A copper layer between 03 microns and 1 micron (preferably between 〇〇3 microns and 〇7 microns) is sputtered onto the titanium nitride layer; or, when the adhesion/barrier layer 24 is The thickness of the money key method is between 〇. 〇丨micron to ο. Between microns (preferably between 0. 03 microns to 0. When a chrome layer is between 7 microns, the seed layer 26 may have a thickness of between 3 micrometers and 1 micrometer (preferably between 〇·〇3 micrometers to 0. A copper layer between 7 microns is sputtered on the chrome layer; or, when the adhesion/barrier layer 24 is formed by sputtering, the thickness is between 0. 01 micrometers and 0. The seed layer 26 may have a thickness of between 0 and 7 (preferably between 〇·〇3 μm and 0·7 μm). Between 0 microns and 1 micron (preferably between 〇. 〇 3 microns to 0. A copper layer between 7 44 200814213 micron is sputtered on the nitride button layer; or, when the adhesion/barrier layer 24 is sputtered, the thickness is between 〇〇1 μm and 〇7 μm. Between (preferably between 0. When a button layer is between 03 micrometers and 〇7 micrometers, the seed layer 26 can have a thickness of between 0.03 micrometers and up to! Between microns (better than 0.) 03 microns to 0. A copper layer between 7 microns is sputtered onto the button layer; or, when the adhesion/barrier layer 24 is formed by sputtering, the thickness is between 1 micron and 0. Between 7 microns (preferably between 〇 3 microns and 0. When a refractory metal alloy layer is between 7 microns, the seed layer 26 may be one having a thickness between 0. 03 microns and 1 micron (preferably between 〇〇 3 microns and 0. 7 microns). A copper layer is sputtered onto the refractory metal alloy layer. For example, when the adhesion/barrier layer 24 is formed by sputtering, the thickness is between 0. 01 micron to 0. Between 7 microns (preferably between 〇 〇 3 microns 2 0. When a layer of titanium is between 7 microns, the seed layer 26 may be a palladium layer sputtering having a thickness ranging from a micron to a micron (preferably between 0 03 and 7 microns). On the titanium layer; or, when the adhesion/barrier layer 24 is formed by a sputtering method, the thickness is between 微米·〇1 μm and 〇·7 μm (preferably between 0. When a titanium-tungsten alloy layer is between 03 micrometers and 77 micrometers, the seed layer 24 may have a thickness between (10) micrometers and w meters (preferably between 0.03 micrometers and 〇7 micrometers). a layer of sputtering on the Titanium alloy layer; or 'When the adhesion/barrier layer 26 is formed by sputtering, the thickness is between 1 μm and 〇·7 μm (more) Preferably, when a layer of titanium nitride is between 〇〇3 μm and 0.7 μm, the seed layer 24 may have a thickness of 0. A palladium layer between 03 μm i 1 micro# (preferably between 〇〇3 μm and 〇μm) is sputtered onto the titanium nitride layer; or, when adhesive/45 200814213 barrier layer 24 The thickness formed by sputtering is between 0. 01 micron to 0. Between 7 microns (preferably between 〇. 〇 3 microns to 0. When a chrome layer is between 7 microns, the seed layer 26 may have a thickness of 0. Between 03 microns and 1 micron (better than 0.) 03 microns to 0. A palladium layer between 7 microns is sputtered onto the chrome layer; or, when the adhesion/barrier layer 24 is sputtered, the thickness is between 0. 01 micron to 0. Between 7 microns (preferably between 0. 03 microns to 0. When a nitride button layer is between 7 microns, the seed layer 26 may have a thickness of 0. Between 0 microns and 1 micron (preferably between 0. 03 microns to 0. A palladium layer between 7 / micron is sputtered on the tantalum nitride layer; or, when the adhesion/barrier layer 24 is formed by sputtering, the thickness is between 0. 01 micron to 0. Between 7 microns (preferably between 〇. 〇 3 microns to 0. When a button layer is between 7 microns, the seed layer 26 may have a thickness of 0. Between 03 microns and 1 micron (better than 〇. 〇 3 microns to 0. A palladium layer between 7 microns is sputtered onto the button layer; or, when the adhesion/barrier layer 24 is sputtered, the thickness is between 0. 01 micron to 0. Between 7 microns (preferably between 0. 03 microns to 0. When a refractory metal alloy layer is between 7 microns, the seed layer 26 can have a thickness of between 〇. 〇 3 microns to 1 micron (preferably 0. 03 micrometers to 0. Between 7 microns) of an I baline mine is on this fossil metal alloy layer. Referring to FIG. 6C, a photoresist layer 28 having a spin-on coating thickness between 1 micrometer and 25 micrometers is disposed on the seed layer 26, wherein the preferred thickness of the photoresist layer 28 is between The photoresist layer 28 is, for example, between a micron and a 10 micron, and the photoresist layer 28 is, for example, a positive-type photoresist layer. Next, referring to FIG. 6D, the photoresist layer 28 is patterned by exposure and development processes to form a photoresist layer opening 28a in the layer 28 of the photoresist 46 200814213 and exposed to The metal layer covers the seed layer % above the cover 18, wherein in the process of patterning the photoresist layer 28, for example, an exposure machine using a double (10) or a double (10) alignment exposure machine (c〇mact tons (4) Performing exposure jtb outside 'after development, the plasma layer (such as a plasma containing oxygen ions or a plasma containing a fluoride ion concentration of less than 200 PPM and oxygen ions) may be used to clean the seed layer % exposed by the photoresist layer opening 28a. By removing the photoresist residue or other foreign matter on the upper surface of the seed layer 26, as shown in Fig. 4E, a metal I 30 having a thickness between 1 μm and 20 μm is exposed in the photoresist layer opening 28a. On the seed layer 26, the preferred thickness of the metal layer 30 is between 3 micrometers and 5 micrometers, and the material of the metal layer 3〇 comprises gold, copper, magnets or handles. For example, the metal layer 30 may be thick. Between 丨 micron and 2 〇 micron (better thickness) a gold layer plating between 3 micrometers to 5 micrometers or between i micrometers to 4 micrometers is plated on the seed layer 26 of the photoresist layer opening 28& exposed to gold; or, metal layer 3 The crucible may be a palladium layer plated at a photoresist layer opening having a thickness between 1 micrometer and 20 micrometers (preferably a thickness of between 3 micrometers to 5 micrometers or between micrometers to 4 micrometers). The material exposed by 28a is on the seed layer % of palladium; or, the metal layer 30 may be a copper layer having a thickness between ! micrometers and 1 micrometer. The material exposed by the photoresist layer opening 28a is copper. a nickel layer having a thickness between 1 micrometer and 5 micrometers on the seed layer 26 is electroplated on the copper layer and a gold layer having a thickness between 1 micrometer and 5 micrometers is electroplated on the nickel layer, wherein the copper layer The total thickness of the layer, the nickel layer and the gold layer is between 丨micrometer and 20 micrometers, and the preferred thickness is between 3 micrometers and 5 micrometers; 47 200814213 or = metal layer 3 〇 can be thickness _Nickel layer of electricity between 1 micrometer and 13 micrometers and between 1 micrometer and 5 micrometers: on the layer And the thickness of the gold layer cover between _micrometer and 2 micrometers, the total thickness of the copper layer, the recording layer and the gold layer in the yttrium; Ι / ρ ^ to 2G micron between 'and better' The thickness is between 3 micrometers and 2 micrometers, or 'metal layer 3 () may be a copper layer having a thickness between ! micrometers to micrometers. The material exposed to the opening of the photoresist layer is copper. A layer of nickel on the seed layer 26 having a thickness between 1 micrometer and 5 micrometers is electroplated on the copper layer and a layer of electric ore having a thickness between 1 micrometer and 5 micrometers is on the nickel layer, wherein the copper layer The total thickness of the layer, the nickel layer and the layer is 'between 1 micrometer to 2G micrometers, and the preferred thickness is between 3 micrometers and 5 micrometers; or the metal layer 3 can be thick. A steel layer between 1 micrometer and 13 micrometers is plated on the seed layer 26 of the photoresist layer opening 28& exposed to copper, and a nickel layer having a thickness between i microns and 5 micrometers is plated here. The layer on the copper layer and the gate having a thickness between 〇〇5 μm and 2 μ” is electrolessly recorded on the nickel layer, wherein the copper layer, the recording layer and the palladium layer are Line thickness between 1 to 20 microns, and the thickness is preferably between 3 to 5 microns. As shown in Fig. 6F, after the formation of the metal layer 3, the photoresist layer 28' is removed, and the photoresist layer 28 is removed by, for example, using an organic solvent containing an amino compound (arrnde). In addition, after removing the photoresist layer 28, the metal layer 48 200814213 30 and the seed layer 26 may be cleaned by using a plasma (for example, a plasma containing oxygen ions or a plasma containing a fluoride ion concentration of less than 200 PPM and oxygen ions). The photoresist residue on the upper surface of the metal layer 30 and the upper surface of the seed layer 26 is removed. Continuing to refer to FIG. 6G, the seed layer 26 and the adhesion/barrier layer 24 that are not under the metal layer 30 are sequentially removed. The manner of removing the seed layer 26 and the adhesion/barrier layer 24 not under the metal layer 30 is, for example, etching, and the etching method can be further divided into dry etching and wet etching, and dry etching includes chemistry. Plasma etching, splash etching and chemical gas etching. For example, in the case of wet residual, when the adhesion/barrier layer 24 is a titanium alloy, it can be removed by etching with a solution containing hydrogen peroxide, and when the adhesion/barrier layer 24 is titanium, it can be etched using a solution containing cyanofluoric acid. When the seed layer 26 is gold, it can be removed by etching using an iodine-containing etching solution (for example, an etchant containing potassium iodide), and when the seed layer 26 is copper, an etching solution containing ammonium hydroxide (NH4OH) can be used. Etching removal; in the dry etching, when the adhesion/barrier layer 24 is titanium or titanium tungsten alloy, it can be removed by gas-containing plasma etching or by reactive ion etching (RIE) process etching, and the seed layer is additionally used. When 26 is gold, it can be removed by ion milling process or removed by argon etching. Therefore, the present invention can form a wire bonding pad 22 on a metal protective cover 18, and the wire bonding pad 22 is formed by an adhesive/barrier layer 24, a sub-layer 26 on the adhesive/barrier layer 24. A metal layer 30 is formed on the seed layer 26. Moreover, the material of the wire bonding pad 22 includes titanium, titanium tungsten alloy, titanium nitride, chromium, nitrided group, gold, copper, nickel or Ιε. Therefore, the wire bonding pad 22 of the present invention can be in the form described below by the manner in which the wire bonding pads 22 are formed. 49 200814213 For example, the wire bonding pad 22 includes a thickness of 0. 01 μm to 〇·7 μm (preferably between 〇·〇3 μm to 0. A titanium-containing metal layer (such as a titanium layer, a titanium nitride layer or a titanium-tungsten alloy layer) between 7 microns is located on the metal bond 18 and has a thickness between 3 μm and 1 μm. (a preferred layer is between 0. 03 micrometers and 〇 7 micrometers) and a sub-layer of gold is used here to contain a titanium metal layer (such as a titanium layer, a titanium nitride layer or a titanium tungsten alloy layer). a gold layer on the seed layer and a thickness between 1 micrometer and 2 micrometers (preferably between 3 micrometers to 5 micrometers or between 1 micrometer and 4 micrometers) Wherein the metal protective cover 18 is fastened to the pad 16 (or copper pad) whose material is mainly exposed by the opening; or the wire bonding pad 22 comprises a thickness of between 微米1 μm and 〇7 μm. Between (preferably between G. G3 micron to 〇. a titanium-containing metal layer between 7 microns), a titanium layer, a titanium nitride layer or a titanium-tungsten alloy layer) on the metal protective cover a, with a thickness of G. G3 micron to 1 micron (preferably between 〇. 03 micron to 0. Between 7 microns) and the material is her-seed layer on this metal-containing layer (such as - titanium layer, - titanium nitride layer or _ titanium alloy layer) and thickness between 1 micron and 20 microns (the preferred thickness is between 3 micrometers and $micrometers or between 1 micrometer and 4 micrometers) - the layer is on the seed layer, wherein the metal protective cover 18 is in the opening W The exposed material mainly includes copper joints 16 (or copper enamels); or, the wire joints 22 include thicknesses ranging from 0. 01 micrometers to 〇·7 micrometers, preferably between 〇·〇3 Micron to 0. A layer of metal containing between 7 microns (such as a layer of lining, a layer of titanium nitride or a layer of titanium-niobium alloy) is placed on the metal protective cover, and is produced between micrometers and micrometers (preferably It is between 〇〇3 μm and ^7 50 200814213 μm. The copper-based seed layer is on the titanium-containing metal layer (such as - 曰 钦 钦 or - titanium tungsten alloy layer), and the thickness is between ^ The "copper layer" between the micron and 1 〇 micron is on the seed layer, and the thickness of the nickel layer is between 5 and 5 - the nickel layer is on the copper layer and the thickness is between 1 micrometer and 5 micrometer - The gold layer is on the recording layer, and the thickness of the recording layer, the copper layer and the gold layer is between ! micron and 2 () micrometers, and the preferred thickness is between 3 micrometers and 5 micrometers. The material in which the metal protective cover is located in the opening 1 a is mainly composed of a copper pad called or a copper pad; or the wire bonding pad 22 includes a thickness of 〇·〇1 μm to 0. . Between 7 micrometers (preferably between G. A titanium-containing metal = (such as a layer of lining, a layer of titanium nitride or a layer of titanium-titanium alloy) of G3 micro-green 〇·7 microns) is located on the metal sluice cover with a thickness ranging from 〇〇3 μm to i μm Between (preferably between 〇. 〇 3 microns to 〇. Between 7 microns and the material f is copper - the seed layer is on the titanium-containing metal layer (such as - titanium layer, - titanium nitride layer or - titanium tungsten ruthenium layer), and the thickness is between! a layer of copper between 1 micron and 1 alpha micron on the seed layer, having a thickness between i microns and 5 microns - a layer of nickel in the copper layer I and a layer having a thickness between i microns and 5 microns Positioned on the layer, and the total thickness of the nickel layer, the copper layer and the palladium layer is between 丨 micrometers and 2 〇 micrometers, and the preferred thickness is between 3 micrometers and 5 micrometers, wherein The metal protective cover 18 is fastened to the pad 16 (or copper pad) whose material is mainly exposed by the opening 14a.匕 For example, the wire bonding pad 22 includes a thickness of 〇. 〇1 μm to 〇7 μm (preferably between 0. 03 microns to 0. A layer of between 7 microns) is located on the metal protective cover 18 and has a thickness between (4) and 3 microns to W meters (compared with 51 200814213 and better than G. G3 micron to G. a sub-layer of between 7 microns and made of gold on the chrome layer and between j microns and 2 microns in thickness (preferably between 3 microns and 5 microns or between The gold layer between the top meter and the glutinous rice is on the seed layer, wherein the metal protective cover (four) is exposed on the opening 14a, and the material mainly includes the copper joint 16 (or copper plaque); or The wire bonding pad 22 includes a chrome layer having a thickness between 〇〇1 μm and 〇·7 μm (preferably between 〇〇3 μm and 〇·7 μm) on the metal protective cover 18, The thickness is between 0 () 3 microns to! A sub-layer between the micrometers (preferably between 3·() and 3 micrometers to 2 micrometers) and having a material density of between 丨 micrometers and 2 micrometers (preferably) A palladium layer having a thickness of between 3 micrometers and 5 micrometers or between 1 micrometer and 4 micrometers is on the seed layer, wherein the metal protective cover 18 is located at the opening of the opening 14a. Mainly comprising a copper pad 16 (or referred to as a copper pad); or, the wire bonding pad 22 comprises a thickness between 〇〇ι micron and 〇·7 micron (preferably between 〇·〇3 micron to 0 . The chrome layer between 7 microns) is on the metal protective cover 18 and has a thickness between 0 03 microns and 1 micron (preferably between 0. 03 microns and 7 microns). a sub-layer of copper on the chrome layer, having a thickness between 丨 micrometers and (7) micrometers - the copper layer is on the seed layer, and the thickness is between i micrometers and 5 micrometers. A gold layer on the copper layer and between 1 micrometer and 5 micrometers in thickness is on the nickel layer, and the total thickness of the recording layer, the copper layer and the gold layer is between i micrometers and 2 micrometers. The preferred thickness is between 3 micrometers and 5 micrometers, wherein the material of the metal protective cover 18 that is violently exposed in the opening 14a mainly comprises a copper pad 16 (or copper pad) 52 200814213 Or, the wire bonding pad 22 includes a thickness ranging from 〇〇1 μm to 〇·7 μm (preferably between 0. A chrome layer between 03 microns and 〇·7 microns is located on the metal protective cover 18 and has a thickness between 〇3 μm and 丨μm (the car is better than 0. a sub-layer of copper between 0 micrometers and 〇·7 micrometers and having a material of copper on the chrome layer, a steel layer having a thickness between 丨 micron and 1 〇 micron on the seed layer, the thickness is between A recording layer between i micrometers and 5 micrometers is on the copper layer and a thickness between 丨 micrometers and 5 micrometers - the layer is on the nickel layer' and the nickel layer, the copper layer and the layer layer The total thickness is between 1 micrometer and 2 micrometers, and the preferred thickness is between 3 micrometers and micrometers. The material in which the metal protective cover 18 is exposed in the opening is mainly composed of copper. Pad 16 (or called a steel pad). For example, the wire bonding pad 22 includes a button metal layer (eg, a group) having a thickness between 1 μm and 〇·7 μm (preferably between 〇〇3 μm and 〇·7 μm). The layer or the nitriding layer is located on the metal protective cover and has a thickness of 0. 03 micron to! a seed layer between the micrometers (preferably between 〇〇3 micrometers and 〇7 micrometers) and the material f is gold. The seed layer is on the group metal layer (for example, a neodymium layer or a nitride layer). a gold layer having a thickness between 1 micrometer and 20 micrometers (preferably a thickness of between 3 micrometers to 5 micrometers or between ^= to 4 micrometers) is on the seed layer, wherein the metal The material of the 8-8 position exposed in the opening 14a mainly includes a copper pad/or copper plaque; or the wire splicing 22 includes a thickness of 〇. 〇1, m, to 〇·7 microns (preferably between 〇·〇3 microns to 0. A 7-button metal layer (for example, a button layer or a nitride button layer) is placed on the metal protective cover 18 at a thickness of between 3 micrometers and (10) meters (preferably 53 200814213 " Between 0. 03 micrometers and 〇 7 micrometers and a sub-layer of material on the button metal layer (for example, a button layer or a nitride button layer) and a thickness of 1 micrometer to 20 micrometers. A palladium layer between (preferably between 3 microns and $ microns or between 1 and 4 microns) is on the seed layer, wherein the metal protective cover 18 is in the opening 14a The exposed material mainly includes a copper pad 16 (or a copper pad); or, the wire bonding pad 22 includes a thickness ranging from 微米·〇1 μm to 〇·7 μm (preferably between 〇 A button metal layer (for example, a button layer or a nitride button layer) between 3 micrometers and 0. 7 micrometers is located on the metal protective cover 18 and has a thickness between 〇〇3 micrometers and 丨micrometers ( Preferably, a sub-layer of copper is between 〇·03 μm and 〇·7 μm and is made of a button metal layer (for example, a button layer or a layer) a layer of copper having a thickness between 1 micrometer and 10 micrometers on the seed layer and having a thickness between i micrometers and 5 micrometers on the copper layer and the thickness layer The gold layer between 1 micrometer and 5 micrometers is on the nickel layer 'and the total thickness of the recording layer, the copper layer and the gold layer is between 1 micrometer and 2 micrometers micron, and the preferred thickness is It is between 3 micrometers and 5 micrometers, wherein the metal protective cover 18 is located on the pad 16 (or copper plaque) whose material is mainly exposed by the opening 14a; or the wire bonding pad 22 includes the thickness. Between 0. 01 micron to 0. A button metal layer (for example, a button layer or a nitride button layer) between 7 microns (preferably between 〇 micron and 〇 7 microns) is located on the metal protective cover 18 and has a thickness of 〇 〇 3 microns to i microns (preferably between 0. 03 μm to 0·7 μm - copper-based seed layer - copper with a thickness of between 1 μm and 1 μm on the button metal layer (for example, a tantalum layer or a nitride button layer) A layer of nickel on the seed layer 54 54142213 having a thickness between 1 micrometer and 5 micrometers on the copper layer and a thickness of between 1 micrometer and 5 micrometers - (four) in the second layer The total thickness of the nickel layer, the copper layer and the palladium layer is between 丨micrometer and ^μm, and the preferred thickness is between 3 micrometers and 5 micrometers, wherein the metal protective cover 18 is in the position The material exposed to the opening 14a is a copper pad 16 (or copper pad). Then, after the wire bonding pad 22 is completed, one of the semiconductor wafers formed by the above steps is completed. Further, the semiconductor wafer 31 is formed by cutting the semiconductor wafer as shown in Fig. 5A.

請參閱第7A圖與第7B圖所示，本發明可形成一金屬 線路32在一聚合物層34上，並透過聚合物層開口 3牝連 接接墊16(例如鋁墊或銅墊），其中聚合物層34係位在保護 層14上’且位在聚合物層34内之一開口 34a暴露出一開 口 所暴露出之一接墊16(例如鋁墊或銅墊），而開口 3乜 可以是暴露出一接墊16且聚合物層34還覆蓋至部分之接 墊34(如第7A圖所示），或是開口 34a暴露出一接墊16的 全部上表面以及暴露出位在此接墊16周圍之保護層14的 上表面（如第7B圖所示）。 聚合物層34比如是選自聚醯亞胺（PI)、環氧樹脂 (epoxy)、笨基環丁烯(bcb)、聚氨脂、聚對二甲苯類高分 子、焊罩材料、彈性體（elastomer)或多孔性介電材料其中 之一 ’且聚合物層34的厚度比如是介於3微米至25微米 之間。例如，聚合物層34可以是厚度介於3微米至25微 米之間的—聚醯亞胺層在保護層14上，且位在聚醯亞胺層 55 200814213 内之一開口暴露出接墊16(例如鋁墊或銅墊）；或者，聚合 物層34可以是厚度介於3微米至25微米之間的一環氧樹 脂層在保護層14上，且位在環氧樹脂層内之一開口暴露出 接墊16(例如鋁墊或銅墊）；或者，聚合物層34可以是厚度 介於3微米至25微米之間的一苯基環丁烯層在保護層14 上，且位在苯基環丁烯層内之一開口暴露出接墊16(例如 鋁墊或銅墊）。此外，形成聚合物層34的方式包括有旋塗、 壓合或網版印刷等方式。 金屬線路32的材質包括金、銅、鎳或鈀，且形成金屬 線路32的方式包括錢鑛製程（sputtering process)、電鑛製 程（electroplating process)或無電電鍍（electroless plating process)製程等。例如，金屬線路32包括厚度介於0.01微 米至0.7微米之間（較佳則是介於0.03微米至0.7微米之間） 的一黏著/阻障層濺鍍形成在聚合物層34上與開口 34a所 暴露出之接墊16(例如鋁墊或銅墊）上、厚度介於0.03微米 至1微米之間（較佳則是介於0.03微米至0.7微米之間）且 材質為金的一種子層濺鍍形成在黏著/阻障層上以及厚度 介於1微米至30微米之間的一金層電鍍形成在種子層上， 其中黏著/阻障層的材質包括鈦、鈦鎢合金、氮化鈦、鉻或 氮化钽，而金層的較佳厚度則是介於2微米至20微米之 間；或者，金屬線路32包括厚度介於0.01微米至0.7微 米之間（較佳則是介於〇.〇3微米至0.7微米之間）的一黏著/ 阻障層濺鍍形成在聚合物層34上與開口 34a所暴露出之接 墊16(例如鋁墊或銅墊）上、厚度介於0.03微米至1微米之 56 200814213 趴較佳則是介於0·03微米至0·7微米之間)且材質為銅的 一種子層_形成在黏著/阻障層上、厚度介⑨〗微米至 20微米之間的一銅層電鍍形成在種子層上、厚度介於1微 米至10微米之間的一鎳層電鍍形成在鋼層上以及厚度介 於0·01微米至5微米之間的一金層電鑛形成在錄層上，其 中黏著/轉層的材f包括鈦、絲合金、氮化鈦、絡或氮 化鈕；或者，金屬線路32包括厚度介於〇·〇1微米至q.7 I卡之間（較佳則是介於㈣3微米至0.7微米之間）的一黏 著/阻障層_形成在聚合物層34上與開口 3如所暴露出 ^接墊16(例如銘塾或銅墊）上、厚度介於〇 〇3微米至^ 米之間（較佳則是介於⑽微米至07微米之間）且材質為 銅的-種子層濺鑛形成在黏著/阻障層上、厚度介於i微米 至20微米之間的—銅層電鍍形成在種子層上、厚度介於^ 微米至10微米之間的一鎳層電鍍形成在銅層上以及厚度 w於0-02微米至2微米之間的一金層無電電鑛形成在錄層 上，、其中黏著/阻障層的材f包括鈦、輯合金、氮化欽、 鉻或鼠化鈕；或者，金屬線路32包括厚度介於〇 〇1微米 至〇·7微求之間（較佳則是介於〇 〇3微米至微米之間） 的一黏著/阻障層濺鍍形成在聚合物層34上與開口 34a所 暴路出之接墊16〇j如|呂墊或銅墊）上、厚度介於Q 微米 至1微米之間（較佳則是介於0.03微米i 〇·7微米之間）且 材貝為銅的種子層機鍍形成在黏著/阻障層上、厚度介於 1 m 2〇微米之間的一銅層電鐘形成在種子層上、厚度 "於1微米至10微米之間的一錄層電鑛形成在銅層上以及 57 200814213 厚度介於0.01微米至5微米之間的一鈀層電鍍形成在鎳層 上，其中黏著/阻障層的材質包括鈦、鈦鎢合金、氮化鈦、 鉻或氮化钽；或者，金屬線路32包括厚度介於0.01微米 至0.7微米之間（較佳則是介於0.03微米至0.7微米之間） 的一黏著/阻障層濺鍍形成在聚合物層34上與開口 34a所 暴露出之接墊16(例如鋁墊或銅墊）上、厚度介於0.03微米 至1微米之間（較佳則是介於0.03微米至0.7微米之間）且 材質為銅的一種子層濺鍍形成在黏著/阻障層上、厚度介於 f 1微米至20微米之間的一銅層電鍍形成在種子層上、厚度 介於1微米至10微米之間的一鎳層電鍍形成在銅層上以及 厚度介於0.05微米至2微米之間的一鈀層無電電鍍形成在 鎳層上，其中黏著/阻障層的材質包括鈦、鈦鎢合金、氮化 鈦、鉻或氮化鈕。另，金屬線路32包括作為接合打線導線 的至少一打線接點，例如金屬線路32包括一第一打線接點 32a與一第二打線接點32b，從俯視透視圖觀之，第一打線 接點32a的位置係位在金屬線路32所連接之接墊16上 、 方，而第二打線接點32b的位置則不同於金屬線路32所連 接之接墊16的位置，因此本發明可依需求於後續製程中， 選擇接合一打線導線（例如金線）至第一打線接點32a、接合 一打線導線（例如金線）至第二打線接點32b或是分別接合 一打線導線（例如金線）至第一打線接點32a與第二打線接 點 32b 〇 接著，於形成金屬線路32之後，透過切割半導體晶 圓，以形成複數半導體晶片36。 58 200814213 請參閱第7C圖與第7D圖所示，本發明在形成金屬線 路32之後（如第7A圖與第7B圖所示），亦可形成一聚合 物層38在金屬線路32上與聚合物層34上，且位在聚合物 層38内之至少一開口 38a暴露出金屬線路32，而從俯視 透視圖觀之，開口 38a所暴露出之金屬線路32的位置可以 是不同於金屬線路32所連接之接墊16的位置，其中開口 38a所暴露出之金屬線路32係作為接合打線導線的打線接 點，例如二開口 38a分別暴露出一金屬線路32的一第一打 線接點32a與一第二打線接點32b，從俯視透視圖觀之， 第一打線接點32a的位置係位在金屬線路32所連接之接墊 16上方，而第二打線接點32b的位置則不同於金屬線路32 所連接之接墊16的位置，因此本發明可依需求於後續製程 中，選擇接合一打線導線（例如金線）至第一打線接點32a、 接合一打線導線（例如金線）至第二打線接點32b或是分別 接合一打線導線（例如金線）至第一打線接點32a與第二打 線接點32b。 聚合物層38比如是選自聚醯亞胺（PI)、環氧樹脂 (epoxy)、苯基環丁烯（BCB)、聚氨脂、聚對二甲苯類高分 子、焊罩材料、彈性體（elastomer)或多孔性介電材料其中 之一，且聚合物層38的厚度比如是介於3微米至25微米 之間。例如，聚合物層38可以是厚度介於3微米至25微 米之間的一聚醯亞胺層在金屬線路32上，且位在聚醯亞胺 層内之一開口暴露出金屬線路32的金層或鈀層；或者，聚 合物層38可以是厚度介於3微米至25微米之間的一環氧 59 200814213 樹脂層在金屬線路32上，且位在環氧樹脂層内之一開口暴 露出金屬線路32的金層或鈀層；或者，聚合物層38可以 是厚度介於3微米至25微米之間的一苯基環丁烯層在金屬 線路32上，且位在苯基環丁烯層内之一開口暴露出金屬線 路32的金層或鈀層。此外，形成聚合物層38的方式包括 有旋塗、壓合或網版印刷等方式。 接著，於形成聚合物層38之後，透過切割半導體晶 圓，以形成複數半導體晶片40。 另，請參閱第7E圖所示，本發明亦可不形成聚合物 層34在保護層14上，即金屬線路32係形成在保護層14 上，並透過開口 14a連接接墊16(例如鋁墊或銅墊），其中 金屬線路32包括作為接合打線導線的至少一打線接點，例 如金屬線路32包括一第一打線接點32a與一第二打線接點 32b，從俯視透視圖觀之，第一打線接點32a的位置係位在 金屬線路32所連接之接墊16上方，而第二打線接點32b 的位置則不同於金屬線路32所連接之接墊16的位置，因 此本發明可依需求於後續製程中，選擇接合一打線導線（例 如金線）至第一打線接點32a、接合一打線導線（例如金線) 至第二打線接點32b或是分別接合一打線導線（例如金線) 至第一打線接點32a與第二打線接點32b。有關金屬線路 32的詳細敘述，請參閱上述第7A圖與第7B圖的說明， 在此不再詳加敘述。接著，於形成金屬線路32之後，透過 切割半導體晶圓，以形成複數半導體晶片42。 請參閱第7F圖所示，本發明在形成金屬線路32之後 200814213 (如第7E圖所示），亦可形成一聚合物層38在金屬線路32 上，且位在聚合物層38内之至少一開口 38a暴露出金屬線 路32，而從俯視透視圖觀之，開口 38a所暴露出之金屬線 路32的位置可以是不同於金屬線路32所連接之接墊16 的位置，其中開口 38a所暴露出之金屬線路32係作為接合 打線導線的打線接點，例如二開口 38a分別暴露出一金屬 線路32的一第一打線接點32a與一第二打線接點32b，從 俯視透視圖觀之，第一打線接點32a的位置係位在金屬線 路32所連接之接墊16上，而第二打線接點32b的位置則 不同於金屬線路32所連接之接墊16的位置，因此本發明 可依需求於後續製程中，選擇接合一打線導線（例如金線） 至第一打線接點32a、接合一打線導線（例如金線）至第二打 線接點32b或是分別接合一打線導線（例如金線）至第一打 線接點32a與第二打線接點32b。有關聚合物層38的詳細 敘述，請參閱上述第7C圖與第7D圖的說明，在此不再詳 加敘述。接著，於形成聚合物層38之後，透過切割半導體 晶圓，以形成複數半導體晶片44。 請參閱第8A圖所示，本發明可形成一金屬線路32在 一聚合物層34上，並透過聚合物層開口 34a連接金屬保镬 蓋18，其中聚合物層34係位在保護層14上，且位在聚合 物層34内之一開口 34a暴露出金屬保護蓋18的含鋁金屬 層（例如一銘層或一铭合金層）’而金屬線路32係透過開口 34a連接含銘金屬層（例如一铭層或一铭合金層），金屬保護 蓋18則是位在開口 14a所暴露出之主要材質包括銅的接墊 61 200814213 16(即銅墊）上。有關聚合物層34的詳細敘述，請參閱上述 第7A圖與第7B圖的說明，在此不再詳加敘述。 金屬線路32的材質包括金、銅、鎳或鈀，且形成金屬 線路32的方式包括濺鍍製程、電鍍製程或無電電鍍製程 等。例如，金屬線路32包括厚度介於〇〇1微米至〇7微 米之間（較佳則是介於〇·〇3微米至〇.7微米之間）的一黏著/ 阻障層濺鍍形成在聚合物層34上與開口 34a所暴露出之金 屬保護蓋18的含鋁金屬層（例如一鋁層或一鋁合金層）上、 厚度介於0.03微米至1微米之間（較佳収介於〇·〇3微米 至〇·7微米之間）且材質為金的一種子層濺鍍形成在黏著/ 阻障層上以及厚度介於1微米至30微米之間的一金層電鍍 形成在種子層上，其中黏著/阻障層的材質包括鈦、鈦鎢合 金、氮化鈦、鉻或氮化鈕，而金層的較佳厚度則是介於2 微米至20微米之間；或者，金屬線路32包括厚度介於〇 〇1 微米至〇.7微米之間（較佳則是介於0.03微米至0·7微米之 間）的一黏著/阻障層濺鍍形成在聚合物層34上與開口 3如 所暴露出之金屬保護蓋18的含鋁金屬層（例如一鋁層或一 鋁合金層）上、厚度介於〇 〇3微米至丨微米之間（較佳則是 ;丨於0.03微米至〇·7微米之間）且材質為銅的一種子層賤鍍 形成在黏著/阻障層上、厚度介於i微米至2〇微米之間的 銅層電鍍形成在種子層上、厚度介於丨微米至1〇微米之 間的錄層電鍍开> 成在銅層上以及厚度介於〇 〇1微米至5 微米之間的金層電鑛形成在錄層上，其中黏著/阻障層的 材質包括鈦、鈦鎢合金、氮化鈦、鉻或氮化鈕；或者，金 62 200814213 屬線路32包括厚度介於〇 〇1微米至〇 7微米之間（較佳則 是介於〇·〇3微米至〇·7微米之間）的一黏著/阻障層濺錢形 成在聚合物層34上與開口 3扣所暴露出之金屬保護蓋W 的含鋁金屬層（例如一鋁層或一鋁合金層）上、厚度介於 0.03微米至1微米之間（較佳則是介於〇〇3微米至〇·7微米 之間）且材質為銅的一種子層濺鍍形成在黏著/阻障層上、 厚度介於1微米至2G微米之間的—銅層電鍍形成在種子層 上厚度"於1微米至1〇微米之間的一錄層電鍍形成在鋼 層上以及厚度介於0·05微米至2微米之間的一金層無電電 鍍形成在鎳層上，其中黏著/阻障層的材質包括鈦、鈦鎢合 金、氮化鈦、鉻或氮化鈕；或者，金屬線路32包括厚度介 於〇·〇1微米至0.7微米之間（較佳則是介於〇 〇3微米至〇 7 微米之間）的一黏著/阻障層濺鍍形成在聚合物層34上與開 口 34a所暴露出之金屬保護蓋18的含鋁金屬層（例如一鋁 層或一鋁合金層）上、厚度介於〇〇3微米至丨微米之間（較 佳則是介於0.03微米至〇·7微米之間）且材質為銅的一種子 層濺鍍形成在黏著/阻障層上、厚度介於丨微米至2〇微米 之間的一銅層電鍍形成在種子層上、厚度介於丨微米至 微米之間的一鎳層電鍍形成在銅層上以及厚度介於〇〇ι 微米至5微米之間的一鈀層電鍍形成在鎳層上，其中黏著/ 阻障層的材質包括鈦、鈦鎢合金、氮化鈦、鉻或氮化鈕； 或者，金屬線路32包括厚度介於〇 〇1微米至〇·7微米之 間（較佳則是介於0·03微米至〇·7微来之間）的一黏著/阻障 層濺鍍形成在聚合物層34上與開口 34a所暴露出之金屬保 63 200814213 護蓋18的含鋁金屬層（例如一鋁層或一鋁合金層）上、厚度 介於0.03微米至1微米之間（較佳則是介於0.03微米至0.7 微米之間）且材質為銅的一種子層濺鍍形成在黏著/阻障層 上、厚度介於1微米至20微米之間的一銅層電鍍形成在種 子層上、厚度介於1微米至10微米之間的一鎳層電鍍形成 在銅層上以及厚度介於0.05微米至2微米之間的一鈀層無 電電鍍形成在鎳層上，其中黏著/阻障層的材質包括鈦、鈦 鎢合金、氮化鈦、鉻或氮化钽。另，金屬線路32包括作為 < 接合打線導線的至少一打線接點，例如金屬線路32包括一 第一打線接點32a與一第二打線接點32b，從俯視透視圖 觀之，第一打線接點32a的位置係位在金屬線路32所連接 之金屬保護蓋18上方，而第二打線接點32b的位置則不同 於金屬線路32所連接之金屬保護蓋18的位置，因此本發 明可依需求於後續製程中，選擇接合一打線導線（例如金線) 至第一打線接點32a、接合一打線導線（例如金線）至第二打 線接點32b或是分別接合一打線導線（例如金線）至第一打 I 線接點32a與第二打線接點32b。 接著，於形成金屬線路32之後，透過切割半導體晶 圓，以形成複數半導體晶片46。 請參閱第8B圖所示，本發明在形成金屬線路32之後 (如第8A圖所示），亦可形成一聚合物層38在金屬線路32 上與聚合物層34上，且位在聚合物層38内之至少一開口 38a暴露出金屬線路32，而從俯視透視圖觀之，開口 38a 所暴露出之金屬線路32的位置可以是不同於金屬線路32 64 200814213 所連接之金屬保護蓋18的位置，其中開口 38a所暴露出之 金屬線路32係作為接合打線導線的打線接點，例如二開口 38a分別暴露出金屬線路32的一第一打線接點32a與一第 二打線接點32b，從俯視透視圖觀之，第一打線接點32a 的位置係位在金屬線路32所連接之金屬保護蓋18上方， 而第二打線接點32b的位置則不同於金屬線路32所連接之 金屬保護蓋18的位置，因此本發明可依需求於後續製程 中，選擇接合一打線導線（例如金線）至第一打線接點32a、 接合一打線導線（例如金線）至第二打線接點32b或是分別 接合一打線導線（例如金線）至第一打線接點32a與第二打 線接點32b。有關聚合物層38的詳細敘述，請參閱上述第 7C圖與第7D圖的說明，在此不再詳加敘述。接著，於形 成聚合物層38之後，透過切割半導體晶圓，以形成複數半 導體晶片48。 請參閱第8C圖所示，本發明亦可不形成聚合物層34 在保護層14上，即金屬線路32係形成在保護層14上與金 屬保護蓋18的含金屬層（例如一銘層或一紹合金層）上， 其中金屬線路32包括作為接合打線導線的至少一打線接 點，例如金屬線路32包括一第一打線接點32a與一第二打 線接點32b，從俯視透視圖觀之，第一打線接點32a的位 置係位在金屬線路32所連接之金屬保護蓋18上方，而第 二打線接點32b的位置則不同於金屬線路32所連接之金屬 保護蓋18的位置，因此本發明可依需求於後續製程中，選 擇接合一打線導線（例如金線）至第一打線接點32a、接合一 65 200814213 打線導線（例如金線）至第二打線接點32b或是分別接合一 打線導線（例如金線）至第一打線接點32a與第二打線接點 32b。有關金屬線路32的詳細敘述，請參閱上述第7A圖 與第7B圖的說明，在此不再詳加敘述。接著，於形成金 屬線路32之後，透過切割半導體晶圓，以形成複數半導體 晶片50。 請參閱第8D圖所示，本發明在形成金屬線路32之後 (如第8C圖所示），亦可形成一聚合物層38在金屬線路32 上，且位在聚合物層38内之至少一開口 38a暴露出金屬線 路32，而從俯視透視圖觀之，開口 38a所暴露出之金屬線 路32的位置可以是不同於金屬線路32所連接之金屬保護 蓋18的位置，其中開口 38a所暴露出之金屬線路32係作 為接合打線導線的打線接點，例如二開口 38a分別暴露出 金屬線路32的一第一打線接點32a與一第二打線接點 32b，從俯視透視圖觀之，第一打線接點32a的位置係位在 金屬線路32所連接之金屬保護蓋18上方，而第二打線接 點32b的位置則不同於金屬線路32所連接之金屬保護蓋 18的位置，因此本發明可依需求於後續製程中，選擇接合 一打線導線（例如金線）至第一打線接點32a、接合一打線導 線（例如金線）至第二打線接點32b或是分別接合一打線導 線（例如金線）至第一打線接點32a與第二打線接點32b。有 關聚合物層38的詳細敘述，請參閱上述第7C圖與第7D 圖的說明，在此不再詳加敘述。接著，於形成聚合物層38 之後，透過切割半導體晶圓，以形成複數半導體晶片52。 66 200814213 笫一實施例 請參閱第9A圖所示，透過一點膠製程（dispensing process)，使複數黏著材料54形成於一基板56上；接著， 將複數半導體晶片23分別壓合在這些黏著材料54上，並 在經過烘烤製程之後使半導體晶片23黏著至基板56，亦 即半導體晶片23係透過黏著材料54以半導體基底2黏著 至基板56。其中，黏著材料54的材質比如是聚合物材料（例 如聚醯亞胺、環氧樹脂或銀膠），且厚度係介於1微米至 50微米之間，例如黏著材料54可以是厚度介於1微米至 50微米之間的聚醯亞胺，或是厚度介於1微米至50微米 之間的環氧樹脂，或是厚度介於1微米至50微米之間的銀 膠（silver-filed epoxy) 〇 此外，基板56可以是厚度介於200微米至2,000微米 之間的一球型柵狀陣列（BGA)基板；或者，基板56可以是 厚度介於200微米至2,000微米之間的一含有玻璃纖維與 環氧樹脂的基板；或者，基板56可以是厚度介於200微米 至2,000微米之間的一玻璃基板；或者，基板56可以是厚 度介於200微米至2,000微米之間的一矽基板；或者，基 板56可以是厚度介於200微米至2,000微米之間的一陶瓷 基板；或者，基板56可以是厚度介於200微米至2,000微 米之間的一有機基板；或者，基板56可以是厚度介於200 微米至2,000微米之間且材質包括鋁的一金屬基板；或 者，基板56可以是厚度介於200微米至2,000微米之間且 67 200814213 材質包括銅的一金屬基板。 請參閱第9B圖所示’透過一打線製程使一打線導線 58的一端球形（ball)接合至一半導體晶片23之一打線接墊 22上（例如接合至打線接墊22的金層或鈀層上），而此打線 導線58的另一端則楔形（wedge)接合至基板56之一金屬線 路的一接點57上，其中打線導線58比如是直徑介於20 微米至50微米之間且材質含金的一金屬線（或稱為金線）。 因此，半導體晶片23的打線接墊22電性連接基板56的金 P 屬線路。 請參閱第9C圖所示，形成厚度t5介於250微米至 1，000微米之間的一聚合物材料60在基板56上並覆蓋半 導體晶片23及打線導線58,其中形成聚合物材料6〇的方 式包括有灌膜製程（molding process)或點膠製程 (dispensing process)等，而聚合物材料6〇的材質包括聚醯 亞胺（PI)、苯基環丁烯（BCB)或環氧樹脂（exp〇y resin)。 例如，利用灌膜製程形成厚度t5介於25〇微米至 微米之間的聚蕴亞胺在基板56上並覆蓋半導體晶片23及 打線導線58 ;或者，利用灌膜製程形成厚度t5介於25〇 微米至1，000微米之間的苯基環丁烯在基板56上並覆蓋半 導體晶片23及打線導線58 ;或者，利用灌膜製程形成厚 度t5介於250微米至1，0〇〇微米之間且含有環氧樹脂的聚 合物材料在基板56上並覆蓋半導體晶片23及打線導線 58 〇 例如’利用點膠製程形成厚度t5介於25〇微米至1，〇〇〇 68 200814213 微米之間的聚醯亞胺在基板56上並覆蓋半導體晶片23及 打線導線58 ;或者，利用點膠製程形成厚度t5介於250 微米至1，000微米之間的苯基環丁烯在基板56上並覆蓋半 導體晶片23及打線導線58 ;或者，利用點膠製程形成厚 度t5介於250微米至1，000微米之間且含有環氧樹脂的聚 合物材料在基板56上並覆蓋半導體晶片23及打線導線 58 〇 請參閱第9D圖所示，以植球製程（ball planting process) 或是網版印刷製程（screen printing process)形成一無錯銲 料（lead-free solder)在基板56的一接點64上，接著在溫度 介於200°C至300°C之間（較佳溫度則是介於230°C至260 °C之間）的環境中對無錯銲料進行一迴銲（reflow)製程，以 形成直徑d介於0.25釐米至1.2釐米之間的一無鉛錫球 (lead-free solder ball)62在基板56的接點64上，其中迴銲 製程的時間係介於5秒至90秒之間，較佳則是介於20秒 至40秒之間。此外，無鉛錫球62的材質可以是錫鉛合金 (tin-lead alloy)、錫銀合金（tin-silver alloy)、錫銀銅合金 (tin-silver-copper alloy)或無鉛合金（lead-free alloy)。另， 因無船錫球62接合基板56之一金屬線路的接點64而連接 接點57，故無鉛錫球62電性連接打線導線58。 請參閱第9E圖所示，於形成無鉛錫球62之後，切割 (例如機械切割）基板56與聚合物材料60,以形成複數個晶 片封裝結構66。在第9E圖中，基板56包括有一第一表面 與一第二表面，且第一表面與第二表面為相對的兩表面， 69 200814213 其中黏著材料54與聚合物材料60係位在第一表面上（半導 體晶片23係透過黏著材料54黏著在第一表面），而無鉛錫 球62則位在第二表面上。 請分別參閱第10A圖至第10L圖所示，透過上述第 9A圖至第9D圖所述之步驟，本發明亦可使用半導體晶片 31、36、40、42、44、46、48、50 與 52 來取代第 9 圖系 列中的半導體晶片23,並於形成無鉛錫球62之後，切割（例 如機械切割）基板56與聚合物材料60，以分別形成晶片封 f 裝結構 68、70、72、74、76、78、80、82 與 84，詳細内 容請參閱第9A圖至第9E圖的說明，在此不再詳加敘述。 另，在第10C圖至第10L圖中，打線導線58接合金 屬線路32的位置從俯視透視圖觀之，此位置可以是不同於 金屬線路32所連接之接墊16的位置，或者是不同於金屬 線路32所連接之金屬保護蓋18的位置。因此，在第10C 圖至第10L圖中，金屬線路32可以是包括一第一打線接 點32a與一第二打線接點32b，從俯視透視圖觀之，第一 ^ 打線接墊32a的位置係位在金屬線路32所連接之接墊16 上方，而第二打線接點32b的位置則不同於金屬線路32 所連接之接墊16的位置，所以本發明可選擇接合一打線導 線58(例如金線）至第一打線接點32a、接合一打線導線 58(例如金線）至第二打線接點32b或是分別接合一打線導 線58(例如金線）至第一打線接點32a與第二打線接點32b。 第二實施例 200814213 請參閱第11A圖所示，透過一點膠製程（dispensing process)，使複數黏著材料54形成於一導線架（lead fi*ame)86之複數晶片承載座86a上；接著，將複數半導體 晶片23分別壓合在這些黏著材料54上，並在經過烘烤製 程之後使半導體晶片23黏著於晶片承載座86a。因此，半 導體晶片23係透過黏著材料54以半導體基底2黏著於晶 片承載座86a。其中，黏著材料54的材質比如是聚合物材 料（例如聚醯亞胺、環氧樹脂或銀膠），且厚度係介於1微 米至50微米之間，例如黏著材料54可以是厚度介於1微 米至50微米之間的聚醯亞胺，或是厚度介於1微米至50 微米之間的環氧樹脂，或是厚度介於1微米至50微米之間 的銀膠（silver-filed epoxy)。此外，導線架86的材質包括 銅或銅合金，且導線架86的厚度t6係介於100微米至2,000 微米之間。 請參閱第11B圖所示，透過一打線製程使一打線導線 58的一端球形（ball)接合至一半導體晶片23之一打線接墊 22上（例如接合至打線接墊22的金層或鈀層上），而此打線 導線58的另一端則楔形（wedge)接合至導線架86之一引腳 (lead)86b上，其中打線導線58比如是直徑介於20微米至 50微米之間且材質含金的一金屬線（或稱為金線）。因此， 半導體晶片23的打線接墊22電性連接導線架86之引腳 86b 〇 請參閱第11C圖所示，以灌膜製程（molding process) 形成厚度t7介於250微米至1，000微米之間的一聚合物材 71 200814213 料88包覆導線架86(其係包覆晶片承载座86a與部份引腳 86b)、半導體晶片23以及打線導線58，並露出導線架86 的部份引腳86b。其中，聚合物材料88的材質包括聚醯亞 胺（PI)、苯基環丁烯（BCB)或環氧樹脂（exp〇yresin)。 例如，利用灌膜製程形成厚度t7介於25〇微米至1000 微米之間的聚醯亞胺包覆導線架86(其係包覆晶片承載座 86a與部份引腳86b)、半導體晶片23以及打線導線58， 並露出導線架86的部份引腳86b ;或者，利用灌膜製程形 成厚度t7介於250微米至1，〇〇〇微米之間的苯基環丁烯包 覆導線架86(其係包覆晶片承載座86a與部份引腳86b)、 半導體晶片23以及打線導線58,並露出導線架86的部份 引腳86b ;或者，利用灌膜製程形成厚度t7介於250微米 至1，000微米之間且含有環氧樹脂的聚合物材料包覆導線 架86(其係包覆晶片承載座86a與部份引腳86b)、半導體 晶片23以及打線導線58，並露出導線架86的部份引腳 86b。 請參閱第11D圖所示，於形成聚合物材料88之後， 透過剪切分離（trim)以及將引腳86b壓成各種預先設計好 之形狀等步驟形成晶片封裝結構90(或稱為導線架封裝， lead-frame package)。其中，導線架封裝結構90可以是小 尺寸封裝（Small Outline Package，SOP)、薄型小尺寸封裝 (Thin Small Outline Package，TSOP)、雙列直插式封裝（DualReferring to FIGS. 7A and 7B, the present invention can form a metal line 32 on a polymer layer 34 and connect the pads 16 (for example, an aluminum pad or a copper pad) through the opening of the polymer layer. The polymer layer 34 is fastened on the protective layer 14 and one of the openings 34a in the polymer layer 34 exposes an opening to expose one of the pads 16 (for example, an aluminum pad or a copper pad), and the opening 3 can be Is exposed a pad 16 and the polymer layer 34 also covers a portion of the pad 34 (as shown in FIG. 7A), or the opening 34a exposes all of the upper surface of a pad 16 and the exposed position is The upper surface of the protective layer 14 around the pad 16 (as shown in Fig. 7B). The polymer layer 34 is, for example, selected from the group consisting of polyimine (PI), epoxy, stupyl cyclobutene (bcb), polyurethane, polyparaxylene polymer, solder mask material, and elastomer. One of the (elastomer) or porous dielectric materials and the thickness of the polymer layer 34 is, for example, between 3 microns and 25 microns. For example, the polymer layer 34 can be a polyimine layer having a thickness between 3 microns and 25 microns on the protective layer 14, and one of the openings in the polyimine layer 55 200814213 exposes the pad 16 (for example, an aluminum pad or a copper pad); or, the polymer layer 34 may be an epoxy layer having a thickness of between 3 micrometers and 25 micrometers on the protective layer 14 and located in an opening in the epoxy layer Exposing the pad 16 (eg, an aluminum pad or a copper pad); or, the polymer layer 34 may be a layer of phenylcyclobutene having a thickness between 3 microns and 25 microns on the protective layer 14 and at benzene One of the openings in the base cyclobutene layer exposes a pad 16 (e.g., an aluminum pad or a copper pad). Further, the manner in which the polymer layer 34 is formed includes spin coating, press bonding, or screen printing. The material of the metal line 32 includes gold, copper, nickel or palladium, and the manner of forming the metal line 32 includes a sputtering process, an electroplating process or an electroless plating process. For example, metal line 32 includes an adhesion/barrier layer sputter deposited between 0.01 microns and 0.7 microns (preferably between 0.03 microns and 0.7 microns) formed on polymer layer 34 and opening 34a. Sub-layer sputtering of exposed pads 16 (eg, aluminum pads or copper pads) having a thickness between 0.03 microns and 1 micron (preferably between 0.03 microns and 0.7 microns) and a gold material A gold layer formed on the adhesion/barrier layer and having a thickness of between 1 micrometer and 30 micrometers is formed on the seed layer, wherein the material of the adhesion/barrier layer comprises titanium, titanium tungsten alloy, titanium nitride, chromium Or tantalum nitride, and the preferred thickness of the gold layer is between 2 microns and 20 microns; or the metal line 32 comprises a thickness between 0.01 microns and 0.7 microns (preferably between 〇.〇3) An adhesion/barrier layer sputtering between microns and 0.7 microns is formed on the polymer layer 34 and the pads 16 (eg, aluminum pads or copper pads) exposed by the openings 34a, having a thickness between 0.03 microns and 1 Micron 56 200814213 趴 preferably between 0·03 micron and 0·7 micron) and material A sublayer of copper—a copper layer formed on the adhesion/barrier layer and having a thickness between 9 μm and 20 μm is electroplated to form a nickel layer on the seed layer and having a thickness between 1 μm and 10 μm. Electroplating is formed on the steel layer and a gold layer of electric ore having a thickness between 0. 01 micrometers and 5 micrometers is formed on the recording layer, wherein the adhesive/transfer layer material f comprises titanium, silk alloy, titanium nitride, and Or a nitride button; or, the metal line 32 includes an adhesion/barrier layer having a thickness between 1 micrometer and q.7 I card (preferably between (4) and 3 micrometers to 0.7 micrometers). On the polymer layer 34 and the opening 3 as exposed by a pad 16 (such as an inscription or a copper pad), the thickness is between 〇〇3 μm and ^m (preferably between (10) and 07 μm Between the material and the copper-seed layer is formed on the adhesion/barrier layer and the thickness is between i microns and 20 microns. The copper layer is electroplated on the seed layer and has a thickness of from μm to 10 A nickel layer between the micrometers is formed on the copper layer and a gold layer of electroless ore having a thickness w between 0 and 2 micrometers to 2 micrometers is formed. On the recording layer, the material f of the adhesion/barrier layer comprises titanium, alloy, nitride, chrome or mouse button; or the metal line 32 comprises a thickness of between 微米1 μm and 〇·7 μ. An adhesive/barrier layer is sputtered between the polymer layer 34 and the opening 34a. a copper pad) having a thickness between Q micrometers and 1 micrometer (preferably between 0.03 micrometers and 7 micrometers) and a seed layer of copper is formed on the adhesion/barrier layer. A copper layer clock having a thickness between 1 m 2 and a micron is formed on the seed layer, and a thickness of between 1 micrometer and 10 micrometers is formed on the copper layer and 57 200814213 thickness is between A palladium layer plating between 0.01 micrometers and 5 micrometers is formed on the nickel layer, wherein the material of the adhesion/barrier layer comprises titanium, titanium tungsten alloy, titanium nitride, chromium or tantalum nitride; or the metal line 32 includes thickness An adhesion/barrier layer sputtering between 0.01 microns and 0.7 microns (preferably between 0.03 microns and 0.7 microns) On the polymer layer 34 and the pad 16 (for example, an aluminum pad or a copper pad) exposed by the opening 34a, the thickness is between 0.03 micrometers and 1 micrometer (preferably between 0.03 micrometers and 0.7 micrometers). And a sub-layer sputtering of copper is formed on the adhesion/barrier layer, and a copper layer having a thickness between f 1 μm and 20 μm is electroplated on the seed layer and has a thickness of 1 μm to 10 μm. A nickel layer is electroplated on the copper layer and a palladium layer having a thickness of between 0.05 micrometers and 2 micrometers is electrolessly plated on the nickel layer, wherein the material of the adhesion/barrier layer comprises titanium, titanium tungsten alloy, Titanium nitride, chrome or nitride button. In addition, the metal line 32 includes at least one wire contact as a bonding wire. For example, the metal wire 32 includes a first wire bonding contact 32a and a second wire bonding contact 32b. The first wire bonding contact is viewed from a top perspective view. The position of 32a is located on the pad 16 connected to the metal line 32, and the position of the second wire contact 32b is different from the position of the pad 16 to which the metal line 32 is connected. Therefore, the present invention can be used according to requirements. In the subsequent process, it is selected to join a wire conductor (such as a gold wire) to the first wire contact 32a, a wire wire (such as a gold wire) to the second wire contact 32b, or a wire wire (such as a gold wire). To the first bonding contact 32a and the second bonding contact 32b, after the metal wiring 32 is formed, the semiconductor wafer is diced to form a plurality of semiconductor wafers 36. 58 200814213 Referring to Figures 7C and 7D, the present invention may also form a polymer layer 38 on the metal line 32 after polymerization of the metal lines 32 (as shown in Figures 7A and 7B). The metal layer 32 is exposed on the object layer 34 and at least one opening 38a in the polymer layer 38. The position of the metal line 32 exposed by the opening 38a may be different from the metal line 32 from a top perspective view. The position of the connected pad 16 is such that the metal line 32 exposed by the opening 38a serves as a wire bonding contact for bonding the wire bonding wire. For example, the two openings 38a respectively expose a first wire bonding point 32a and a metal wire 32. The second wire contact 32b is viewed from a top perspective view, the position of the first wire contact 32a is above the pad 16 to which the metal line 32 is connected, and the position of the second wire contact 32b is different from the metal line. The position of the connected pads 16 of the present invention. Therefore, the present invention can selectively engage a wire bonding wire (for example, a gold wire) to the first wire bonding contact 32a and a wire bonding wire (such as a gold wire) to the first process. Second-line connection Point 32b or a wire bonding wire (e.g., gold wire) is bonded to the first wire bonding node 32a and the second wire bonding node 32b, respectively. The polymer layer 38 is, for example, selected from the group consisting of polyimine (PI), epoxy, phenylcyclobutene (BCB), polyurethane, polyparaxylene polymer, solder mask material, and elastomer. One of the (elastomer) or porous dielectric materials, and the thickness of the polymer layer 38 is, for example, between 3 microns and 25 microns. For example, the polymer layer 38 can be a layer of polyamidene having a thickness between 3 microns and 25 microns on the metal line 32, and the opening in the polyimine layer exposes the gold of the metal line 32. a layer or a palladium layer; or, the polymer layer 38 may be an epoxy 59 having a thickness between 3 microns and 25 microns. The 200814213 resin layer is on the metal line 32 and is exposed in one of the openings in the epoxy layer. a gold or palladium layer of metal line 32; alternatively, polymer layer 38 may be a layer of phenylcyclobutene having a thickness between 3 microns and 25 microns on metal line 32 and at phenylcyclobutene One of the openings in the layer exposes a gold or palladium layer of metal line 32. Further, the manner in which the polymer layer 38 is formed includes spin coating, press bonding, or screen printing. Next, after the polymer layer 38 is formed, the semiconductor wafer is diced to form a plurality of semiconductor wafers 40. In addition, referring to FIG. 7E, the present invention may also not form the polymer layer 34 on the protective layer 14, that is, the metal line 32 is formed on the protective layer 14, and is connected to the pad 16 through the opening 14a (for example, an aluminum pad or a copper pad), wherein the metal line 32 includes at least one wire contact as a bonding wire, for example, the metal wire 32 includes a first wire bonding contact 32a and a second wire bonding contact 32b, viewed from a top perspective view, first The position of the wire bonding contact 32a is above the pad 16 to which the metal wire 32 is connected, and the position of the second wire bonding contact 32b is different from the position of the pad 16 to which the metal wire 32 is connected. Therefore, the present invention can be adapted to the requirements. In the subsequent process, it is selected to join a wire conductor (such as a gold wire) to the first wire contact 32a, a wire wire (such as a gold wire) to a second wire contact 32b, or a wire wire (such as a gold wire). ) to the first wire bonding contact 32a and the second wire bonding contact 32b. For a detailed description of the metal line 32, please refer to the description of Figures 7A and 7B above, which will not be described in detail herein. Next, after the metal wiring 32 is formed, the semiconductor wafer is diced to form a plurality of semiconductor wafers 42. Referring to FIG. 7F, the present invention, after forming the metal line 32, 200814213 (as shown in FIG. 7E), may also form a polymer layer 38 on the metal line 32 and at least within the polymer layer 38. An opening 38a exposes the metal line 32, and the position of the metal line 32 exposed by the opening 38a may be different from the position of the pad 16 to which the metal line 32 is connected, as viewed from a top perspective view, wherein the opening 38a is exposed The metal line 32 is used as a wire bonding joint for bonding the wire bonding wires. For example, the two openings 38a respectively expose a first wire bonding node 32a and a second wire bonding node 32b of a metal wire 32. The position of the one-wire contact 32a is located on the pad 16 to which the metal line 32 is connected, and the position of the second wire contact 32b is different from the position of the pad 16 to which the metal line 32 is connected, so the present invention can be In the subsequent process, it is required to join a wire conductor (such as gold wire) to the first wire contact 32a, join a wire wire (such as gold wire) to the second wire contact 32b or respectively engage a wire wire (for example Line) to a first contact point 32a and the wire contacts the second wire 32b. For a detailed description of the polymer layer 38, please refer to the descriptions of Figures 7C and 7D above, and will not be described in detail herein. Next, after the polymer layer 38 is formed, the semiconductor wafer is diced to form a plurality of semiconductor wafers 44. Referring to FIG. 8A, the present invention can form a metal line 32 on a polymer layer 34 and connect the metal protective cover 18 through the polymer layer opening 34a, wherein the polymer layer 34 is tied to the protective layer 14. And an opening 34a in the polymer layer 34 exposes an aluminum-containing metal layer (for example, a layer or an alloy layer) of the metal protective cover 18, and the metal line 32 is connected to the metal-containing layer through the opening 34a ( For example, a layer of inscription or a layer of alloy, the metal protective cover 18 is located on the opening 61a of the main material including copper pad 61 200814213 16 (ie copper pad). For a detailed description of the polymer layer 34, please refer to the description of Figures 7A and 7B above, which will not be described in detail herein. The material of the metal line 32 includes gold, copper, nickel or palladium, and the manner of forming the metal line 32 includes a sputtering process, an electroplating process or an electroless plating process. For example, the metal line 32 includes an adhesion/barrier layer sputtering formed in a polymerization thickness between 〇〇1 μm and 〇7 μm (preferably between 〇·〇3 μm and 〇.7 μm). The metal layer (such as an aluminum layer or an aluminum alloy layer) of the metal protective cover 18 exposed on the object layer 34 and the opening 34a has a thickness of between 0.03 micrometers and 1 micrometer (preferably between子 3 microns to 〇 7 microns) and a sub-layer of gold is sputtered on the adhesion/barrier layer and a gold layer between 1 micron and 30 microns thick is formed in the seed layer. The material of the adhesion/barrier layer comprises titanium, titanium tungsten alloy, titanium nitride, chromium or nitride button, and the preferred thickness of the gold layer is between 2 micrometers and 20 micrometers; or, metal lines 32 includes an adhesion/barrier layer sputtering formed on the polymer layer 34 and having an opening thickness between 〇〇1 μm and 〇.7 μm (preferably between 0.03 μm and 0.7 μm) 3 as in the exposed metal protective cover 18 of the aluminum-containing metal layer (for example, an aluminum layer or an aluminum alloy layer), thickness A sublayer of bismuth between 〇〇3 microns and 丨micron (preferably; between 0.03 microns and 〇7 microns) and formed of copper is formed on the adhesion/barrier layer and has a thickness of i A copper layer plating between micrometers and 2 micrometers is formed on the seed layer, and a recording layer having a thickness of between 丨 micrometers and 1 micrometer is plated on the copper layer and has a thickness of between 1 micrometer and 5 micrometers. A gold layer of electric ore between the micrometers is formed on the recording layer, wherein the material of the adhesion/barrier layer comprises titanium, titanium tungsten alloy, titanium nitride, chromium or nitride button; or, gold 62 200814213 belongs to the line 32 including thickness An adhesive/barrier layer splashing between 1 micron and 7 micron (preferably between 3 micrometers and 〇7 micrometers) is formed on the polymer layer 34 and the opening 3 The exposed metal protective cover W has an aluminum-containing metal layer (for example, an aluminum layer or an aluminum alloy layer) having a thickness of between 0.03 micrometers and 1 micrometer (preferably between 〇〇3 micrometers and 〇7). A sub-layer of material between the micron and copper is formed on the adhesion/barrier layer and has a thickness ranging from 1 micron to 2G micro The intercalation between the copper layer and the thickness of the seed layer formed between 1 micron and 1 micron is formed on the steel layer and a gold thickness between 0. 05 micrometers and 2 micrometers. The layer is electrolessly plated on the nickel layer, wherein the material of the adhesion/barrier layer comprises titanium, titanium tungsten alloy, titanium nitride, chromium or nitride button; or the metal line 32 comprises a thickness of between 1 micron and 0.7. An adhesion/barrier layer between micrometers (preferably between 〇〇3 micrometers and 〇7 micrometers) is formed by sputtering on the polymer layer 34 and the aluminum protective cover 18 exposed by the opening 34a. a metal layer (for example, an aluminum layer or an aluminum alloy layer) having a thickness between 〇〇3 μm and 丨μm (preferably between 0.03 μm and 〇·7 μm) and a material of copper Layer sputtering is formed on the adhesion/barrier layer, and a copper layer having a thickness between 丨 micrometers and 2 micrometers is electroplated to form a nickel layer formed on the seed layer and having a thickness between 丨 micrometers to micrometers. Electroplating on a copper layer and a palladium layer having a thickness between 微米ι μm and 5 μm On the nickel layer, the material of the adhesion/barrier layer comprises titanium, titanium tungsten alloy, titanium nitride, chromium or nitride button; or the metal line 32 comprises a thickness between 〇〇1 μm and 〇·7 μm. (Adhesively between 0. 03 micrometers and 〇 7 micrometers) an adhesion/barrier layer is formed on the polymer layer 34 and exposed by the opening 34a. 63 200814213 Cover 18 A sub-layer splash of aluminum-containing metal layer (for example, an aluminum layer or an aluminum alloy layer) having a thickness of between 0.03 micrometers and 1 micrometer (preferably between 0.03 micrometers and 0.7 micrometers) and having a material of copper Plating a copper layer formed on the adhesion/barrier layer and having a thickness between 1 micrometer and 20 micrometers is formed on the seed layer, and a nickel layer having a thickness of between 1 micrometer and 10 micrometers is electroplated to form a copper layer. A palladium layer having a thickness of between 0.05 micrometers and 2 micrometers is electrolessly plated on the nickel layer, wherein the material of the adhesion/barrier layer comprises titanium, titanium tungsten alloy, titanium nitride, chromium or tantalum nitride. In addition, the metal line 32 includes at least one wire contact as the junction wire, for example, the metal wire 32 includes a first wire contact 32a and a second wire contact 32b, viewed from a top perspective view, the first line The position of the contact 32a is located above the metal protection cover 18 to which the metal line 32 is connected, and the position of the second connection line 32b is different from the position of the metal protection cover 18 to which the metal line 32 is connected, so the present invention can be In the subsequent process, it is required to join a wire conductor (such as a gold wire) to the first wire contact 32a, a wire wire (such as a gold wire) to a second wire contact 32b, or a wire wire (such as gold). Line) to the first I line contact 32a and the second line contact 32b. Next, after the metal wiring 32 is formed, the semiconductor wafer is cut by dicing to form a plurality of semiconductor wafers 46. Referring to FIG. 8B, after forming the metal line 32 (as shown in FIG. 8A), a polymer layer 38 may be formed on the metal line 32 and the polymer layer 34, and in the polymer. At least one opening 38a in layer 38 exposes metal line 32, and from a top perspective view, the location of metal line 32 exposed by opening 38a may be different from metal protective cover 18 to which metal line 32 64 200814213 is attached. The position, wherein the metal line 32 exposed by the opening 38a serves as a wire bonding contact for the bonding wire, for example, the two openings 38a respectively expose a first wire contact 32a and a second wire contact 32b of the metal wire 32. Viewed from a perspective view, the position of the first wire contact 32a is above the metal protection cover 18 to which the metal line 32 is connected, and the position of the second wire contact 32b is different from the metal protection cover to which the metal line 32 is attached. 18 position, so the present invention can be selected in the subsequent process, a single wire conductor (such as gold wire) is selected to the first wire bonding point 32a, a wire bonding wire (such as gold wire) is joined to the second wire bonding. 32b engage a wire or conductor (e.g., gold wire) to the first contact point 32a and the wire contacts the second wire 32b. For a detailed description of the polymer layer 38, please refer to the descriptions of Figures 7C and 7D above, which will not be described in detail herein. Next, after forming the polymer layer 38, the semiconductor wafer is diced to form a plurality of semiconductor wafers 48. Referring to FIG. 8C, the present invention may also not form the polymer layer 34 on the protective layer 14, that is, the metal line 32 is formed on the protective layer 14 and the metal-containing layer of the metal protective cover 18 (for example, a layer or a layer) On the alloy layer, wherein the metal line 32 includes at least one wire contact as a bonding wire, for example, the metal circuit 32 includes a first wire bonding contact 32a and a second wire bonding contact 32b, viewed from a top perspective view. The position of the first wire contact 32a is above the metal protection cover 18 to which the metal line 32 is connected, and the position of the second wire contact 32b is different from the position of the metal protection cover 18 to which the metal line 32 is connected. According to the invention, in the subsequent process, a wire bonding wire (for example, a gold wire) is bonded to the first wire bonding contact 32a, a 65 200814213 wire bonding wire (for example, a gold wire) is connected to the second wire bonding contact 32b, or a bonding wire is respectively connected. A wire conductor (for example, a gold wire) is connected to the first wire bonding contact 32a and the second wire bonding contact 32b. For a detailed description of the metal line 32, please refer to the description of Figures 7A and 7B above, which will not be described in detail herein. Next, after the metal wiring 32 is formed, the semiconductor wafer is diced to form a plurality of semiconductor wafers 50. Referring to FIG. 8D, after forming the metal line 32 (as shown in FIG. 8C), a polymer layer 38 may be formed on the metal line 32 and at least one of the polymer layers 38. The opening 38a exposes the metal line 32, and the position of the metal line 32 exposed by the opening 38a may be different from the position of the metal protective cover 18 to which the metal line 32 is attached, as viewed from a top perspective view, wherein the opening 38a is exposed The metal line 32 is used as a wire bonding joint for bonding the wire bonding wires. For example, the two openings 38a respectively expose a first wire bonding node 32a and a second wire bonding node 32b of the metal wire 32, which are viewed from a top perspective view. The position of the wire bonding contact 32a is located above the metal protection cover 18 to which the metal wire 32 is connected, and the position of the second wire bonding contact 32b is different from the position of the metal protection cover 18 to which the metal wire 32 is connected, so the present invention can According to the requirements in the subsequent process, it is selected to join a wire conductor (such as gold wire) to the first wire contact 32a, join a wire wire (such as gold wire) to the second wire contact 32b or respectively engage a dozen Wire (e.g., gold wire) to the first contact point 32a and the wire contacts the second wire 32b. For a detailed description of the polymer layer 38, please refer to the description of Figures 7C and 7D above, which will not be described in detail herein. Next, after the polymer layer 38 is formed, the semiconductor wafer is diced to form a plurality of semiconductor wafers 52. 66 200814213 First Embodiment Referring to FIG. 9A, a plurality of adhesive materials 54 are formed on a substrate 56 through a dispensing process; then, a plurality of semiconductor wafers 23 are respectively pressed against the adhesive materials. 54, and after the baking process, the semiconductor wafer 23 is adhered to the substrate 56, that is, the semiconductor wafer 23 is adhered to the substrate 56 through the adhesive material 54 to the semiconductor substrate 2. Wherein, the material of the adhesive material 54 is, for example, a polymer material (for example, polyimide, epoxy or silver glue), and the thickness is between 1 micrometer and 50 micrometers, for example, the adhesive material 54 may have a thickness of 1 Polyimine between micrometers and 50 micrometers, or epoxy resin having a thickness between 1 micrometer and 50 micrometers, or silver-filed epoxy having a thickness between 1 micrometer and 50 micrometers. Further, the substrate 56 may be a spherical grid array (BGA) substrate having a thickness between 200 micrometers and 2,000 micrometers; or the substrate 56 may be a glass fiber having a thickness between 200 micrometers and 2,000 micrometers. a substrate with an epoxy resin; or, the substrate 56 may be a glass substrate having a thickness between 200 micrometers and 2,000 micrometers; or, the substrate 56 may be a germanium substrate having a thickness between 200 micrometers and 2,000 micrometers; or The substrate 56 may be a ceramic substrate having a thickness between 200 micrometers and 2,000 micrometers; or the substrate 56 may be an organic substrate having a thickness between 200 micrometers and 2,000 micrometers; or the substrate 56 may have a thickness between 20 A metal substrate of between 0 micrometers and 2,000 micrometers and comprising aluminum material; or the substrate 56 may be a metal substrate having a thickness between 200 micrometers and 2,000 micrometers and 67 200814213 material comprising copper. Referring to FIG. 9B, a ball of one wire conductor 58 is bonded to one of the wire pads 22 of a semiconductor wafer 23 through a one-wire process (eg, a gold or palladium layer bonded to the wire bond pads 22). The other end of the wire bonding wire 58 is wedge-bonded to a contact 57 of one of the metal wires of the substrate 56, wherein the wire bonding wire 58 is, for example, between 20 micrometers and 50 micrometers in diameter and contains a material. A metal wire of gold (or gold wire). Therefore, the bonding pads 22 of the semiconductor wafer 23 are electrically connected to the gold P of the substrate 56. Referring to FIG. 9C, a polymer material 60 having a thickness t5 between 250 micrometers and 1,000 micrometers is formed on the substrate 56 and covers the semiconductor wafer 23 and the wire bonding wires 58 in which the polymer material is formed. The method includes a molding process or a dispensing process, and the material of the polymer material 6醯 comprises polyimine (PI), phenylcyclobutene (BCB) or epoxy resin ( Exp〇y resin). For example, a polyimine having a thickness t5 between 25 μm and micron is formed on the substrate 56 by the filling process and covers the semiconductor wafer 23 and the wire bonding wire 58; or, by using a film filling process, the thickness t5 is 25 〇. Phenylcyclobutene between micrometers and 1,000 micrometers is on the substrate 56 and covers the semiconductor wafer 23 and the wire bonding wires 58; or, by using a film filling process, the thickness t5 is between 250 micrometers and 1,0 micrometers. And the epoxy resin-containing polymer material is on the substrate 56 and covers the semiconductor wafer 23 and the wire bonding wire 58, for example, 'forming a thickness of t5 between 25 〇 micrometers to 1, 〇〇〇68 200814213 micrometers by using a dispensing process. The quinone imine is on the substrate 56 and covers the semiconductor wafer 23 and the wire bonding wire 58; or, by using a dispensing process, a phenylcyclobutene having a thickness t5 of between 250 μm and 1,000 μm is formed on the substrate 56 and covers the semiconductor. The wafer 23 and the wire bonding wire 58; or, by using a dispensing process, a polymer material having a thickness t5 between 250 micrometers and 1,000 micrometers and containing an epoxy resin on the substrate 56 and covering the semiconductor wafer 23 and the wire bonding wire 58 〇Please refer to FIG. 9D to form a lead-free solder on a contact 64 of the substrate 56 by a ball planting process or a screen printing process. And then performing a reflow process on the error-free solder in an environment where the temperature is between 200 ° C and 300 ° C (preferably between 230 ° C and 260 ° C). A lead-free solder ball 62 having a diameter d between 0.25 cm and 1.2 cm is formed on the joint 64 of the substrate 56, wherein the reflow process is between 5 seconds and 90 seconds. Preferably, it is between 20 seconds and 40 seconds. In addition, the material of the lead-free solder ball 62 may be a tin-lead alloy, a tin-silver alloy, a tin-silver-copper alloy or a lead-free alloy. ). Further, since the ball-free solder ball 62 is bonded to the contact 64 of the metal line of one of the substrates 56, the lead-free solder ball 62 is electrically connected to the wire bonding wire 58. Referring to Figure 9E, after forming the lead-free solder balls 62, the substrate 56 and the polymeric material 60 are cut (e.g., mechanically cut) to form a plurality of wafer package structures 66. In FIG. 9E, the substrate 56 includes a first surface and a second surface, and the first surface and the second surface are opposite surfaces, 69 200814213 wherein the adhesive material 54 and the polymeric material 60 are tied to the first surface. The upper (the semiconductor wafer 23 is adhered to the first surface through the adhesive material 54), and the lead-free solder ball 62 is positioned on the second surface. Referring to FIGS. 10A to 10L, respectively, the present invention may also use semiconductor wafers 31, 36, 40, 42, 44, 46, 48, 50 through the steps described in FIGS. 9A to 9D. Substituting the semiconductor wafer 23 in the series of FIG. 9 and, after forming the lead-free solder balls 62, cutting (eg, mechanically cutting) the substrate 56 and the polymer material 60 to form the wafer package structures 68, 70, 72, respectively. 74, 76, 78, 80, 82 and 84. For details, please refer to the descriptions of Figs. 9A to 9E, which will not be described in detail herein. In addition, in the 10Cth to 10thth drawings, the position where the wire bonding wire 58 engages the metal wire 32 is viewed from a top perspective view, and the position may be different from the position of the pad 16 to which the metal wire 32 is connected, or different from The location of the metal protective cover 18 to which the metal line 32 is attached. Therefore, in the 10Cth to 10thth drawings, the metal line 32 may include a first wire bonding contact 32a and a second wire bonding contact 32b. The position of the first wire bonding pad 32a is viewed from a top perspective view. The position is above the pad 16 to which the metal line 32 is connected, and the position of the second wire contact 32b is different from the position of the pad 16 to which the metal line 32 is connected, so the present invention can optionally engage a wire conductor 58 (eg Gold wire) to the first wire bonding point 32a, joining a wire bonding wire 58 (for example, gold wire) to the second wire bonding contact 32b or respectively bonding a wire bonding wire 58 (for example, a gold wire) to the first bonding wire contact 32a and the first Two-line contact 32b. Second Embodiment 200814213 Referring to FIG. 11A, a plurality of adhesive materials 54 are formed on a plurality of wafer carriers 86a of a lead frame 86 through a dispensing process; The plurality of semiconductor wafers 23 are respectively pressed against the adhesive materials 54, and the semiconductor wafers 23 are adhered to the wafer carrier 86a after the baking process. Therefore, the semiconductor wafer 23 is adhered to the wafer carrier 86a via the adhesive material 54 with the semiconductor substrate 2. Wherein, the material of the adhesive material 54 is, for example, a polymer material (for example, polyimide, epoxy or silver glue), and the thickness is between 1 micrometer and 50 micrometers, for example, the adhesive material 54 may have a thickness of 1 Polyimine between micrometers and 50 micrometers, or epoxy resin between 1 micrometer and 50 micrometers thick, or silver-filed epoxy having a thickness between 1 micrometer and 50 micrometers . In addition, the material of the lead frame 86 includes copper or a copper alloy, and the thickness t6 of the lead frame 86 is between 100 micrometers and 2,000 micrometers. Referring to FIG. 11B, one end of the wire bonding wire 58 is ball bonded to one of the wire bonding pads 22 of the semiconductor wafer 23 through a one-wire process (for example, a gold layer or a palladium layer bonded to the bonding pad 22). The other end of the wire bonding wire 58 is wedge-bonded to one of the lead 86b of the lead frame 86, wherein the wire bonding wire 58 is, for example, between 20 micrometers and 50 micrometers in diameter and contains a material. A metal wire of gold (or gold wire). Therefore, the wire bonding pad 22 of the semiconductor wafer 23 is electrically connected to the lead 86b of the lead frame 86. Referring to FIG. 11C, the thickness of the wire is formed by a molding process, and the thickness t7 is between 250 micrometers and 1,000 micrometers. A polymer material 71 200814213 material 88 covers the lead frame 86 (which covers the wafer carrier 86a and a portion of the lead 86b), the semiconductor wafer 23 and the wire bonding wire 58, and exposes a part of the lead of the lead frame 86. 86b. The material of the polymer material 88 includes polyimine (PI), phenylcyclobutene (BCB) or epoxy resin (exp〇yresin). For example, a polyimide coated lead frame 86 (which covers the wafer carrier 86a and a portion of the leads 86b) having a thickness t7 between 25 μm and 1000 μm, a semiconductor wafer 23, and a filling process are formed by a film filling process. Wire the wire 58 and expose a portion of the lead 86b of the lead frame 86; or, by using a film filling process, form a phenylcyclobutene coated lead frame 86 having a thickness t7 between 250 μm and 1 μm ( It covers the wafer carrier 86a and the partial leads 86b), the semiconductor wafer 23 and the wire bonding wires 58, and exposes a part of the leads 86b of the lead frame 86; or, by using a film filling process, the thickness t7 is formed to be 250 micrometers. A polymer material containing between 1,000 micrometers and containing epoxy resin covers the lead frame 86 (which covers the wafer carrier 86a and a portion of the leads 86b), the semiconductor wafer 23, and the wire bonding wires 58, and exposes the lead frame 86. Part of the pin 86b. Referring to FIG. 11D, after forming the polymer material 88, the chip package structure 90 (or the lead frame package) is formed by shear trimming and pressing the pins 86b into various pre-designed shapes. , lead-frame package). The lead frame package structure 90 may be a Small Outline Package (SOP), a Thin Small Outline Package (TSOP), or a dual in-line package (Dual).

In-Line Package，DIP)、陶瓷雙列直插式封裝（Ceramic Dual In-Line Package，CDIP)、玻璃陶瓷型雙列直插式封裝（Giass 72 200814213In-Line Package, DIP), Ceramic Dual In-Line Package (CDIP), Glass Ceramic Type Dual In-Line Package (Giass 72 200814213

Ceramic Dual In-Line Packag，CERDIP)、表面貼裝型封裝 (CERQUAD)、陶瓷有引腳晶片承載封裝（Ceramic leaded chip carrier，CLCC)、四方扁平封裝（Quad Flat Package， QFP)、塑膠有引腳晶片承載封裝（Plastic Leaded Chip Carrier，PLCC)、小尺寸 J 形引腳封裝（Small Outline J-lead，SOJ)、小尺寸積體電路封裝（Small Outline Integrated Circuit，SOIC)或交叉引腳封裝（Zig-zag In-line Package，ZIP)等封裝型式。 請分別參閱第12A圖至第12L圖所示，透過上述第 11A圖至第11D圖所述之步驟，本發明亦可使用半導體晶 片 31、36、40、42、44、46、48、50 與 52 來取代第 11 圖系列中的半導體晶片23，並於剪切分離（trim)以及將引 腳86b壓成各種預先設計好之形狀等步驟之後，形成晶片 封裝結構 92、94、96、98、100、102、104、106 與 108， 詳細内容請參閱第11A圖至第11D圖的說明，在此不再詳 加敘述。 另，在第12C圖至第12L圖中，打線導線58接合金 屬線路32的位置從俯視透視圖觀之，此位置可以是不同於 金屬線路32所連接之接墊16的位置，或者是不同於金屬 線路32所連接之金屬保護蓋18的位置。因此，在第12C 圖至第12L圖中，金屬線路32可以是包括一第一打線接 點32a與一第二打線接點32b，從俯視透視圖觀之，第一 打線接塾32a的位置係位在金屬線路32所連接之接墊16 上方，而第二打線接點32b的位置則不同於金屬線路32 73 200814213 所連接之接墊16的位置，所以本發明可選擇接合一打線導 線58(例如金線）至第一打線接點32a、接合一打線導線 58(例如金線）至第二打線接點32b或是分別接合一打線導 線58(例如金線）至第一打線接點32a與第二打線接點32b。 以上所述係藉由實施例說明本發明之特點，其目的在 使熟習該技術者能暸解本發明之内容並據以實施，而非限 定本發明之專利範圍，故，凡其他未脫離本發明所揭示之 精神所完成之等效修飾或修改，仍應包含在以下所述之申 請專利範圍中。 【圖式簡單說明】 圖式說明： 第1圖為習知球型柵狀陣列封裝結構的剖面示意圖。 第2A圖至第2B圖分別為本發明之一結構的剖面示意圖。 第3圖為本發明之一半導體晶片具有打線接墊的剖面示意 圖。 第4A圖至第4G圖為本發明形成打線接墊的製程剖面示意 圖。 第5A圖與第5B圖為本發明之一半導體晶片具有打線接墊 的剖面示意圖。 第6A圖至第6G圖為本發明形成打線接墊的製程剖面示意 圖。 第7A圖與第7F圖分別為本發明之一半導體晶片具有金屬 74 200814213 線路在保護層上方的剖面示意圖。 第8A圖與第8D圖分別為本發明之一半導體晶片具有金屬 線路在保護層上方的剖面示意圖。 第9A圖至第9E圖為本發明之一實施例的製程剖面示意 圖0 之一晶片封裝結構的剖 實施例的製程剖面示意 之一導線架封裝結構的 第10A圖與第l〇L圖分別為本發明 面示意圖。 第11A圖至第iid圖為本發明之一Ceramic Dual In-Line Packag, CERDIP), surface mount package (CERQUAD), ceramic leaded chip carrier (CLCC), quad flat package (QFP), plastic pin Plastic Leaded Chip Carrier (PLCC), Small Outline J-lead (SOJ), Small Outline Integrated Circuit (SOIC) or Cross-Lead Package (Zig) -zag In-line Package, ZIP) and other package types. Referring to FIGS. 12A to 12L, respectively, the present invention may also use semiconductor wafers 31, 36, 40, 42, 44, 46, 48, 50 through the steps described in FIGS. 11A to 11D. Substituting the semiconductor wafer 23 in the series of FIG. 11 and forming the chip package structures 92, 94, 96, 98 after the steps of shearing and pressing the pins 86b into various pre-designed shapes. 100, 102, 104, 106, and 108. For details, refer to the description of FIGS. 11A to 11D, which will not be described in detail herein. In addition, in the 12th to 12th drawings, the position where the wire bonding wire 58 engages the metal wire 32 is viewed from a top perspective view, and the position may be different from the position of the pad 16 to which the metal wire 32 is connected, or different from The location of the metal protective cover 18 to which the metal line 32 is attached. Therefore, in the 12th to 12thth drawings, the metal line 32 may include a first wire bonding contact 32a and a second wire bonding contact 32b. The position of the first wire bonding port 32a is viewed from a top perspective view. The position is above the pad 16 to which the metal line 32 is connected, and the position of the second wire contact 32b is different from the position of the pad 16 to which the metal line 32 73 200814213 is connected, so the present invention can optionally engage a wire conductor 58 ( For example, a gold wire) to the first wire contact 32a, a wire bonding wire 58 (for example, a gold wire) to a second wire bonding node 32b, or a wire bonding wire 58 (for example, a gold wire) to the first wire bonding contact 32a, respectively. The second wire contact 32b. The above description of the embodiments of the present invention is intended to be understood by those skilled in the art, and the invention may be practiced without departing from the scope of the invention. Equivalent modifications or modifications made by the spirit of the invention should still be included in the scope of the claims described below. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic cross-sectional view showing a conventional ball grid array package structure. 2A to 2B are respectively schematic cross-sectional views showing a structure of the present invention. Fig. 3 is a schematic cross-sectional view showing a semiconductor wafer having a wire bonding pad of the present invention. 4A to 4G are schematic cross-sectional views showing a process for forming a wire bonding pad of the present invention. 5A and 5B are schematic cross-sectional views showing a semiconductor wafer having a wire bonding pad according to the present invention. 6A to 6G are schematic cross-sectional views showing a process for forming a wire bonding pad of the present invention. 7A and 7F are respectively schematic cross-sectional views of a semiconductor wafer having a metal 74 200814213 line above a protective layer. 8A and 8D are respectively schematic cross-sectional views showing a semiconductor wafer having a metal line over a protective layer. 9A to 9E are schematic cross-sectional views showing a process of a wafer package structure according to an embodiment of the present invention. FIG. 10A and FIG. A schematic view of the invention. 11A to iid are one of the inventions

圖。 第12A圖與第12L圖分別為本發明 剖面示意圖。 圖號說明： 2半導體基底 6線路結構 1〇金屬插塞 14保護層 16接塾 20結構 23半導體晶片 26種子層 28a光阻層開口 31半導體晶片 4半導體元件 8圖案化金屬層 12介電層Figure. Fig. 12A and Fig. 12L are respectively schematic cross-sectional views of the present invention. Description of the drawings: 2 semiconductor substrate 6 line structure 1 〇 metal plug 14 protective layer 16 interface 20 structure 23 semiconductor wafer 26 seed layer 28a photoresist layer opening 31 semiconductor wafer 4 semiconductor component 8 patterned metal layer 12 dielectric layer

Ma開口 18金屬保護蓋 22打線接墊 24黏著/阻障層 28光阻層 3〇金屬層 32金屬線路 75 200814213 32a打線接點 34聚合物層 36半導體晶片 38a 開口 42半導體晶片 46半導體晶片 50半導體晶片 5 4黏者材料 57接點 60聚合物材料 64接點 68晶片封裝結構 72晶片封裝結構 76晶片封裝結構 80晶片封裝結構 84晶片封裝結構 86a晶片承載座 88聚合物材料 92晶片封裝結構 96晶片封裝結構 100晶片封裝結構 104晶片封裝結構 108晶片封裝結構 112半導體晶片 32b打線接點 34a 開口 38聚合物層 40半導體晶片 44半導體晶片 48半導體晶片 52半導體晶片 56基板 58打線導線 62無鉛錫球 66晶片封裝結構 70晶片封裝結構 74晶片封裝結構 78晶片封裝結構 82晶片封裝結構 86導線架 86b引腳 90晶片封裝結構 94晶片封裝結構 98晶片封裝結構 102晶片封裝結構 106晶片封裝結構 110金線 114鋁金屬保護蓋 76 200814213 116球型柵狀陣列基板 118保護層 118a 開口 122錫球 120銅墊 i, 77Ma opening 18 metal protective cover 22 wire bonding pad 24 adhesion/barrier layer 28 photoresist layer 3 〇 metal layer 32 metal circuit 75 200814213 32a wire bonding 34 polymer layer 36 semiconductor wafer 38a opening 42 semiconductor wafer 46 semiconductor wafer 50 semiconductor Wafer 5 4 Adhesive Material 57 Contact 60 Polymer Material 64 Contact 68 Chip Package Structure 72 Chip Package Structure 76 Chip Package Structure 80 Chip Package Structure 84 Chip Package Structure 86a Wafer Carrier 88 Polymer Material 92 Chip Package Structure 96 Wafer Package structure 100 wafer package structure 104 chip package structure 108 chip package structure 112 semiconductor wafer 32b wire bond 34a opening 38 polymer layer 40 semiconductor wafer 44 semiconductor wafer 48 semiconductor wafer 52 semiconductor wafer 56 substrate 58 wire conductor 62 lead-free solder ball 66 wafer Package Structure 70 Chip Package Structure 74 Chip Package Structure 78 Chip Package Structure 82 Chip Package Structure 86 Lead Frame 86b Pin 90 Chip Package Structure 94 Chip Package Structure 98 Chip Package Structure 102 Chip Package Structure 106 Chip Package Structure 110 Gold Line 114 Aluminum Metal Protective cover 76 200814213 116 spherical grid array Column substrate 118 protective layer 118a opening 122 solder ball 120 copper pad i, 77

Claims (1)

200814213 十、申請專利範圍 1、 一種晶片封裝結構’包括· 一基板； 一無船錫球（lead-free solder ball)，接合該基板； 一黏著材料，位在該基板上； 一半導體晶片’位在該黏者材料上’且該半導體晶片包 括· 一半導體基底； 一線路結構，位在該半導體基底上方； 一保護層，位在該線路結構上方，且位在該保護層 内之一開口暴露出該線路結構之一接墊；以及 一打線接墊，包括一黏著/阻障層與一金屬層位在該 黏著/阻障層上，其中該黏著/阻障層位在該開口所暴 露出之該接墊上，且該金屬層包括一金層； 一打線導線，接合該金層與該基板；以及 一聚合物材料，位在該基板上，並覆蓋該半導體晶片與 該打線導線。 2、 如申請專利範圍第1項所述之晶片封裝結構，其中該基 板為球型柵狀陣列（BGA)基板。 3、 如申請專利範圍第1項所述之晶片封裝結構，其中該基 板為含有玻璃纖維與環氧樹脂的基板。 4、 如申請專利範圍第1項所述之晶片封裝結構，其中該基 板為玻璃基板。 5、 如申請專利範圍第1項所述之晶片封裝結構，其中該基 78 200814213 板為發基板。 6、 如申請專利範圍第1項所述之晶片封裝結構，其中該夷 板為陶瓷基板。 μ 土 7、 如申請專利範圍第旧所述之晶片封裝結構，其中職 板為有機基板。 8、 如申請專利範圍第1項所述之晶片封裝 板為金屬基板。 其中該基 9、 如申請專㈣圍第1項所述之晶片封裝結構，其中該基 板為金屬基板，且該金屬基板的材質包括鋁。 土 10、 如申請專利範圍第旧所述之晶片封裝結構，其中該 基板為金屬基板，且該金屬基板的材質包括銅。’、μ U、如申請專利範圍第！項所述之晶片封裝結構，其中該 基板的厚度係介於200微米至2,000微米之間。 &quot; 12、 如申請專利範圍第旧所述之晶片封裝結構，其中該 匕括第&quot;'表面與—第^表面’且該黏著材料與該聚 1材料位在該第-表面上，該無錯踢球位在該第二表面 上。 13、 如申請專利範圍第1所述之晶片封裝結構，其中該 無鉛錫球的材質包括錫銀合金（tin-Silver allQy)。 14、 如申請專利範圍第旧所述之晶片封裳結構，其中該 無錯錫球的材質包㈣銀銅合金(tin_sil ν—ρρ㈣㈣。 15、 如申請專利範圍第旧所述之晶片封裝結構，其中該 ^錫球的直徑介於〇·251米至12釐米(贿)之間。 申明專利範圍第1項所述之晶片封裝結構，其中該 79 200814213 其中該 黏著材料的厚度係介於1微米至5〇微米之間。 17、如申請專利範圍第1項所述之晶片封裳結構 黏著材料的材質包括聚合物材料。 “如甲請專利範圍第1項所述之晶片封裝結構，其中該 黏著材料的材質包括聚醯亞胺（p〇lyimide，pi &gt;。 19三如申請專利範圍第旧所述之晶片封裝結構，其中該 黏著材料的材質包括環氧樹脂（epoxy resin)。 Λ200814213 X. Patent application scope 1. A chip package structure 'includes a substrate; a lead-free solder ball to bond the substrate; an adhesive material on the substrate; a semiconductor wafer And the semiconductor wafer includes a semiconductor substrate; a wiring structure positioned over the semiconductor substrate; a protective layer positioned over the wiring structure and exposed to an opening in the protective layer a pad of the wire structure; and a wire bonding pad comprising an adhesive/barrier layer and a metal layer on the adhesion/barrier layer, wherein the adhesion/barrier layer is exposed at the opening And the metal layer comprises a gold layer; a wire bonding wire bonding the gold layer and the substrate; and a polymer material disposed on the substrate and covering the semiconductor wafer and the wire bonding wire. 2. The chip package structure of claim 1, wherein the substrate is a ball grid array (BGA) substrate. 3. The wafer package structure of claim 1, wherein the substrate is a substrate comprising glass fibers and an epoxy resin. 4. The chip package structure of claim 1, wherein the substrate is a glass substrate. 5. The chip package structure of claim 1, wherein the base 78 200814213 board is a hair substrate. 6. The chip package structure of claim 1, wherein the slab is a ceramic substrate. μ soil 7. The wafer package structure as described in the patent application scope, wherein the job board is an organic substrate. 8. The chip package board according to claim 1 is a metal substrate. The substrate package structure of claim 1, wherein the substrate is a metal substrate, and the material of the metal substrate comprises aluminum. The substrate package structure of the above-mentioned patent application, wherein the substrate is a metal substrate, and the material of the metal substrate comprises copper. ', μ U, as claimed in the scope of patents! The wafer package structure of the invention, wherein the substrate has a thickness between 200 microns and 2,000 microns. &quot; 12. The wafer package structure of the above-mentioned patent application, wherein the "the surface and the surface of the surface" and the adhesive material and the material 1 are located on the first surface, The error-free kick is on the second surface. 13. The chip package structure of claim 1, wherein the material of the lead-free solder ball comprises tin-silver all-Qy. 14. The wafer sealing structure as described in the patent application scope, wherein the material of the error-free solder ball is (4) silver-copper alloy (tin_sil ν - ρρ (4) (4). 15. The chip package structure as described in the patent application scope, Wherein the diameter of the solder ball is between 251 and 12 cm (brieze). The wafer package structure according to claim 1, wherein the thickness of the adhesive material is between 1 micrometer and The material of the wafer sealing structure adhesive material according to the first aspect of the invention is the polymer material. The wafer packaging structure according to the first aspect of the invention, wherein The material of the adhesive material comprises a polyimine (p〇lyimide, pi &gt; 19). The chip package structure as described in the patent application scope, wherein the material of the adhesive material comprises an epoxy resin. 20、如申請專利範圍第i項所述之晶片封裝 半導體基底包括矽。 八 =如申請專利範圍第1項所述之晶片封裝結構，其中該 半導體基底位在該黏著材料上。 甲味專利範圍第1項所述之晶片封裝結構，更包括 ^少-金氧半導體（MOS)元件位在該半導體基底内或上 方0 &gt; 如申請專利範圍第1項所述之晶片封裝結構，其中 線路結構包括厚度介於G. 2微米至2微米之間的一銅層。 24、如申請專利範圍第W所述之晶片封裝結構，其曰中該 線路結構包括電鍍銅。 人 封裝結構，其中該 米之間的一含鋁金 5如申請專利範圍第1項所述之晶片 線路結構包括厚度介於0·2微米至2微 屬層。 缸如申請相項所叙w料結構，更 複數介電層位在該半導 結構之複數間，且該線路 數圖案化金屬層位在該些介電層之間，並透過位 200814213 鄰兩 在該些介電層内的該線路結構之複數金屬插塞連接相 層之該些圖案化金屬層。 封教結構，其中該 5之間。 封裝結構，其中該 27、 如申請專利範圍第26項所述之晶片 些介電層的介電常數值（k)係介於1.5至 28、 如申請專利範圍第％項所述之晶片 些介電層的材質包括氧矽化合物。 29、如申請專利範圍第26項所述之晶片封袭結構，其中該 些介電層的材質包括氮矽化合物。20. The wafer package semiconductor substrate of claim i wherein the semiconductor substrate comprises germanium. The wafer package structure of claim 1, wherein the semiconductor substrate is on the adhesive material. The chip package structure according to the first aspect of the invention, further comprising: a metal-doped-storage (MOS) device in or on the semiconductor substrate; &gt; The chip package structure as described in claim 1 Wherein the wiring structure comprises a copper layer having a thickness between G. 2 microns and 2 microns. 24. The wafer package structure of claim W, wherein the circuit structure comprises electroplated copper. A package structure in which an aluminum-containing gold 5 between the meters has a thickness of between 0.2 micrometers and 2 micro-layers as described in claim 1 of the wafer wiring structure. The cylinder is as described in the application phase, wherein a plurality of dielectric layers are between the plurality of semiconductor structures, and the number of patterned metal layers is between the dielectric layers and transmitted through the bits 200814213. A plurality of metal plugs of the line structure in the dielectric layers connect the patterned metal layers of the phase layer. The teaching structure, which is between the 5th. a package structure, wherein the dielectric constant value (k) of the dielectric layers of the wafer as described in claim 26 is between 1.5 and 28, and the wafers as described in claim % of the patent application range The material of the electric layer includes an oxonium compound. The wafer encapsulation structure of claim 26, wherein the material of the dielectric layer comprises a nitrogen bismuth compound. 3〇、如申請專利範圍第26項所述之晶片封裝結構，其中該 些介電層的材質包括氮氧石夕化合物。 31、 如申請專利範圍第26項所述之晶片封裂結構，其中該 些介電層的材質包括含矽、碳、氧與氫之化合物。 32、 如中請專鄉圍第26項所述之晶片封裝^構，其中該 些介電層的材質包括氟梦玻璃（FluGHnated ⑴对 33、 如申請專利範圍第26項所述之晶片封震結構，其中該 些介電層的厚度係介於〇·3微米至2·5微米之間。 34、 如申請專利範圍第！項所述之晶片封裝結構，其中該 保護層包括氧石夕化合物。 仏如申請專利範圍第旧所述之晶片封裳結構，其中該 保護層包括氮石夕化合物。 %、如申請專利範圍第w所述之晶片封裝結構，其中該 保護層包括氮氧石夕化合物。 37、如申請專利範圍第！項所述之晶片封褒結構，其中該 保護層的厚度係介於〇·3微米至h5微米&amp;叫之間。 81 200814213 38、如申請專利範圍第1項所述之晶片封裝結構盆 接墊的厚度係介於〇·2微米至2微米之間。 其中該 片封裝結構，其中該 之間的-鋁合金層， 39、如申請專利範圍第1項所述之晶 接墊包括厚度介於〇·2微米至2微米 且該黏著/阻障層位在該鋁合金層上。 4〇、如申請專利範圍第1項所述之晶片封 黏著/阻障層的材質包括鈦。 、〜，其中該The wafer package structure of claim 26, wherein the material of the dielectric layer comprises a oxynitride compound. The wafer-cracking structure of claim 26, wherein the material of the dielectric layer comprises a compound containing ruthenium, carbon, oxygen and hydrogen. 32. The wafer package structure as described in item 26 of the hometown, wherein the materials of the dielectric layers include fluorine dream glass (FluGHnated (1) pair 33, such as the wafer seal described in claim 26 The structure, wherein the thickness of the dielectric layer is between 3·3 μm and 2.5 μm. The wafer package structure according to the item of claim, wherein the protective layer comprises an oxygen compound. For example, the wafer sealing structure of the above-mentioned patent application scope, wherein the protective layer comprises a nitrous oxide compound. The wafer packaging structure according to claim w, wherein the protective layer comprises oxynitrite 37. The wafer package structure of claim 4, wherein the thickness of the protective layer is between 3·3 micrometers to h5 micrometers and amp; 81 200814213 38, as claimed in the patent application The thickness of the wafer package structure of the wafer package structure is in the range of 〇·2 μm to 2 μm. The sheet package structure, wherein the aluminum alloy layer between the three, 39, as claimed in the patent scope Crystal The pad comprises a thickness of between 2 μm and 2 μm and the adhesion/barrier layer is on the aluminum alloy layer. The material of the wafer sealing/barrier layer as described in claim 1 includes Titanium, ~, which 41、 如申請專利範圍第1項所述之晶片封裝於構盆一 黏著/阻障層的材質包括鈦鎢合金。 /、中該 42、 如申請專利範圍第1項所述之晶片封裝結構，1 黏著/阻障層的材質包括氮化鈦。 /、中該 43、 如申請專利範圍第1項所述之晶片封裝結構，盆 黏著/阻障層的材質包括鉻。 其中該 44、 如申請專利範圍第1項所述之晶片封裳結構，並 黏著/阻障層的材質包括钽。 。，其中該 45、 如申請專利範圍第1項所述之晶片封裝結構，1 黏著/阻障層的材質包括氮化组。 /、中“ 46、 如申請專利範圍第1項所述之晶片封裝結構，盆 黏著/阻障層的厚度係介於〇·〇3微米至〇·7微米之門、μ 47、 如申請專利範圍第1項所述之晶片封裂結構，其中該 金屬層更包括材質為金的一種子層位在該黏著/阻：: 上，且該金層位在該種子層上。 9 仆、如申請專利範圍第丨項所述之晶片封襞結構，其中該 金屬層更包括材質為銅的一種子層位在該黏著/阻障層 82 200814213 上、一銅層録雜子層上収—料位在轴層上 該金層位在該鎳層上。 ’其中該 49、如申請專利範圍第1項所述之晶片封裝結構 金層的厚度係介於1微米至20微米之間。 5〇、如申請專利範圍第旧所述之晶片封裝結構，其中該 金層的厚度係介於3微米至5微米之間。 μ 5卜如申請專利範圍第】項所述之晶片封袭結構，其中該 打線接墊的厚度係介於1微米至20微米之間。 、^ …如申請專利範圍第旧所述之晶片封裝結構，其中該 打線接墊的厚度係介於3微米至5微米之間。 ^ …如申請專利範圍第！項所述之晶片封裝結構，其中該 打線導線的材質包括金。 人 54、如申請專利範圍第旧所述之晶片封裝結構，其中該 打線導線的直徑介於20微米至50微米之間。 、以 …如申請專利範圍第1所述之晶片封裝結構，其中該 聚合物材料的材質包括環氧樹脂（ep〇xy)。 、&quot; 56、 如申請專利範圍第旧所述之晶片封裝結構，其中該 聚合物材料的材質包括聚醯亞胺（PI)。 57、 如申請專利範圍第旧所述之晶片封裝結構，其中該 聚合物層材料的材質包括苯基環丁烯(BCB)。 58、 如申請專利範圍第旧所述之晶片封裳結構，其中該 聚合物材料的厚度係介於250微米至1，〇〇〇微米之門 A 59、 如申請專利範圍第丨項所述之晶片封裝結構，^中該 打線導線係透過該基板的一金屬線路電性二 &quot; 弘1王逆接該無鉛錫 83 200814213 球。 60、 一種晶片封裝結構，包括： 一基板； 一無錯錫球（lead-free solder ball)，接合該基板； 一黏著材料，位在該基板上； 一半導體晶片5位在該黏者材料上’且該半導體晶片包 括： 一半導體基底； 一線路結構，位在該半導體基底上方； 一保護層，位在該線路結構上方，且位在該保護層 内之一開口暴露出該線路結構之一銅墊；以及 一打線接墊，包括一黏著/阻障層與一金屬層位在該 黏著/阻障層上，其中該黏著/阻障層位在該開口所暴 露出之該銅墊上，且該金屬層包括一金層； 一打線導線，接合該金層與該基板；以及 一聚合物材料，位在該基板上，並覆蓋該半導體晶片與 該打線導線。 61、 如申請專利範圍第60項所述之晶片封裝結構，其中該 基板為球型柵狀陣列（BGA)基板。 62、 如申請專利範圍第60項所述之晶片封裝結構，其中該 基板為含有玻璃纖維與環氧樹脂的基板。 63、 如申請專利範圍第60項所述之晶片封裝結構，其中該 基板為玻璃基板。 64、 如申請專利範圍第60項所述之晶片封裝結構，其中該 84 200814213 基板為碎基板。 65、 如申請專利範圍第60項所述之晶片封裝結構，其中該 基板為陶瓷基板。 66、 如申請專利範圍第60項所述之晶片封裝結構，其中該 基板為有機基板。 67、 如申請專利範圍第60項所述之晶片封裝結構，其中該 基板為金屬基板。 68、 如申請專利範圍第60項所述之晶片封裝結構，其中該 基板為金屬基板，且該金屬基板的材質包括鋁。 69、 如申請專利範圍第60項所述之晶片封裝結構，其中該 基板為金屬基板，且該金屬基板的材質包括銅。 70、 如申請專利範圍第60項所述之晶片封裝結構，其中該 基板的厚度係介於200微米至2,000微米之間。 71、 如申請專利範圍第60項所述之晶片封裝結構，其中該 基板包括一第一表面與一第二表面，且該黏著材料與該聚 合物材料位在該第一表面上，該無鉛錫球位在該第二表面 上。 72、 如申請專利範圍第60項所述之晶片封裝結構，其中該 無船錫球的材質包括錫銀合金(tin-silver alloy)。 73、 如申請專利範圍第60項所述之晶片封裝結構，其中該 無鉛錫球的材質包括錫銀銅合金（tin-silver-copper alloy)。 74、 如申請專利範圍第60項所述之晶片封裝結構，其中該 無鉛錫球的直徑介於0.25釐米至1.2釐米（mm)之間。 75、 如申請專利範圍第60項所述之晶片封裝結構，其中該 85 200814213 黏著材料的厚度係介於1微米至5〇微米之間。 %、如申請專利範圍第60項所述之晶片封裝結構，其中該 黏著材料的材質包括聚合物材料。 ^ 77、如申請專利範圍第60項所述之晶片封裝結構，其中該 黏者材料的材質包括聚醯亞胺（polyimide，pij。 #如申請專利範圍第60項所述之晶片封裝結構，其中寄 黏著材料的材質包括環氧樹脂（ep〇Xy代以…。41. The material of the wafer package described in claim 1 is encapsulated in a pelvic adhesive/barrier layer comprising a titanium-tungsten alloy. In the wafer package structure described in claim 1, the material of the adhesion/barrier layer comprises titanium nitride. 43. The wafer package structure according to claim 1, wherein the material of the potting/barrier layer comprises chromium. Wherein, the wafer sealing structure as described in claim 1 of the patent application, and the material of the adhesive/barrier layer comprises ruthenium. . 45. The wafer package structure according to claim 1, wherein the material of the adhesion/barrier layer comprises a nitride group. /, "46, as claimed in the patent scope of the wafer package structure, the thickness of the pot adhesion / barrier layer is between 〇 · 〇 3 microns to 〇 · 7 microns door, μ 47, such as the patent application The wafer-splitting structure of claim 1, wherein the metal layer further comprises a sub-layer of gold on the adhesion/resistance: and the gold layer is on the seed layer. The wafer sealing structure of claim 2, wherein the metal layer further comprises a sub-layer of copper material on the adhesion/barrier layer 82 200814213 and a copper layer recording layer. The gold layer is on the nickel layer. The thickness of the gold layer of the wafer package structure as described in claim 1 is between 1 micrometer and 20 micrometers. The wafer package structure of the above-mentioned patent application, wherein the thickness of the gold layer is between 3 micrometers and 5 micrometers, and the wafer sealing structure according to the patent application scope, wherein The thickness of the wire bonding pad is between 1 micrometer and 20 micrometers. The wafer package structure of the above-mentioned patent application, wherein the thickness of the wire bonding pad is between 3 micrometers and 5 micrometers. The wafer packaging structure according to the above-mentioned claim, wherein the wire bonding wire The material of the wafer package structure of the first aspect of the invention, wherein the wire bonding wire has a diameter of between 20 micrometers and 50 micrometers. The package structure, wherein the material of the polymer material comprises an epoxy resin (ep〇xy). The wafer package structure as described in the patent application scope, wherein the material of the polymer material comprises polyimine. (PI) 57. The wafer package structure of the above-mentioned patent application, wherein the material of the polymer layer material comprises phenylcyclobutene (BCB). 58. The wafer seal as described in the patent application scope a skirt structure, wherein the thickness of the polymer material is between 250 micrometers and 1, the gate of the micro-aluminum A 59, the wafer package structure as described in the scope of the patent application, Passing through a metal line of the substrate, the second is reversed to the lead-free tin 83 200814213. 60. A chip package structure comprising: a substrate; a lead-free solder ball, bonding The substrate; an adhesive material on the substrate; a semiconductor wafer 5 on the adhesive material' and the semiconductor wafer comprises: a semiconductor substrate; a wiring structure located above the semiconductor substrate; a protective layer, Positioned above the circuit structure, and one of the openings in the protective layer exposes one of the copper pads of the circuit structure; and a wire bonding pad including an adhesive/barrier layer and a metal layer in the adhesion/resistance a barrier layer, wherein the adhesion/barrier layer is on the copper pad exposed by the opening, and the metal layer comprises a gold layer; a wire bonding wire bonding the gold layer and the substrate; and a polymer material, Positioned on the substrate and covering the semiconductor wafer and the wire bonding wire. The wafer package structure of claim 60, wherein the substrate is a ball grid array (BGA) substrate. The wafer package structure of claim 60, wherein the substrate is a substrate comprising glass fibers and an epoxy resin. The wafer package structure of claim 60, wherein the substrate is a glass substrate. 64. The wafer package structure of claim 60, wherein the 84 200814213 substrate is a broken substrate. The wafer package structure of claim 60, wherein the substrate is a ceramic substrate. The wafer package structure of claim 60, wherein the substrate is an organic substrate. 67. The wafer package structure of claim 60, wherein the substrate is a metal substrate. 68. The chip package structure of claim 60, wherein the substrate is a metal substrate, and the material of the metal substrate comprises aluminum. The wafer package structure of claim 60, wherein the substrate is a metal substrate, and the material of the metal substrate comprises copper. 70. The wafer package structure of claim 60, wherein the substrate has a thickness between 200 microns and 2,000 microns. The wafer package structure of claim 60, wherein the substrate comprises a first surface and a second surface, and the adhesive material and the polymer material are on the first surface, the lead-free tin The ball is on the second surface. The wafer package structure of claim 60, wherein the material of the shipless solder ball comprises a tin-silver alloy. The wafer package structure of claim 60, wherein the material of the lead-free solder ball comprises a tin-silver-copper alloy. The wafer package structure of claim 60, wherein the lead-free solder ball has a diameter of between 0.25 cm and 1.2 cm. 75. The wafer package structure of claim 60, wherein the thickness of the adhesive material is between 1 micrometer and 5 micrometers. The wafer package structure of claim 60, wherein the material of the adhesive material comprises a polymer material. The wafer package structure of claim 60, wherein the material of the adhesive material comprises a polyimide (pij.), such as the chip package structure described in claim 60, wherein The material of the adhesive material includes epoxy resin (ep〇Xy is replaced by... / \ 79、如申請專利範圍第60項所述之晶片封裝結構，其中索 半導體基底包括石夕。 8〇、如申請專利範圍第60項所述之晶片封裝結構，其中該 半導體基底位在該黏著材料上。 人 8卜如申請專利範圍第60項所述之晶片封裝結構，更包括 至少—金氧半導體（MOS)元件位在該半導體基底内或上 封裳結構，其中該 之間的一銅層。 封裝結構，其中該 82、 如申請專利範圍第60項所述之晶片 線路結構包括厚度介於0.2微米至2微米 83、 如申請專利範圍第6〇項所述之晶片 線路結構包括電鏟銅。 ㈣如甲請專利範圍第60項所述之晶片封裳結構，更達 複數介電層位在該半導體基底與該保護層之 #,上仕 曰J 言襄备 〜構之複數圖案化金屬層位在該些介電層 %日〈間，並透封 在該些介電層内的該線路結構之複數金屬插塞連接相糊 層之該些圖案化金屬層。 85、如申請專利範圍第84項所述之晶片封裝結構，其令 86 200814213 些介電層的介電常數值（k)係介於1.5至3之間。 86、 如申請專利範圍第84項所述之晶片封裳結構，其中該 些介電層的材質包括氧矽化合物。 Μ 87、 如申請專利範圍第84項所述之晶片封裝結構，其中該 些介電層的材質包括氮矽化合物。 ^ 封裝結構，其中該 88、如申請專利範圍第84項所述之晶片 些介電層的材質包括氮氧矽化合物。The wafer package structure of claim 60, wherein the semiconductor substrate comprises a stone eve. The wafer package structure of claim 60, wherein the semiconductor substrate is on the adhesive material. The chip package structure of claim 60, further comprising at least a metal oxide semiconductor (MOS) device positioned in or over the semiconductor substrate, wherein a copper layer is between the layers. The package structure, wherein the wafer wiring structure of claim 60, wherein the wafer wiring structure comprises a thickness of between 0.2 μm and 2 μm, and the wafer wiring structure as described in claim 6 includes the electric shovel copper. (4) A wafer sealing structure as described in item 60 of the patent scope, and a plurality of dielectric layers on the semiconductor substrate and the protective layer #, 上 曰 构 构 构 构 构 构 构 构 构 构 构 构The plurality of metal plugs of the line structure interposed between the dielectric layers and the dielectric layers are connected to the patterned metal layers of the paste layer. 85. The wafer package structure of claim 84, wherein the dielectric constants (k) of the dielectric layers of 86 200814213 are between 1.5 and 3. 86. The wafer sealing structure of claim 84, wherein the material of the dielectric layer comprises an oxonium compound. The wafer package structure of claim 84, wherein the material of the dielectric layer comprises a nitrogen cerium compound. The package structure, wherein the material of the dielectric layers of the wafer according to claim 84 of the patent application includes the oxynitride compound. 的、如申請專利範圍第84項所述之晶片封裝結構，其中該 些介電層的材質包括含矽、碳、氧與氫之化合物。 Χ 、如甲^專職圍第84項所述之晶片料結構其中該 些介電層的材質包括氟碎玻璃（Flu。細ted叫丨 91、如申請專利範圍第84項所述之晶片封裝結構，其中該 些介電層的厚度係介於0·3微米至2·5微米之間。、μ .如申請專利範圍第60項所述之晶片封裝結構， 保護層包括氧矽化合物。 以The chip package structure of claim 84, wherein the material of the dielectric layer comprises a compound containing ruthenium, carbon, oxygen and hydrogen. The wafer material structure of the above-mentioned dielectric layer, including the fluorine cullet (Flu. The thickness of the dielectric layer is between 0.3 micrometer and 2.5 micrometer. The wafer package structure according to claim 60, wherein the protective layer comprises an oxonium compound. 93、如申請專利範圍第60項所述之晶片 保護層包括氮矽化合物。 封袭結構，其中該 =::氧=。項所述之“封裝結構，其中該 如甲請專利範 乐OU項所迷之晶片封裝結構， 保護層的厚度係介於〇.3微米S 1.5微米Um)°之間。 96、如中請專利範圍第60項所述之晶片封裝結構二 銅墊的厚度係介於〇.2微米至2微米之間。 八&quot; 91、 如申請專利範圍第60項所述之晶片 封裝結構，其中該 87 200814213 黏著/阻障層的材質包括鈦。 98、如申請專利範圍第6〇項所述之晶片封袭結構，其中該 黏著/阻障層的材質包括鈦鎢合金。 ’、^ &quot;、如申請專利範圍第6〇項所述之晶片封裝結構，其中該 黏著/阻障層的材質包括氮化鈦。 人 100、如中請專利範圍第60項所述之晶片封裝結構，並中 該黏著/阻障層的材質包括鉻。 /、 101如中請專利範圍第60項所述之晶片封裝結構，其中 該黏著/阻障層的材質包括|旦。 如中請專利範圍第_所述之晶片封裝結構，其中 該黏著/阻障層的材質包括氮化鈕。 103、#如中請專利範圍第60項所述之晶片封裝結構，其中 該黏著/阻障層的厚度係介於0.03微米至〇 7微米之門 1 〇 4、如申請專利範圍第6 〇項所述之晶片 曰° 該金屬層更包括材質為金的一種子層位在二阻:層中 上，且該金層位在該種子層上。 ⑽、如中請專利範圍第60項所述之晶片封裝結構， 該金屬層更包括材質為銅的—種子層位在該黏著/阻障層 上、-銅層位在該種子層上以及—鎳層位在該銅層上，I 該金層位在該鎳層上。 106、如申請專圍第則所述之晶（封裝 該金層的厚度係介於1微米至2〇微米之間。 八 1〇7、如中請專利範圍第6G項所述之晶片封裝 該金層的厚度係介於3微米至5微米之間。 /、 88 200814213 108、 如中請專利範㈣6Q項所述之晶片封裝結構其中 該打線接墊的厚度係介於！微米至2〇微米之間。 109、 如中請專利範㈣6G項所述之晶片封裝料，其中 該打線接墊的厚度係介於3微米至5微米之間。 /、 110、 如中請專利範圍第60項所述之晶片封裝結構㈠ 該打線導線的材質包括金。 111、 如中請專利範圍第6G項所述之晶片封裝結構，其中 該打線導線的直徑介於20微米至5〇微米之間。 112、 如中請專利範圍第6G項所述之晶片封裝結構，其中 該聚合物材料的材質包括環氧樹脂（epoxy)。 113、 如中請專利範圍第60項所述之晶片料結構，其中 該聚合物材料的材質包括聚醯亞胺（PI)。 114、 如巾請專利範圍第6G項所述之晶片封裝結構，其中 該聚合物層材料的材質包括苯基環丁烯（Bcb)。 ⑴、如中請專利範圍第_所述之晶片封裝結構，其中 該聚合物材料的厚度係介於250微米至L000微米之間。 116、如中請專㈣圍第60項所述之晶片封裝結構，^中 該打線導線係透過該基板的一金屬線路電性連接該•锡 117、一種晶片封裝結構，包括： 一基板； 一無鉛錫球（lead-free solder ball)，接合該基板· 一黏著材料，位在該基板上； 一半導體晶片，位在該黏著材料上，且該半導體晶片包 89 200814213 括： 一半導體基底； 一線路結構，位在該半導體基底上方； 一保護層，位在該線路結構上方，且位在該保護層 内之一開口暴露出該線路結構之一接墊；以及 一打線接墊，包括一黏著/阻障層與一金屬層位在該 黏著/阻障層上，其中該黏著/阻障層位在該開口所暴 露出之該接墊上，且該金屬層包括一鈀（pd)層； 一打線導線，接合該鈀層與該基板；以及 一聚合物材料，位在該基板上，並覆蓋該半導體晶片與 該打線導線。 118、 如申請專利範圍第117項所述之晶片封裝結構，其中 該基板為球型柵狀陣列（BGA)基板。 119、 如申請專利範圍第117項所述之晶片封裝結構，其中 該基板為含有玻璃纖維與環氧樹脂的基板。 120、 如申請專利範圍第117項所述之晶片封裝結構，其中 該基板為玻璃基板。 121、 如申請專利範圍第117項所述之晶片封裝結構，其中 該基板為矽基板。 122、 如申請專利範圍第117項所述之晶片封裝結構，其中 該基板為陶瓷基板。 123、 如申請專利範圍第117項所述之晶片封裝結構，其中 該基板為有機基板。 124、 如申請專利範圍第117項所述之晶片封裝結構，其中 200814213 該基板為金屬基板。 125、 如申請專利範圍第117項所述之晶片封裝結構，其中 該基板為金屬基板，且該金屬基板的材質包括鋁。 126、 如申請專利範圍第117項所述之晶片封裝結構，其中 該基板為金屬基板，且該金屬基板的材質包括銅。 127、 如申請專利範圍第117項所述之晶片封裝結構，其中 該基板的厚度係介於2〇〇微米至2,000微米之間。 128、 如申請專利範圍第117項所述之晶片封裝結構，其中 該基板包括一第一表面與一第二表面，且該黏著材料與該 來a物材料位在該第一表面上，該無錯錫球位在該第一表 面上。 129、 如申請專利範圍第117項所述之晶片封裂結構，其中 該無錯錫球的材質包括錫銀合金(tin-silver alloy；)。 130、 如申請專利範圍第117項所述之晶片封裳結構，其中 該無錯錫球的材質包括錫銀銅合金（tin_silve^e ϊτ r ^ ^ alloy)。 131、 如申請專利範圍第117項所述之晶片封裝結構，其中 該無錯錫球的直徑介於0.25釐米至1.2釐米（mm)之間。 132、 如申請專利範圍第117項所述之晶片封裳結構，其中 該黏著材料的厚度係介於1微米至50微米之間。 133、 如申請專利範圍第117項所述之晶片封裝結構，其中 該黏著材料的材質包括聚合物材料。 134、 如申請專利範圍第117項所述之晶片封褒結構，其中 該黏著材料的材質包括聚醯亞胺（polyimide，。 91 200814213 135、 如申請專利範圍第117項所述之晶片封裝結構，其中 該黏著材料的材質包括環氧樹脂（epoxy resin)。 136、 如申請專利範圍第117項所述之晶片封裝結構，其中 該半導體基底包括碎。 137、 如申請專利範圍第117項所述之晶片封裝結構，其中 該半導體基底位在該黏著材料上。93. The wafer protective layer of claim 60, wherein the wafer protective layer comprises a nitrogen cerium compound. Sealed structure, where =::oxygen=. The package structure described in the item, wherein the wafer package structure as disclosed in the patent OU Le OU item, the thickness of the protective layer is between 〇.3 μm S 1.5 μm Um). The wafer-mounting structure of the copper-clad pad of the invention of claim 60, wherein the thickness of the copper-clad pad is between 0.25 μm and 2 μm, and the chip package structure according to claim 60, wherein 87 200814213 The material of the adhesion/barrier layer comprises titanium. 98. The wafer encapsulation structure according to claim 6 , wherein the material of the adhesion/barrier layer comprises titanium tungsten alloy. ', ^ &quot; The wafer package structure of claim 6, wherein the material of the adhesion/barrier layer comprises titanium nitride. The chip package structure of claim 60, wherein The material of the adhesive/barrier layer comprises a chrome. The wafer package structure of the invention of claim 60, wherein the material of the adhesion/barrier layer comprises: Chip package structure in which the adhesion/resistance The material of the layer includes a nitride button. The chip package structure of claim 60, wherein the thickness of the adhesion/barrier layer is between 0.03 micrometers and 〇7 micrometers. The wafer 曰° as described in claim 6 is further characterized in that the metal layer further comprises a sub-layer of gold in the second layer: the layer, and the gold layer is on the seed layer. (10) The chip package structure of claim 60, wherein the metal layer further comprises a copper-based seed layer on the adhesion/barrier layer, a copper layer on the seed layer, and a nickel layer. On the copper layer, I the gold layer is on the nickel layer. 106. The crystal according to the application specification (the thickness of the gold layer is between 1 micrometer and 2 micrometers. 7. The thickness of the gold layer of the wafer package described in the patent scope of claim 6G is between 3 micrometers and 5 micrometers. /, 88 200814213 108, the wafer package structure described in the patent specification (4) 6Q The thickness of the wire bonding pad is between ! micrometers and 2 micrometers. 109. The wafer package according to the item (4), wherein the thickness of the wire bonding pad is between 3 micrometers and 5 micrometers. /, 110, the chip package structure according to claim 60 of the patent scope (1) the wire bonding wire The material includes gold. 111. The chip package structure according to claim 6G, wherein the wire diameter is between 20 micrometers and 5 micrometers. 112, as claimed in claim 6G The wafer package structure, wherein the material of the polymer material comprises an epoxy resin. The wafer material structure of claim 60, wherein the material of the polymer material comprises polyimine. (PI). 114. The wafer package structure according to claim 6G, wherein the material of the polymer layer material comprises phenylcyclobutene (Bcb). (1) The wafer package structure of the invention, wherein the thickness of the polymer material is between 250 micrometers and L000 micrometers. 116. The chip package structure according to the item (4), wherein the wire is electrically connected to the tin 117 through a metal line of the substrate, and a chip package structure comprises: a substrate; a lead-free solder ball, bonding the substrate, an adhesive material, on the substrate; a semiconductor wafer positioned on the adhesive material, and the semiconductor wafer package 89 200814213 includes: a semiconductor substrate; a wiring structure positioned above the semiconductor substrate; a protective layer positioned above the wiring structure, and an opening in the protective layer exposing one of the wiring structures; and a wire bonding pad including an adhesive a barrier layer and a metal layer on the adhesion/barrier layer, wherein the adhesion/barrier layer is on the pad exposed by the opening, and the metal layer comprises a palladium (pd) layer; a wire bonding wire joining the palladium layer and the substrate; and a polymer material positioned on the substrate and covering the semiconductor wafer and the wire bonding wire. The wafer package structure of claim 117, wherein the substrate is a ball grid array (BGA) substrate. 119. The wafer package structure of claim 117, wherein the substrate is a substrate comprising glass fibers and an epoxy resin. 120. The wafer package structure of claim 117, wherein the substrate is a glass substrate. 121. The wafer package structure of claim 117, wherein the substrate is a germanium substrate. The wafer package structure of claim 117, wherein the substrate is a ceramic substrate. 123. The wafer package structure of claim 117, wherein the substrate is an organic substrate. 124. The chip package structure of claim 117, wherein the substrate is a metal substrate. The chip package structure of claim 117, wherein the substrate is a metal substrate, and the material of the metal substrate comprises aluminum. 126. The chip package structure of claim 117, wherein the substrate is a metal substrate, and the material of the metal substrate comprises copper. 127. The wafer package structure of claim 117, wherein the substrate has a thickness between 2 Å and 2,000 microns. The wafer package structure of claim 117, wherein the substrate comprises a first surface and a second surface, and the adhesive material and the material are located on the first surface, the The wrong tin ball is on the first surface. 129. The wafer chipping structure of claim 117, wherein the material of the error-free solder ball comprises a tin-silver alloy. 130. The wafer sealing structure according to claim 117, wherein the material of the error-free solder ball comprises tin-silve copper alloy (tin_silve^e ϊτ r ^ ^ alloy). The wafer package structure of claim 117, wherein the error-free solder ball has a diameter of between 0.25 cm and 1.2 cm. 132. The wafer sealing structure of claim 117, wherein the thickness of the adhesive material is between 1 micrometer and 50 micrometers. 133. The wafer package structure of claim 117, wherein the material of the adhesive material comprises a polymer material. 134. The wafer sealing structure according to claim 117, wherein the material of the adhesive material comprises polyimide (91 200814213 135, the wafer package structure as described in claim 117, The material of the adhesive material comprises an epoxy resin. The wafer package structure of claim 117, wherein the semiconductor substrate comprises a chip. 137, as described in claim 117. A chip package structure, wherein the semiconductor substrate is on the adhesive material. 138、 如中請專利範圍第117項所述之晶片封裝結構，更包 括至H氧半導體_s)元件位在該半導體基底内或上 B9、如中請專利範圍第117項所述之晶片封裝結構，其中 該線路結構包括厚度介於〇·2微米至2微米 &lt;間的一鋼層。 140、如申請專利範圍第117項所述之晶片封裝結構， 該線路結構包括電鍍銅。 、 ⑷、*申請專利範圍第117項所述之晶片封襄結構，其中 該線路結構包括厚度介於〇·2微米至2微 .Μ 、义間的一含銘 、月專利範圍第117項戶斤述之晶片封裝結構，υ 括複數介電層位在該半導體基底與該保護層之間， L 路結構之複數圖案化金屬層位在該些介電曰且該線 ㈢〈間，並透ig ==電層内的該線路結構之複數金屬插 鄰 兩層之該些圖案化金屬層。 舛 :人如申請專利範圍第142項所述之晶片封裝結構 該二，丨電層的介電常數值（k)係介於15至3之間。、 ⑷、如申請專利範圍第142項所述之晶片封^结構，其中 92 200814213 該些介電層的材質包括氧矽化合物。 145、 如申請專利範圍第142項所述之晶片封袭斧構，其中 該些介電層的材質包括氮矽化合物。 146、 如申請專利範圍第142項所述之晶片封裝結構，其中 該些介電層的材質包括氮氧矽化合物。 147、 如申請專利範圍第142項所述之晶片封裝結構，其中 該些介電層的材質包括含矽、碳、氧與氫之化合物。 148、 如申請專利範圍第142項所述之晶片封裝結構，其中 該些介電層的材質包括氟矽玻璃（Flu〇rinated SiHeate Glass) 〇 149、 如申請專利範圍第ι42項所述之晶片封袭結構，其中 該些介電層的厚度係介於〇·3微米至2.5微来之間。 150、 如申請專利範圍第117項所述之晶片封裝結構，其中 該保護層包括氧矽化合物。 151、 如申請專利範圍第117項所述之晶片封裝結構，其中 該保護層包括氮石夕化合物。 152、 如申請專利範圍第117項所述之晶片封裝結構，其中 該保護層包括氮氧石夕化合物。 153、 如申請專利範圍第117項所述之晶片封裳結構，其中 該保護層的厚度係介於〇·3微米至L5微米m)之間。 154、 如申請專利範圍第117項所述之晶片封裝結構，其中 該接墊的厚度係介於〇·2微米至2微米之間。 155 如申睛專利範圍第117項所述之晶片封裝結構，其中 該接墊包括厚度介於〇·2徵米至2微米之間的一銘合金 93 200814213 層’且該黏著/阻障層位在該鋁合金層上。 156、 如申請專利範圍第117項所述之晶片圭子裝結構，兑中 該黏著/阻障層的材質包括鈦。 ’、 157、 如申請專利範圍第117項所述之晶片封裝結構，其中 該黏著/阻障層的材質包括鈦鎢合金。 ’、 158、 如申請專利範圍第117項所述之晶片封裝結構， 該黏著/阻障層的材質包括氮化鈦。 ^ 159、 如申請專利範圍第117項所述之晶片封裝結構， 該黏著/阻障層的材質包括鉻。 ’、 160、 如申請專利範圍第117項所述之晶片封裳結構， 該黏著/阻障層的材質包括钽。 八 161、 如申請專利範圍第117項所述之晶片封裴結構 該黏著/阻障層的材質包括氮化鈕。 、 162、 #如中請專利範圍第117項所述之晶片封裳結構，其中 該黏著/阻障層的厚度係介於〇·〇3微米至〇·7微米之門、 163、 如申請專利範圍第117項所述之晶片封裝結構，复中 該金屬層更包括材質為銅的—種子層位在該黏著/阻障層 上、一鋼層位在該種子層上以及—鎳層位在該鋼層上，: 該鈀層位在該鎳層上。 曰 164、 如申請專利範圍第117項所述之晶片封震結構， 該鈀層的厚度係介於1微米至20微米之間。 、 165、 如申請專利範圍第117項所述之晶片封裝結構， 該把層的厚度係介於3微米至5微米之間。 166、 如中請專利範圍第117項所述之晶片封裳結構，其中 94 200814213 該打線接墊的厚度係介於1微米至20微米之間。 167、 如申請專利範圍第117項所述之晶片封裝結構，其中 該打線接墊的厚度係介於3微米至5微米之間。 168、 如申請專利範圍第117項所述之晶片封裝結構，其中 該打線導線的材質包括金。 〃 169、 如申請專利範圍第117項所述之晶片封裝結構，其中 該打線導線的直徑介於20微米至50微米之間。 170、 如申請專利範圍第117項所述之晶片封裝結構，其中 該聚合物材料的材質包括環氧樹脂（ep〇xy)。 171、 如申請專利範圍第117項所述之晶片封裝結構，其中 該聚合物材料的材質包括聚醯亞胺（PI)。 172、 如申請專利範圍第117項所述之晶片封裝結構，其中 該聚合物層材料的材質包括苯基環丁烯(BCB)。 173、 如申請專利範圍第117項所述之晶片封裝結構，其中 該聚合物材料的厚度係介於250微米至1，000微米之間。 174、 如申請專利範圍第117項所述之晶片封褒結構，^中 該打線導線係透過該基板的—金屬線路電性連接該益金、 球。 “、、口踢 175、 一種晶片封裝結構，包括： 一基板； 一無錯錫球（lead-free solderball)，接合該基板； 一黏著材料，位在該基板上； -半導體晶片’位在該黏著材料上’且該半導體晶片包 95 200814213 一半導體基底； 一線路結構，位在該半導體基底上方； 一保護層，位在該線路結構上方，且位在該保護層 内之一開口暴露出該線路結構之一銅墊；以及 一打線接墊，包括一黏著/阻障層與一金屬層位在該 黏著/阻障層上，其中該黏著/阻障層位在該開口所暴 露出之該銅墊上，且該金屬層包括一鈀（pd)層； 一打線導線，接合該鈀層與該基板；以及 一聚合物材料’位在該基板上’並覆盖該半導體晶片與 該打線導線。 176、 如申請專利範圍第175項所述之晶片封裝結構，其中 該基板為球型柵狀陣列（BGA)基板。 177、 如申請專利範圍第175項所述之晶片封裝結構，其中 該基板為含有玻璃纖維與環氧樹脂的基板。 178、 如申請專利範圍第175項所述之晶片封裝結構，其中 該基板為玻璃基板。 179、 如申請專利範圍第175項所述之晶片封裝結構，其中 該基板為梦基板。 180、 如申請專利範圍第175項所述之晶片封裝結構，其中 該基板為陶瓷基板。 181、 如申請專利範圍第175項所述之晶片封裝結構，其中 該基板為有機基板。 182、 如申請專利範圍第175項所述之晶片封裝結構，其中 該基板為金屬基板。 96 200814213 183、 如申請專利範圍第175項所述之晶片封襞結構，其中 該基板為金屬基板，且該金屬基板的材質包括鋁。 184、 如申請專利範圍第175項所述之晶片封裝結構，其中 該基板為金屬基板，且該金屬基板的材質包括銅。 185、 如申請專利範圍第175項所述之晶片封裝結構，其中 該基板的厚度係介於200微米至2,000微米之間。 186、 如申請專利範圍第175項所述之晶片封裝結構，其中 … 該基板包括一第一表面與一第二表面，且該黏著材料與該 聚合物材料位在該第一表面上，該無鉛錫球位在該第二^ 面上。 187、 如申請專利範圍第175項所述之晶片封裝結構，其中 該無錯錫球的材質包括錫銀合金（tin-silver alloy)。 188、 如申請專利範圍第175項所述之晶片封裝結構，其中 該無鉛錫球的材質包括錫銀銅合金（tin_silverc〇卯打 alloy) 〇 189、 如申請專利範圍第175項所述之晶片封裝結構，其中 、該無錯錫球的直徑介於〇·25釐米至1·2釐米之間。 190、 如申請專利範圍第175項所述之晶片封裝結構，其中 該黏著材料的厚度係介於1微米至50微米之間。 191、 如申請專利範圍第175項所述之晶片封裝結構，其中 該黏著材料的材質包括聚合物材料。 D2、如申請專利範圍第175項所述之晶片封裝結構，其中 該黏著材料的材質包括聚醯亞胺（polyimide，pij。 193、如申請專利範圍第175項所述之晶片封裝結構，其中 97 200814213 該黏著材料的材質包括環氧樹脂（epOXy resin)。 194、 如申請專利範圍第175項所述之晶片封裝結構，其中 該半導體基底包括矽。 八 195、 如申請專利範圍第175項所述之晶片封裝結構其中 該半導體基底位在該黏著材料上。 196、 如申請專利範圍第175項所述之晶片封裝結構更包 括至少一金氧半導體(MOS)元件位在該半導體基底内或上 方。 / 197、如申請專利範圍第175項所述之晶片封裝結構，其中 該線路結構包括厚度介於〇·2微米至2微米之„从 ^ &lt;間的一銅層。 19 8、如申請專利範圍第丨7 5項所述之晶片封裝結構，其中 該線路結構包括電鍍銅。 199、 如申請專利範圍第175項所述之晶片封裝結構更包 括複數介電層位在該半導體基底與該保護層之間，且談線 路結構之複數圖案化金屬層位在該些介電層 曰又間，並透過 赛 位在該些介電層内的該線路結構之複數金屬插塞連接相鄰 V 兩層之該些圖案化金屬層。 200、 如申請專利範圍第ι99項所述之晶片封裝結構，其中 該些介電層的介電常數值(k)係介於1·5至3之間。、 201、 如申請專利範圍第199項所述之晶片封裝結構，其中 該些介電層的材質包括氧矽化合物。 ’、 202、 如申請專利範圍第199項所述之晶片封裝結構，其中 該些介電層的材質包括氮石夕化合物。 203、 如申請專利範圍第199項所述之晶片封裝結構，其中 98 200814213 該些介電層的材質包括氮氧矽化合物。 204、 如申請專利範圍第199項所述之晶片封裂結構，其中 該些介電層的材質包括含矽、碳、氧與氫之化合物。 205、 如申請專利範圍第I%項所述之晶片封裝結構，其中 該些介電層的材質包括氟矽玻璃（Flu〇rinated smeate Glass) ° 206、 如申請專利範圍第199項所述之晶片封裝結構，其中 該些介電層的厚度係介於〇·3微米至2.5微米之間。 207、 如申請專利範圍第175項所述之晶片封裝結構，其中 該保護層包括氧石夕化合物。 208、 如申請專利範圍第175項所述之晶片封裝結構，其中 該保遵層包括氮碎化合物。 209、 如申請專利範圍第175項所述之晶片封裝結構，其中 該保護層包括氮氧矽化合物。 210、 如申請專利範圍第175項所述之晶片封裳結構，其中 該保護層的厚度係介於〇·3微米至L5微米（以叫之門 211、 如申請專利範圍第175項所述之晶片封裝結構，其中 該銅墊的厚度係介於〇·2微米至2微米之間。 212、 如申請專利範圍第175項所述之晶片封裝結構，其中 該黏著/阻障層的材質包括鈦。 213、 如申請專利範圍第175項所述之晶片封裝結構，其中 該黏著/阻障層的材質包括鈦鎢合金。 Μ、如中請專利範圍第175項所述之晶片封|結構，复中 該黏著/阻障層的材質包括氮化鈦。 ^ 99 200814213 21:二如中請專利範圍第175項所述之晶片封裝結構 該黏者/阻障層的材質包括鉻。 ’、 216、 广申請專利範圍第175項所述之晶片封裝結構， 該黏著/阻障層的材質包括鈕。 八 217、 #如中請專利範圍第175項所述之晶片封裝結構， 該黏著/阻障層的材質包括氮化钽。 218 \如申請專利範圍第175項所述之晶片封裝結構，其中 該黏著/阻障層的厚度係介於〇 〇3微米至〇 7微米 219、 如申請專利範圍第175項所述之晶片封裝結二中 該金屬層更包括材質為銅的—種子層位在該黏著/阻障層 上、一鋼層位在該種子層上以及一鎳層位在該銅層上，I 該鈀層位在該鎳層上。 220、 如中請專利範圍第175項所述之晶片封|結構，其中 該把層的厚度係介於1微米至20微米之間。 221、 如申請專利範圍第175項所述之晶片封裝結構，其中 該絶層的厚度係介於3微米至5微米之間。 222、 如申請專利範圍第175項所述之晶片封裝結構，其中 該打線接墊的厚度係介於1微米至20微米之間。 223、 如申請專利範圍第175項所述之晶片封裝結構，其中 該打線接墊的厚度係介於3微米至5微米之間。 224、 如申請專利範圍第175項所述之晶片封裳結構，其中 該打線導線的材質包括金。 225、 如申請專利範圍第175項所述之晶片封裝結構，其中 該打線導線的直徑介於20微米至50微米之間。 100 200814213 226、 如申請專利範圍第175項所述之晶片封裝結構，其中 該聚合物材料的材質包括環氧樹脂（epoxy)。 227、 如申請專利範圍第175項所述之晶片封裝結構，其中 該聚合物材料的材質包括聚醯亞胺（PI)。 228、 如申請專利範圍第175項所述之晶片封裝結構，其中 該聚合物層材料的材質包括苯基環丁烯（BCB)。 229、 如申請專利範圍第175項所述之晶片封裝結構，其中 該聚合物材料的厚度係介於250微米至1，000微米之間。 230、 如申請專利範圍第175項所述之晶片封裝結構，其中 該打線導線係透過該基板的一金屬線路電性連接該無鉛錫 球。 231、 一種晶片封裝結構，包括： 一基板； 一無船錫球（lead-free solder ball)，接合該基板； 一黏者材料’位在該基板上； 一半導體晶片’位在該黏者材料上5且該半導體晶片包 括： 一半導體基底； 一線路結構，位在該半導體基底上方； 一保護層，位在該線路結構上方，且位在該保護層 内之一開口暴露出該線路結構之一銅墊； 一金屬保護蓋，位在該開口所暴露出之該銅墊上； 以及 一打線接墊，包括一黏著/阻障層與一金屬層位在該 101 200814213 黏著/阻障層上，其中該黏著/阻障層位在該金屬保護 蓋上，且該金屬層包括一金層； 一打線導線，接合該金層與該基板；以及 一聚合物材料，位在該基板上，並覆蓋該半導體晶片與 該打線導線。 232、 如申請專利範圍第231項所述之晶片封裝結構，其中 該基板為球型柵狀陣列（BGA)基板。 233、 如申請專利範圍第231項所述之晶片封裝結構，其中 該基板為含有玻璃纖維與環氧樹脂的基板。 234、 如申請專利範圍第231項所述之晶片封裝結構，其中 該基板為玻璃基板。 235、 如申請專利範圍第231項所述之晶片封裝結構，其中 該基板為碎基板。 236、 如申請專利範圍第231項所述之晶片封裝結構，其中 該基板為陶瓷基板。 237、 如申請專利範圍第231項所述之晶片封裝結構，其中 該基板為有機基板。 238、 如申請專利範圍第231項所述之晶片封裝結構，其中 該基板為金屬基板。 239、 如申請專利範圍第231項所述之晶片封裝結構，其中 該基板為金屬基板，且該金屬基板的材質包括鋁。 240、 如申請專利範圍第231項所述之晶片封裝結構，其中 該基板為金屬基板，且該金屬基板的材質包括銅。 241、 如申請專利範圍第231項所述之晶片封裝結構，其中 102 200814213 該基板的厚度係介於200微米至2,000微米之間。 242、 如申請專利範圍第231項所述之晶片封裝結構，其中 該基板包括一第一表面與一第二表面，且該黏著材料與該 聚合物材料位在該第一表面上，該無錯錫球位在該第一表 面上。 243、 如申請專利範圍第231項所述之晶片封裝結構，其中 該無錯錫球的材質包括錫銀合金（tin_siiver any&gt;。 244、 如申請專利範圍第231項所述之晶片封裝結構，其中 該無錯錫球的材質包括錫銀銅合金⑴n_silveKappa alloy)。 245、 如申請專利範圍第231項所述之晶片封裝結構，其中 該無錯錫球的直徑介於〇·25釐米至1.2釐米（mm)之間。 246、 如申請專利範圍第231項所述之晶片封裝結構，其中 該黏著材料的厚度係介於1微米至50微米之間。 247、 如申請專利範圍第231項所述之晶片封裝結構，其中 該黏著材料的材質包括聚合物材料。 248、 如申請專利範圍第231項所述之晶片封裝結構，其中 該黏著材料的材質包括聚醯亞胺（polyimide，。 249、 如申請專利範圍第231項所述之晶片封裝結構，其中 該黏著材料的材質包括環氧樹脂（epoxy resin)。 250、 如申請專利範圍第231項所述之晶片封裝結構，其中 該半導體基底包括石夕。 25卜如申請專利_第231項所述之晶片封裝結構，其中 該半導體基底位在該黏著材料上。 103 200814213 252、如 括至少一 方0 申請專利範圍第23丨項所述之晶片封裝結構，更包 金氧半導體（MOS)元件位在該半導體其底内 或上 ⑸、如申請專利第231項所述之晶片封裝結構，其中 該線路結構包括厚度介於〇·2微米至2微米之„ &lt;間的一銅層。 254、 如申請專利範圍第231項所述之晶片封裝結構，其中 該線路結構包括電鑛銅。 /138. The chip package structure of claim 117, further comprising: the device to the H-oxide semiconductor_s) in or on the semiconductor substrate, and the chip package as described in claim 117 of the patent application. A structure wherein the wiring structure comprises a steel layer having a thickness of between 2 micrometers and 2 micrometers. 140. The wafer package structure of claim 117, wherein the wiring structure comprises electroplated copper. (4), * The patented wafer sealing structure described in claim 117, wherein the circuit structure includes a thickness of between 〇 2 micrometers to 2 micrometers. The chip package structure includes a plurality of dielectric layers between the semiconductor substrate and the protective layer, and a plurality of patterned metal layers of the L-channel structure are located between the dielectric layers and the lines (3) Ig == The plurality of metals of the line structure in the electrical layer are interposed between the two patterned metal layers.舛 : The wafer package structure as described in claim 142 of the patent application. The dielectric constant value (k) of the tantalum layer is between 15 and 3. (4) The wafer sealing structure of claim 142, wherein the material of the dielectric layer comprises an oxonium compound. 145. The wafer encapsulation axe of claim 142, wherein the material of the dielectric layer comprises a nitrogen hydrazine compound. 146. The chip package structure of claim 142, wherein the material of the dielectric layer comprises a oxynitride compound. 147. The wafer package structure of claim 142, wherein the material of the dielectric layer comprises a compound containing ruthenium, carbon, oxygen and hydrogen. 148. The wafer package structure of claim 142, wherein the material of the dielectric layer comprises a Fluorinated SiHeate Glass, 149, and the wafer seal of claim 4 The structure is characterized in that the thickness of the dielectric layers is between 3·3 μm and 2.5 μm. 150. The wafer package structure of claim 117, wherein the protective layer comprises an oxonium compound. 151. The wafer package structure of claim 117, wherein the protective layer comprises a Nitrogen compound. 152. The wafer package structure of claim 117, wherein the protective layer comprises a oxynitride compound. 153. The wafer sealing structure of claim 117, wherein the protective layer has a thickness between 〇3 μm and L5 μm. 154. The wafer package structure of claim 117, wherein the thickness of the pad is between 2 micrometers and 2 micrometers. 155. The wafer package structure of claim 117, wherein the pad comprises a layer of a layer of alloy 93 and a thickness of between 2 and 2 micrometers, and the adhesion/barrier layer On the aluminum alloy layer. 156. The wafer structure according to claim 117, wherein the material of the adhesion/barrier layer comprises titanium. The chip package structure of claim 117, wherein the material of the adhesion/barrier layer comprises a titanium-tungsten alloy. The chip package structure of claim 117, wherein the material of the adhesion/barrier layer comprises titanium nitride. 159. The wafer package structure of claim 117, wherein the material of the adhesion/barrier layer comprises chromium. The wafer sealing structure of claim 117, wherein the material of the adhesive/barrier layer comprises ruthenium. VIII 161. The wafer sealing structure according to claim 117, wherein the material of the adhesive/barrier layer comprises a nitride button. 162. The wafer sealing structure of claim 117, wherein the thickness of the adhesive/barrier layer is between 〇·〇3 μm to 〇·7 μm, 163, as claimed The chip package structure of claim 117, wherein the metal layer further comprises a copper-based seed layer on the adhesion/barrier layer, a steel layer on the seed layer, and a nickel layer. On the steel layer, the palladium layer is on the nickel layer. 164. The wafer sealing structure of claim 117, wherein the palladium layer has a thickness of between 1 micrometer and 20 micrometers. 165. The wafer package structure of claim 117, wherein the layer has a thickness between 3 microns and 5 microns. 166. The wafer sealing structure of claim 117, wherein the thickness of the wire bonding pad is between 1 micrometer and 20 micrometers. 167. The wafer package structure of claim 117, wherein the wire bond pad has a thickness between 3 microns and 5 microns. 168. The chip package structure of claim 117, wherein the wire bonding material comprises gold. The wafer package structure of claim 117, wherein the wire bonding wire has a diameter of between 20 micrometers and 50 micrometers. The wafer package structure of claim 117, wherein the material of the polymer material comprises an epoxy resin (ep〇xy). 171. The wafer package structure of claim 117, wherein the material of the polymer material comprises polyimine (PI). 172. The wafer package structure of claim 117, wherein the material of the polymer layer material comprises phenylcyclobutene (BCB). 173. The wafer package structure of claim 117, wherein the polymer material has a thickness between 250 microns and 1,000 microns. 174. The wafer package structure of claim 117, wherein the wire is electrically connected to the gold and the ball through a metal line of the substrate. ", mouth kick 175, a chip package structure, comprising: a substrate; a lead-free solder ball (joining the substrate; an adhesive material on the substrate; - the semiconductor wafer 'located in the Adhesive material' and the semiconductor wafer package 95 200814213 a semiconductor substrate; a wiring structure located above the semiconductor substrate; a protective layer positioned above the wiring structure, and an opening in the protective layer exposing the a copper pad of the wiring structure; and a wire bonding pad comprising an adhesive/barrier layer and a metal layer on the adhesion/barrier layer, wherein the adhesion/barrier layer is exposed at the opening a copper pad, and the metal layer comprises a palladium (pd) layer; a wire bonding wire bonding the palladium layer and the substrate; and a polymer material 'on the substrate' and covering the semiconductor wafer and the wire bonding wire. The wafer package structure of claim 175, wherein the substrate is a ball grid array (BGA) substrate. 177. The wafer package of claim 175 The substrate is a substrate containing a glass fiber and an epoxy resin. The wafer package structure of claim 175, wherein the substrate is a glass substrate. 179, as described in claim 175 The chip package structure, wherein the substrate is a dream substrate. The chip package structure of claim 175, wherein the substrate is a ceramic substrate. 181. The chip package structure according to claim 175 The substrate is an organic substrate. The wafer package structure of claim 175, wherein the substrate is a metal substrate. 96 200814213 183. The wafer sealing structure according to claim 175, The substrate is a metal substrate, and the material of the metal substrate comprises aluminum. The chip package structure of claim 175, wherein the substrate is a metal substrate, and the material of the metal substrate comprises copper. The wafer package structure of claim 175, wherein the substrate has a thickness of between 200 μm and 186. The wafer package structure of claim 175, wherein the substrate comprises a first surface and a second surface, and the adhesive material and the polymer material are located at the first The surface of the wafer package structure of claim 175, wherein the material of the error-free solder ball comprises a tin-silver alloy. 188. The chip package structure of claim 175, wherein the material of the lead-free solder ball comprises a tin-silver-copper alloy (tin_silverc), 189, the wafer according to claim 175 The package structure, wherein the diameter of the error-free solder ball is between 〇·25 cm and 1.2 cm. 190. The wafer package structure of claim 175, wherein the thickness of the adhesive material is between 1 micrometer and 50 micrometers. 191. The wafer package structure of claim 175, wherein the material of the adhesive material comprises a polymer material. The chip package structure of claim 175, wherein the material of the adhesive material comprises polyimide (pij. 193), the chip package structure as described in claim 175, wherein 97 The material of the adhesive material comprises an epoxy resin (epOXy resin). The wafer package structure of claim 175, wherein the semiconductor substrate comprises ruthenium. 195, as described in claim 175 The chip package structure is characterized in that the semiconductor substrate is located on the adhesive material. The wafer package structure of claim 175, further comprising at least one metal oxide semiconductor (MOS) device in or above the semiconductor substrate. 197. The wafer package structure of claim 175, wherein the circuit structure comprises a copper layer having a thickness between 〇2 μm and 2 μm. The chip package structure of claim 7 , wherein the circuit structure comprises electroplated copper. 199, as described in claim 175 The chip package structure further includes a plurality of dielectric layers between the semiconductor substrate and the protective layer, and a plurality of patterned metal layers of the line structure are located between the dielectric layers and through the game spaces. The plurality of metal plugs of the circuit structure in the electrical layer are connected to the patterned metal layers of the two adjacent layers of the V. 200. The chip package structure according to claim 119, wherein the dielectric layers are The electric constant value (k) is between 1. 5 and 3. The semiconductor package structure of claim 203, wherein the material of the dielectric layer comprises an oxonium compound. The chip package structure of claim 199, wherein the material of the dielectric layer comprises a nitridant compound. 203. The chip package structure according to claim 199, wherein 98 200814213 The material of the dielectric layer includes a oxynitride compound. The wafer sealing structure according to claim 199, wherein the material of the dielectric layer comprises a compound containing ruthenium, carbon, oxygen and hydrogen.The chip package structure of claim 1 , wherein the material of the dielectric layer comprises a Fluorinated smeate glass, and the chip package structure as described in claim 199 The thickness of the dielectric layer is between 33 μm and 2.5 μm. 207. The wafer package structure of claim 175, wherein the protective layer comprises an oxygen stone compound. The wafer package structure of claim 175, wherein the protective layer comprises a nitrogen compound. 209. The wafer package structure of claim 175, wherein the protective layer comprises a oxynitride compound. 210. The wafer sealing structure of claim 175, wherein the protective layer has a thickness ranging from 微米3 μm to L5 μm (referred to as 211, as described in claim 175). The chip package structure, wherein the thickness of the copper pad is between 微米 2 μm and 2 μm. The chip package structure of claim 175, wherein the material of the adhesion/barrier layer comprises titanium 213. The wafer package structure of claim 175, wherein the material of the adhesion/barrier layer comprises a titanium-tungsten alloy. 晶片, the wafer package structure as described in claim 175 of the patent application, The material of the adhesion/barrier layer includes titanium nitride. ^ 99 200814213 21: The wafer package structure as described in Patent Application No. 175, the material of the adhesive/barrier layer comprises chromium. ', 216, The wafer package structure of the acknowledgment range 175, wherein the material of the adhesion/barrier layer comprises a button. 816, #, pp. 175, the wafer package structure, the adhesion/barrier layer The material includes tantalum nitride. 218. The wafer package structure of claim 175, wherein the thickness of the adhesion/barrier layer is between 〇〇3 micrometers and 〇7 micrometers 219, as described in claim 175 of the wafer package. In the second embodiment, the metal layer further comprises a copper-based seed layer on the adhesion/barrier layer, a steel layer on the seed layer and a nickel layer on the copper layer, and the palladium layer. 220. The wafer package structure of claim 175, wherein the thickness of the layer is between 1 micrometer and 20 micrometers. 221, as claimed in claim 175 The chip package structure, wherein the thickness of the layer is between 3 micrometers and 5 micrometers. 222. The chip package structure of claim 175, wherein the thickness of the wire bonding pad is between 223. The wafer package structure of claim 175, wherein the wire bonding pad has a thickness of between 3 micrometers and 5 micrometers. 224. The wafer sealing structure of the item, wherein the 225. The wafer package structure of claim 175, wherein the wire bonding wire has a diameter of between 20 micrometers and 50 micrometers. 100 200814213 226, as claimed in claim 175 The chip package structure, wherein the material of the polymer material comprises an epoxy resin. The wafer package structure according to claim 175, wherein the material of the polymer material comprises polyimine. 228. The wafer package structure of claim 175, wherein the material of the polymer layer material comprises phenylcyclobutene (BCB). 229. The wafer package structure of claim 175, wherein the polymer material has a thickness between 250 microns and 1,000 microns. The chip package structure of claim 175, wherein the wire bonding wire electrically connects the lead-free solder ball through a metal line of the substrate. 231. A chip package structure comprising: a substrate; a lead-free solder ball bonded to the substrate; an adhesive material positioned on the substrate; and a semiconductor wafer positioned on the adhesive material And the semiconductor wafer comprises: a semiconductor substrate; a wiring structure located above the semiconductor substrate; a protective layer positioned above the wiring structure, and an opening in the protective layer exposing the wiring structure a copper pad; a metal protective cover on the copper pad exposed by the opening; and a wire bonding pad including an adhesive/barrier layer and a metal layer on the 101 200814213 adhesive/barrier layer Wherein the adhesion/barrier layer is on the metal protective cover, and the metal layer comprises a gold layer; a wire bonding wire bonding the gold layer and the substrate; and a polymer material on the substrate and covering The semiconductor wafer and the wire bonding wire. 232. The chip package structure of claim 231, wherein the substrate is a ball grid array (BGA) substrate. 233. The wafer package structure of claim 231, wherein the substrate is a substrate comprising glass fibers and an epoxy resin. 234. The wafer package structure of claim 231, wherein the substrate is a glass substrate. 235. The wafer package structure of claim 231, wherein the substrate is a broken substrate. 236. The wafer package structure of claim 231, wherein the substrate is a ceramic substrate. 237. The wafer package structure of claim 231, wherein the substrate is an organic substrate. 238. The wafer package structure of claim 231, wherein the substrate is a metal substrate. 239. The chip package structure of claim 231, wherein the substrate is a metal substrate, and the material of the metal substrate comprises aluminum. The chip package structure of claim 231, wherein the substrate is a metal substrate, and the material of the metal substrate comprises copper. 241. The wafer package structure of claim 231, wherein 102 200814213 has a thickness of between 200 microns and 2,000 microns. 242. The chip package structure of claim 231, wherein the substrate comprises a first surface and a second surface, and the adhesive material and the polymer material are located on the first surface, the error-free A solder ball is positioned on the first surface. 243. The chip package structure of claim 231, wherein the material of the error-free solder ball comprises a tin-silver alloy (tin_siiver any). 244. The chip package structure according to claim 231, wherein The material of the error-free solder ball includes tin-silver-copper alloy (1) n_silveKappa alloy). 245. The wafer package structure of claim 231, wherein the error-free solder ball has a diameter of between 2525 cm and 1.2 cm (mm). 246. The wafer package structure of claim 231, wherein the thickness of the adhesive material is between 1 micrometer and 50 micrometers. 247. The wafer package structure of claim 231, wherein the material of the adhesive material comprises a polymer material. 248. The chip package structure of claim 231, wherein the material of the adhesive material comprises polyimide (249), the chip package structure according to claim 231, wherein the adhesive is The material of the material includes an epoxy resin. The wafer package structure of claim 231, wherein the semiconductor substrate comprises a stone plaque. The structure in which the semiconductor substrate is located on the adhesive material. 103 200814213 252. The wafer package structure of claim 23, wherein the packaged metal oxide semiconductor (MOS) device is located in the semiconductor The chip package structure of the invention, wherein the circuit structure comprises a copper layer having a thickness between 〇 2 μm and 2 μm. 254, as claimed in the patent application. The chip package structure of item 231, wherein the line structure comprises electro-mineral copper. 255、 如申請專利範圍第231項所述之晶片封裝結構，更包 括複數介電層位在該半導體基底與該保護層 曰又間，且該線 路結構之複數圖案化金屬層位在該些介電層 % «〈間，並透過 位在該些介電層内的該線路結構之複數金屬插塞連接相鄰 兩層之該些圖案化金屬層。 256、 如申請專利範圍第255項所述之晶片封裝結構，其中 該些介電層的介電常數值（k)係介於1.5至3之間。 257、 如申請專利範圍第255項所述之晶片封裝結構，其中 該些71電層的材質包括氧碎化合物。 258、 如申請專利範圍第255項所述之晶片封裝結構，其中 該些介電層的材質包括氮矽化合物。 Μ 259、 如申請專利範圍第255項所述之晶片封裝結構，其中 該些介電層的材質包括氮氧矽化合物。 260、 如申請專利範圍第255項所述之晶片封裝結構，其中 該些介電層的材質包括含矽、碳、氧與氫之化合物。 261、 如申請專利範圍第255項所述之晶片封裝結構，其中 該些介電層的材質包括氣矽玻璃（Flu〇rinated SUk咖 104 200814213 Glass) ° 262、 如申請專利範圍第255項所述之晶片封裝結構，其中 該些介電層的厚度係介於〇·3微米至2.5微米之間。 263、 如申請專利範圍第231項所述之晶片封裝結構，其中 該保濩層包括氧碎化合物。 264、 如申請專利範圍第231項所述之晶片封裝結構，其中 該保護層包括氮石夕化合物。 265、 如申請專利範圍第231項所述之晶片封裳結構，其中 該保護層包括氮氧矽化合物。 266、 如申請專利範圍第231項所述之晶片封裝結構，其中 該保護層的厚度係介於〇·3微米至15微米（“叫之間。 267、 如申請專利範圍第231項所述之晶片封裝結構，其中 該金屬保護蓋包括厚度介於0.4微米至2微米之間的一人 鋁金屬層位在該開口所暴露出之該銅墊上，且該黏著/阻障 層位在該含紹金屬層上。 268、 如申請專利範圍第267項所述之晶片封裝結構，其中 該含銘金屬層的材質包括銅。 269、 如申請專利範圍第267項所述之晶片封袈結構，其中 該含鋁金屬層的材質包括銅與石夕。 27〇、如申請專利範圍第231項所述之晶片封裝結構，其中 該金屬保護蓋包括厚度介於〇 〇1微米至〇 7微米之間的一 阻障層（barrier layer)位在該開口所暴露出之該銅塾上，以 及=度介於0.4微米至2微米之間的—含銘金屬層位在該 阻障層上，且該黏著/阻障層位在該含鋁金屬層上。 105 200814213 271、 如申請專利範圍第27〇項所述之晶片封裝纟士構，其 該阻障層的材質包括鈦。 272、 如申請專利範圍第27〇項所述之晶片封裝奸構，其 該阻障層的材質包括鈦鎢合金。 、 273、 如申請專利範圍第27〇項所述之晶片封裝結構，其中 該阻障層的材質包括氮化鈦。 274、 如申請專利範圍第，項所述之晶片料結構，其中 該阻障層的材質包括鉻。 275、 如申請專利範圍第27〇項所述之晶片封裝結構，其中 該含叙金屬層的材質包括銅。 276、 如申請專利範圍第27〇項所述之晶片封裝結構，其中 該含銘金屬層的材質包括銅與石夕。 277'如申請專利範圍第231項所述之晶片封裝結構，其中 該金屬保護蓋包括厚度介於0·01微米至〇·7微米之門的一 含鈕金屬層位在該開口所暴露出之該銅墊 以及厚度介 於〇.4微米至2微米之_—含綠屬層位在該含纽金屬 層上，且該黏著/阻障層位在該含鋁金屬層上。 278、 如申請專利範圍第277項所述之晶片封裝結構，其中 該含鈕金屬層為一鈕層。 ^ 279、 如申請專利範圍第277項所述之晶片封裴結構，其中 該含组金屬層為一氮化鈕層。 280、 如申請專利範圍第277項所述之晶片封裝結構，其中 該含銘金屬層的材質包括銅。 八 281、 如申請專利範圍第277項所述之晶片封裝結構，其中 106 200814213 該含銘金屬層的材質包括銅與石夕。 282、 如申請專利範圍第231項所述之晶片封裝結構，其中 該銅塾的厚度係介於〇·2微米至2微米之間。 283、 如申請專利範圍第231項所述之晶片封裝結構，其中 該黏著/阻障層的材質包括鈦。 一 284 '如申請專利範圍第231項所述之晶片封裳結構，其中 該黏著/阻障層的材質包括鈦鶴合金。 285、 —如申請專利範圍第231項所述之晶片封裳結構，其中 該黏著/阻障層的材質包括氮化鈦。 286、 如申請專利範圍第231項所述之晶片封裳結構，复中 該黏著/阻障層的材質包括鉻。 八 287、 如申請專利範圍第231項所述之晶片封裝結構，兑中 該黏著/阻障層的材質包括鈕。 ^ 288、 #如申請專利範圍第叫項所述之晶片封裝結構，其中 該黏著/阻障層的材質包括氮化鈕。 289、 如申請專利範圍第231項所述之晶片封裝結構其中 該黏著/阻障層的厚度係介於〇.〇3微米至0.7微米之間、。 謂、如申請專利範圍第231項所述之晶片封裝結構，盆中 該金屬層更包括材質為金的—種子層位在該黏著/阻障層 上’且該金層位在談種子層上。 291、如申請專利範圍第231項所述之晶片封裝結構盆中 該金屬層更包括材質為銅的—種子層位在該黏著/阻障層 上、一銅層位在該種子層上以及一鎳層位在該銅層上，I 該金層位在該鎳層上。 107 200814213 ⑽、如申請專利範圍第231項所述之晶片封裝結構， 該金層的厚度係介於1微米至20微米之間。 293、 如申請專利範圍第231項所述之晶片封裝結構，1 該金層的厚度係介於3微米至5微米之間。 &quot;中 294、 如申請專利範圍第231項所述之晶片封裝結構，並 該打線接墊的厚度係介於i微米至2〇微米之間 ^中 295、 如申請專利範圍第231項所述之晶片封裝鈇構，1 該打線接墊的厚度係介於3微米至5微米之間。 八255. The chip package structure of claim 231, further comprising a plurality of dielectric layers between the semiconductor substrate and the protective layer, and wherein the plurality of patterned metal layers of the line structure are The electrical layer %« is connected to the adjacent two layers of the patterned metal layers through a plurality of metal plugs of the wiring structure located in the dielectric layers. 256. The chip package structure of claim 255, wherein the dielectric layers have a dielectric constant value (k) between 1.5 and 3. 257. The wafer package structure of claim 255, wherein the material of the 71 electrical layer comprises an oxycide compound. 258. The chip package structure of claim 255, wherein the material of the dielectric layer comprises a nitrogen cerium compound. The chip package structure of claim 255, wherein the material of the dielectric layer comprises a oxynitride compound. 260. The chip package structure of claim 255, wherein the material of the dielectric layer comprises a compound containing bismuth, carbon, oxygen and hydrogen. 261. The chip package structure of claim 255, wherein the material of the dielectric layer comprises a gas-filled glass (Flu〇rinated SUK coffee 104 200814213 Glass) ° 262, as described in claim 255 The chip package structure, wherein the thickness of the dielectric layers is between 3·3 μm and 2.5 μm. 263. The wafer package structure of claim 231, wherein the protective layer comprises an oxycide compound. 264. The wafer package structure of claim 231, wherein the protective layer comprises a Nitrogen compound. 265. The wafer sealing structure of claim 231, wherein the protective layer comprises a oxynitride compound. 266. The wafer package structure of claim 231, wherein the protective layer has a thickness of between 3 micrometers and 15 micrometers ("between. 267, as described in claim 231" a chip package structure, wherein the metal protection cover comprises a layer of one-person aluminum metal having a thickness between 0.4 micrometers and 2 micrometers on the copper pad exposed by the opening, and the adhesion/barrier layer is located on the metal layer The wafer package structure of claim 267, wherein the material containing the metal layer comprises copper. 269. The wafer package structure according to claim 267, wherein the The material of the aluminum metal layer comprises a copper and a stone slab. The wafer package structure of claim 231, wherein the metal protection cover comprises a resistance between 〇〇1 μm and 〇7 μm. a barrier layer is located on the copper plaque exposed by the opening, and a degree of between 0.4 micrometers and 2 micrometers is included on the barrier layer, and the adhesion/resistance is Barrier layer in the aluminum-containing metal The substrate of the wafer package of the invention of claim 27, wherein the material of the barrier layer comprises titanium. 272. The wafer package described in claim 27 The material of the barrier layer comprises a titanium-tungsten alloy. The chip package structure according to claim 27, wherein the material of the barrier layer comprises titanium nitride. 274. The wafer material structure of the present invention, wherein the material of the barrier layer comprises chromium. 275. The wafer package structure of claim 27, wherein the metal layer comprises copper. The chip package structure of claim 27, wherein the material containing the metal layer comprises a copper and a stone etch. The chip package structure of claim 231, wherein the metal protection cover The copper pad including the button metal layer having a thickness ranging from 0. 01 micrometers to 〇 7 micrometers is exposed at the opening, and the green layer is 厚度. 4 micrometers to 2 micrometers thick. In this The enamel layer is a chip package structure as described in claim 277, wherein the button metal layer is a button layer. ^ 279 The wafer package structure of claim 277, wherein the metal layer is a nitride button layer. 280. The chip package structure of claim 277, wherein the metal is included The material of the layer includes copper. 281. The wafer package structure of claim 277, wherein 106 200814213 comprises a metal layer of copper and stone. 282. The wafer package structure of claim 231, wherein the copper beryllium has a thickness of between 2 micrometers and 2 micrometers. 283. The chip package structure of claim 231, wherein the material of the adhesion/barrier layer comprises titanium. A wafer sealing structure as described in claim 231, wherein the material of the adhesive/barrier layer comprises a titanium alloy. 285. The wafer sealing structure of claim 231, wherein the material of the adhesion/barrier layer comprises titanium nitride. 286. The wafer sealing structure according to claim 231, wherein the material of the adhesion/barrier layer comprises chromium. 287. The wafer package structure according to claim 231, wherein the material of the adhesion/barrier layer comprises a button. 288. The wafer package structure of claim 1, wherein the material of the adhesion/barrier layer comprises a nitride button. 289. The chip package structure of claim 231, wherein the thickness of the adhesion/barrier layer is between 微米3 至 and 0.7 μm. The wafer package structure of claim 231, wherein the metal layer further comprises a gold-based seed layer on the adhesion/barrier layer and the gold layer is on the seed layer. . 291. The metal package layer of the wafer package structure according to claim 231, further comprising a copper-based seed layer on the adhesion/barrier layer, a copper layer on the seed layer, and a The nickel layer is on the copper layer, and the gold layer is on the nickel layer. The wafer package structure of claim 231, wherein the gold layer has a thickness of between 1 micrometer and 20 micrometers. 293. The wafer package structure of claim 231, wherein the gold layer has a thickness of between 3 micrometers and 5 micrometers. &quot; 294, the wafer package structure of claim 231, and the thickness of the wire bonding pad is between i micrometers and 2 micrometers, 295, as described in claim 231 The chip package structure, 1 the thickness of the wire bonding pad is between 3 microns and 5 microns. Eight 296、 如申請專利範圍第231項所述之晶片封裝結構，苴 該打線導線的材質包括金。 其中 297、如申請專利範圍第231項所述之晶片封裴結構，其中 該打線導線的直徑介於20微米至50微米之間。 ⑽、如申請專利範圍第231項所述之晶片封裝結構，其中 該t合物材料的材質包括環氧樹脂（epoxy)。 299、如申請專利範圍第231項所述之晶片封裝結構，其中 該聚合物材料的材質包括聚醯亞胺（PI)。 300、 如申請專利範圍第231項所述之晶片封裝結構，其中 該聚合物層材料的材質包括苯基環丁烯(Bcb)。 301、 如申請專利範圍第231項所述之晶片封裝結構，其中 該聚合物材料的厚度係介於250微米至1，〇〇〇微米之門 302、 如申請專利範圍第231項所述之晶片封裝結構，^中 該打線導線係透過該基板的一金屬線路電性連接該無#錫 球0 303、一種晶片封裝結構，包括·· 108 200814213 一基板； 一無錯錫球（lead-free solder ball)，接合該基板； 一黏者材料’位在該基板上， 一半導體晶片’位在該黏者材料上’且該半導體晶片包 括： 一半導體基底； 一線路結構，位在該半導體基底上方； 一保護層，位在該線路結構上方，且位在該保護層 内之一開口暴露出該線路結構之一銅墊； 一金屬保護蓋，位在該開口所暴露出之該銅墊上； 以及 一打線接墊，包括一黏著/阻障層與一金屬層位在該 黏著/阻障層上，其中該黏著/阻障層位在該金屬保護 蓋上，且該金屬層包括一把層； 一打線導線，接合該鈀層與該基板；以及 一聚合物材料，位在該基板上，並覆蓋該半導體晶片與 該打線導線。 304、 如申請專利範圍第303項所述之晶片封裝結構，其中 該基板為球型柵狀陣列（BGA)基板。 305、 如申請專利範圍第303項所述之晶片封裝結構，其中 該基板為含有玻璃纖維與環氧樹脂的基板。 306、 如申請專利範圍第303項所述之晶片封裝結構，其中 該基板為玻璃基板。 307、 如申請專利範圍第303項所述之晶片封裝結構，其中 109 200814213 該基板為砍基板。 308、 如申請專利範圍第303項所述之晶片封裝結構，其中 該基板為陶兗基板。 309、 如申請專利範圍第303項所述之晶片封裝結構，其中 該基板為有機基板。 310、 如申請專利範圍第303項所述之晶片封裝結構，其中 該基板為金屬基板。 311、 如申請專利範圍第303項所述之晶片封裝結構，其中 C 該基板為金屬基板，且該金屬基板的材質包括铭。 312、 如申請專利範圍第303項所述之晶片封裝結構，其中 該基板為金屬基板，且該金屬基板的材質包括銅。 313、 如申請專利範圍第303項所述之晶片封裝結構，其中 該基板的厚度係介於200微米至2,000微米之間。 314、 如申請專利範圍第303項所述之晶片封裝結構，其中 該基板包括一第一表面與一第二表面，且該黏著材料與該 聚合物材料位在該第一表面上，該無鉛錫球位在該第二表 1' 面上。 315、 如申請專利範圍第303項所述之晶片封裝結構，其中 該無錯錫球的材質包括錫銀合金（tin-silver alloy)。 316、 如申請專利範圍第303項所述之晶片封裝結構，其中 該無錯錫球的材質包括錫銀銅合金（tin-silver-copper alloy) 〇 317、 如申請專利範圍第303項所述之晶片封裝結構，其中 該無鉛錫球的直徑介於0.25釐米至1.2釐米（mm)之間。 110 200814213 318、 如申請專利範圍第3〇3項所述之晶片封農結構，其中 該黏著材料的厚度係介於1微米至50微米之間。 319、 如申請專利範圍第3〇3項所述之晶片封襄結構，其中 該黏著材料的材質包括聚合物材料。 320、 如申請專利範圍第3〇3項所述之晶片封裝結構，其中 該黏著材料的材質包括聚醯亞胺（polyimide，。 321、 如申請專利範圍第3〇3項所述之晶片封裝結構，其中 該黏著材料的材質包括環氧樹脂（epoxy resin)。296. The chip package structure of claim 231, wherein the wire material comprises gold. The wafer sealing structure of claim 231, wherein the wire bonding wire has a diameter of between 20 micrometers and 50 micrometers. (10) The chip package structure of claim 231, wherein the material of the t-material comprises an epoxy. 299. The wafer package structure of claim 231, wherein the material of the polymer material comprises polyimine (PI). The wafer package structure of claim 231, wherein the material of the polymer layer material comprises phenylcyclobutene (Bcb). 301. The wafer package structure of claim 231, wherein the thickness of the polymer material is between 250 micrometers and 1, and the gate of the micro-gate 302 is as described in claim 231. In the package structure, the wire is electrically connected to the non-tin ball 0 303 through a metal line of the substrate, a chip package structure, including a substrate of 200814213; a lead-free solder Ball), bonding the substrate; an adhesive material 'on the substrate, a semiconductor wafer 'on the adhesive material' and the semiconductor wafer comprises: a semiconductor substrate; a wiring structure located above the semiconductor substrate a protective layer positioned above the wiring structure, and an opening in the protective layer exposing a copper pad of the wiring structure; a metal protective cover located on the copper pad exposed by the opening; a wire bonding pad comprising an adhesive/barrier layer and a metal layer on the adhesion/barrier layer, wherein the adhesion/barrier layer is on the metal protection cover, and the metal layer is wrapped a layer of wire is bonded to the substrate, and a palladium layer is bonded to the substrate; and a polymer material is disposed on the substrate and covers the semiconductor wafer and the wire. The wafer package structure of claim 303, wherein the substrate is a ball grid array (BGA) substrate. 305. The wafer package structure of claim 303, wherein the substrate is a substrate comprising glass fibers and an epoxy resin. 306. The wafer package structure of claim 303, wherein the substrate is a glass substrate. 307. The chip package structure of claim 303, wherein the substrate is a chopped substrate. 308. The wafer package structure of claim 303, wherein the substrate is a ceramic substrate. 309. The chip package structure of claim 303, wherein the substrate is an organic substrate. The wafer package structure of claim 303, wherein the substrate is a metal substrate. 311. The chip package structure of claim 303, wherein the substrate is a metal substrate, and the material of the metal substrate comprises a metal. 312. The chip package structure of claim 303, wherein the substrate is a metal substrate, and the material of the metal substrate comprises copper. 313. The wafer package structure of claim 303, wherein the substrate has a thickness between 200 microns and 2,000 microns. The chip package structure of claim 303, wherein the substrate comprises a first surface and a second surface, and the adhesive material and the polymer material are on the first surface, the lead-free tin The ball position is on the 1' side of the second table. 315. The chip package structure of claim 303, wherein the material of the error-free solder ball comprises a tin-silver alloy. 316. The chip package structure of claim 303, wherein the material of the error-free solder ball comprises a tin-silver-copper alloy 〇317, as described in claim 303. A chip package structure, wherein the lead-free solder ball has a diameter of between 0.25 cm and 1.2 cm. The wafer sealing structure as described in claim 3, wherein the thickness of the adhesive material is between 1 micrometer and 50 micrometers. 319. The wafer package structure of claim 3, wherein the material of the adhesive material comprises a polymer material. The chip package structure of claim 3, wherein the material of the adhesive material comprises polyimide (321), the chip package structure as described in claim 3, item 3. The material of the adhesive material comprises an epoxy resin. 322、 如申請專利範圍第303項所述之晶片封裝結構，其中 該半導體基底包括碎。 323、如申請專利範圍第3〇3項所述之晶片封裝結構，其中 該半導體基底位在該黏著材料上。 M4、如申請專利範圍第3〇3項所述之晶片封裝結構，更包 括至少一金氧半導體（M〇s)元件位在該半導體基底内2 325、 如申請專利範圍第3〇3項所述之晶片封裝結構，其中 該線路結構包括厚度介於〇·2微米至2微米 、 ·、4間的一銅層。 326、 如申請專利範圍第303項所述之晶片封裝結構，其中 該線路結構包括電鍍銅。 327、 如申請專利範圍第3〇3項所述之晶片封裝結構，更包 括複數介電層位在該半導體基底與該保護層 ^ 曰之間，且該線 路結構之複數圖案化金屬層位在該些介電層 曰又間，亚透過 位在該些介電層内的該線路結構之複數金屬插塞連接相鄰 兩層之該些圖案化金屬層。 111 200814213 328、 如申請專利範圍第327項所述之晶片封裝結構，其中 該些介電層的介電常數值（k)係介於1.5至3之間。 329、 如申請專利範圍第327項所述之晶片封裝結構，其中 該些介電層的材質包括氧矽化合物。 330、 如申請專利範圍第327項所述之晶片封裝結構，其中 該些介電層的材質包括氮矽化合物。 331、 如申請專利範圍第327項所述之晶片封裝結構，其中 該些介電層的材質包括氮氧矽化合物。 332、 如申請專利範圍第327項所述之晶片封裝結構，其中 該些介電層的材質包括含矽、碳、氧與氳之化合物。 333、 如申請專利範圍第327項所述之晶片封裝結構，其中 該些介電層的材質包括氟石夕玻璃（Fluorinated Silicate Glass) 〇 334、 如申請專利範圍第327項所述之晶片封裝結構，其中 該些介電層的厚度係介於0.3微米至2.5微米之間。 335、 如申請專利範圍第303項所述之晶片封裝結構，其中 I 該保護層包括氧矽化合物。 336、 如申請專利範圍第303項所述之晶片封裝結構，其中 該保護層包括氮石夕化合物。 337、 如申請專利範圍第303項所述之晶片封裝結構，其中 該保護層包括氮氧石夕化合物。 338、 如申請專利範圍第303項所述之晶片封裝結構，其中 該保護層的厚度係介於0.3微米至1.5微米（// m)之間。 339、 如申請專利範圍第303項所述之晶片封裝結構，其中 112 200814213 2微未之間的 &gt;一含 上，且該黏著/阻障 該金屬保護蓋包括厚度介於0·4微米至2 鋁金屬層位在該開口所暴露出之該銅墊上 、如申請專利範圍第339項所述之晶片封震結構 層位在該含鋁金屬層上。 340、 如由諸直丨愁落！始 該含铭金屬層的材質包括銅。 %、如申請專利範圍第339項所述之晶片封裝結構，其中 該含鋁金屬層的材質包括銅與矽。322. The wafer package structure of claim 303, wherein the semiconductor substrate comprises a chip. 323. The wafer package structure of claim 3, wherein the semiconductor substrate is on the adhesive material. M4. The chip package structure according to claim 3, wherein the at least one metal oxide semiconductor (M〇s) device is located in the semiconductor substrate 2 325, as in the third and third items of the patent application. The chip package structure, wherein the circuit structure comprises a copper layer having a thickness of between 2 μm and 2 μm, and 4 layers. 326. The wafer package structure of claim 303, wherein the wiring structure comprises electroplated copper. 327. The chip package structure of claim 3, further comprising a plurality of dielectric layers between the semiconductor substrate and the protective layer, and the plurality of patterned metal layers of the line structure are The plurality of dielectric plugs are connected to the patterned metal layers of the adjacent two layers through a plurality of metal plugs of the line structure located in the dielectric layers. The wafer package structure of claim 327, wherein the dielectric layers have a dielectric constant value (k) between 1.5 and 3. 329. The chip package structure of claim 327, wherein the material of the dielectric layer comprises an oxonium compound. The wafer package structure of claim 327, wherein the material of the dielectric layer comprises a nitrogen bismuth compound. The wafer package structure of claim 327, wherein the material of the dielectric layer comprises a oxynitride compound. 332. The chip package structure of claim 327, wherein the material of the dielectric layer comprises a compound containing ruthenium, carbon, oxygen and ruthenium. 333. The chip package structure of claim 327, wherein the material of the dielectric layer comprises a Fluorinated Silicate Glass 334, and the chip package structure according to claim 327 The thickness of the dielectric layers is between 0.3 microns and 2.5 microns. 335. The wafer package structure of claim 303, wherein the protective layer comprises an oxonium compound. 336. The wafer package structure of claim 303, wherein the protective layer comprises a Nitrogen compound. 337. The wafer package structure of claim 303, wherein the protective layer comprises a oxynitride compound. 338. The wafer package structure of claim 303, wherein the protective layer has a thickness between 0.3 microns and 1.5 microns (//m). 339. The chip package structure according to claim 303, wherein: 112 200814213 2 micro-between, and the adhesion/barrier metal protective cover comprises a thickness of 0.4 micron to 2 The aluminum metal layer is on the copper pad exposed by the opening, and the wafer sealing structure layer as described in claim 339 is on the aluminum-containing metal layer. 340, as if by the straight fall! The material containing the metal layer of the inscription includes copper. The wafer package structure of claim 339, wherein the material of the aluminum-containing metal layer comprises copper and tantalum. 及厚没介於0.4微米至2微米之間的一 口所暴露出之該鋼墊上，以 之間的-含鋁金屬層位在該 阻障層上，且該黏著/阻障層位在該含鋁金屬層上。 ^ 343、如申請專利範圍第342項所述之晶片封^結構，其中 該阻障層的材質包括鈦。 3料、立如申請專利範圍第342項所述之晶片封裝結構，其中 該阻障層的材質包括鈦鎢合金。 345、 /申請專利範圍第342項所述之晶片封裝結構，其中 該阻p早層的材質包括氮化鈥。 346、 如巾請專利範圍第342項所述之晶片封裝結構， 該阻障層的材質包括鉻。 、 347、 如申請專利範圍第342項所述之晶片封裝纤構复 該含I呂金屬層的材質包括銅。 八中 348、 如申請專利範圍第342項所述之晶片封裝奸構兑 該含銘金屬層的材質包括銅與石夕。 一中 113 200814213 349、如申請專利範圍第3〇3項所述之晶片封裝結構，其中 該金屬保護蓋包括厚度介於〇·()!微米至U微米之間的一 含鈕金屬層位在該開口所暴露出之該銅墊上，以及厚度介 於〇·4微米至2微米之間的一含鋁金屬層位在該含紐金屬 層上’且該黏著/阻障層位在該含鋁金屬層上。 35()、如申請專利範圍第349項所述之晶片封裝結構，其中 該含鈕金屬層為一鈕層。 八 351、如申請專利範圍第349項所述之晶片封裝結構，其中 該含组金屬層為一氮化鈕層。 W、如申請專利範圍第349項所述之晶片封裝結構，其中 該含铭金屬層的材質包括銅。 A 奶、如申請專利範圍第349項所述之晶片封裝結構，其中 該含鋁金屬層的材質包括銅與矽。 八 354、 如中請專利範圍第3G3項所述之晶片封裝結構，其中 該銅墊的厚度係介於0.2微米至2微米之間。 355、 如申請專利範圍第3〇3項所述之晶片封裝結構，复中 該黏著/阻障層的材質包括鈦。 ^ 356、 #如申請專利範圍第3〇3項所述之晶片封裝結構其中 該黏著/阻障層的材質包括鈦鎢合金。 、 357、 如申請專利範圍第3〇3項所述之晶片封裝結構，复 該黏著/阻障層的材質包括氮化鈦。 h 358、 如申請專利範圍第3〇3項所述之晶片封裝社構，复 該黏著/阻障層的材質包括鉻。 ’、中 359、 如申請專利範圍第3〇3項所述之晶片封裝鈇構，其中 114 200814213 該黏著/阻障層的材質包括钽。 360、从如申請專利範圍第则項所述之晶片封裝結構，其中 該黏著/阻障層的材質包括氮化钽。 361 ^如申請專利範圍第3〇3項所述之晶片封裳結構，其中 該黏著/阻障層的厚度係介於〇 〇3微米至〇 7微米之門 362、 如申請專利範圍第303項所述之晶片封裝結構，其中 該金屬層更包括材質為銅的—種子層位在該黏著/阻障層 上、一銅層位在該種子層上以及一鎳層位在該鋼層上，I 該鈀層位在該鎳層上。 363、 如申請專利範圍第3〇3項所述之晶片封裝結構，其中 該把層的厚度係介於1微米至20微米之間。 364、 如申請專利範圍第3〇3項所述之晶片封装結構，其中 該把層的厚度係介於3微米至5微米之間。 365、 如申請專利範圍第3〇3項所述之晶片封裝結構，其中 該打線接墊的厚度係介於1微米至20微米之間。 366、 如申請專利範圍第3〇3項所述之晶片封裳結構，其中 該打線接墊的厚度係介於3微米至5微米之間。 367、 如申請專利範圍第3〇3項所述之晶片封裝結構，其中 該打線導線的材質包括金。 368、 如申請專利範圍第3〇3項所述之晶片封裝結構，其中 該打線導線的直徑介於20微米至50微米之間。 369、 如申請專利範圍第303項所述之晶片封裝結構，其中 該聚合物材料的材質包括環氧樹脂（epoxy)。 370、 如申請專利範圍第303項所述之晶片封裝結構，其中 115 200814213 該聚合物材料的材質包括聚醯亞胺（pi)。 371、 如申請專利範圍第303項所述之晶片封裝結構，其中 該聚合物層材料的材質包括苯基環丁烯（BCB)。 372、 如申請專利範圍第303項所述之晶片封裝結構，其中 該聚合物材料的厚度係介於250微米至1，000微米之間。 373、 如申請專利範圍第303項所述之晶片封裝結構，其中 該打線導線係透過該基板的一金屬線路電性連接該無鉛錫 球。 374、 一種晶片封裝結構，包括： 一基板， 一無鉛錫球（lead-free solder ball)，接合該基板； 一黏著材料，位在該基板上； 一半導體晶片’位在該黏者材料上’且該半導體晶片包 括： 一半導體基底； 一線路結構’位在該半導體基底上方； 一保護層，位在該線路結構上方，且位在該保護層 内之一開口暴露出該線路結構之一接墊；以及 一金屬線路，位在該保護層上方，並透過該開口連 接該接墊，且該金屬線路包括一金層； 一打線導線，接合該金層與該基板；以及 一聚合物材料’位在該基板上’並覆盡該半導體晶片與 該打線導線。 375、 如申請專利範圍第374項所述之晶片封裝結構，其中 116 200814213 該基板為球型柵狀陣列（BGA)基板。 376、 如申請專利範圍第374項所述之晶片封裝結構，其中 該基板為含有玻璃纖維與環氧樹脂的基板。 377、 如申請專利範圍第374項所述之晶片封裝結構，其中 該基板為玻璃基板。 378、 如申請專利範圍第374項所述之晶片封裝結構，其中 該基板為矽基板。 379、 如申請專利範圍第374項所述之晶片封裝結構，其中 該基板為陶甍基板。 380、 如申請專利範圍第374項所述之晶片封裝結構，其中 該基板為有機基板。 381、 如申請專利範圍第374項所述之晶片封裝結構，其中 該基板為金屬基板。 382、 如申請專利範圍第374項所述之晶片封裝結構，其中 該基板為金屬基板，且該金屬基板的材質包括鋁。 383、 如申請專利範圍第374項所述之晶片封裝結構，其中 該基板為金屬基板，且該金屬基板的材質包括銅。 384、 如申請專利範圍第374項所述之晶片封裝結構，其中 該基板的厚度係介於200微米至2,000微米之間。 385、 如申請專利範圍第374項所述之晶片封裝結構，其中 該基板包括一第一表面與一第二表面，且該黏著材料與該 聚合物材料位在該第一表面上，該無鉛錫球位在該第二表 面上。 386、 如申請專利範圍第374項所述之晶片封裝結構，其中 117 200814213 該無錯錫球的材質包括錫銀合金（tin-silver alloy)。 387、 如申請專利範圍第374項所述之晶片封裝結構，其中 該無錯錫球的材質包括錫銀銅合金（tin-silver-copper alloy) ° 388、 如申請專利範圍第374項所述之晶片封裝結構，其中 該無鉛錫球的直徑介於0.25釐米至1.2釐米（mm)之間。 389、 如申請專利範圍第374項所述之晶片封裝結構，其中 該黏著材料的厚度係介於1微米至50微米之間。 390、 如申請專利範圍第374項所述之晶片封裝結構，其中 該黏著材料的材質包括聚合物材料。 391、 如申請專利範圍第374項所述之晶片封裝結構，其中 該黏著材料的材質包括聚醯亞胺（polyimide，PI)。 392、 如申請專利範圍第374項所述之晶片封裝結構，其中 該黏著材料的材質包括環氧樹脂（epoxy resin)。 393、 如申請專利範圍第374項所述之晶片封裝結構，其中 該半導體基底包括碎。 394、 如申請專利範圍第374項所述之晶片封裝結構，其中 該半導體基底位在該黏著材料上。 395、 如申請專利範圍第374項所述之晶片封裝結構，更包 括至少一金氧半導體（MOS)元件位在該半導體基底内或上 方。 396、 如申請專利範圍第374項所述之晶片封裝結構，其中 該線路結構包括厚度介於0.2微米至2微米之間的一銅層。 397、 如申請專利範圍第374項所述之晶片封裝結構，其中 118 200814213 該線路結構包括電鍍銅。 398、 如申請專利範圍第374項所述之晶片封裝結構，其中 該線路結構包括厚度介於0.2微米至2微米之間的一含鋁 金屬層。 399、 如申請專利範圍第374項所述之晶片封裝結構，更包 括複數介電層位在該半導體基底與該保護層之間，且該線 路結構之複數圖案化金屬層位在該些介電層之間，並透過 位在該些介電層内的該線路結構之複數金屬插塞連接相鄰 ( 兩層之該些圖案化金屬層。 400、 如申請專利範圍第399項所述之晶片封裝結構，其中 該些介電層的介電常數值（k)係介於1.5至3之間。 401、 如申請專利範圍第399項所述之晶片封裝結構，其中 該些介電層的材質包括氧矽化合物。 402、 如申請專利範圍第399項所述之晶片封裝結構，其中 該些介電層的材質包括氮矽化合物。 403、 如申請專利範圍第399項所述之晶片封裝結構，其中 該些介電層的材質包括氮氧矽化合物。 404、 如申請專利範圍第399項所述之晶片封裝結構，其中 該些介電層的材質包括含矽、碳、氧與氫之化合物。 405、 如申請專利範圍第399項所述之晶片封裝結構，其中 該些介電層的材質包括敗石夕玻璃（Fluorinated Silicate Glass) 〇 406、 如申請專利範圍第399項所述之晶片封裝結構，其中 該些介電層的厚度係介於0.3微米至2.5微米之間。 119 200814213 =護:::=Γ項所述…_結構，其中 封裝結構，其中 409、如申請專利範圍第374項所述之晶片 該保護層包括氮氧矽化合物。 楊、；如申請專利範圍第374項所述之晶片封裝結構，其中 該保濩層的厚度係介於〇·3微米至15微米（“瓜)之門 Mi、如申請專利範圍第374項戶斤述之晶片封裝m 該接塾包括厚度介於G·2微米至2微米之間的n且 該金屬線路連接該銅層。 曰 王丁褒結構，盆中 該接塾包括厚度介於〇.2微米至2微米之間的—銘ς金 層，且該金屬線路連接該銘合金層。 、 川、如申請專利範圍第374項所述之晶片封裝結構，更包 括一金屬保護蓋位在該開口所暴露出之該接墊上，且該 屬線路連接該金屬保護蓋。 ““ 封裝結構，其中 414、如申請專利範圍第4Π項所述之晶片 該接塾為銅塾。 如申請專利範圍第413項所述之晶片封裝結構，盆中 該金屬保護蓋包括厚度介於（).4微米至2微米之間的—含 紹金屬層位在該開口所暴露出之該接墊上，且部分 線路位在該含鋁金屬層上。 μ、屬 416、如申請專利範圍第415項所述之晶片封裝結構，其中 120 200814213 該含紹金屬層的材質包括銅。 417、 如申請專利範圍第415項所述之晶片 該含铭金屬層的材質包㈣財。 “構八中 418、 如申請專利範圍第413項所述之晶片封裝結構，其中 該金屬保護蓋包括厚度介於〇 〇1微米至〇·7微米之間的一 阻障層（barrier layerMi在該開口所暴露出之And the steel pad exposed by a port having a thickness of between 0.4 micrometers and 2 micrometers, with an aluminum-containing metal layer interposed on the barrier layer, and the adhesion/barrier layer is in the On the aluminum metal layer. 343. The wafer sealing structure of claim 342, wherein the material of the barrier layer comprises titanium. A wafer package structure as described in claim 342, wherein the material of the barrier layer comprises a titanium-tungsten alloy. 345. The wafer package structure of claim 342, wherein the material of the early layer of the resistive layer comprises tantalum nitride. 346. The wafer package structure according to claim 342, wherein the material of the barrier layer comprises chromium. 347. The wafer package fiber structure according to claim 342, wherein the material of the Ilu metal layer comprises copper.八中 348. The wafer encapsulation described in Section 342 of the patent application includes the material of the metal layer including the copper and the stone eve. The wafer package structure of claim 3, wherein the metal protection cover comprises a button metal layer having a thickness between 〇·()!micron to U micron. An aluminum-containing metal layer on the copper pad exposed by the opening and having a thickness between 4 μm and 2 μm on the gold-containing metal layer and the adhesion/barrier layer is in the aluminum-containing layer On the metal layer. The chip package structure of claim 349, wherein the button metal layer is a button layer. The chip package structure of claim 349, wherein the group metal layer is a nitride button layer. The wafer package structure of claim 349, wherein the material containing the metal layer comprises copper. A wafer package structure according to claim 349, wherein the material of the aluminum-containing metal layer comprises copper and tantalum. The chip package structure of claim 3, wherein the thickness of the copper pad is between 0.2 micrometers and 2 micrometers. 355. The chip package structure as claimed in claim 3, wherein the material of the adhesion/barrier layer comprises titanium. 356. The wafer package structure of claim 3, wherein the material of the adhesion/barrier layer comprises a titanium-tungsten alloy. 357. The chip package structure according to claim 3, wherein the material of the adhesion/barrier layer comprises titanium nitride. h 358. The wafer packaging mechanism of claim 3, wherein the material of the adhesion/barrier layer comprises chromium. </ RTI> </ RTI> </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; The chip package structure of claim 1, wherein the material of the adhesion/barrier layer comprises tantalum nitride. 361 ^ The wafer sealing structure of claim 3, wherein the thickness of the adhesive/barrier layer is between 〇〇3 micrometers and 〇7 micrometers 362, as in claim 303. The chip package structure, wherein the metal layer further comprises a copper-based seed layer on the adhesion/barrier layer, a copper layer on the seed layer, and a nickel layer on the steel layer. I The palladium layer is on the nickel layer. 363. The wafer package structure of claim 3, wherein the thickness of the layer is between 1 micrometer and 20 micrometers. 364. The wafer package structure of claim 3, wherein the thickness of the layer is between 3 microns and 5 microns. 365. The chip package structure of claim 3, wherein the wire bonding pad has a thickness of between 1 micrometer and 20 micrometers. 366. The wafer sealing structure of claim 3, wherein the thickness of the wire bonding pad is between 3 micrometers and 5 micrometers. 367. The chip package structure of claim 3, wherein the wire bonding material comprises gold. 368. The chip package structure of claim 3, wherein the wire bonding wire has a diameter of between 20 micrometers and 50 micrometers. 369. The chip package structure of claim 303, wherein the material of the polymer material comprises epoxy. 370. The wafer package structure of claim 303, wherein the material of the polymer material comprises polyimine (pi). 371. The wafer package structure of claim 303, wherein the material of the polymer layer material comprises phenylcyclobutene (BCB). 372. The wafer package structure of claim 303, wherein the polymer material has a thickness between 250 microns and 1,000 microns. 373. The chip package structure of claim 303, wherein the wire bonding wire electrically connects the lead-free solder ball through a metal line of the substrate. 374. A chip package structure comprising: a substrate, a lead-free solder ball bonded to the substrate; an adhesive material positioned on the substrate; and a semiconductor wafer positioned on the adhesive material And the semiconductor wafer comprises: a semiconductor substrate; a wiring structure positioned above the semiconductor substrate; a protective layer positioned above the wiring structure, and an opening in the protective layer exposing one of the wiring structures a pad; and a metal line positioned above the protective layer and connected to the pad through the opening, and the metal line includes a gold layer; a wire bonding wire bonding the gold layer and the substrate; and a polymer material Positioned on the substrate 'and over the semiconductor wafer and the wire bonding wire. 375. The chip package structure of claim 374, wherein 116 200814213 the substrate is a ball grid array (BGA) substrate. 376. The wafer package structure of claim 374, wherein the substrate is a substrate comprising glass fibers and an epoxy resin. 377. The wafer package structure of claim 374, wherein the substrate is a glass substrate. 378. The wafer package structure of claim 374, wherein the substrate is a germanium substrate. 379. The wafer package structure of claim 374, wherein the substrate is a ceramic substrate. 380. The wafer package structure of claim 374, wherein the substrate is an organic substrate. 381. The wafer package structure of claim 374, wherein the substrate is a metal substrate. 382. The chip package structure of claim 374, wherein the substrate is a metal substrate, and the material of the metal substrate comprises aluminum. 383. The chip package structure of claim 374, wherein the substrate is a metal substrate, and the material of the metal substrate comprises copper. 384. The wafer package structure of claim 374, wherein the substrate has a thickness between 200 microns and 2,000 microns. 385. The chip package structure of claim 374, wherein the substrate comprises a first surface and a second surface, and the adhesive material and the polymer material are on the first surface, the lead-free tin The ball is on the second surface. 386. The chip package structure of claim 374, wherein: 117 200814213 the material of the error-free solder ball comprises a tin-silver alloy. 387. The chip package structure of claim 374, wherein the material of the error-free solder ball comprises a tin-silver-copper alloy 388, as described in claim 374. A chip package structure, wherein the lead-free solder ball has a diameter of between 0.25 cm and 1.2 cm. 389. The wafer package structure of claim 374, wherein the thickness of the adhesive material is between 1 micrometer and 50 micrometers. 390. The wafer package structure of claim 374, wherein the material of the adhesive material comprises a polymer material. 391. The wafer package structure of claim 374, wherein the adhesive material comprises polyimide (PI). 392. The chip package structure of claim 374, wherein the material of the adhesive material comprises an epoxy resin. 393. The wafer package structure of claim 374, wherein the semiconductor substrate comprises a chip. 394. The wafer package structure of claim 374, wherein the semiconductor substrate is on the adhesive material. 395. The chip package structure of claim 374, further comprising at least one metal oxide semiconductor (MOS) device positioned in or on the semiconductor substrate. 396. The wafer package structure of claim 374, wherein the wiring structure comprises a copper layer having a thickness between 0.2 microns and 2 microns. 397. The chip package structure of claim 374, wherein 118 200814213 the circuit structure comprises electroplated copper. 398. The wafer package structure of claim 374, wherein the wiring structure comprises an aluminum-containing metal layer having a thickness between 0.2 microns and 2 microns. 399. The chip package structure of claim 374, further comprising a plurality of dielectric layers between the semiconductor substrate and the protective layer, and wherein the plurality of patterned metal layers of the line structure are in the dielectric Between the layers, the plurality of metal plugs are connected adjacent to each other through the plurality of metal plugs in the dielectric layer (the two layers of the patterned metal layer. 400, the wafer according to claim 399) The package structure, wherein the dielectric layers have a dielectric constant value (k) of between 1.5 and 3. 401. The chip package structure of claim 399, wherein the dielectric layers are made of a material. The wafer package structure of claim 399, wherein the material of the dielectric layer comprises a nitrogen ruthenium compound. 403. The wafer package structure according to claim 399, The material of the dielectric layer includes a oxynitride compound. The wafer package structure of claim 399, wherein the material of the dielectric layer comprises a compound containing ruthenium, carbon, oxygen and hydrogen. 405. The chip package structure of claim 399, wherein the material of the dielectric layer comprises a Fluorinated Silicate Glass 406, the chip package structure as described in claim 399 The thickness of the dielectric layers is between 0.3 micrometers and 2.5 micrometers. 119 200814213 = protection:::= Γ 所述 ... ... ... 结构 结构 其中 其中 其中 其中 其中 其中 其中 409 409 409 409 409 409 409 409 The protective layer of the wafer comprises a oxynitride compound. The wafer package structure of claim 374, wherein the thickness of the protective layer is between 3 micrometers and 15 micrometers ("melon" The door Mi, as claimed in the patent application No. 374, describes the chip package m. The interface includes n having a thickness between G·2 μm and 2 μm and the metal line connects the copper layer. In the structure, the joint comprises a layer of indole gold having a thickness of between 微米. 2 μm and 2 μm, and the metal line is connected to the layer of the alloy. 川, as described in claim 374 Chip package structure, more package a metal protection cover is disposed on the pad exposed by the opening, and the genus line is connected to the metal protection cover. "" package structure, wherein 414, the wafer according to claim 4 is copper. The wafer package structure of claim 413, wherein the metal protective cover comprises a thickness of between (4. 4 micrometers and 2 micrometers), wherein the metal layer is exposed at the opening. On the pad, and a portion of the line is on the aluminum-containing metal layer. μ, genus 416, the wafer package structure of claim 415, wherein the material of the metal layer comprises copper. 417. The wafer according to claim 415 of the patent application. The material package containing the metal layer of the inscription (4). The wafer package structure of claim 418, wherein the metal protection cover comprises a barrier layer having a thickness between 〇〇1 μm and 〇·7 μm (the barrier layer Mi is in the The opening is exposed 及^度介於（M微米至2微米之間的—含|g金屬層位在該 阻障層上，且部分該金屬線路位在該含鋁金屬層上。 彻、如中請專利範圍第418項所述之晶片封裝結構，其中 該阻障層的材質包括鈥。 、如申請專利範圍第418項所述之晶片封裝結構，其中 該阻障層的材質包括鈦鎢合金。 421、 如申請專利範圍第418項所述之晶片封裝結構， 該阻障層的材質包括氮化鈥。 八 422、 *申請專利範圍第418項所述之晶片封裝結構， 該阻障層的材質包括鉻。 封裝結構，其中 423 '如申請專利範圍第418項所述之晶片 該阻障層的材質包括紐。 424、 如申請專利範圍第418項所述之晶片封裝結構 該阻障層的材質包括氮化钽。 八 425、 如申請專利範圍第418項所述之晶片封裝於構，直 該含鋁金屬層的材質包括銅。 其中 426、 如申請專利範圍第418項所述之晶片封裝梦構直 該含鋁金屬層的材質包括銅與矽。 ”中 121 200814213 42/ - 如申請專利範圍第374項所述之晶片封裝結構，其中 該金屬線路更包括一黏著/阻障層與一種 ^ a 嘈位在該黏著/ 阻P羊層上，且該金層位在該種子層上方。 428、如申請專利範圍第427項所述之晶片封裝結構，其中 該黏著/阻障層的材質包括鈦。 ^ 429、 如申請專利範圍第427項所述之晶片封裝結構，其 該黏著/阻障層的材質包括鈦鎢合金。And a degree of (between M micrometers and 2 micrometers) containing a layer of |g metal on the barrier layer, and a portion of the metal trace is on the aluminum-containing metal layer. The wafer package structure of claim 418, wherein the material of the barrier layer comprises a wafer package structure according to claim 418, wherein the material of the barrier layer comprises a titanium tungsten alloy. The chip package structure of the invention of claim 418, wherein the material of the barrier layer comprises tantalum nitride. The chip package structure described in claim 418, the material of the barrier layer comprises chromium. The structure of the barrier layer according to claim 418, wherein the material of the barrier layer comprises a germanium. 424. The material of the barrier layer according to claim 418, wherein the material of the barrier layer comprises tantalum nitride. </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> <RTIgt; </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> <RTIgt; Aluminum gold The material of the genus layer includes copper and germanium. The medium of the wafer package structure of claim 374, wherein the metal circuit further comprises an adhesive/barrier layer and a a a </ RTI> </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; The wafer package structure of claim 427, wherein the material of the adhesion/barrier layer comprises a titanium-tungsten alloy. 430、 “如申請專利範圍第427項所述之晶片封裝結構，其中 該黏著/阻障層的材質包括氮化鈦。 431、 如申請專利範圍第427項所述之晶片封装結構，盆中 該黏著/阻障層的材質包括鉻。 八 432、 如申請專㈣圍第427項所述之晶片封裝結構，其中 該黏著/阻障層的材質包括鈕。 八 433、 如申請專利範圍第427項所述之晶片封裝結構，盆中 該黏著/阻障層的材質包括氮化鈕。 /、 434如申請專利範圍第427項所述之晶片封裝結構，其中 該黏著/阻障層的厚度係介於0·03微米至〇·7微米之門。 435、 如申請專利範圍第427項所述之晶片封裝結構，其中 該種子層的材質為金，且該金層位在該種子層上。 436、 如申請專利範圍第427項所述之晶片封裝結構，其中 該種子層的材質為銅’且該金屬線路更包括—銅層位ς該 種子層上以及一鎳層位在該銅層上，該金層位在該鎳層上。 437、 如申請專利範圍第374項所述之晶片封裝結構，曰其中 該金層的厚度係介於1微米至20微米之間。 122 200814213 438、 如申請專利範圍第374項所述之晶片封裝結構，其中 該金層的厚度係介於3微米至5微米之間。 439、 如申請專利範圍第374項所述之晶片封裝結構，其中 該金屬線路的厚度係介於1微米至20微米之間。 440、 如申請專利範圍第374項所述之晶片封裝結構，其中 該金屬線路的厚度係介於3微米至5微米之間。 441、 如申請專利範圍第374項所述之晶片封裝結構，其中 該打線導線的材質包括金。 442、 如申請專利範圍第374項所述之晶片封裝結構，其中 該打線導線的直徑介於20微米至50微米之間。 443、 如申請專利範圍第374項所述之晶片封裝結構，其中 該聚合物材料的材質包括環氧樹脂（epoxy)。 444、 如申請專利範圍第374項所述之晶片封裝結構，其中 該聚合物材料的材質包括聚醯亞胺（PI)。 445、 如申請專利範圍第374項所述之晶片封裝結構，其中 該聚合物層材料的材質包括苯基環丁浠(BCB)。 446、 如申請專利範圍第374項所述之晶片封裝結構，其中 該聚合物材料的厚度係介於250微米至1，000微米之間。 447、 如申請專利範圍第374項所述之晶片封裝結構，其中 該打線導線係透過該基板的一金屬線路電性連接該無鉛錫 球。 448、 如申請專利範圍第374項所述之晶片封裝結構，其中 該打線導線接合該金層的位置從俯視透視圖觀之，係不同 於該接墊的位置。 123 200814213 449、 如申請專利範圍第374項所述之晶片封裝結構，更包 括一聚合物層位在該保護層上，且位在該聚合物層内之一 聚合物層開口暴露出該接墊，該金屬線路位在該聚合物層 上並透過該聚合物層開口連接該接墊。 450、 如申請專利範圍第449項所述之晶片封裝結構，其中 該聚合物層的材質包括聚醯亞胺（PI)。 451、 如申請專利範圍第449項所述之晶片封裝結構，其中 該聚合物層的材質包括環氧樹脂（epoxy)。 452、 如申請專利範圍第449項所述之晶片封裝結構，其中 該聚合物層的材質包括苯基環丁烯（BCB)。 453、 如申請專利範圍第449項所述之晶片封裝結構，其中 該聚合物層的厚度係介於3微米至25微米之間。 454、 如申請專利範圍第374項所述之晶片封裝結構，更包 括一聚合物層位在該金屬線路上，且位在該聚合物層内之 一聚合物層開口暴露出該金層，該打線導線透過該聚合物 層開口接合該金層。 455、 如申請專利範圍第454項所述之晶片封裝結構，其中 該聚合物層的材質包括聚醯亞胺（PI)。 456、 如申請專利範圍第454項所述之晶片封裝結構，其中 該聚合物層的材質包括環氧樹脂（epoxy)。 457、 如申請專利範圍第454項所述之晶片封裝結構，其中 該聚合物層的材質包括苯基環丁烯（BCB)。 458、 如申請專利範圍第454項所述之晶片封裝結構，其中 該聚合物層的厚度係介於3微米至25微米之間。 124 200814213 459、 一種晶片封裝結構，包括： 一基板； 一無錯錫球（lead-free solder ball)，接合該基板； 一黏著材料，位在該基板上； 一半導體晶片’位在該黏著材料上’且該半導體晶片包 括一打線接點； 一打線導線，接合該打線接點與該基板；以及 一聚合物材料，位在該基板上，並覆蓋該半導體晶片與 該打線導線。 460、 如申請專利範圍第459項所述之晶片封裝結構，其中 該基板為球型柵狀陣列（BGA)基板。 461、 如申請專利範圍第459項所述之晶片封裝結構，其中 該基板為含有玻璃纖維與環氧樹脂的基板。 462、 如申請專利範圍第459項所述之晶片封裝結構，其中 該基板為玻璃基板。 463、 如申請專利範圍第459項所述之晶片封裝結構，其中 該基板為矽基板。 464、 如申請專利範圍第459項所述之晶片封裝結構，其中 該基板為陶瓷基板。 465、 如申請專利範圍第459項所述之晶片封裝結構，其中 該基板為有機基板。 466、 如申請專利範圍第459項所述之晶片封裝結構，其中 該基板為金屬基板。 467、 如申請專利範圍第459項所述之晶片封裝結構，其中 125 200814213 該基板為金屬基板，且該金屬基板的材質包括鋁。 468、 如申請專利範圍第459項所述之晶片封裝結構，其中 該基板為金屬基板，且該金屬基板的材質包括銅。 469、 如申請專利範圍第459項所述之晶片封裝結構，其中 該基板的厚度係介於200微米至2,000微米之間。 470、 如申請專利範圍第459項所述之晶片封裝結構，其中 該基板包括一第一表面與一第二表面，且該黏著材料與該 聚合物材料位在該第一表面上，該無鉛錫球位在該第二表 面上。 471、 如申請專利範圍第459項所述之晶片封裝結構，其中 該無錯錫球的材質包括錫銀合金（tin-silver alloy)。 472、 如申請專利範圍第459項所述之晶片封裝結構，其中 該無船鍚球的材質包括錫銀銅合金（tin-silver-copper alloy) 〇 473、 如申請專利範圍第459項所述之晶片封裝結構，其中 該無鉛錫球的直徑介於（K25釐米至1.2釐米（mm)之間。 474、 如申請專利範圍第459項所述之晶片封裝結構，其中 該黏著材料的厚度係介於1微米至50微米之間。 475、 如申請專利範圍第459項所述之晶片封裝結構，其中 該黏著材料的材質包括聚合物材料。 476、 如申請專利範圍第459項所述之晶片封裝結構，其中 該黏著材料的材質包括聚驢亞胺（polyimide，PI)。 477、 如申請專利範圍第459項所述之晶片封裝結構，其中 該黏著材料的材質包括環氧樹脂（epoxy resin)。 126 200814213 478、 如申請專利範圍第459項所述之晶片封裝結構，其中 該半導體晶片更包括· 一半導體基底； 一線路結構，位在該半導體基底上方；以及 一保護層，位在該線路結構上方，且位在該保護層内之 一開口暴露出該線路結構之一接墊。 479、 如申請專利範圍第478項所述之晶片封裝結構，其中 該半導體基底包括矽。 480、 如申請專利範圍第478項所述之晶片封裝結構，其中 該半導體基底位在該黏者材料上。 481、 如申請專利範圍第478項所述之晶片封裝結構，更包 括至少一金氧半導體（MOS)元件位在該半導體基底内或上 方。 482、 如申請專利範圍第478項所述之晶片封裝結構，其中 該線路結構包括厚度介於0·2微米至2微米之間的一銅層。 483、 如申請專利範圍第478項所述之晶片封裝結構，其中 該線路結構包括電鍍銅。 484、 如申請專利範圍第478項所述之晶片封裝結構，其中 該線路結構包括厚度介於0.2微米至2微米之間的一含鋁 金屬層。 485、 如申請專利範圍第478項所述之晶片封裝結構，更包 括複數介電層位在該半導體基底與該保護層之間，且該線 路結構之複數圖案化金屬層位在該些介電層之間，並透過 位在該些介電層内的該線路結構之複數金屬插塞連接相鄰 127 200814213 兩層之該些圖案化金屬層。 486、 如申請專利範圍第485項所述之晶片封裝結構，其中 該些介電層的介電常數值（k)係介於1.5至3之間。 487、 如申請專利範圍第485項所述之晶片封裝結構，其中 該些介電層的材質包括氧矽化合物。 488、 如申請專利範圍第485項所述之晶片封裝結構，其中 該些介電層的材質包括氮;e夕化合物。 489、 如申請專利範圍第485項所述之晶片封裝結構，其中 該些介電層的材質包括氮氧矽化合物。 490、 如申請專利範圍第485項所述之晶片封裝結構，其中 該些介電層的材質包括含矽、碳、氧與氳之化合物。 491、 如申請專利範圍第485項所述之晶片封裝結構，其中 該些介電層的材質包括氟石夕玻璃（Fluorinated Silicate Glass) 〇 492、 如申請專利範圍第485項所述之晶片封裝結構，其中 該些介電層的厚度係介於0.3微米至2.5微米之間。 493、 如申請專利範圍第478項所述之晶片封裝結構，其中 該保護層包括氧矽化合物。 、 494、 如申請專利範圍第478項所述之晶片封裝結構，其中 該保護層包括氮碎化合物。 495、 如申請專利範圍第478項所述之晶片封裝結構，其中 該保護層包括氮氧矽化合物。 496、 如申請專利範圍第478項所述之晶片封裝結構，其中 該保護層的厚度係介於0.3微米至1.5微米（// m)之間。 200814213 497、如申請專利範圍第梢項所述之晶片封裝結構，其中 該接墊包括厚度介於〇.2微米至2微米之間的—鋼層。 视、如申請專利範圍第谓項所述之晶片封裝結構其中 該接墊包括厚度介於〇.2微米至2微米之間的—鋁合金層。 499、 如申請專利範圍第478項所述之晶片封裝結二其曰中 該打線接點位在該接墊上。 500、 如申請專利範圍第478項所述之晶片封裝結構，其中 該打線接點位在該保護層上方。 501、 如申請專利範圍第478項所述之晶片封裝結構，更包 括一，屬保護蓋位在該接塾上，且該打線接點位在該金屬 保遵盖上。 “ 502曰、如中請專利範圍第谓項所述之晶片封裝結構，更包 括厚度w S G.4微米至2微米之間的一含銘金屬層位在該 開口所暴露出之該接塾上，且該打線接點位在該含銘金屬 層上。 503:如中請專利範圍第項所述之晶片封裝結構，更包 括厚度介於0·01微米至〇·7微米之間的一含鈦金屬層位在 該開口所暴露出之該接墊上，以及厚度介於G.4微米至2 微米之間的一含鋁金屬層位在該阻障層上，且該打線接點 位在該含鋁金屬層上。 〇4^如申凊專利範圍第478項所述之晶片封裝結構，更包 s + ’1於〇 〇1微米至〇·7微米之間的一鉻層位在該開口 出之該接墊上，以及厚度介於〇·4微米至2微米之 金屬層位在該鉻層上，且該打線接點位在該含 129 200814213 铭金屬層上。 505、 如申請專利範圍第478項所述之晶片封裝結構，更包 括厚度介於0.01微米至0.7微米之間的一含钽金屬層位在 該開口所暴露出之該接墊上，以及厚度介於0.4微米至2 微米之間的一含鋁金屬層位在該含钽金屬層上，且該打線 接點位在該含鋁金屬層上。 506、 如申請專利範圍第478項所述之晶片封裝結構，更包 括一金屬線路位在該保護層上方，並透過該開口連接該接 墊，且該打線接點係為該金屬線路之一部份。 507、 如申請專利範圍第506項所述之晶片封裝結構，其中 該金屬線路的材質包括金。 508、 如申請專利範圍第506項所述之晶片封裝結構，其中 該金屬線路的材質包括銅。 509、 如申請專利範圍第506項所述之晶片封裝結構，其中 該金屬線路的材質包括鎳。 510、 如申請專利範圍第506項所述之晶片封裝結構，其中 該金屬線路的材質包括鈀。 511、 如申請專利範圍第459項所述之晶片封裝結構，其中 該打線接點包括一金層，且該打線導線接合該金層。 512、 如申請專利範圍第459項所述之晶片封裝結構，其中 該打線接點包括一鈀層，且該打線導線接合該鈀層。 513、 如申請專利範圍第459項所述之晶片封裝結構，其中 該打線接點包括一黏著/阻障層、一種子層位在該黏著/阻 障層上以及一金屬層位在該種子層上。 130 200814213 514、 如申請專利範圍第513項所述之晶片封裝於構，直 該黏著/阻障層的材質包括鈦。 /、中 515、 如申請專利範圍第513項所述之晶片封裝奸構，复 該黏著/阻障層的材質包括鈦鎢合金。 〃中 516、 如申請專利範圍第513項所述之晶片封裝結構，其中 該黏著/阻障層的材質包括氮化鈦。 517、 如申請專利範圍第513項所述之晶片封裝結構，其 該黏著/阻障層的材質包括鉻。 /、 518二如申請專利範圍第513項所述之晶片封裝結構，其中 該黏著/阻障層的材質包括钽。 519、如申請專利範圍第513項所述之晶片封裝結構，盆中 該黏著/阻障層的材質包括氮化鈕。 '、 52〇、#如申請專利範圍第513項所述之晶片封裴結構，其中 該黏著/阻障層的厚度係介於〇 〇3微米至〇·7微米之門 521、 如申請專利範圍第513項所述之晶片封裴結構，其中 該種子層的厚度係介於0.03微米至0.7微米之間。 522、 如申請專利範圍第513項所述之晶片封裝結構，其中 該種子層的材質為金，且該金屬層的材質為金。 523、 如申請專利範圍第513項所述之晶片封裝結構，其中 該種子層的材質為銅，且該金屬層包括一鋼層位在該種子 層上、一鎳層位在該銅層上以及一金層位在該鎳層上，該 打線導線接合該金層。 ~ 524如申喷專利範圍第513項所述之晶片封裝結構，其中 該種子層的材質為銅，且該金屬層包括_銅層位在該種子 131 200814213 層上、一鎳層位在該銅層上以及一鈀層位在該鎳層上，該 打線導線接合該鈀層。 525、 如申請專利範圍第513項所述之晶片封裝結構，其中 該金屬層的厚度係介於1微米至20微米之間。 526、 如申請專利範圍第513項所述之晶片封裝結構，其中 該金屬層的厚度係介於3微米至5微米之間。 527、 如申請專利範圍第459項所述之晶片封裝結構，其中 該打線接點的厚度係介於1微米至20微米之間。 528、 如申請專利範圍第459項所述之晶片封裝結構，其中 該打線接點的厚度係介於3微米至5微米之間。 529、 如申請專利範圍第459項所述之晶片封裝結構，其中 該打線導線的材質包括金。 530、 如申請專利範圍第459項所述之晶片封裝結構，其中 該打線導線的直徑介於20微米至50微米之間。 531、 如申請專利範圍第459項所述之晶片封裝結構，其中 該聚合物材料的材質包括環氧樹脂（epoxy)。 532、 如申請專利範圍第459項所述之晶片封裝結構，其中 該聚合物材料的材質包括聚醯亞胺（PI)。 533、 如申請專利範圍第459項所述之晶片封裝結構，其中 該聚合物層材料的材質包括苯基環丁烯（BCB)。 534、 如申請專利範圍第459項所述之晶片封裝結構，其中 該聚合物材料的厚度係介於250微來至1,000微米之間。 535、 如申請專利範圍第459項所述之晶片封裝結構，其中 該打線導線係透過該基板的一金屬線路電性連接該無鉛錫 132 200814213 球。 536、一種晶片封裝結構，包括·· ^線架（lead frame)，包括一晶片承載座與一引腳； 一黏著材料，位在該晶片承載座上； 一半導體晶片，位在該黏著材料上，且該半導體晶片包 括： 一半導體基底； 一線路結構，位在該半導體基底上方； 保濩層，位在該線路結構上方，且位在該保護層 内之一開口暴露出該線路結構之一接墊；以及 一打線接墊，包括一黏著/阻障層與一金屬層位在該 黏著/阻障層上，其中該黏著/阻障層位在該開口所暴 露出之該接墊上，且該金屬層包括一金層； 一打線導線，接合該金層與該引腳；以及 一聚合物材料，包覆該晶片承載座、該半導體晶片、該 打線導線與部份之該引腳。 537、 如申請專利範圍第536項所述之晶片封裝結構，其中 該導線架的材質包括銅。 538、 如申請專利範圍第536項所述之晶片封叢結構，其中 該導線架的厚度係介於1〇〇微米至2,000微米之間。 539、 如申請專利範圍第536項所述之晶片封裝結構，其中 該黏著材料的厚度係介於1微米至50微米之間。 540、 如申請專利範圍第536項所述之晶片封裝結構，其中 該黏著材料的材質包括聚合物材料。 133 200814213 541、 如申請專利範圍第536項所述之晶片封裝結構，其中 該黏著材料的材質包括聚醯亞胺（polyimide，PI)。 542、 如申請專利範圍第536項所述之晶片封裝結構，其中 該黏著材料的材質包括環氧樹脂（epoxy resin)。 543、 如申請專利範圍第536項所述之晶片封裝結構，其中 該半導體基底包括梦。 544、 如申請專利範圍第536項所述之晶片封裝結構，其中 該半導體基底位在該黏者材料上。 545、 如申請專利範圍第536項所述之晶片封裝結構，更包 括至少一金氧半導體（MOS)元件位在該半導體基底内或上 方。 546、 如申請專利範圍第536項所述之晶片封裝結構，其中 該線路結構包括厚度介於0.2微米至2微米之間的一銅層。 547、 如申請專利範圍第536項所述之晶片封裝結構，其中 該線路結構包括電鍍銅。 548、 如申請專利範圍第536項所述之晶片封裝結構，其中 該線路結構包括厚度介於0.2微米至2微米之間的一含鋁 金屬層。 549、 如申請專利範圍第536項所述之晶片封裝結構，更包 括複數介電層位在該半導體基底與該保護層之間，且該線 路結構之複數圖案化金屬層位在該些介電層之間，並透過 位在該些介電層内的該線路結構之複數金屬插塞連接相鄰 兩層之該些圖案化金屬層。 550、 如申請專利範圍第549項所述之晶片封裝結構，其中 134 200814213 該些介電層的介電常數值（k)係介於1.5至3之間。 551、 如申請專利範圍第549項所述之晶片封裝結構，其中 該些介電層的材質包括氧矽化合物。 552、 如申請專利範圍第549項所述之晶片封裝結構，其中 該些介電層的材質包括氮矽化合物。 553、 如申請專利範圍第549項所述之晶片封裝結構，其中 該些介電層的材質包括氮氧矽化合物。 554、 如申請專利範圍第549項所述之晶片封裝結構，其中 該些介電層的材質包括含矽、碳、氧與氫之化合物。 555、 如申請專利範圍第549項所述之晶片封裝結構，其中 該些介電層的材質包括氣石夕玻璃（Fluorinated Silicate Glass) 〇 556、 如申請專利範圍第549項所述之晶片封裝結構，其中 該些介電層的厚度係介於0.3微米至2.5微米之間。 557、 如申請專利範圍第536項所述之晶片封裝結構，其中 該保護層包括氧矽化合物。 558、 如申請專利範圍第536項所述之晶片封裝結構，其中 該保護層包括氮石夕化合物。 559、 如申請專利範圍第536項所述之晶片封裝結構，其中 該保護層包括氮氧矽化合物。 560、 如申請專利範圍第536項所述之晶片封裝結構，其中 該保護層的厚度係介於〇·3微米至1.5微米（// m)之間。 561、 如申請專利範圍第536項所述之晶片封裝結構，其中 該接墊的厚度係介於0.2微米至2微米之間。 135 200814213 562、 如申請專利範圍第536項所述之晶片封裝奸構，其中 該接塾包括厚度介於〇·2微米至2微米之 间的一銘合金 層’且該黏著/阻障層位在該鋁合金層上。 563、 如申請專利範圍第536項所述之晶片封裝結構，其中 該黏著/阻障層的材質包括鈦。 〃 564、 如申請專利範圍第536項所述之晶片封骏結構，其中 該黏著/阻障層的材質包括鈦鎢合金。 、 565、 如申請專利範圍第536項所述之晶片封裝結構，其中 該黏著/阻障層的材質包括氮化鈦。 566、 如申請專利範圍第536項所述之晶片封裝結構，其中 該黏著/阻障層的材質包括鉻。 567、 —如申請專利範圍第536項所述之晶片封裝結構，其中 該黏著/阻障層的材質包括鈕。 、 568、 #如中請專利範圍第別項所述之晶片封|結構，其中 該黏著/阻障層的材質包括氮化鈕。 569、 #如申請專利範圍第536項所述之晶片封襄結構，其中 該黏著/阻障層的厚度係介於〇 〇3微米至〇·7微米之門 570、 如申請專利範圍第別項所述之晶片封裝結構，盆中 該金屬層更包括材質為金的—種子層位在該黏著/阻障層 上’且該金層位在該種子層上。 曰 571、 如申請專利範圍第536項所述之晶片封裝結構，其中 該金屬層更包括材質為銅的—種子層位在該黏著/阻障層 上、一銅層位在該種子層上以及一鎳層位在該銅層上，且 該金層位在該鎳層上。 136 200814213 572、 如申請專利範圍第536項所述之晶片封裝結構，其中 該金層的厚度係介於1微米至20微米之間。 573、 如申請專利範圍第536項所述之晶片封裝結構，其中 該金層的厚度係介於3微米至5微米之間。 574、 如申請專利範圍第536項所述之晶片封裝結構，其中 該打線接墊的厚度係介於1微米至20微米之間。 575、 如申請專利範圍第536項所述之晶片封裝結構，其中 該打線接墊的厚度係介於3微米至5微米之間。 576、 如申請專利範圍第536項所述之晶片封裝結構，其中 該打線導線的材質包括金。 577、 如申請專利範圍第536項所述之晶片封裝結構，其中 該打線導線的直徑介於20微米至50微米之間。 578、 如申請專利範圍第536項所述之晶片封裝結構，其中 該聚合物材料的材質包括環氧樹脂（epoxy)。 579、 如申請專利範圍第536項所述之晶片封裝結構，其中 該聚合物材料的材質包括聚醯亞胺（PI)。 580、 如申請專利範圍第536項所述之晶片封裝結構，其中 該聚合物層材料的材質包括苯基環丁烯（BCB)。 581、 如申請專利範圍第536項所述之晶片封裝結構，其中 該聚合物材料的厚度係介於250微米至1，000微米之間。 582、 一種晶片封裝結構，包括： 一導線架（lead frame)，包括一晶片承載座與一引腳； 一黏著材料，位在該晶片承載座上； 一半導體晶片^位在該黏者材料上’且該半導體晶片包 137 200814213 括： 一半導體基底； 一線路結構’位在該半導體基底上方； 一保護層，位在該線路結構上方，且位在該保護層 内之一開口暴露出該線路結構之一銅墊；以及 一打線接墊，包括一黏著/阻障層與一金屬層位在該 黏著/阻障層上，其中該黏著/阻障層位在該開口所暴 露出之該銅墊上，且該金屬層包括一金層； 一打線導線，接合該金層與該引腳；以及 一聚合物材料，包覆該晶片承載座、該半導體晶片、該 打線導線與部份之該引腳。 583、 如申請專利範圍第582項所述之晶片封裝結構，其中 該導線架的材質包括銅。 584、 如申請專利範圍第582項所述之晶片封裝結構，其中 該導線架的厚度係介於100微米至2,000微米之間。 585、 如申請專利範圍第582項所述之晶片封裝結構，其中 該黏著材料的厚度係介於1微米至50微米之間。 586、 如申請專利範圍第582項所述之晶片封裝結構，其中 該黏著材料的材質包括聚合物材料。 587、 如申請專利範圍第582項所述之晶片封裝結構，其中 該黏著材料的材質包括聚醯亞胺（polyimide，PI)。 588、 如申請專利範圍第582項所述之晶片封裝結構，其中 該黏著材料的材質包括環氧樹脂（epoxy resin)。 589、 如申請專利範圍第582項所述之晶片封裝結構，其中 138 200814213 該半導體基底包括矽。 590、 如申請專利範圍第582項所述之晶片封裝結構，其中 該半導體基底位在該黏著材料上。 591、 如申請專利範圍第582項所述之晶片封裝結構，更包 括至少一金氧半導體（MOS)元件位在該半導體基底内或上 方。 592、 如申請專利範圍第582項所述之晶片封裝結構，其中 該線路結構包括厚度介於0.2微米至2微米之間的一銅層。 593、 如申請專利範圍第582項所述之晶片封裝結構，其中 該線路結構包括電鍍銅。 594、 如申請專利範圍第582項所述之晶片封裝結構，更包 括複數介電層位在該半導體基底與該保護層之間，且該線 路結構之複數圖案化金屬層位在該些介電層之間，並透過 位在該些介電層内的該線路結構之複數金屬插塞連接相鄰 兩層之該些圖案化金屬層。 595、 如申請專利範圍第594項所述之晶片封裝結構，其中 該些介電層的介電常數值（k)係介於1.5至3之間。 596、 如申請專利範圍第594項所述之晶片封裝結構，其中 該些介電層的材質包括氧矽化合物。 597、 如申請專利範圍第594項所述之晶片封裝結構，其中 該些介電層的材質包括氮矽化合物。 598、 如申請專利範圍第594項所述之晶片封裝結構，其中 該些介電層的材質包括氮氧矽化合物。 599、 如申請專利範圍第594項所述之晶片封裝結構，其中 139 200814213 該二η電層的材質包括含碎、碳、氧與氫之化合物。 600、 如申請專利範圍第594項所述之晶片封裝結構，其中 該些介電層的材質包括氟矽玻璃（Flu〇rinated sme'ate Glass) 〇 601、 如申請專利範圍第594項所述之晶片封裝結構其中 該些介電層的厚度係介於〇·3微米至2.5微米之間。 602、 如申請專利範圍第582項所述之晶片封裴結構，其中 該保護層包括氧石夕化合物。 603、 如申請專利範圍第582項所述之晶片封裝結構其中 該保護層包括氮石夕化合物。 604、 如申請專利範圍第582項所述之晶片封裝結構其中 該保護層包括氮氧矽化合物。 605、 如申請專利範圍第582項所述之晶片封裝結構，其中 該保護層的厚度係介於〇·3微米至h5微米（以瓜)之間。 606、 如申請專利範圍第582項所述之晶片封裝結構，其中 該銅塾的厚度係介於0.2微米至2微米之間。 607、 如申請專利範圍第582項所述之晶片封裝結構，其中 該黏著/阻障層的材質包括鈦。 h 608 ^如申請專利範圍第582項所述之晶片封裝結構，其中 該黏著/阻障層的材質包括鈦鎢合金。 609 ^如申請專利範圍第582項所述之晶片封裝結構，其中 該黏著/阻障層的材質包括氮化鈦。 “ _、如申請專利範圍第582項所述之晶片封裝結構， 該黏著/阻障層的材質包括鉻。 ^ 140 200814213 611、 如申請專利範圍第582項所述之晶片封裝結構，且中 該黏著/阻障層的材質包括鈕。 612、 广申請專利範圍第582項所述之晶片封裝結構，其中 該黏著/阻障層的材質包括氮化鈕。 613、 如申請專利_第5 8 2項所述之晶片封裝結構，其中 該黏著/阻障層的厚度係介於〇·〇3微米至〇·7微米之間。 614、 如申請專利範圍第582項所述之晶片封裝結構，其中 該金屬層更包括材質為金的—種子層位在該黏著/阻障層 上’且該金層位在該種子層上。 615、 如中請專利範圍第582項所述之晶片封裝結構，其中 該金屬層更包括材質為銅的—種子層位在該黏著/阻障層 上、一銅層位在該種子層上以及一鎳層位在該銅層上，且 該金層位在該錄層上。 616、 如申請專利範圍第582項所述之晶片封裝結構，其中 該金層的厚度係介於1微米至2〇微米之間。 617、 如申請專利範圍第582項所述之晶片封裝結構，其中 該金層的厚度係介於3微米至5微米之間。 618、 如申請專利範圍第582項所述之晶片封裝結構，其中 該打線接墊的厚度係介於1微米至20微米之間。 619、 如申請專利範圍第5 8 2項所述之晶片封裝結構，其中 該打線接墊的厚度係介於3微米至5微米之間。 620、 如申請專利範圍第582項所述之晶片封裝結構，其中 該打線導線的材質包括金。 621、 如申請專利範圍第582項所述之晶片封裝結構，其中 141 200814213 該打線導線的直徑介於20微米至50微米之間。 622、 如申請專利範圍第582項所述之晶片封裝結構，其中 該聚合物材料的材質包括環氧樹脂（epoxy)。 623、 如申請專利範圍第582項所述之晶片封裝結構，其中 該聚合物材料的材質包括聚醯亞胺（PI)。 624、 如申請專利範圍第582項所述之晶片封裝結構，其中 該聚合物層材料的材質包括苯基環丁烯(BCB)。 625、 如申請專利範圍第582項所述之晶片封裝結構，其中 該聚合物材料的厚度係介於250微米至1,000微米之間。 626、 一種晶片封裝結構，包括： 一導線架，包括一晶片承載座與一引腳； 一黏著材料，位在該晶片承載座上； 一半導體晶片’位在該黏者材料上’且該半導體晶片包 括： 一半導體基底； 一線路結構，位在該半導體基底上方； 一保護層，位在該線路結構上方，且位在該保護層 内之一開口暴露出該線路結構之一接墊；以及 一打線接墊，包括一黏著/阻障層與一金屬層位在該 黏著/阻障層上，其中該黏著/阻障層位在該開口所暴 露出之該接墊上，且該金屬層包括一鈀層； 一打線導線，接合該鈀層與該引腳；以及 一聚合物材料，包覆該晶片承載座、該半導體晶片、該 打線導線與部份之該引腳。 142 200814213 627、 如申請專利範圍第626項所述之晶片封裝結構，其中 該導線架的材質包括銅。 628、 如申請專利範圍第626項所述之晶片封裝結構，其中 該導線架的厚度係介於100微米至2,000微米之間。 629、 如申請專利範圍第626項所述之晶片封裝結構，其中 該黏著材料的厚度係介於1微米至50微米之間。 630、 如申請專利範圍第626項所述之晶片封裝結構，其中 該黏著材料的材質包括聚合物材料。 631、 如申請專利範圍第626項所述之晶片封裝結構，其中 該黏著材料的材質包括聚酸亞胺（polyimide，PI)。 632、 如申請專利範圍第626項所述之晶片封裝結構，其中 該黏著材料的材質包括環氧樹脂（epoxy resin)。 633、 如申請專利範圍第626項所述之晶片封裝結構，其中 該半導體基底包括矽。 634、 如申請專利範圍第626項所述之晶片封裝結構，其中 該半導體基底位在該黏者材料上。 635、 如申請專利範圍第626項所述之晶片封裝結構，更包 括至少一金氧半導體（MOS)元件位在該半導體基底内或上 方。 636、 如申請專利範圍第626項所述之晶片封裝結構，其中 該線路結構包括厚度介於0.2微米至2微米之間的一銅層。 637、 如申請專利範圍第626項所述之晶片封裝結構，其中 該線路結構包括電鍍銅。 638、 如申請專利範圍第626項所述之晶片封裝結構，其中 143 200814213 該線路結構包括厚度介於0.2微米至2微米之間的一含鋁 金屬層。 639、 如申請專利範圍第626項所述之晶片封裝結構，更包 括複數介電層位在該半導體基底與該保護層之間，且該線 路結構之複數圖案化金屬層位在該些介電層之間，並透過 位在該些介電層内的該線路結構之複數金屬插塞連接相鄰 兩層之該些圖案化金屬層。 640、 如申請專利範圍第639項所述之晶片封裝結構，其中 該些介電層的介電常數值（k)係介於1.5至3之間。 641、 如申請專利範圍第639項所述之晶片封裝結構，其中 該些介電層的材質包括氧矽化合物。 642、 如申請專利範圍第639項所述之晶片封裝結構，其中 該些介電層的材質包括氮矽化合物。 643、 如申請專利範圍第639項所述之晶片封裝結構，其中 該些介電層的材質包括氮氧矽化合物。 644、 如申請專利範圍第639項所述之晶片封裝結構，其中 該些介電層的材質包括含矽、碳、氧與氫之化合物。 645、 如申請專利範圍第639項所述之晶片封裝結構，其中 該些介電層的材質包括氟^石夕玻璃（Fluorinated Silicate Glass) 〇 646、 如申請專利範圍第639項所述之晶片封裝結構，其中 該些介電層的厚度係介於0.3微米至2.5微米之間。 647、 如申請專利範圍第626項所述之晶片封裝結構，其中 該保護層包括氧石夕化合物。 144 200814213 648、如申請專利範圍第626項所述之晶片封裝結構，其中 該保護層包括氮石夕化合物。 649、如申請專利範圍第626項所述之晶片封裝結構，其中 該保護層包括氮氧石夕化合物。 650、 如申請專利範圍第626項所述之晶片封裝結構，其中 該保護層的厚度係介於〇·3微米至1·5微米（以叫之門 651、 如申請專利範圍第626項所述之晶片封裝結構，其中 該接墊的厚度係介於〇·2微米至2微米之間。430. The wafer package structure of claim 427, wherein the material of the adhesion/barrier layer comprises titanium nitride. 431. The wafer package structure according to claim 427, in the basin The material of the adhesive/barrier layer comprises chrome. 432. The wafer package structure as described in claim 4, wherein the material of the adhesive/barrier layer comprises a button. 8433, as claimed in claim 427 In the chip package structure, the material of the adhesion/barrier layer in the basin comprises a nitride button. The wafer package structure according to claim 427, wherein the thickness of the adhesion/barrier layer is 435. The wafer package structure of claim 427, wherein the seed layer is made of gold and the gold layer is on the seed layer. The wafer package structure of claim 427, wherein the seed layer is made of copper and the metal circuit further comprises a copper layer on the seed layer and a nickel layer on the copper layer. The gold layer is on the nickel layer 437. The wafer package structure of claim 374, wherein the thickness of the gold layer is between 1 micrometer and 20 micrometers. 122 200814213 438, as described in claim 374. The chip package structure, wherein the thickness of the gold layer is between 3 micrometers and 5 micrometers. 439. The chip package structure of claim 374, wherein the metal trace has a thickness of between 1 micrometer and 20 micrometers. 440. The wafer package structure of claim 374, wherein the thickness of the metal line is between 3 micrometers and 5 micrometers. 441. The wafer of claim 374. The package structure, wherein the material of the wire bonding wire comprises gold. 442. The chip package structure of claim 374, wherein the wire bonding wire has a diameter of between 20 micrometers and 50 micrometers. 443. The chip package structure of claim 374, wherein the material of the polymer material comprises epoxy. 444. The chip package structure according to claim 374 The material of the polymer material comprises a polyimine (PI). The wafer package structure according to claim 374, wherein the material of the polymer layer material comprises phenylcyclobutane (BCB). 446. The wafer package structure of claim 374, wherein the polymer material has a thickness between 250 micrometers and 1,000 micrometers. 447. The wafer of claim 374. The package structure, wherein the wire is electrically connected to the lead-free solder ball through a metal line of the substrate. 448. The wafer package structure of claim 374, wherein the position of the wire bonding the gold layer is different from the position of the pad from a top perspective view. The wafer package structure of claim 374, further comprising a polymer layer on the protective layer, and one of the polymer layer openings in the polymer layer exposing the pad The metal line is on the polymer layer and is connected to the pad through the polymer layer opening. The wafer package structure of claim 449, wherein the material of the polymer layer comprises polyimine (PI). 451. The wafer package structure of claim 449, wherein the material of the polymer layer comprises epoxy. 452. The wafer package structure of claim 449, wherein the polymer layer comprises phenylcyclobutene (BCB). 453. The wafer package structure of claim 449, wherein the polymer layer has a thickness between 3 microns and 25 microns. 454. The chip package structure of claim 374, further comprising a polymer layer on the metal line, and a polymer layer opening in the polymer layer exposing the gold layer, A wire conductor engages the gold layer through the polymer layer opening. 455. The wafer package structure of claim 454, wherein the material of the polymer layer comprises polyimine (PI). 456. The wafer package structure of claim 454, wherein the material of the polymer layer comprises epoxy. 457. The wafer package structure of claim 454, wherein the material of the polymer layer comprises phenylcyclobutene (BCB). 458. The wafer package structure of claim 454, wherein the polymer layer has a thickness between 3 microns and 25 microns. 124 200814213 459. A wafer package structure comprising: a substrate; a lead-free solder ball bonded to the substrate; an adhesive material positioned on the substrate; and a semiconductor wafer positioned on the adhesive material And the semiconductor wafer includes a wire bonding node; a wire bonding wire bonding the wire bonding node and the substrate; and a polymer material disposed on the substrate and covering the semiconductor wafer and the wire bonding wire. 460. The wafer package structure of claim 459, wherein the substrate is a ball grid array (BGA) substrate. 461. The wafer package structure of claim 459, wherein the substrate is a substrate comprising glass fibers and an epoxy resin. 462. The wafer package structure of claim 459, wherein the substrate is a glass substrate. 463. The wafer package structure of claim 459, wherein the substrate is a germanium substrate. 464. The wafer package structure of claim 459, wherein the substrate is a ceramic substrate. 465. The wafer package structure of claim 459, wherein the substrate is an organic substrate. 466. The chip package structure of claim 459, wherein the substrate is a metal substrate. 467. The chip package structure of claim 459, wherein 125 200814213 the substrate is a metal substrate, and the material of the metal substrate comprises aluminum. 468. The chip package structure of claim 459, wherein the substrate is a metal substrate, and the material of the metal substrate comprises copper. 469. The wafer package structure of claim 459, wherein the substrate has a thickness between 200 microns and 2,000 microns. 470. The chip package structure of claim 459, wherein the substrate comprises a first surface and a second surface, and the adhesive material and the polymer material are on the first surface, the lead-free tin The ball is on the second surface. 471. The chip package structure of claim 459, wherein the material of the error-free solder ball comprises a tin-silver alloy. 472. The chip package structure of claim 459, wherein the material of the ruling ball comprises a tin-silver-copper alloy 473, as described in claim 459. a chip package structure in which the diameter of the lead-free solder ball is between (K25 cm and 1. Between 2 cm (mm). 474. The wafer package structure of claim 459, wherein the thickness of the adhesive material is between 1 micrometer and 50 micrometers. 475. The wafer package structure of claim 459, wherein the material of the adhesive material comprises a polymer material. 476. The chip package structure of claim 459, wherein the material of the adhesive material comprises polyimide (PI). 477. The chip package structure of claim 459, wherein the material of the adhesive material comprises an epoxy resin. The wafer package structure of claim 459, wherein the semiconductor wafer further comprises: a semiconductor substrate; a wiring structure located above the semiconductor substrate; and a protective layer located in the circuit structure Above, and one of the openings in the protective layer exposes one of the pads of the line structure. 479. The wafer package structure of claim 478, wherein the semiconductor substrate comprises germanium. 480. The wafer package structure of claim 476, wherein the semiconductor substrate is on the adhesive material. 481. The chip package structure of claim 478, further comprising at least one metal oxide semiconductor (MOS) device positioned in or on the semiconductor substrate. 482. The wafer package structure of claim 478, wherein the wiring structure comprises a copper layer having a thickness between 0 and 2 microns to 2 microns. 483. The wafer package structure of claim 478, wherein the wiring structure comprises electroplated copper. 484. The chip package structure of claim 478, wherein the line structure comprises a thickness of 0. An aluminum-containing metal layer between 2 microns and 2 microns. 485. The chip package structure of claim 478, further comprising a plurality of dielectric layers between the semiconductor substrate and the protective layer, and the plurality of patterned metal layers of the line structure are in the dielectric Between the layers, the plurality of metal plugs of the line structure disposed in the dielectric layers are connected to the patterned metal layers of the adjacent layers of 127 200814213. 486. The chip package structure of claim 485, wherein the dielectric constants (k) of the dielectric layers are between 1. Between 5 and 3. 487. The chip package structure of claim 485, wherein the material of the dielectric layer comprises an oxonium compound. 488. The wafer package structure of claim 485, wherein the material of the dielectric layer comprises nitrogen; 489. The chip package structure of claim 485, wherein the material of the dielectric layer comprises a oxynitride compound. 490. The chip package structure of claim 485, wherein the material of the dielectric layer comprises a compound containing ruthenium, carbon, oxygen and ruthenium. 491. The chip package structure of claim 485, wherein the material of the dielectric layer comprises Fluorinated Silicate Glass 492, the chip package structure as described in claim 485. , wherein the thickness of the dielectric layer is between 0. 3 microns to 2. Between 5 microns. 493. The wafer package structure of claim 476, wherein the protective layer comprises an oxonium compound. 494. The wafer package structure of claim 476, wherein the protective layer comprises a nitrogen compound. 495. The wafer package structure of claim 476, wherein the protective layer comprises a oxynitride compound. 496. The chip package structure of claim 478, wherein the thickness of the protective layer is between 0. 3 microns to 1. Between 5 microns (//m). The chip package structure of claim 1, wherein the pad comprises a thickness of between 〇. a steel layer between 2 microns and 2 microns. The wafer package structure as described in the above claims, wherein the pad comprises a thickness of 〇. An aluminum alloy layer between 2 microns and 2 microns. 499. The chip package junction of claim 478, wherein the wire bonding contact is located on the pad. 500. The chip package structure of claim 478, wherein the wire bonding contact is located above the protective layer. 501. The chip package structure of claim 478, further comprising a protective cover on the interface, and the wire contact is located on the metal cover. " 502 曰, as claimed in the patent scope, the chip package structure, including the thickness w S G. A layer of metal containing between 4 micrometers and 2 micrometers is on the interface exposed by the opening, and the bonding terminal is on the metal layer containing the metal. 503. The chip package structure of claim 1, further comprising a titanium-containing metal layer having a thickness between 0. 01 micrometers and 〇 7 micrometers on the pad exposed by the opening. And the thickness is between G. An aluminum-containing metal layer between 4 microns and 2 microns is on the barrier layer, and the wire bonding contacts are on the aluminum-containing metal layer. 〇4^ The wafer package structure described in claim 478 of the patent application, further comprising a chrome layer of s + '1 between 微米1 μm and 〇·7 μm on the pad exiting the opening, And a metal layer having a thickness of between 4 micrometers and 2 micrometers is on the chromium layer, and the wire bonding contacts are on the metal layer containing 129 200814213. 505. The chip package structure as described in claim 478, further comprising a thickness of 0. 01 micron to 0. A layer of germanium containing metal between 7 microns is on the pad exposed by the opening, and has a thickness of 0. An aluminum-containing metal layer between 4 micrometers and 2 micrometers is on the germanium-containing metal layer, and the wire bonding contacts are on the aluminum-containing metal layer. 506. The chip package structure of claim 478, further comprising a metal line above the protective layer, and connecting the pad through the opening, and the wire contact is one of the metal lines. Share. 507. The chip package structure of claim 506, wherein the metal line material comprises gold. 508. The chip package structure of claim 506, wherein the material of the metal line comprises copper. 509. The chip package structure of claim 506, wherein the metal line material comprises nickel. 510. The chip package structure of claim 506, wherein the material of the metal line comprises palladium. 511. The chip package structure of claim 459, wherein the wire bonding contact comprises a gold layer, and the wire bonding wire joins the gold layer. 512. The chip package structure of claim 459, wherein the wire bonding contact comprises a palladium layer, and the wire bonding wire bonds the palladium layer. 513. The chip package structure of claim 459, wherein the wire bonding contact comprises an adhesion/barrier layer, a sub-layer on the adhesion/barrier layer, and a metal layer on the seed layer. on. 130 200814213 514. The wafer package of claim 513, wherein the material of the adhesive/barrier layer comprises titanium. /, 515, as claimed in claim 513, the material of the adhesive/barrier layer comprises a titanium-tungsten alloy. 516. The chip package structure of claim 513, wherein the material of the adhesion/barrier layer comprises titanium nitride. 517. The chip package structure of claim 513, wherein the material of the adhesion/barrier layer comprises chromium. The chip package structure of claim 513, wherein the material of the adhesion/barrier layer comprises ruthenium. 519. The wafer package structure of claim 513, wherein the material of the adhesion/barrier layer in the basin comprises a nitride button. ', 52 〇, #, as claimed in claim 513, wherein the thickness of the adhesion/barrier layer is between 〇〇3 μm and 7·7 μm, 521, as claimed The wafer sealing structure of item 513, wherein the seed layer has a thickness of 0. 03 microns to 0. Between 7 microns. 522. The chip package structure of claim 513, wherein the seed layer is made of gold and the metal layer is made of gold. 523. The chip package structure of claim 513, wherein the seed layer is made of copper, and the metal layer comprises a steel layer on the seed layer, a nickel layer on the copper layer, and A gold layer is on the nickel layer, and the wire bonding wire bonds the gold layer. The chip package structure of claim 513, wherein the seed layer is made of copper, and the metal layer comprises a copper layer on the seed layer 131 200814213, and a nickel layer on the copper layer. A palladium layer is on the layer and the palladium layer is bonded to the palladium layer. 525. The wafer package structure of claim 513, wherein the metal layer has a thickness of between 1 micrometer and 20 micrometers. 526. The wafer package structure of claim 513, wherein the metal layer has a thickness between 3 microns and 5 microns. 527. The chip package structure of claim 459, wherein the wire bonding contact has a thickness between 1 micrometer and 20 micrometers. 528. The chip package structure of claim 459, wherein the wire bonding contact has a thickness of between 3 micrometers and 5 micrometers. 529. The chip package structure of claim 459, wherein the wire bonding material comprises gold. 530. The wafer package structure of claim 459, wherein the wire bonding wire has a diameter of between 20 micrometers and 50 micrometers. 531. The wafer package structure of claim 459, wherein the material of the polymer material comprises epoxy. 532. The chip package structure of claim 459, wherein the material of the polymer material comprises polyimine (PI). 533. The wafer package structure of claim 459, wherein the material of the polymer layer material comprises phenylcyclobutene (BCB). 534. The wafer package structure of claim 459, wherein the polymer material has a thickness between 250 micrometers and 1,000 micrometers. 535. The chip package structure of claim 459, wherein the wire bonding wire is electrically connected to the lead-free tin 132 200814213 ball through a metal line of the substrate. 536. A chip package structure, comprising: a lead frame, comprising a wafer carrier and a pin; an adhesive material disposed on the wafer carrier; a semiconductor wafer positioned on the adhesive material And the semiconductor wafer comprises: a semiconductor substrate; a wiring structure positioned above the semiconductor substrate; a germanium layer positioned above the wiring structure, and one of the openings in the protective layer exposing one of the wiring structures a pad; and a wire bonding pad comprising an adhesive/barrier layer and a metal layer on the bonding/barrier layer, wherein the adhesion/barrier layer is on the pad exposed by the opening, and The metal layer includes a gold layer; a wire bonding wire bonding the gold layer and the pin; and a polymer material covering the wafer carrier, the semiconductor wafer, the wire bonding wire and a portion of the pin. 537. The chip package structure of claim 536, wherein the lead frame is made of copper. 538. The wafer-clad structure of claim 536, wherein the leadframe has a thickness between 1 Å and 2,000 microns. 539. The wafer package structure of claim 536, wherein the adhesive material has a thickness between 1 micrometer and 50 micrometers. 540. The chip package structure of claim 536, wherein the material of the adhesive material comprises a polymer material. 133. The chip package structure of claim 536, wherein the material of the adhesive material comprises polyimide (PI). 542. The chip package structure of claim 536, wherein the material of the adhesive material comprises an epoxy resin. 543. The wafer package structure of claim 536, wherein the semiconductor substrate comprises a dream. 544. The wafer package structure of claim 536, wherein the semiconductor substrate is on the adhesive material. 545. The chip package structure of claim 536, further comprising at least one metal oxide semiconductor (MOS) device positioned in or on the semiconductor substrate. 546. The chip package structure of claim 536, wherein the line structure comprises a thickness of 0. A copper layer between 2 microns and 2 microns. 547. The wafer package structure of claim 536, wherein the wiring structure comprises electroplated copper. 548. The chip package structure of claim 536, wherein the line structure comprises a thickness of 0. An aluminum-containing metal layer between 2 microns and 2 microns. 549. The chip package structure of claim 536, further comprising a plurality of dielectric layers between the semiconductor substrate and the protective layer, and wherein the plurality of patterned metal layers of the line structure are in the dielectric Between the layers, the patterned metal layers of the adjacent two layers are connected by a plurality of metal plugs of the line structure located in the dielectric layers. 550. The chip package structure of claim 549, wherein the dielectric constant value (k) of the dielectric layers is 1. Between 5 and 3. 551. The chip package structure of claim 549, wherein the material of the dielectric layer comprises an oxonium compound. 552. The chip package structure of claim 549, wherein the material of the dielectric layer comprises a nitrogen cerium compound. 553. The chip package structure of claim 549, wherein the material of the dielectric layer comprises a oxynitride compound. 554. The chip package structure of claim 549, wherein the material of the dielectric layer comprises a compound containing ruthenium, carbon, oxygen and hydrogen. 555. The chip package structure of claim 549, wherein the material of the dielectric layer comprises a Fluorinated Silicate Glass 556, the chip package structure as described in claim 549 , wherein the thickness of the dielectric layer is between 0. 3 microns to 2. Between 5 microns. 557. The wafer package structure of claim 536, wherein the protective layer comprises an oxonium compound. 558. The wafer package structure of claim 536, wherein the protective layer comprises a Nitrogen compound. 559. The wafer package structure of claim 536, wherein the protective layer comprises a oxynitride compound. 560. The chip package structure of claim 536, wherein the thickness of the protective layer is between 微米3 micrometers and 1. Between 5 microns (//m). 561. The chip package structure of claim 536, wherein the thickness of the pad is between 0. Between 2 microns and 2 microns. </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> <RTIgt; </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> <RTIgt; On the aluminum alloy layer. 563. The chip package structure of claim 536, wherein the material of the adhesion/barrier layer comprises titanium. 564. The wafer sealing structure of claim 536, wherein the material of the adhesion/barrier layer comprises a titanium-tungsten alloy. The chip package structure of claim 536, wherein the material of the adhesion/barrier layer comprises titanium nitride. 562. The chip package structure of claim 536, wherein the material of the adhesion/barrier layer comprises chromium. 567. The wafer package structure of claim 536, wherein the material of the adhesion/barrier layer comprises a button. 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 569. The wafer sealing structure of claim 536, wherein the thickness of the adhesive/barrier layer is between 〇〇3 micrometers and 〇7 micrometers, 570, as claimed in the patent application. In the chip package structure, the metal layer in the basin further comprises a gold-based seed layer on the adhesion/barrier layer and the gold layer is on the seed layer. The chip package structure of claim 536, wherein the metal layer further comprises a copper-based seed layer on the adhesion/barrier layer, a copper layer on the seed layer, and A layer of nickel is on the copper layer and the gold layer is on the layer of nickel. 136. The chip package structure of claim 536, wherein the gold layer has a thickness between 1 micrometer and 20 micrometers. 573. The wafer package structure of claim 536, wherein the gold layer has a thickness between 3 microns and 5 microns. 574. The chip package structure of claim 536, wherein the wire bonding pad has a thickness of between 1 micrometer and 20 micrometers. 575. The chip package structure of claim 536, wherein the wire bonding pad has a thickness of between 3 micrometers and 5 micrometers. 576. The chip package structure of claim 536, wherein the wire bonding material comprises gold. 577. The chip package structure of claim 536, wherein the wire bonding wire has a diameter of between 20 micrometers and 50 micrometers. 578. The chip package structure of claim 536, wherein the material of the polymer material comprises epoxy. 579. The chip package structure of claim 536, wherein the material of the polymer material comprises polyimine (PI). 580. The wafer package structure of claim 536, wherein the material of the polymer layer material comprises phenylcyclobutene (BCB). 581. The wafer package structure of claim 536, wherein the polymer material has a thickness between 250 microns and 1,000 microns. 582. A chip package structure comprising: a lead frame including a wafer carrier and a pin; an adhesive material disposed on the wafer carrier; and a semiconductor wafer positioned on the adhesive material And the semiconductor wafer package 137 200814213 comprises: a semiconductor substrate; a wiring structure positioned above the semiconductor substrate; a protective layer positioned over the wiring structure, and an opening in the protective layer exposing the wiring a copper pad of the structure; and a wire bonding pad comprising an adhesive/barrier layer and a metal layer on the adhesion/barrier layer, wherein the adhesion/barrier layer is exposed to the copper at the opening a pad, and the metal layer comprises a gold layer; a wire bonding wire bonding the gold layer and the pin; and a polymer material covering the wafer carrier, the semiconductor wafer, the wire bonding wire and the portion of the wire foot. 583. The chip package structure of claim 582, wherein the lead frame is made of copper. 584. The wafer package structure of claim 582, wherein the leadframe has a thickness between 100 microns and 2,000 microns. 585. The wafer package structure of claim 582, wherein the adhesive material has a thickness between 1 micrometer and 50 micrometers. 586. The chip package structure of claim 582, wherein the material of the adhesive material comprises a polymer material. 587. The wafer package structure of claim 582, wherein the adhesive material comprises polyimide (PI). 588. The chip package structure of claim 582, wherein the material of the adhesive material comprises an epoxy resin. 598. The wafer package structure of claim 582, wherein 138 200814213 the semiconductor substrate comprises germanium. 590. The wafer package structure of claim 582, wherein the semiconductor substrate is on the adhesive material. 591. The chip package structure of claim 582, further comprising at least one metal oxide semiconductor (MOS) device positioned in or on the semiconductor substrate. 592. The chip package structure of claim 582, wherein the line structure comprises a thickness of 0. A copper layer between 2 microns and 2 microns. 593. The wafer package structure of claim 582, wherein the wiring structure comprises electroplated copper. 594. The chip package structure of claim 582, further comprising a plurality of dielectric layers between the semiconductor substrate and the protective layer, and wherein the plurality of patterned metal layers of the line structure are in the dielectric Between the layers, the patterned metal layers of the adjacent two layers are connected by a plurality of metal plugs of the line structure located in the dielectric layers. 595. The chip package structure of claim 594, wherein the dielectric constants (k) of the dielectric layers are between 1. Between 5 and 3. 596. The chip package structure of claim 594, wherein the material of the dielectric layer comprises an oxonium compound. 597. The chip package structure of claim 594, wherein the material of the dielectric layer comprises a nitrogen bismuth compound. 598. The chip package structure of claim 594, wherein the material of the dielectric layer comprises a oxynitride compound. 599. The wafer package structure of claim 594, wherein the material of the two η electrical layer comprises a compound containing a mixture of carbon, oxygen and hydrogen. The chip package structure of claim 594, wherein the material of the dielectric layer comprises fluorocarbon glass (Flu〇rinated sme'ate Glass) 601, as described in claim 594 In the chip package structure, the thickness of the dielectric layers is between 微米·3 μm and 2. Between 5 microns. 602. The wafer package structure of claim 582, wherein the protective layer comprises an oxygen stone compound. 603. The wafer package structure of claim 582, wherein the protective layer comprises a Nitrogen compound. 604. The wafer package structure of claim 582, wherein the protective layer comprises a oxynitride compound. 605. The wafer package structure of claim 582, wherein the protective layer has a thickness between 〇3 μm and h5 μm (for melon). 606. The chip package structure of claim 582, wherein the thickness of the copper beryllium is between 0. Between 2 microns and 2 microns. 607. The chip package structure of claim 582, wherein the material of the adhesion/barrier layer comprises titanium. The chip package structure of claim 582, wherein the material of the adhesion/barrier layer comprises a titanium tungsten alloy. 609. The chip package structure of claim 582, wherein the material of the adhesion/barrier layer comprises titanium nitride. _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ The material of the adhesive/barrier layer includes a button. The chip package structure of the invention of claim 582, wherein the material of the adhesive/barrier layer comprises a nitride button. 613. For example, the patent application _ 5 8 2 The chip package structure of the present invention, wherein the thickness of the adhesion/barrier layer is between 微米·〇3 μm and 〇·7 μm. 614. The chip package structure of claim 582, wherein The metal layer further includes a gold-based seed layer on the adhesion/barrier layer and the gold layer is on the seed layer. 615. The wafer package structure of claim 582, The metal layer further includes a copper-based seed layer on the adhesion/barrier layer, a copper layer on the seed layer, and a nickel layer on the copper layer, and the gold layer is located thereon. On the recording layer. 616, such as the scope of patent application The chip package structure of claim 582, wherein the thickness of the gold layer is between 1 micrometer and 2 micrometers. 617. The wafer package structure of claim 582, wherein the thickness of the gold layer is 618. The chip package structure of claim 582, wherein the wire bonding pad has a thickness of between 1 micrometer and 20 micrometers. 619. The chip package structure of the invention, wherein the wire bonding pad has a thickness of between 3 micrometers and 5 micrometers. 620. The chip package structure of claim 582, wherein the wire bonding wire 621. The chip package structure of claim 582, wherein 141 200814213 has a diameter of between 20 micrometers and 50 micrometers. 622, as described in claim 582. The chip package structure, wherein the material of the polymer material comprises an epoxy resin. The chip package structure according to claim 582, wherein the polymer material is The material includes a polyacrylonitrile (PI). The chip package structure of claim 582, wherein the material of the polymer layer material comprises phenylcyclobutene (BCB). 625. The chip package structure of claim 582, wherein the polymer material has a thickness of between 250 micrometers and 1,000 micrometers. 626. A chip package structure comprising: a lead frame comprising a wafer carrier and a pin An adhesive material is disposed on the wafer carrier; a semiconductor wafer 'on the adhesive material' and the semiconductor wafer includes: a semiconductor substrate; a wiring structure positioned above the semiconductor substrate; a protective layer, Positioned above the line structure, and one opening in the protective layer exposes one of the wiring structures; and a wire bonding pad including an adhesive/barrier layer and a metal layer in the adhesion/resistance a barrier layer, wherein the adhesion/barrier layer is on the pad exposed by the opening, and the metal layer comprises a palladium layer; a wire bonding wire bonding the palladium layer and the pin; A polymeric material, covering the wafer carrier base, the semiconductor chip, the bonding wires and part of the pin. 142. The chip package structure of claim 626, wherein the lead frame is made of copper. 628. The wafer package structure of claim 626, wherein the leadframe has a thickness between 100 microns and 2,000 microns. 629. The wafer package structure of claim 626, wherein the thickness of the adhesive material is between 1 micrometer and 50 micrometers. 630. The chip package structure of claim 626, wherein the material of the adhesive material comprises a polymer material. 631. The chip package structure of claim 626, wherein the material of the adhesive material comprises polyimide (PI). 632. The chip package structure of claim 626, wherein the material of the adhesive material comprises an epoxy resin. 633. The wafer package structure of claim 626, wherein the semiconductor substrate comprises germanium. 634. The wafer package structure of claim 626, wherein the semiconductor substrate is on the adhesive material. 635. The chip package structure of claim 626, further comprising at least one metal oxide semiconductor (MOS) device positioned in or on the semiconductor substrate. 636. The chip package structure of claim 626, wherein the line structure comprises a thickness of 0. A copper layer between 2 microns and 2 microns. 637. The wafer package structure of claim 626, wherein the wiring structure comprises electroplated copper. 638. The chip package structure of claim 626, wherein 143 200814213 the line structure comprises a thickness of 0. An aluminum-containing metal layer between 2 microns and 2 microns. 639. The chip package structure of claim 626, further comprising a plurality of dielectric layers between the semiconductor substrate and the protective layer, and the plurality of patterned metal layers of the line structure are in the dielectric Between the layers, the patterned metal layers of the adjacent two layers are connected by a plurality of metal plugs of the line structure located in the dielectric layers. 640. The chip package structure of claim 639, wherein the dielectric constants (k) of the dielectric layers are between 1. Between 5 and 3. 641. The chip package structure of claim 639, wherein the material of the dielectric layer comprises an oxonium compound. 642. The chip package structure of claim 639, wherein the material of the dielectric layer comprises a nitrogen cerium compound. 643. The chip package structure of claim 639, wherein the material of the dielectric layer comprises a oxynitride compound. The chip package structure of claim 639, wherein the material of the dielectric layer comprises a compound containing ruthenium, carbon, oxygen and hydrogen. 645. The chip package structure of claim 639, wherein the material of the dielectric layer comprises Fluorinated Silicate Glass 646, the chip package according to claim 639 The structure, wherein the thickness of the dielectric layers is between 0. 3 microns to 2. Between 5 microns. 647. The wafer package structure of claim 626, wherein the protective layer comprises an oxygen stone compound. The wafer package structure of claim 626, wherein the protective layer comprises a Nitrogen compound. 649. The wafer package structure of claim 626, wherein the protective layer comprises a oxynitride compound. 650. The wafer package structure of claim 626, wherein the thickness of the protective layer is between 微米3 micrometers and 1.5 micrometers (referred to as 651, as described in claim 626) The chip package structure, wherein the thickness of the pad is between 微米·2 μm and 2 μm. 652、 如申請專利範圍第項所述之晶片封裝結構，其中 該接墊包括厚度介於〇·2微米至2微米 〈間的一鋁合金 層’且該黏著/阻障層位在該鋁合金層上。 653、 *申請專利範圍第㈣項所述之晶片封裝結構，盆中 該黏著/阻障層的材質包括鈦。 、 654、—如申請專利範圍第心項所述之晶片封裝結構， 該黏著/阻障層的材質包括鈦鎢合金。 封裝結構，其中 封裝結構，其中 封裝結構，其中 封裝結構，其中 655、 如申請專利範圍第626項所述之晶片 該黏著/阻障層的材質包括氮化鈦。 656、 如申請專利範圍第626項所述之晶片 該黏著/阻障層的材質包括鉻。 657、 如申請專利範圍第626項所述之晶片 該黏著/阻障層的材質包括鈕。 658、 如申請專利範圍第6%項所述之晶片 該黏著/阻障層的材質包括氮化鈕。 659、 如申請專利範圍第626項所述之晶片 封裝結構，其中 145 200814213 該黏著/阻障層的厚度係介於0.03微米至0.7微米之間。 _、如申請專利範圍第_項所述之晶片封裝結構，盆中 該金屬層更包括材質為銅的一種子層位在該黏著/阻障層 上、一鋼層位在該種子層上以及一鎳層位在該銅層上，且 該鈀層位在該鎳層上。 661、 如申請專利範圍第似項所述之晶片封裝結構，其中 該把層的厚度係介於1微米至20微米之間。 662、 如申請專利範圍第626項所述之晶片封裝結構，其中 該把層的厚度係介於3微米至5微米之間。 663、 如申請專利範圍第626項所述之晶片封裝結構，其中 該打線接墊的厚度係介於丨微米至2〇微米之間。 664、 如申請專利範圍第626項所述之晶片封裳結構，其中 該打線接墊的厚度係介於3微米至5微米之間。 665、 如申請專利範圍第626項所述之晶片封裝結構，其中 該打線導線的材質包括金。 666、 如申請專利範圍第626項所述之晶片封裝結構，其中 該打線導線的直徑介於20微米至50微米之間。 667、 如申請專利範圍第626項所述之晶片封裝結構，其中 該聚合物材料的材質包括環氧樹脂（epoxy)。 668、 如申請專利範圍第626項所述之晶片封裝結構，其中 該聚合物材料的材質包括聚醯亞胺（PI)。 669、 如申請專利範圍第626項所述之晶片封裝奸構，其中 該聚合物層材料的材質包括苯基環丁烯。 670、 如申請專利範圍第626項所述之晶片封裝、社構，其中 146 200814213 該聚合物材料的厚度係介於250微来至_〇微米之間。 671、一種晶片封裝結構，包括·· 一導線架，包括一晶片承載座與一引腳； 一黏著材料，位在該晶片承载座上，· -半導體晶片，位在該黏著材料上，且該半導體晶片包 括： 一半導體基底； 一線路結構，位在該半導體基底上方； 保濩層，位在該線路結構上方，且位在該保護層 内之一開口暴露出該線路結構之一銅墊；以及 一打線接墊，包括一黏著/阻障層與一金屬層位在該 黏著/阻障層上，其中該黏著/阻障層位在該開口所暴 露出之該銅墊上，且該金屬層包括一鈀層； 一打線導線，接合該鈀層與該引腳；以及 一聚合物材料，包覆該晶片承載座、該半導體晶片、該 打線導線與部份之該引腳。 μ 672、 如申請專利範圍第671項所述之晶片封裝結構，其中 該導線架的材質包括銅。 673、 如申請專利範圍第671項所述之晶片封裝結構，其中 該導線架的厚度係介於1〇〇微米至2,〇〇〇微米之間。 674 ^如申請專利範圍第671項所述之晶片封裳結構，其中 該黏著材料的厚度係介於1微米至50微米之間。 675、如申請專利範圍第671項所述之晶片封袭結構，其中 該黏著材料的材質包括聚合物材料。 147 200814213 676、 如申請專利範圍第671項所述之晶片封裝結構，其中 該黏著材料的材質包括聚醯亞胺（polyimide，pij。 677、 如申請專利範圍第671項所述之晶片封裝結構，其中 該黏著材料的材質包括環氧樹脂（ep0Xy resin)。 678、 如申請專利範圍第671項所述之晶片封裳結構，其中 該半導體基底包括碎。 679、 如申請專利範圍第671項所述之晶片封裳結構，其中 該半導體基底位在該黏著材料上。652. The chip package structure of claim 1, wherein the pad comprises an aluminum alloy layer having a thickness between 22 μm and 2 μm and the adhesion/barrier layer is on the aluminum alloy. On the floor. 653. The wafer package structure described in claim 4, wherein the material of the adhesion/barrier layer in the basin comprises titanium. 654. The material of the adhesive/barrier layer comprises a titanium-tungsten alloy, as described in the patent application. The package structure, wherein the package structure, wherein the package structure, wherein the package structure, wherein 655, the wafer of claim 626, the material of the adhesion/barrier layer comprises titanium nitride. 656. The wafer of claim 626, wherein the material of the adhesion/barrier layer comprises chromium. 657. The wafer of claim 626, wherein the material of the adhesive/barrier layer comprises a button. 658. The wafer of claim 6%, wherein the material of the adhesion/barrier layer comprises a nitride button. 659. The wafer package structure of claim 626, wherein 145 200814213 has an adhesion/barrier layer thickness between 0.03 micrometers and 0.7 micrometers. The wafer package structure of claim _, wherein the metal layer further comprises a sub-layer of copper on the adhesion/barrier layer, a steel layer on the seed layer, and A layer of nickel is on the copper layer and the palladium layer is on the layer of nickel. 661. The wafer package structure of claim 1, wherein the layer has a thickness between 1 micrometer and 20 micrometers. 662. The wafer package structure of claim 626, wherein the layer has a thickness between 3 microns and 5 microns. 663. The chip package structure of claim 626, wherein the wire bonding pad has a thickness of between 丨micrometers and 2 micrometers. 664. The wafer sealing structure of claim 626, wherein the wire bonding pad has a thickness of between 3 micrometers and 5 micrometers. 665. The chip package structure of claim 626, wherein the wire bonding material comprises gold. 666. The wafer package structure of claim 626, wherein the wire bonding wire has a diameter of between 20 micrometers and 50 micrometers. 667. The wafer package structure of claim 626, wherein the material of the polymer material comprises epoxy. 668. The wafer package structure of claim 626, wherein the material of the polymer material comprises polyimine (PI). 669. The wafer package of claim 626, wherein the material of the polymer layer material comprises phenylcyclobutene. 670. The wafer package and the structure of claim 626, wherein the thickness of the polymer material is between 250 micrometers and _micrometers. 671. A chip package structure comprising: a lead frame comprising a wafer carrier and a pin; an adhesive material disposed on the wafer carrier, a semiconductor wafer positioned on the adhesive material, and The semiconductor wafer comprises: a semiconductor substrate; a wiring structure positioned above the semiconductor substrate; a protection layer positioned above the wiring structure, and an opening in the protective layer exposing a copper pad of the wiring structure; And a wire bonding pad comprising an adhesive/barrier layer and a metal layer on the adhesion/barrier layer, wherein the adhesion/barrier layer is on the copper pad exposed by the opening, and the metal layer A palladium layer is included; a wire bonding wire bonding the palladium layer and the pin; and a polymer material covering the wafer carrier, the semiconductor wafer, the wire bonding wire and a portion of the pin. The chip package structure of claim 671, wherein the lead frame is made of copper. 673. The wafer package structure of claim 671, wherein the leadframe has a thickness of between 1 micron and 2 micrometers. 674. The wafer sealing structure of claim 671, wherein the thickness of the adhesive material is between 1 micrometer and 50 micrometers. 675. The wafer encapsulation structure of claim 671, wherein the material of the adhesive material comprises a polymer material. 147. The wafer package structure of claim 671, wherein the material of the adhesive material comprises a polyimide (pij. 677, the wafer package structure as described in claim 671, The material of the adhesive material comprises an epoxy resin (ep0Xy resin). The wafer sealing structure of claim 671, wherein the semiconductor substrate comprises a chip. 679, as described in claim 671 The wafer sealing structure, wherein the semiconductor substrate is on the adhesive material. 680、 如申請專利範圍第671項所述之晶片封裝結構，更勺 括至少一金氧半導體（MOS)元件位在該半導體基底内或= 681、如申請專利範圍第671項所述之晶片封裝結構，其中 該線路結構包括厚度介於0.2微米至2微米之門 日]的一銅層。 、申請專利範圍第671項所述之晶片封裝結構， 該線路結構包括電鍵銅。 683 、如申請專利範圍第671項所述之晶片封震結構，更包 括複數介電層位在該半導體基底與該保護層之間，= 路、構之複數圖案化金屬層位在該些介電層之門，、、1、 位在該些介電相_線路結構之複數金屬 == 兩層之該些圖案化金屬層。 連接相卻 684、如申請專利範圍第683項所述之晶片封 該些介電層的介電常數值（k)係介於1.5至3 、 其中 =、如巾料利_第683項所狀晶片封 該些介電層的材質包括氧矽化合物。 稱”中 148 200814213 686、 如申請專利範圍第683項所述之晶片封裝結構，其中 該些介電層的材質包括氮矽化合物。 687、 如申請專利範圍第683項所述之晶片封裴結構，其中 該些介電層的材質包括氮氧矽化合物。 〃 688、 如申請專利範圍第683項所述之晶片封裝結構，其中 該些介電層的材質包括含矽、碳、氧與氫之化合物。 689、 如申請專利範圍第683項所述之晶片封襄結構其中 該些介電層的材質包括氟矽玻璃(Flu〇rinated sm⑽ Glass)。 69〇、如申請專利範圍第683項所述之晶片封裝結構其中 該些介電層的厚度係介於0.3微米至2.5微米之間。 691、 如申請專利範圍第671項所述之晶片封裝結構，其中 該保護層包括氧矽化合物。 692、 ▲如申請專利範圍第671項所述之晶片封裂結構，其中 該保護層包括氮矽化合物。 693 ^如申請專利範圍第671項所述之晶片封裝結構其中 該保護層包括氮氧矽化合物。 如申請專利範圍第671項所述之晶片封裝結構其中 該保護層的厚度係介於〇.3微米至1.5微米之門。 6%、如申請專利範圍第671項所述之晶片封裝結構其中 該銅墊的厚度係介於〇·2微米至2微米之間。 696、 从如申請專利範圍第671項所述之晶片封裝結構， 該黏著/阻障層的材質包括鈦。 697、 如申請專利範圍第671項所述之晶片封裝結構其中 149 200814213 該黏著/阻障層的材質包括鈦鎢合金。 6卯、如申請專利範圍第671項所述之晶片 該黏著/阻障層的材質包括氮化鈦。 ^構’其中 69\如中請專利範圍第671項所述之晶片封裝結構其中 該黏著/阻障層的材質包括鉻。 7〇〇、如申請專利範圍第671項所述之晶片封裳結構， 該黏著/阻障層的材質包括鉉。 八 701、如申請專利範圍第671項所述之晶片封 該黏著/阻障層的材質包括氮化鈕。 、、 702二如申請專利範圍第671項所述之晶片封裝結構，其中 該黏著/阻障層的厚度係介於0.03微米至〇·7微米 703、如中請專利範圍第671項所述之晶片封裝結構門其中 該金屬層更包括材質為銅的一種子層位在該點著/阻障層 上、一銅層位在該種子層上以及一鎳層位在該鋼層上，I 該鈀層位在該鎳層上。 剔、#中請專利範圍第671項所述之晶片封裝結構，其中 y 該把層的厚度係介於1微米至20微米之間。 705、 如申請專職圍第671項所述之晶片封震結構，其中 該把層的厚度係介於3微米至5微米之間。 706、 如申請專利範圍第671項所述之晶片封裳結構，其中 該打線接墊的厚度係介於1微米至20微米之間。 707、 如申請專利範圍第671項所述之晶片封裝結構，其中 該打線接墊的厚度係介於3微米至5微米之間。 708、 如申請專利範圍第671項所述之晶片封裝結構，其中 150 200814213 該打線導線的材質包括金。 709、 如申請專利範圍第671項所述之晶片封裝結構其中 該打線導線的直徑介於20微米至50微米之間。 710、 ”請專利範圍第671項所述之晶片封裝結構，其中 該聚合物材料的材質包括環氧樹脂（ep〇xy)。 、 71卜如申請專利範圍第671項所述之晶片封裝結構，其中 該聚合物材料的材質包括聚醯亞胺（pj)。 712、 ”請專利範圍第671項所述之晶片封裝結構，其中 該聚合物層材料的材質包括苯基環丁烯(BCb)。 713、 如申請專利範圍第671項所述之晶片封裝結構，其中 該聚合物材料的厚度係介於250微米至丨…㈧微米之間。 714、 一種晶片封装結構，包括·· 一導線架，包括一晶片承載座與一引腳； 一黏著材料，位在該晶片承載座上； -半導體晶片，位在該黏著材料上，且該半導體晶片包 括： ^ 一半導體基底； 一線路結構，位在該半導體基底上方； 一保護層，位在該線路結構上方，且位在該保護層 内之一開口暴露出該線路結構之一銅墊； 一金屬保護蓋，位在該開口所暴露出之該銅墊上； 以及 一打線接墊，包括一黏著/阻障層與一金屬層位在該 黏著/阻障層上，其中該黏著/阻障層位在該金屬保護 151 200814213 蓋上，且該金屬層包括一金層； 一打線導線，接合該金層與該引腳；以及 一聚合物材料，包覆該晶片承載座、該半導體晶片、談 打線導線與部份之該引腳。 715、 如申請專利範圍第714項所述之晶片封裝結構，其中 該導線架的材質包括銅。 716、 如申請專利範圍第714項所述之晶片封裝結構，其中 該導線架的厚度係介於1〇〇微米至2,000微米之間。 717、 如申請專利範圍第714項所述之晶片封裝結構，其中 該黏著材料的厚度係介於1微米至50微米之間。 718、 如申請專利範圍第714項所述之晶片封裳結構，其中 該黏著材料的材質包括聚合物材料。 719、 如申請專利範圍第714項所述之晶片封裝結構，其中 該黏著材料的材質包括聚醯亞胺（p〇lyimide，。 720、 如申請專利範圍第714項所述之晶片封裝結構，直中 該黏著材料的材質包括環氧樹脂（epoxy resin)。 、 721、 如申請專利範圍第714項所述之晶片封裝結構， 該半導體基底包括石夕。 、 722、 如申請專利範圍第714項所述之晶片封裝結構，其中 該半導體基底位在該黏著材料上。 723、 、如申請專利範圍第714項所述之晶片封裝結構，更包 =至少-金氧半導體_s)元件位在該半導體基底内或上 W、如申請專利範圍第714項所述之晶片封裝結構，其中 152 200814213 該線路結構包括厚度介於0.2微米至2微米之間的一銅層。 725、 如申請專利範圍第714項所述之晶片封裝結構，其中 該線路結構包括電鍍銅。 726、 如申請專利範圍第714項所述之晶片封裝結構，更包 括複數介電層位在該半導體基底與該保護層之間，且該線 路結構之複數圖案化金屬層位在該些介電層之間，並透過 位在該些介電層内的該線路結構之複數金屬插塞連接相鄰 兩層之該些圖案化金屬層。 727、 如申請專利範圍第726項所述之晶片封裝結構，其中 該些介電層的介電常數值（k)係介於1.5至3之間。 728、 如申請專利範圍第726項所述之晶片封裝結構，其中 該些介電層的材質包括氧矽化合物。 729、 如申請專利範圍第726項所述之晶片封裝結構，其中 該些介電層的材質包括氮矽化合物。 730、 如申請專利範圍第726項所述之晶片封裝結構，其中 該些介電層的材質包括氮氧矽化合物。 731、 如申請專利範圍第726項所述之晶片封裝結構，其中 該些介電層的材質包括含矽、碳、氧與氫之化合物。 732、 如申請專利範圍第726項所述之晶片封裝結構，其中 該些介電層的材質包括敦石夕玻璃（Fluorinated Silicate Glass) 〇 733、 如申請專利範圍第726項所述之晶片封裝結構，其中 該些介電層的厚度係介於0.3微米至2.5微米之間。 734、 如申請專利範圍第714項所述之晶片封裝結構，其中 153 200814213 該保護層包括氧石夕化合物。 735、 如申請專利範圍第714項所述之晶片封襄結構，其中 該保護層包括氮石夕化合物。 736、 ”請專利範圍第714頊所述之晶片封裝結構，其中 該保遵層包括氮氧碎化合物。 737、 如申請專利範圍第714項所述之晶片封裳結構，其中 該保護層的厚度係介於〇·3微米至1·5微米（以瓜)之間。 738、 ”請專利範圍第714項所述之晶片封裝結構，其中 該金屬保護蓋包括厚度介於〇·4微米至2微米之間的一人 鋁金屬層位在該開口所暴露出之該銅墊上，且該黏著/阻二 層位在該含鋁金屬層上。 739、 如申請專利範圍第738項所述之晶片封裝結構，其中 該含銘金屬層的材質包括銅。 740、 如申請專利範圍第738項所述之晶片封裝結構，其中 該含銘金屬層的材質包括銅與石夕。 741、 如申請專利範圍第714項所述之晶片封裴結構，其中 &quot; 該金屬保護蓋包括厚度介於0.01微米至0.7微米之間的一 阻障層（barrier layer)位在該開口所暴露出之該鋼墊上，以 及厚度介於0.4微米至2微米之間的一含鋁金屬層位在該 阻障層上，且該黏著/阻障層位在該含鋁金屬層上。 742、 如申請專利範圍第741項所述之晶片封裴結構，其中 該阻障層的材質包括鈦。 743、 如申請專利範圍第741項所述之晶片封裝結構，其中 該阻障層的材質包括鈦鎢合金。 154 200814213 ，如申請專利範圍第741項所述之晶片封裝結構， 該阻障層的材質包括氮化鈦。 /、τ 封裝結構，其中 745、如申請專利範圍第項所述之晶片 該阻障層的材質包括鉻。 爾、*申請專利範圍第741項所述之晶片封裝結構 該含銘金屬層的材質包括銅。 、 川、如中請專利範圍第741項所述之晶片封裝結構， 該含銘金屬層的材質包括銅與石夕。 •如中請專利範圍第714項所述之晶片封裝結構， 該金屬保護蓋包括厚度介於0·01微米至/、 偏^木之間的一 各鈕金屬層位在該開口所暴露出之該銅塾 上，以及厚度介 於0.4微米至2微米之間的—含銘金屬層位在該含組金屬 層上，且該黏著/阻障層位在該含鋁金屬層上。 749、如申請專利範圍第748項所述之晶片封裝結構，其中 該含纽金屬層為一鈕層。680. The chip package structure of claim 671, further comprising at least one metal oxide semiconductor (MOS) device in the semiconductor substrate or 681, the chip package as described in claim 671 A structure in which the wiring structure comprises a copper layer having a thickness of between 0.2 micrometers and 2 micrometers. The wafer package structure described in claim 671, wherein the circuit structure comprises a key copper. 683. The wafer sealing structure of claim 671, further comprising a plurality of dielectric layers between the semiconductor substrate and the protective layer, wherein the plurality of patterned metal layers are in the middle of the circuit. The gates of the electrical layer, 1, and the plurality of metal layers in the dielectric phase-line structure == two of the patterned metal layers. The phase of the connection is 684. The dielectric constant value (k) of the dielectric layers of the wafer package as described in claim 683 is between 1.5 and 3, wherein =, as in the case of the towel material _ 683 item The material of the wafer sealing the dielectric layers includes an oxonium compound. The wafer package structure of claim </ RTI> </ RTI> </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> </ RTI> <RTIgt; The material of the dielectric layer includes a oxynitride compound. The chip package structure according to claim 683, wherein the material of the dielectric layer comprises bismuth, carbon, oxygen and hydrogen. The wafer sealing structure of claim 683, wherein the material of the dielectric layer comprises Fluorinated sm (10) Glass. 69〇, as described in claim 683 The chip package structure wherein the thickness of the dielectric layer is between 0.3 μm and 2.5 μm. The chip package structure of claim 671, wherein the protective layer comprises an oxonium compound. ▲ The wafer-seal structure of claim 671, wherein the protective layer comprises a nitrogen cerium compound. 693 ^ The wafer package junction as described in claim 671 The protective layer includes a oxynitride compound, such as the wafer package structure described in claim 671, wherein the thickness of the protective layer is between 〇3 μm and 1.5 μm. 6%, as claimed in the patent application The chip package structure of claim 671, wherein the thickness of the copper pad is between 微米 2 μm and 2 μm. 696. The chip package structure as described in claim 671, the adhesion/barrier layer The material includes titanium. 697. The chip package structure of claim 671, wherein the material of the adhesion/barrier layer comprises titanium tungsten alloy. 6卯, the wafer according to claim 671 The material of the adhesion/barrier layer comprises titanium nitride. The structure of the wafer package structure as described in claim 671, wherein the material of the adhesion/barrier layer comprises chromium. The wafer sealing structure of the invention of claim 671, wherein the material of the adhesive/barrier layer comprises ruthenium. The 701, the wafer sealing material as described in claim 671, the material of the adhesive/barrier layer comprises nitrogen. Chemical The chip package structure of claim 671, wherein the thickness of the adhesion/barrier layer is between 0.03 micrometers and 〇7 micrometers 703, as claimed in claim 671. The chip package structure door, wherein the metal layer further comprises a sub-layer of copper on the puncture/barrier layer, a copper layer on the seed layer, and a nickel layer on the steel layer. I. The palladium layer is on the nickel layer. The chip package structure described in claim 671, wherein the thickness of the layer is between 1 micrometer and 20 micrometers. 705. The wafer sealing structure of claim 671, wherein the thickness of the layer is between 3 micrometers and 5 micrometers. 706. The wafer sealing structure of claim 671, wherein the wire bonding pad has a thickness of between 1 micrometer and 20 micrometers. 707. The chip package structure of claim 671, wherein the wire bonding pad has a thickness of between 3 micrometers and 5 micrometers. 708. The chip package structure of claim 671, wherein the material of the wire bonding wire comprises gold. 709. The chip package structure of claim 671, wherein the wire bonding wire has a diameter of between 20 micrometers and 50 micrometers. 710. The wafer package structure of claim 671, wherein the material of the polymer material comprises an epoxy resin (ep〇xy), 71, such as the chip package structure described in claim 671, The material of the polymer material comprises a polyimine (pj). The wafer package structure of the invention of claim 671, wherein the material of the polymer layer material comprises phenylcyclobutene (BCb). 713. The wafer package structure of claim 671, wherein the polymer material has a thickness between 250 micrometers and (eight) micrometers. 714. A chip package structure, comprising: a lead frame comprising a wafer carrier and a pin; an adhesive material disposed on the wafer carrier; a semiconductor wafer positioned on the adhesive material, and the semiconductor The wafer comprises: a semiconductor substrate; a wiring structure positioned above the semiconductor substrate; a protective layer positioned above the wiring structure, and an opening in the protective layer exposing a copper pad of the wiring structure; a metal protective cover on the copper pad exposed by the opening; and a wire bonding pad comprising an adhesive/barrier layer and a metal layer on the adhesive/barrier layer, wherein the adhesion/barrier The layer is covered by the metal protection 151 200814213, and the metal layer comprises a gold layer; a wire bonding wire bonding the gold layer and the pin; and a polymer material covering the wafer carrier, the semiconductor wafer, Talk about the wire and part of this pin. 715. The chip package structure of claim 714, wherein the lead frame is made of copper. 716. The wafer package structure of claim 714, wherein the leadframe has a thickness between 1 Å and 2,000 microns. 717. The wafer package structure of claim 714, wherein the adhesive material has a thickness of between 1 micrometer and 50 micrometers. 718. The wafer sealing structure of claim 714, wherein the material of the adhesive material comprises a polymer material. 719. The chip package structure of claim 714, wherein the material of the adhesive material comprises a polyimine (p 〇 lyimide, 720, the wafer package structure as described in claim 714, straight The material of the adhesive material comprises an epoxy resin, 721, the wafer package structure according to claim 714, wherein the semiconductor substrate comprises Shi Xi. 722, as claimed in claim 714 The chip package structure, wherein the semiconductor substrate is on the adhesive material. 723. The chip package structure according to claim 714, wherein the package is at least - the MOS device is located in the semiconductor. A wafer package structure as described in claim 714, wherein the circuit structure comprises a copper layer having a thickness of between 0.2 micrometers and 2 micrometers. 725. The wafer package structure of claim 714, wherein the wiring structure comprises electroplated copper. 726. The chip package structure of claim 714, further comprising a plurality of dielectric layers between the semiconductor substrate and the protective layer, and the plurality of patterned metal layers of the line structure are in the dielectric Between the layers, the patterned metal layers of the adjacent two layers are connected by a plurality of metal plugs of the line structure located in the dielectric layers. 727. The chip package structure of claim 726, wherein the dielectric layers have a dielectric constant value (k) between 1.5 and 3. 728. The wafer package structure of claim 726, wherein the material of the dielectric layer comprises an oxonium compound. 729. The chip package structure of claim 726, wherein the material of the dielectric layer comprises a nitrogen cerium compound. 730. The chip package structure of claim 726, wherein the material of the dielectric layer comprises a oxynitride compound. 731. The chip package structure of claim 726, wherein the material of the dielectric layer comprises a compound containing ruthenium, carbon, oxygen and hydrogen. 732. The chip package structure of claim 726, wherein the material of the dielectric layer comprises a Fluorinated Silicate Glass 733, the chip package structure as described in claim 726 The thickness of the dielectric layers is between 0.3 microns and 2.5 microns. 734. The wafer package structure of claim 714, wherein 153 200814213 the protective layer comprises an oxygen stone compound. 735. The wafer package structure of claim 714, wherein the protective layer comprises a Nitrogen compound. 736. The wafer package structure of claim 714, wherein the protective layer comprises a oxynitride compound. 737. The wafer sealing structure of claim 714, wherein the thickness of the protective layer </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> <RTIgt; A layer of aluminum metal between the micrometers is on the copper pad exposed by the opening, and the adhesion/resistance layer is on the aluminum-containing metal layer. 739. The chip package structure of claim 738, wherein the material containing the metal layer comprises copper. 740. The chip package structure of claim 738, wherein the material containing the metal layer comprises copper and stone. 741. The wafer package structure of claim 714, wherein the metal protection cover comprises a barrier layer having a thickness between 0.01 micrometers and 0.7 micrometers exposed at the opening. An aluminum-containing metal layer on the steel pad and between 0.4 micrometers and 2 micrometers in thickness is disposed on the barrier layer, and the adhesion/barrier layer is on the aluminum-containing metal layer. 742. The wafer package structure of claim 741, wherein the material of the barrier layer comprises titanium. 743. The chip package structure of claim 741, wherein the material of the barrier layer comprises a titanium tungsten alloy. 154. The semiconductor package structure of claim 741, wherein the material of the barrier layer comprises titanium nitride. /, τ package structure, wherein 745, as described in the scope of the patent application, the material of the barrier layer comprises chromium. The wafer package structure described in claim 741 of the patent application includes the copper material. The wafer package structure described in Patent Application No. 741, the material of the metal layer including the copper and the stone. The chip package structure of claim 714, wherein the metal protection cover comprises a layer of a metal layer having a thickness between 0. 01 micrometers and/or a metal layer exposed at the opening. The beryllium, and a thickness of between 0.4 micrometers and 2 micrometers, is contained on the metal-containing layer, and the adhesion/barrier layer is on the aluminum-containing metal layer. 749. The wafer package structure of claim 748, wherein the neon-containing metal layer is a button layer. 75〇、如申請專利範圍第748項所述之晶片封裝結構，其中 該含组金屬層為一氮化鈕層。 751、 如申請專利範圍第748項所述之晶片封裴結構，其中 該含銘金屬層的材質包括銅。 752、 如申請專利範圍第748項所述之晶片封裴結構，其中 該含銘金屬層的材質包括銅與矽。 753、 如申請專利範圍第714項所述之晶片封裝結構其中 該銅墊的厚度係介於0·2微米至2微米之間。 754、 如申請專利範圍第714項所述之晶片封裝結構，其中 155 200814213 該黏著/阻障層的材質包括鈦。 755、如申請專利範圍第714項所述之晶 該黏著/阻障層的材質包括鈦鎢合金。 裝、、、。構，其中 :、”請專利範圍第714項所述之晶片封裝結 該黏者/阻障層的材質包括氮化鈦。 ，、中 757、如申請專利範圍第714項所述之晶片 該黏著/阻障層的材質包括鉻。 一 ’其中 如中請專利範圍第714項所述之晶片封裝結構， 該黏著/阻障層的材質包括鈕。 /、中 759、如申請專利範圍第714項所述之晶片封裝結構 該黏著/阻障層的材質包括氮化鈕。 ^ T 760二如申請專利範圍第714項所述之晶片封裝結構，其中 該黏著/阻障層的厚度係介於〇 〇3微米至〇 7微米之門 761、 如申請專利範圍第714項所述之晶片封裝結構，曰其中 該金屬層更包括材質為金的一種子層位在該黏著/阻障層 上，且該金層位在該種子層上。 9 762、 如申請專利範圍第714項所述之晶片封裝結構，坌中 該金屬層更包括材質為銅的一種子層位在該黏著/阻障層 上、一銅層位在該種子層上以及一鎳層位在該銅層上，且 該金層位在該鎳層上。 763、 如申請專利範圍第714項所述之晶片封裝結構，其中 該金層的厚度係介於1微米至20微米之間。 764、 如申請專利範圍第714項所述之晶片封裝結構，其中 該金層的厚度係介於3微米至5微米之間。 156 200814213 765、 如申請專利範圍第714項所述之晶片封装辞構盆 該打線接墊的厚度係介於1微米至2〇微米之門 八中 766、 如申請專利範圍第？14項所述之晶片封裝結構，其 該打線接墊的厚度係介於3微米至5微米之間。 ’、中 767、 如中請專利範圍第714項所述之晶片封裝結構， 該打線導線的材質包括金。 768、 如中請專利範圍第714項所述之晶片封裝結構，其中 該打線導線的直徑介於20微米至50微米之間。 ’、 769、 如中請專利範圍第714項所述之晶片封裝結構，其中 該聚合物材料的材質包括環氧樹脂（eP〇xy)。 八 谓、如申請專利範圍第714項所述之晶片封裝結構，其中 該聚合物材料的材質包括聚醯亞胺（PJ)。 爪、如申請專利範圍第m項所述之晶片封裝結構，其中 該聚合物層材料的材質包括苯基環丁烯(BCb)。 772、 如申請專利範圍第714項所述之晶片封裝結構，其中 該聚合物材料的厚度係介於250微米至L000微米之間。 773、 一種晶片封裝結構，包括·· 一導線架，包括一晶片承載座與一引腳； 一黏著材料，位在該晶片承載座上； -半導體晶片，位在該黏著材料上，且該半導體晶片包 括： 一半導體基底； 一線路結構，位在該半導體基底上方； 一保護層，位在該線路結構上方，且位在該保護層 157 200814213 内之-開σ暴露it}該線路結構之一銅塾； -金屬保護盍’位在該開口所暴露出之該銅塾上· 以及 ’ :打、《墊’包括-黏著/阻障層與—金屬層位在該 黏者/阻P早層上，其中該黏著/阻障層位在該金屬保護 蓋上，且該金屬層包括一鈀層； 一打線導線，接合該鈀層與該引腳；以及 -聚合物材料，包覆該晶W載座、該半導體晶片、該 打線導線與部份之該引腳。 w 如申請專利範圍第773項所述之晶片封裝結構， 該導線架的材質包括銅。 σ /、 775、如申請專利範圍第773項所述之晶片封 該導線架的厚度係介於_微米至2，_微米之°門 =、奸如中請專利範圍第773項所述之晶片封裝料，其中 ^黏者材料的厚度係介於丨微米至5〇微米之間。 爪、如中請專利範圍第？73項所述之晶片封^結 該黏著材料的材質包括聚合物材料。 〃 =、著請專利範圍第773項所述之晶片封裝結構，其中 該黏者材料的材質包括聚亞胺(p()lyimide，叫 τ 請專利範圍第773項所述之晶片封裝結構，其中 該黏者材料的材質包括環氧樹脂(epGxy resin)。 〒 導Γ請專利範圍第773項所述之晶片封裝結構，1中 該+導體基底包括石夕。 再/、中 781、如申請專利範圍第773項所述之晶片封裝結構，其中 200814213 該半導體基底位在該黏者材料上。 782、 如申請專利範圍第773項所述之晶片封裝結構，更包 括至少一金氧半導體（MOS)元件位在該半導體基底内或上 方。 783、 如申請專利範圍第773項所述之晶片封裝結構，其中 該線路結構包括厚度介於0.2微米至2微米之間的一銅層。 784、 如申請專利範圍第773項所述之晶片封裝結構，其中 該線路結構包括電鍍銅。 785、 如申請專利範圍第773項所述之晶片封裝結構，更包 括複數介電層位在該半導體基底與該保護層之間，且該線 路結構之複數圖案化金屬層位在該些介電層之間，並透過 位在該些介電層内的該線路結構之複數金屬插塞連接相鄰 兩層之該些圖案化金屬層。 786、 如申請專利範圍第785項所述之晶片封裝結構，其中 該些介電層的介電常數值（k)係介於1.5至3之間。 787、 如申請專利範圍第785項所述之晶片封裝結構，其中 該些介電層的材質包括氧矽化合物。 788、 如申請專利範圍第785項所述之晶片封裝結構，其中 該些介電層的材質包括氮矽化合物。 789、 如申請專利範圍第785項所述之晶片封裝結構，其中 該些介電層的材質包括氮氧矽化合物。 790、 如申請專利範圍第785項所述之晶片封裝結構，其中 該些介電層的材質包括含矽、碳、氧與氫之化合物。 791、 如申請專利範圍第785項所述之晶片封裝結構，其中 159 200814213 該些介電層的材質包括氟矽玻璃（Fluori Glass)。792、 士 nated Silicate 片封裝結構，其中 微米之間。 片封裝結構，其中 、如申請專利範圍第785項所述之晶片The wafer package structure of claim 748, wherein the group metal layer is a nitride button layer. 751. The wafer package structure of claim 748, wherein the material containing the metal layer comprises copper. 752. The wafer package structure of claim 748, wherein the material containing the metal layer comprises copper and tantalum. 753. The chip package structure of claim 714, wherein the thickness of the copper pad is between 0. 2 microns and 2 microns. 754. The chip package structure of claim 714, wherein the material of the adhesion/barrier layer comprises titanium. 755. The material of the adhesion/barrier layer as described in claim 714 includes a titanium-tungsten alloy. Installed,,,. The structure of the wafer packaged with the adhesive/barrier layer described in claim 714 of the patent includes titanium nitride, and 757, the wafer of the invention as claimed in claim 714. The material of the barrier layer comprises chrome. A wafer package structure as described in claim 714 of the patent application, the material of the adhesion/barrier layer comprises a button. /, 759, as claimed in item 714 The material of the adhesion/barrier layer includes a nitride button. The T-760 is a wafer package structure as described in claim 714, wherein the thickness of the adhesion/barrier layer is between 〇 The chip package structure of the invention of claim 761, wherein the metal layer further comprises a sub-layer of gold as the adhesion/barrier layer, and The gold layer is on the seed layer. The chip package structure of claim 714, wherein the metal layer further comprises a sub-layer of copper on the adhesion/barrier layer. a copper layer on the seed layer A nickel layer is on the copper layer, and the gold layer is on the nickel layer. 763. The chip package structure of claim 714, wherein the gold layer has a thickness of between 1 micrometer and 20 764. The wafer package structure of claim 714, wherein the thickness of the gold layer is between 3 micrometers and 5 micrometers. 156 200814213 765, as described in claim 714 The thickness of the wire bond pad is between 1 micrometer and 2 micrometers. The wafer package structure as described in claim 14 of the patent application, the thickness of the wire bonding pad is Between 3 micrometers and 5 micrometers. The middle of the wafer package structure of the invention, wherein the wire bonding material comprises gold. 768, as described in claim 714 of the patent scope The chip package structure, wherein the wire material has a diameter of between 20 micrometers and 50 micrometers. The chip package structure of the invention of claim 714, wherein the material of the polymer material comprises epoxy Resin (eP The chip package structure of claim 714, wherein the material of the polymer material comprises polyimine (PJ). The chip, the chip package according to claim m The structure of the polymer layer material comprises phenylcyclobutene (BCb). The wafer package structure of claim 714, wherein the polymer material has a thickness of between 250 micrometers and L000. Between 微米, 773, a chip package structure, comprising: a lead frame comprising a wafer carrier and a pin; an adhesive material disposed on the wafer carrier; - a semiconductor wafer positioned on the adhesive material And the semiconductor wafer comprises: a semiconductor substrate; a wiring structure located above the semiconductor substrate; a protective layer positioned above the wiring structure and located within the protective layer 157 200814213 - open σ exposure it} One of the line structures is a copper plaque; - the metal protection 盍 'is located on the gong exposed by the opening · and ': hit, the 'pad' includes - adhesion / barrier layer - metal layer at Adhesive/resistive P layer, wherein the adhesion/barrier layer is on the metal protective cover, and the metal layer comprises a palladium layer; a wire bonding wire bonding the palladium layer and the pin; and - a polymer a material covering the crystal W carrier, the semiconductor wafer, the wire bonding wire and a portion of the pin. w. The wafer package structure of claim 773, wherein the lead frame is made of copper. σ /, 775, as described in the patent application scope 773, the thickness of the lead frame is between _ micron to 2, _ micron ° =, such as the patent described in the scope of the patent 773 The encapsulant, wherein the thickness of the adhesive material is between 丨 micrometers and 5 micrometers. Claws, such as the scope of patents? The wafer sealing material described in item 73 includes the polymer material. 〃 =, the wafer package structure described in the scope of Patent No. 773, wherein the material of the adhesive material comprises polyimine (p() lyimide, called τ, the wafer package structure described in Patent Item 773, wherein The material of the adhesive material includes epoxy resin (epGxy resin). 〒 The wafer package structure described in Patent Document No. 773 is used, and the + conductor substrate includes Shi Xi. In /, 781, such as patent application The chip package structure of claim 773, wherein the semiconductor substrate is located on the adhesive material. 782. The chip package structure of claim 773, further comprising at least one metal oxide semiconductor (MOS). The device is located in or on the semiconductor substrate. The wafer package structure of claim 773, wherein the circuit structure comprises a copper layer having a thickness of between 0.2 micrometers and 2 micrometers. The chip package structure of claim 773, wherein the circuit structure comprises electroplated copper. 785. The chip package structure according to claim 773, further comprising a plurality of a layer between the semiconductor substrate and the protective layer, and the plurality of patterned metal layers of the line structure are between the dielectric layers and pass through the plurality of metals of the line structure located in the dielectric layers The chip is connected to the two adjacent layers of the patterned metal layer. The chip package structure of claim 785, wherein the dielectric layers have a dielectric constant value (k) of 1.5 to The chip package structure of claim 785, wherein the material of the dielectric layer comprises an oxonium compound. 788. The chip package structure of claim 785, wherein The material of the dielectric layer includes a ytterbium compound. The chip package structure of claim 785, wherein the material of the dielectric layer comprises a oxynitride compound. 790, as claimed in claim 785 The chip package structure of the present invention, wherein the material of the dielectric layer comprises a compound containing ruthenium, carbon, oxygen and hydrogen. 791. The chip package structure of claim 785, wherein 159 20081421 3 The material of the dielectric layer comprises Fluori Glass. The 792, the Nated Silicate package structure, wherein the chip is packaged, wherein the wafer is as described in claim 785. 琢俅謾層包括氧矽化合物。 794、如申請專利範圍第773項所述之晶片封裝結構 該保護層包括氮矽化合物。 7仏如申請專利範圍第773項所述之晶片封裳結構，其中 該保護層包括氮氧矽化合物。 ^ 796、 如巾請專㈣㈣773項所述之晶片封裝結構，並中 該保護層的厚度係介於〇.3微米至15微米（叫之間了 797、 如巾請專利範圍第773項所述之晶片封裝結構，其中 該金屬保護蓋包括厚度介於〇.4微米至2微米之間的一入 銘金屬層位在該開π所暴露出之該銅墊上，且 層位在該含鋁金屬層上。 ，、如申請專利範圍第797項所述之晶片封裝結構，其中 該含銘金屬層的材質包括銅。 7的、如申請專利範圍第797項所述之晶片封裝結構，其中 該含銘金屬層的材質包括銅與石夕。 阻障層（barrier layer)位在該開口所暴露出之該銅墊上，The ruthenium layer includes an oxonium compound. 794. The wafer package structure of claim 773, wherein the protective layer comprises a nitrogen bismuth compound. 7. The wafer sealing structure of claim 773, wherein the protective layer comprises a oxynitride compound. ^ 796, such as the towel, please (4) (four) 773 of the chip package structure, and the thickness of the protective layer is between 微米. 3 microns to 15 microns (called 797, as described in the scope of the patent The chip package structure, wherein the metal protection cover comprises a metal layer having a thickness between 〇.4 μm and 2 μm on the copper pad exposed by the opening π, and the layer is on the aluminum-containing metal The wafer package structure of claim 797, wherein the material of the metal layer comprises a copper package, wherein the wafer package structure of claim 797, wherein the The material of the metal layer includes copper and stone eve. The barrier layer is located on the copper pad exposed by the opening. 刪、如申請專利範圍第773項所述之晶片封裝結構，其中 該金屬保護蓋包括厚度介於0·01微米至〇·7微米之間的一 160 200814213 阻障層上，且該黏著/阻障層位在該含鋁金屬芦上。 8〇卜如申請專利範圍第800項所述之晶片封裝結構，盆中 該阻障層的材質包括鈦。 八 802、 如申請專利範圍第8〇〇項所述之晶片封裝結構，其中 該阻障層的材質包括鈦鎢合金。 803、 如申請專利範圍第8〇〇項所述之晶片封裝結構，其中 該阻障層的材質包括氮化鈦。The chip package structure of claim 773, wherein the metal protection cover comprises a 160 200814213 barrier layer having a thickness between 0·01 μm and 〇·7 μm, and the adhesion/resistance The barrier layer is on the aluminum-containing metal reed. The wafer package structure of claim 800, wherein the material of the barrier layer comprises titanium. The chip package structure of claim 8, wherein the material of the barrier layer comprises a titanium tungsten alloy. 803. The chip package structure of claim 8, wherein the material of the barrier layer comprises titanium nitride. 綱、如申請專利範圍第議項所述之晶片封裝結構其中 該阻障層的材質包括鉻。 8〇5、如中請專利範圍第綱項所述之晶片封裝結構其中 該含鋁金屬層的材質包括銅。 8〇6、如申請專利範圍第_項所述之晶片封裝結構其中 該含銘金屬層的材質包括銅與石夕。 8〇7、如申請專利範圍第773項所述之晶片封裝結構其中 該金屬保護蓋包括厚度介於0.01微米至0·7微米之門的 含钽金屬層位在該開口所暴露出之該銅墊 Μ及厚度介 於0.4微米至2微米之間的—含銘金屬層位在該含组金屬 層上’且該黏著/阻障層位在該含銘金屬層上。 麵、如申請專利範圍第謝項所述之晶片封裝結構，其中 該含组金屬層為一组層。 ㈣、如申請專利範圍第807項所述之晶片封裝結構其中 該含麵金屬層為一氮化纽層。 ⑽'如中請專利範圍第8G7項所述之晶片封裝結構其中 該含銘金屬層的材質包括銅。 161 200814213 81、如申請專利範圍第807項所述之晶片封裝結構， 該3铭金屬層的材質包括銅與矽。 、 =、如申請專利範圍第773項所述之晶片封 該銅墊的厚度係介於〇·2微米至2微米之間。 ^二如申請專利範圍第773項所述之晶片封裝結構，直中 該黏著/阻障層的材質包括鈦。 、 814、朴如申請專利範圍第773項所述之晶片封裝結構，其中 該黏著/阻障層的材質包括鈦鎢合金。 如巾請專利範圍第773項所述之晶片封裝結構，其中 該黏著/阻障層的材質包括氮化鈦。 816、奸如申請專利範圍第773項所述之晶片封裝結構， 該黏著/阻障層的材質包括鉻。 爪、如申請專利範圍第773項所述之晶片封裂結構盆 該黏著/阻障層的材質包括鈕。 a 818 ^如中請專利範圍第773項所述之晶片封裝結構其中 該黏著/阻障層的材質包括氮化钽。 819、 如申請專利範圍第773項所述之晶片封裝結構，其中 該黏著/阻障層的厚度係介於0.03微米至〇.7微米之間、。 820、 如申請專利範圍第773項所述之晶片封裝結構^中 該金屬層更包括材質為銅的—種子層位錢黏著/阻障層 上、一銅層位在該種子層上以及一鎳層位在該銅層上，2 該鈀層位在該鎳層上。 821、 如申請專利範圍第773項所述之晶片封裝結構其中 該鈀層的厚度係介於丨微米至2〇微米之間。 162 200814213 822、 如申請專利範圍第773項所述之晶片封裝結構，其中 該鈀層的厚度係介於3微米至5微米之間。 823、 如申請專利範圍第773項所述之晶片封裝結構，其中 該打線接墊的厚度係介於1微米至20微米之間。 824、 如申請專利範圍第773項所述之晶片封裝結構，其中 該打線接墊的厚度係介於3微米至5微米之間。 825、 如申請專利範圍第773項所述之晶片封裝結構，其中 該打線導線的材質包括金。 826、 如申請專利範圍第773項所述之晶片封裝結構，其中 該打線導線的直徑介於20微米至50微米之間。 827、 如申請專利範圍第773項所述之晶片封裝結構，其中 該聚合物材料的材質包括環氧樹脂（epoxy)。 828、 如申請專利範圍第773項所述之晶片封裝結構，其中 該聚合物材料的材質包括聚醯亞胺（PI)。 829、 如申請專利範圍第773項所述之晶片封裝結構，其中 該聚合物層材料的材質包括苯基環丁烯(BCB)。 830、 如申請專利範圍第773項所述之晶片封裝結構，其中 該聚合物材料的厚度係介於250微米至1，000微米之間。 831、 一種晶片封裝結構，包括： 一導線架，包括一晶片承載座與一引腳； 一黏者材料’位在該晶片承載座上， 一半導體晶片’位在該黏者材料上’且該半導體晶片包 括： 一半導體基底； 163 200814213 一線路結構，位在該半導體基底上方； 一保護層，位在該線路結構上方，且位在該保護層 内之開口暴路出該線路結構之一接墊；以及 金屬線路’位在該保護層上方，並透過該開口連 接該接墊，且該金屬線路包括一金層； 一打線導線，接合該金層與談引腳；以及 一聚合物材料，包覆該晶片承載座、該半導體晶片、該 打線導線與部份之該引腳。The wafer package structure of the above-mentioned patent application scope, wherein the material of the barrier layer comprises chromium. 8. The wafer package structure of the first aspect of the invention, wherein the material of the aluminum-containing metal layer comprises copper. 8. The chip package structure according to claim _ wherein the material containing the metal layer comprises copper and stone. 8. The wafer package structure of claim 773, wherein the metal protective cover comprises a copper-containing metal layer having a thickness of between 0.01 micrometers and 0.7 micrometers, the copper layer exposed at the opening The mat and the thickness between 0.4 micrometers and 2 micrometers - the layer containing the metal layer on the metal layer of the group - and the adhesion/barrier layer is on the metal layer containing the metal. The chip package structure of claim 1, wherein the group of metal layers is a set of layers. (4) The chip package structure of claim 807, wherein the surface metal layer is a nitrided layer. (10) The chip package structure as described in claim 8G7, wherein the material containing the metal layer comprises copper. 161 200814213 81. The wafer package structure of claim 807, wherein the material of the metal layer comprises copper and tantalum. , =, as claimed in claim 773, the thickness of the copper pad is between 2 2 microns and 2 microns. ^2. The wafer package structure of claim 773, wherein the material of the adhesion/barrier layer comprises titanium. 814. The wafer package structure of claim 773, wherein the material of the adhesion/barrier layer comprises a titanium-tungsten alloy. The wafer package structure of claim 773, wherein the material of the adhesion/barrier layer comprises titanium nitride. 816. The chip package structure according to claim 773, wherein the adhesive/barrier layer material comprises chromium. The claw, the wafer-sealing structure basin according to claim 773, the material of the adhesive/barrier layer comprises a button. A 818. The chip package structure of claim 773, wherein the material of the adhesion/barrier layer comprises tantalum nitride. The chip package structure of claim 773, wherein the thickness of the adhesion/barrier layer is between 0.03 micrometers and 〇.7 micrometers. 820. The chip package structure of claim 773, wherein the metal layer further comprises a copper-based seed layer adhesion/barrier layer, a copper layer on the seed layer, and a nickel layer. The layer is on the copper layer and 2 the palladium layer is on the nickel layer. 821. The wafer package structure of claim 773, wherein the palladium layer has a thickness ranging from 丨micron to 2 〇 micron. The wafer package structure of claim 773, wherein the palladium layer has a thickness of between 3 microns and 5 microns. 823. The chip package structure of claim 773, wherein the wire bonding pad has a thickness of between 1 micrometer and 20 micrometers. 824. The wafer package structure of claim 773, wherein the wire bonding pad has a thickness of between 3 micrometers and 5 micrometers. 825. The chip package structure of claim 773, wherein the wire bonding material comprises gold. 826. The wafer package structure of claim 773, wherein the wire bonding wire has a diameter of between 20 micrometers and 50 micrometers. 827. The wafer package structure of claim 773, wherein the material of the polymer material comprises epoxy. 828. The wafer package structure of claim 773, wherein the material of the polymer material comprises polyimine (PI). 829. The wafer package structure of claim 773, wherein the material of the polymer layer material comprises phenylcyclobutene (BCB). 830. The wafer package structure of claim 773, wherein the polymer material has a thickness between 250 microns and 1,000 microns. 831. A chip package structure comprising: a lead frame comprising a wafer carrier and a pin; an adhesive material 'positioned on the wafer carrier, a semiconductor wafer 'located on the adhesive material' and The semiconductor wafer comprises: a semiconductor substrate; 163 200814213 a line structure located above the semiconductor substrate; a protective layer positioned above the line structure, and an opening in the protective layer exits the circuit structure a pad; and a metal line 'located above the protective layer and connected to the pad through the opening, and the metal line includes a gold layer; a wire bonding wire bonding the gold layer and the talk pin; and a polymer material, The wafer carrier, the semiconductor wafer, the wire bonding wire and a portion of the pin are covered. 832、如申請專利範圍第831項所述之晶片封裝結構，其中 該導線架的材質包括銅。 833、 如申請專利範圍第831項所述之晶片封裝結構，其中 該導線架的厚度係介於1〇〇微米至2,〇〇〇微米之間。 834、 从如申請專利範圍第831項所述之晶片封裝結構，其中 該黏著材料的厚度係介於1微米至50微米之間。 835、如申請專利範圍第831項所述之晶片封裝結構，其中 該黏著材料的材質包括聚合物材料。 836、 分如申請專利範圍第831項所述之晶片封裝結構，其中 該黏著材料的材質包括聚醯亞胺（polyimide，。 ’、 837、 #如申請專利範圍第831項所述之晶片封裝結構，其中 該黏者材料的材質包括環氧樹脂（ep〇xy resin)。 838、 如申請專利範圍第831項所述之晶片 該半導體基底包括矽。 839、 如申請專利範圍第831項所述之晶片 該半導體基底位在該黏著材料上。 封裝結構，其中 封裝結構，其中 164 200814213 840、 如申請專利範圍第831項所述之晶片封裝結構，更包 括至少一金氧半導體（MOS)元件位在該半導體基底内或上 方。 841、 如申請專利範圍第831項所述之晶片封裝結構，其中 該線路結構包括厚度介於0.2微米至2微米之間的一銅層。 842、 如申請專利範圍第831項所述之晶片封裝結構，其中 該線路結構包括電鍍銅。 843、 如申請專利範圍第831項所述之晶片封裝結構，其中 該線路結構包括厚度介於0.2微米至2微米之間的一含鋁 金屬層。 844、 如申請專利範圍第831項所述之晶片封裝結構，更包 括複數介電層位在該半導體基底與該保護層之間，且該線 路結構之複數圖案化金屬層位在該些介電層之間，並透過 位在該些介電層内的該線路結構之複數金屬插塞連接相鄰 兩層之該些圖案化金屬層。 845、 如申請專利範圍第844項所述之晶片封裝結構，其中 該些介電層的介電常數值（k)係介於1.5至3之間。 846、 如申請專利範圍第844項所述之晶片封裝結構，其中 該些介電層的材質包括氧矽化合物。 847、 如申請專利範圍第844項所述之晶片封裝結構，其中 該些介電層的材質包括氮石夕化合物。 848、 如申請專利範圍第844項所述之晶片封裝結構，其中 該些介電層的材質包括氮氧石夕化合物。 849、 如申請專利範圍第844項所述之晶片封裝結構，其中 165 200814213 該些介電層的材質包括含矽、碳、氧與氫之化合物。 850、 如申請專利範圍第844項所述之晶片封裝結構，其中 該些介電層的材質包括氟矽玻璃（Flu〇rinated smeate Glass) 〇 851、 如申請專利範圍第844項所述之晶片封裝結構，其中 該些介電層的厚度係介於〇·3微米至2.5微米之間。 852、 如申請專利範圍第831項所述之晶片封裝結構，其中 該保護層包括氧矽化合物。 853、 如申請專利範圍第831項所述之晶片封裝結構，其中 該保護層包括氮矽化合物。 854、 如申請專利範圍第831項所述之晶片封裴結構，其中 該保護層包括氮氧矽化合物。 855、 如申請專利範圍第831項所述之晶片封裝結構，其中 該保護層的厚度係介於0.3微米至1·5微米（//m)之間。 856、 如申請專利範圍第831項所述之晶片封裝結構，其中 該接墊包括厚度介於〇·2微米至2微米之間的一銅層，且 該金屬線路連接該銅層。 857、 如申請專利範圍第831項所述之晶片封裝結構，其中 該接墊包括厚度介於〇.2微米至2微米之間的—鋁合金 層’且該金屬線路連接該鋁合金層。 858、 如申請專利範圍第831項所述之晶片封褒結構，更包 括一金屬保護蓋位在該開口所暴露出之該接墊上，且該金 屬線路連接該金屬保護蓋。 859、 如申請專利範圍第858項所述之晶片封裳結構，其中 166 200814213 該接墊為銅墊。 860、如申請專利範圍第858項所述之晶片封裝結構其中 該金屬保護蓋包括厚度介於0.4微米至2微米之間的一含 鋁金屬層位在該開口所暴露出之該接墊上，且部分該金屬 線路位在該含鋁金屬層上。 861、 如申請專利範圍第86〇項所述之晶片封裝結構，其中 該含鋁金屬層的材質包括銅。832. The chip package structure of claim 831, wherein the lead frame is made of copper. The wafer package structure of claim 831, wherein the lead frame has a thickness of between 1 μm and 2 μm. 834. The wafer package structure of claim 831, wherein the thickness of the adhesive material is between 1 micrometer and 50 micrometers. 835. The wafer package structure of claim 831, wherein the material of the adhesive material comprises a polymer material. 836. The chip package structure of claim 831, wherein the material of the adhesive material comprises polyimide, ', 837, #, as claimed in claim 831. The material of the adhesive material comprises an epoxy resin (ep〇xy resin) 838. The semiconductor substrate according to claim 831, wherein the semiconductor substrate comprises a crucible. 839, as described in claim 831. The semiconductor substrate is located on the adhesive material. The package structure, wherein the package structure, wherein: 164 200814213 840, the chip package structure of claim 831, further comprising at least one metal oxide semiconductor (MOS) component 841. The wafer package structure of claim 831, wherein the circuit structure comprises a copper layer having a thickness between 0.2 micrometers and 2 micrometers. 842. The wafer package structure of item 831, wherein the circuit structure comprises electroplated copper. 843, the wafer seal of claim 831 The package structure, wherein the circuit structure comprises an aluminum-containing metal layer having a thickness of between 0.2 μm and 2 μm. 844. The wafer package structure of claim 831, further comprising a plurality of dielectric layers Between the semiconductor substrate and the protective layer, and the plurality of patterned metal layers of the wiring structure are between the dielectric layers and are connected to the plurality of metal plugs of the circuit structure located in the dielectric layers 845. The chip package structure of claim 844, wherein the dielectric layers have a dielectric constant value (k) between 1.5 and 3. 846. The chip package structure of claim 844, wherein the material of the dielectric layer comprises an oxonium compound. The wafer package structure of claim 844, wherein the dielectric is The material of the layer includes a nitrous oxide compound. The wafer package structure of claim 844, wherein the material of the dielectric layer comprises a oxynitride compound. 849, as claimed in claim 844 The chip package structure, wherein the material of the dielectric layer comprises a compound containing germanium, carbon, oxygen and hydrogen. 850. The chip package structure of claim 844, wherein the dielectric is The material of the layer includes a fluorocarbon glass (Flu〇rinated smeate glass) 851, which is a wafer package structure as described in claim 844, wherein the thickness of the dielectric layer is between 微米3 micrometers and 2.5 micrometers. 852. The wafer package structure of claim 831, wherein the protective layer comprises an oxonium compound. 853. The wafer package structure of claim 831, wherein the protective layer comprises a nitrogen hydrazine compound. 854. The wafer package structure of claim 831, wherein the protective layer comprises a oxynitride compound. 855. The wafer package structure of claim 831, wherein the protective layer has a thickness of between 0.3 micrometers and 1.5 micrometers (//m). 856. The wafer package structure of claim 831, wherein the pad comprises a copper layer having a thickness of between 2 μm and 2 μm, and the metal line connects the copper layer. 857. The wafer package structure of claim 831, wherein the pad comprises an aluminum alloy layer having a thickness between 微米.2 μm and 2 μm and the metal line is connected to the aluminum alloy layer. 858. The wafer package structure of claim 831, further comprising a metal protection cover on the pad exposed by the opening, and the metal wire is connected to the metal protection cover. 859. The wafer sealing structure according to claim 858, wherein 166 200814213 is a copper pad. 860. The chip package structure of claim 858, wherein the metal protective cover comprises an aluminum-containing metal layer having a thickness between 0.4 micrometers and 2 micrometers on the pad exposed by the opening, and A portion of the metal line is on the aluminum-containing metal layer. 861. The chip package structure of claim 86, wherein the material of the aluminum-containing metal layer comprises copper. 862、 如申請專利範圍第86〇項所述之晶片封裝結構，其中 該含銘金屬層的材質包括銅與石夕。 863、 如申請專利範圍第858項所述之晶片封裝結構，其中 該金屬保護蓋包括厚度介於〇.〇1微米至0·7微米之間的一 阻障層（barrier layer)位在該開口所暴露出之該接墊上，以 及厚度介於0.4微米至2微来之間的—含銘金屬層位在該 阻障層上，且部分該金屬線路位在該含鋁金屬層上。&quot; 864、 如申請專利範圍第863項所述之晶片封裝結構，盆中 該阻障層的材質包括鈥。 〃 865、如申請專職圍第863項所述之晶片封裝結構，其中 該阻障層的材質包括鈦鎢合金。 866、如申請專利範圍第863項所述之晶片封裝結構，其中 該阻障層的材質包括氮化鈦。 &quot;八 867、如申請專利範圍第863項所述之晶片封 該阻障層的材質包括鉻 I&quot; 封裝結構，其中 868、如申請專利範圍第863項所述之晶片 該阻障層的材質包括鈕。 167 200814213 869、 如申請專利範圍第863項所述之晶片封 該阻障層的材質包括氮化鈕。 -、吉構，其中 870、 如申請專利範圍第863項所述之晶片封 該含鋁金屬層的材質包括銅。 、、籌/、中 871、 如申請專利範圍第863項所述之晶片封穿妗 該含銘金屬層的材質包括銅與矽。 冓/、中 :如申請專利範圍第831項所述之晶片封裝結構，其中 該金屬線路更包括一黏著/阻障層與一種子層位 ^ 阻障層上，且該金層位在該種子層上方。 “黏著/ ⑺、如中請專利範圍第872項所述之晶片封裝結構， 該黏著/阻障層的材質包括鈦。 ，、Y 8'如申請專利範圍第872項所述之晶片封裝結 該黏著/阻障層的材質包括鈦鎢合金。 一 仍、#如申請專利範圍第872項所述之晶片封裝結構， 該黏著/阻障層的材質包括氮化鈦。 876、 #如中請專利範圍第m項所述之晶片封裝結構， 該黏著/阻障層的材質包括鉻。 /、 877、 如申請專利範圍第872項所述之晶片 該黏著/阻障層的材質包括组。 裝、，、。構，其中 ㈣^如申請專利範圍第872項所述之晶片封裝結構， 該黏著/阻障層的材質包括氮化鈕。 、 ’乂如申請專利範圍第872項所述之晶片封裝結構， 該黏者/阻障層的厚度係介於〇·〇3微米至幻微米之間。 議、如申請專利範圍第872項所述之晶片封裝結構，复中 168 200814213 該種子層的材質為金，且該金層位在該種子層上。 881、 如申請專利範圍第872項所述之晶片封裝結構，其中 該種子層的材質為銅’且該金屬線路更包括—銅層位在該 種子層上以及一鎳層位在該銅層上，該金層位在該鎳層上。 882、 如申請專利範圍第831項所述之晶片封裝結構，曰其中 該金層的厚度係介於1微米至2〇微米之間。 883、 如申請專利範圍第831項所述之晶片封裝結構，其中 該金層的厚度係介於3微米至5微米之間。 884、 如申請專利範圍第831項所述之晶片封裝結構，其中 該金屬線路的厚度係介於1微米至2〇微米之間。 885、 如申請專利範圍第831項所述之晶片封裝結構，其中 該金屬線路的厚度係介於3微米至5微米之間。 886、 如申請專利範圍第831項所述之晶片封裝結構，其中 該打線導線的材質包括金。 887、 如申請專利範圍第831項所述之晶片封裝結構，其中 該打線導線的直徑介於20微米至50微米之間。 888、 如申請專利範圍第831項所述之晶片封裝結構，其中 該聚合物材料的材質包括環氧樹脂（ep〇xy)。 889、 如申請專利範圍第831項所述之晶片封裴結構，其中 該聚合物材料的材質包括聚醯亞胺（PI)。 890、 如申請專利範圍第831項所述之晶片封裝結構，其中 該聚合物層材料的材質包括苯基環丁烯(BCB)。 891、 如申請專利範圍第831項所述之晶片封裝結構，其中 該聚合物材料的厚度係介於250微米至1，〇〇〇微米之門 169 200814213 892、 如申請專利範圍第831項所述之晶片封裝結構，其中 該打線導線接合該金層的位置從俯視透視圖觀之，係不同 於該接墊的位置。 893、 如申請專利範圍第831項所述之晶片封裝結構，更包 括一聚合物層位在該保護層上，且位在該聚合物層内之一 聚合物層開口暴露出該接墊，該金屬線路位在該聚合物層 上並透過該聚合物層開口連接該接墊。 894、 如申請專利範圍第893項所述之晶片封裝結構，其中 該聚合物層的材質包括聚醯亞胺（PI)。 895、 如申請專利範圍第893項所述之晶片封裝結構，其中 該聚合物層的材質包括環氧樹脂（epoxy)。 896、 如申請專利範圍第893項所述之晶片封裝結構，其中 該聚合物層的材質包括苯基環丁烯(BCB)。 897、 如申請專利範圍第893項所述之晶片封裝結構，其中 該聚合物層的厚度係介於3微米至25微米之間。 898、 如申請專利範圍第831項所述之晶片封裝結構，更包 括一聚合物層位在該金屬線路上，且位在該聚合物層内之 一聚合物層開口暴露出該金層，該打線導線透過該聚合物 層開口接合該金層。 899、 如申請專利範圍第898項所述之晶片封裝結構，其中 該聚合物層的材質包括聚醯亞胺（PI)。 900、 如申請專利範圍第898項所述之晶片封裝結構，其中 該聚合物層的材質包括環氧樹脂（epoxy)。 901、 如申請專利範圍第898項所述之晶片封裝結構，其中 170 200814213 該聚合物層的材質包括苯基環丁烯（BCB)。 902、 如申請專利範圍第898項所述之晶片封裝結構，其中 該聚合物層的厚度係介於3微米至25微米之間。 903、 一種晶片封裝製程，其步驟包括： 提供一半導體晶片，其係包括： 一半導體基底； 一線路結構’位在該半導體基底上方； 一保護層，位在該線路結構上方，且位在該保 &quot; 護層内之一開口暴露出該線路結構之一接墊； 一黏著/阻障層，位在該開口所暴露出該線路 結構之該接塾上方， 一種子層，位在該黏著/阻障層上；以及 一金屬層，位在該種子層上； 利用一黏著材料黏著該半導體晶片至一基板的一第一 表面； 形成一打線導線接合該金屬層與該基板； i 形成一聚合物材料在該第一表面上，並覆蓋該半導體 晶片與該打線導線；以及 形成一無錯銲料（lead-free solder)在該基板之一第二 表面上，並在溫度介於230°C至260°C之間進行一迴銲 (reflow)製程，以形成一無錯錫球（lead-free solder ball)。 904、 如申請專利範圍第903項所述之晶片封裝製程，其中 該半導體基底包括矽。 905、 如申請專利範圍第903項所述之晶片封裝製程，更包 171 200814213 括至少一金氧半導體（MOS)元件位在該半導體基底内或上 方。 906如申请專利範圍第903項所述之晶片封裝製程，其中 該線路結構包括厚度介於〇·2微米至2微米之間的一銅層。 907、 如申請專利範圍第9〇3項所述之晶片封裝製程，其中 該線路結構包括電鍍銅。 908、 如申請專利範圍第9〇3項所述之晶片封裝製程，其中 , $線路結構包括厚度介於0.2微米至2微米之間的一含銘 金屬層。 909、 如申請專利範圍第903項所述之晶片封裝製程，更包 括複數介電層位在該半導體基底與該保護層之間，且該= 路結構之複數圖案化金屬層位在該些介電層之間，並透過 位在該些介電層内的該線路結構之複數金屬插塞連接相^ 兩層之該些圖案化金屬層。 910、 如申請專利範圍第9〇9項所述之晶片封裝製程，其中 該些介電層的介電常數值（k)係介於1.5至3之間。 k ' 911、如申請專利範圍第909項所述之晶片封萝匍 該些介電層的材質包括氧矽化合物。 、 八 912、 如申請專利範圍第9〇9項所述之晶片封裝製程，其中 該些介電層的材質包括氮矽化合物。 913、 如申請專利範圍第9〇9項所述之晶片封裝製程，其中 該些介電層的材質包括氮氧矽化合物。 914、 如申請專利範圍第9〇9項所述之晶片封裝製程，其中 該些介電層的材質包括含矽、碳、氧與氫之化合物。/、 172 200814213 915、如申請專利範圍第9〇9項所述之晶片封裝製程，其中 該些介電層的材質包括氟矽玻璃（FlU0rinated以以咖 Glass) 〇 916、 如申請專利範圍第9〇9項所述之晶片封裝製程，其中 該些介電層的厚度係介於〇·3微米至2·5微米之間。 917、 如申請專利範圍第9〇3項所述之晶片封襄製程，其中 該保護層包括氧;5夕化合物。 918、 如申請專利範圍第903項所述之晶片封裝製程，其中 該保遵層包括氮石夕化合物。 919、 如申請專利範圍第9〇3項所述之晶片封裝製程，其中 該保護層包括氮氧矽化合物。 920、 如申請專利範圍第903項所述之晶片封裝製程，其中 該保護層的厚度係介於0.3微米至1.5微米（&quot;叫之間。 921、 如申請專利範圍第9〇3項所述之晶片封裝製程，其中 該接塾包括厚度介於〇·2微米至2微米之間的一銅層，且 該黏著/阻障層位在該銅層上。 922、 如申請專利範圍第go)項所述之晶片封裝製程，其中 該接塾包括厚度介於〇·2微米至2微米之間的一銘合金 層’且該黏著/阻障層位在該鋁合金層上。 923、 如申請專利範圍第9〇3項所述之晶片封裝製程，其中 該黏著/阻障層的材質包括鈦。 924、 如申請專利範圍第903項所述之晶片封裝製程，其中 該黏著/阻障層的材質包括鈦鎢合金。 925、 如申請專利範圍第9〇3項所述之晶片封裝製程，其中 173 200814213 該黏著/阻障層的材質包括氮化鈦。 926、 如申請專利範圍第9〇3項所述之晶片封 該黏著/阻障層的材質包括鉻。 W /、中 927、 如申請專利範圍第9〇3項所述之晶 該黏著/阻障層的材質包括组。 封裝製程，其中 =、+如中請專利範圍第9G3項所述之晶片封裝製程 該黏著/阻障層的材質包括氮化鈕。 /、中862. The chip package structure of claim 86, wherein the material containing the metal layer comprises copper and stone. 863. The chip package structure of claim 858, wherein the metal protective cover comprises a barrier layer having a thickness between 〇1 至1 μm and 0·7 μm. The exposed pad, and a thickness between 0.4 micrometers and 2 micrometers, is present on the barrier layer, and a portion of the metal trace is on the aluminum-containing metal layer. &quot; 864. The wafer package structure according to claim 863, wherein the material of the barrier layer comprises a crucible. 865 865. The chip package structure as claimed in claim 863, wherein the material of the barrier layer comprises titanium tungsten alloy. 866. The chip package structure of claim 863, wherein the material of the barrier layer comprises titanium nitride. &quot;8,867, the material of the barrier layer as described in claim 863, the material of the barrier layer comprises a chromium I&quot; package structure, wherein 868, the material of the barrier layer of the wafer according to claim 863 Includes buttons. 167 200814213 869. The wafer seal of claim 863, the material of the barrier layer comprises a nitride button. - 吉理, wherein 870, the wafer seal as described in claim 863, the material of the aluminum-containing metal layer comprises copper. , ー , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , The chip package structure of claim 831, wherein the metal circuit further comprises an adhesive/barrier layer and a sub-layer barrier layer, and the gold layer is located in the seed Above the layer. The adhesive/barrier layer material comprises titanium, and Y 8' is as described in claim 872, the wafer package is as described in claim 872. The material of the adhesion/barrier layer comprises a titanium-tungsten alloy. The chip package structure as described in claim 872 of the patent application, the material of the adhesion/barrier layer comprises titanium nitride. 876, #如中专利The chip package structure of the item m, wherein the material of the adhesion/barrier layer comprises chromium. /, 877. The material of the adhesive/barrier layer according to the invention of claim 872 comprises a group. The structure of the adhesion/barrier layer includes a nitride button. The wafer package described in claim 872, for example, is the wafer package structure described in claim 872. The thickness of the viscous/barrier layer is between 3 micrometers and imaginary micrometers. The wafer package structure as described in claim 872, Fuzhong 168 200814213 The material of the seed layer Is gold, and the gold layer is in the species 881. The chip package structure of claim 872, wherein the seed layer is made of copper and the metal line further comprises a copper layer on the seed layer and a nickel layer. The gold layer is on the nickel layer. The wafer package structure of claim 831, wherein the gold layer has a thickness of between 1 micrometer and 2 micrometers. The chip package structure of claim 831, wherein the thickness of the gold layer is between 3 micrometers and 5 micrometers. 884. The wafer package structure of claim 831, wherein The thickness of the metal line is between 1 micrometer and 2 micrometers. 885. The chip package structure of claim 831, wherein the metal line has a thickness of between 3 micrometers and 5 micrometers. 886. The chip package structure of claim 831, wherein the wire bonding material comprises gold. 887. The chip package structure of claim 831, wherein the wire diameter is between </ RTI> </ RTI> </ RTI> </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; The wafer package structure, wherein the material of the polymer material comprises a polyimine (PI). The wafer package structure according to claim 831, wherein the material of the polymer layer material comprises benzene. 851. The wafer package structure of claim 831, wherein the thickness of the polymer material is between 250 micrometers and 1, 〇〇〇 micron gate 169 200814213 892, such as The wafer package structure of claim 831, wherein the position of the wire bonding the gold layer is different from the position of the pad from a top perspective view. 893. The wafer package structure of claim 831, further comprising a polymer layer on the protective layer, wherein a polymer layer opening in the polymer layer exposes the pad, A metal line is positioned on the polymer layer and connected to the pad through the polymer layer opening. 894. The wafer package structure of claim 893, wherein the material of the polymer layer comprises polyimine (PI). 895. The chip package structure of claim 893, wherein the material of the polymer layer comprises an epoxy. 896. The wafer package structure of claim 893, wherein the material of the polymer layer comprises phenylcyclobutene (BCB). 897. The wafer package structure of claim 893, wherein the polymer layer has a thickness between 3 microns and 25 microns. The chip package structure of claim 831, further comprising a polymer layer on the metal line, and a polymer layer opening in the polymer layer exposing the gold layer, A wire conductor engages the gold layer through the polymer layer opening. 899. The wafer package structure of claim 898, wherein the polymer layer comprises a polyimine (PI). The chip package structure of claim 8, wherein the material of the polymer layer comprises epoxy. 901. The chip package structure of claim 898, wherein the material of the polymer layer comprises phenylcyclobutene (BCB). 902. The wafer package structure of claim 898, wherein the polymer layer has a thickness between 3 microns and 25 microns. 903. A wafer packaging process, the method comprising: providing a semiconductor wafer, comprising: a semiconductor substrate; a wiring structure positioned above the semiconductor substrate; a protective layer positioned above the wiring structure and located at One of the openings in the protective layer exposes one of the pads of the circuit structure; an adhesive/barrier layer is located above the interface of the opening exposed by the opening, and a sub-layer is located at the bonding And a metal layer on the seed layer; bonding the semiconductor wafer to a first surface of a substrate by using an adhesive material; forming a wire bonding wire to bond the metal layer and the substrate; i forming a a polymer material on the first surface and covering the semiconductor wafer and the wire bonding wire; and forming a lead-free solder on a second surface of the substrate at a temperature of 230 ° C A reflow process is performed up to 260 ° C to form a lead-free solder ball. 904. The wafer packaging process of claim 903, wherein the semiconductor substrate comprises germanium. 905. The wafer packaging process of claim 903, further comprising 171 200814213 including at least one metal oxide semiconductor (MOS) device located in or above the semiconductor substrate. 906. The wafer packaging process of claim 903, wherein the wiring structure comprises a copper layer having a thickness between 2 and 2 microns. 907. The wafer packaging process of claim 9, wherein the wiring structure comprises electroplated copper. 908. The wafer packaging process of claim 9, wherein the circuit structure comprises a metal layer having a thickness between 0.2 micrometers and 2 micrometers. 909. The chip packaging process of claim 903, further comprising a plurality of dielectric layers between the semiconductor substrate and the protective layer, and wherein the plurality of patterned metal layers of the circuit structure are The patterned metal layers of the two layers are connected between the electrical layers and through a plurality of metal plugs of the wiring structure located in the dielectric layers. 910. The wafer packaging process of claim 9, wherein the dielectric layers have a dielectric constant value (k) between 1.5 and 3. k ' 911. The wafer encapsulation as described in claim 909. The material of the dielectric layers includes an oxonium compound. 8. The chip packaging process of claim 9, wherein the material of the dielectric layer comprises a nitrogen bismuth compound. 913. The wafer packaging process of claim 9, wherein the material of the dielectric layer comprises a oxynitride compound. 914. The wafer packaging process of claim 9, wherein the dielectric layers comprise a compound comprising ruthenium, carbon, oxygen and hydrogen. 172. The method of claim 1, wherein the material of the dielectric layer comprises fluorocarbon glass (FlO0rinated to Coffee Glass) 916, as claimed in claim 9 The chip packaging process of claim 9, wherein the dielectric layers have a thickness between 〇3 μm and 2.5 μm. 917. The wafer packaging process of claim 9, wherein the protective layer comprises oxygen; 918. The wafer packaging process of claim 903, wherein the protective layer comprises a Nitrogen compound. 919. The wafer packaging process of claim 9, wherein the protective layer comprises a oxynitride compound. 920. The wafer packaging process of claim 903, wherein the protective layer has a thickness of between 0.3 micrometers and 1.5 micrometers (between &quot; 921, as described in claim 9/3 of the patent application scope. a wafer packaging process, wherein the interface comprises a copper layer having a thickness between 2 μm and 2 μm, and the adhesion/barrier layer is on the copper layer. 922, as claimed in the specification. The wafer packaging process of claim 1, wherein the interface comprises an alloy layer of thickness between 〇2 μm and 2 μm and the adhesion/barrier layer is on the aluminum alloy layer. 923. The wafer packaging process of claim 9, wherein the material of the adhesion/barrier layer comprises titanium. 924. The wafer packaging process of claim 903, wherein the material of the adhesion/barrier layer comprises a titanium tungsten alloy. 925. The wafer packaging process of claim 9, wherein the material of the adhesion/barrier layer comprises titanium nitride. 926. The wafer seal of claim 9 or 3, wherein the adhesive/barrier layer comprises chromium. W /, 927, as described in the scope of claim 9 〇 3, the material of the adhesion / barrier layer includes a group. The packaging process, wherein =, +, as described in the patent scope of the invention, the chip packaging process of the 9G3 item, the material of the adhesion/barrier layer comprises a nitride button. /,in 929、奸如申請專利範圍第9〇3項所述之晶片封裝製程，其 該黏著/阻障層的厚度係介於〇 〇3微米至〇 f •’儆木之間。 〇、如申請專利範圍第903項所述之晶片封装製程， 該種子層的材質為金。 ^ T 931、 如申請專利範圍第9〇3項所述之晶片封裝製程，其中 該種子層的材質為銅。 八 932、 如申請專利範圍第9〇3項所述之晶片封裝製程，其中 該種子層的厚度係介於〇 〇3微米至〇·7微米之間。 933、 如申請專利範圍第9〇3項所述之晶片封裝製程，其中 該金屬層包括厚度介於！微米至2〇微米之間的一金層^在 ^子層上，且該種子層的材質為金，該打線導線接合該 34如申請專利範圍第903項所述之晶片封裝製程，其中 該金屬層包括厚度介於3微米至5微米之間的—金層;立在 b種子層上，且該種子層的材質為金，該打線導線接合該 金層。 人 935、如申請專利範圍第9〇3項所述之晶片封裝製程，其中 174 200814213 該金屬層包括-鋼層位在該種子層上、—錄 上以及-金層位在該鎳層上，且該種子層心：銅層 打線導線接合該金層。 貝為鋼，該 936、如申請專利範圍第9〇3項所述之晶 該金屬層包括-鋼層位在難子層上、_鋅/|程，其中 上以及-纪層位在該鎳層上，且該種子層的c層 打線導線接合該鈀層。 貝為鋼，該 937、 如申請專利範圍第9〇3項所述之晶片封 該金屬層的厚度係介於1微米至20微米之間。 八 938、 如申請專利範圍第9〇3項所述之晶片封裝製程， 該金屬層的厚度係介於3微米至5微米之間。主’/、中 939、 如申請專利範圍第9〇3項所述之晶片封裝製程 括一金屬保護蓋位在該開口所暴露出之該接墊上 匕 著/阻障層位在該金屬保護蓋上。 ，且該黏 940、如申請專利範圍第939項所述之晶片封裝 該接塾為銅塾。 ·/、中 941、 如申請專利範圍第939項所述之晶片封裝製程，其中 該金屬保護蓋包括厚度介於〇·4微米至2 ’、 双木之間的一含 鋁金屬層位在該開口所暴露出之該接墊上， 及該黏著/阻障 層位在該含銘金屬層上。 942、 如申請專利範圍第941項所述之晶片封裝製程，其 該含銘金屬層的材質包括銅。 943、如申請專利範圍第941項所述之晶片封裝製程，其中 該含鋁金屬層的材質包括銅與石夕。 175 200814213 944、如申請專利範圍第939項所述之晶片封裝製程，其中 該金屬保護蓋包括厚度介於〇·〇1微米至0·7微米之間的一 阻障層（barrier layerMi在該開口所暴露出之該接墊上，、 及^度介於0.4微米至2微米之間的―含叙金屬層位在= 阻P早層上，且該黏著/阻障層位在該含銘金屬居上。 945、如申請專利範圍第944項所述之晶片封裝製程，豆 該阻障層的材質包括鈦。 &quot;、中 946、 如申請專利範圍第944項所述之晶片封裝製程，其 該阻障層的材質包括鈦鎢合金。 〃 947、 如申請專利範圍第944項所述之晶片封裝製程，其 該阻P爭層的材質包括氮化鈦。 948、 如申請專利範圍第944項所述之晶片 J衣裂程，盆Φ 該阻障層的材質包括鉻。 八 949、如申請專利範圍第944項所述之晶片封。 該阻障層的材質包括鈕。 程’其中 950、 如申請專利範圍第944項所述之晶片封事製^盆 該阻障層的材質包括氮化鈕。 八中 951、 如申請專利範圍第944項所述之晶片封 程，_甘 該含鋁金屬層的材質包括銅。 /、 952、 如申請專利範圍第944項所述之晶片封裝製程豆 該含銘金屬層的材質包括銅與石夕。 中 953 如申請專利範圍第903項所述之晶片封穿製 該黏著/阻障層位在該開口所暴露出該線路鈇耘其中 上方以及位在該保護層上方。 ％之該接塾 176 200814213 954、 如申請專利範圍第903項所述之晶片封裝製程，其中 該基板為球型柵狀陣列（BGA)基板。 955、 如申請專利範圍第903項所述之晶片封裝製程，其中 該基板為含有玻璃纖維與環氧樹脂的基板。 956、 如申請專利範圍第903項所述之晶片封裝製程，其中 該基板為玻璃基板。 957、 如申請專利範圍第903項所述之晶片封裝製程，其中 該基板為矽基板。 958、 如申請專利範圍第903項所述之晶片封裝製程，其中 該基板為陶瓷基板。 959、 如申請專利範圍第903項所述之晶片封裝製程，其中 該基板為有機基板。 960、 如申請專利範圍第903項所述之晶片封裝製程，其中 該基板為金屬基板。 961、 如申請專利範圍第903項所述之晶片封裝製程，其中 該基板為金屬基板，且該金屬基板的材質包括鋁。 962、 如申請專利範圍第903項所述之晶片封裝製程，其中 該基板為金屬基板，且該金屬基板的材質包括銅。 963、 如申請專利範圍第903項所述之晶片封裝製程，其中 該基板的厚度係介於200微米至2,000微米之間。 964、 如申請專利範圍第903項所述之晶片封裝製程，其中 該利用該黏著材料黏著該半導體晶片的步驟包括利用厚度 介於1微米至50微米之間的聚醯亞胺（PI)黏著該半導體晶 片至該第一表面。 177 200814213 965、如申請專利範圍第9〇3項所述之晶片封裝製程，其中 該利用該黏著材料黏著該半導體日日日片的步驟包括利用厚度 介於1微米至5G微米之間的環氧樹脂（epoxy resin)黏著該 半導體晶片至該第一表面。 μ 966、如申請專利_第9〇3項所述之晶片封裂製程，其中 該打線導線的材質包括金。 ’、 967、 如申請專利範圍第9〇3項所述之晶片封裳製程，其中 該打線導線的直徑介於2〇微米至50微米之間。 968、 如申請專利範圍第9〇3項所述之晶片封裝製程，其中 該形成該聚合物材料的步驟包括一灌膜製程 process) ° 969、 如申請專利範圍第9〇3項所述之晶片封裝製程，其中 該形成該聚合物材料的步驟包括利用灌膜製程形成厚度介 於250微米至1，〇〇〇微米之間的聚醯亞胺（pi)在該第一表面 上，並覆蓋該半導體晶片與該打線導線。 970、 如申請專利範圍第9〇3項所述之晶片封裴製程，其中 該形成該聚合物材料的步驟包括利用灌膜製程形成厚度介 於250微米至1，〇〇〇微米之間的苯基環丁烯（BCB)在該第一 表面上，並覆蓋該半導體晶片與該打線導線。 971、 如申請專利範圍第903項所述之晶片封裝製程，其中 該形成該聚合物材料的步驟包括利用灌膜製程形成厚度介 於250微米至1，〇〇〇微米之間且含有環氧樹脂（ep〇Xy)的聚 合物材料在該第一表面上，並覆蓋該半導體晶片與該打線 導線。 178 200814213 972、 如申請專利範圍第903項所述之晶片封裝製程，其中 該形成該無鉛銲料的步驟包括一植球製程（ball planting process) 〇 973、 如申請專利範圍第903項所述之晶片封裝製程，其中 該形成該無鉛銲料的步驟包括一網版印刷製程（screen printing process) 〇 974、 如申請專利範圍第903項所述之晶片封裝製程，其中 該迴銲製程的時間係介於5秒至90秒之間。 975、 如申請專利範圍第903項所述之晶片封裝製程，其中 該迴銲製程的時間係介於20秒至40秒之間。 976、 如申請專利範圍第903項所述之晶片封裝製程，其中 該無錯錫球的材質包括錫銀合金（tin-silver alloy)。 977、 如申請專利範圍第903項所述之晶片封裝製程，其中 該無錯錫球的材質包括錫銀銅合金（tin-silver-copper alloy) ° 978、 如申請專利範圍第903項所述之晶片封裝製程，其中 該無鉛錫球的直徑介於0.25釐米至1.2釐米（mm)之間。 979、 如申請專利範圍第903項所述之晶片封裝製程，其中 在該形成該無鉛錫球之後，更包括切割該基板與該聚合物 材料。 980、 如申請專利範圍第903項所述之晶片封裝製程，其中 在該形成該無鉛錫球之後，更包括機械切割該基板與該聚 合物材料。 179929. The wafer packaging process as described in claim 9/3, wherein the thickness of the adhesion/barrier layer is between 〇3 μm and 〇f •’ eucalyptus. For example, in the wafer packaging process described in claim 903, the seed layer is made of gold. ^ T 931. The wafer packaging process of claim 9, wherein the seed layer is made of copper. </ RTI> </ RTI> </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; 933. The wafer packaging process as described in claim 9-3, wherein the metal layer comprises a thickness of between! a gold layer between 2 μm and 2 μm, and the seed layer is made of gold, and the wire bonding wire is bonded to the wafer packaging process as described in claim 903, wherein the metal The layer includes a gold layer having a thickness between 3 microns and 5 microns; standing on the b seed layer, and the seed layer is made of gold, and the wire bond joins the gold layer. 935. The wafer packaging process of claim 9, wherein the metal layer comprises a steel layer on the seed layer, a recording layer, and a gold layer on the nickel layer. And the seed layer core: a copper layer wire bonding the gold layer. The shell metal, the 936, as described in the scope of the patent application, the metal layer includes: a steel layer on the hard layer, _ zinc / | process, wherein the upper and the - layer in the nickel On the layer, and the c-layer wire of the seed layer joins the palladium layer. The steel sheet is as described in claim 9/3, and the thickness of the metal layer is between 1 micrometer and 20 micrometers. </ RTI> </ RTI> </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; The main package assembly of the present invention, as described in claim 9/3, includes a metal protective cover on the pad exposed by the opening, and a barrier layer is disposed on the metal protective cover. on. And the adhesive 940, such as the wafer package described in claim 939, is a copper crucible. The wafer packaging process of claim 939, wherein the metal protective cover comprises an aluminum-containing metal layer having a thickness of between 4 micrometers and 2', and between the double woods. The pad exposed by the opening, and the adhesion/barrier layer are on the metal layer containing the inscription. 942. The wafer packaging process of claim 941, wherein the material of the metal layer comprises copper. 943. The wafer packaging process of claim 941, wherein the material of the aluminum-containing metal layer comprises copper and stone. 175. The chip packaging process of claim 939, wherein the metal protective cover comprises a barrier layer having a thickness between 1 micrometer and 0. 7 micrometers (the barrier layer Mi is in the opening) The exposed metal layer on the exposed pad, between 0.4 μm and 2 μm, is on the early layer of the resist P, and the adhesion/barrier layer is in the 945. The wafer encapsulation process of claim 944, wherein the material of the barrier layer comprises titanium. &quot;, 946, the wafer packaging process as described in claim 944, The material of the barrier layer comprises a titanium-tungsten alloy. 947 947. The wafer packaging process as described in claim 944, wherein the material of the resist layer comprises titanium nitride. 948, as claimed in claim 944 The wafer J is cracked, and the material of the barrier layer is chrome. The 940 is a wafer seal as described in claim 944. The material of the barrier layer includes a button. Patent Application No. 944 The material of the barrier layer includes a nitride button. 八中951, such as the wafer sealing process described in claim 944, the material of the aluminum-containing metal layer includes copper. /, 952, such as The wafer packaging process described in claim 944 includes the material of the metal layer including copper and shixi. The medium 953 is sealed as described in claim 903, and the adhesion/barrier layer is The opening is exposed to the upper side of the line and above the protective layer. The substrate is a chip package process as described in claim 903, wherein the substrate is a spherical grid. 955. The wafer packaging process of claim 903, wherein the substrate is a substrate comprising a glass fiber and an epoxy resin. 956. The chip package of claim 903 The process of the present invention, wherein the substrate is a glass substrate. 957. The wafer packaging process of claim 903, wherein the substrate is a germanium substrate. 958, as claimed in claim 903 The wafer packaging process, wherein the substrate is a ceramic substrate. 959. The wafer packaging process of claim 903, wherein the substrate is an organic substrate. 960. The wafer packaging process as described in claim 903 The substrate is a metal substrate. The wafer packaging process of claim 903, wherein the substrate is a metal substrate, and the material of the metal substrate comprises aluminum. 962, as claimed in claim 903 In the wafer packaging process, the substrate is a metal substrate, and the material of the metal substrate comprises copper. 963. The wafer packaging process of claim 903, wherein the substrate has a thickness between 200 microns and 2,000 microns. 964. The wafer packaging process of claim 903, wherein the step of bonding the semiconductor wafer with the adhesive material comprises bonding the polyimide (PI) having a thickness between 1 micrometer and 50 micrometers. A semiconductor wafer to the first surface. 177. The method of claim 1, wherein the step of adhering the semiconductor day and day sheets with the adhesive material comprises using an epoxy having a thickness between 1 micrometer and 5 nanometers. An epoxy resin adheres the semiconductor wafer to the first surface. The chip-cracking process of claim 9, wherein the wire bonding material comprises gold. </ RTI> </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; 968. The wafer packaging process of claim 9, wherein the step of forming the polymer material comprises a film processing process, 969, the wafer according to claim 9 (3) a packaging process, wherein the step of forming the polymer material comprises forming a polyimine (pi) having a thickness between 250 μm and 1 μm on the first surface by a film filling process and covering the A semiconductor wafer and the wire bonding wire. 970. The wafer packaging process of claim 9, wherein the step of forming the polymer material comprises forming a benzene having a thickness between 250 micrometers and 1 micrometer by using a film filling process. A cyclobutene (BCB) is on the first surface and covers the semiconductor wafer and the wire. 971. The wafer packaging process of claim 903, wherein the step of forming the polymer material comprises forming a thickness between 250 micrometers and 1 micrometer and using an epoxy resin by using a film filling process. The polymer material of (ep〇Xy) is on the first surface and covers the semiconductor wafer and the wire bonding wire. 178. The chip packaging process of claim 903, wherein the step of forming the lead-free solder comprises a ball planting process 〇 973, the wafer of claim 903 a packaging process, wherein the step of forming the lead-free solder comprises a screen printing process 974, the wafer packaging process as described in claim 903, wherein the time of the reflow process is between 5 Between seconds and 90 seconds. 975. The wafer packaging process of claim 903, wherein the reflow process is between 20 seconds and 40 seconds. 976. The wafer packaging process of claim 903, wherein the material of the error-free solder ball comprises a tin-silver alloy. 977. The wafer packaging process of claim 903, wherein the material of the error-free solder ball comprises a tin-silver-copper alloy 978, as described in claim 903. A wafer packaging process wherein the lead-free solder balls have a diameter between 0.25 cm and 1.2 cm. 979. The wafer packaging process of claim 903, wherein after the forming the lead-free solder ball, the substrate and the polymer material are further cut. 980. The wafer packaging process of claim 903, wherein after the forming the lead-free solder ball, further comprising mechanically cutting the substrate and the polymer material. 179
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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103715109A (en) * 2012-10-04 2014-04-09 德州仪器公司 Packaged IC having printed dielectric adhesive on die pad
US9536821B2 (en) 2009-04-16 2017-01-03 Renesas Electronics Corporation Semiconductor integrated circuit device having protective split at peripheral area of bonding pad and method of manufacturing same
US10340259B2 (en) 2015-05-14 2019-07-02 Mediatek Inc. Method for fabricating a semiconductor package
US10685943B2 (en) 2015-05-14 2020-06-16 Mediatek Inc. Semiconductor chip package with resilient conductive paste post and fabrication method thereof

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI745213B (en) * 2021-01-06 2021-11-01 南茂科技股份有限公司 Semiconductor package structure and manufacturing method thereof

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6376353B1 (en) * 2000-07-03 2002-04-23 Chartered Semiconductor Manufacturing Ltd. Aluminum and copper bimetallic bond pad scheme for copper damascene interconnects
US7067918B2 (en) * 2003-03-18 2006-06-27 Ngk Spark Plug Co., Ltd. Wiring board
JP4405246B2 (en) * 2003-11-27 2010-01-27 スリーエム イノベイティブ プロパティズ カンパニー Manufacturing method of semiconductor chip
TWI236722B (en) * 2004-07-09 2005-07-21 Megic Corp Chip structure
TWI242847B (en) * 2004-08-18 2005-11-01 United Microelectronics Corp Chip covered with polymer and electrical package structure including the same

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9536821B2 (en) 2009-04-16 2017-01-03 Renesas Electronics Corporation Semiconductor integrated circuit device having protective split at peripheral area of bonding pad and method of manufacturing same
TWI578474B (en) * 2009-04-16 2017-04-11 Renesas Electronics Corp Semiconductor integrated circuit device and method for manufacturing semiconductor integrated circuit device
CN103715109A (en) * 2012-10-04 2014-04-09 德州仪器公司 Packaged IC having printed dielectric adhesive on die pad
CN103715109B (en) * 2012-10-04 2018-11-09 德州仪器公司 There is the encapsulation IC of printing dielectric adhesive in die pad
US10340259B2 (en) 2015-05-14 2019-07-02 Mediatek Inc. Method for fabricating a semiconductor package
US10685943B2 (en) 2015-05-14 2020-06-16 Mediatek Inc. Semiconductor chip package with resilient conductive paste post and fabrication method thereof

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