TWI395275B - Chip package and method for fabricating the same - Google Patents

Chip package and method for fabricating the same Download PDF

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Publication number
TWI395275B
TWI395275B TW096133091A TW96133091A TWI395275B TW I395275 B TWI395275 B TW I395275B TW 096133091 A TW096133091 A TW 096133091A TW 96133091 A TW96133091 A TW 96133091A TW I395275 B TWI395275 B TW I395275B
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Taiwan
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layer
micrometers
thickness
metal
copper
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TW096133091A
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Chinese (zh)
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TW200814213A (en
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Mou Shiung Lin
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Megica Corp
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93Batch processes
    • H01L2224/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01013Aluminum [Al]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01029Copper [Cu]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/014Solder alloys
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

A method for fabricating chip package includes providing a semiconductor chip with a bonding pad, comprising an adhesion/barrier layer, connected to a pad through an opening in a passivation layer, next adhering the semiconductor chip to a substrate using a glue material, next bonding a wire to the bonding pad and to the substrate, forming a polymer material on the substrate, covering the semiconductor chip and the wire, next forming a lead-free solder ball on the substrate, and then cutting the substrate and polymer material to form a chip package.

Description

晶片封裝結構及其製程Chip package structure and its process

本發明係有關一種結構及其製程,特別是有關一種晶片封裝結構及其製程。The present invention relates to a structure and process thereof, and more particularly to a wafer package structure and process thereof.

打線接合(wire bonding)是用來使半導體晶片(semiconductor chip)向外連接外部電路的技術之一,此技術是先將半導體晶片固定於基板(例如印刷電路板)或導線架(lead frame)上,再以細金屬線(或稱打線導線)使半導體晶片與導線架的引腳電性連接或是使半導體晶片與基板的線路電性連接。Wire bonding is one of the techniques used to connect a semiconductor chip to an external circuit. The technique is to first fix the semiconductor wafer on a substrate (such as a printed circuit board) or a lead frame. Then, the thin metal wire (or wire bonding wire) is used to electrically connect the semiconductor chip to the lead of the lead frame or electrically connect the semiconductor chip to the circuit of the substrate.

請參閱第1圖所示,習知球型柵狀陣列(Ball Grid Array,BGA)封裝技術係利用一金線(gold wire)110接合一半導體晶片112之一鋁金屬保護蓋(aluminum cap)114與一球型柵狀陣列基板116的一接點,其中鋁金屬保護蓋114係位在保護層(passivation layer)118內之一開口118a所暴露出的一銅墊(copper pad)120上,因此銅墊120透過金線110電性連接球型柵狀陣列基板116的線路,進而與接合球型柵狀陣列基板116的錫球(solder ball)122電性連接。Referring to FIG. 1 , a conventional Ball Grid Array (BGA) packaging technology uses a gold wire 110 to bond an aluminum cap 114 and a semiconductor chip 112 . A contact of the spherical grid array substrate 116, wherein the aluminum metal protective cover 114 is fastened to a copper pad 120 exposed by one of the openings 118a in the passivation layer 118, thus the copper pad The 120 is electrically connected to the ball grid array substrate 116 through the gold wire 110, and is electrically connected to the solder ball 122 of the ball grid array substrate 116.

惟,習知金線接合鋁金屬保護蓋的打線技術,容易在後續的組裝製程(assembly process)中以及無鉛錫球(lead-free solder ball)製程中,因高溫而使金線的金原子與 鋁墊或鋁金屬保護蓋的鋁金屬形成介金屬化合物(intermetallic compound,IMC),進而造成結構的脆化並影響結構的可靠度。另,在產品化之後,金線與半導體晶片亦容易在高功率的使用情況下產生高熱,進而使金線的金原子與鋁墊或鋁金屬保護蓋的鋁金屬形成介金屬化合物(IMC),以造成結構的脆化並影響結構的可靠度。However, the wire bonding technology of the conventional gold wire joint aluminum metal protective cover is easy to make the gold atom of the gold wire due to the high temperature in the subsequent assembly process and the lead-free solder ball process. The aluminum metal of the aluminum pad or the aluminum metal protective cover forms an intermetallic compound (IMC), which causes embrittlement of the structure and affects the reliability of the structure. In addition, after the productization, the gold wire and the semiconductor wafer are also prone to generate high heat under high power use, and the gold atom of the gold wire forms a metal intermetallic compound (IMC) with the aluminum metal of the aluminum pad or the aluminum metal protective cover. To cause embrittlement of the structure and affect the reliability of the structure.

本發明之一目的,係在提供一種晶片封裝結構及其製程,其可防止金線的金原子與鋁墊或鋁金屬保護蓋的鋁金屬形成介金屬化合物(IMC)。It is an object of the present invention to provide a wafer package structure and process thereof that prevents gold atoms of a gold wire from forming a metal intermetallic compound (IMC) with an aluminum pad of an aluminum pad or an aluminum metal protective cover.

為了上述之目的,本發明提出一種晶片封裝結構,其係包括一基板;一無鉛錫球(lead-free solder ball),接合該基板;一黏著材料,位在該基板上;一半導體晶片,位在該黏著材料上,且該半導體晶片包括含有黏著/阻障層之一打線接墊位在保護層之一開口所暴露出之一接墊上方;一打線導線,接合該打線接墊與該基板;以及一聚合物材料,位在該基板上,並覆蓋該半導體晶片與該打線導線。For the above purposes, the present invention provides a chip package structure comprising a substrate; a lead-free solder ball bonded to the substrate; an adhesive material positioned on the substrate; a semiconductor wafer, On the adhesive material, the semiconductor wafer includes a bonding pad having an adhesion/barrier layer positioned over one of the pads exposed by one of the openings of the protective layer; a wire bonding wire bonding the bonding pad and the substrate And a polymer material positioned on the substrate and covering the semiconductor wafer and the wire bonding wire.

為了上述之目的,本發明提出一種晶片封裝結構,其係包括一基板;一無鉛錫球,接合該基板;一黏著材料,位在該基板上;一半導體晶片,位在該黏著材料上,且該半導體晶片包括含有黏著/阻障層之一打線接點;一打線導線,接合該打線接點與該基板;以及一聚合物材料,位在該基板上,並覆蓋該半導體晶片與該打線導線。For the above purpose, the present invention provides a chip package structure comprising a substrate; a lead-free solder ball bonded to the substrate; an adhesive material positioned on the substrate; and a semiconductor wafer positioned on the adhesive material, and The semiconductor wafer includes a wire bonding contact including an adhesion/barrier layer; a wire bonding wire bonding the wire bonding node and the substrate; and a polymer material disposed on the substrate and covering the semiconductor wafer and the wire bonding wire .

為了上述之目的,本發明提出一種晶片封裝結構,其係包括一導線架(lead frame),包括一晶片承載座與一引腳;一黏著材料,位在該晶片承載座上;一半導體晶片,位在該黏著材料上,且該半導體晶片包括含有黏著/阻障層之一打線接墊位在保護層之一開口所暴露出之一接墊上方;一打線導線,接合該打線接墊與該引腳;以及一聚合物材料,包覆該晶片承載座、該半導體晶片、該打線導線與部份之該引腳。For the above purpose, the present invention provides a chip package structure including a lead frame including a wafer carrier and a pin, an adhesive material on the wafer carrier, and a semiconductor wafer. Positioned on the adhesive material, and the semiconductor wafer includes a bonding pad having one of the adhesion/barrier layers positioned over one of the pads exposed by one of the openings of the protective layer; a wire bonding wire bonding the wire bonding pad and the wire bonding pad a pin; and a polymer material covering the wafer carrier, the semiconductor wafer, the wire bonding wire and a portion of the pin.

為了上述之目的,本發明提出一種晶片封裝結構,其係包括含有一晶片承載座與一引腳的一導線架;一黏著材料,位在該晶片承載座上;一半導體晶片,位在該黏著材料上,且該半導體晶片包括含有黏著/阻障層之一打線接點;一打線導線,接合該打線接點與該引腳;以及一聚合物材料,包覆該晶片承載座、該半導體晶片、該打線導線與部份之該引腳。For the above purposes, the present invention provides a chip package structure including a lead frame including a wafer carrier and a lead; an adhesive material on the wafer carrier; and a semiconductor wafer positioned on the bond In the material, the semiconductor wafer includes a wire bonding contact including an adhesion/barrier layer; a wire bonding wire bonding the wire bonding contact and the pin; and a polymer material covering the wafer carrier and the semiconductor wafer , the wire conductor and part of the pin.

為了上述之目的,本發明提出一種晶片封裝製程,其步驟包括提供一半導體晶片,其係包括含有黏著/阻障層之一打線接墊位在保護層之一開口所暴露出的一接墊上方;利用一黏著材料黏著該半導體晶片至一基板的一第一表面;形成一打線導線接合該打線接墊與該基板的一接點;形成一聚合物材料在該第一表面上,並覆蓋該半導體晶片與該打線導線;形成一無鉛銲料(lead-free solder)在該基板之一第二表面上,並在溫度介於230℃至260℃之間進行一迴銲(reflow)製程,以形成一無鉛錫球(lead-free solder ball);以及切割基板與聚合物材料,以形成晶片封裝結構。For the above purposes, the present invention provides a wafer packaging process including the steps of providing a semiconductor wafer comprising a bonding pad having an adhesion/barrier layer positioned over a pad exposed by an opening in one of the protective layers Adhering the semiconductor wafer to a first surface of a substrate by using an adhesive material; forming a wire bonding wire to bond the wire bonding pad to the substrate; forming a polymer material on the first surface and covering the a semiconductor wafer and the wire bonding wire; forming a lead-free solder on a second surface of the substrate, and performing a reflow process at a temperature between 230 ° C and 260 ° C to form a lead-free solder Lead-free solder Ball); and cutting the substrate and the polymer material to form a wafer package structure.

底下藉由具體實施例配合所附的圖式詳加說明,當更容易瞭解本發明之目的、技術內容、特點及其所達成之功效。The purpose, technical contents, features and effects achieved by the present invention will be more readily understood by the detailed description of the embodiments and the accompanying drawings.

請參閱第2A圖所示,一半導體基底2(或稱為積體電路基底,IC substrate)比如是矽基底、砷化鎵(GaAs)基底或矽化鍺(SiGe)基底,另外半導體基底2也可以是一空白晶圓(blank wafer),而此空白晶圓比如是矽晶圓(silicon wafer)、砷化鎵晶圓或矽化鍺晶圓。複數半導體元件4位在半導體基底2內或上方,而這些半導體元件4包括記憶體、邏輯元件、被動元件(例如電阻、電容或電感)或主動元件等,其中主動元件比如是金氧半導體(MOS)元件,此金氧半導體元件例如是p通道金氧半導體元件(p-channel MOS devices)、n通道金氧半導體元件(n-channel MOS devices)、雙載子互補式金氧半導體元件(BiCMOS devices)、雙載子連接電晶體(Bipolar Junction Transistor,BJT)或互補金屬氧化半導體(CMOS)。另,「上方」一詞在本發明中是表示位在某物上面並與之接觸,或是表示位在某物上面但未與之接觸。Referring to FIG. 2A, a semiconductor substrate 2 (or an IC substrate), such as a germanium substrate, a gallium arsenide (GaAs) substrate, or a germanium telluride (SiGe) substrate, may also be used. It is a blank wafer, such as a silicon wafer, a gallium arsenide wafer, or a germanium telluride wafer. The plurality of semiconductor elements 4 are located in or above the semiconductor substrate 2, and the semiconductor elements 4 include a memory, a logic element, a passive element (such as a resistor, a capacitor or an inductor) or an active element, etc., wherein the active element is, for example, a metal oxide semiconductor (MOS). The MOS device is, for example, a p-channel MOS device, an n-channel MOS device, or a bi-carrier complementary MOS device (BiCMOS devices). ), Bipolar Junction Transistor (BJT) or Complementary Metal Oxide Semiconductor (CMOS). In addition, the term "above" in the present invention means that it is located on and in contact with something, or that it is located on something but not in contact with it.

一線路結構6位在半導體基底2上方,並連接這些半導體元件4。線路結構6可以是由複數圖案化金屬層8(其厚度t1比如是小於3微米,例如是介於0.2微米至2微米 之間)與複數金屬插塞(metal plug)10所構成。例如,這些圖案化金屬層8與這些金屬插塞10的材質主要是銅,亦即圖案化金屬層8可以是厚度小於3微米(比如是介於0.2微米至2微米之間)的一銅層;或是,這些圖案化金屬層8的材質主要是含鋁金屬(如鋁或鋁合金),而這些金屬插塞10的材質主要是鎢,也就是說圖案化金屬層8可以是厚度小於3微米(比如是介於0.2微米至2微米之間)的一含鋁金屬層。此外,形成線路結構6的方式包括濺鍍製程(sputtering process)、鑲嵌製程(damascene process)或電鍍製程(electroplating process)等。A wiring structure 6 is placed over the semiconductor substrate 2, and these semiconductor elements 4 are connected. The line structure 6 may be a plurality of patterned metal layers 8 (having a thickness t1 such as less than 3 microns, for example between 0.2 microns and 2 microns Between) and a plurality of metal plugs 10 are formed. For example, the patterned metal layer 8 and the metal plug 10 are mainly made of copper, that is, the patterned metal layer 8 may be a copper layer having a thickness of less than 3 micrometers (for example, between 0.2 micrometers and 2 micrometers). Or, the material of the patterned metal layer 8 is mainly aluminum-containing metal (such as aluminum or aluminum alloy), and the material of the metal plug 10 is mainly tungsten, that is, the patterned metal layer 8 can be less than 3 An aluminum-containing metal layer of micron (such as between 0.2 microns and 2 microns). Further, the manner of forming the wiring structure 6 includes a sputtering process, a damascene process, or an electroplating process.

例如以鑲嵌製程而言,形成線路結構6的方式包括利用化學氣相沉積(Chemical Vapor Deposition,CVD)的方式沈積一第一介電層(dielectric layer)在一第二介電層的上表面上,其中第一介電層的材質與第二介電層的材質包括有氮氧矽化合物與介電常數值(k)介於1.5至3之間的材質;接著,形成一第一光阻層在第一介電層上,並利用位在第一光阻層內的第一光阻層開口蝕刻第一介電層,以暴露出第二介電層而形成溝渠;於形成溝渠之後,去除此第一光阻層;繼續,形成一第二光阻層在第一介電層上與溝渠所暴露出之第二介電層上,且位在第二光阻層內之第二光阻層開口暴露出第二介電層;再來,去除第二光阻層開口所暴露出之第二介電層而形成導通孔,並在形成導通孔之後,去除第二光阻層。因此,由溝渠與導通孔所組成的開口形成在第一介電層內與第二介電層內。接著,利用濺 鍍或化學氣相沉積的方式沈積一阻障層在此開口內的下表面與側壁上以及第一介電層的上表面上,其中此阻障層的材質係選自鉭(Ta)、氮化鉭(TaN)、氮化鎢(WN)、氮化鈦(TiN)及鈦(Ti)其中之一者或是上述材料所形成之組合,例如此阻障層可以是濺鍍鉭;繼續,利用濺鍍或化學氣相沉積的方式沈積一層例如是銅材質之種子層在阻障層上,再來電鍍一銅金屬在此種子層上,最後利用化學機械研磨(Chemical Mechanical Polish,CMP)的方式去除位在此開口外的銅金屬、種子層及阻障層,直到曝露出第一介電層的上表面為止。以此種方式形成在溝渠內的金屬(其係包括阻障層、種子層及電鍍銅)係為圖案化金屬層8,而形成在導通孔內的金屬則為金屬插塞10,且這些圖案化金屬層8可以透過導通孔內的金屬插塞10連通相鄰兩層之間的圖案化金屬層8或是連接至半導體元件4。For example, in the case of a damascene process, the manner of forming the wiring structure 6 includes depositing a first dielectric layer on the upper surface of a second dielectric layer by means of chemical vapor deposition (CVD). The material of the first dielectric layer and the material of the second dielectric layer comprise a material having a oxynitride compound and a dielectric constant value (k) of between 1.5 and 3; then, forming a first photoresist layer Depositing a first dielectric layer on the first dielectric layer with a first photoresist layer opening in the first photoresist layer to expose the second dielectric layer to form a trench; after forming the trench, removing The first photoresist layer continues; forming a second photoresist layer on the first dielectric layer and the second dielectric layer exposed by the trench, and the second photoresist layer in the second photoresist layer The layer opening exposes the second dielectric layer; then, the second dielectric layer exposed by the opening of the second photoresist layer is removed to form a via hole, and after the via hole is formed, the second photoresist layer is removed. Therefore, an opening composed of the trench and the via hole is formed in the first dielectric layer and the second dielectric layer. Then, use splash Plating or chemical vapor deposition depositing a barrier layer on the lower surface and sidewalls of the opening and on the upper surface of the first dielectric layer, wherein the barrier layer is made of a material selected from the group consisting of tantalum (Ta) and nitrogen. One of tantalum (TaN), tungsten nitride (WN), titanium nitride (TiN), and titanium (Ti) or a combination of the above materials, for example, the barrier layer may be sputtered; Depositing a layer of a seed layer of, for example, copper on the barrier layer by sputtering or chemical vapor deposition, and then plating a copper metal on the seed layer, and finally using chemical mechanical polishing (CMP). The copper metal, the seed layer and the barrier layer outside the opening are removed until the upper surface of the first dielectric layer is exposed. The metal formed in the trench in this manner (including the barrier layer, the seed layer, and the electroplated copper) is the patterned metal layer 8, and the metal formed in the via hole is the metal plug 10, and these patterns The metal layer 8 can pass through the metal plug 10 in the via hole to communicate with the patterned metal layer 8 between the adjacent two layers or to the semiconductor element 4.

又,形成圖案化金屬層8方式比如是先利用濺鍍製程濺鍍一鋁合金層(其係包括90 wt%以上的鋁及10 wt%以下的銅)在一介電層上,接著再透過微影蝕刻製程圖案化此鋁合金層。也就是說,線路結構6包括濺鍍鋁。Moreover, the method of forming the patterned metal layer 8 is to first sputter an aluminum alloy layer (which includes 90 wt% or more of aluminum and 10 wt% or less of copper) on a dielectric layer by a sputtering process, and then pass through. The lithography process patterns the aluminum alloy layer. That is, the wiring structure 6 includes sputtered aluminum.

複數介電層12位在半導體基底2的上方,且圖案化金屬層8是位在這些介電層12之間,並透過位在這些介電層12內的金屬插塞10連接相鄰兩層之圖案化金屬層8。介電層12一般是利用化學氣相沉積(CVD)的方式所形成,而介電層12比如是氧矽化合物(例如SiO2 )、四乙氧基矽烷(TEOS)之氧化物、含矽、碳、氧與氫之化合物(例如 Siw Cx Oy Hz )、氮矽化合物(例如Si3 N4 )、氮氧矽化合物、氟矽玻璃(Fluorinated Silicate Glass,FSG)、絲印層(SiLK)、黑鑽石薄膜(Black Diamond)、硼磷矽玻璃(Borophosphosilicate Glass,BPSG)、聚芳基酯(polyarylene ether)、多孔性氧化矽(porous silicon oxide)、聚苯噁唑(polybenzoxazole,PBO)、介電常數值(k)介於1.5至3之間的材質或者是以旋塗方式形成之玻璃(Spin-On Glass,SOG;中文亦可譯為旋塗式玻璃)。另,介電層12的厚度t2比如是小於3微米,較佳厚度則是介於0.3微米至2.5微米之間。The plurality of dielectric layers 12 are positioned above the semiconductor substrate 2, and the patterned metal layer 8 is positioned between the dielectric layers 12, and is connected to the adjacent two layers through the metal plugs 10 located in the dielectric layers 12. The patterned metal layer 8 is formed. The dielectric layer 12 is generally formed by chemical vapor deposition (CVD), and the dielectric layer 12 is, for example, an oxonium compound (for example, SiO 2 ), an oxide of tetraethoxy decane (TEOS), or Carbon, oxygen and hydrogen compounds (eg Si w C x O y H z ), nitrogen ruthenium compounds (eg Si 3 N 4 ), oxynitride compounds, Fluorinated Silicate Glass (FSG), silk screen (SiLK) ), Black Diamond, Borophosphosilicate Glass (BPSG), polyarylene ether, porous silicon oxide, polybenzoxazole (PBO), A material having a dielectric constant value (k) between 1.5 and 3 or a glass formed by spin coating (Spin-On Glass, SOG; Chinese can also be translated as spin-on glass). Further, the thickness t2 of the dielectric layer 12 is, for example, less than 3 μm, and preferably the thickness is between 0.3 μm and 2.5 μm.

一保護層14位在線路結構6與介電層12的上方,此保護層14可以保護半導體元件4與線路結構6免於受到濕氣與外來離子污染物(foreign ion contamination)的破壞,也就是說保護層14可以防止移動離子(比如是鈉離子)、水氣(moisture)、過渡金屬(比如是金、銀、銅)及其它雜質(impurity)穿透,而損壞保護層14下方的半導體元件4(例如電晶體、多晶矽電阻元件或多晶矽-多晶矽電容元件)或線路結構6。另,「下方」一詞在本發明中是表示位在某物下面並與之接觸,或是表示位在某物下面但未與之接觸;「下」一字在本發明中則是表示位在某物下面並與之接觸。A protective layer 14 is positioned over the wiring structure 6 and the dielectric layer 12. The protective layer 14 protects the semiconductor component 4 and the wiring structure 6 from moisture and foreign ion contamination, that is, It is said that the protective layer 14 can prevent mobile ions (such as sodium ions), moisture, transition metals (such as gold, silver, copper) and other impurities from penetrating, and damage the semiconductor components under the protective layer 14. 4 (for example a transistor, a polysilicon resistor or a polysilicon-polysilicon capacitor) or a line structure 6. In addition, the term "below" is used in the present invention to mean that it is underneath and in contact with something, or that it is below something but not in contact with it; the word "below" is used in the present invention to indicate a bit. Under and in contact with something.

保護層14通常是由氧矽化合物(例如SiO2 )、磷矽玻璃(Phosphosilicate Glass,PSG)、氮矽化合物(例如Si3 N4 )或氮氧矽化合物等所組成,而保護層14的厚度t3一般係大於0.3微米(μm),例如保護層14的厚度t3是介於0.3微 米至1.5微米之間。又,保護層14在包括氮矽化合物層的情況下,此氮矽化合物層的厚度通常大於0.3微米。接著,將敘述保護層14的製作方式,其係約有十種不同方法,分別說明如下。The protective layer 14 is usually composed of an oxonium compound (for example, SiO 2 ), Phosphosilicate Glass (PSG), a nitrogen cerium compound (for example, Si 3 N 4 ) or an oxynitride compound, and the thickness of the protective layer 14 T3 is typically greater than 0.3 microns (μm), for example, the thickness t3 of the protective layer 14 is between 0.3 microns and 1.5 microns. Further, in the case where the protective layer 14 includes a layer of a ruthenium nitride compound, the thickness of the ruthenium nitride compound layer is usually more than 0.3 μm. Next, the manner of manufacturing the protective layer 14 will be described, which is about ten different methods, which are respectively described below.

第一種製作保護層14的方法是先利用化學氣相沉積(CVD)形成厚度介於0.2微米至1.2微米之間的一氧化矽層,接著再利用化學氣相沉積(CVD)形成厚度介於0.2微米至1.2微米之間的一氮化矽層在氧化矽層上。其中,「上」一字在本發明中是表示位在某物上面並與之接觸。The first method of forming the protective layer 14 is to first form a layer of germanium oxide having a thickness of between 0.2 μm and 1.2 μm by chemical vapor deposition (CVD), followed by chemical vapor deposition (CVD) to form a thickness between A layer of tantalum nitride between 0.2 micrometers and 1.2 micrometers is on the tantalum oxide layer. Among them, the word "upper" in the present invention means that it is placed on and in contact with something.

第二種製作保護層14的方法是先利用化學氣相沉積(CVD)形成厚度介於0.2微米至1.2微米之間的一氧化矽層,繼續利用電漿加強型化學氣相沉積(Plasma Enhanced Chemical Vapor Deposition,PECVD)形成厚度介於0.05微米至0.15微米之間的一氮氧化矽層在氧化矽層上,接著再利用化學氣相沉積(CVD)形成厚度介於0.2微米至1.2微米之間的一氮化矽層在氮氧化矽層上。The second method of forming the protective layer 14 is to first form a niobium oxide layer having a thickness of between 0.2 μm and 1.2 μm by chemical vapor deposition (CVD), and continue to utilize plasma enhanced chemical vapor deposition (Plasma Enhanced Chemical). Vapor Deposition (PECVD) forms a layer of bismuth oxynitride between 0.05 μm and 0.15 μm on the yttrium oxide layer, followed by chemical vapor deposition (CVD) to form a thickness between 0.2 μm and 1.2 μm. A tantalum nitride layer is on the niobium oxynitride layer.

第三種製作保護層14的方法是先利用化學氣相沉積(CVD)形成厚度介於0.05微米至0.15微米之間的一氮氧化矽層,繼續利用化學氣相沉積(CVD)形成厚度介於0.2微米至1.2微米之間的一氧化矽層在氮氧化矽層上,接著再利用化學氣相沉積(CVD)形成厚度介於0.2微米至1.2微米之間的一氮化矽層在氧化矽層上。A third method of forming the protective layer 14 is to first form a layer of bismuth oxynitride having a thickness of between 0.05 μm and 0.15 μm by chemical vapor deposition (CVD), and continue to form a thickness by chemical vapor deposition (CVD). A layer of germanium oxide between 0.2 μm and 1.2 μm is deposited on the hafnium oxynitride layer, followed by chemical vapor deposition (CVD) to form a tantalum nitride layer having a thickness between 0.2 μm and 1.2 μm in the hafnium oxide layer. on.

第四種製作保護層14的方法是先利用化學氣相沉積(CVD)形成厚度介於0.2微米至0.5微米之間的一第一氧化 矽層,繼續利用旋塗法(spin-coating)形成厚度介於0.5微米至1微米之間的一第二氧化矽層在第一氧化矽層上,接著利用化學氣相沉積(CVD)形成厚度介於0.2微米至0.5微米之間的一第三氧化矽層在第二氧化矽層上,最後再利用化學氣相沉積(CVD)形成厚度介於0.2微米至1.2微米之間的一氮化矽層在第三氧化矽層上。The fourth method of fabricating the protective layer 14 is to first form a first oxidation thickness between 0.2 micrometers and 0.5 micrometers by chemical vapor deposition (CVD). The ruthenium layer continues to form a second ruthenium oxide layer having a thickness of between 0.5 μm and 1 μm on the first ruthenium oxide layer by spin-coating, followed by thickness formation by chemical vapor deposition (CVD). A third layer of ruthenium oxide between 0.2 micrometers and 0.5 micrometers is on the second ruthenium oxide layer, and finally a chemical vapor deposition (CVD) is used to form tantalum nitride having a thickness of between 0.2 micrometers and 1.2 micrometers. The layer is on the third layer of ruthenium oxide.

第五種製作保護層14的方法是先利用高密度電漿化學氣相沉積(High Density Plasma Chemical Vapor Deposition,HDP-CVD)形成厚度介於0.5微米至2微米之間的一氧化矽層,接著再利用化學氣相沉積(CVD)形成厚度介於0.2微米至1.2微米之間的一氮化矽層在氧化矽層上。The fifth method for forming the protective layer 14 is to form a layer of germanium oxide having a thickness of between 0.5 μm and 2 μm by using High Density Plasma Chemical Vapor Deposition (HDP-CVD). A layer of tantalum nitride having a thickness of between 0.2 micrometers and 1.2 micrometers is formed on the tantalum oxide layer by chemical vapor deposition (CVD).

第六種製作保護層14的方法是先形成厚度介於0.2微米至3微米之間的一未摻雜矽玻璃層(undoped silicate glass,USG),繼續形成比如是四乙氧基矽烷、硼磷矽玻璃(BPSG)或磷矽玻璃(PSG)等之厚度介於0.5微米至3微米之間的一絕緣層在未摻雜矽玻璃層上,接著再利用化學氣相沉積(CVD)形成厚度介於0.2微米至1.2微米之間的一氮化矽層在絕緣層上。The sixth method for forming the protective layer 14 is to first form an undoped silicate glass (USG) having a thickness between 0.2 μm and 3 μm, and continue to form, for example, tetraethoxy decane, borophosphorus. An insulating layer having a thickness of between 0.5 micrometers and 3 micrometers, such as bismuth glass (BPSG) or phosphor bismuth glass (PSG), is deposited on the undoped bismuth glass layer, followed by chemical vapor deposition (CVD) to form a thickness layer. A layer of tantalum nitride between 0.2 microns and 1.2 microns is on the insulating layer.

第七種製作保護層14的方法是選擇性地先利用化學氣相沉積(CVD)形成厚度介於0.05微米至0.15微米之間的一第一氮氧化矽層,繼續利用化學氣相沉積(CVD)形成厚度介於0.2微米至1.2微米之間的一氧化矽層在第一氮氧化矽層上,接著可以選擇性地利用化學氣相沉積(CVD)形 成厚度介於0.05微米至0.15微米之間的一第二氮氧化矽層在氧化矽層上,再來利用化學氣相沉積(CVD)形成厚度介於0.2微米至1.2微米之間的一氮化矽層在第二氮氧化矽層上或在氧化矽層上,接著可以選擇性地利用化學氣相沉積(CVD)形成厚度介於0.05微米至0.15微米之間的一第三氮氧化矽層在氮化矽層上,最後再利用化學氣相沉積(CVD)形成厚度介於0.2微米至1.2微米之間的一氧化矽層在第三氮氧化矽層上或在氮化矽層上。A seventh method of fabricating the protective layer 14 is to selectively form a first layer of bismuth oxynitride having a thickness between 0.05 micrometers and 0.15 micrometers by chemical vapor deposition (CVD), and continue to utilize chemical vapor deposition (CVD). Forming a layer of germanium oxide having a thickness between 0.2 microns and 1.2 microns on the first layer of hafnium oxynitride, followed by selective use of chemical vapor deposition (CVD) A second layer of bismuth oxynitride having a thickness of between 0.05 micrometers and 0.15 micrometers is formed on the yttrium oxide layer, and then chemical vapor deposition (CVD) is used to form a nitriding layer having a thickness of between 0.2 micrometers and 1.2 micrometers. The ruthenium layer is on the second ruthenium oxynitride layer or on the ruthenium oxide layer, and then a third ruthenium oxynitride layer having a thickness of between 0.05 μm and 0.15 μm can be selectively formed by chemical vapor deposition (CVD). On the tantalum nitride layer, chemical vapor deposition (CVD) is finally used to form a tantalum oxide layer having a thickness between 0.2 μm and 1.2 μm on the third hafnium oxide layer or on the tantalum nitride layer.

第八種製作保護層14的方法是先利用化學氣相沉積(CVD)形成厚度介於0.2微米至1.2微米之間的一第一氧化矽層,繼續利用旋塗法形成厚度介於0.5微米至1微米之間的一第二氧化矽層在第一氧化矽層上,接著利用化學氣相沉積(CVD)形成厚度介於0.2微米至1.2微米之間的一第三氧化矽層在第二氧化矽層上,再來利用化學氣相沉積(CVD)形成厚度介於0.2微米至1.2微米之間的一氮化矽層在第三氧化矽層上,最後再利用化學氣相沉積(CVD)形成厚度介於0.2微米至1.2微米之間的一第四氧化矽層在氮化矽層上。The eighth method for forming the protective layer 14 is to first form a first ruthenium oxide layer having a thickness of between 0.2 μm and 1.2 μm by chemical vapor deposition (CVD), and continue to form a thickness of 0.5 μm by spin coating. A second ruthenium oxide layer between 1 micron is on the first ruthenium oxide layer, followed by chemical vapor deposition (CVD) to form a third ruthenium oxide layer having a thickness between 0.2 micrometers and 1.2 micrometers in the second oxidation On the ruthenium layer, a layer of tantalum nitride having a thickness of between 0.2 μm and 1.2 μm is formed on the third yttria layer by chemical vapor deposition (CVD), and finally formed by chemical vapor deposition (CVD). A fourth layer of ruthenium oxide having a thickness between 0.2 microns and 1.2 microns is on the tantalum nitride layer.

第九種製作保護層14的方法是先利用高密度電漿化學氣相沉積(HDP-CVD)形成厚度介於0.5微米至2微米之間的一第一氧化矽層,繼續利用化學氣相沉積(CVD)形成厚度介於0.2微米至1.2微米之間的一氮化矽層在第一氧化矽層上,接著再利用高密度電漿化學氣相沉積(HDP-CVD)形成厚度介於0.5微米至2微米之間的一第二 氧化矽層在氮化矽層上。The ninth method for fabricating the protective layer 14 is to first form a first ruthenium oxide layer having a thickness of between 0.5 μm and 2 μm by high-density plasma chemical vapor deposition (HDP-CVD), and continue to utilize chemical vapor deposition. (CVD) forming a tantalum nitride layer having a thickness between 0.2 μm and 1.2 μm on the first tantalum oxide layer, followed by high-density plasma chemical vapor deposition (HDP-CVD) to a thickness of 0.5 μm a second between 2 microns The ruthenium oxide layer is on the tantalum nitride layer.

第十種製作保護層14的方法是先利用化學氣相沉積(CVD)形成厚度介於0.2微米至1.2微米之間的一第一氮化矽層,繼續利用化學氣相沉積(CVD)形成厚度介於0.2微米至1.2微米之間的一氧化矽層在第一氮化矽層上,接著再利用化學氣相沉積(CVD)形成厚度介於0.2微米至1.2微米之間的一第二氮化矽層在氧化矽層上。The tenth method for fabricating the protective layer 14 is to first form a first tantalum nitride layer having a thickness of between 0.2 μm and 1.2 μm by chemical vapor deposition (CVD), and continue to form a thickness by chemical vapor deposition (CVD). A layer of germanium oxide between 0.2 micrometers and 1.2 micrometers is on the first tantalum nitride layer, followed by chemical vapor deposition (CVD) to form a second nitride having a thickness between 0.2 micrometers and 1.2 micrometers. The ruthenium layer is on the ruthenium oxide layer.

本發明係透過位在保護層14內的一開口14a暴露出線路結構6之一接墊16,此接墊16的厚度t4比如是介於0.4微米至3微米之間或是介於0.2微米至2微米之間。形成接墊16的方式例如是以濺鍍製程形成鋁或鋁合金作為接墊16(其厚度例如是介於0.2微米至2微米之間),或是以電鍍製程形成銅作為接墊16(其厚度例如是介於0.2微米至2微米之間)。因此,接墊16可以是厚度介於0.2微米至2微米之間且材質主要包括鋁的金屬層(亦稱為鋁墊,aluminum pad),或是厚度介於0.2微米至2微米之間且材質主要包括銅的金屬層(亦稱為銅墊,copper pad)。此外,當接墊16包括以電鍍製程所形成之銅金屬時,在電鍍銅的底部下與側壁外具有一阻障層(barrier layer),此阻障層的材質比如是鉭(Ta)或氮化鉭(TaN)。In the present invention, a pad 16 of the line structure 6 is exposed through an opening 14a in the protective layer 14. The thickness t4 of the pad 16 is, for example, between 0.4 micrometers and 3 micrometers or between 0.2 micrometers. Between 2 microns. The method of forming the pad 16 is, for example, forming a silicon or aluminum alloy as a pad 16 (having a thickness of, for example, between 0.2 μm and 2 μm) by a sputtering process, or forming copper as a pad 16 by an electroplating process (its The thickness is, for example, between 0.2 microns and 2 microns). Therefore, the pad 16 may be a metal layer (also referred to as an aluminum pad) having a thickness of between 0.2 micrometers and 2 micrometers and a material mainly comprising aluminum, or a material having a thickness of between 0.2 micrometers and 2 micrometers. It mainly consists of a copper metal layer (also known as a copper pad). In addition, when the pad 16 includes copper metal formed by an electroplating process, a barrier layer is disposed under the bottom of the electroplated copper and outside the sidewall, and the material of the barrier layer is, for example, tantalum (Ta) or nitrogen.钽 (TaN).

另,開口14a的橫向尺寸d係介於0.5微米至20微米之間或是介於20微米至200微米之間,且開口14a的形狀可以是圓形、正方形、長方形或五邊以上之多邊形(例如六邊形或八邊形)。亦即,開口14a的形狀可以是圓形,且直 徑是介於0.5微米至20微米之間或是介於20微米至200微米之間;或是,開口14a的形狀可以是正方形,且一邊長是介於0.5微米至20微米之間或是介於20微米至200微米之間;或是,開口14a的形狀可以是長方形,且一寬度是介於0.5微米至20微米之間或是介於20微米至200微米之間;或是,開口14a的形狀可以是五邊以上之多邊形(例如六邊形或八邊形),且一寬度是介於0.5微米至20微米之間或是介於20微米至200微米之間,例如開口14a的形狀為六邊形(或稱六角形)時,其對邊寬度是介於0.5微米至20微米之間或是介於20微米至200微米之間。In addition, the lateral dimension d of the opening 14a is between 0.5 micrometers and 20 micrometers or between 20 micrometers and 200 micrometers, and the shape of the opening 14a may be a circle, a square, a rectangle or a polygon of five or more sides ( For example, a hexagon or an octagon). That is, the shape of the opening 14a may be circular and straight The diameter is between 0.5 micrometers and 20 micrometers or between 20 micrometers and 200 micrometers; or the shape of the opening 14a may be square and the length of one side is between 0.5 micrometers and 20 micrometers or Between 20 micrometers and 200 micrometers; or, the shape of the opening 14a may be a rectangle, and a width is between 0.5 micrometers and 20 micrometers or between 20 micrometers and 200 micrometers; or, the opening 14a The shape may be a polygon of five or more sides (for example, a hexagon or an octagon), and a width is between 0.5 micrometers and 20 micrometers or between 20 micrometers and 200 micrometers, for example, the shape of the opening 14a. In the case of a hexagon (or hexagon), the width of the opposite side is between 0.5 micrometers and 20 micrometers or between 20 micrometers and 200 micrometers.

請參閱第2B圖所示,本發明可選擇形成厚度介於0.4微米至3微米之間的一金屬保護蓋(metal cap)18在保護層14之一開口14a所暴露出的一接墊16上,使接墊16免於受到氧化而侵蝕損壞。例如,金屬保護蓋18包括厚度介於0.01微米至0.7微米之間的一阻障層(barrier layer)位在開口14a所暴露出之接墊16上,以及包括厚度介於0.4微米至2微米之間的一含鋁金屬層位在此阻障層上,其中此阻障層比如是一鈦層、一鈦鎢合金層、一氮化鈦層、一鉭層、一氮化鉭層、一鉻(Cr)層或一耐火金屬合金層等,而含鋁金屬層則比如是一鋁層、一鋁-銅合金(Al-Cu alloy)層或是一鋁-矽-銅合金(Al-Si-Cu alloy)層;或者,金屬保護蓋18為厚度介於0.4微米至2微米之間的一含鋁金屬層位在開口14a所暴露出之接墊16(如銅墊)上,其中含鋁金屬層比如是一鋁層、一鋁-銅合金(Al-Cu alloy)層或是一鋁-矽-銅 合金(Al-Si-Cu alloy)層。Referring to FIG. 2B, the present invention can optionally form a metal cap 18 having a thickness between 0.4 micrometers and 3 micrometers on a pad 16 exposed by one of the openings 14a of the protective layer 14. The pad 16 is protected from oxidation and damage. For example, the metal protective cover 18 includes a barrier layer having a thickness between 0.01 micrometers and 0.7 micrometers on the pads 16 exposed by the openings 14a, and a thickness ranging from 0.4 micrometers to 2 micrometers. An aluminum-containing metal layer is disposed on the barrier layer, wherein the barrier layer is a titanium layer, a titanium-tungsten alloy layer, a titanium nitride layer, a tantalum layer, a tantalum nitride layer, and a chromium layer. (Cr) layer or a refractory metal alloy layer, etc., and the aluminum-containing metal layer is, for example, an aluminum layer, an aluminum-copper alloy (Al-Cu alloy) layer or an aluminum-bismuth-copper alloy (Al-Si- a layer of Cu alloy); or, the metal protective cover 18 is an aluminum-containing metal layer having a thickness of between 0.4 μm and 2 μm on the pad 16 (such as a copper pad) exposed by the opening 14a, and the aluminum alloy is contained therein. The layer is, for example, an aluminum layer, an aluminum-copper alloy layer or an aluminum-bismuth-copper layer. Alloy (Al-Si-Cu alloy) layer.

例如,當接墊16的材質主要包括銅金屬時,接墊16上通常具有金屬保護蓋18,讓主要含有銅金屬的接墊16(或稱為銅墊)免於受到氧化而侵蝕損壞,其中此金屬保護蓋18包括一含鉭金屬層(例如一鉭層或一氮化鉭層)位在此接墊16上,以及包括一含鋁金屬層(例如一鋁層或一鋁合金層)位在此含鉭金屬層上。For example, when the material of the pad 16 mainly includes copper metal, the pad 16 usually has a metal protective cover 18, so that the pad 16 (or copper pad) mainly containing copper metal is protected from oxidation and erosion. The metal protective cover 18 includes a tantalum-containing metal layer (for example, a tantalum layer or a tantalum nitride layer) on the pad 16, and includes an aluminum-containing metal layer (for example, an aluminum layer or an aluminum alloy layer). On this layer containing a base metal.

本發明係以結構20代表第2A圖與第2B圖中,保護層14與半導體基底2之間的結構,亦即以結構20包括第2A圖與第2B圖中的半導體元件4、線路結構6(包括圖案化金屬層8及金屬插塞10)與介電層12等。In the present invention, the structure 20 represents the structure between the protective layer 14 and the semiconductor substrate 2 in FIGS. 2A and 2B, that is, the structure 20 includes the semiconductor element 4 and the line structure 6 in FIGS. 2A and 2B. (including patterned metal layer 8 and metal plug 10) and dielectric layer 12 and the like.

請參閱第3圖所示,本發明可形成厚度介於1微米至20微米之間的一打線接墊(bonding pad)22在一開口14a所暴露出之一接墊16(例如鋁墊或銅墊)上,其中打線接墊22的較佳厚度是介於3微米至5微米之間,且此打線接墊22係作為接合一打線導線(例如金線)的打線接點。有關形成打線接墊22在開口14a所暴露出之接墊16上的方法,請參閱第4圖系列的說明。另,在形成打線接墊22之後,透過切割半導體晶圓(semiconductor wafer),以形成複數半導體晶片23(或稱為積體電路晶片,IC chip)。Referring to FIG. 3, the present invention can form a bonding pad 22 having a thickness between 1 micrometer and 20 micrometers, and a pad 16 (for example, an aluminum pad or copper) exposed in an opening 14a. The pad has a preferred thickness of between 3 micrometers and 5 micrometers, and the wire bonding pad 22 serves as a wire bonding junction for bonding a wire conductor such as a gold wire. For a method of forming the wire bonding pads 22 on the pads 16 exposed by the openings 14a, refer to the description of the series of Fig. 4. Further, after the wire bonding pads 22 are formed, a semiconductor wafer 23 is cut by dicing to form a plurality of semiconductor wafers 23 (or IC chips).

請參閱第4A圖所示,形成厚度介於0.01微米至0.7微米之間(較佳則是介於0.03微米至0.7微米之間)的一黏著/阻障層(adhesion/barrier layer)24在保護層14上與開口14a所暴露出之接墊16上,其中此接墊16可以是鋁墊或 是銅墊。另,黏著/阻障層24的材質包括鈦、鈦鎢合金、氮化鈦、鉻、鉭、氮化鉭或耐火金屬合金(alloy of refractory metal)等。Referring to FIG. 4A, an adhesion/barrier layer 24 having a thickness between 0.01 micrometers and 0.7 micrometers (preferably between 0.03 micrometers and 0.7 micrometers) is formed on the protective layer. 14 on the pad 16 exposed by the opening 14a, wherein the pad 16 may be an aluminum pad or It is a copper pad. In addition, the material of the adhesion/barrier layer 24 includes titanium, titanium tungsten alloy, titanium nitride, chromium, tantalum, tantalum nitride or alloy of refractory metal.

例如,黏著/阻障層24可以是厚度介於0.01微米至0.7微米之間(較佳則是介於0.03微米至0.7微米之間)的一鈦層濺鍍在保護層14上與開口14a所暴露出之主要材質包括鋁的接墊16(即鋁墊)上;或者,黏著/阻障層24可以是厚度介於0.01微米至0.7微米之間(較佳則是介於0.03微米至0.7微米之間)的一鈦鎢合金層濺鍍在保護層14上與開口14a所暴露出之主要材質包括鋁的接墊16上;或者,黏著/阻障層24可以是厚度介於0.01微米至0.7微米之間(較佳則是介於0.03微米至0.7微米之間)的一氮化鈦層濺鍍在保護層14上與開口14a所暴露出之主要材質包括鋁的接墊16上;或者,黏著/阻障層24可以是厚度介於0.01微米至0.7微米之間(較佳則是介於0.03微米至0.7微米之間)的一鉻層濺鍍在保護層14上與開口14a所暴露出之主要材質包括鋁的接墊16上;或者,黏著/阻障層24可以是厚度介於0.01微米至0.7微米之間(較佳則是介於0.03微米至0.7微米之間)的一氮化鉭層濺鍍在保護層14上與開口14a所暴露出之主要材質包括鋁的接墊16上;或者,黏著/阻障層24可以是厚度介於0.01微米至0.7微米之間(較佳則是介於0.03微米至0.7微米之間)的一鉭層濺鍍在保護層14上與開口14a所暴露出之主要材質包括鋁的接墊16上;或者,黏著/阻障層24可以是厚度介於0.01微米至0.7微米 之間(較佳則是介於0.03微米至0.7微米之間)的一耐火金屬合金層濺鍍在保護層14上與開口14a所暴露出之主要材質包括鋁的接墊16上。For example, the adhesion/barrier layer 24 can be a titanium layer having a thickness between 0.01 microns and 0.7 microns (preferably between 0.03 microns and 0.7 microns) sputtered onto the protective layer 14 and exposed to the opening 14a. The primary material comprises aluminum pads 16 (ie, aluminum pads); alternatively, the adhesion/barrier layer 24 can be between 0.01 microns and 0.7 microns thick (preferably between 0.03 microns and 0.7 microns). a titanium-tungsten alloy layer is sputtered on the protective layer 14 and the main material exposed by the opening 14a includes the pad 16 of aluminum; or the adhesion/barrier layer 24 may have a thickness of 0.01 micron to 0.7 micron. A layer of titanium nitride (preferably between 0.03 micrometers and 0.7 micrometers) is sputtered on the protective layer 14 and the main material exposed by the opening 14a comprises a pad 16 of aluminum; or, adhesion/resistance The barrier layer 24 may be a chrome layer having a thickness between 0.01 micrometers and 0.7 micrometers (preferably between 0.03 micrometers and 0.7 micrometers). The main material exposed on the protective layer 14 and the opening 14a includes: The pad 16 of aluminum; or the adhesion/barrier layer 24 may have a thickness between 0.01 microns and 0.7 microns ( Preferably, the tantalum nitride layer is sputtered on the protective layer 14 and the pad 16 of the main material including the aluminum exposed by the opening 14a; or the adhesion/barrier layer 24 It may be a layer of a thickness of between 0.01 micrometers and 0.7 micrometers (preferably between 0.03 micrometers and 0.7 micrometers) which is sputtered on the protective layer 14 and the main material exposed by the opening 14a comprises aluminum. Pad 16; alternatively, the adhesion/barrier layer 24 can be between 0.01 microns and 0.7 microns thick A refractory metal alloy layer between (preferably between 0.03 micrometers and 0.7 micrometers) is sputtered onto the protective layer 14 and the main material exposed to the opening 14a comprises a pad 16 of aluminum.

例如,黏著/阻障層24可以是厚度介於0.01微米至0.7微米之間(較佳則是介於0.03微米至0.7微米之間)的一鈦層濺鍍在保護層14上與開口14a所暴露出之主要材質包括銅的接墊16(即銅墊)上;或者,黏著/阻障層24可以是厚度介於0.01微米至0.7微米之間(較佳則是介於0.03微米至0.7微米之間)的一鈦鎢合金層濺鍍在保護層14上與開口14a所暴露出之主要材質包括銅的接墊16上;或者,黏著/阻障層24可以是厚度介於0.01微米至0.7微米之間(較佳則是介於0.03微米至0.7微米之間)的一氮化鈦層濺鍍在保護層14上與開口14a所暴露出之主要材質包括銅的接墊16上;或者,黏著/阻障層24可以是厚度介於0.01微米至0.7微米之間(較佳則是介於0.03微米至0.7微米之間)的一鉻層濺鍍在保護層14上與開口14a所暴露出之主要材質包括銅的接墊16上;或者,黏著/阻障層24可以是厚度介於0.01微米至0.7微米之間(較佳則是介於0.03微米至0.7微米之間)的一氮化鉭層濺鍍在保護層14上與開口14a所暴露出之主要材質包括銅的接墊16上;或者,黏著/阻障層24可以是厚度介於0.01微米至0.7微米之間(較佳則是介於0.03微米至0.7微米之間)的一鉭層濺鍍在保護層14上與開口14a所暴露出之主要材質包括銅的接墊16上;或者,黏著/阻障層24可以是厚度介於0.01微米至0.7微米 之間(較佳則是介於0.03微米至0.7微米之間)的一耐火金屬合金層濺鍍在保護層14上與開口14a所暴露出之主要材質包括銅的接墊16上。For example, the adhesion/barrier layer 24 can be a titanium layer having a thickness between 0.01 microns and 0.7 microns (preferably between 0.03 microns and 0.7 microns) sputtered onto the protective layer 14 and exposed to the opening 14a. The main material is copper pad 16 (ie, copper pad); or the adhesion/barrier layer 24 may be between 0.01 micrometers and 0.7 micrometers thick (preferably between 0.03 micrometers and 0.7 micrometers). a titanium-tungsten alloy layer is sputtered on the protective layer 14 and the main material exposed by the opening 14a comprises copper pads 16; or the adhesion/barrier layer 24 may be between 0.01 micrometers and 0.7 micrometers thick. A titanium nitride layer (preferably between 0.03 micrometers and 0.7 micrometers) is sputtered on the protective layer 14 and the main material exposed by the opening 14a comprises copper pads 16; or, adhesion/resistance The barrier layer 24 may be a chrome layer having a thickness between 0.01 micrometers and 0.7 micrometers (preferably between 0.03 micrometers and 0.7 micrometers). The main material exposed on the protective layer 14 and the opening 14a includes: The pad 16 of copper; or the adhesion/barrier layer 24 may be between 0.01 microns and 0.7 microns thick ( a layer of tantalum nitride which is preferably between 0.03 micrometers and 0.7 micrometers is sputtered on the protective layer 14 and the pad 16 of the main material including the copper exposed by the opening 14a; or the adhesion/barrier layer 24 A layer of sputtering which may be between 0.01 micrometers and 0.7 micrometers thick (preferably between 0.03 micrometers and 0.7 micrometers) is sputtered on the protective layer 14 and the main material exposed by the opening 14a comprises copper. Pad 16; alternatively, the adhesion/barrier layer 24 can be between 0.01 microns and 0.7 microns thick A refractory metal alloy layer between (preferably between 0.03 micrometers and 0.7 micrometers) is sputtered onto the protective layer 14 and the pads 16 of the main material exposed by the openings 14a, including copper.

請參閱第4B圖所示,濺鍍厚度介於0.03微米至1微米之間(較佳則是介於0.03微米至0.7微米之間)的一種子層26在黏著/阻障層24上。另,種子層26亦可利用蒸鍍、物理氣相沉積或無電電鍍(electroless plating)等方式形成。由於種子層26可以有利於後續金屬層的形成,因此種子層26的材質會隨後續金屬層的材質而有所變化,如當材質為金(Au)的金屬層電鍍形成在種子層26上時,種子層26的材質係以金為佳;或者,當材質為銅(Cu)的金屬層電鍍形成在種子層26上時,種子層26的材質係以銅為佳;或者,當材質為鈀(palladium,Pd)的金屬層電鍍形成在種子層26上時,種子層26的材質係以鈀為佳。Referring to FIG. 4B, a sub-layer 26 having a sputter thickness between 0.03 microns and 1 micron (preferably between 0.03 microns and 0.7 microns) is on the adhesion/barrier layer 24. Alternatively, the seed layer 26 may be formed by evaporation, physical vapor deposition, or electroless plating. Since the seed layer 26 can facilitate the formation of the subsequent metal layer, the material of the seed layer 26 may vary depending on the material of the subsequent metal layer, such as when a metal layer of gold (Au) is electroplated on the seed layer 26. The material of the seed layer 26 is preferably gold; or, when the metal layer of copper (Cu) is plated on the seed layer 26, the material of the seed layer 26 is preferably copper; or, when the material is palladium When the metal layer of (palladium, Pd) is electroplated on the seed layer 26, the material of the seed layer 26 is preferably palladium.

例如,當黏著/阻障層24是以濺鍍方式所形成之厚度介於0.01微米至0.7微米之間(較佳則是介於0.03微米至0.7微米之間)的一鈦層時,種子層26可以是厚度介於0.03微米至1微米之間(較佳則是介於0.03微米至0.7微米之間)的一金層濺鍍在此鈦層上;或是,當黏著/阻障層24是以濺鍍方式所形成之厚度介於0.01微米至0.7微米之間(較佳則是介於0.03微米至0.7微米之間)的一鈦鎢合金層時,種子層24可以是厚度介於0.03微米至1微米之間(較佳則是介於0.03微米至0.7微米之間)的一金層濺鍍在此鈦鎢合金層上;或是,當黏著/阻障層26是以濺鍍方式所形成之厚 度介於0.01微米至0.7微米之間(較佳則是介於0.03微米至0.7微米之間)的一氮化鈦層時,種子層24可以是厚度介於0.03微米至1微米之間(較佳則是介於0.03微米至0.7微米之間)的一金層濺鍍在此氮化鈦層上;或是,當黏著/阻障層24是以濺鍍方式所形成之厚度介於0.01微米至0.7微米之間(較佳則是介於0.03微米至0.7微米之間)的一鉻層時,種子層26可以是厚度介於0.03微米至1微米之間(較佳則是介於0.03微米至0.7微米之間)的一金層濺鍍在此鉻層上;或是,當黏著/阻障層24是以濺鍍方式所形成之厚度介於0.01微米至0.7微米之間(較佳則是介於0.03微米至0.7微米之間)的一氮化鉭層時,種子層26可以是厚度介於0.03微米至1微米之間(較佳則是介於0.03微米至0.7微米之間)的一金層濺鍍在此氮化鉭層上;或是,當黏著/阻障層24是以濺鍍方式所形成之厚度介於0.01微米至0.7微米之間(較佳則是介於0.03微米至0.7微米之間)的一鉭層時,種子層26可以是厚度介於0.03微米至1微米之間(較佳則是介於0.03微米至0.7微米之間)的一金層濺鍍在此鉭層上;或是,當黏著/阻障層24是以濺鍍方式所形成之厚度介於0.01微米至0.7微米之間(較佳則是介於0.03微米至0.7微米之間)的一耐火金屬合金層時,種子層26可以是厚度介於0.03微米至1微米之間(較佳則是介於0.03微米至0.7微米之間)的一金層濺鍍在此耐火金屬合金層上。For example, when the adhesion/barrier layer 24 is formed by sputtering in a titanium layer having a thickness between 0.01 micrometers and 0.7 micrometers (preferably between 0.03 micrometers and 0.7 micrometers), the seed layer 26 A gold layer having a thickness of between 0.03 micrometers and 1 micrometer (preferably between 0.03 micrometers and 0.7 micrometers) may be sputtered onto the titanium layer; or, when the adhesion/barrier layer 24 is When the sputtering method forms a titanium-tungsten alloy layer having a thickness of between 0.01 micrometers and 0.7 micrometers (preferably between 0.03 micrometers and 0.7 micrometers), the seed layer 24 may have a thickness of 0.03 micrometers to 1 A gold layer between the micrometers (preferably between 0.03 micrometers and 0.7 micrometers) is sputtered onto the titanium-tungsten alloy layer; or, when the adhesion/barrier layer 26 is formed by sputtering When the titanium nitride layer is between 0.01 micrometers and 0.7 micrometers (preferably between 0.03 micrometers and 0.7 micrometers), the seed layer 24 may have a thickness of between 0.03 micrometers and 1 micrometer (preferably a gold layer between 0.03 micrometers and 0.7 micrometers is sputtered onto the titanium nitride layer; or, when the adhesion/barrier layer 24 is sputtered, the thickness is between 0.01 micrometers and 0.7. The seed layer 26 may have a thickness between 0.03 microns and 1 micron (preferably between 0.03 microns and 0.7 microns) between one micron (preferably between 0.03 microns and 0.7 microns). a gold layer is sputtered onto the chrome layer; or, when the adhesion/barrier layer 24 is sputtered, the thickness is between 0.01 micrometers and 0.7 micrometers (preferably between 0.03 micrometers) When a layer of tantalum nitride is between 0.7 microns, the seed layer 26 may be a gold layer sputtered between 0.03 microns and 1 micron (preferably between 0.03 microns and 0.7 microns). On the tantalum nitride layer; or, when the adhesion/barrier layer 24 is formed by sputtering, the thickness is between 0.01 micrometers and 0.7 micrometers (preferably When a layer of between 0.03 microns and 0.7 microns is used, the seed layer 26 can be a gold layer sputtering having a thickness between 0.03 microns and 1 micron (preferably between 0.03 microns and 0.7 microns). On the ruthenium layer; or, when the adhesion/barrier layer 24 is formed by sputtering, the thickness is between 0.01 micrometers and 0.7 micrometers (preferably between 0.03 micrometers and 0.7 micrometers). In the case of the refractory metal alloy layer, the seed layer 26 may be a gold layer having a thickness of between 0.03 micrometers and 1 micrometer (preferably between 0.03 micrometers and 0.7 micrometers) sputtered onto the refractory metal alloy layer.

例如,當黏著/阻障層24是以濺鍍方式所形成之厚度介於0.01微米至0.7微米之間(較佳則是介於0.03微米至 0.7微米之間)的一鈦層時,種子層26可以是厚度介於0.03微米至1微米之間(較佳則是介於0.03微米至0.7微米之間)的一銅層濺鍍在此鈦層上;或是,當黏著/阻障層24是以濺鍍方式所形成之厚度介於0.01微米至0.7微米之間(較佳則是介於0.03微米至0.7微米之間)的一鈦鎢合金層時,種子層24可以是厚度介於0.03微米至1微米之間(較佳則是介於0.03微米至0.7微米之間)的一銅層濺鍍在此鈦鎢合金層上;或是,當黏著/阻障層26是以濺鍍方式所形成之厚度介於0.01微米至0.7微米之間(較佳則是介於0.03微米至0.7微米之間)的一氮化鈦層時,種子層24可以是厚度介於0.03微米至1微米之間(較佳則是介於0.03微米至0.7微米之間)的一銅層濺鍍在此氮化鈦層上;或是,當黏著/阻障層24是以濺鍍方式所形成之厚度介於0.01微米至0.7微米之間(較佳則是介於0.03微米至0.7微米之間)的一鉻層時,種子層26可以是厚度介於0.03微米至1微米之間(較佳則是介於0.03微米至0.7微米之間)的一銅層濺鍍在此鉻層上;或是,當黏著/阻障層24是以濺鍍方式所形成之厚度介於0.01微米至0.7微米之間(較佳則是介於0.03微米至0.7微米之間)的一氮化鉭層時,種子層26可以是厚度介於0.03微米至1微米之間(較佳則是介於0.03微米至0.7微米之間)的一銅層濺鍍在此氮化鉭層上;或是,當黏著/阻障層24是以濺鍍方式所形成之厚度介於0.01微米至0.7微米之間(較佳則是介於0.03微米至0.7微米之間)的一鉭層時,種子層26可以是厚度介於0.03微米至1微米之間(較 佳則是介於0.03微米至0.7微米之間)的一銅層濺鍍在此鉭層上;或是,當黏著/阻障層24是以濺鍍方式所形成之厚度介於0.01微米至0.7微米之間(較佳則是介於0.03微米至0.7微米之間)的一耐火金屬合金層時,種子層26可以是厚度介於0.03微米至1微米之間(較佳則是介於0.03微米至0.7微米之間)的一銅層濺鍍在此耐火金屬合金層上。For example, when the adhesion/barrier layer 24 is formed by sputtering, the thickness is between 0.01 micrometers and 0.7 micrometers (preferably between 0.03 micrometers and so far). When a titanium layer is between 0.7 micrometers, the seed layer 26 may be a copper layer having a thickness of between 0.03 micrometers and 1 micrometer (preferably between 0.03 micrometers and 0.7 micrometers). Or; when the adhesion/barrier layer 24 is formed by sputtering, the thickness of the titanium-tungsten alloy layer is between 0.01 micrometers and 0.7 micrometers (preferably between 0.03 micrometers and 0.7 micrometers). The seed layer 24 may be a copper layer having a thickness of between 0.03 micrometers and 1 micrometer (preferably between 0.03 micrometers and 0.7 micrometers) sputtered onto the titanium-tungsten alloy layer; or, when adhered The barrier layer 26 is a titanium nitride layer formed by sputtering in a thickness of between 0.01 micrometers and 0.7 micrometers (preferably between 0.03 micrometers and 0.7 micrometers), and the seed layer 24 may be a copper layer having a thickness of between 0.03 micrometers and 1 micrometer (preferably between 0.03 micrometers and 0.7 micrometers) is sputtered onto the titanium nitride layer; or, when the adhesion/barrier layer 24 is When the sputtering method forms a chromium layer having a thickness of between 0.01 micrometers and 0.7 micrometers (preferably between 0.03 micrometers and 0.7 micrometers), the seed layer 26 a copper layer having a thickness of between 0.03 micrometers and 1 micrometer (preferably between 0.03 micrometers and 0.7 micrometers) is sputtered onto the chromium layer; or, when the adhesion/barrier layer 24 is When the sputtering method forms a tantalum nitride layer having a thickness of between 0.01 micrometers and 0.7 micrometers (preferably between 0.03 micrometers and 0.7 micrometers), the seed layer 26 may have a thickness of 0.03 micrometers to 1 A copper layer between the micrometers (preferably between 0.03 micrometers and 0.7 micrometers) is sputtered onto the tantalum nitride layer; or, when the adhesion/barrier layer 24 is formed by sputtering When a layer of between 0.01 microns and 0.7 microns (preferably between 0.03 microns and 0.7 microns) is used, the seed layer 26 may have a thickness between 0.03 microns and 1 micron (more) a copper layer of between 0.03 micrometers and 0.7 micrometers is sputtered onto the germanium layer; or, when the adhesion/barrier layer 24 is sputtered, the thickness is between 0.01 micrometers and 0.7 micrometers. The seed layer 26 may have a thickness between 0.03 microns and 1 micron (preferably between 0.03 microns and 0.7 microns) between a refractory metal alloy layer (preferably between 0.03 microns and 0.7 microns). A copper layer is sputtered between the refractory metal alloy layers.

例如,當黏著/阻障層24是以濺鍍方式所形成之厚度介於0.01微米至0.7微米之間(較佳則是介於0.03微米至0.7微米之間)的一鈦層時,種子層26可以是厚度介於0.03微米至1微米之間(較佳則是介於0.03微米至0.7微米之間)的一鈀層濺鍍在此鈦層上;或是,當黏著/阻障層24是以濺鍍方式所形成之厚度介於0.01微米至0.7微米之間(較佳則是介於0.03微米至0.7微米之間)的一鈦鎢合金層時,種子層24可以是厚度介於0.03微米至1微米之間(較佳則是介於0.03微米至0.7微米之間)的一鈀層濺鍍在此鈦鎢合金層上;或是,當黏著/阻障層26是以濺鍍方式所形成之厚度介於0.01微米至0.7微米之間(較佳則是介於0.03微米至0.7微米之間)的一氮化鈦層時,種子層24可以是厚度介於0.03微米至1微米之間(較佳則是介於0.03微米至0.7微米之間)的一鈀層濺鍍在此氮化鈦層上;或是,當黏著/阻障層24是以濺鍍方式所形成之厚度介於0.01微米至0.7微米之間(較佳則是介於0.03微米至0.7微米之間)的一鉻層時,種子層26可以是厚度介於0.03微米至1微米之間(較佳則是介於0.03微米至0.7微米之間)的一鈀層濺鍍在此鉻 層上;或是,當黏著/阻障層24是以濺鍍方式所形成之厚度介於0.01微米至0.7微米之間(較佳則是介於0.03微米至0.7微米之間)的一氮化鉭層時,種子層26可以是厚度介於0.03微米至1微米之間(較佳則是介於0.03微米至0.7微米之間)的一鈀層濺鍍在此氮化鉭層上;或是,當黏著/阻障層24是以濺鍍方式所形成之厚度介於0.01微米至0.7微米之間(較佳則是介於0.03微米至0.7微米之間)的一鉭層時,種子層26可以是厚度介於0.03微米至1微米之間(較佳則是介於0.03微米至0.7微米之間)的一鈀層濺鍍在此鉭層上;或是,當黏著/阻障層24是以濺鍍方式所形成之厚度介於0.01微米至0.7微米之間(較佳則是介於0.03微米至0.7微米之間)的一耐火金屬合金層時,種子層26可以是厚度介於0.03微米至1微米之間(較佳則是介於0.03微米至0.7微米之間)的一鈀層濺鍍在此耐火金屬合金層上。For example, when the adhesion/barrier layer 24 is formed by sputtering in a titanium layer having a thickness between 0.01 micrometers and 0.7 micrometers (preferably between 0.03 micrometers and 0.7 micrometers), the seed layer 26 A palladium layer having a thickness of between 0.03 micrometers and 1 micrometer (preferably between 0.03 micrometers and 0.7 micrometers) may be sputtered onto the titanium layer; or, when the adhesion/barrier layer 24 is When the sputtering method forms a titanium-tungsten alloy layer having a thickness of between 0.01 micrometers and 0.7 micrometers (preferably between 0.03 micrometers and 0.7 micrometers), the seed layer 24 may have a thickness of 0.03 micrometers to 1 A palladium layer between the micrometers (preferably between 0.03 micrometers and 0.7 micrometers) is sputtered onto the titanium-tungsten alloy layer; or, when the adhesion/barrier layer 26 is formed by sputtering When a titanium nitride layer is between 0.01 micrometers and 0.7 micrometers (preferably between 0.03 micrometers and 0.7 micrometers), the seed layer 24 may have a thickness between 0.03 micrometers and 1 micrometer (preferably a palladium layer between 0.03 microns and 0.7 microns is sputtered onto the titanium nitride layer; or, when the adhesion/barrier layer 24 is sputtered When a chromium layer having a thickness of between 0.01 micrometers and 0.7 micrometers (preferably between 0.03 micrometers and 0.7 micrometers) is formed, the seed layer 26 may have a thickness of between 0.03 micrometers and 1 micrometer (compared to a palladium layer sputtered between 0.03 microns and 0.7 microns) On the layer; or, when the adhesion/barrier layer 24 is formed by sputtering, the thickness is between 0.01 micrometers and 0.7 micrometers (preferably between 0.03 micrometers and 0.7 micrometers) of tantalum nitride. In the case of a layer, the seed layer 26 may be a palladium layer having a thickness of between 0.03 micrometers and 1 micrometer (preferably between 0.03 micrometers and 0.7 micrometers) sputtered on the tantalum nitride layer; or, when When the adhesion/barrier layer 24 is formed by sputtering, a thickness of between 0.01 micrometers and 0.7 micrometers (preferably between 0.03 micrometers and 0.7 micrometers), the seed layer 26 may be thick. A palladium layer between 0.03 micrometers and 1 micrometer (preferably between 0.03 micrometers and 0.7 micrometers) is sputtered onto the germanium layer; or, when the adhesion/barrier layer 24 is sputtered When a refractory metal alloy layer having a thickness of between 0.01 micrometers and 0.7 micrometers (preferably between 0.03 micrometers and 0.7 micrometers) is formed, the seed layer 26 may have a thickness of between 0.03 micrometers and 1 micrometer. A palladium layer (preferably between 0.03 microns and 0.7 microns) is sputtered onto the refractory metal alloy layer.

請參閱第4C圖所示,旋塗(spin-on coating)厚度介於1微米至25微米之間的一光阻層28在種子層26上,其中光阻層28的較佳厚度係介於3微米至10微米之間,且光阻層28比如是一正型(positive-type)光阻層。接著,請參閱第4D圖所示,透過曝光(exposure)與顯影(development)等製程圖案化光阻層28,以形成一光阻層開口28a在光阻層28內並暴露出位在接墊16上方的種子層26,其中在圖案化光阻層28的過程中比如是利用一倍(1X)之曝光機(stepper)或是一倍(1X)之對準曝光機(contact aligner)進行曝光。此外,在顯影後可先利用電漿(例如含有氧離子之電 漿或是含有氟離子濃度小於200PPM與氧離子之電漿)清洗光阻層開口28a所暴露出之種子層26,藉以去除種子層26上表面之光阻殘留物或其它異物。Referring to FIG. 4C, a photoresist layer 28 having a spin-on coating thickness between 1 micrometer and 25 micrometers is disposed on the seed layer 26, wherein the preferred thickness of the photoresist layer 28 is between The photoresist layer 28 is, for example, between a micron and a 10 micron, and the photoresist layer 28 is, for example, a positive-type photoresist layer. Next, referring to FIG. 4D, the photoresist layer 28 is patterned by exposure and development processes to form a photoresist layer opening 28a in the photoresist layer 28 and exposed to the pads. The seed layer 26 above the 16th, wherein during the process of patterning the photoresist layer 28, for example, a double (1X) stepper or a double (1X) contact aligner is used for exposure. . In addition, after development, the plasma can be used first (for example, electricity containing oxygen ions) The slurry or a plasma containing a fluoride ion having a concentration of less than 200 PPM and oxygen ions cleans the seed layer 26 exposed by the photoresist layer opening 28a, thereby removing photoresist residue or other foreign matter on the upper surface of the seed layer 26.

請參閱第4E圖所示,形成厚度介於1微米至20微米之間的一金屬層30在光阻層開口28a所暴露出之種子層26上,其中此金屬層30的較佳厚度係介於3微米至5微米之間,且金屬層30的材質包括金、銅、鎳或鈀。Referring to FIG. 4E, a metal layer 30 having a thickness between 1 micrometer and 20 micrometers is formed on the seed layer 26 exposed by the photoresist layer opening 28a, wherein the preferred thickness of the metal layer 30 is The material is between 3 microns and 5 microns, and the material of the metal layer 30 comprises gold, copper, nickel or palladium.

例如,金屬層30可以是厚度介於1微米至20微米之間(較佳厚度則是介於3微米至5微米之間或是介於1微米至4微米之間)的一金層電鍍在光阻層開口28a所暴露出之材質為金的種子層26上;或者,金屬層30可以是厚度介於1微米至20微米之間(較佳厚度則是介於3微米至5微米之間或是介於1微米至4微米之間)的一鈀層電鍍在光阻層開口28a所暴露出之材質為鈀的種子層26上;或者,金屬層30可以是厚度介於1微米至10微米之間的一銅層電鍍在光阻層開口28a所暴露出之材質為銅的種子層26上、厚度介於1微米至5微米之間的一鎳層電鍍在此銅層上以及厚度介於1微米至5微米之間的一金層電鍍在此鎳層上,其中銅層、鎳層與金層三者的總厚度係介於1微米至20微米之間,而較佳厚度則是介於3微米至5微米之間;或者,金屬層30可以是厚度介於1微米至13微米之間的一銅層電鍍在光阻層開口28a所暴露出之材質為銅的種子層26上、厚度介於1微米至5微米之間的一鎳層電鍍在此銅層上以及厚度介於0.05微米至2微米之間的一金層無電 電鍍在此鎳層上,其中銅層、鎳層與金層三者的總厚度係介於1微米至20微米之間,而較佳厚度則是介於3微米至5微米之間;或者,金屬層30可以是厚度介於1微米至10微米之間的一銅層電鍍在光阻層開口28a所暴露出之材質為銅的種子層26上、厚度介於1微米至5微米之間的一鎳層電鍍在此銅層上以及厚度介於1微米至5微米之間的一鈀層電鍍在此鎳層上,其中銅層、鎳層與鈀層三者的總厚度係介於1微米至20微米之間,而較佳厚度則是介於3微米至5微米之間;或者,金屬層30可以是厚度介於1微米至13微米之間的一銅層電鍍在光阻層開口28a所暴露出之材質為銅的種子層26上、厚度介於1微米至5微米之間的一鎳層電鍍在此銅層上以及厚度介於0.05微米至2微米之間的一鈀層無電電鍍在此鎳層上,其中銅層、鎳層與鈀層三者的總厚度係介於1微米至20微米之間,而較佳厚度則是介於3微米至5微米之間。For example, the metal layer 30 may be a gold layer plating having a thickness between 1 micrometer and 20 micrometers (preferably a thickness of between 3 micrometers to 5 micrometers or between 1 micrometer and 4 micrometers). The photoresist layer opening 28a is exposed on the gold seed layer 26; alternatively, the metal layer 30 may have a thickness between 1 micrometer and 20 micrometers (preferably, the thickness is between 3 micrometers and 5 micrometers). Or a palladium layer between 1 micrometer and 4 micrometers is plated on the seed layer 26 of palladium exposed by the photoresist layer opening 28a; or the metal layer 30 may have a thickness of 1 micrometer to 10 A copper layer between the micrometers is plated on the copper seed layer 26 exposed by the photoresist layer opening 28a, and a nickel layer having a thickness between 1 micrometer and 5 micrometers is plated on the copper layer and the thickness is A gold layer between 1 micrometer and 5 micrometers is electroplated on the nickel layer, wherein the total thickness of the copper layer, the nickel layer and the gold layer is between 1 micrometer and 20 micrometers, and the preferred thickness is Between 3 micrometers and 5 micrometers; or, the metal layer 30 may be a copper layer having a thickness between 1 micrometer and 13 micrometers plated on the photoresist layer A nickel layer having a thickness of between 1 micrometer and 5 micrometers on the copper seed layer 26 exposed by the port 28a is electroplated on the copper layer and a gold layer having a thickness of between 0.05 micrometers and 2 micrometers. No electricity Electroplating on the nickel layer, wherein the total thickness of the copper layer, the nickel layer and the gold layer is between 1 micrometer and 20 micrometers, and the preferred thickness is between 3 micrometers and 5 micrometers; or The metal layer 30 may be a copper layer having a thickness between 1 micrometer and 10 micrometers plated on the copper seed layer 26 exposed by the photoresist layer opening 28a and having a thickness between 1 micrometer and 5 micrometers. A nickel layer is electroplated on the copper layer and a palladium layer having a thickness of between 1 micrometer and 5 micrometers is electroplated on the nickel layer, wherein the total thickness of the copper layer, the nickel layer and the palladium layer is 1 micron. Between 20 microns and a preferred thickness is between 3 microns and 5 microns; alternatively, the metal layer 30 can be a copper layer having a thickness between 1 micron and 13 microns plated in the photoresist layer opening 28a A nickel layer having a thickness of between 1 micrometer and 5 micrometers on the exposed copper seed layer 26 is electrolessly plated on the copper layer and a palladium layer having a thickness of between 0.05 micrometers and 2 micrometers. On the nickel layer, the total thickness of the copper layer, the nickel layer and the palladium layer is between 1 micrometer and 20 micrometers, and the thickness is preferably It is between 3 and 5 micrometers interposed.

請參閱第4F圖所示,在形成金屬層30之後,接著去除光阻層28,而去除方式比如是利用含有氨基化合物(amide)之有機溶劑去除光阻層28。此外,在去除光阻層28之後,可以先利用電漿(例如含有氧離子之電漿或是含有氟離子濃度小於200PPM與氧離子之電漿)清洗金屬層30與種子層26,藉以去除金屬層30上表面與種子層26上表面之光阻殘留物。Referring to FIG. 4F, after the metal layer 30 is formed, the photoresist layer 28 is subsequently removed, for example, by removing the photoresist layer 28 using an organic solvent containing an amide. In addition, after removing the photoresist layer 28, the metal layer 30 and the seed layer 26 may be cleaned by using a plasma (for example, a plasma containing oxygen ions or a plasma containing a fluoride ion concentration of less than 200 PPM and oxygen ions) to remove the metal. The upper surface of layer 30 and the photoresist residue on the upper surface of seed layer 26.

繼續請參閱第4G圖所示,依序去除未在金屬層30下方的種子層26與黏著/阻障層24。其中,去除未在金屬層 30下方的種子層26與黏著/阻障層24之方式比如是以蝕刻方式去除,而蝕刻方式又可分為乾蝕刻與濕蝕刻兩種方式,另乾蝕刻包括化學電漿蝕刻、濺擊蝕刻與化學氣體蝕刻。例如在濕蝕刻方面,當黏著/阻障層24為鈦鎢合金時,可使用含有雙氧水之溶液蝕刻去除,而當黏著/阻障層24為鈦時,可使用含氰氟酸的溶液蝕刻去除,另當種子層26為金時,可利用含有碘之蝕刻液(例如含有碘化鉀之蝕刻液)蝕刻去除,而當種子層26為銅時,可利用含有氫氧化銨(NH4 OH)之蝕刻液蝕刻去除;在乾蝕刻方面,當黏著/阻障層24為鈦或鈦鎢合金時,可使用含氯的電漿蝕刻去除或是利用反應性離子蝕刻(RIE)製程蝕刻去除,另當種子層26為金時,可使用離子研磨(ion milling)製程蝕刻去除或是利用氬氣濺擊蝕刻(Ar sputtering etching)製程蝕刻去除。Continuing to refer to FIG. 4G, the seed layer 26 and the adhesion/barrier layer 24 that are not under the metal layer 30 are sequentially removed. The manner of removing the seed layer 26 and the adhesion/barrier layer 24 not under the metal layer 30 is, for example, etching, and the etching method can be further divided into dry etching and wet etching, and dry etching includes chemistry. Plasma etching, splash etching and chemical gas etching. For example, in the wet etching, when the adhesion/barrier layer 24 is a titanium-tungsten alloy, it can be removed by etching using a solution containing hydrogen peroxide, and when the adhesion/barrier layer 24 is titanium, it can be removed by using a solution containing a cyanofluoric acid. When the seed layer 26 is gold, it can be removed by etching using an iodine-containing etching solution (for example, an etching solution containing potassium iodide), and when the seed layer 26 is copper, etching using ammonium hydroxide (NH 4 OH) can be utilized. Liquid etching removal; in dry etching, when the adhesion/barrier layer 24 is titanium or titanium tungsten alloy, it can be removed by plasma etching using chlorine or by reactive ion etching (RIE) process etching, and seed When layer 26 is gold, it can be removed by ion milling or by argon etching.

因此,本發明可形成一打線接墊22在一開口14a所暴露出之一接墊16上,且打線接墊22是由一黏著/阻障層24、位在黏著/阻障層24上的一種子層26與位在種子層26上的一金屬層30所構成。又,打線接墊22的材質包括鈦、鈦鎢合金、氮化鈦、鉻、鉭、氮化鉭、金、銅、鎳或鈀等。因此,透過上述形成打線接墊22的方式,本發明之打線接墊22可以是下列所述之形式。Therefore, the present invention can form a wire bonding pad 22 on one of the pads 16 exposed by the opening 14a, and the wire bonding pad 22 is formed by an adhesion/barrier layer 24 on the adhesion/barrier layer 24. A sub-layer 26 is formed with a metal layer 30 positioned on the seed layer 26. Moreover, the material of the wire bonding pad 22 includes titanium, titanium tungsten alloy, titanium nitride, chromium, tantalum, tantalum nitride, gold, copper, nickel or palladium. Therefore, the wire bonding pad 22 of the present invention may be in the form described below by the above-described manner of forming the wire bonding pads 22.

例如,打線接墊22包括厚度介於0.01微米至0.7微米之間(較佳則是介於0.03微米至0.7微米之間)的一含鈦金屬層(如一鈦層、一氮化鈦層或一鈦鎢合金層)位在開口14a所暴露出之材質主要包括銅的接墊16(或稱為銅墊) 上、厚度介於0.03微米至1微米之間(較佳則是介於0.03微米至0.7微米之間)且材質為金的一種子層位在此含鈦金屬層(如一鈦層、一氮化鈦層或一鈦鎢合金層)上以及厚度介於1微米至20微米之間(較佳厚度則是介於3微米至5微米之間或是介於1微米至4微米之間)的一金層位在此種子層上;或者,打線接墊22包括厚度介於0.01微米至0.7微米之間(較佳則是介於0.03微米至0.7微米之間)的一含鈦金屬層(如一鈦層、一氮化鈦層或一鈦鎢合金層)位在開口14a所暴露出之材質主要包括銅的接墊16(或稱為銅墊)上、厚度介於0.03微米至1微米之間(較佳則是介於0.03微米至0.7微米之間)且材質為鈀的一種子層位在此含鈦金屬層(如一鈦層、一氮化鈦層或一鈦鎢合金層)上以及厚度介於1微米至20微米之間(較佳厚度則是介於3微米至5微米之間或是介於1微米至4微米之間)的一鈀層位在此種子層上;或者,打線接墊22包括厚度介於0.01微米至0.7微米之間(較佳則是介於0.03微米至0.7微米之間)的一含鈦金屬層(如一鈦層、一氮化鈦層或一鈦鎢合金層)位在開口14a所暴露出之材質主要包括銅的接墊16(或稱為銅墊)上、厚度介於0.03微米至1微米之間(較佳則是介於0.03微米至0.7微米之間)且材質為銅的一種子層位在此含鈦金屬層(如一鈦層、一氮化鈦層或一鈦鎢合金層)上、厚度介於1微米至10微米之間的一銅層位在此種子層上、厚度介於1微米至5微米之間的一鎳層位在此銅層上以及厚度介於1微米至5微米之間的一金層位在此鎳層上,且鎳層、 銅層與金層三者的總厚度係介於1微米至20微米之間,而較佳厚度則是介於3微米至5微米之間;或者,打線接墊22包括厚度介於0.01微米至0.7微米之間(較佳則是介於0.03微米至0.7微米之間)的一含鈦金屬層(如一鈦層、一氮化鈦層或一鈦鎢合金層)位在開口14a所暴露出之材質主要包括銅的接墊16(或稱為銅墊)上、厚度介於0.03微米至1微米之間(較佳則是介於0.03微米至0.7微米之間)且材質為銅的一種子層位在此含鈦金屬層(如一鈦層、一氮化鈦層或一鈦鎢合金層)上、厚度介於1微米至10微米之間的一銅層位在此種子層上、厚度介於1微米至5微米之間的一鎳層位在此銅層上以及厚度介於1微米至5微米之間的一鈀層位在此鎳層上,且鎳層、銅層與鈀層三者的總厚度係介於1微米至20微米之間,而較佳厚度則是介於3微米至5微米之間。For example, the wire bonding pad 22 includes a titanium-containing metal layer (such as a titanium layer, a titanium nitride layer, or a titanium) having a thickness of between 0.01 micrometers and 0.7 micrometers (preferably between 0.03 micrometers and 0.7 micrometers). The material of the tungsten alloy layer exposed in the opening 14a mainly comprises a copper pad 16 (or a copper pad). a sub-layer having a thickness of between 0.03 micrometers and 1 micrometer (preferably between 0.03 micrometers and 0.7 micrometers) and having a gold material layer containing a titanium metal layer (eg, a titanium layer, a titanium nitride layer) a layer or a titanium-tungsten alloy layer) and a gold having a thickness between 1 micrometer and 20 micrometers (preferably a thickness of between 3 micrometers to 5 micrometers or between 1 micrometer and 4 micrometers) The layer is on the seed layer; or, the wire bonding pad 22 comprises a titanium-containing metal layer (such as a titanium layer, having a thickness of between 0.01 micrometers and 0.7 micrometers (preferably between 0.03 micrometers and 0.7 micrometers). a titanium nitride layer or a titanium-tungsten alloy layer) is formed on the surface of the opening 14a mainly comprising a copper pad 16 (or a copper pad) having a thickness of between 0.03 micrometers and 1 micrometer (preferably a sub-layer of palladium between 0.03 micrometers and 0.7 micrometers) and a titanium-containing metal layer (such as a titanium layer, a titanium nitride layer or a titanium-tungsten alloy layer) and a thickness of 1 micron. a palladium layer on the seed layer between 20 microns (preferably between 3 microns and 5 microns or between 1 and 4 microns); The wire bonding pad 22 includes a titanium-containing metal layer (such as a titanium layer, a titanium nitride layer or a titanium) having a thickness of between 0.01 micrometers and 0.7 micrometers (preferably between 0.03 micrometers and 0.7 micrometers). The tungsten alloy layer is located on the pad 16 (or copper pad) of the material mainly exposed by the opening 14a, and has a thickness of between 0.03 micrometers and 1 micrometer (preferably between 0.03 micrometers and 0.7 micrometers). And a material layer of copper is a copper layer having a thickness of between 1 micrometer and 10 micrometers on the titanium metal layer (such as a titanium layer, a titanium nitride layer or a titanium tungsten alloy layer). a layer of nickel on the seed layer having a thickness between 1 micrometer and 5 micrometers on the copper layer and a gold layer having a thickness between 1 micrometer and 5 micrometers on the nickel layer. And the nickel layer, The total thickness of the copper layer and the gold layer is between 1 micrometer and 20 micrometers, and the preferred thickness is between 3 micrometers and 5 micrometers; or the wire bonding pad 22 comprises a thickness of 0.01 micrometers to A titanium-containing metal layer (such as a titanium layer, a titanium nitride layer or a titanium-tungsten alloy layer) between 0.7 micrometers (preferably between 0.03 micrometers and 0.7 micrometers) is exposed to the opening 14a. A sub-layer of material consisting of copper pads 16 (or copper pads) having a thickness between 0.03 microns and 1 micron (preferably between 0.03 microns and 0.7 microns) and having a material of copper a copper layer having a thickness of between 1 micrometer and 10 micrometers on the titanium-containing metal layer (such as a titanium layer, a titanium nitride layer or a titanium-tungsten alloy layer) on the seed layer and having a thickness of 1 micrometer A nickel layer between 5 micrometers on the copper layer and a palladium layer having a thickness between 1 micrometer and 5 micrometers on the nickel layer, and the total of the nickel layer, the copper layer and the palladium layer The thickness is between 1 micrometer and 20 micrometers, and the preferred thickness is between 3 micrometers and 5 micrometers.

例如,打線接墊22包括厚度介於0.01微米至0.7微米之間(較佳則是介於0.03微米至0.7微米之間)的一鉻層位在開口14a所暴露出之材質主要包括銅的接墊16(或稱為銅墊)上、厚度介於0.03微米至1微米之間(較佳則是介於0.03微米至0.7微米之間)且材質為金的一種子層位在此鉻層上以及厚度介於1微米至20微米之間(較佳厚度則是介於3微米至5微米之間或是介於1微米至4微米之間)的一金層位在此種子層上;或者,打線接墊22包括厚度介於0.01微米至0.7微米之間(較佳則是介於0.03微米至0.7微米之間)的一鉻層位在開口14a所暴露出之材質主要包 括銅的接墊16(或稱為銅墊)上、厚度介於0.03微米至1微米之間(較佳則是介於0.03微米至0.7微米之間)且材質為鈀的一種子層位在此鉻層上以及厚度介於1微米至20微米之間(較佳厚度則是介於3微米至5微米之間或是介於1微米至4微米之間)的一鈀層位在此種子層上;或者,打線接墊22包括厚度介於0.01微米至0.7微米之間(較佳則是介於0.03微米至0.7微米之間)的一鉻層位在開口14a所暴露出之材質主要包括銅的接墊16(或稱為銅墊)上、厚度介於0.03微米至1微米之間(較佳則是介於0.03微米至0.7微米之間)且材質為銅的一種子層位在此鉻層上、厚度介於1微米至10微米之間的一銅層位在此種子層上、厚度介於1微米至5微米之間的一鎳層位在此銅層上以及厚度介於1微米至5微米之間的一金層位在此鎳層上,且鎳層、銅層與金層三者的總厚度係介於1微米至20微米之間,而較佳厚度則是介於3微米至5微米之間;或者,打線接墊22包括厚度介於0.01微米至0.7微米之間(較佳則是介於0.03微米至0.7微米之間)的一鉻層位在開口14a所暴露出之材質主要包括銅的接墊16(或稱為銅墊)上、厚度介於0.03微米至1微米之間(較佳則是介於0.03微米至0.7微米之間)且材質為銅的一種子層位在此鉻層上、厚度介於1微米至10微米之間的一銅層位在此種子層上、厚度介於1微米至5微米之間的一鎳層位在此銅層上以及厚度介於1微米至5微米之間的一鈀層位在此鎳層上,且鎳層、銅層與鈀層三者的總厚度係介於1微米至20微米之間,而較佳厚度則是 介於3微米至5微米之間。For example, the wire bonding pad 22 includes a chrome layer having a thickness between 0.01 micrometers and 0.7 micrometers (preferably between 0.03 micrometers and 0.7 micrometers). The material exposed in the opening 14a mainly includes copper pads. a sub-layer of 16 (or referred to as a copper pad) having a thickness between 0.03 micrometers and 1 micrometer (preferably between 0.03 micrometers and 0.7 micrometers) and having a gold content on the chromium layer and thickness a gold layer between 1 micrometer and 20 micrometers (preferably having a thickness between 3 micrometers and 5 micrometers or between 1 micrometer and 4 micrometers) on the seed layer; or The pad 22 includes a chrome layer having a thickness between 0.01 micrometers and 0.7 micrometers (preferably between 0.03 micrometers and 0.7 micrometers), and the material layer exposed in the opening 14a is mainly packaged. a sub-layer of copper on the pad 16 (or referred to as a copper pad) having a thickness between 0.03 microns and 1 micron (preferably between 0.03 microns and 0.7 microns) and having a palladium material a palladium layer on the chrome layer and between 1 micrometer and 20 micrometers in thickness (preferably between 3 micrometers and 5 micrometers or between 1 micrometer and 4 micrometers) Or; the wire bonding pad 22 comprises a chrome layer having a thickness of between 0.01 micrometers and 0.7 micrometers (preferably between 0.03 micrometers and 0.7 micrometers). The material exposed in the opening 14a mainly comprises copper. a sub-layer of copper on the pad 16 (or referred to as a copper pad) having a thickness between 0.03 micrometers and 1 micrometer (preferably between 0.03 micrometers and 0.7 micrometers) and having a material of copper a layer of copper having a thickness between 1 micrometer and 10 micrometers on the seed layer, a nickel layer having a thickness between 1 micrometer and 5 micrometers on the copper layer and a thickness ranging from 1 micrometer to 5 A gold layer between the micrometers is on the nickel layer, and the total thickness of the nickel layer, the copper layer and the gold layer is between 1 micrometer and 20 micrometers, and the preferred thickness is Between 3 microns and 5 microns; or, the wire bond pad 22 includes a chrome layer having a thickness between 0.01 microns and 0.7 microns (preferably between 0.03 microns and 0.7 microns) at the opening 14a The exposed material mainly comprises a copper pad 16 (or a copper pad) having a thickness between 0.03 micrometers and 1 micrometer (preferably between 0.03 micrometers and 0.7 micrometers) and a material of copper. a layer of nickel on the chrome layer having a thickness between 1 micrometer and 10 micrometers on the seed layer and a nickel layer having a thickness between 1 micrometer and 5 micrometers on the copper layer And a palladium layer having a thickness between 1 micrometer and 5 micrometers is on the nickel layer, and the total thickness of the nickel layer, the copper layer and the palladium layer is between 1 micrometer and 20 micrometers, and preferably. Thickness is Between 3 microns and 5 microns.

例如,打線接墊22包括厚度介於0.01微米至0.7微米之間(較佳則是介於0.03微米至0.7微米之間)的一含鉭金屬層(如一鉭層或一氮化鉭層)位在開口14a所暴露出之材質主要包括銅的接墊16(或稱為銅墊)上、厚度介於0.03微米至1微米之間(較佳則是介於0.03微米至0.7微米之間)且材質為金的一種子層位在此含鉭金屬層(如一鉭層或一氮化鉭層)上以及厚度介於1微米至20微米之間(較佳厚度則是介於3微米至5微米之間或是介於1微米至4微米之間)的一金層位在此種子層上;或者,打線接墊22包括厚度介於0.01微米至0.7微米之間(較佳則是介於0.03微米至0.7微米之間)的一含鉭金屬層(如一鉭層或一氮化鉭層)位在開口14a所暴露出之材質主要包括銅的接墊16(或稱為銅墊)上、厚度介於0.03微米至1微米之間(較佳則是介於0.03微米至0.7微米之間)且材質為鈀的一種子層位在此含鉭金屬層(如一鉭層或一氮化鉭層)上以及厚度介於1微米至20微米之間(較佳厚度則是介於3微米至5微米之間或是介於1微米至4微米之間)的一鈀層位在此種子層上;或者,打線接墊22包括厚度介於0.01微米至0.7微米之間(較佳則是介於0.03微米至0.7微米之間)的一含鉭金屬層(如一鉭層或一氮化鉭層)位在開口14a所暴露出之材質主要包括銅的接墊16(或稱為銅墊)上、厚度介於0.03微米至1微米之間(較佳則是介於0.03微米至0.7微米之間)且材質為銅的一種子層位在此含鉭金屬層(如一鉭層或一氮 化鉭層)上、厚度介於1微米至10微米之間的一銅層位在此種子層上、厚度介於1微米至5微米之間的一鎳層位在此銅層上以及厚度介於1微米至5微米之間的一金層位在此鎳層上,且鎳層、銅層與金層三者的總厚度係介於1微米至20微米之間,而較佳厚度則是介於3微米至5微米之間;或者,打線接墊22包括厚度介於0.01微米至0.7微米之間(較佳則是介於0.03微米至0.7微米之間)的一含鉭金屬層(如一鉭層或一氮化鉭層)位在開口14a所暴露出之材質主要包括銅的接墊16(或稱為銅墊)上、厚度介於0.03微米至1微米之間(較佳則是介於0.03微米至0.7微米之間)且材質為銅的一種子層位在此含鉭金屬層(如一鉭層或一氮化鉭層)上、厚度介於1微米至10微米之間的一銅層位在此種子層上、厚度介於1微米至5微米之間的一鎳層位在此銅層上以及厚度介於1微米至5微米之間的一鈀層位在此鎳層上,且鎳層、銅層與鈀層三者的總厚度係介於1微米至20微米之間,而較佳厚度則是介於3微米至5微米之間。For example, the wire bonding pad 22 includes a germanium-containing metal layer (such as a germanium layer or a tantalum nitride layer) having a thickness between 0.01 micrometers and 0.7 micrometers (preferably between 0.03 micrometers and 0.7 micrometers). The material exposed by the opening 14a mainly comprises a copper pad 16 (or a copper pad) having a thickness of between 0.03 micrometers and 1 micrometer (preferably between 0.03 micrometers and 0.7 micrometers) and the material is A sub-layer of gold is on the tantalum-containing metal layer (such as a tantalum layer or a tantalum nitride layer) and has a thickness of between 1 micrometer and 20 micrometers (preferably, the thickness is between 3 micrometers and 5 micrometers). Or a gold layer between 1 micrometer and 4 micrometers on the seed layer; or, the wire bonding pad 22 includes a thickness between 0.01 micrometers and 0.7 micrometers (preferably between 0.03 micrometers and 0.7 micrometers) A layer of germanium containing metal (such as a layer of germanium or a layer of tantalum nitride) is located on the opening 16a of the material which is mainly composed of copper pads 16 (or copper pads) and has a thickness of 0.03. a sub-layer of between 1 micron and 1 micron (preferably between 0.03 micron and 0.7 micron) and having a palladium-like metal layer (eg, a layer of germanium) Or a palladium nitride layer and a palladium layer having a thickness between 1 micrometer and 20 micrometers (preferably a thickness of between 3 micrometers to 5 micrometers or between 1 micrometer and 4 micrometers) Positioned on the seed layer; or, the wire bonding pad 22 includes a germanium-containing metal layer (such as a germanium layer or a layer) having a thickness of between 0.01 micrometers and 0.7 micrometers (preferably between 0.03 micrometers and 0.7 micrometers). The tantalum nitride layer is on the pad 16 (or copper pad) which is exposed on the opening 14a and has a thickness of between 0.03 micrometers and 1 micrometer (preferably between 0.03 micrometers and 0.7). a sub-layer of copper between the micro-layers and a copper-containing layer (such as a layer of germanium or nitrogen) a layer of copper having a thickness between 1 micrometer and 10 micrometers on the seed layer, a nickel layer having a thickness between 1 micrometer and 5 micrometers on the copper layer and a thickness layer A gold layer between 1 micrometer and 5 micrometers is on the nickel layer, and the total thickness of the nickel layer, the copper layer and the gold layer is between 1 micrometer and 20 micrometers, and the preferred thickness is Between 3 microns and 5 microns; or, the wire bond pad 22 comprises a layer of germanium containing metal (eg, a stack of between 0.01 microns and 0.7 microns thick) The layer or the tantalum nitride layer is located on the pad 16 (or copper pad) of the material mainly exposed by the opening 14a, and has a thickness of between 0.03 micrometers and 1 micrometer (preferably between 0.03). a sub-layer of copper between 0.7 micrometers and 0.7 micrometers and having a thickness of between 1 micrometer and 10 micrometers on a tantalum-containing metal layer (such as a tantalum layer or a tantalum nitride layer) a nickel layer on the seed layer having a thickness between 1 micrometer and 5 micrometers on the copper layer and a palladium layer having a thickness between 1 micrometer and 5 micrometers in the nickel layer , And the nickel layer, the total thickness of the copper-based layer and a palladium layer three between between 1 to 20 microns, and the thickness is preferably between 3 to 5 microns.

例如,打線接墊22包括厚度介於0.01微米至0.7微米之間(較佳則是介於0.03微米至0.7微米之間)的一含鈦金屬層(如一鈦層、一氮化鈦層或一鈦鎢合金層)位在開口14a所暴露出之材質主要包括鋁的接墊16(或稱為鋁墊)上、厚度介於0.03微米至1微米之間(較佳則是介於0.03微米至0.7微米之間)且材質為金的一種子層位在此含鈦金屬層(如一鈦層、一氮化鈦層或一鈦鎢合金層)上以及厚度 介於1微米至20微米之間(較佳厚度則是介於3微米至5微米之間或是介於1微米至4微米之間)的一金層位在此種子層上;或者,打線接墊22包括厚度介於0.01微米至0.7微米之間(較佳則是介於0.03微米至0.7微米之間)的一含鈦金屬層(如一鈦層、一氮化鈦層或一鈦鎢合金層)位在開口14a所暴露出之材質主要包括鋁的接墊16(或稱為鋁墊)上、厚度介於0.03微米至1微米之間(較佳則是介於0.03微米至0.7微米之間)且材質為鈀的一種子層位在此含鈦金屬層(如一鈦層、一氮化鈦層或一鈦鎢合金層)上以及厚度介於1微米至20微米之間(較佳厚度則是介於3微米至5微米之間或是介於1微米至4微米之間)的一鈀層位在此種子層上;或者,打線接墊22包括厚度介於0.01微米至0.7微米之間(較佳則是介於0.03微米至0.7微米之間)的一含鈦金屬層(如一鈦層、一氮化鈦層或一鈦鎢合金層)位在開口14a所暴露出之材質主要包括鋁的接墊16(或稱為鋁墊)上、厚度介於0.03微米至1微米之間(較佳則是介於0.03微米至0.7微米之間)且材質為銅的一種子層位在此含鈦金屬層(如一鈦層、一氮化鈦層或一鈦鎢合金層)上、厚度介於1微米至10微米之間的一銅層位在此種子層上、厚度介於1微米至5微米之間的一鎳層位在此銅層上以及厚度介於1微米至5微米之間的一金層位在此鎳層上,且鎳層、銅層與金層三者的總厚度係介於1微米至20微米之間,而較佳厚度則是介於3微米至5微米之間;或者,打線接墊22包括厚度介於0.01微米至0.7微米之間(較佳則是介於 0.03微米至0.7微米之間)的一含鈦金屬層(如一鈦層、一氮化鈦層或一鈦鎢合金層)位在開口14a所暴露出之材質主要包括鋁的接墊16(或稱為鋁墊)上、厚度介於0.03微米至1微米之間(較佳則是介於0.03微米至0.7微米之間)且材質為銅的一種子層位在此含鈦金屬層(如一鈦層、一氮化鈦層或一鈦鎢合金層)上、厚度介於1微米至10微米之間的一銅層位在此種子層上、厚度介於1微米至5微米之間的一鎳層位在此銅層上以及厚度介於1微米至5微米之間的一鈀層位在此鎳層上,且鎳層、銅層與鈀層三者的總厚度係介於1微米至20微米之間,而較佳厚度則是介於3微米至5微米之間。For example, the wire bonding pad 22 includes a titanium-containing metal layer (such as a titanium layer, a titanium nitride layer, or a titanium) having a thickness of between 0.01 micrometers and 0.7 micrometers (preferably between 0.03 micrometers and 0.7 micrometers). The material of the tungsten alloy layer exposed on the opening 14a mainly comprises a pad 16 (or aluminum pad) of aluminum, and has a thickness of between 0.03 micrometers and 1 micrometer (preferably between 0.03 micrometers and 0.7 micrometers). And a sub-layer of gold-based material on the titanium-containing metal layer (such as a titanium layer, a titanium nitride layer or a titanium-tungsten alloy layer) and the thickness a gold layer between 1 micrometer and 20 micrometers (preferably having a thickness between 3 micrometers and 5 micrometers or between 1 micrometer and 4 micrometers) on the seed layer; or The pad 22 comprises a titanium-containing metal layer (such as a titanium layer, a titanium nitride layer or a titanium-tungsten alloy layer) having a thickness of between 0.01 micrometers and 0.7 micrometers (preferably between 0.03 micrometers and 0.7 micrometers). The material exposed in the opening 14a mainly comprises a pad 16 (or aluminum pad) of aluminum, and has a thickness of between 0.03 micrometers and 1 micrometer (preferably between 0.03 micrometers and 0.7 micrometers). And a sub-layer of palladium is on the titanium-containing metal layer (such as a titanium layer, a titanium nitride layer or a titanium-tungsten alloy layer) and the thickness is between 1 micrometer and 20 micrometers (the preferred thickness is a palladium layer between 3 microns and 5 microns or between 1 micrometer and 4 microns is on the seed layer; alternatively, the wire bond pads 22 comprise between 0.01 microns and 0.7 microns thick ( a titanium-containing metal layer (such as a titanium layer, a titanium nitride layer or a titanium-tungsten alloy layer) preferably between 0.03 micrometers and 0.7 micrometers is exposed in the opening 14a. The material mainly comprises a sub-layer of copper on the pad 16 (or aluminum pad) of thickness, between 0.03 micrometers and 1 micrometer (preferably between 0.03 micrometers and 0.7 micrometers) and made of copper. a copper layer on the titanium-containing metal layer (such as a titanium layer, a titanium nitride layer or a titanium-tungsten alloy layer) having a thickness between 1 micrometer and 10 micrometers on the seed layer and having a thickness between A nickel layer between 1 micrometer and 5 micrometers is on the copper layer and a gold layer having a thickness between 1 micrometer and 5 micrometers is on the nickel layer, and the nickel layer, the copper layer and the gold layer are three The total thickness is between 1 micrometer and 20 micrometers, and the preferred thickness is between 3 micrometers and 5 micrometers; or the wire bonding pad 22 comprises a thickness between 0.01 micrometers and 0.7 micrometers (preferably Is between A titanium-containing metal layer (such as a titanium layer, a titanium nitride layer or a titanium-tungsten alloy layer) between 0.03 micrometers and 0.7 micrometers is exposed to the opening 14a and mainly comprises a pad 16 of aluminum (or a sub-layer of copper on the aluminum pad, having a thickness between 0.03 micrometers and 1 micrometer (preferably between 0.03 micrometers and 0.7 micrometers) and having a material of copper, such as a titanium layer, a layer of copper on a titanium nitride layer or a titanium-tungsten alloy layer having a thickness between 1 micrometer and 10 micrometers on the seed layer and a nickel layer between 1 micrometer and 5 micrometers thick A palladium layer on the copper layer and between 1 micrometer and 5 micrometers in thickness is on the nickel layer, and the total thickness of the nickel layer, the copper layer and the palladium layer is between 1 micrometer and 20 micrometers. The preferred thickness is between 3 microns and 5 microns.

例如,打線接墊22包括厚度介於0.01微米至0.7微米之間(較佳則是介於0.03微米至0.7微米之間)的一鉻層位在開口14a所暴露出之材質主要包括鋁的接墊16(或稱為鋁墊)上、厚度介於0.03微米至1微米之間(較佳則是介於0.03微米至0.7微米之間)且材質為金的一種子層位在此鉻層上以及厚度介於1微米至20微米之間(較佳厚度則是介於3微米至5微米之間或是介於1微米至4微米之間)的一金層位在此種子層上;或者,打線接墊22包括厚度介於0.01微米至0.7微米之間(較佳則是介於0.03微米至0.7微米之間)的一鉻層位在開口14a所暴露出之材質主要包括鋁的接墊16(或稱為鋁墊)上、厚度介於0.03微米至1微米之間(較佳則是介於0.03微米至0.7微米之間)且材質為鈀的一種子層位在此鉻層上以及厚度介於1微米至20微米 之間(較佳厚度則是介於3微米至5微米之間或是介於1微米至4微米之間)的一鈀層位在此種子層上;或者,打線接墊22包括厚度介於0.01微米至0.7微米之間(較佳則是介於0.03微米至0.7微米之間)的一鉻層位在開口14a所暴露出之材質主要包括鋁的接墊16(或稱為鋁墊)上、厚度介於0.03微米至1微米之間(較佳則是介於0.03微米至0.7微米之間)且材質為銅的一種子層位在此鉻層上、厚度介於1微米至10微米之間的一銅層位在此種子層上、厚度介於1微米至5微米之間的一鎳層位在此銅層上以及厚度介於1微米至5微米之間的一金層位在此鎳層上,且鎳層、銅層與金層三者的總厚度係介於1微米至20微米之間,而較佳厚度則是介於3微米至5微米之間;或者,打線接墊22包括厚度介於0.01微米至0.7微米之間(較佳則是介於0.03微米至0.7微米之間)的一鉻層位在開口14a所暴露出之材質主要包括鋁的接墊16(或稱為鋁墊)上、厚度介於0.03微米至1微米之間(較佳則是介於0.03微米至0.7微米之間)且材質為銅的一種子層位在此鉻層上、厚度介於1微米至10微米之間的一銅層位在此種子層上、厚度介於1微米至5微米之間的一鎳層位在此銅層上以及厚度介於1微米至5微米之間的一鈀層位在此鎳層上,且鎳層、銅層與鈀層三者的總厚度係介於1微米至20微米之間,而較佳厚度則是介於3微米至5微米之間。For example, the wire bonding pad 22 includes a chrome layer having a thickness between 0.01 micrometers and 0.7 micrometers (preferably between 0.03 micrometers and 0.7 micrometers). The material exposed in the opening 14a mainly includes aluminum pads. a sub-layer of 16 (or referred to as an aluminum pad) having a thickness between 0.03 micrometers and 1 micrometer (preferably between 0.03 micrometers and 0.7 micrometers) and having a gold content on the chromium layer and thickness a gold layer between 1 micrometer and 20 micrometers (preferably having a thickness between 3 micrometers and 5 micrometers or between 1 micrometer and 4 micrometers) on the seed layer; or The pad 22 includes a chrome layer having a thickness between 0.01 micrometers and 0.7 micrometers (preferably between 0.03 micrometers and 0.7 micrometers). The material exposed in the opening 14a mainly comprises a pad 16 of aluminum (or a sub-layer of a material having a thickness of between 0.03 μm and 1 μm (preferably between 0.03 μm and 0.7 μm) and having a material palladium on the chromium layer and having a thickness of 1 Micron to 20 microns A palladium layer between (preferably a thickness of between 3 microns and 5 microns or between 1 micron and 4 microns) is on the seed layer; or the wire bond pad 22 comprises a thickness between A chrome layer of between 0.01 micrometers and 0.7 micrometers (preferably between 0.03 micrometers and 0.7 micrometers) is exposed on the opening 14a. The material mainly comprises aluminum pads 16 (or aluminum pads). a sub-layer of copper having a thickness between 0.03 micrometers and 1 micrometer (preferably between 0.03 micrometers and 0.7 micrometers) and having a thickness of between 1 micrometer and 10 micrometers. a layer of copper on the seed layer having a thickness between 1 micrometer and 5 micrometers on the copper layer and a gold layer having a thickness between 1 micrometer and 5 micrometers in the nickel layer The total thickness of the nickel layer, the copper layer and the gold layer is between 1 micrometer and 20 micrometers, and the preferred thickness is between 3 micrometers and 5 micrometers; or the wire bonding pad 22 comprises A chrome layer having a thickness between 0.01 micrometers and 0.7 micrometers (preferably between 0.03 micrometers and 0.7 micrometers) is exposed to the opening 14a. a pad layer 16 (or referred to as an aluminum pad) having a thickness between 0.03 micrometers and 1 micrometer (preferably between 0.03 micrometers and 0.7 micrometers) and a sub-layer of copper material is present in the chromium layer a layer of copper having a thickness between 1 micrometer and 10 micrometers on the seed layer, a nickel layer having a thickness between 1 micrometer and 5 micrometers on the copper layer and a thickness of 1 micron to A palladium layer between 5 microns is on the nickel layer, and the total thickness of the nickel layer, the copper layer and the palladium layer is between 1 micrometer and 20 micrometers, and the preferred thickness is between 3 micrometers. Between 5 microns.

例如,打線接墊22包括厚度介於0.01微米至0.7微米之間(較佳則是介於0.03微米至0.7微米之間)的一含鉭 金屬層(如一鉭層或一氮化鉭層)位在開口14a所暴露出之材質主要包括鋁的接墊16(或稱為鋁墊)上、厚度介於0.03微米至1微米之間(較佳則是介於0.03微米至0.7微米之間)且材質為金的一種子層位在此含鉭金屬層(如一鉭層或一氮化鉭層)上以及厚度介於1微米至20微米之間(較佳厚度則是介於3微米至5微米之間或是介於1微米至4微米之間)的一金層位在此種子層上;或者,打線接墊22包括厚度介於0.01微米至0.7微米之間(較佳則是介於0.03微米至0.7微米之間)的一含鉭金屬層(如一鉭層或一氮化鉭層)位在開口14a所暴露出之材質主要包括鋁的接墊16(或稱為鋁墊)上、厚度介於0.03微米至1微米之間(較佳則是介於0.03微米至0.7微米之間)且材質為鈀的一種子層位在此含鉭金屬層(如一鉭層或一氮化鉭層)上以及厚度介於1微米至20微米之間(較佳厚度則是介於3微米至5微米之間或是介於1微米至4微米之間)的一鈀層位在此種子層上;或者,打線接墊22包括厚度介於0.01微米至0.7微米之間(較佳則是介於0.03微米至0.7微米之間)的一含鉭金屬層(如一鉭層或一氮化鉭層)位在開口14a所暴露出之材質主要包括鋁的接墊16(或稱為鋁墊)上、厚度介於0.03微米至1微米之間(較佳則是介於0.03微米至0.7微米之間)且材質為銅的一種子層位在此含鉭金屬層(如一鉭層或一氮化鉭層)上、厚度介於1微米至10微米之間的一銅層位在此種子層上、厚度介於1微米至5微米之間的一鎳層位在此銅層上以及厚度介於1微米至5微米之間的一金層位在 此鎳層上,且鎳層、銅層與金層三者的總厚度係介於1微米至20微米之間,而較佳厚度則是介於3微米至5微米之間;或者,打線接墊22包括厚度介於0.01微米至0.7微米之間(較佳則是介於0.03微米至0.7微米之間)的一含鉭金屬層(如一鉭層或一氮化鉭層)位在開口14a所暴露出之材質主要包括鋁的接墊16(或稱為鋁墊)上、厚度介於0.03微米至1微米之間(較佳則是介於0.03微米至0.7微米之間)且材質為銅的一種子層位在此含鉭金屬層(如一鉭層或一氮化鉭層)上、厚度介於1微米至10微米之間的一銅層位在此種子層上、厚度介於1微米至5微米之間的一鎳層位在此銅層上以及厚度介於1微米至5微米之間的一鈀層位在此鎳層上,且鎳層、銅層與鈀層三者的總厚度係介於1微米至20微米之間,而較佳厚度則是介於3微米至5微米之間。For example, the wire bond pad 22 includes a germanium having a thickness between 0.01 microns and 0.7 microns (preferably between 0.03 microns and 0.7 microns). The metal layer (such as a tantalum layer or a tantalum nitride layer) is located on the opening 14a of the material mainly including the aluminum pad 16 (or aluminum pad), and the thickness is between 0.03 micrometers and 1 micrometer (more) Preferably, a sub-layer of gold is between 0.03 micrometers and 0.7 micrometers and is made of a base metal layer (such as a tantalum layer or a tantalum nitride layer) and a thickness of between 1 micrometer and 20 micrometers. (a preferred thickness is between 3 microns and 5 microns or between 1 micron and 4 microns) a gold layer on the seed layer; or, the wire bond pad 22 comprises a thickness of 0.01 microns A metal-containing layer (such as a tantalum layer or a tantalum nitride layer) between 0.7 micrometers (preferably between 0.03 micrometers and 0.7 micrometers) is exposed to the opening 14a and mainly comprises aluminum. a sub-layer of a pad 16 (or referred to as an aluminum pad) having a thickness between 0.03 micrometers and 1 micrometer (preferably between 0.03 micrometers and 0.7 micrometers) and having a palladium material (such as a tantalum layer or a tantalum nitride layer) and a thickness between 1 micron and 20 micron (preferably, the thickness is between 3 micrometers and 5 micrometers or between 1 micron) a palladium layer between 4 microns) is on the seed layer; alternatively, the wire bond pad 22 comprises a thickness between 0.01 microns and 0.7 microns (preferably between 0.03 microns and 0.7 microns) The bismuth-containing metal layer (such as a germanium layer or a tantalum nitride layer) is exposed on the opening 14a, and the material mainly includes the aluminum pad 16 (or aluminum pad) and has a thickness of between 0.03 micrometers and 1 micrometer. (preferably between 0.03 micrometers and 0.7 micrometers) and a sub-layer of copper material on the tantalum-containing metal layer (such as a tantalum layer or a tantalum nitride layer) having a thickness of between 1 micrometer and 10 micrometers A layer of copper between the layer of copper on the seed layer and having a thickness between 1 micrometer and 5 micrometers on the copper layer and a gold layer between 1 micrometer and 5 micrometers in thickness The nickel layer, and the total thickness of the nickel layer, the copper layer and the gold layer are between 1 micrometer and 20 micrometers, and the preferred thickness is between 3 micrometers and 5 micrometers; or The mat 22 includes a tantalum-containing metal layer (such as a tantalum layer or a tantalum nitride layer) having a thickness between 0.01 micrometers and 0.7 micrometers (preferably between 0.03 micrometers and 0.7 micrometers) exposed at the opening 14a. The material is mainly composed of a pad 16 (or aluminum pad) of aluminum, a thickness of between 0.03 micrometers and 1 micrometer (preferably between 0.03 micrometers and 0.7 micrometers) and a material of copper. A copper layer having a thickness between 1 micrometer and 10 micrometers on the germanium-containing metal layer (such as a germanium layer or a tantalum nitride layer) on the seed layer and having a thickness of 1 micrometer to 5 micrometers A nickel layer between the copper layer and a palladium layer having a thickness between 1 micrometer and 5 micrometers is on the nickel layer, and the total thickness of the nickel layer, the copper layer and the palladium layer is It is between 1 micrometer and 20 micrometers, and a preferred thickness is between 3 micrometers and 5 micrometers.

接著,於完成打線接墊22之後,即完成由上述步驟所形成之一半導體晶圓。再來,透過切割半導體晶圓,以形成複數半導體晶片23,如第3圖所示。Then, after the wire bonding pad 22 is completed, one of the semiconductor wafers formed by the above steps is completed. Then, the semiconductor wafer is cut by dicing to form a plurality of semiconductor wafers 23 as shown in FIG.

請參閱第5A圖與第5B圖所示,本發明可形成厚度介於1微米至20微米之間(較佳厚度則是介於3微米至5微米之間)的一打線接墊22在一金屬保護蓋18上,且此打線接墊22係作為接合一打線導線的打線接點,其中金屬保護蓋18係位在一開口14a所暴露出之一接墊16(例如銅墊)上,且此金屬保護蓋18比如包括一含鉭金屬層(例如一鉭層或一氮化鉭層)位在接墊16(例如銅墊)上,以及一含鋁金 屬層(例如一鋁層或一鋁合金層)位在此含鉭金屬層上;或者,此金屬保護蓋18包括一含鋁金屬層(例如一鋁層或一鋁合金層)位在接墊16(例如銅墊)上。有關形成打線接墊22在金屬保護蓋18上的方法,請參閱第6圖系列的敘述。另,在第5A圖中,打線接墊22係位在金屬保護蓋18的全部上表面上以及位在金屬保護蓋18周圍之保護層8上;在第5B圖中,打線接墊22係位在金屬保護蓋18的部份上表面上。本發明在第6圖系列的說明係以「打線接墊22位在金屬保護蓋18的全部上表面上以及位在金屬保護蓋18周圍之保護層8上」的內容進行敘述,然熟習該技術者當可藉由第6圖系列的說明,以「打線接墊22位在金屬保護蓋18的部份上表面上」的方式來據以實施。此外,在形成打線接墊22之後,透過切割半導體晶圓,以形成複數半導體晶片31,如第5A圖與第5B圖所示。Referring to FIGS. 5A and 5B, the present invention can form a wire bonding pad 22 having a thickness of between 1 micrometer and 20 micrometers (preferably, a thickness of between 3 micrometers and 5 micrometers). a metal protection cover 18, and the wire bonding pad 22 is used as a wire bonding joint for bonding a wire bonding wire, wherein the metal protective cover 18 is fastened to a pad 16 (for example, a copper pad) exposed by an opening 14a, and The metal protective cover 18 includes, for example, a ruthenium-containing metal layer (for example, a tantalum layer or a tantalum nitride layer) on the pad 16 (for example, a copper pad), and an aluminum-containing gold layer. a genus layer (for example, an aluminum layer or an aluminum alloy layer) is disposed on the ruthenium-containing metal layer; or the metal protection cover 18 includes an aluminum-containing metal layer (for example, an aluminum layer or an aluminum alloy layer) on the pad 16 (for example, copper pad). For the method of forming the wire bonding pad 22 on the metal protective cover 18, please refer to the description of the series of Fig. 6. In addition, in FIG. 5A, the wire bonding pads 22 are fastened on the entire upper surface of the metal protective cover 18 and on the protective layer 8 around the metal protective cover 18; in FIG. 5B, the wire bonding pads 22 are in the position On the upper surface of a portion of the metal protective cover 18. The description of the series of Fig. 6 of the present invention is described in the context of "the wire bonding pad 22 is located on the entire upper surface of the metal protective cover 18 and the protective layer 8 located around the metal protective cover 18", and is familiar with the technology. It can be implemented by means of the description of the series of Fig. 6, "the wire pad 22 is placed on the upper surface of the metal protection cover 18". Further, after the wire bonding pads 22 are formed, the semiconductor wafers are cut by dicing to form a plurality of semiconductor wafers 31 as shown in FIGS. 5A and 5B.

請參閱第6A圖所示,形成厚度介於0.01微米至0.7微米之間(較佳則是介於0.03微米至0.7微米之間)的一黏著/阻障層24在保護層14上與金屬保護蓋18上,其中金屬保護蓋18係位在材質主要包括銅的接墊16(即銅墊)上,且此金屬保護蓋18比如包括一含鉭金屬層(例如一鉭層或一氮化鉭層)位在此材質主要包括銅的接墊16上以及包括一含鋁金屬層(例如一鋁層或一鋁合金層)位在此含鉭金屬層上,或者金屬保護蓋18為一含鋁金屬層(例如一鋁層或一鋁合金層)位在此材質主要包括銅的接墊16上,而黏著/阻障層24係位在含鋁金屬層(例如一鋁層或一鋁合金 層)上。另,黏著/阻障層24的材質包括鈦、鈦鎢合金、氮化鈦、鉻、鉭、氮化鉭或耐火金屬合金(alloy of refractory metal)等。Referring to FIG. 6A, an adhesion/barrier layer 24 having a thickness between 0.01 micrometers and 0.7 micrometers (preferably between 0.03 micrometers and 0.7 micrometers) is formed on the protective layer 14 and the metal protective cover. 18, wherein the metal protective cover 18 is fastened on a pad 16 (ie, a copper pad) whose material mainly includes copper, and the metal protective cover 18 includes, for example, a ruthenium-containing metal layer (for example, a tantalum layer or a tantalum nitride layer). The material is mainly composed of a copper pad 16 and includes an aluminum-containing metal layer (for example, an aluminum layer or an aluminum alloy layer) on the germanium-containing metal layer, or the metal protective cover 18 is an aluminum-containing metal. The layer (for example, an aluminum layer or an aluminum alloy layer) is located on the pad 16 of the material mainly comprising copper, and the adhesion/barrier layer 24 is tied to the aluminum-containing metal layer (for example, an aluminum layer or an aluminum alloy). Layer). In addition, the material of the adhesion/barrier layer 24 includes titanium, titanium tungsten alloy, titanium nitride, chromium, tantalum, tantalum nitride or alloy of refractory metal.

例如,黏著/阻障層24可以是厚度介於0.01微米至0.7微米之間(較佳則是介於0.03微米至0.7微米之間)的一鈦層濺鍍在保護層14上與金屬保護蓋18上,其中金屬保護蓋18包括一含鉭金屬層(例如一鉭層或一氮化鉭層)位在材質主要包括銅的接墊16上以及一含鋁金屬層(例如一鋁層或一鋁合金層)位在此含鉭金屬層上,或者金屬保護蓋18為一含鋁金屬層(例如一鋁層或一鋁合金層)位在此材質主要包括銅的接墊16上,而此鈦層係濺鍍在含鋁金屬層(例如一鋁層或一鋁合金層)上;或者,黏著/阻障層24可以是厚度介於0.01微米至0.7微米之間(較佳則是介於0.03微米至0.7微米之間)的一鈦鎢合金層濺鍍在保護層14上與金屬保護蓋18上,其中金屬保護蓋18包括一含鉭金屬層(例如一鉭層或一氮化鉭層)位在材質主要包括銅的接墊16上以及一含鋁金屬層(例如一鋁層或一鋁合金層)位在此含鉭金屬層上,或者金屬保護蓋18為一含鋁金屬層(例如一鋁層或一鋁合金層)位在此材質主要包括銅的接墊16上,而此鈦鎢合金層係濺鍍在含鋁金屬層(例如一鋁層或一鋁合金層)上;或者,黏著/阻障層24可以是厚度介於0.01微米至0.7微米之間(較佳則是介於0.03微米至0.7微米之間)的一氮化鈦層濺鍍在保護層14上與金屬保護蓋18上,其中金屬保護蓋18包括一含鉭金屬層(例如一鉭層或一氮 化鉭層)位在材質主要包括銅的接墊16上以及一含鋁金屬層(例如一鋁層或一鋁合金層)位在此含鉭金屬層上,或者金屬保護蓋18為一含鋁金屬層(例如一鋁層或一鋁合金層)位在此材質主要包括銅的接墊16上,而此氮化鈦層係濺鍍在含鋁金屬層(例如一鋁層或一鋁合金層)上;或者,黏著/阻障層24可以是厚度介於0.01微米至0.7微米之間(較佳則是介於0.03微米至0.7微米之間)的一氮化鉭層濺鍍在保護層14上與金屬保護蓋18上,其中金屬保護蓋18包括一含鉭金屬層(例如一鉭層或一氮化鉭層)位在材質主要包括銅的接墊16上以及一含鋁金屬層(例如一鋁層或一鋁合金層)位在此含鉭金屬層上,或者金屬保護蓋18為一含鋁金屬層(例如一鋁層或一鋁合金層)位在此材質主要包括銅的接墊16上,而此氮化鉭層係濺鍍在的含鋁金屬層(例如一鋁層或一鋁合金層)上;或者,黏著/阻障層24可以是厚度介於0.01微米至0.7微米之間(較佳則是介於0.03微米至0.7微米之間)的一鉭層濺鍍在保護層14上與金屬保護蓋18上,其中金屬保護蓋18包括一含鉭金屬層(例如一鉭層或一氮化鉭層)位在材質主要包括銅的接墊16上以及一含鋁金屬層(例如一鋁層或一鋁合金層)位在此含鉭金屬層上,或者金屬保護蓋18為一含鋁金屬層(例如一鋁層或一鋁合金層)位在此材質主要包括銅的接墊16上,而此鉭層係濺鍍在含鋁金屬層(例如一鋁層或一鋁合金層)上;或者,黏著/阻障層24可以是厚度介於0.01微米至0.7微米之間(較佳則是介於0.03微米至0.7微米之間)的一耐火金 屬合金層濺鍍在保護層14上與金屬保護蓋18上,其中金屬保護蓋18包括一含鉭金屬層(例如一鉭層或一氮化鉭層)位在材質主要包括銅的接墊16上以及一含鋁金屬層(例如一鋁層或一鋁合金層)位在此含鉭金屬層上,或者金屬保護蓋18為一含鋁金屬層(例如一鋁層或一鋁合金層)位在此材質主要包括銅的接墊16上,而此耐火金屬合金層係濺鍍在含鋁金屬層(例如一鋁層或一鋁合金層)上。For example, the adhesion/barrier layer 24 can be a titanium layer having a thickness between 0.01 microns and 0.7 microns (preferably between 0.03 microns and 0.7 microns) sputtered over the protective layer 14 and the metal protective cover 18. The metal protective cover 18 includes a ruthenium-containing metal layer (for example, a tantalum layer or a tantalum nitride layer) on the pad 16 mainly composed of copper and an aluminum-containing metal layer (for example, an aluminum layer or an aluminum layer). The alloy layer is located on the base metal-containing layer, or the metal protective cover 18 is an aluminum-containing metal layer (for example, an aluminum layer or an aluminum alloy layer) on the pad 16 of the material mainly comprising copper, and the titanium The layer is sputtered on the aluminum-containing metal layer (for example, an aluminum layer or an aluminum alloy layer); or the adhesion/barrier layer 24 may have a thickness of between 0.01 μm and 0.7 μm (preferably between 0.03 μm) A titanium-tungsten alloy layer of between 0.7 micrometers is sputtered onto the protective layer 14 and the metal protective cover 18, wherein the metal protective cover 18 comprises a germanium-containing metal layer (for example, a germanium layer or a tantalum nitride layer). On the pad 16 whose material mainly comprises copper and an aluminum-containing metal layer (for example, an aluminum layer or an aluminum alloy layer) The layer or the metal protective cover 18 is an aluminum-containing metal layer (for example, an aluminum layer or an aluminum alloy layer) on the pad 16 of the material mainly comprising copper, and the titanium-tungsten alloy layer is sputtered on the aluminum-containing layer. a metal layer (for example, an aluminum layer or an aluminum alloy layer); or, the adhesion/barrier layer 24 may have a thickness of between 0.01 micrometers and 0.7 micrometers (preferably between 0.03 micrometers and 0.7 micrometers). A titanium nitride layer is sputtered onto the protective layer 14 and the metal protective cover 18, wherein the metal protective cover 18 comprises a layer of germanium containing metal (eg, a layer of germanium or a layer of nitrogen) The ruthenium layer is located on the pad 16 mainly composed of copper and an aluminum-containing metal layer (for example, an aluminum layer or an aluminum alloy layer) on the ruthenium-containing metal layer, or the metal protection cover 18 is an aluminum-containing layer. A metal layer (such as an aluminum layer or an aluminum alloy layer) is located on the pad 16 of the material mainly comprising copper, and the titanium nitride layer is sputtered on the aluminum-containing metal layer (for example, an aluminum layer or an aluminum alloy layer). Or the adhesion/barrier layer 24 may be a tantalum nitride layer having a thickness between 0.01 micrometers and 0.7 micrometers (preferably between 0.03 micrometers and 0.7 micrometers) sputtered on the protective layer 14. And a metal protective cover 18, wherein the metal protective cover 18 comprises a ruthenium-containing metal layer (for example, a tantalum layer or a tantalum nitride layer) on the pad 16 mainly composed of copper and an aluminum-containing metal layer (for example, The aluminum layer or the aluminum alloy layer is located on the base metal layer, or the metal protective cover 18 is an aluminum-containing metal layer (for example, an aluminum layer or an aluminum alloy layer). The material is mainly composed of copper pads 16 . And the tantalum nitride layer is sputtered on the aluminum-containing metal layer (for example, an aluminum layer or an aluminum alloy layer); or the adhesion/barrier layer 24 can be A layer of germanium having a thickness between 0.01 micrometers and 0.7 micrometers (preferably between 0.03 micrometers and 0.7 micrometers) is sputtered onto the protective layer 14 and the metal protective cover 18, wherein the metal protective cover 18 comprises A ruthenium-containing metal layer (for example, a tantalum layer or a tantalum nitride layer) is disposed on the pad 16 mainly composed of copper and an aluminum-containing metal layer (for example, an aluminum layer or an aluminum alloy layer). The metal layer, or the metal protective cover 18 is an aluminum-containing metal layer (for example, an aluminum layer or an aluminum alloy layer) on the substrate 16 mainly comprising copper, and the germanium layer is sputtered on the aluminum-containing metal. a layer (for example, an aluminum layer or an aluminum alloy layer); or, the adhesion/barrier layer 24 may be a thickness of between 0.01 micrometers and 0.7 micrometers (preferably between 0.03 micrometers and 0.7 micrometers). Fire resistant gold The alloy layer is sputtered on the protective layer 14 and the metal protective cover 18, wherein the metal protective cover 18 comprises a ruthenium-containing metal layer (for example, a tantalum layer or a tantalum nitride layer) in the material of the material mainly comprising copper. And an aluminum-containing metal layer (for example, an aluminum layer or an aluminum alloy layer) is disposed on the base metal-containing layer, or the metal protective cover 18 is an aluminum-containing metal layer (for example, an aluminum layer or an aluminum alloy layer). Here, the material mainly comprises copper pads 16, and the refractory metal alloy layer is sputtered on an aluminum-containing metal layer (for example, an aluminum layer or an aluminum alloy layer).

請參閱第6B圖所示,濺鍍厚度介於0.03微米至1微米之間(較佳則是介於0.03微米至0.7微米之間)的一種子層26在黏著/阻障層24上。另,種子層26亦可利用蒸鍍、物理氣相沉積或無電電鍍(electroless plating)等方式形成。由於種子層26可以有利於後續金屬層的形成,因此種子層26的材質會隨後續金屬層的材質而有所變化,如當材質為金(Au)的金屬層電鍍形成在種子層26上時,種子層26的材質係以金為佳;或者,當材質為銅(Cu)的金屬層電鍍形成在種子層26上時,種子層26的材質係以銅為佳;或者,當材質為鈀(palladium,Pd)的金屬層電鍍形成在種子層26上時,種子層26的材質係以鈀為佳。Referring to Figure 6B, a sub-layer 26 having a sputter thickness between 0.03 microns and 1 micron (preferably between 0.03 microns and 0.7 microns) is on the adhesion/barrier layer 24. Alternatively, the seed layer 26 may be formed by evaporation, physical vapor deposition, or electroless plating. Since the seed layer 26 can facilitate the formation of the subsequent metal layer, the material of the seed layer 26 may vary depending on the material of the subsequent metal layer, such as when a metal layer of gold (Au) is electroplated on the seed layer 26. The material of the seed layer 26 is preferably gold; or, when the metal layer of copper (Cu) is plated on the seed layer 26, the material of the seed layer 26 is preferably copper; or, when the material is palladium When the metal layer of (palladium, Pd) is electroplated on the seed layer 26, the material of the seed layer 26 is preferably palladium.

例如,當黏著/阻障層24是以濺鍍方式所形成之厚度介於0.01微米至0.7微米之間(較佳則是介於0.03微米至0.7微米之間)的一鈦層時,種子層26可以是厚度介於0.03微米至1微米之間(較佳則是介於0.03微米至0.7微米之間)的一金層濺鍍在此鈦層上;或是,當黏著/阻障層24是以濺鍍方式所形成之厚度介於0.01微米至0.7微米之間(較佳 則是介於0.03微米至0.7微米之間)的一鈦鎢合金層時,種子層24可以是厚度介於0.03微米至1微米之間(較佳則是介於0.03微米至0.7微米之間)的一金層濺鍍在此鈦鎢合金層上;或是,當黏著/阻障層26是以濺鍍方式所形成之厚度介於0.01微米至0.7微米之間(較佳則是介於0.03微米至0.7微米之間)的一氮化鈦層時,種子層24可以是厚度介於0.03微米至1微米之間(較佳則是介於0.03微米至0.7微米之間)的一金層濺鍍在此氮化鈦層上;或是,當黏著/阻障層24是以濺鍍方式所形成之厚度介於0.01微米至0.7微米之間(較佳則是介於0.03微米至0.7微米之間)的一鉻層時,種子層26可以是厚度介於0.03微米至1微米之間(較佳則是介於0.03微米至0.7微米之間)的一金層濺鍍在此鉻層上;或是,當黏著/阻障層24是以濺鍍方式所形成之厚度介於0.01微米至0.7微米之間(較佳則是介於0.03微米至0.7微米之間)的一氮化鉭層時,種子層26可以是厚度介於0.03微米至1微米之間(較佳則是介於0.03微米至0.7微米之間)的一金層濺鍍在此氮化鉭層上;或是,當黏著/阻障層24是以濺鍍方式所形成之厚度介於0.01微米至0.7微米之間(較佳則是介於0.03微米至0.7微米之間)的一鉭層時,種子層26可以是厚度介於0.03微米至1微米之間(較佳則是介於0.03微米至0.7微米之間)的一金層濺鍍在此鉭層上;或是,當黏著/阻障層24是以濺鍍方式所形成之厚度介於0.01微米至0.7微米之間(較佳則是介於0.03微米至0.7微米之間)的一耐火金屬合金層時,種子層26可以 是厚度介於0.03微米至1微米之間(較佳則是介於0.03微米至0.7微米之間)的一金層濺鍍在此耐火金屬合金層上。For example, when the adhesion/barrier layer 24 is formed by sputtering in a titanium layer having a thickness between 0.01 micrometers and 0.7 micrometers (preferably between 0.03 micrometers and 0.7 micrometers), the seed layer 26 A gold layer having a thickness of between 0.03 micrometers and 1 micrometer (preferably between 0.03 micrometers and 0.7 micrometers) may be sputtered onto the titanium layer; or, when the adhesion/barrier layer 24 is The thickness of the sputtering method is between 0.01 micrometers and 0.7 micrometers (preferably When a titanium-tungsten alloy layer is between 0.03 micrometers and 0.7 micrometers, the seed layer 24 may have a thickness between 0.03 micrometers and 1 micrometer (preferably between 0.03 micrometers and 0.7 micrometers). A gold layer is sputtered onto the titanium tungsten alloy layer; or, when the adhesion/barrier layer 26 is formed by sputtering, the thickness is between 0.01 micrometers and 0.7 micrometers (preferably between 0.03 micrometers and When a layer of titanium nitride is between 0.7 micrometers, the seed layer 24 may be a gold layer having a thickness of between 0.03 micrometers and 1 micrometer (preferably between 0.03 micrometers and 0.7 micrometers). On the titanium nitride layer; or, when the adhesion/barrier layer 24 is formed by sputtering, the thickness is between 0.01 micrometers and 0.7 micrometers (preferably between 0.03 micrometers and 0.7 micrometers). In the case of a chrome layer, the seed layer 26 may be a gold layer having a thickness of between 0.03 micrometers and 1 micrometer (preferably between 0.03 micrometers and 0.7 micrometers) sputtered onto the chromium layer; or, when adhered The barrier layer 24 is formed by sputtering to a thickness of between 0.01 micrometers and 0.7 micrometers (preferably between 0.03 micrometers and 0.7 micrometers). In the tantalum nitride layer, the seed layer 26 may be a gold layer having a thickness of between 0.03 micrometers and 1 micrometer (preferably between 0.03 micrometers and 0.7 micrometers) sputtered onto the tantalum nitride layer; or That is, when the adhesion/barrier layer 24 is formed by sputtering in a thickness of between 0.01 micrometers and 0.7 micrometers (preferably between 0.03 micrometers and 0.7 micrometers), the seed layer 26 A gold layer having a thickness of between 0.03 micrometers and 1 micrometer (preferably between 0.03 micrometers and 0.7 micrometers) may be sputtered onto the germanium layer; or, when the adhesion/barrier layer 24 is When the sputtering method forms a refractory metal alloy layer having a thickness of between 0.01 micrometers and 0.7 micrometers (preferably between 0.03 micrometers and 0.7 micrometers), the seed layer 26 can A gold layer having a thickness of between 0.03 micrometers and 1 micrometer (preferably between 0.03 micrometers and 0.7 micrometers) is sputtered onto the refractory metal alloy layer.

例如,當黏著/阻障層24是以濺鍍方式所形成之厚度介於0.01微米至0.7微米之間(較佳則是介於0.03微米至0.7微米之間)的一鈦層時,種子層26可以是厚度介於0.03微米至1微米之間(較佳則是介於0.03微米至0.7微米之間)的一銅層濺鍍在此鈦層上;或是,當黏著/阻障層24是以濺鍍方式所形成之厚度介於0.01微米至0.7微米之間(較佳則是介於0.03微米至0.7微米之間)的一鈦鎢合金層時,種子層24可以是厚度介於0.03微米至1微米之間(較佳則是介於0.03微米至0.7微米之間)的一銅層濺鍍在此鈦鎢合金層上;或是,當黏著/阻障層26是以濺鍍方式所形成之厚度介於0.01微米至0.7微米之間(較佳則是介於0.03微米至0.7微米之間)的一氮化鈦層時,種子層24可以是厚度介於0.03微米至1微米之間(較佳則是介於0.03微米至0.7微米之間)的一銅層濺鍍在此氮化鈦層上;或是,當黏著/阻障層24是以濺鍍方式所形成之厚度介於0.01微米至0.7微米之間(較佳則是介於0.03微米至0.7微米之間)的一鉻層時,種子層26可以是厚度介於0.03微米至1微米之間(較佳則是介於0.03微米至0.7微米之間)的一銅層濺鍍在此鉻層上;或是,當黏著/阻障層24是以濺鍍方式所形成之厚度介於0.01微米至0.7微米之間(較佳則是介於0.03微米至0.7微米之間)的一氮化鉭層時,種子層26可以是厚度介於0.03微米至1微米之間(較佳則是介於0.03微米至0.7 微米之間)的一銅層濺鍍在此氮化鉭層上;或是,當黏著/阻障層24是以濺鍍方式所形成之厚度介於0.01微米至0.7微米之間(較佳則是介於0.03微米至0.7微米之間)的一鉭層時,種子層26可以是厚度介於0.03微米至1微米之間(較佳則是介於0.03微米至0.7微米之間)的一銅層濺鍍在此鉭層上;或是,當黏著/阻障層24是以濺鍍方式所形成之厚度介於0.01微米至0.7微米之間(較佳則是介於0.03微米至0.7微米之間)的一耐火金屬合金層時,種子層26可以是厚度介於0.03微米至1微米之間(較佳則是介於0.03微米至0.7微米之間)的一銅層濺鍍在此耐火金屬合金層上。For example, when the adhesion/barrier layer 24 is formed by sputtering in a titanium layer having a thickness between 0.01 micrometers and 0.7 micrometers (preferably between 0.03 micrometers and 0.7 micrometers), the seed layer 26 A copper layer having a thickness of between 0.03 micrometers and 1 micrometer (preferably between 0.03 micrometers and 0.7 micrometers) may be sputtered onto the titanium layer; or, when the adhesion/barrier layer 24 is When the sputtering method forms a titanium-tungsten alloy layer having a thickness of between 0.01 micrometers and 0.7 micrometers (preferably between 0.03 micrometers and 0.7 micrometers), the seed layer 24 may have a thickness of 0.03 micrometers to 1 A copper layer between the micrometers (preferably between 0.03 micrometers and 0.7 micrometers) is sputtered onto the titanium-tungsten alloy layer; or, when the adhesion/barrier layer 26 is formed by sputtering When a titanium nitride layer is between 0.01 micrometers and 0.7 micrometers (preferably between 0.03 micrometers and 0.7 micrometers), the seed layer 24 may have a thickness between 0.03 micrometers and 1 micrometer (preferably a copper layer between 0.03 microns and 0.7 microns is sputtered onto the titanium nitride layer; or, when the adhesion/barrier layer 24 is sputtered When a chromium layer having a thickness of between 0.01 micrometers and 0.7 micrometers (preferably between 0.03 micrometers and 0.7 micrometers) is formed, the seed layer 26 may have a thickness of between 0.03 micrometers and 1 micrometer (compared to a copper layer of between 0.03 micrometers and 0.7 micrometers is sputtered onto the chromium layer; or, when the adhesion/barrier layer 24 is sputtered, the thickness is between 0.01 micrometers and 0.7 micrometers. The seed layer 26 may have a thickness between 0.03 microns and 1 micron (preferably between 0.03 microns and 0.7) between the layers (preferably between 0.03 microns and 0.7 microns). A copper layer between the micrometers is sputtered on the tantalum nitride layer; or, when the adhesion/barrier layer 24 is formed by sputtering, the thickness is between 0.01 micrometers and 0.7 micrometers (preferably When a layer of between 0.03 microns and 0.7 microns is used, the seed layer 26 may be a copper layer having a thickness of between 0.03 microns and 1 micron (preferably between 0.03 microns and 0.7 microns). Plating on the ruthenium layer; or, when the adhesion/barrier layer 24 is formed by sputtering, the thickness is between 0.01 micrometers and 0.7 micrometers (preferably between 0.03 micrometers and 0.7 micrometers). In the case of a refractory metal alloy layer, the seed layer 26 may be a copper layer having a thickness of between 0.03 microns and 1 micron (preferably between 0.03 microns and 0.7 microns) sputtered onto the refractory metal alloy layer.

例如,當黏著/阻障層24是以濺鍍方式所形成之厚度介於0.01微米至0.7微米之間(較佳則是介於0.03微米至0.7微米之間)的一鈦層時,種子層26可以是厚度介於0.03微米至1微米之間(較佳則是介於0.03微米至0.7微米之間)的一鈀層濺鍍在此鈦層上;或是,當黏著/阻障層24是以濺鍍方式所形成之厚度介於0.01微米至0.7微米之間(較佳則是介於0.03微米至0.7微米之間)的一鈦鎢合金層時,種子層24可以是厚度介於0.03微米至1微米之間(較佳則是介於0.03微米至0.7微米之間)的一鈀層濺鍍在此鈦鎢合金層上;或是,當黏著/阻障層26是以濺鍍方式所形成之厚度介於0.01微米至0.7微米之間(較佳則是介於0.03微米至0.7微米之間)的一氮化鈦層時,種子層24可以是厚度介於0.03微米至1微米之間(較佳則是介於0.03微米至0.7微米之間)的一鈀層濺鍍在此氮化鈦層上;或是,當黏著/ 阻障層24是以濺鍍方式所形成之厚度介於0.01微米至0.7微米之間(較佳則是介於0.03微米至0.7微米之間)的一鉻層時,種子層26可以是厚度介於0.03微米至1微米之間(較佳則是介於0.03微米至0.7微米之間)的一鈀層濺鍍在此鉻層上;或是,當黏著/阻障層24是以濺鍍方式所形成之厚度介於0.01微米至0.7微米之間(較佳則是介於0.03微米至0.7微米之間)的一氮化鉭層時,種子層26可以是厚度介於0.03微米至1微米之間(較佳則是介於0.03微米至0.7微米之間)的一鈀層濺鍍在此氮化鉭層上;或是,當黏著/阻障層24是以濺鍍方式所形成之厚度介於0.01微米至0.7微米之間(較佳則是介於0.03微米至0.7微米之間)的一鉭層時,種子層26可以是厚度介於0.03微米至1微米之間(較佳則是介於0.03微米至0.7微米之間)的一鈀層濺鍍在此鉭層上;或是,當黏著/阻障層24是以濺鍍方式所形成之厚度介於0.01微米至0.7微米之間(較佳則是介於0.03微米至0.7微米之間)的一耐火金屬合金層時,種子層26可以是厚度介於0.03微米至1微米之間(較佳則是介於0.03微米至0.7微米之間)的一鈀層濺鍍在此耐火金屬合金層上。For example, when the adhesion/barrier layer 24 is formed by sputtering in a titanium layer having a thickness between 0.01 micrometers and 0.7 micrometers (preferably between 0.03 micrometers and 0.7 micrometers), the seed layer 26 A palladium layer having a thickness of between 0.03 micrometers and 1 micrometer (preferably between 0.03 micrometers and 0.7 micrometers) may be sputtered onto the titanium layer; or, when the adhesion/barrier layer 24 is When the sputtering method forms a titanium-tungsten alloy layer having a thickness of between 0.01 micrometers and 0.7 micrometers (preferably between 0.03 micrometers and 0.7 micrometers), the seed layer 24 may have a thickness of 0.03 micrometers to 1 A palladium layer between the micrometers (preferably between 0.03 micrometers and 0.7 micrometers) is sputtered onto the titanium-tungsten alloy layer; or, when the adhesion/barrier layer 26 is formed by sputtering When a titanium nitride layer is between 0.01 micrometers and 0.7 micrometers (preferably between 0.03 micrometers and 0.7 micrometers), the seed layer 24 may have a thickness between 0.03 micrometers and 1 micrometer (preferably a palladium layer between 0.03 microns and 0.7 microns is sputtered onto the titanium nitride layer; or, when adhered/ When the barrier layer 24 is formed by sputtering, a chromium layer having a thickness of between 0.01 micrometers and 0.7 micrometers (preferably between 0.03 micrometers and 0.7 micrometers), the seed layer 26 may have a thickness between A palladium layer between 0.03 micrometers and 1 micrometer (preferably between 0.03 micrometers and 0.7 micrometers) is sputtered onto the chromium layer; or, when the adhesion/barrier layer 24 is formed by sputtering When the thickness is between 0.01 micrometers and 0.7 micrometers (preferably between 0.03 micrometers and 0.7 micrometers) of the tantalum nitride layer, the seed layer 26 may have a thickness of between 0.03 micrometers and 1 micrometer (compared to a palladium layer which is preferably between 0.03 micrometers and 0.7 micrometers is sputtered on the tantalum nitride layer; or, when the adhesion/barrier layer 24 is formed by sputtering, the thickness is between 0.01 micrometers and When a layer of between 0.7 microns (preferably between 0.03 microns and 0.7 microns) is used, the seed layer 26 may have a thickness between 0.03 microns and 1 micron (preferably between 0.03 microns and 0.7 microns). a palladium layer is sputtered onto the ruthenium layer; or, when the adhesion/barrier layer 24 is sputtered, the thickness is between 0.01 microns When a refractory metal alloy layer is between 0.7 microns (preferably between 0.03 microns and 0.7 microns), the seed layer 26 may have a thickness between 0.03 microns and 1 micron (preferably between 0.03 microns and A palladium layer between 0.7 microns is sputtered onto this refractory metal alloy layer.

請參閱第6C圖所示,旋塗(spin-on coating)厚度介於1微米至25微米之間的一光阻層28在種子層26上,其中光阻層28的較佳厚度係介於3微米至10微米之間,且光阻層28比如是一正型(positive-type)光阻層。接著,請參閱第6D圖所示,透過曝光(exposure)與顯影(development)等製程圖案化光阻層28,以形成一光阻層開口28a在光阻 層28內並暴露出位在金屬保護蓋18上方的種子層26,其中在圖案化光阻層28的過程中比如是利用一倍(1X)之曝光機(stepper)或是一倍(1X)之對準曝光機(contact aligner)進行曝光。此外,在顯影後可先利用電漿(例如含有氧離子之電漿或是含有氟離子濃度小於200PPM與氧離子之電漿)清洗光阻層開口28a所暴露出之種子層26,藉以去除種子層26上表面之光阻殘留物或其它異物。Referring to FIG. 6C, a photoresist layer 28 having a spin-on coating thickness between 1 micrometer and 25 micrometers is disposed on the seed layer 26, wherein the preferred thickness of the photoresist layer 28 is between The photoresist layer 28 is, for example, between a micron and a 10 micron, and the photoresist layer 28 is, for example, a positive-type photoresist layer. Next, referring to FIG. 6D, the photoresist layer 28 is patterned by an exposure and development process to form a photoresist layer opening 28a at the photoresist. The seed layer 26 is positioned within the layer 28 and over the metal protective cover 18, wherein in the process of patterning the photoresist layer 28, for example, a one-time (1X) stepper or a double (1X) is utilized. The exposure is performed by a contact aligner. In addition, after development, the seed layer 26 exposed by the photoresist layer opening 28a may be cleaned by using a plasma (for example, a plasma containing oxygen ions or a plasma containing a fluoride ion concentration of less than 200 PPM and oxygen ions) to remove the seed. A photoresist residue or other foreign matter on the upper surface of layer 26.

請參閱第6E圖所示,形成厚度介於1微米至20微米之間的一金屬層30在光阻層開口28a所暴露出之種子層26上,其中此金屬層30的較佳厚度係介於3微米至5微米之間,且金屬層30的材質包括金、銅、鎳或鈀。Referring to FIG. 6E, a metal layer 30 having a thickness between 1 micrometer and 20 micrometers is formed on the seed layer 26 exposed by the photoresist layer opening 28a, wherein the preferred thickness of the metal layer 30 is The material is between 3 microns and 5 microns, and the material of the metal layer 30 comprises gold, copper, nickel or palladium.

例如,金屬層30可以是厚度介於1微米至20微米之間(較佳厚度則是介於3微米至5微米之間或是介於1微米至4微米之間)的一金層電鍍在光阻層開口28a所暴露出之材質為金的種子層26上;或者,金屬層30可以是厚度介於1微米至20微米之間(較佳厚度則是介於3微米至5微米之間或是介於1微米至4微米之間)的一鈀層電鍍在光阻層開口28a所暴露出之材質為鈀的種子層26上;或者,金屬層30可以是厚度介於1微米至10微米之間的一銅層電鍍在光阻層開口28a所暴露出之材質為銅的種子層26上、厚度介於1微米至5微米之間的一鎳層電鍍在此銅層上以及厚度介於1微米至5微米之間的一金層電鍍在此鎳層上,其中銅層、鎳層與金層三者的總厚度係介於1微米至20微米之間,而較佳厚度則是介於3微米至5微米之間; 或者,金屬層30可以是厚度介於1微米至13微米之間的一銅層電鍍在光阻層開口28a所暴露出之材質為銅的種子層26上、厚度介於1微米至5微米之間的一鎳層電鍍在此銅層上以及厚度介於0.05微米至2微米之間的一金層無電電鍍在此鎳層上,其中銅層、鎳層與金層三者的總厚度係介於1微米至20微米之間,而較佳厚度則是介於3微米至5微米之間;或者,金屬層30可以是厚度介於1微米至10微米之間的一銅層電鍍在光阻層開口28a所暴露出之材質為銅的種子層26上、厚度介於1微米至5微米之間的一鎳層電鍍在此銅層上以及厚度介於1微米至5微米之間的一鈀層電鍍在此鎳層上,其中銅層、鎳層與鈀層三者的總厚度係介於1微米至20微米之間,而較佳厚度則是介於3微米至5微米之間;或者,金屬層30可以是厚度介於1微米至13微米之間的一銅層電鍍在光阻層開口28a所暴露出之材質為銅的種子層26上、厚度介於1微米至5微米之間的一鎳層電鍍在此銅層上以及厚度介於0.05微米至2微米之間的一鈀層無電電鍍在此鎳層上,其中銅層、鎳層與鈀層三者的總厚度係介於1微米至20微米之間,而較佳厚度則是介於3微米至5微米之間。For example, the metal layer 30 may be a gold layer plating having a thickness between 1 micrometer and 20 micrometers (preferably a thickness of between 3 micrometers to 5 micrometers or between 1 micrometer and 4 micrometers). The photoresist layer opening 28a is exposed on the gold seed layer 26; alternatively, the metal layer 30 may have a thickness between 1 micrometer and 20 micrometers (preferably, the thickness is between 3 micrometers and 5 micrometers). Or a palladium layer between 1 micrometer and 4 micrometers is plated on the seed layer 26 of palladium exposed by the photoresist layer opening 28a; or the metal layer 30 may have a thickness of 1 micrometer to 10 A copper layer between the micrometers is plated on the copper seed layer 26 exposed by the photoresist layer opening 28a, and a nickel layer having a thickness between 1 micrometer and 5 micrometers is plated on the copper layer and the thickness is A gold layer between 1 micrometer and 5 micrometers is electroplated on the nickel layer, wherein the total thickness of the copper layer, the nickel layer and the gold layer is between 1 micrometer and 20 micrometers, and the preferred thickness is Between 3 microns and 5 microns; Alternatively, the metal layer 30 may be a copper layer having a thickness between 1 micrometer and 13 micrometers plated on the copper seed layer 26 exposed by the photoresist layer opening 28a and having a thickness between 1 micrometer and 5 micrometers. A nickel layer is electroplated on the copper layer and a gold layer having a thickness of between 0.05 micrometers and 2 micrometers is electrolessly plated on the nickel layer, wherein the total thickness of the copper layer, the nickel layer and the gold layer is Between 1 micrometer and 20 micrometers, and a preferred thickness is between 3 micrometers and 5 micrometers; or, the metal layer 30 may be a copper layer having a thickness between 1 micrometer and 10 micrometers. A nickel layer having a thickness of between 1 micrometer and 5 micrometers on the copper seed layer 26 exposed by the layer opening 28a is electroplated on the copper layer and a palladium having a thickness of between 1 micrometer and 5 micrometers. Layer plating on the nickel layer, wherein the total thickness of the copper layer, the nickel layer and the palladium layer is between 1 micrometer and 20 micrometers, and the preferred thickness is between 3 micrometers and 5 micrometers; or The metal layer 30 may be a copper layer having a thickness between 1 micrometer and 13 micrometers. The material exposed by the photoresist layer opening 28a is exposed. A nickel layer on the copper seed layer 26 having a thickness between 1 micrometer and 5 micrometers is electrolessly plated on the copper layer and a palladium layer having a thickness between 0.05 micrometers and 2 micrometers is electrolessly plated on the nickel layer. The total thickness of the copper layer, the nickel layer and the palladium layer is between 1 micrometer and 20 micrometers, and the preferred thickness is between 3 micrometers and 5 micrometers.

請參閱第6F圖所示,在形成金屬層30之後,接著去除光阻層28,而去除方式比如是利用含有氨基化合物(amide)之有機溶劑去除光阻層28。此外,在去除光阻層28之後,可以先利用電漿(例如含有氧離子之電漿或是含有氟離子濃度小於200PPM與氧離子之電漿)清洗金屬層 30與種子層26,藉以去除金屬層30上表面與種子層26上表面之光阻殘留物。Referring to FIG. 6F, after the metal layer 30 is formed, the photoresist layer 28 is subsequently removed, for example, by removing the photoresist layer 28 using an organic solvent containing an amide. In addition, after removing the photoresist layer 28, the metal layer may be cleaned first by using a plasma (for example, a plasma containing oxygen ions or a plasma containing a fluoride ion concentration of less than 200 PPM and oxygen ions). 30 and seed layer 26, whereby the photoresist residue on the upper surface of the metal layer 30 and the upper surface of the seed layer 26 is removed.

繼續請參閱第6G圖所示,依序去除未在金屬層30下方的種子層26與黏著/阻障層24。其中,去除未在金屬層30下方的種子層26與黏著/阻障層24之方式比如是以蝕刻方式去除,而蝕刻方式又可分為乾蝕刻與濕蝕刻兩種方式,另乾蝕刻包括化學電漿蝕刻、濺擊蝕刻與化學氣體蝕刻。例如在濕蝕刻方面,當黏著/阻障層24為鈦鎢合金時,可使用含有雙氧水之溶液蝕刻去除,而當黏著/阻障層24為鈦時,可使用含氰氟酸的溶液蝕刻去除,另當種子層26為金時,可利用含有碘之蝕刻液(例如含有碘化鉀之蝕刻液)蝕刻去除,而當種子層26為銅時,可利用含有氫氧化銨(NH4 OH)之蝕刻液蝕刻去除;在乾蝕刻方面,當黏著/阻障層24為鈦或鈦鎢合金時,可使用含氯的電漿蝕刻去除或是利用反應性離子蝕刻(RIE)製程蝕刻去除,另當種子層26為金時,可使用離子研磨(ion milling)製程蝕刻去除或是利用氬氣濺擊蝕刻(Ar sputtering etching)製程蝕刻去除。Continuing to refer to FIG. 6G, the seed layer 26 and the adhesion/barrier layer 24 that are not under the metal layer 30 are sequentially removed. The manner of removing the seed layer 26 and the adhesion/barrier layer 24 not under the metal layer 30 is, for example, etching, and the etching method can be further divided into dry etching and wet etching, and dry etching includes chemistry. Plasma etching, splash etching and chemical gas etching. For example, in the wet etching, when the adhesion/barrier layer 24 is a titanium-tungsten alloy, it can be removed by etching using a solution containing hydrogen peroxide, and when the adhesion/barrier layer 24 is titanium, it can be removed by using a solution containing a cyanofluoric acid. When the seed layer 26 is gold, it can be removed by etching using an iodine-containing etching solution (for example, an etching solution containing potassium iodide), and when the seed layer 26 is copper, etching using ammonium hydroxide (NH 4 OH) can be utilized. Liquid etching removal; in dry etching, when the adhesion/barrier layer 24 is titanium or titanium tungsten alloy, it can be removed by plasma etching using chlorine or by reactive ion etching (RIE) process etching, and seed When layer 26 is gold, it can be removed by ion milling or by argon etching.

因此,本發明可形成一打線接墊22在一金屬保護蓋18上,且打線接墊22是由一黏著/阻障層24、位在黏著/阻障層24上的一種子層26與位在種子層26上的一金屬層30所構成。又,打線接墊22的材質包括鈦、鈦鎢合金、氮化鈦、鉻、氮化鉭、金、銅、鎳或鈀等。因此,透過上述形成打線接墊22的方式,本發明之打線接墊22可以是下列所述之形式。Therefore, the present invention can form a wire bonding pad 22 on a metal protective cover 18, and the wire bonding pad 22 is formed by an adhesive/barrier layer 24, a sub-layer 26 on the adhesion/barrier layer 24. A metal layer 30 is formed on the seed layer 26. Moreover, the material of the wire bonding pad 22 includes titanium, titanium tungsten alloy, titanium nitride, chromium, tantalum nitride, gold, copper, nickel or palladium. Therefore, the wire bonding pad 22 of the present invention may be in the form described below by the above-described manner of forming the wire bonding pads 22.

例如,打線接墊22包括厚度介於0.01微米至0.7微米之間(較佳則是介於0.03微米至0.7微米之間)的一含鈦金屬層(如一鈦層、一氮化鈦層或一鈦鎢合金層)位在金屬保護蓋18上、厚度介於0.03微米至1微米之間(較佳則是介於0.03微米至0.7微米之間)且材質為金的一種子層位在此含鈦金屬層(如一鈦層、一氮化鈦層或一鈦鎢合金層)上以及厚度介於1微米至20微米之間(較佳厚度則是介於3微米至5微米之間或是介於1微米至4微米之間)的一金層位在此種子層上,其中金屬保護蓋18係位在開口14a所暴露出之材質主要包括銅的接墊16(或稱為銅墊)上;或者,打線接墊22包括厚度介於0.01微米至0.7微米之間(較佳則是介於0.03微米至0.7微米之間)的一含鈦金屬層(如一鈦層、一氮化鈦層或一鈦鎢合金層)位在金屬保護蓋18上、厚度介於0.03微米至1微米之間(較佳則是介於0.03微米至0.7微米之間)且材質為鈀的一種子層位在此含鈦金屬層(如一鈦層、一氮化鈦層或一鈦鎢合金層)上以及厚度介於1微米至20微米之間(較佳厚度則是介於3微米至5微米之間或是介於1微米至4微米之間)的一鈀層位在此種子層上,其中金屬保護蓋18係位在開口14a所暴露出之材質主要包括銅的接墊16(或稱為銅墊)上;或者,打線接墊22包括厚度介於0.01微米至0.7微米之間(較佳則是介於0.03微米至0.7微米之間)的一含鈦金屬層(如一鈦層、一氮化鈦層或一鈦鎢合金層)位在金屬保護蓋18上、厚度介於0.03微米至1微米之間(較佳則是介於0.03微米至0.7 微米之間)且材質為銅的一種子層位在此含鈦金屬層(如一鈦層、一氮化鈦層或一鈦鎢合金層)上、厚度介於1微米至10微米之間的一銅層位在此種子層上、厚度介於1微米至5微米之間的一鎳層位在此銅層上以及厚度介於1微米至5微米之間的一金層位在此鎳層上,且鎳層、銅層與金層三者的總厚度係介於1微米至20微米之間,而較佳厚度則是介於3微米至5微米之間,其中金屬保護蓋18係位在開口14a所暴露出之材質主要包括銅的接墊16(或稱為銅墊)上;或者,打線接墊22包括厚度介於0.01微米至0.7微米之間(較佳則是介於0.03微米至0.7微米之間)的一含鈦金屬層(如一鈦層、一氮化鈦層或一鈦鎢合金層)位在金屬保護蓋18上、厚度介於0.03微米至1微米之間(較佳則是介於0.03微米至0.7微米之間)且材質為銅的一種子層位在此含鈦金屬層(如一鈦層、一氮化鈦層或一鈦鎢合金層)上、厚度介於1微米至10微米之間的一銅層位在此種子層上、厚度介於1微米至5微米之間的一鎳層位在此銅層上以及厚度介於1微米至5微米之間的一鈀層位在此鎳層上,且鎳層、銅層與鈀層三者的總厚度係介於1微米至20微米之間,而較佳厚度則是介於3微米至5微米之間,其中金屬保護蓋18係位在開口14a所暴露出之材質主要包括銅的接墊16(或稱為銅墊)上。For example, the wire bonding pad 22 includes a titanium-containing metal layer (such as a titanium layer, a titanium nitride layer, or a titanium) having a thickness of between 0.01 micrometers and 0.7 micrometers (preferably between 0.03 micrometers and 0.7 micrometers). a tungsten alloy layer) on the metal protective cover 18, having a thickness between 0.03 micrometers and 1 micrometer (preferably between 0.03 micrometers and 0.7 micrometers) and a sub-layer of gold material containing titanium metal a layer (such as a titanium layer, a titanium nitride layer or a titanium tungsten alloy layer) and a thickness between 1 micrometer and 20 micrometers (preferably a thickness of between 3 micrometers to 5 micrometers or between 1) a gold layer between micrometers and 4 micrometers is on the seed layer, wherein the metal protective cover 18 is fastened on the pad 16 (or copper pad) whose material is mainly exposed by the opening 14a; or The wire bonding pad 22 includes a titanium-containing metal layer (such as a titanium layer, a titanium nitride layer or a titanium tungsten) having a thickness of between 0.01 micrometers and 0.7 micrometers (preferably between 0.03 micrometers and 0.7 micrometers). The alloy layer) is on the metal protective cover 18 and has a thickness between 0.03 micrometers and 1 micrometer (preferably between 0.03 micrometers and 0.7 micrometers) and a sub-layer of palladium on the titanium-containing metal layer (such as a titanium layer, a titanium nitride layer or a titanium-tungsten alloy layer) and a thickness of between 1 micrometer and 20 micrometers (the preferred thickness is a palladium layer between 3 micrometers to 5 micrometers or between 1 micrometer and 4 micrometers is on the seed layer, wherein the metal protective cover 18 is located at the opening 14a and the material is mainly composed of copper. a pad 16 (or referred to as a copper pad); or, the wire pad 22 includes a titanium-containing metal layer having a thickness between 0.01 micrometers and 0.7 micrometers (preferably between 0.03 micrometers and 0.7 micrometers) ( For example, a titanium layer, a titanium nitride layer or a titanium tungsten alloy layer is located on the metal protective cover 18 and has a thickness of between 0.03 micrometers and 1 micrometer (preferably between 0.03 micrometers and 0.7 micrometers). a sub-layer between the micrometers and made of copper on the titanium-containing metal layer (such as a titanium layer, a titanium nitride layer or a titanium-tungsten alloy layer) having a thickness between 1 micrometer and 10 micrometers a layer of nickel on the seed layer having a thickness between 1 micrometer and 5 micrometers on the copper layer and a gold layer having a thickness between 1 micrometer and 5 micrometers on the nickel layer And the total thickness of the nickel layer, the copper layer and the gold layer is between 1 micrometer and 20 micrometers, and the preferred thickness is between 3 micrometers and 5 micrometers, wherein the metal protective cover 18 is in the The material exposed by the opening 14a mainly comprises a copper pad 16 (or referred to as a copper pad); or the wire bonding pad 22 comprises a thickness between 0.01 micrometers and 0.7 micrometers (preferably between 0.03 micrometers and 0.7 micrometers). A titanium-containing metal layer (such as a titanium layer, a titanium nitride layer or a titanium-tungsten alloy layer) between the micrometers is located on the metal protective cover 18 and has a thickness of between 0.03 micrometers and 1 micrometer (preferably a sub-layer of copper between 0.03 micrometers and 0.7 micrometers and having a material of copper on the titanium-containing metal layer (such as a titanium layer, a titanium nitride layer or a titanium-tungsten alloy layer) a layer of copper having a thickness between 1 micrometer and 10 micrometers on the seed layer, a nickel layer having a thickness between 1 micrometer and 5 micrometers on the copper layer and a thickness ranging from 1 micrometer to 5 micrometers A palladium layer is on the nickel layer, and the total thickness of the nickel layer, the copper layer and the palladium layer is between 1 micrometer and 20 micrometers, and the preferred thickness is between 3 micrometers and 5 micrometers. Between the micrometers, the metal protective cover 18 is fastened to the pad 16 (or copper pad) whose material is mainly exposed by the opening 14a.

例如,打線接墊22包括厚度介於0.01微米至0.7微米之間(較佳則是介於0.03微米至0.7微米之間)的一鉻層位在金屬保護蓋18上、厚度介於0.03微米至1微米之間(較 佳則是介於0.03微米至0.7微米之間)且材質為金的一種子層位在此鉻層上以及厚度介於1微米至20微米之間(較佳厚度則是介於3微米至5微米之間或是介於1微米至4微米之間)的一金層位在此種子層上,其中金屬保護蓋18係位在開口14a所暴露出之材質主要包括銅的接墊16(或稱為銅墊)上;或者,打線接墊22包括厚度介於0.01微米至0.7微米之間(較佳則是介於0.03微米至0.7微米之間)的一鉻層位在金屬保護蓋18上、厚度介於0.03微米至1微米之間(較佳則是介於0.03微米至0.7微米之間)且材質為鈀的一種子層位在此鉻層上以及厚度介於1微米至20微米之間(較佳厚度則是介於3微米至5微米之間或是介於1微米至4微米之間)的一鈀層位在此種子層上,其中金屬保護蓋18係位在開口14a所暴露出之材質主要包括銅的接墊16(或稱為銅墊)上;或者,打線接墊22包括厚度介於0.01微米至0.7微米之間(較佳則是介於0.03微米至0.7微米之間)的一鉻層位在金屬保護蓋18上、厚度介於0.03微米至1微米之間(較佳則是介於0.03微米至0.7微米之間)且材質為銅的一種子層位在此鉻層上、厚度介於1微米至10微米之間的一銅層位在此種子層上、厚度介於1微米至5微米之間的一鎳層位在此銅層上以及厚度介於1微米至5微米之間的一金層位在此鎳層上,且鎳層、銅層與金層三者的總厚度係介於1微米至20微米之間,而較佳厚度則是介於3微米至5微米之間,其中金屬保護蓋18係位在開口14a所暴露出之材質主要包括銅的接墊16(或稱為銅墊) 上;或者,打線接墊22包括厚度介於0.01微米至0.7微米之間(較佳則是介於0.03微米至0.7微米之間)的一鉻層位在金屬保護蓋18上、厚度介於0.03微米至1微米之間(較佳則是介於0.03微米至0.7微米之間)且材質為銅的一種子層位在此鉻層上、厚度介於1微米至10微米之間的一銅層位在此種子層上、厚度介於1微米至5微米之間的一鎳層位在此銅層上以及厚度介於1微米至5微米之間的一鈀層位在此鎳層上,且鎳層、銅層與鈀層三者的總厚度係介於1微米至20微米之間,而較佳厚度則是介於3微米至5微米之間,其中金屬保護蓋18係位在開口14a所暴露出之材質主要包括銅的接墊16(或稱為銅墊)上。For example, the wire bonding pad 22 includes a chrome layer having a thickness between 0.01 micrometers and 0.7 micrometers (preferably between 0.03 micrometers and 0.7 micrometers) on the metal protective cover 18 and having a thickness of 0.03 micrometers to 1 Between microns (compared Preferably, a sub-layer of gold is between 0.03 micrometers and 0.7 micrometers and is made of gold and has a thickness between 1 micrometer and 20 micrometers (preferably, the thickness is between 3 micrometers and 5 micrometers). A gold layer between or between 1 micrometer and 4 micrometers is on the seed layer, wherein the metal protective cover 18 is fastened to the opening 14a and the material mainly includes the copper pad 16 (or Or a wire pad 22 comprising a chrome layer having a thickness between 0.01 micrometers and 0.7 micrometers (preferably between 0.03 micrometers and 0.7 micrometers) on the metal protective cover 18, thickness a sub-layer of between 0.03 micrometers and 1 micrometer (preferably between 0.03 micrometers and 0.7 micrometers) and having a palladium material on the chromium layer and having a thickness between 1 micrometer and 20 micrometers (compared to a palladium layer having a thickness of between 3 micrometers and 5 micrometers or between 1 micrometer and 4 micrometers is on the seed layer, wherein the metal protective cover 18 is exposed to the opening 14a. The material mainly includes a copper pad 16 (or referred to as a copper pad); or, the wire bonding pad 22 includes a thickness between 0.01 micrometers and 0.7 micrometers ( a chrome layer preferably between 0.03 microns and 0.7 microns is on the metal protective cover 18 and has a thickness between 0.03 microns and 1 micron (preferably between 0.03 microns and 0.7 microns) and a nickel layer having a thickness of between 1 micrometer and 5 micrometers on the seed layer and a copper layer having a thickness of between 1 micrometer and 10 micrometers on the chromium layer. A gold layer on the copper layer and between 1 micrometer and 5 micrometers in thickness is on the nickel layer, and the total thickness of the nickel layer, the copper layer and the gold layer is between 1 micrometer and 20 micrometers. The preferred thickness is between 3 micrometers and 5 micrometers, wherein the metal protective cover 18 is exposed to the opening 14a. The material mainly includes the copper pad 16 (or copper pad). Or; the wire bonding pad 22 includes a chrome layer having a thickness between 0.01 micrometers and 0.7 micrometers (preferably between 0.03 micrometers and 0.7 micrometers) on the metal protective cover 18 and having a thickness of 0.03 micrometers. a sub-layer of between 1 micron (preferably between 0.03 micron and 0.7 micron) and having a copper layer on the chromium layer with a thickness between 1 micrometer and 10 micrometers a layer of nickel on the seed layer having a thickness between 1 micrometer and 5 micrometers on the copper layer and a palladium layer having a thickness between 1 micrometer and 5 micrometers on the nickel layer, and a nickel layer The total thickness of the copper layer and the palladium layer is between 1 micrometer and 20 micrometers, and the preferred thickness is between 3 micrometers and 5 micrometers, wherein the metal protective cover 18 is exposed at the opening 14a. The material is mainly composed of copper pads 16 (or copper pads).

例如,打線接墊22包括厚度介於0.01微米至0.7微米之間(較佳則是介於0.03微米至0.7微米之間)的一含鉭金屬層(例如一鉭層或一氮化鉭層)位在金屬保護蓋18上、厚度介於0.03微米至1微米之間(較佳則是介於0.03微米至0.7微米之間)且材質為金的一種子層位在此含鉭金屬層(例如一鉭層或一氮化鉭層)上以及厚度介於1微米至20微米之間(較佳厚度則是介於3微米至5微米之間或是介於1微米至4微米之間)的一金層位在此種子層上,其中金屬保護蓋18係位在開口14a所暴露出之材質主要包括銅的接墊16(或稱為銅墊)上;或者,打線接墊22包括厚度介於0.01微米至0.7微米之間(較佳則是介於0.03微米至0.7微米之間)的一含鉭金屬層(例如一鉭層或一氮化鉭層)位在金屬保護蓋18上、厚度介於0.03微米至1微米之間(較佳則是 介於0.03微米至0.7微米之間)且材質為鈀的一種子層位在此含鉭金屬層(例如一鉭層或一氮化鉭層)上以及厚度介於1微米至20微米之間(較佳厚度則是介於3微米至5微米之間或是介於1微米至4微米之間)的一鈀層位在此種子層上,其中金屬保護蓋18係位在開口14a所暴露出之材質主要包括銅的接墊16(或稱為銅墊)上;或者,打線接墊22包括厚度介於0.01微米至0.7微米之間(較佳則是介於0.03微米至0.7微米之間)的一含鉭金屬層(例如一鉭層或一氮化鉭層)位在金屬保護蓋18上、厚度介於0.03微米至1微米之間(較佳則是介於0.03微米至0.7微米之間)且材質為銅的一種子層位在此含鉭金屬層(例如一鉭層或一氮化鉭層)上、厚度介於1微米至10微米之間的一銅層位在此種子層上、厚度介於1微米至5微米之間的一鎳層位在此銅層上以及厚度介於1微米至5微米之間的一金層位在此鎳層上,且鎳層、銅層與金層三者的總厚度係介於1微米至20微米之間,而較佳厚度則是介於3微米至5微米之間,其中金屬保護蓋18係位在開口14a所暴露出之材質主要包括銅的接墊16(或稱為銅墊)上;或者,打線接墊22包括厚度介於0.01微米至0.7微米之間(較佳則是介於0.03微米至0.7微米之間)的一含鉭金屬層(例如一鉭層或一氮化鉭層)位在金屬保護蓋18上、厚度介於0.03微米至1微米之間(較佳則是介於0.03微米至0.7微米之間)且材質為銅的一種子層位在此含鉭金屬層(例如一鉭層或一氮化鉭層)上、厚度介於1微米至10微米之間的一銅層位在此種子層 上、厚度介於1微米至5微米之間的一鎳層位在此銅層上以及厚度介於1微米至5微米之間的一鈀層位在此鎳層上,且鎳層、銅層與鈀層三者的總厚度係介於1微米至20微米之間,而較佳厚度則是介於3微米至5微米之間,其中金屬保護蓋18係位在開口14a所暴露出之材質主要包括銅的接墊16(或稱為銅墊)上。For example, the wire bonding pad 22 includes a germanium-containing metal layer (eg, a germanium layer or a tantalum nitride layer) having a thickness of between 0.01 micrometers and 0.7 micrometers (preferably between 0.03 micrometers and 0.7 micrometers). A sub-layer on the metal protective cover 18 having a thickness between 0.03 micrometers and 1 micrometer (preferably between 0.03 micrometers and 0.7 micrometers) and having a gold-based layer (eg, a tantalum layer) a layer or a tantalum nitride layer and a gold having a thickness between 1 micrometer and 20 micrometers (preferably a thickness of between 3 micrometers to 5 micrometers or between 1 micrometer and 4 micrometers) The layer is on the seed layer, wherein the metal protective cover 18 is fastened on the pad 16 (or copper pad) whose material is mainly exposed by the opening 14a; or the wire bonding pad 22 comprises a thickness of 0.01. A germanium-containing metal layer (for example, a germanium layer or a tantalum nitride layer) between micrometers to 0.7 micrometers (preferably between 0.03 micrometers and 0.7 micrometers) is on the metal protective cover 18 and has a thickness of 0.03. Between microns and 1 micron (preferably a sub-layer of between 0.03 micrometers and 0.7 micrometers and having a palladium material on the tantalum-containing metal layer (eg, a tantalum layer or a tantalum nitride layer) and having a thickness between 1 micrometer and 20 micrometers ( A palladium layer having a preferred thickness of between 3 micrometers and 5 micrometers or between 1 micrometer and 4 micrometers is on the seed layer, wherein the metal protective cover 18 is exposed at the opening 14a. The material mainly includes a copper pad 16 (or referred to as a copper pad); or, the wire bonding pad 22 includes a thickness between 0.01 micrometers and 0.7 micrometers (preferably between 0.03 micrometers and 0.7 micrometers). A germanium-containing metal layer (eg, a germanium layer or a tantalum nitride layer) is on the metal protective cover 18 and has a thickness between 0.03 micrometers and 1 micrometer (preferably between 0.03 micrometers and 0.7 micrometers) and a sub-layer of copper material on the ruthenium-containing metal layer (for example, a tantalum layer or a tantalum nitride layer), a copper layer having a thickness between 1 micrometer and 10 micrometers on the seed layer, and a thickness a layer of nickel between 1 micrometer and 5 micrometers on the copper layer and a gold layer having a thickness between 1 micrometer and 5 micrometers on the nickel layer, and nickel The total thickness of the layer, the copper layer and the gold layer is between 1 micrometer and 20 micrometers, and the preferred thickness is between 3 micrometers and 5 micrometers, wherein the metal protective cover 18 is located at the opening 14a. The exposed material mainly comprises a copper pad 16 (or referred to as a copper pad); or, the wire bonding pad 22 comprises a thickness between 0.01 micrometers and 0.7 micrometers (preferably between 0.03 micrometers and 0.7 micrometers). a germanium-containing metal layer (eg, a germanium layer or a tantalum nitride layer) on the metal protective cover 18 having a thickness between 0.03 micrometers and 1 micrometer (preferably between 0.03 micrometers and 0.7 micrometers) And a sub-layer of copper material on the base metal layer (for example, a tantalum layer or a tantalum nitride layer) having a thickness of between 1 micrometer and 10 micrometers in the seed layer a layer of nickel having a thickness between 1 micrometer and 5 micrometers on the copper layer and a palladium layer having a thickness between 1 micrometer and 5 micrometers on the nickel layer, and a nickel layer and a copper layer The total thickness of the palladium layer is between 1 micrometer and 20 micrometers, and the preferred thickness is between 3 micrometers and 5 micrometers, wherein the metal protective cover 18 is located at the opening 14a. It mainly consists of copper pads 16 (or copper pads).

接著,於完成打線接墊22之後,即完成由上述步驟所形成之一半導體晶圓。再來,透過切割半導體晶圓,以形成複數半導體晶片31,如第5A圖所示。Then, after the wire bonding pad 22 is completed, one of the semiconductor wafers formed by the above steps is completed. Further, the semiconductor wafer is diced to form a plurality of semiconductor wafers 31 as shown in FIG. 5A.

請參閱第7A圖與第7B圖所示,本發明可形成一金屬線路32在一聚合物層34上,並透過聚合物層開口34a連接接墊16(例如鋁墊或銅墊),其中聚合物層34係位在保護層14上,且位在聚合物層34內之一開口34a暴露出一開口14a所暴露出之一接墊16(例如鋁墊或銅墊),而開口34a可以是暴露出一接墊16且聚合物層34還覆蓋至部分之接墊34(如第7A圖所示),或是開口34a暴露出一接墊16的全部上表面以及暴露出位在此接墊16周圍之保護層14的上表面(如第7B圖所示)。Referring to Figures 7A and 7B, the present invention can form a metal line 32 on a polymer layer 34 and connect the pads 16 (e.g., aluminum pads or copper pads) through the polymer layer openings 34a. The layer 34 is located on the protective layer 14, and an opening 34a in the polymer layer 34 exposes a pad 16 (for example, an aluminum pad or a copper pad) exposed by an opening 14a, and the opening 34a may be A pad 16 is exposed and the polymer layer 34 also covers a portion of the pad 34 (as shown in FIG. 7A), or the opening 34a exposes all of the upper surface of a pad 16 and is exposed to the pad. The upper surface of the protective layer 14 around 16 (as shown in Fig. 7B).

聚合物層34比如是選自聚醯亞胺(PI)、環氧樹脂(epoxy)、苯基環丁烯(BCB)、聚氨脂、聚對二甲苯類高分子、焊罩材料、彈性體(elastomer)或多孔性介電材料其中之一,且聚合物層34的厚度比如是介於3微米至25微米之間。例如,聚合物層34可以是厚度介於3微米至25微米之間的一聚醯亞胺層在保護層14上,且位在聚醯亞胺層 內之一開口暴露出接墊16(例如鋁墊或銅墊);或者,聚合物層34可以是厚度介於3微米至25微米之間的一環氧樹脂層在保護層14上,且位在環氧樹脂層內之一開口暴露出接墊16(例如鋁墊或銅墊);或者,聚合物層34可以是厚度介於3微米至25微米之間的一苯基環丁烯層在保護層14上,且位在苯基環丁烯層內之一開口暴露出接墊16(例如鋁墊或銅墊)。此外,形成聚合物層34的方式包括有旋塗、壓合或網版印刷等方式。The polymer layer 34 is, for example, selected from the group consisting of polyimine (PI), epoxy, phenylcyclobutene (BCB), polyurethane, polyparaxylene polymer, solder mask material, and elastomer. One of the (elastomer) or porous dielectric materials, and the thickness of the polymer layer 34 is, for example, between 3 microns and 25 microns. For example, the polymer layer 34 may be a polyiminoimine layer having a thickness between 3 microns and 25 microns on the protective layer 14 and in the polyimide layer. One of the openings exposes a pad 16 (eg, an aluminum pad or a copper pad); alternatively, the polymer layer 34 may be an epoxy layer having a thickness between 3 microns and 25 microns on the protective layer 14, and Opening a pad 16 (eg, an aluminum pad or a copper pad) in one of the openings in the epoxy layer; or, the polymer layer 34 may be a layer of phenylcyclobutene having a thickness between 3 microns and 25 microns. An opening in the protective layer 14 and located in the phenylcyclobutene layer exposes a pad 16 (e.g., an aluminum pad or a copper pad). Further, the manner in which the polymer layer 34 is formed includes spin coating, press bonding, or screen printing.

金屬線路32的材質包括金、銅、鎳或鈀,且形成金屬線路32的方式包括濺鍍製程(sputtering process)、電鍍製程(electroplating process)或無電電鍍(electroless plating process)製程等。例如,金屬線路32包括厚度介於0.01微米至0.7微米之間(較佳則是介於0.03微米至0.7微米之間)的一黏著/阻障層濺鍍形成在聚合物層34上與開口34a所暴露出之接墊16(例如鋁墊或銅墊)上、厚度介於0.03微米至1微米之間(較佳則是介於0.03微米至0.7微米之間)且材質為金的一種子層濺鍍形成在黏著/阻障層上以及厚度介於1微米至30微米之間的一金層電鍍形成在種子層上,其中黏著/阻障層的材質包括鈦、鈦鎢合金、氮化鈦、鉻或氮化鉭,而金層的較佳厚度則是介於2微米至20微米之間;或者,金屬線路32包括厚度介於0.01微米至0.7微米之間(較佳則是介於0.03微米至0.7微米之間)的一黏著/阻障層濺鍍形成在聚合物層34上與開口34a所暴露出之接墊16(例如鋁墊或銅墊)上、厚度介於0.03微米至1微米之 間(較佳則是介於0.03微米至0.7微米之間)且材質為銅的一種子層濺鍍形成在黏著/阻障層上、厚度介於1微米至20微米之間的一銅層電鍍形成在種子層上、厚度介於1微米至10微米之間的一鎳層電鍍形成在銅層上以及厚度介於0.01微米至5微米之間的一金層電鍍形成在鎳層上,其中黏著/阻障層的材質包括鈦、鈦鎢合金、氮化鈦、鉻或氮化鉭;或者,金屬線路32包括厚度介於0.01微米至0.7微米之間(較佳則是介於0.03微米至0.7微米之間)的一黏著/阻障層濺鍍形成在聚合物層34上與開口34a所暴露出之接墊16(例如鋁墊或銅墊)上、厚度介於0.03微米至1微米之間(較佳則是介於0.03微米至0.7微米之間)且材質為銅的一種子層濺鍍形成在黏著/阻障層上、厚度介於1微米至20微米之間的一銅層電鍍形成在種子層上、厚度介於1微米至10微米之間的一鎳層電鍍形成在銅層上以及厚度介於0.02微米至2微米之間的一金層無電電鍍形成在鎳層上,其中黏著/阻障層的材質包括鈦、鈦鎢合金、氮化鈦、鉻或氮化鉭;或者,金屬線路32包括厚度介於0.01微米至0.7微米之間(較佳則是介於0.03微米至0.7微米之間)的一黏著/阻障層濺鍍形成在聚合物層34上與開口34a所暴露出之接墊16(例如鋁墊或銅墊)上、厚度介於0.03微米至1微米之間(較佳則是介於0.03微米至0.7微米之間)且材質為銅的一種子層濺鍍形成在黏著/阻障層上、厚度介於1微米至20微米之間的一銅層電鍍形成在種子層上、厚度介於1微米至10微米之間的一鎳層電鍍形成在銅層上以及 厚度介於0.01微米至5微米之間的一鈀層電鍍形成在鎳層上,其中黏著/阻障層的材質包括鈦、鈦鎢合金、氮化鈦、鉻或氮化鉭;或者,金屬線路32包括厚度介於0.01微米至0.7微米之間(較佳則是介於0.03微米至0.7微米之間)的一黏著/阻障層濺鍍形成在聚合物層34上與開口34a所暴露出之接墊16(例如鋁墊或銅墊)上、厚度介於0.03微米至1微米之間(較佳則是介於0.03微米至0.7微米之間)且材質為銅的一種子層濺鍍形成在黏著/阻障層上、厚度介於1微米至20微米之間的一銅層電鍍形成在種子層上、厚度介於1微米至10微米之間的一鎳層電鍍形成在銅層上以及厚度介於0.05微米至2微米之間的一鈀層無電電鍍形成在鎳層上,其中黏著/阻障層的材質包括鈦、鈦鎢合金、氮化鈦、鉻或氮化鉭。另,金屬線路32包括作為接合打線導線的至少一打線接點,例如金屬線路32包括一第一打線接點32a與一第二打線接點32b,從俯視透視圖觀之,第一打線接點32a的位置係位在金屬線路32所連接之接墊16上方,而第二打線接點32b的位置則不同於金屬線路32所連接之接墊16的位置,因此本發明可依需求於後續製程中,選擇接合一打線導線(例如金線)至第一打線接點32a、接合一打線導線(例如金線)至第二打線接點32b或是分別接合一打線導線(例如金線)至第一打線接點32a與第二打線接點32b。The material of the metal line 32 includes gold, copper, nickel or palladium, and the manner of forming the metal line 32 includes a sputtering process, an electroplating process or an electroless plating process. For example, metal line 32 includes an adhesion/barrier layer sputter deposited between 0.01 microns and 0.7 microns (preferably between 0.03 microns and 0.7 microns) formed on polymer layer 34 and opening 34a. Sub-layer sputtering of exposed pads 16 (eg, aluminum pads or copper pads) having a thickness between 0.03 microns and 1 micron (preferably between 0.03 microns and 0.7 microns) and a gold material A gold layer formed on the adhesion/barrier layer and having a thickness of between 1 micrometer and 30 micrometers is formed on the seed layer, wherein the material of the adhesion/barrier layer comprises titanium, titanium tungsten alloy, titanium nitride, chromium Or tantalum nitride, and the preferred thickness of the gold layer is between 2 microns and 20 microns; or the metal line 32 comprises a thickness between 0.01 microns and 0.7 microns (preferably between 0.03 microns and 0.7) An adhesion/barrier layer sputtering between the micrometers is formed on the polymer layer 34 and the pads 16 (e.g., aluminum pads or copper pads) exposed by the openings 34a, having a thickness of between 0.03 micrometers and 1 micrometer. A sub-layer sputtering of between (preferably between 0.03 micrometers and 0.7 micrometers) and having a material of copper is formed by electroplating a copper layer formed on the adhesion/barrier layer and having a thickness of between 1 micrometer and 20 micrometers. A nickel layer plating on the seed layer and having a thickness between 1 micrometer and 10 micrometers is formed on the copper layer and a gold layer having a thickness of between 0.01 micrometers and 5 micrometers is formed on the nickel layer, wherein the adhesion/ The material of the barrier layer comprises titanium, titanium tungsten alloy, titanium nitride, chromium or tantalum nitride; or the metal line 32 comprises a thickness between 0.01 micrometers and 0.7 micrometers (preferably between 0.03 micrometers and 0.7 micrometers). An adhesion/barrier layer sputtering is formed on the polymer layer 34 and the pad 16 (for example, an aluminum pad or a copper pad) exposed by the opening 34a, and has a thickness of between 0.03 micrometers and 1 micrometer (more) Preferably, a sub-layer sputtering of between 0.03 micrometers and 0.7 micrometers and having a material of copper is formed on the adhesion/barrier layer, and a copper layer having a thickness of between 1 micrometer and 20 micrometers is electroplated to form a seed layer. A nickel layer having a thickness between 1 micrometer and 10 micrometers is formed on the copper layer and has a thickness of 0.02 A gold layer of electroless plating between meters and 2 microns is formed on the nickel layer, wherein the material of the adhesion/barrier layer comprises titanium, titanium tungsten alloy, titanium nitride, chromium or tantalum nitride; or the metal line 32 includes thickness An adhesion/barrier layer sputtering between 0.01 microns and 0.7 microns (preferably between 0.03 microns and 0.7 microns) is formed on the polymer layer 34 and the pads 16 exposed by the openings 34a ( For example, an aluminum pad or a copper pad, a sub-layer sputtering of a thickness of between 0.03 micrometers and 1 micrometer (preferably between 0.03 micrometers and 0.7 micrometers) and a material of copper is formed on the adhesion/barrier layer. a copper layer formed on the seed layer and having a thickness between 1 micrometer and 20 micrometers is formed on the seed layer, and a nickel layer having a thickness of between 1 micrometer and 10 micrometers is plated on the copper layer and A palladium layer having a thickness of between 0.01 micrometers and 5 micrometers is electroplated on the nickel layer, wherein the material of the adhesion/barrier layer comprises titanium, titanium tungsten alloy, titanium nitride, chromium or tantalum nitride; or, metal lines 32 includes an adhesion/barrier layer sputter having a thickness between 0.01 microns and 0.7 microns (preferably between 0.03 microns and 0.7 microns) formed on the polymer layer 34 and exposed by the opening 34a. A sub-layer sputtering of a pad 16 (eg, an aluminum pad or a copper pad) having a thickness between 0.03 micrometers and 1 micrometer (preferably between 0.03 micrometers and 0.7 micrometers) and a material of copper is formed on the adhesion/ A copper layer on the barrier layer having a thickness between 1 micrometer and 20 micrometers is plated on the seed layer, and a nickel layer having a thickness of between 1 micrometer and 10 micrometers is plated on the copper layer and the thickness is between A palladium layer between 0.05 micrometers and 2 micrometers is electrolessly plated on the nickel layer, wherein the material of the adhesion/barrier layer comprises titanium, titanium tungsten alloy, titanium nitride, chromium or tantalum nitride. In addition, the metal line 32 includes at least one wire contact as a bonding wire. For example, the metal wire 32 includes a first wire bonding contact 32a and a second wire bonding contact 32b. The first wire bonding contact is viewed from a top perspective view. The position of 32a is above the pad 16 to which the metal line 32 is connected, and the position of the second wire contact 32b is different from the position of the pad 16 to which the metal line 32 is connected. Therefore, the present invention can be used in subsequent processes according to requirements. Selecting to engage a wire conductor (such as a gold wire) to the first wire contact 32a, joining a wire conductor (such as a gold wire) to the second wire contact 32b, or respectively bonding a wire conductor (such as a gold wire) to the first One line contact 32a and second line contact 32b.

接著,於形成金屬線路32之後,透過切割半導體晶圓,以形成複數半導體晶片36。Next, after the metal lines 32 are formed, the semiconductor wafers are diced to form a plurality of semiconductor wafers 36.

請參閱第7C圖與第7D圖所示,本發明在形成金屬線路32之後(如第7A圖與第7B圖所示),亦可形成一聚合物層38在金屬線路32上與聚合物層34上,且位在聚合物層38內之至少一開口38a暴露出金屬線路32,而從俯視透視圖觀之,開口38a所暴露出之金屬線路32的位置可以是不同於金屬線路32所連接之接墊16的位置,其中開口38a所暴露出之金屬線路32係作為接合打線導線的打線接點,例如二開口38a分別暴露出一金屬線路32的一第一打線接點32a與一第二打線接點32b,從俯視透視圖觀之,第一打線接點32a的位置係位在金屬線路32所連接之接墊16上方,而第二打線接點32b的位置則不同於金屬線路32所連接之接墊16的位置,因此本發明可依需求於後續製程中,選擇接合一打線導線(例如金線)至第一打線接點32a、接合一打線導線(例如金線)至第二打線接點32b或是分別接合一打線導線(例如金線)至第一打線接點32a與第二打線接點32b。Referring to FIGS. 7C and 7D, the present invention may also form a polymer layer 38 on the metal line 32 and the polymer layer after forming the metal line 32 (as shown in FIGS. 7A and 7B). At least one opening 38a in the polymer layer 38 exposes the metal line 32, and the position of the metal line 32 exposed by the opening 38a may be different from that of the metal line 32, as viewed from a top perspective view. The position of the pad 16 is such that the metal line 32 exposed by the opening 38a serves as a wire bonding contact for bonding the wire bonding wire. For example, the two openings 38a respectively expose a first wire bonding point 32a and a second wire of a metal wire 32. The wire bonding contact 32b is viewed from a top perspective view, the position of the first wire bonding contact 32a is above the pad 16 to which the metal wire 32 is connected, and the position of the second wire bonding contact 32b is different from the metal wire 32. The position of the connection pad 16 is connected. Therefore, the present invention can selectively engage a wire bonding wire (for example, a gold wire) to the first wire bonding contact 32a and a wire bonding wire (such as a gold wire) to the second bonding wire in a subsequent process. The contacts 32b are respectively connected to a wire conductor ( The gold wire) to the first contact point 32a and the wire contacts the second wire 32b.

聚合物層38比如是選自聚醯亞胺(PI)、環氧樹脂(epoxy)、苯基環丁烯(BCB)、聚氨脂、聚對二甲苯類高分子、焊罩材料、彈性體(elastomer)或多孔性介電材料其中之一,且聚合物層38的厚度比如是介於3微米至25微米之間。例如,聚合物層38可以是厚度介於3微米至25微米之間的一聚醯亞胺層在金屬線路32上,且位在聚醯亞胺層內之一開口暴露出金屬線路32的金層或鈀層;或者,聚合物層38可以是厚度介於3微米至25微米之間的一環氧 樹脂層在金屬線路32上,且位在環氧樹脂層內之一開口暴露出金屬線路32的金層或鈀層;或者,聚合物層38可以是厚度介於3微米至25微米之間的一苯基環丁烯層在金屬線路32上,且位在苯基環丁烯層內之一開口暴露出金屬線路32的金層或鈀層。此外,形成聚合物層38的方式包括有旋塗、壓合或網版印刷等方式。The polymer layer 38 is, for example, selected from the group consisting of polyimine (PI), epoxy, phenylcyclobutene (BCB), polyurethane, polyparaxylene polymer, solder mask material, and elastomer. One of the (elastomer) or porous dielectric materials, and the thickness of the polymer layer 38 is, for example, between 3 microns and 25 microns. For example, the polymer layer 38 can be a layer of polyamidene having a thickness between 3 microns and 25 microns on the metal line 32, and the opening in the polyimine layer exposes the gold of the metal line 32. a layer or a palladium layer; alternatively, the polymer layer 38 may be an epoxy having a thickness between 3 microns and 25 microns The resin layer is on the metal line 32, and one of the openings in the epoxy layer exposes the gold or palladium layer of the metal line 32; alternatively, the polymer layer 38 may be between 3 microns and 25 microns thick. A monophenylcyclobutene layer is on the metal line 32 and one of the openings in the phenylcyclobutene layer exposes a gold or palladium layer of the metal line 32. Further, the manner in which the polymer layer 38 is formed includes spin coating, press bonding, or screen printing.

接著,於形成聚合物層38之後,透過切割半導體晶圓,以形成複數半導體晶片40。Next, after the polymer layer 38 is formed, the semiconductor wafer is diced to form a plurality of semiconductor wafers 40.

另,請參閱第7E圖所示,本發明亦可不形成聚合物層34在保護層14上,即金屬線路32係形成在保護層14上,並透過開口14a連接接墊16(例如鋁墊或銅墊),其中金屬線路32包括作為接合打線導線的至少一打線接點,例如金屬線路32包括一第一打線接點32a與一第二打線接點32b,從俯視透視圖觀之,第一打線接點32a的位置係位在金屬線路32所連接之接墊16上方,而第二打線接點32b的位置則不同於金屬線路32所連接之接墊16的位置,因此本發明可依需求於後續製程中,選擇接合一打線導線(例如金線)至第一打線接點32a、接合一打線導線(例如金線)至第二打線接點32b或是分別接合一打線導線(例如金線)至第一打線接點32a與第二打線接點32b。有關金屬線路32的詳細敘述,請參閱上述第7A圖與第7B圖的說明,在此不再詳加敘述。接著,於形成金屬線路32之後,透過切割半導體晶圓,以形成複數半導體晶片42。In addition, as shown in FIG. 7E, the present invention may also not form the polymer layer 34 on the protective layer 14, that is, the metal line 32 is formed on the protective layer 14, and is connected to the pad 16 through the opening 14a (for example, an aluminum pad or a copper pad), wherein the metal line 32 includes at least one wire contact as a bonding wire, for example, the metal wire 32 includes a first wire bonding contact 32a and a second wire bonding contact 32b, viewed from a top perspective view, first The position of the wire bonding contact 32a is above the pad 16 to which the metal wire 32 is connected, and the position of the second wire bonding contact 32b is different from the position of the pad 16 to which the metal wire 32 is connected. Therefore, the present invention can be adapted to the requirements. In the subsequent process, it is selected to join a wire conductor (such as a gold wire) to the first wire contact 32a, a wire wire (such as a gold wire) to the second wire contact 32b, or a wire wire (such as a gold wire). ) to the first wire bonding contact 32a and the second wire bonding contact 32b. For a detailed description of the metal line 32, please refer to the descriptions of Figures 7A and 7B above, which will not be described in detail herein. Next, after the metal line 32 is formed, the semiconductor wafer is diced to form a plurality of semiconductor wafers 42.

請參閱第7F圖所示,本發明在形成金屬線路32之後 (如第7E圖所示),亦可形成一聚合物層38在金屬線路32上,且位在聚合物層38內之至少一開口38a暴露出金屬線路32,而從俯視透視圖觀之,開口38a所暴露出之金屬線路32的位置可以是不同於金屬線路32所連接之接墊16的位置,其中開口38a所暴露出之金屬線路32係作為接合打線導線的打線接點,例如二開口38a分別暴露出一金屬線路32的一第一打線接點32a與一第二打線接點32b,從俯視透視圖觀之,第一打線接點32a的位置係位在金屬線路32所連接之接墊16上,而第二打線接點32b的位置則不同於金屬線路32所連接之接墊16的位置,因此本發明可依需求於後續製程中,選擇接合一打線導線(例如金線)至第一打線接點32a、接合一打線導線(例如金線)至第二打線接點32b或是分別接合一打線導線(例如金線)至第一打線接點32a與第二打線接點32b。有關聚合物層38的詳細敘述,請參閱上述第7C圖與第7D圖的說明,在此不再詳加敘述。接著,於形成聚合物層38之後,透過切割半導體晶圓,以形成複數半導體晶片44。Referring to FIG. 7F, the present invention is formed after forming the metal line 32. (As shown in FIG. 7E), a polymer layer 38 may also be formed on the metal line 32, and at least one opening 38a in the polymer layer 38 exposes the metal line 32, and from a top perspective view, The position of the metal line 32 exposed by the opening 38a may be different from the position of the pad 16 to which the metal line 32 is connected, wherein the metal line 32 exposed by the opening 38a serves as a wire bonding joint for bonding the wire bonding wire, for example, two openings. 38a exposes a first wire contact 32a and a second wire contact 32b of a metal line 32 respectively. From a top perspective view, the position of the first wire contact 32a is tied to the connection of the metal line 32. The position of the second wire bonding contact 32b is different from the position of the bonding wire 16 to which the metal wire 32 is connected. Therefore, the present invention can selectively connect a wire bonding wire (for example, a gold wire) to a subsequent process according to requirements. The first wire bonding point 32a, the bonding of a wire bonding wire (for example, a gold wire) to the second wire bonding contact 32b or respectively bonding a wire bonding wire (for example, a gold wire) to the first wire bonding contact 32a and the second wire bonding contact 32b. For a detailed description of the polymer layer 38, please refer to the description of the 7C and 7D above, which will not be described in detail herein. Next, after the polymer layer 38 is formed, the semiconductor wafer is diced to form a plurality of semiconductor wafers 44.

請參閱第8A圖所示,本發明可形成一金屬線路32在一聚合物層34上,並透過聚合物層開口34a連接金屬保護蓋18,其中聚合物層34係位在保護層14上,且位在聚合物層34內之一開口34a暴露出金屬保護蓋18的含鋁金屬層(例如一鋁層或一鋁合金層),而金屬線路32係透過開口34a連接含鋁金屬層(例如一鋁層或一鋁合金層),金屬保護蓋18則是位在開口14a所暴露出之主要材質包括銅的接墊 16(即銅墊)上。有關聚合物層34的詳細敘述,請參閱上述第7A圖與第7B圖的說明,在此不再詳加敘述。Referring to FIG. 8A, the present invention can form a metal line 32 on a polymer layer 34 and connect the metal protective cover 18 through the polymer layer opening 34a, wherein the polymer layer 34 is tied to the protective layer 14. And an opening 34a in the polymer layer 34 exposes the aluminum-containing metal layer of the metal protective cover 18 (for example, an aluminum layer or an aluminum alloy layer), and the metal line 32 connects the aluminum-containing metal layer through the opening 34a (for example) An aluminum layer or an aluminum alloy layer), the metal protective cover 18 is a pad which is exposed to the main material exposed by the opening 14a, including copper. 16 (ie copper pad). For a detailed description of the polymer layer 34, please refer to the description of Figures 7A and 7B above, which will not be described in detail herein.

金屬線路32的材質包括金、銅、鎳或鈀,且形成金屬線路32的方式包括濺鍍製程、電鍍製程或無電電鍍製程等。例如,金屬線路32包括厚度介於0.01微米至0.7微米之間(較佳則是介於0.03微米至0.7微米之間)的一黏著/阻障層濺鍍形成在聚合物層34上與開口34a所暴露出之金屬保護蓋18的含鋁金屬層(例如一鋁層或一鋁合金層)上、厚度介於0.03微米至1微米之間(較佳則是介於0.03微米至0.7微米之間)且材質為金的一種子層濺鍍形成在黏著/阻障層上以及厚度介於1微米至30微米之間的一金層電鍍形成在種子層上,其中黏著/阻障層的材質包括鈦、鈦鎢合金、氮化鈦、鉻或氮化鉭,而金層的較佳厚度則是介於2微米至20微米之間;或者,金屬線路32包括厚度介於0.01微米至0.7微米之間(較佳則是介於0.03微米至0.7微米之間)的一黏著/阻障層濺鍍形成在聚合物層34上與開口34a所暴露出之金屬保護蓋18的含鋁金屬層(例如一鋁層或一鋁合金層)上、厚度介於0.03微米至1微米之間(較佳則是介於0.03微米至0.7微米之間)且材質為銅的一種子層濺鍍形成在黏著/阻障層上、厚度介於1微米至20微米之間的一銅層電鍍形成在種子層上、厚度介於1微米至10微米之間的一鎳層電鍍形成在銅層上以及厚度介於0.01微米至5微米之間的一金層電鍍形成在鎳層上,其中黏著/阻障層的材質包括鈦、鈦鎢合金、氮化鈦、鉻或氮化鉭;或者,金 屬線路32包括厚度介於0.01微米至0.7微米之間(較佳則是介於0.03微米至0.7微米之間)的一黏著/阻障層濺鍍形成在聚合物層34上與開口34a所暴露出之金屬保護蓋18的含鋁金屬層(例如一鋁層或一鋁合金層)上、厚度介於0.03微米至1微米之間(較佳則是介於0.03微米至0.7微米之間)且材質為銅的一種子層濺鍍形成在黏著/阻障層上、厚度介於1微米至20微米之間的一銅層電鍍形成在種子層上、厚度介於1微米至10微米之間的一鎳層電鍍形成在銅層上以及厚度介於0.05微米至2微米之間的一金層無電電鍍形成在鎳層上,其中黏著/阻障層的材質包括鈦、鈦鎢合金、氮化鈦、鉻或氮化鉭;或者,金屬線路32包括厚度介於0.01微米至0.7微米之間(較佳則是介於0.03微米至0.7微米之間)的一黏著/阻障層濺鍍形成在聚合物層34上與開口34a所暴露出之金屬保護蓋18的含鋁金屬層(例如一鋁層或一鋁合金層)上、厚度介於0.03微米至1微米之間(較佳則是介於0.03微米至0.7微米之間)且材質為銅的一種子層濺鍍形成在黏著/阻障層上、厚度介於1微米至20微米之間的一銅層電鍍形成在種子層上、厚度介於1微米至10微米之間的一鎳層電鍍形成在銅層上以及厚度介於0.01微米至5微米之間的一鈀層電鍍形成在鎳層上,其中黏著/阻障層的材質包括鈦、鈦鎢合金、氮化鈦、鉻或氮化鉭;或者,金屬線路32包括厚度介於0.01微米至0.7微米之間(較佳則是介於0.03微米至0.7微米之間)的一黏著/阻障層濺鍍形成在聚合物層34上與開口34a所暴露出之金屬保 護蓋18的含鋁金屬層(例如一鋁層或一鋁合金層)上、厚度介於0.03微米至1微米之間(較佳則是介於0.03微米至0.7微米之間)且材質為銅的一種子層濺鍍形成在黏著/阻障層上、厚度介於1微米至20微米之間的一銅層電鍍形成在種子層上、厚度介於1微米至10微米之間的一鎳層電鍍形成在銅層上以及厚度介於0.05微米至2微米之間的一鈀層無電電鍍形成在鎳層上,其中黏著/阻障層的材質包括鈦、鈦鎢合金、氮化鈦、鉻或氮化鉭。另,金屬線路32包括作為接合打線導線的至少一打線接點,例如金屬線路32包括一第一打線接點32a與一第二打線接點32b,從俯視透視圖觀之,第一打線接點32a的位置係位在金屬線路32所連接之金屬保護蓋18上方,而第二打線接點32b的位置則不同於金屬線路32所連接之金屬保護蓋18的位置,因此本發明可依需求於後續製程中,選擇接合一打線導線(例如金線)至第一打線接點32a、接合一打線導線(例如金線)至第二打線接點32b或是分別接合一打線導線(例如金線)至第一打線接點32a與第二打線接點32b。The material of the metal line 32 includes gold, copper, nickel or palladium, and the manner of forming the metal line 32 includes a sputtering process, an electroplating process or an electroless plating process. For example, metal line 32 includes an adhesion/barrier layer sputter deposited between 0.01 microns and 0.7 microns (preferably between 0.03 microns and 0.7 microns) formed on polymer layer 34 and opening 34a. The exposed metal protective layer 18 has an aluminum-containing metal layer (eg, an aluminum layer or an aluminum alloy layer) having a thickness between 0.03 micrometers and 1 micrometer (preferably between 0.03 micrometers and 0.7 micrometers) and A gold layer of gold is deposited on the adhesion/barrier layer and a gold layer having a thickness between 1 micrometer and 30 micrometers is formed on the seed layer, wherein the adhesion/barrier layer material comprises titanium, a titanium tungsten alloy, titanium nitride, chromium or tantalum nitride, and the preferred thickness of the gold layer is between 2 microns and 20 microns; or the metal line 32 comprises a thickness between 0.01 microns and 0.7 microns ( An adhesive/barrier layer, preferably between 0.03 micrometers and 0.7 micrometers, is sputtered to form an aluminum-containing metal layer (eg, an aluminum layer) on the polymer layer 34 and the metal protective cover 18 exposed by the opening 34a. Or an aluminum alloy layer) having a thickness between 0.03 microns and 1 micron (preferably between 0.03 microns) a sub-layer sputtering of between 0.7 micron and copper is formed on the adhesion/barrier layer, and a copper layer having a thickness between 1 micrometer and 20 micrometers is electroplated on the seed layer and has a thickness of 1 A nickel layer plating between micrometers to 10 micrometers is formed on the copper layer and a gold layer having a thickness of between 0.01 micrometers and 5 micrometers is electroplated on the nickel layer, wherein the material of the adhesion/barrier layer comprises titanium and titanium. Tungsten alloy, titanium nitride, chromium or tantalum nitride; or, gold The line 32 includes an adhesion/barrier layer sputter deposited between 0.01 microns and 0.7 microns (preferably between 0.03 microns and 0.7 microns) formed on the polymer layer 34 and exposed by the opening 34a. The metal protective cover 18 has an aluminum-containing metal layer (for example, an aluminum layer or an aluminum alloy layer) having a thickness of between 0.03 μm and 1 μm (preferably between 0.03 μm and 0.7 μm) and a material of A sub-layer of copper is formed by depositing a copper layer formed on the adhesion/barrier layer and having a thickness between 1 micrometer and 20 micrometers to form a nickel layer on the seed layer and having a thickness between 1 micrometer and 10 micrometers. Layer plating is formed on the copper layer and a gold layer having a thickness of between 0.05 micrometers and 2 micrometers is electrolessly plated on the nickel layer, wherein the material of the adhesion/barrier layer comprises titanium, titanium tungsten alloy, titanium nitride, chromium Or tantalum nitride; or the metal line 32 includes an adhesion/barrier layer sputtering formed on the polymer layer 34 having a thickness between 0.01 micrometers and 0.7 micrometers (preferably between 0.03 micrometers and 0.7 micrometers). An aluminum-containing metal layer (eg, an aluminum layer or an aluminum layer) of the metal protective cover 18 exposed to the opening 34a On the alloy layer), a sub-layer sputtering of a thickness of between 0.03 micrometers and 1 micrometer (preferably between 0.03 micrometers and 0.7 micrometers) and a material of copper is formed on the adhesion/barrier layer, and the thickness is A nickel layer plating between 1 micrometer and 20 micrometers is formed on the seed layer, and a nickel layer having a thickness of between 1 micrometer and 10 micrometers is plated on the copper layer and has a thickness of between 0.01 micrometers and 5 micrometers. A palladium layer is electroplated on the nickel layer, wherein the material of the adhesion/barrier layer comprises titanium, titanium tungsten alloy, titanium nitride, chromium or tantalum nitride; or the metal line 32 comprises a thickness of 0.01 micron to 0.7 micron. An adhesion/barrier layer between (preferably between 0.03 and 0.7) is formed on the polymer layer 34 and exposed by the opening 34a. The aluminum-containing metal layer (for example, an aluminum layer or an aluminum alloy layer) of the cover 18 has a thickness of between 0.03 micrometers and 1 micrometer (preferably between 0.03 micrometers and 0.7 micrometers) and is made of copper. A nickel layer plating is formed by depositing a copper layer formed on the adhesion/barrier layer and having a thickness between 1 micrometer and 20 micrometers on the seed layer and having a thickness between 1 micrometer and 10 micrometers. A palladium layer formed on the copper layer and having a thickness of between 0.05 μm and 2 μm is electrolessly plated on the nickel layer, wherein the material of the adhesion/barrier layer comprises titanium, titanium tungsten alloy, titanium nitride, chromium or nitrogen. Phlegm. In addition, the metal line 32 includes at least one wire contact as a bonding wire. For example, the metal wire 32 includes a first wire bonding contact 32a and a second wire bonding contact 32b. The first wire bonding contact is viewed from a top perspective view. The position of 32a is above the metal protection cover 18 to which the metal line 32 is connected, and the position of the second connection line 32b is different from the position of the metal protection cover 18 to which the metal line 32 is connected. Therefore, the present invention can be used according to requirements. In the subsequent process, it is selected to join a wire conductor (such as a gold wire) to the first wire contact 32a, a wire wire (such as a gold wire) to a second wire contact 32b, or a wire wire (such as a gold wire). The first wire bonding contact 32a and the second wire bonding contact 32b.

接著,於形成金屬線路32之後,透過切割半導體晶圓,以形成複數半導體晶片46。Next, after the metal lines 32 are formed, the semiconductor wafers are diced to form a plurality of semiconductor wafers 46.

請參閱第8B圖所示,本發明在形成金屬線路32之後(如第8A圖所示),亦可形成一聚合物層38在金屬線路32上與聚合物層34上,且位在聚合物層38內之至少一開口38a暴露出金屬線路32,而從俯視透視圖觀之,開口38a所暴露出之金屬線路32的位置可以是不同於金屬線路32 所連接之金屬保護蓋18的位置,其中開口38a所暴露出之金屬線路32係作為接合打線導線的打線接點,例如二開口38a分別暴露出金屬線路32的一第一打線接點32a與一第二打線接點32b,從俯視透視圖觀之,第一打線接點32a的位置係位在金屬線路32所連接之金屬保護蓋18上方,而第二打線接點32b的位置則不同於金屬線路32所連接之金屬保護蓋18的位置,因此本發明可依需求於後續製程中,選擇接合一打線導線(例如金線)至第一打線接點32a、接合一打線導線(例如金線)至第二打線接點32b或是分別接合一打線導線(例如金線)至第一打線接點32a與第二打線接點32b。有關聚合物層38的詳細敘述,請參閱上述第7C圖與第7D圖的說明,在此不再詳加敘述。接著,於形成聚合物層38之後,透過切割半導體晶圓,以形成複數半導體晶片48。Referring to FIG. 8B, after forming the metal line 32 (as shown in FIG. 8A), a polymer layer 38 may be formed on the metal line 32 and the polymer layer 34, and in the polymer. At least one opening 38a in layer 38 exposes metal line 32, and from a top perspective view, the location of metal line 32 exposed by opening 38a may be different than metal line 32. The position of the connected metal protection cover 18, wherein the metal line 32 exposed by the opening 38a serves as a wire bonding contact for bonding the wire bonding wire, for example, the two openings 38a respectively expose a first wire bonding point 32a and a metal wire 32. The second wire contact 32b is viewed from a top perspective view. The position of the first wire contact 32a is located above the metal protection cover 18 to which the metal line 32 is connected, and the position of the second wire contact 32b is different from the metal. The position of the metal protection cover 18 connected to the line 32, so the present invention can selectively engage a wire conductor (such as a gold wire) to the first wire bonding point 32a and the bonding wire (such as a gold wire) in a subsequent process. To the second wire contact 32b or a wire bonding wire (for example, a gold wire) to the first wire bonding contact 32a and the second wire bonding contact 32b, respectively. For a detailed description of the polymer layer 38, please refer to the description of the 7C and 7D above, which will not be described in detail herein. Next, after the polymer layer 38 is formed, the semiconductor wafer is diced to form a plurality of semiconductor wafers 48.

請參閱第8C圖所示,本發明亦可不形成聚合物層34在保護層14上,即金屬線路32係形成在保護層14上與金屬保護蓋18的含鋁金屬層(例如一鋁層或一鋁合金層)上,其中金屬線路32包括作為接合打線導線的至少一打線接點,例如金屬線路32包括一第一打線接點32a與一第二打線接點32b,從俯視透視圖觀之,第一打線接點32a的位置係位在金屬線路32所連接之金屬保護蓋18上方,而第二打線接點32b的位置則不同於金屬線路32所連接之金屬保護蓋18的位置,因此本發明可依需求於後續製程中,選擇接合一打線導線(例如金線)至第一打線接點32a、接合一 打線導線(例如金線)至第二打線接點32b或是分別接合一打線導線(例如金線)至第一打線接點32a與第二打線接點32b。有關金屬線路32的詳細敘述,請參閱上述第7A圖與第7B圖的說明,在此不再詳加敘述。接著,於形成金屬線路32之後,透過切割半導體晶圓,以形成複數半導體晶片50。Referring to FIG. 8C, the present invention may also not form the polymer layer 34 on the protective layer 14, that is, the metal line 32 is formed on the protective layer 14 and the aluminum-containing metal layer of the metal protective cover 18 (for example, an aluminum layer or An aluminum alloy layer, wherein the metal line 32 includes at least one wire contact as a bonding wire, for example, the metal wire 32 includes a first wire bonding contact 32a and a second wire bonding contact 32b, which are viewed from a top perspective view. The position of the first wire contact 32a is located above the metal protection cover 18 to which the metal line 32 is connected, and the position of the second wire contact 32b is different from the position of the metal protection cover 18 to which the metal line 32 is connected. According to the invention, in the subsequent process, a wire bonding wire (for example, a gold wire) is selectively joined to the first wire bonding contact 32a, and the bonding is performed. A wire bonding wire (for example, a gold wire) is connected to the second wire bonding node 32b or a wire bonding wire (for example, a gold wire) to the first wire bonding contact 32a and the second wire bonding contact 32b, respectively. For a detailed description of the metal line 32, please refer to the descriptions of FIGS. 7A and 7B above, and the detailed description thereof will not be repeated here. Next, after the metal lines 32 are formed, the semiconductor wafers are diced to form a plurality of semiconductor wafers 50.

請參閱第8D圖所示,本發明在形成金屬線路32之後(如第8C圖所示),亦可形成一聚合物層38在金屬線路32上,且位在聚合物層38內之至少一開口38a暴露出金屬線路32,而從俯視透視圖觀之,開口38a所暴露出之金屬線路32的位置可以是不同於金屬線路32所連接之金屬保護蓋18的位置,其中開口38a所暴露出之金屬線路32係作為接合打線導線的打線接點,例如二開口38a分別暴露出金屬線路32的一第一打線接點32a與一第二打線接點32b,從俯視透視圖觀之,第一打線接點32a的位置係位在金屬線路32所連接之金屬保護蓋18上方,而第二打線接點32b的位置則不同於金屬線路32所連接之金屬保護蓋18的位置,因此本發明可依需求於後續製程中,選擇接合一打線導線(例如金線)至第一打線接點32a、接合一打線導線(例如金線)至第二打線接點32b或是分別接合一打線導線(例如金線)至第一打線接點32a與第二打線接點32b。有關聚合物層38的詳細敘述,請參閱上述第7C圖與第7D圖的說明,在此不再詳加敘述。接著,於形成聚合物層38之後,透過切割半導體晶圓,以形成複數半導體晶片52。Referring to FIG. 8D, after forming the metal line 32 (as shown in FIG. 8C), a polymer layer 38 may be formed on the metal line 32 and at least one of the polymer layers 38. The opening 38a exposes the metal line 32, and the position of the metal line 32 exposed by the opening 38a may be different from the position of the metal protective cover 18 to which the metal line 32 is attached, as viewed from a top perspective view, wherein the opening 38a is exposed The metal line 32 is used as a wire bonding joint for bonding the wire bonding wires. For example, the two openings 38a respectively expose a first wire bonding node 32a and a second wire bonding node 32b of the metal wire 32, which are viewed from a top perspective view. The position of the wire bonding contact 32a is located above the metal protection cover 18 to which the metal wire 32 is connected, and the position of the second wire bonding contact 32b is different from the position of the metal protection cover 18 to which the metal wire 32 is connected, so the present invention can According to the requirements in the subsequent process, it is selected to join a wire conductor (such as gold wire) to the first wire contact 32a, join a wire wire (such as gold wire) to the second wire contact 32b or respectively engage a wire wire (for example Gold line) to the first One line contact 32a and second line contact 32b. For a detailed description of the polymer layer 38, please refer to the description of the 7C and 7D above, which will not be described in detail herein. Next, after the polymer layer 38 is formed, the semiconductor wafer is diced to form a plurality of semiconductor wafers 52.

第一實施例First embodiment

請參閱第9A圖所示,透過一點膠製程(dispensing process),使複數黏著材料54形成於一基板56上;接著,將複數半導體晶片23分別壓合在這些黏著材料54上,並在經過烘烤製程之後使半導體晶片23黏著至基板56,亦即半導體晶片23係透過黏著材料54以半導體基底2黏著至基板56。其中,黏著材料54的材質比如是聚合物材料(例如聚醯亞胺、環氧樹脂或銀膠),且厚度係介於1微米至50微米之間,例如黏著材料54可以是厚度介於1微米至50微米之間的聚醯亞胺,或是厚度介於1微米至50微米之間的環氧樹脂,或是厚度介於1微米至50微米之間的銀膠(silver-filed epoxy)。Referring to FIG. 9A, the plurality of adhesive materials 54 are formed on a substrate 56 through a dispensing process. Then, the plurality of semiconductor wafers 23 are respectively pressed onto the adhesive materials 54 and passed through. After the baking process, the semiconductor wafer 23 is adhered to the substrate 56, that is, the semiconductor wafer 23 is adhered to the substrate 56 by the semiconductor substrate 2 through the adhesive material 54. Wherein, the material of the adhesive material 54 is, for example, a polymer material (for example, polyimide, epoxy or silver glue), and the thickness is between 1 micrometer and 50 micrometers, for example, the adhesive material 54 may have a thickness of 1 Polyimine between microns and 50 microns, or epoxy between 1 and 50 microns thick, or silver-filed epoxy between 1 and 50 microns .

此外,基板56可以是厚度介於200微米至2,000微米之間的一球型柵狀陣列(BGA)基板;或者,基板56可以是厚度介於200微米至2,000微米之間的一含有玻璃纖維與環氧樹脂的基板;或者,基板56可以是厚度介於200微米至2,000微米之間的一玻璃基板;或者,基板56可以是厚度介於200微米至2,000微米之間的一矽基板;或者,基板56可以是厚度介於200微米至2,000微米之間的一陶瓷基板;或者,基板56可以是厚度介於200微米至2,000微米之間的一有機基板;或者,基板56可以是厚度介於200微米至2,000微米之間且材質包括鋁的一金屬基板;或者,基板56可以是厚度介於200微米至2,000微米之間且 材質包括銅的一金屬基板。In addition, the substrate 56 may be a ball grid array (BGA) substrate having a thickness between 200 micrometers and 2,000 micrometers; or the substrate 56 may be a glass fiber containing between 200 micrometers and 2,000 micrometers thick. a substrate of epoxy resin; or, the substrate 56 may be a glass substrate having a thickness between 200 micrometers and 2,000 micrometers; or, the substrate 56 may be a germanium substrate having a thickness between 200 micrometers and 2,000 micrometers; or The substrate 56 may be a ceramic substrate having a thickness between 200 micrometers and 2,000 micrometers; or the substrate 56 may be an organic substrate having a thickness between 200 micrometers and 2,000 micrometers; or the substrate 56 may have a thickness of 200 a metal substrate between micrometers and 2,000 micrometers and comprising aluminum; or the substrate 56 may have a thickness between 200 micrometers and 2,000 micrometers The material includes a metal substrate of copper.

請參閱第9B圖所示,透過一打線製程使一打線導線58的一端球形(ball)接合至一半導體晶片23之一打線接墊22上(例如接合至打線接墊22的金層或鈀層上),而此打線導線58的另一端則楔形(wedge)接合至基板56之一金屬線路的一接點57上,其中打線導線58比如是直徑介於20微米至50微米之間且材質含金的一金屬線(或稱為金線)。因此,半導體晶片23的打線接墊22電性連接基板56的金屬線路。Referring to FIG. 9B, one end of the one-wire wire 58 is ball-bonded to one of the wire pads 22 of a semiconductor wafer 23 through a one-wire process (eg, a gold or palladium layer bonded to the wire bond pad 22). The other end of the wire bonding wire 58 is wedge-bonded to a contact 57 of one of the metal wires of the substrate 56, wherein the wire bonding wire 58 is, for example, between 20 micrometers and 50 micrometers in diameter and contains a material. A metal wire of gold (or gold wire). Therefore, the bonding pads 22 of the semiconductor wafer 23 are electrically connected to the metal lines of the substrate 56.

請參閱第9C圖所示,形成厚度t5介於250微米至1,000微米之間的一聚合物材料60在基板56上並覆蓋半導體晶片23及打線導線58,其中形成聚合物材料60的方式包括有灌膜製程(molding process)或點膠製程(dispensing process)等,而聚合物材料60的材質包括聚醯亞胺(PI)、苯基環丁烯(BCB)或環氧樹脂(expoy resin)。Referring to FIG. 9C, a polymer material 60 having a thickness t5 between 250 micrometers and 1,000 micrometers is formed on the substrate 56 and covers the semiconductor wafer 23 and the wire bonding wires 58. The manner in which the polymer material 60 is formed includes The molding process or the dispensing process, and the like, and the material of the polymer material 60 includes polyimine (PI), phenylcyclobutene (BCB) or epoxy resin.

例如,利用灌膜製程形成厚度t5介於250微米至1,000微米之間的聚醯亞胺在基板56上並覆蓋半導體晶片23及打線導線58;或者,利用灌膜製程形成厚度t5介於250微米至1,000微米之間的苯基環丁烯在基板56上並覆蓋半導體晶片23及打線導線58;或者,利用灌膜製程形成厚度t5介於250微米至1,000微米之間且含有環氧樹脂的聚合物材料在基板56上並覆蓋半導體晶片23及打線導線58。For example, a polyimine having a thickness t5 between 250 micrometers and 1,000 micrometers is formed on the substrate 56 by the filling process and covering the semiconductor wafer 23 and the wire bonding wires 58; or, by using a film filling process, the thickness t5 is formed to be 250 micrometers. Phenylcyclobutene to between 1,000 micrometers on the substrate 56 and covering the semiconductor wafer 23 and the wire bonding wire 58; or, by using a film filling process, a polymerization having an epoxy resin concentration of between 250 micrometers and 1,000 micrometers is formed. The material is on the substrate 56 and covers the semiconductor wafer 23 and the wire bonding wires 58.

例如,利用點膠製程形成厚度t5介於250微米至1,000 微米之間的聚醯亞胺在基板56上並覆蓋半導體晶片23及打線導線58;或者,利用點膠製程形成厚度t5介於250微米至1,000微米之間的苯基環丁烯在基板56上並覆蓋半導體晶片23及打線導線58;或者,利用點膠製程形成厚度t5介於250微米至1,000微米之間且含有環氧樹脂的聚合物材料在基板56上並覆蓋半導體晶片23及打線導線58。For example, using a dispensing process to form a thickness t5 between 250 microns and 1,000 Polyimine between the micrometers on the substrate 56 and covering the semiconductor wafer 23 and the wire bonding wire 58; or, using a dispensing process to form a phenylcyclobutene having a thickness t5 between 250 micrometers and 1,000 micrometers on the substrate 56 And covering the semiconductor wafer 23 and the wire bonding wire 58; or forming a polymer material having a thickness t5 between 250 micrometers and 1,000 micrometers and containing epoxy resin on the substrate 56 and covering the semiconductor wafer 23 and the wire bonding wire 58 by using a dispensing process .

請參閱第9D圖所示,以植球製程(ball planting process)或是網版印刷製程(screen printing process)形成一無鉛銲料(lead-free solder)在基板56的一接點64上,接著在溫度介於200℃至300℃之間(較佳溫度則是介於230℃至260℃之間)的環境中對無鉛銲料進行一迴銲(reflow)製程,以形成直徑d介於0.25釐米至1.2釐米之間的一無鉛錫球(lead-free solder ball)62在基板56的接點64上,其中迴銲製程的時間係介於5秒至90秒之間,較佳則是介於20秒至40秒之間。此外,無鉛錫球62的材質可以是錫鉛合金(tin-lead alloy)、錫銀合金(tin-silver alloy)、錫銀銅合金(tin-silver-copper alloy)或無鉛合金(lead-free alloy)。另,因無鉛錫球62接合基板56之一金屬線路的接點64而連接接點57,故無鉛錫球62電性連接打線導線58。Referring to FIG. 9D, a lead-free solder is formed on a contact 64 of the substrate 56 by a ball planting process or a screen printing process, and then A reflow process for lead-free solder in an environment with a temperature between 200 ° C and 300 ° C (preferably between 230 ° C and 260 ° C) to form a diameter d of between 0.25 cm and A lead-free solder ball 62 between 1.2 cm is on the contact 64 of the substrate 56, wherein the reflow process is between 5 seconds and 90 seconds, preferably 20 seconds. Between 40 seconds. In addition, the material of the lead-free solder ball 62 may be a tin-lead alloy, a tin-silver alloy, a tin-silver-copper alloy or a lead-free alloy. ). Further, since the lead-free solder ball 62 is bonded to the contact 64 of the metal line of one of the substrates 56, the contact-free solder ball 62 is electrically connected to the wire bonding wire 58.

請參閱第9E圖所示,於形成無鉛錫球62之後,切割(例如機械切割)基板56與聚合物材料60,以形成複數個晶片封裝結構66。在第9E圖中,基板56包括有一第一表面與一第二表面,且第一表面與第二表面為相對的兩表面, 其中黏著材料54與聚合物材料60係位在第一表面上(半導體晶片23係透過黏著材料54黏著在第一表面),而無鉛錫球62則位在第二表面上。Referring to FIG. 9E, after forming the lead-free solder balls 62, the substrate 56 and the polymer material 60 are cut (eg, mechanically cut) to form a plurality of wafer package structures 66. In FIG. 9E, the substrate 56 includes a first surface and a second surface, and the first surface and the second surface are opposite surfaces. The adhesive material 54 and the polymer material 60 are tied on the first surface (the semiconductor wafer 23 is adhered to the first surface through the adhesive material 54), and the lead-free solder balls 62 are located on the second surface.

請分別參閱第10A圖至第10L圖所示,透過上述第9A圖至第9D圖所述之步驟,本發明亦可使用半導體晶片31、36、40、42、44、46、48、50與52來取代第9圖系列中的半導體晶片23,並於形成無鉛錫球62之後,切割(例如機械切割)基板56與聚合物材料60,以分別形成晶片封裝結構68、70、72、74、76、78、80、82與84,詳細內容請參閱第9A圖至第9E圖的說明,在此不再詳加敘述。Referring to FIGS. 10A to 10L, respectively, the present invention can also use semiconductor wafers 31, 36, 40, 42, 44, 46, 48, 50 through the steps described in FIGS. 9A to 9D. Substituting the semiconductor wafer 23 in the series of FIG. 9 and, after forming the lead-free solder balls 62, cutting (eg, mechanically cutting) the substrate 56 and the polymer material 60 to form the chip package structures 68, 70, 72, 74, respectively. 76, 78, 80, 82, and 84. For details, please refer to the descriptions of FIGS. 9A to 9E, which will not be described in detail herein.

另,在第10C圖至第10L圖中,打線導線58接合金屬線路32的位置從俯視透視圖觀之,此位置可以是不同於金屬線路32所連接之接墊16的位置,或者是不同於金屬線路32所連接之金屬保護蓋18的位置。因此,在第10C圖至第10L圖中,金屬線路32可以是包括一第一打線接點32a與一第二打線接點32b,從俯視透視圖觀之,第一打線接墊32a的位置係位在金屬線路32所連接之接墊16上方,而第二打線接點32b的位置則不同於金屬線路32所連接之接墊16的位置,所以本發明可選擇接合一打線導線58(例如金線)至第一打線接點32a、接合一打線導線58(例如金線)至第二打線接點32b或是分別接合一打線導線58(例如金線)至第一打線接點32a與第二打線接點32b。In addition, in the 10Cth to 10thth drawings, the position where the wire bonding wire 58 engages the metal wire 32 is viewed from a top perspective view, and the position may be different from the position of the pad 16 to which the metal wire 32 is connected, or different from The location of the metal protective cover 18 to which the metal line 32 is attached. Therefore, in the 10th to 10th drawings, the metal line 32 may include a first wire bonding contact 32a and a second wire bonding contact 32b. The position of the first wire bonding pad 32a is viewed from a top perspective view. Positioned above the pads 16 to which the metal lines 32 are connected, and the position of the second wire contacts 32b is different from the position of the pads 16 to which the metal lines 32 are connected, so the present invention can optionally engage a wire conductor 58 (eg, gold). Line) to the first wire bonding point 32a, joining a wire bonding wire 58 (for example, gold wire) to the second wire bonding contact 32b or respectively bonding a wire bonding wire 58 (for example, a gold wire) to the first wire bonding contact 32a and the second Wire the contact 32b.

第二實施例Second embodiment

請參閱第11A圖所示,透過一點膠製程(dispensing process),使複數黏著材料54形成於一導線架(lead frame)86之複數晶片承載座86a上;接著,將複數半導體晶片23分別壓合在這些黏著材料54上,並在經過烘烤製程之後使半導體晶片23黏著於晶片承載座86a。因此,半導體晶片23係透過黏著材料54以半導體基底2黏著於晶片承載座86a。其中,黏著材料54的材質比如是聚合物材料(例如聚醯亞胺、環氧樹脂或銀膠),且厚度係介於1微米至50微米之間,例如黏著材料54可以是厚度介於1微米至50微米之間的聚醯亞胺,或是厚度介於1微米至50微米之間的環氧樹脂,或是厚度介於1微米至50微米之間的銀膠(silver-filed epoxy)。此外,導線架86的材質包括銅或銅合金,且導線架86的厚度t6係介於100微米至2,000微米之間。Referring to FIG. 11A, the plurality of adhesive materials 54 are formed on a plurality of wafer carriers 86a of a lead frame 86 through a dispensing process; then, the plurality of semiconductor wafers 23 are respectively pressed. The adhesive material 54 is incorporated and the semiconductor wafer 23 is adhered to the wafer carrier 86a after the baking process. Therefore, the semiconductor wafer 23 is adhered to the wafer carrier 86a via the adhesive material 54 with the semiconductor substrate 2. Wherein, the material of the adhesive material 54 is, for example, a polymer material (for example, polyimide, epoxy or silver glue), and the thickness is between 1 micrometer and 50 micrometers, for example, the adhesive material 54 may have a thickness of 1 Polyimine between micrometers and 50 micrometers, or epoxy resin having a thickness between 1 micrometer and 50 micrometers, or silver-filed epoxy having a thickness between 1 micrometer and 50 micrometers. . In addition, the material of the lead frame 86 includes copper or a copper alloy, and the thickness t6 of the lead frame 86 is between 100 micrometers and 2,000 micrometers.

請參閱第11B圖所示,透過一打線製程使一打線導線58的一端球形(ball)接合至一半導體晶片23之一打線接墊22上(例如接合至打線接墊22的金層或鈀層上),而此打線導線58的另一端則楔形(wedge)接合至導線架86之一引腳(lead)86b上,其中打線導線58比如是直徑介於20微米至50微米之間且材質含金的一金屬線(或稱為金線)。因此,半導體晶片23的打線接墊22電性連接導線架86之引腳86b。Referring to FIG. 11B, one end of the wire bonding wire 58 is ball bonded to one of the wire bonding pads 22 of the semiconductor wafer 23 through a one-wire process (for example, a gold layer or a palladium layer bonded to the bonding pad 22). The other end of the wire bonding wire 58 is wedge-bonded to one of the lead 86b of the lead frame 86, wherein the wire bonding wire 58 is, for example, between 20 micrometers and 50 micrometers in diameter and contains a material. A metal wire of gold (or gold wire). Therefore, the wire bonding pads 22 of the semiconductor wafer 23 are electrically connected to the leads 86b of the lead frame 86.

請參閱第11C圖所示,以灌膜製程(molding process)形成厚度t7介於250微米至1,000微米之間的一聚合物材 料88包覆導線架86(其係包覆晶片承載座86a與部份引腳86b)、半導體晶片23以及打線導線58,並露出導線架86的部份引腳86b。其中,聚合物材料88的材質包括聚醯亞胺(PI)、苯基環丁烯(BCB)或環氧樹脂(expoy resin)。Referring to FIG. 11C, a polymer material having a thickness t7 between 250 micrometers and 1,000 micrometers is formed by a molding process. The material 88 covers the lead frame 86 (which covers the wafer carrier 86a and the partial leads 86b), the semiconductor wafer 23, and the wire bonding wires 58, and exposes a portion of the leads 86b of the lead frame 86. The material of the polymer material 88 includes polyimine (PI), phenylcyclobutene (BCB) or epoxy resin.

例如,利用灌膜製程形成厚度t7介於250微米至1,000微米之間的聚醯亞胺包覆導線架86(其係包覆晶片承載座86a與部份引腳86b)、半導體晶片23以及打線導線58,並露出導線架86的部份引腳86b;或者,利用灌膜製程形成厚度t7介於250微米至1,000微米之間的苯基環丁烯包覆導線架86(其係包覆晶片承載座86a與部份引腳86b)、半導體晶片23以及打線導線58,並露出導線架86的部份引腳86b;或者,利用灌膜製程形成厚度t7介於250微米至1,000微米之間且含有環氧樹脂的聚合物材料包覆導線架86(其係包覆晶片承載座86a與部份引腳86b)、半導體晶片23以及打線導線58,並露出導線架86的部份引腳86b。For example, a polyimide coated lead frame 86 (which covers the wafer carrier 86a and a portion of the leads 86b) having a thickness t7 between 250 micrometers and 1,000 micrometers, a semiconductor wafer 23, and a wire bonding is formed by a film filling process. a wire 58 and exposing a portion of the lead 86b of the lead frame 86; or, by using a film filling process, a phenylcyclobutene coated lead frame 86 having a thickness t7 between 250 micrometers and 1,000 micrometers (which is a coated wafer) a carrier 86a and a portion of the lead 86b), the semiconductor wafer 23 and the wire bonding wire 58 and exposing a portion of the lead 86b of the lead frame 86; or, by using a film filling process, forming a thickness t7 between 250 micrometers and 1,000 micrometers and The epoxy-containing polymer material covers the lead frame 86 (which covers the wafer carrier 86a and the partial leads 86b), the semiconductor wafer 23, and the wire bonding wires 58, and exposes a portion of the leads 86b of the lead frame 86.

請參閱第11D圖所示,於形成聚合物材料88之後,透過剪切分離(trim)以及將引腳86b壓成各種預先設計好之形狀等步驟形成晶片封裝結構90(或稱為導線架封裝,lead-frame package)。其中,導線架封裝結構90可以是小尺寸封裝(Small Outline Package,SOP)、薄型小尺寸封裝(Thin Small Outline Package,TSOP)、雙列直插式封裝(Dual In-Line Package,DIP)、陶瓷雙列直插式封裝(Ceramic Dual In-Line Package,CDIP)、玻璃陶瓷型雙列直插式封裝(Glass Ceramic Dual In-Line Packag,CERDIP)、表面貼裝型封裝(CERQUAD)、陶瓷有引腳晶片承載封裝(Ceramic leaded chip carrier,CLCC)、四方扁平封裝(Quad Flat Package,QFP)、塑膠有引腳晶片承載封裝(Plastic Leaded Chip Carrier,PLCC)、小尺寸J形引腳封裝(Small Outline J-lead,SOJ)、小尺寸積體電路封裝(Small Outline Integrated Circuit,SOIC)或交叉引腳封裝(Zig-zag In-line Package,ZIP)等封裝型式。Referring to FIG. 11D, after forming the polymer material 88, the chip package structure 90 (or the lead frame package) is formed by shear trimming and pressing the pins 86b into various pre-designed shapes. , lead-frame package). The lead frame package structure 90 can be a Small Outline Package (SOP), a Thin Small Outline Package (TSOP), a Dual In-Line Package (DIP), or a ceramic. Ceramic Dual In-Line Package (CDIP), glass ceramic dual in-line package (Glass Ceramic Dual In-Line Packag, CERDIP), surface mount package (CERQUAD), ceramic leaded chip carrier (CLCC), quad flat package (QFP), plastic pin Plastic Leaded Chip Carrier (PLCC), Small Outline J-lead (SOJ), Small Outline Integrated Circuit (SOIC) or Cross-Lead Package (Zig) -zag In-line Package, ZIP) and other package types.

請分別參閱第12A圖至第12L圖所示,透過上述第11A圖至第11D圖所述之步驟,本發明亦可使用半導體晶片31、36、40、42、44、46、48、50與52來取代第11圖系列中的半導體晶片23,並於剪切分離(trim)以及將引腳86b壓成各種預先設計好之形狀等步驟之後,形成晶片封裝結構92、94、96、98、100、102、104、106與108,詳細內容請參閱第11A圖至第11D圖的說明,在此不再詳加敘述。Referring to FIGS. 12A to 12L, respectively, the present invention may also use semiconductor wafers 31, 36, 40, 42, 44, 46, 48, 50 through the steps described in FIGS. 11A to 11D. Substituting the semiconductor wafer 23 in the series of FIG. 11 and forming the chip package structures 92, 94, 96, 98 after the steps of shearing and pressing the pins 86b into various pre-designed shapes. 100, 102, 104, 106, and 108. For details, please refer to the descriptions of FIGS. 11A to 11D, which will not be described in detail herein.

另,在第12C圖至第12L圖中,打線導線58接合金屬線路32的位置從俯視透視圖觀之,此位置可以是不同於金屬線路32所連接之接墊16的位置,或者是不同於金屬線路32所連接之金屬保護蓋18的位置。因此,在第12C圖至第12L圖中,金屬線路32可以是包括一第一打線接點32a與一第二打線接點32b,從俯視透視圖觀之,第一打線接墊32a的位置係位在金屬線路32所連接之接墊16上方,而第二打線接點32b的位置則不同於金屬線路32 所連接之接墊16的位置,所以本發明可選擇接合一打線導線58(例如金線)至第一打線接點32a、接合一打線導線58(例如金線)至第二打線接點32b或是分別接合一打線導線58(例如金線)至第一打線接點32a與第二打線接點32b。In addition, in the 12th to 12th drawings, the position where the wire bonding wire 58 engages the metal wire 32 is viewed from a top perspective view, and the position may be different from the position of the pad 16 to which the metal wire 32 is connected, or different from The location of the metal protective cover 18 to which the metal line 32 is attached. Therefore, in the 12th to 12thth drawings, the metal line 32 may include a first wire bonding contact 32a and a second wire bonding contact 32b. The position of the first wire bonding pad 32a is viewed from a top perspective view. The position is above the pad 16 to which the metal line 32 is connected, and the position of the second wire contact 32b is different from the metal line 32. The position of the connected pads 16, so the present invention can optionally engage a wire conductor 58 (e.g., gold wire) to the first wire bond 32a, engage a wire conductor 58 (e.g., gold wire) to the second wire bond 32b or A wire bonding wire 58 (for example, a gold wire) is bonded to the first wire bonding contact 32a and the second wire bonding contact 32b, respectively.

以上所述係藉由實施例說明本發明之特點,其目的在使熟習該技術者能暸解本發明之內容並據以實施,而非限定本發明之專利範圍,故,凡其他未脫離本發明所揭示之精神所完成之等效修飾或修改,仍應包含在以下所述之申請專利範圍中。The above description of the embodiments of the present invention is intended to be understood by those skilled in the art, and the invention may be practiced without departing from the scope of the invention. Equivalent modifications or modifications made by the spirit of the invention should still be included in the scope of the claims described below.

2‧‧‧半導體基底2‧‧‧Semiconductor substrate

4‧‧‧半導體元件4‧‧‧Semiconductor components

6‧‧‧線路結構6‧‧‧Line structure

8‧‧‧圖案化金屬層8‧‧‧ patterned metal layer

10‧‧‧金屬插塞10‧‧‧Metal plug

12‧‧‧介電層12‧‧‧Dielectric layer

14‧‧‧保護層14‧‧‧Protective layer

14a‧‧‧開口14a‧‧‧ Opening

16‧‧‧接墊16‧‧‧ pads

18‧‧‧金屬保護蓋18‧‧‧Metal protective cover

20‧‧‧結構20‧‧‧ structure

22‧‧‧打線接墊22‧‧‧Wire pad

23‧‧‧半導體晶片23‧‧‧Semiconductor wafer

24‧‧‧黏著/阻障層24‧‧‧Adhesive/barrier layer

26‧‧‧種子層26‧‧‧ seed layer

28‧‧‧光阻層28‧‧‧Photoresist layer

28a‧‧‧光阻層開口28a‧‧‧Photoresistive opening

30‧‧‧金屬層30‧‧‧metal layer

31‧‧‧半導體晶片31‧‧‧Semiconductor wafer

32‧‧‧金屬線路32‧‧‧Metal lines

32a‧‧‧打線接點32a‧‧‧Wire contact

32b‧‧‧打線接點32b‧‧‧Wire contact

34‧‧‧聚合物層34‧‧‧ polymer layer

34a‧‧‧開口34a‧‧‧ openings

36‧‧‧半導體晶片36‧‧‧Semiconductor wafer

38‧‧‧聚合物層38‧‧‧ polymer layer

38a‧‧‧開口38a‧‧‧ Opening

40‧‧‧半導體晶片40‧‧‧Semiconductor wafer

42‧‧‧半導體晶片42‧‧‧Semiconductor wafer

44‧‧‧半導體晶片44‧‧‧Semiconductor wafer

46‧‧‧半導體晶片46‧‧‧Semiconductor wafer

48‧‧‧半導體晶片48‧‧‧Semiconductor wafer

50‧‧‧半導體晶片50‧‧‧Semiconductor wafer

52‧‧‧半導體晶片52‧‧‧Semiconductor wafer

54‧‧‧黏著材料54‧‧‧Adhesive materials

56‧‧‧基板56‧‧‧Substrate

57‧‧‧接點57‧‧‧Contacts

58‧‧‧打線導線58‧‧‧Wire wire

60‧‧‧聚合物材料60‧‧‧Polymer materials

62‧‧‧無鉛錫球62‧‧‧Unleaded solder balls

64‧‧‧接點64‧‧‧Contacts

66‧‧‧晶片封裝結構66‧‧‧ Chip package structure

68‧‧‧晶片封裝結構68‧‧‧ Chip package structure

70‧‧‧晶片封裝結構70‧‧‧ Chip package structure

72‧‧‧晶片封裝結構72‧‧‧ Chip package structure

74‧‧‧晶片封裝結構74‧‧‧ Chip package structure

76‧‧‧晶片封裝結構76‧‧‧ Chip package structure

78‧‧‧晶片封裝結構78‧‧‧ Chip package structure

80‧‧‧晶片封裝結構80‧‧‧ Chip package structure

82‧‧‧晶片封裝結構82‧‧‧ Chip package structure

84‧‧‧晶片封裝結構84‧‧‧ Chip package structure

86‧‧‧導線架86‧‧‧ lead frame

86a‧‧‧晶片承載座86a‧‧‧ wafer carrier

86b‧‧‧引腳86b‧‧‧ pin

88‧‧‧聚合物材料88‧‧‧Polymer materials

90‧‧‧晶片封裝結構90‧‧‧ Chip package structure

92‧‧‧晶片封裝結構92‧‧‧ Chip package structure

94‧‧‧晶片封裝結構94‧‧‧ Chip package structure

96‧‧‧晶片封裝結構96‧‧‧ Chip package structure

98‧‧‧晶片封裝結構98‧‧‧ Chip package structure

100‧‧‧晶片封裝結構100‧‧‧ Chip package structure

102‧‧‧晶片封裝結構102‧‧‧ Chip package structure

104‧‧‧晶片封裝結構104‧‧‧ Chip package structure

106‧‧‧晶片封裝結構106‧‧‧ Chip package structure

108‧‧‧晶片封裝結構108‧‧‧ Chip package structure

110‧‧‧金線110‧‧‧ Gold wire

112‧‧‧半導體晶片112‧‧‧Semiconductor wafer

114‧‧‧鋁金屬保護蓋114‧‧‧Aluminum metal protective cover

116‧‧‧球型柵狀陣列基板116‧‧‧Spherical grid array substrate

118‧‧‧保護層118‧‧‧Protective layer

118a‧‧‧開口118a‧‧‧ Opening

120‧‧‧銅墊120‧‧‧ copper pad

122‧‧‧錫球122‧‧‧ solder balls

圖式說明:Schematic description:

第1圖為習知球型柵狀陣列封裝結構的剖面示意圖。FIG. 1 is a schematic cross-sectional view of a conventional ball grid array package structure.

第2A圖至第2B圖分別為本發明之一結構的剖面示意圖。2A to 2B are respectively schematic cross-sectional views showing a structure of the present invention.

第3圖為本發明之一半導體晶片具有打線接墊的剖面示意圖。Fig. 3 is a schematic cross-sectional view showing a semiconductor wafer having a wire bonding pad of the present invention.

第4A圖至第4G圖為本發明形成打線接墊的製程剖面示意圖。4A to 4G are schematic cross-sectional views showing a process for forming a wire bonding pad according to the present invention.

第5A圖與第5B圖為本發明之一半導體晶片具有打線接墊的剖面示意圖。5A and 5B are schematic cross-sectional views showing a semiconductor wafer having a wire bonding pad according to the present invention.

第6A圖至第6G圖為本發明形成打線接墊的製程剖面示意圖。6A to 6G are schematic cross-sectional views showing a process of forming a wire bonding pad according to the present invention.

第7A圖與第7F圖分別為本發明之一半導體晶片具有金屬 線路在保護層上方的剖面示意圖。7A and 7F are respectively a semiconductor wafer having a metal according to the present invention A schematic cross-section of the line above the protective layer.

第8A圖與第8D圖分別為本發明之一半導體晶片具有金屬線路在保護層上方的剖面示意圖。8A and 8D are respectively schematic cross-sectional views showing a semiconductor wafer having a metal line over a protective layer.

第9A圖至第9E圖為本發明之一實施例的製程剖面示意圖。9A to 9E are schematic cross-sectional views showing a process of an embodiment of the present invention.

第10A圖與第10L圖分別為本發明之一晶片封裝結構的剖面示意圖。10A and 10L are respectively schematic cross-sectional views of a wafer package structure of the present invention.

第11A圖至第11D圖為本發明之一實施例的製程剖面示意圖。11A to 11D are schematic cross-sectional views showing a process of an embodiment of the present invention.

第12A圖與第12L圖分別為本發明之一導線架封裝結構的剖面示意圖。12A and 12L are respectively schematic cross-sectional views of a lead frame package structure of the present invention.

2‧‧‧半導體基底2‧‧‧Semiconductor substrate

14‧‧‧保護層14‧‧‧Protective layer

14a‧‧‧開口14a‧‧‧ Opening

16‧‧‧接墊16‧‧‧ pads

20‧‧‧結構20‧‧‧ structure

22‧‧‧打線接墊22‧‧‧Wire pad

23‧‧‧半導體晶片23‧‧‧Semiconductor wafer

54‧‧‧黏著材料54‧‧‧Adhesive materials

56‧‧‧基板56‧‧‧Substrate

57‧‧‧接點57‧‧‧Contacts

58‧‧‧打線導線58‧‧‧Wire wire

60‧‧‧聚合物材料60‧‧‧Polymer materials

62‧‧‧無鉛錫球62‧‧‧Unleaded solder balls

64‧‧‧接點64‧‧‧Contacts

66‧‧‧晶片封裝結構66‧‧‧ Chip package structure

Claims (20)

一種晶片封裝結構,其包括:球型柵狀陣列(BGA)基板;半導體晶片,其係位於該球型柵狀陣列基板上方,其中該半導體晶片包括半導體基底、金氧半導體(MOS)元件、第一介電層、線路結構、第二介電層、保護層以及打線接合墊,該金氧半導體(MOS)元件位於該半導體基底內或上方,該第一介電層位於該半導體基底上方,該線路結構位於該第一介電層上方,其中該線路結構包括第一金屬層及第二金屬層,該第二金屬層位於該第一金屬層上方,該第二介電層位於該第一金屬層及該第二金屬層之間,該保護層位於該MOS元件上方,該保護層位於該第一介電層及該第二介電層上方,且該保護層位於該線路結構上方,其中該保護層包括氮化物層,其中在該保護層中的一開口位於該線路結構的一接點上方,並且該接點位於該開口的底部,且該打線接合墊位於該半導體基底上方,其中該打線接合墊經由該開口連接該接點,其中該打線接合墊包括一銅層;黏著材料(glue material),位於該球型柵狀陣列基板與該半導體晶片之間,其中該黏著材料接觸該球型柵狀陣列基板與該半導體基底;打線導線,接合該打線接合墊與該球型柵狀陣列基板;聚合物材料,位於該球型柵狀陣列基板與該保護層上方,其中該聚合物材料包覆該打線導線;以及無鉛錫球(lead-free solder ball),位於該球型柵狀陣列基板 上,其中該無鉛錫球包括錫。 A chip package structure comprising: a ball grid array (BGA) substrate; a semiconductor wafer disposed above the ball grid array substrate, wherein the semiconductor wafer comprises a semiconductor substrate, a metal oxide semiconductor (MOS) device, a dielectric layer, a wiring structure, a second dielectric layer, a protective layer, and a wire bond pad, the metal oxide semiconductor (MOS) device being located in or over the semiconductor substrate, the first dielectric layer being over the semiconductor substrate, The circuit structure is located above the first dielectric layer, wherein the circuit structure comprises a first metal layer and a second metal layer, the second metal layer is located above the first metal layer, and the second dielectric layer is located at the first metal layer Between the layer and the second metal layer, the protective layer is located above the MOS device, the protective layer is located above the first dielectric layer and the second dielectric layer, and the protective layer is located above the circuit structure, wherein the The protective layer includes a nitride layer, wherein an opening in the protective layer is located above a junction of the wiring structure, and the contact is located at a bottom of the opening, and the bonding pad is located at the semiconductor a bottom layer, wherein the wire bond pad is connected to the contact via the opening, wherein the wire bond pad comprises a copper layer; a glue material is located between the ball grid array substrate and the semiconductor wafer, wherein the wire bond pad The adhesive material contacts the spherical grid array substrate and the semiconductor substrate; the wire bonding wire joins the wire bonding pad and the spherical grid array substrate; the polymer material is located above the spherical grid array substrate and the protective layer, Wherein the polymer material covers the wire bonding wire; and a lead-free solder ball is located on the ball grid array substrate Above, wherein the lead-free solder ball comprises tin. 如申請專利範圍第1項所述之晶片封裝結構,其中該線路結構包括電鍍銅。 The wafer package structure of claim 1, wherein the wiring structure comprises electroplated copper. 如申請專利範圍第1項所述之晶片封裝結構,其中該線路結構包括鋁。 The wafer package structure of claim 1, wherein the wiring structure comprises aluminum. 如申請專利範圍第1項所述之晶片封裝結構,其中該打線接合墊進一步包括含鈦金屬層,該含鈦金屬層位於該銅層下方。 The wafer package structure of claim 1, wherein the wire bonding pad further comprises a titanium-containing metal layer, the titanium-containing metal layer being located under the copper layer. 如申請專利範圍第1項所述之晶片封裝結構,其中該打線接合墊進一步包括鎳層,該鎳層位於該銅層上方。 The wafer package structure of claim 1, wherein the wire bond pad further comprises a nickel layer, the nickel layer being over the copper layer. 如申請專利範圍第1項所述之晶片封裝結構,其中該打線接合墊進一步包括鎳層及金層,該鎳層位在該銅層上,該金層位於該鎳層上。 The chip package structure of claim 1, wherein the wire bond pad further comprises a nickel layer and a gold layer, the nickel layer being on the copper layer, the gold layer being on the nickel layer. 如申請專利範圍第1項所述之晶片封裝結構,其中該打線接合墊進一步包括鎳層及鈀層,該鎳層位於該銅層上方,該鈀層位於該鎳層上方。 The wafer package structure of claim 1, wherein the wire bond pad further comprises a nickel layer and a palladium layer, the nickel layer being above the copper layer, the palladium layer being above the nickel layer. 如申請專利範圍第1項所述之晶片封裝結構,其中該銅層的厚度係介於1微米至13微米之間。 The wafer package structure of claim 1, wherein the copper layer has a thickness of between 1 micrometer and 13 micrometers. 如申請專利範圍第1項所述之晶片封裝結構,其中該聚合物材料具有第一左側壁及第一右側壁,該第一右側壁相對於且平行於該第一左側壁,並且該球型柵狀陣列基板具有第二左側壁及第二右側壁,該第二右側壁相對於且平行於該第二左側壁,其中該第一左側壁與該第二左側壁基本上共平面,並且該第一右側壁與該第二右側壁基本上共平面。 The wafer package structure of claim 1, wherein the polymer material has a first left side wall and a first right side wall, the first right side wall being opposite and parallel to the first left side wall, and the spherical type The grid array substrate has a second left side wall and a second right side wall, the second right side wall being opposite and parallel to the second left side wall, wherein the first left side wall and the second left side wall are substantially coplanar, and The first right side wall is substantially coplanar with the second right side wall. 如申請專利範圍第1項所述之晶片封裝結構,其中該無 鉛錫球進一步包括銀,並且該無鉛錫球的直徑係介於0.25釐米至1.2釐米之間。 The chip package structure of claim 1, wherein the The lead solder ball further includes silver, and the lead-free solder ball has a diameter of between 0.25 cm and 1.2 cm. 如申請專利範圍第1項所述之晶片封裝結構,其中該球型柵狀陣列基板具有頂側與底側,其中該半導體晶片、該黏著材料及該聚合物材料位於該頂側,並且該無鉛錫球位於該底側。 The chip package structure of claim 1, wherein the ball grid array substrate has a top side and a bottom side, wherein the semiconductor wafer, the adhesive material and the polymer material are on the top side, and the lead-free The solder ball is located on the bottom side. 一種晶片封裝結構,其包括:球型柵狀陣列(BGA)基板;半導體晶片,其係位於該球型柵狀陣列基板上方,其中該半導體晶片包括矽基底、金氧半導體(MOS)元件、第一介電層、線路結構、第二介電層、保護層以及打線接合墊,該金氧半導體(MOS)元件位於該矽基底內或上方,該第一介電層位於該矽基底上方,該線路結構位於該第一介電層上方,其中該線路結構包括第一金屬層及第二金屬層,該第二金屬層位於該第一金屬層上方,該第二介電層位於該第一金屬層及該第二金屬層之間,該保護層位於該MOS元件上方,該保護層位於該第一介電層及該第二介電層上方,且該保護層位於該線路結構上方,其中該保護層包括氮化物層,其中在該保護層中的一開口位於該線路結構的一接點上方,並且該接點位於該開口的底部,且該打線接合墊位於該矽基底上方,其中該打線接合墊經由該開口連接該接點,其中該打線接合墊包括一含鈦金屬層及一金層,該含鈦金屬層的厚度係介於0.03微米至0.7微米之間,該金層的厚度係介於1微米至20微米之間,該金層位於該含鈦金屬層上方;黏著材料(glue material),位於該球型柵狀陣列基板與該半 導體晶片之間,其中該黏著材料接觸該球型柵狀陣列基板與該矽基底;金線,接合該金層與該球型柵狀陣列基板;聚合物材料,位於該球型柵狀陣列基板與該保護層上方,其中該聚合物材料包覆該金線;以及無鉛錫球,位於該球型柵狀陣列基板上,其中該無鉛錫球包括錫。 A chip package structure comprising: a ball grid array (BGA) substrate; a semiconductor wafer disposed above the ball grid array substrate, wherein the semiconductor wafer comprises a germanium substrate, a metal oxide semiconductor (MOS) device, a dielectric layer, a wiring structure, a second dielectric layer, a protective layer, and a wire bonding pad, the metal oxide semiconductor (MOS) device being located in or above the germanium substrate, the first dielectric layer being located above the germanium substrate, The circuit structure is located above the first dielectric layer, wherein the circuit structure comprises a first metal layer and a second metal layer, the second metal layer is located above the first metal layer, and the second dielectric layer is located at the first metal layer Between the layer and the second metal layer, the protective layer is located above the MOS device, the protective layer is located above the first dielectric layer and the second dielectric layer, and the protective layer is located above the circuit structure, wherein the The protective layer includes a nitride layer, wherein an opening in the protective layer is above a junction of the wiring structure, and the contact is located at a bottom of the opening, and the bonding pad is located above the germanium substrate, wherein the The wire bonding pad is connected to the contact via the opening, wherein the wire bonding pad comprises a titanium-containing metal layer and a gold layer, and the titanium-containing metal layer has a thickness of between 0.03 micrometers and 0.7 micrometers, and the thickness of the gold layer Between 1 micrometer and 20 micrometers, the gold layer is above the titanium-containing metal layer; a glue material is located on the spherical grid array substrate and the half Between the conductor wafers, wherein the adhesive material contacts the spherical grid array substrate and the germanium substrate; a gold wire bonding the gold layer and the spherical grid array substrate; and a polymer material located on the spherical grid array substrate And the protective layer, wherein the polymer material covers the gold wire; and the lead-free solder ball is located on the ball grid array substrate, wherein the lead-free solder ball comprises tin. 如申請專利範圍第12項所述之晶片封裝結構,其中該線路結構包括電鍍銅。 The wafer package structure of claim 12, wherein the wiring structure comprises electroplated copper. 如申請專利範圍第12項所述之晶片封裝結構,其中該線路結構包括鋁。 The wafer package structure of claim 12, wherein the wiring structure comprises aluminum. 如申請專利範圍第12項所述之晶片封裝結構,其中該金層的該厚度係介於3微米至5微米之間。 The wafer package structure of claim 12, wherein the thickness of the gold layer is between 3 microns and 5 microns. 如申請專利範圍第12項所述之晶片封裝結構,其中該無鉛錫球進一步包括銀,並且該無鉛錫球的直徑係介於0.25釐米至1.2釐米之間。 The wafer package structure of claim 12, wherein the lead-free solder ball further comprises silver, and the lead-free solder ball has a diameter of between 0.25 cm and 1.2 cm. 如申請專利範圍第12項所述之晶片封裝結構,其中該球型柵狀陣列基板具有頂側與底側,其中該半導體晶片、該黏著材料及該聚合物材料位於該頂側,並且該無鉛錫球位於該底側。 The chip package structure of claim 12, wherein the spherical grid array substrate has a top side and a bottom side, wherein the semiconductor wafer, the adhesive material and the polymer material are on the top side, and the lead-free The solder ball is located on the bottom side. 如申請專利範圍第12項所述之晶片封裝結構,其中該黏著材料包括以環氧樹脂為基質的材料。 The wafer package structure of claim 12, wherein the adhesive material comprises an epoxy resin-based material. 如申請專利範圍第12項所述之晶片封裝結構,其中該聚合物材料包括以環氧樹脂為基質的材料。 The wafer package structure of claim 12, wherein the polymer material comprises an epoxy resin based material. 如申請專利範圍第12項所述之晶片封裝結構,其中在該 金線與該打線接合墊之間的接觸區域係直立地位於該接點上方。 The chip package structure of claim 12, wherein The contact area between the gold wire and the wire bond pad is located upright above the joint.
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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6376353B1 (en) * 2000-07-03 2002-04-23 Chartered Semiconductor Manufacturing Ltd. Aluminum and copper bimetallic bond pad scheme for copper damascene interconnects
US20040227239A1 (en) * 2003-03-18 2004-11-18 Ngk Spark Plug Co., Ltd. Wiring board

Family Cites Families (3)

* Cited by examiner, † Cited by third party
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6376353B1 (en) * 2000-07-03 2002-04-23 Chartered Semiconductor Manufacturing Ltd. Aluminum and copper bimetallic bond pad scheme for copper damascene interconnects
US20040227239A1 (en) * 2003-03-18 2004-11-18 Ngk Spark Plug Co., Ltd. Wiring board

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