TWI427718B - Chip package and method for fabricating the same - Google Patents

Description

Chip package structure and manufacturing method thereof

The present invention relates to a chip package structure and a method of fabricating the same, and more particularly to a chip package structure having different types of metal pads over the same semiconductor substrate and a method of fabricating the same.

In today's highly information-based society, the market for multimedia applications is rapidly expanding. The integrated circuit packaging technology also needs to be developed in line with the digitalization, networking, regional connectivity and user-friendly trends of electronic devices. In order to achieve the above requirements, it is necessary to strengthen the high-speed processing, multi-function, accumulation, small size, light weight, and low cost of electronic components. Therefore, the integrated circuit packaging technology is also oriented toward miniaturization and high density. Development, so Ball Grid Array (BGA), Chip-Scale Package (CSP), Flip Chip (F/C) and Multi-Chip Module (Multi High-density integrated circuit packaging technology such as -Chip Module, MCM) has also emerged. For high-density integrated circuit packages, shortening the length of the connection line will improve the signal transmission speed, so the application of the bump has gradually become the mainstream of high-density packaging.

In addition, in these package structures, solder bumps are used as a dielectric to electrically connect a semiconductor wafer to another semiconductor wafer, and also form a plurality of wires by a wire-bonding process. A wire bonding wire connects the semiconductor wafer to a printed circuit board.

In the prior art, most of the bonding pads on the wafer use aluminum pads, so if solder bumps are to be formed on the same wafer and some aluminum pads for wire bonding are reserved, The aluminum pad used for wire bonding is often damaged because the under bump metallurgy (UBM) must be formed between the solder bump and the aluminum pad to have an adhesion function and a barrier function. The etching solution used in the etching process of the underlying metal of the bump usually contains hydrofluoric acid (HF) and other buffer solutions, and hydrofluoric acid will cause surface damage of the aluminum pad, thereby making the soldering process of the wire bonding process reliable. Reliability is not good.

It is an object of the present invention to provide a wafer package structure having two different types of metal pads positioned over the same semiconductor substrate.

It is an object of the present invention to provide a chip package structure having a pad that connects one of the tin-containing metal layers and another wire that connects the wire wires.

It is an object of the present invention to provide a chip package structure having another pad that connects one of the tin-containing metal layers and the connection tape.

It is an object of the present invention to provide a chip package structure having a pad for connecting one of the tin-containing metal layers and another pad for bonding an external circuit with an anisotropic conductive paste.

It is an object of the present invention to provide a chip package structure having a pad for bonding an external circuit with an anisotropic conductive paste, and another pad for attaching the tape.

It is an object of the present invention to provide a chip package structure having a pad for connecting a wire conductor and another pad for attaching the tape.

It is an object of the present invention to provide a chip package structure having a pad for connecting a wire bonding wire and another pad having an external circuit bonded by an anisotropic conductive paste.

It is an object of the present invention to provide a wafer package structure having at least two metal pads of different thicknesses positioned above the same semiconductor substrate.

It is an object of the present invention to provide a wafer package structure having a plurality of metal pads of the same thickness positioned above the same semiconductor substrate.

For the above purpose, the present invention provides a chip package structure comprising: a semiconductor substrate; a line structure disposed above the semiconductor substrate and including a first pad and a second pad; a protective layer located at Above the circuit structure, and a first opening and a second opening in the protective layer respectively expose the first pad and the second pad; a metal pad is located in the first a pad; a tape that engages the metal pad; and a tin-containing metal layer positioned above the second pad.

For the above purpose, the present invention provides a chip package structure comprising: a semiconductor substrate; a line structure disposed above the semiconductor substrate and including a first pad and a second pad; a protective layer located at Above the circuit structure, a first opening and a second opening in the protective layer respectively expose the first pad and the second pad; a metal pad is located on the first pad, And an anisotropic conductive paste is used to connect an external circuit; and a tin-containing metal layer is disposed above the second pad.

For the above purpose, the present invention provides a chip package structure comprising: a semiconductor substrate; a line structure disposed above the semiconductor substrate and including a first pad and a second pad; a protective layer located at Above the circuit structure, a first opening and a second opening in the protective layer respectively expose the first pad and the second pad; a first metal pad is located at the first connection a second metal pad on the second pad; a tape bonding the first metal pad; and a wire bonding wire to engage the second metal pad.

For the above purpose, the present invention provides a chip package structure comprising: a semiconductor substrate; a line structure disposed above the semiconductor substrate and including a first pad and a second pad; a protective layer located at Above the circuit structure, a first opening and a second opening in the protective layer respectively expose the first pad and the second pad; a first metal pad is located at the first connection Padded with an anisotropic conductive paste to bond an external circuit; a second metal pad on the second pad; and a wire bond to engage the second metal pad.

For the above purpose, the present invention provides a chip package structure comprising: a semiconductor substrate; a line structure disposed above the semiconductor substrate and including a first pad and a second pad; a protective layer located at Above the circuit structure, a first opening and a second opening in the protective layer respectively expose the first pad and the second pad; a first metal pad is located at the first connection And affixing an external circuit with an anisotropic conductive paste; a second metal pad is disposed on the second pad; and a tape bonding the second metal pad.

For the above purpose, the present invention provides a chip package structure comprising: a semiconductor substrate; a line structure disposed above the semiconductor substrate and including a first pad and a second pad; a protective layer located at Above the circuit structure, a first opening and a second opening in the protective layer respectively expose the first pad and the second pad; a metal pad is connected to the first opening through the first opening a first pad; a tape bonding the metal pad; and a tin-containing metal layer connected to the second pad through the second opening.

For the above purpose, the present invention provides a chip package structure comprising: a semiconductor substrate; a line structure disposed above the semiconductor substrate and including a first pad and a second pad; a protective layer located at Above the circuit structure, a first opening and a second opening in the protective layer respectively expose the first pad and the second pad; a metal pad is connected to the first opening through the first opening a first pad, and an external circuit is bonded by using an anisotropic conductive paste; and a tin-containing metal layer is connected to the second pad through the second opening.

For the above purpose, the present invention provides a chip package structure comprising: a semiconductor substrate; a line structure disposed above the semiconductor substrate and including a first pad and a second pad; a protective layer located at Above the circuit structure, a first opening and a second opening in the protective layer respectively expose the first pad and the second pad; a first metal pad is connected through the first opening To the first pad; a second metal pad connected to the second pad through the second opening; a tape bonding the first metal pad; and a wire bonding wire connecting the second metal pad pad.

For the above purpose, the present invention provides a chip package structure comprising: a semiconductor substrate; a line structure disposed above the semiconductor substrate and including a first pad and a second pad; a protective layer located at Above the circuit structure, a first opening and a second opening in the protective layer respectively expose the first pad and the second pad; a first metal pad is connected through the first opening To the first pad, and using an anisotropic conductive adhesive to bond an external circuit; a second metal pad connected to the second pad through the second opening; and a wire bonding wire connecting the second metal connection pad.

For the above purpose, the present invention provides a chip package structure comprising: a semiconductor substrate; a line structure disposed above the semiconductor substrate and including a first pad and a second pad; a protective layer located at Above the circuit structure, a first opening and a second opening in the protective layer respectively expose the first pad and the second pad; a first metal pad is connected through the first opening To the first pad, and an external circuit is bonded by using an anisotropic conductive paste; a second metal pad is connected to the second pad through the second opening; and a tape is attached to the second metal bond pad.

For the above purpose, the present invention provides a chip package structure comprising: a semiconductor substrate; a line structure disposed above the semiconductor substrate and including a first pad and a second pad; a protective layer located at Above the circuit structure, a first opening and a second opening in the protective layer respectively expose the first pad and the second pad; a metal pad is connected to the first opening through the first opening a first pad, and the metal pad comprises a gold layer; a tape bonding the gold layer; and a wire bonding wire connecting the second pad.

For the above purpose, the present invention provides a chip package structure comprising: a semiconductor substrate; a line structure disposed above the semiconductor substrate and including a first pad and a second pad; a protective layer located at Above the circuit structure, a first opening and a second opening in the protective layer respectively expose the first pad and the second pad; a metal pad is connected to the first opening through the first opening a first pad, wherein the metal pad comprises a gold layer, and an external circuit is directly connected to the gold layer through the anisotropic conductive paste; and a wire bonding wire is connected to the second pad.

For the above purpose, the present invention provides a chip package structure comprising: a semiconductor substrate; a line structure disposed above the semiconductor substrate and including a first pad and a second pad; a protective layer located at Above the circuit structure, a first opening and a second opening in the protective layer respectively expose the first pad and the second pad; a metal pad is connected to the first opening through the first opening a first pad, and the metal pad comprises a gold layer; a metal bump is located on the gold layer; and a wire bonding wire is connected to the second pad.

The purpose, technical contents, features and effects achieved by the present invention will be more readily understood by the detailed description of the embodiments and the accompanying drawings.

The present invention relates to a semiconductor wafer or semiconductor chip having two different types of metal pads over the same semiconductor substrate, which can be used for wire bonding (wire- Bonding, metal bump bonding, solder bump bonding, tape automated bonding (TAB), thin film polycrystalline bonding, or glass polycrystalline bonding. The word "above" means that it is on or in contact with something, or that it is on something but not in contact with it.

Each of the structures and methods disclosed in the present invention is constructed on a passivation layer of a semiconductor wafer, and the semiconductor wafer can be diced after construction to form a plurality of semiconductor wafers. Among them, the word "upper" means that it is located on and in contact with something. The underside of the protective layer includes a semiconductor substrate, and a wiring structure and a plurality of dielectric layers between the protective layer and the semiconductor substrate, and the openings above the semiconductor substrate are exposed through openings located in the protective layer. Structured pads. Therefore, the contents of the semiconductor substrate, the wiring structure, the dielectric layer, the pads, and the protective layer will be described first, followed by the description of various embodiments of the present invention.

Referring to FIG. 1, the semiconductor substrate 2 may be a germanium substrate, a gallium arsenide substrate (GaAs) or a germanium telluride (SiGe) substrate, and a plurality of semiconductor elements 4 are located in or above the semiconductor substrate 2. Wherein, the semiconductor elements 4 include passive components (such as resistors, capacitors, inductors) or active components, and the active components are, for example, metal oxide semiconductor (MOS) components, such as p-channel MOS devices (p -channel MOS devices), n-channel MOS devices, biCMOS devices, Bipolar Junction Transistors (BJT) or complementary metals Oxide semiconductor (CMOS).

A wiring structure 6 is positioned above the semiconductor substrate 2, and the wiring structure 6 is composed of a plurality of metal wiring layers 8 (having a thickness of, for example, less than 3 μm) and a plurality of metal plugs 10, wherein the metal wiring layers are formed. 8 and the metal plug 10 are made of copper, or the metal wiring layer 8 is made of aluminum, and the metal plug 10 is made of tungsten. In addition, the manner of forming the metal wiring layer 8 includes a damascene process, an electroplating process, or a sputtering process, for example, forming a metal wiring layer 8 by a damascene process, an electroplating process, or a sputtering process. Or aluminum is formed as a metal wiring layer 8 by a sputtering process.

A plurality of dielectric layers 12 (having a thickness of, for example, less than 3 micrometers) are positioned over the semiconductor substrate 2, and the metal wiring layers 8 are located between the dielectric layers 12, and are transmitted through the dielectric layers The metal plug 10 in the electrical layer 12 connects the adjacent two layers of the metal wiring layer 8. In addition, the dielectric layer 12 is generally formed by chemical vapor deposition (CVD), and the dielectric layer 12 is, for example, an oxonium compound (for example, SiO 2 ) or tetraethoxy decane (TEOS). Oxides, compounds containing ruthenium, carbon, oxygen and hydrogen (eg SiwCxOyHz), nitrogen ruthenium compounds (eg Si3N4), Fluorinated Silicate Glass (FSG), Black Diamond, Silk Screen (SiLK) , porous silicon oxide or oxynitride compound, or glass formed by spin coating (SOG), polyarylene ether, polybenzoxazole (PBO), or Other materials with dielectric constant values (k) between 1.5 and 3.

A protective layer 14 is positioned over the wiring structure 6 and the dielectric layer 12. The protective layer 14 protects the semiconductor component 4 and the wiring structure 6 from moisture and foreign ion contamination, that is, It is said that the protective layer 14 can prevent mobile ions (such as sodium ions), moisture, transition metals (such as gold, silver, copper) and other impurities from penetrating, and damage the semiconductor elements under the protective layer 14. 4 (for example a transistor, a polysilicon resistor or a polysilicon-polysilicon capacitor) or a line structure 6.

The protective layer 14 is generally composed of an oxonium compound (for example, SiO2), Phosphosilicate Glass (PSG), a nitrogen-onium compound (for example, Si3N4) or an oxynitride compound, and the above-mentioned oxonium compound includes an organic oxide. Alternatively to the inorganic oxide, the thickness of the additional protective layer 14 is generally greater than 0.35 micrometers (μm), while in the case of the layer comprising the nitrogen cerium compound, the thickness of the nitrogen cerium compound layer is typically greater than 0.3 micrometers. The current manufacturing method of the protective layer 14 is about ten different methods, as described below.

The first method of forming the protective layer 14 is to first form a layer of germanium oxide having a thickness of between 0.2 μm and 1.2 μm by chemical vapor deposition, followed by chemical vapor deposition to form a thickness of between 0.2 μm and 1.2 μm. The tantalum nitride layer is on the tantalum oxide layer.

The second method of forming the protective layer 14 is to first form a ruthenium oxide layer having a thickness of between 0.2 μm and 1.2 μm by chemical vapor deposition, and continue to utilize Plasma Enhanced Chemical Vapor Deposition (Plasma Enhanced Chemical Vapor Deposition, PECVD) forming a layer of bismuth oxynitride having a thickness between 0.05 micrometers and 0.15 micrometers on the yttrium oxide layer, followed by chemical vapor deposition to form a tantalum nitride layer having a thickness between 0.2 micrometers and 1.2 micrometers. On the ruthenium oxynitride layer.

A third method of forming the protective layer 14 is to first form a niobium oxynitride layer having a thickness of between 0.05 μm and 0.15 μm by chemical vapor deposition, and continue to form a thickness of 0.2 μm to 1.2 μm by chemical vapor deposition. The inter-phosphorus oxide layer is on the hafnium oxynitride layer, followed by chemical vapor deposition to form a tantalum nitride layer having a thickness between 0.2 μm and 1.2 μm on the hafnium oxide layer.

A fourth method of forming the protective layer 14 is to first form a first ruthenium oxide layer having a thickness of between 0.2 μm and 0.5 μm by chemical vapor deposition, and continue to form a thickness of 0.5 by spin-coating. a second ruthenium oxide layer between micrometers to 1 micrometer on the first ruthenium oxide layer, followed by chemical vapor deposition to form a third ruthenium oxide layer having a thickness between 0.2 micrometers and 0.5 micrometers in the second ruthenium oxide layer On the layer, finally, a layer of tantalum nitride having a thickness of between 0.2 μm and 1.2 μm is formed on the third hafnium oxide layer by chemical vapor deposition.

The fifth method for forming the protective layer 14 is to form a layer of germanium oxide having a thickness of between 0.5 μm and 2 μm by using High Density Plasma Chemical Vapor Deposition (HDP-CVD). A layer of tantalum nitride having a thickness of between 0.2 micrometers and 1.2 micrometers is formed on the tantalum oxide layer by chemical vapor deposition.

The sixth method for forming the protective layer 14 is to first form an undoped silicate glass (USG) having a thickness between 0.2 μm and 3 μm, and continue to form, for example, tetraethoxy decane, borophosphorus. An insulating layer having a thickness of between 0.5 μm and 3 μm, such as borophosphosilicate glass (BPSG) or phosphosilicate glass (PSG), on an undoped bismuth glass layer, followed by chemical vapor deposition A tantalum nitride layer having a thickness of between 0.2 micrometers and 1.2 micrometers is formed on the insulating layer.

A seventh method of fabricating the protective layer 14 is to selectively form a first layer of bismuth oxynitride having a thickness between 0.05 micrometers and 0.15 micrometers by chemical vapor deposition, and continue to form a thickness of 0.2 by chemical vapor deposition. A layer of germanium oxide between micrometers and 1.2 micrometers is on the first layer of hafnium oxynitride, and then a second layer of hafnium oxynitride having a thickness of between 0.05 micrometers and 0.15 micrometers can be selectively formed by chemical vapor deposition. On the yttrium oxide layer, chemical vapor deposition is used to form a tantalum nitride layer having a thickness between 0.2 μm and 1.2 μm on the second ruthenium oxynitride layer or on the ruthenium oxide layer, which can then be selectively utilized. Chemical vapor deposition to form a third layer of bismuth oxynitride between 0.05 micrometers and 0.15 micrometers on the tantalum nitride layer, and finally using chemical vapor deposition to form a thickness between 0.2 micrometers and 1.2 micrometers. The ruthenium oxide layer is on the third ruthenium oxynitride layer or on the tantalum nitride layer.

The eighth method for forming the protective layer 14 is to first form a first ruthenium oxide layer having a thickness of between 0.2 μm and 1.2 μm by chemical vapor deposition, and continue to form a thickness of 0.5 μm to 1 μm by spin coating. a second layer of tantalum oxide on the first layer of tantalum oxide, followed by chemical vapor deposition to form a third layer of tantalum oxide between 0.2 microns and 1.2 microns on the second layer of tantalum oxide, and then Forming a tantalum nitride layer having a thickness between 0.2 μm and 1.2 μm on the third tantalum oxide layer by chemical vapor deposition, and finally forming a thickness between 0.2 μm and 1.2 μm by chemical vapor deposition. The fourth hafnium oxide layer is on the tantalum nitride layer.

The ninth method for fabricating the protective layer 14 is to first form a first ruthenium oxide layer having a thickness of between 0.5 μm and 2 μm by high-density plasma chemical vapor deposition, and continue to form a thickness of 0.2 by chemical vapor deposition. A layer of tantalum nitride between micrometers and 1.2 micrometers is on the first tantalum oxide layer, followed by high-density plasma chemical vapor deposition to form a second layer of tantalum oxide having a thickness between 0.5 micrometers and 2 micrometers. On the tantalum nitride layer.

The tenth method for fabricating the protective layer 14 is to first form a first tantalum nitride layer having a thickness between 0.2 μm and 1.2 μm by chemical vapor deposition, and continue to form a thickness of 0.2 μm to 1.2 by chemical vapor deposition. A tantalum oxide layer between the micrometers is on the first tantalum nitride layer, followed by chemical vapor deposition to form a second tantalum nitride layer having a thickness between 0.2 micrometers and 1.2 micrometers on the tantalum oxide layer.

Further, as shown in FIG. 1, the opening 14a in the protective layer 14 exposes a bonding pad 16. Wherein, the pad 16 is used for input/output of signals, or is used for connecting a power source or a ground, etc., and the manner of forming the pads 16 includes an electroplating process or a sputtering process, for example, The sputtering process forms aluminum or aluminum alloy as the pad 16, or forms copper as a pad 16 by an electroplating process, and when the pad 16 is a copper pad formed by an electroplating process, there is one outside the bottom and side walls of the copper pad. A barrier layer, such as a barrier layer (Ta) or tantalum nitride (TaN).

The maximum lateral dimension of the opening 14a is between 5 microns and 40 microns, or between 40 microns and 300 microns. In addition, the shape of the opening 14a may be a circle, a square or a polygon of five or more sides, and the maximum lateral dimension of the opening 14a refers to the diameter dimension of the circular opening, the side length dimension of the square opening or the polygonal opening of five or more sides. The longest diagonal size. Further, the shape of the opening 14a may also be a rectangle, and the length of the rectangular opening is between 80 micrometers and 200 micrometers, and the width dimension is between 40 micrometers and 110 micrometers. Alternatively, the semiconductor element 4 may be present under the pads 16 exposed by the openings 14a or without any semiconductor elements 4.

A metal top layer (not shown) may be selectively formed over the pads 16 exposed by the openings 14a in the protective layer 14 to protect the pads 16 from oxidation and damage. The metal top layer is, for example, an aluminum layer, a gold layer, a titanium layer, a titanium tungsten alloy layer, a tantalum layer, a tantalum nitride layer or a nickel layer. For example, when the pad 16 is a Cu pad, a metal top layer (for example, an aluminum layer) is required to protect the copper pad exposed by the opening 14a, so that the copper pad is protected from oxidation and damage. When the metal top layer is an aluminum layer, a barrier layer is formed between the copper pad and the aluminum layer, and the barrier layer comprises titanium, titanium tungsten alloy, titanium nitride, tantalum, tantalum nitride. , chromium (Cr) or nickel. The following description is made only in the absence of a metal top layer, but those skilled in the art can implement it by adding a metal top layer by the following examples.

Thus, the related descriptions of the semiconductor substrate 2, the wiring structure 6, the dielectric layer 12, the protective layer 14, and the pads 16 are completed, and the respective embodiments of the present invention will be sequentially described below.

First embodiment:

2A to 2H are schematic cross-sectional views showing a process for forming a tin-containing metal layer and a metal pad on a wafer or wafer.

Referring to FIG. 2A, the pad 16 includes a first pad 16a and a second pad 16b, and is formed to have a thickness between 0.01 micrometers and 3 micrometers (preferably, the thickness is between 0.01 micrometers and 1 micrometer). An adhesion/barrier layer 18 is on the protective layer 14 and the first pads 16a and the second pads 16b exposed by the openings 14a. The material of the adhesion/barrier layer 18 is selected from the group consisting of titanium, tungsten, cobalt, nickel, titanium nitride, titanium tungsten alloy, nickel vanadium alloy, tantalum, tantalum nitride, chromium, copper, chromium copper alloy, gold, tantalum, At least one of platinum, palladium, rhodium, iridium, and silver, or at least one of the group consisting of, for example, by sputtering or evaporation.

Next, a seed layer 20 having a thickness of between 0.005 micrometers and 2 micrometers (preferably having a thickness between 0.1 micrometers and 0.7 micrometers) is formed on the adhesion/barrier layer 18 to form a seed layer. The method of 20 is, for example, sputtering, evaporation, physical vapor deposition, electroplating or electroless plating. This seed layer 20 facilitates the placement of subsequent metal lines, so the material of the seed layer 20 will vary with the material of the subsequent metal lines. For example, when the seed layer 20 is plated to form a metal layer of copper, the material of the seed layer 20 is preferably copper; when the seed layer 20 is plated with a metal layer of gold, the material of the seed layer 20 is made of gold. Preferably, when the seed layer 20 is plated to form a metal layer of palladium material, the material of the seed layer 20 is preferably palladium; when the seed layer 20 is plated to form a metal layer of platinum material, the material of the seed layer 20 is made of platinum. Preferably, when the seed layer 20 is plated to form a metal layer of tantalum material, the material of the seed layer 20 is preferably ruthenium; when the seed layer 20 is plated to form a metal layer of tantalum material, the material of the seed layer 20 is preferably 钌. When the seed layer 20 is plated to form a metal layer of tantalum material, the material of the seed layer 20 is preferably 铼; when the seed layer 20 is plated with a metal layer of nickel, the material of the seed layer 20 is preferably nickel. .

Referring to FIG. 2B, a photoresist layer 22 is formed on the seed layer 20, and the photoresist layer 22 is patterned by an exposure and development process to form a photoresist layer opening 22a in the photoresist layer. The seed layer 20 located above the first pad 16a is exposed and formed in the process of forming the photoresist layer opening 22a, for example, by one-time (1X) steppers or scanners. exposure. Further, a metal layer 24 having a thickness between 1 micrometer and 200 micrometers (for example, between 1 micrometer and 50 micrometers) is formed on the seed layer 20 exposed by the photoresist layer opening 22a, and the metal layer 24 is formed. The preferred thickness is between 2 microns and 30 microns, and the metal layer 24 is formed by electroplating or electroless plating. Alternatively, the metal layer 24 may be a single metal layer structure of gold, copper, silver, palladium, platinum, rhodium, ruthenium, iridium or nickel, or a composite layer composed of the above metal materials. For example, the metal layer 24 may be a gold layer formed by electroplating having a thickness of between 8 micrometers and 35 micrometers or a copper layer formed by electroplating having a thickness of between 8 micrometers and 35 micrometers. Further, the metal layer 24 is formed by, for example, plating a copper layer having a thickness of between 8 μm and 35 μm on the seed layer 20 of, for example, copper, and then plating the thickness between 0.1 μm and 10 μm ( a nickel layer having a preferred thickness between 0.1 micrometers and 5 micrometers is on the copper layer, and the final plating thickness is between 0.01 micrometers and 10 micrometers (preferably, the thickness is between 0.1 micrometers and 2 micrometers). A gold layer is on the nickel layer.

Referring to FIG. 2C, after the metal layer 24 is formed, the photoresist layer 22 is subsequently removed. Continuing, the seed layer 20 and the adhesion/barrier layer 18 that are not under the metal layer 24 are removed. The manner of removing the adhesion/barrier layer 18 can be divided into dry etching and wet etching, and dry etching is performed by using high-pressure argon gas for sputtering etching, and in wet etching, if it is adhered. When the barrier layer 18 is a titanium or titanium tungsten alloy, it can be removed using hydrogen peroxide. Further, when the seed layer 20 is gold, it can be removed by using an iodine-containing etching solution (for example, an etching solution such as potassium iodide).

Therefore, a metal pad 26 is formed on a first pad 16a exposed by the opening 14a of the protective layer 14. The metal pad 26 is formed by an adhesive/barrier layer 18, which is located in the adhesion/barrier layer. A sub-layer 20 on the 18 is formed with a metal layer 24 on the seed layer 20, and the metal pad 26 can be bonded to a wire conductor (such as a gold wire or a copper wire) through a wire bonding process, and automatically bonded by a tape. The technique is to bond a metal bump (such as a gold bump) to an external circuit, a tin-containing metal layer bonded to an external circuit, or an external circuit through an anisotropic conductive paste, wherein the external circuit can be a semiconductor wafer, a printed circuit board (PCB) containing glass fibers, a soft board containing a polymer layer (for example, polyimide) having a thickness of between 30 micrometers and 200 micrometers, and a substrate containing a ceramic material , a glass substrate or a previously formed passive passive device.

Taking the metal layer 24 as a gold layer as an example, when the metal pad 26 is used to bond a wire conductor (such as a gold wire), the preferred thickness of the gold layer is between 2 micrometers and 10 micrometers, and when the metal is When the pad 26 is used to bond a tape, the preferred thickness of the gold layer is between 10 microns and 30 microns.

Forming a metal pad 26 for bonding a wire bonding wire, bonding a tape, bonding an external circuit, bonding a tin-containing metal layer of an external circuit, or bonding an external circuit through an anisotropic conductive paste, and then forming A tin-containing metal layer 36 is over the second pads 16b. Referring to FIG. 2D, an adhesion/barrier layer 28 having a thickness between 0.01 micrometers and 3 micrometers (preferably having a thickness between 0.01 micrometers and 1 micrometer) is formed on the protective layer 14 at the opening. 14a is exposed on the second pad 16b and on the metal pad 26. The material of the adhesion/barrier layer 28 is selected from the group consisting of titanium, tungsten, cobalt, nickel, titanium nitride, titanium tungsten alloy, nickel vanadium alloy, tantalum, tantalum nitride, chromium, copper, chromium copper alloy, gold, tantalum, At least one of platinum, palladium, rhodium, iridium, and silver, or at least one of the group consisting of, for example, by sputtering or evaporation.

Further, a sub-layer 30 having a thickness of between 0.005 micrometers and 2 micrometers (preferably having a thickness between 0.1 micrometers and 0.7 micrometers) is formed on the adhesion/barrier layer 28 to form the seed layer 30. Such as sputtering, evaporation, physical vapor deposition, electroplating or electroless plating. This seed layer 30 facilitates the placement of subsequent metal lines, so the material of the seed layer 30 will vary with the material of the subsequent metal lines. For example, when the seed layer 30 is plated to form a metal layer of copper, the material of the seed layer 30 is preferably copper; when the seed layer 30 is plated with a metal layer of gold, the material of the seed layer 30 is made of gold. good.

Continuing, a photoresist layer 32 is formed on the seed layer 30, and the photoresist layer 32 is patterned through the exposure and development process to form the photoresist layer opening 32a in the photoresist layer 32 and exposed to the second pad 16b. The upper seed layer 30 is exposed during the process of forming the photoresist layer opening 32a, for example, by a double exposure machine or scanner. Then, referring to FIG. 2E, a diffusion barrier layer 34 is formed on the seed layer 30 exposed by the photoresist layer opening 32a, and the diffusion barrier layer 34 is formed by, for example, borrowing. A layer of copper having a plating thickness between 0.5 microns and 10 microns is on the seed layer 30, such as copper, followed by electroplating a layer of nickel between 0.1 microns and 5 microns on the copper layer. Therefore, the diffusion barrier layer 34 may be composed of a copper layer and a nickel layer on the copper layer.

Next, a tin-containing metal layer 36 having a thickness of between 1 micrometer and 500 micrometers is formed on the diffusion barrier layer 34 in the photoresist layer opening 32a. The preferred thickness of the tin-containing metal layer 36 is between 3. The micron to 250 micron, and the formation of the tin-containing metal layer 36 is, for example, electroplated, electroless plating or screen printing. In addition, the tin-containing metal layer 36 is, for example, a tin-lead alloy, a tin-silver alloy, a tin-silver-copper alloy or a lead-free alloy. ). Taking tin-lead alloy as an example, the tin/lead ratio can be adjusted according to the demand. The common tin-lead ratio is 90/10, 95/5, 97/3, 99/1, 37/63, etc.

As can be seen from the above, the diffusion barrier layer 34 is under the tin-containing metal layer 36. The diffusion barrier layer 34 includes, for example, a nickel layer having a thickness between 0.1 μm and 5 μm under the tin-containing metal layer 36. And a copper layer having a thickness between 0.5 micrometers and 10 micrometers is under the nickel layer, and the nickel layer and the copper layer are tied above the second pads 16b.

In addition, in this embodiment, a solder wettable layer (not shown) may be further formed on the diffusion barrier layer 34 to enhance the adhesion between the subsequent tin-containing metal layer 36 and the diffusion barrier layer 34. Bonding property of the solder-impregnated film layer is gold, copper, tin, tin-lead alloy, tin-silver alloy, tin-silver-copper alloy or lead-free alloy.

Referring to FIG. 2F, after the tin-containing metal layer 36 is formed, the photoresist layer 32 is subsequently removed. Continuing, the seed layer 30 and the adhesion/barrier layer 28 that are not under the tin-containing metal layer 36 are removed. The method of removing the adhesion/barrier layer 28 can be divided into dry etching and wet etching, and dry etching is performed by using high-pressure argon gas for sputtering etching, and in wet etching, if the adhesion/barrier layer 28 is titanium or In the case of titanium tungsten alloy, it can be removed using hydrogen peroxide.

Referring to FIG. 2G, a reflow process is selectively performed to cause the tin-containing metal layer 36 to reach a melting point and cohere into a spherical shape. However, in this embodiment, the reflow process may be performed first, so that the tin-containing metal layer 36 reaches the melting point and is internally spherical, and then the seed layer 30 and the adhesion/barrier layer 28 not under the tin-containing metal layer 36 are removed. Alternatively, in this embodiment, the reflow process may not be performed until the tin-containing metal layer 36 is connected to an external circuit, such as a semiconductor wafer, a printed circuit board containing glass fibers, and a thickness. A soft plate having a polymer layer between 30 micrometers and 200 micrometers, a substrate containing a ceramic material, or a passive component formed in advance.

Therefore, the present invention can be formed on the pads 16 exposed by the partial openings 14a of the protective layer 14 for bonding wire bonding wires (such as gold wires or copper wires), for bonding tapes, for bonding an external circuit. a metal bump, a tin-containing metal layer for bonding an external circuit, or a metal pad 26 for bonding an external circuit through an anisotropic conductive paste, and a tin-containing metal layer is formed over the pad 16 where the metal pad 26 is not formed. 36. Alternatively, the top of the metal pad 26 may include a wettable layer (not shown) for bonding the wire bonding wires, such as a gold layer. Further, before the formation of the tin-containing metal layer 36, a gold layer may be formed on the diffusion barrier layer 34, and then the tin-containing metal layer 36 may be formed on the gold layer. Further, the tin-containing metal layer in the present invention may also be replaced by a solder bump.

Referring to FIG. 2H, after the above process is completed, the semiconductor substrate 2 can be subsequently cut to form a plurality of semiconductor wafers 38, wherein each semiconductor wafer 38 includes a semiconductor substrate 2, a wiring structure 6, and a plurality of dielectric layers. 12. A protective layer 14, at least one metal pad 26 and at least one tin-containing metal layer 36, and the like. In addition, a plurality of semiconductor elements 4 (eg, transistors or metal oxide semiconductors, etc.) are located in or above the semiconductor substrate 2, and one of the semiconductor elements 4 is selectively positioned on the metal pad 26 or the tin-containing metal layer 36. In the lower part, two of the semiconductor elements 4 are electrically connected to the metal pad 26 and the tin-containing metal layer 36, respectively. Further, in each of the semiconductor wafers 38, the top of the protective layer 14 may be an oxysulfide compound layer or a ruthenium nitride compound layer.

Each of the semiconductor wafers 38 may be connected to an external circuit through the tin-containing metal layer 36. The external circuit may be a semiconductor wafer, a printed circuit board (PCB), a flexible board, a substrate containing a ceramic material, or a passive formed in advance. A discrete passive device in which a printed circuit board contains glass fibers, and the soft board comprises a polymer layer having a thickness of between 30 micrometers and 200 micrometers, such as a polyimide.

In addition, through a wire bonding process, a metal pad 26 of a semiconductor wafer 38 can be bonded to a wire (for example, a gold wire or a copper wire) to be connected to an external circuit. The external circuit can be a semiconductor chip or a printed circuit. a board, a flexible board, a substrate or a lead frame containing a ceramic material, wherein the printed circuit board contains glass fibers, and the soft board comprises a polymer layer having a thickness of between 30 micrometers and 200 micrometers, such as a polymer layer Imine.

Furthermore, by means of tape bonding, a metal pad 26 of a semiconductor wafer 38 can be bonded to a tape, which in turn can be connected to an external circuit, which can be a semiconductor wafer, a printed circuit board, a flexible board or A substrate comprising a ceramic material, wherein the printed circuit board contains glass fibers, and the soft board comprises a polymer layer having a thickness of between 30 micrometers and 200 micrometers, such as a polyimide. Additionally, the tape has at least one metal line and at least one polymer layer, and the metal lines connect the metal pads 26, such as metal pads 26 via tin metal or tin-silver alloy.

Moreover, through the thermocompression bonding process, one of the semiconductor pads 38 can be pressed into an anisotropic conductive film (ACF or anisotropic conductive paste (ACP) to make the anisotropic conductive. The metal particles in the glue are accumulated between the metal pad 26 and a pad of an external circuit (such as a glass substrate) containing indium tin oxide, thereby electrically connecting the metal pad 26 and the external circuit containing indium tin oxide. The mat of the object. Alternatively, the external circuit may be a semiconductor wafer, a printed circuit board, a flexible board containing a polymer layer having a thickness of between 30 micrometers and 200 micrometers, or a substrate containing a ceramic material.

Moreover, one of the metal pads 38 of the semiconductor wafer 38 can be bonded to a metal bump (for example, a gold bump) to be connected to an external circuit. The external circuit can be a semiconductor wafer, a printed circuit board, a glass substrate, a flexible board, or A substrate of ceramic material, wherein the printed circuit board contains glass fibers, and the soft board comprises a polymer layer having a thickness of between 30 micrometers and 200 micrometers, such as a polyimide.

In this embodiment, before the semiconductor substrate 2 is cut, an external circuit is first connected through the tin-containing metal layer 36. The external circuit may be a semiconductor wafer, a printed circuit board, a flexible board, a substrate containing a ceramic material, or a passive component formed in advance. Where the printed circuit board contains glass fibers, and the soft board comprises a polymer layer having a thickness between 30 microns and 200 microns, such as a polyimide. Next, the semiconductor substrate 2 is diced to form a plurality of semiconductor wafers. Finally, the present embodiment can bond a wire bonding wire (using a wire bonding process), a bonding tape (using tape bonding automatic bonding technology), and a metal bump (such as a gold bump) bonded to an external circuit on the metal pad 26 of each semiconductor wafer. Block), bonding a tin-containing metal layer of an external circuit or bonding an external circuit through an anisotropic conductive paste.

Referring to FIG. 2I, in this embodiment, a polymer layer 39 may be formed on the protective layer 14, and the polymer layer opening 39a and the polymer layer opening 39b located in the polymer layer 39 are respectively exposed. a pad 16a and a second pad 16b, and then forming a metal pad 26 on the first pad 16a exposed by the polymer layer opening 39a, and forming according to the process steps described in FIGS. 2A to 2G The tin-containing metal layer 36 is above the second pad 16b exposed by the polymer layer opening 39b. For details, please refer to the above description, which will not be described in detail herein. Wherein, the polymer layer 39 is selected from the group consisting of polyiminoimine, phenylcyclobutene, polyurethane, epoxy resin, parylene polymer, solder mask material, elastic material or porous dielectric material. First, the method of forming the polymer layer 39 may be performed by a hot press dry film method or a screen printing method in addition to the spin coating method, and the thickness of the other polymer layer 39 is between 1 μm and 30 μm. Please refer to the above for the related application of the semiconductor wafer 38' shown in Fig. 2I, and will not be described here.

Second embodiment:

The present invention can also be applied to a re-distribution layer (RDL) or an interconnecting trace, and a reconfiguration line and a connection line are simultaneously formed on the semiconductor substrate as an embodiment. For the purpose of illustration, the present invention can also form only a reconfiguration line or a connection line above the semiconductor substrate by the following method, thereby forming a metal pad and a tin-containing metal layer on the reconfiguration line or the connection line.

Referring to FIG. 3C, the metal line 40 as the reconfiguration line and the metal line 42 as the connection line are respectively formed above the protective layer 44 and exposed to the opening 44a located in the protective layer 44, respectively. The pads 46 are connected, and the materials and structures of the protective layer 44 and the pads 46 are described. Please refer to the descriptions of the protective layer 14 and the pads 16 respectively, and will not be described in detail herein.

In addition, the maximum lateral dimension of the opening 44a in the protective layer 44 may be the same as the maximum lateral dimension of the opening 14a in the protective layer 14, or less than the maximum lateral dimension of the opening 14a in the protective layer 14. For example, the opening 44a may have a maximum lateral dimension of between 0.05 micrometers and 25 micrometers, preferably a size of between 1 micrometer and 15 micrometers, and the opening 44a may be circular, square, rectangular or five-sided. The above polygonal shape, and the maximum lateral dimension of the opening 44a refers to the diameter dimension of the circular opening, the side length dimension of the square opening, the longest side length dimension of the rectangular opening, or the longest diagonal dimension of the polygonal opening of five or more sides. Further, the semiconductor element 4 may be disposed under the pad 46 exposed by the opening 44a, or any semiconductor element 4 may not be disposed.

Referring to FIG. 3A, which is a cross-sectional view of the fabrication of the reconfiguration line and the connection line, as shown, a polymer layer 48 is formed on the protective layer 44 and the polymer is located in the polymer layer 48. The layer openings 48a, 48b expose the pads 46 exposed by the openings 44a, wherein the polymer layer 48 is selected from the group consisting of polyimine, phenylcyclobutene, polyurethane, epoxy, parylene One of a polymer, a welding cap material, an elastic material or a porous dielectric material, and the method of forming the polymer layer 48 may be by a hot press dry film method or a screen printing method, in addition to the spin coating method. Polymer layer 48 has a thickness between 1 micron and 30 microns.

Next, metal lines 40, 42 are formed over polymer layer 48 and joined to pads 46 exposed by polymer layer openings 48a, 48b. The method of forming the metal lines 40, 42 is described as follows: [Step 1] forming an adhesion/barrier forming a thickness between 0.01 micrometers and 3 micrometers (preferably, the thickness is between 0.01 micrometers and 1 micrometer). Layer 52 is on polymer layer 48 on pads 46 exposed by polymer layer openings 48a, 48b. The material of the adhesion/barrier layer 52 is selected from the group consisting of titanium, tungsten, cobalt, nickel, titanium nitride, titanium tungsten alloy, nickel vanadium alloy, tantalum, tantalum nitride, chromium, copper, chromium copper alloy, gold, tantalum, At least one of platinum, palladium, rhodium, iridium, and silver, or at least one of the group consisting of, for example, by sputtering or evaporation.

[Step 2] Forming a sub-layer 54 having a thickness between 0.005 micrometers and 2 micrometers (preferably having a thickness between 0.1 micrometers and 0.7 micrometers) on the adhesion/barrier layer 52 to form the seed layer 30 The method is, for example, sputtering, evaporation, physical vapor deposition, electroplating or electroless plating. This seed layer 54 facilitates the placement of subsequent metal lines, so the material of the seed layer 54 will vary with the material of the subsequent metal lines. For example, when the seed layer 54 is plated to form a metal layer of copper, the material of the seed layer 54 is preferably copper; when the seed layer 54 is plated with a metal layer of gold, the material of the seed layer 54 is made of gold. good.

[Step 3] Forming a photoresist layer 56 on the seed layer 54 and then patterning the photoresist layer 56 through the exposure and development process to form the photoresist layer opening 56a in the photoresist layer 56 and exposing the seed layer 54. In the process of forming the photoresist layer opening 56a, for example, exposure is performed by a double exposure machine or a scanner.

[Step 4] Forming a metal layer 58 having a thickness of between 1 micrometer and 50 micrometers on the seed layer 54 exposed by the photoresist layer opening 56a. The preferred thickness of the metal layer 58 is between 1 micrometer and 35 degrees. Between the micrometers, the manner in which the metal layer 58 is formed is, for example, electroplating or electroless plating. Alternatively, the metal layer 58 may be a single metal layer structure of gold, copper, silver, palladium, platinum, rhodium, ruthenium, iridium or nickel, or a composite layer composed of the above metal materials.

For example, the metal layer 58 may be formed by electroplating with a thickness of between 1 micrometer and 35 micrometers (preferably between 2 micrometers and 12 micrometers) or formed by electroplating. A copper layer having a thickness between 1 micrometer and 35 micrometers (preferably between 2 micrometers and 20 micrometers thick). Further, the metal layer 58 is formed by, for example, plating a copper layer having a thickness of between 2 μm and 20 μm on a seed layer 54 of, for example, copper, followed by a plating thickness of between 0.1 μm and 10 μm ( a nickel layer having a preferred thickness between 0.5 microns and 5 microns is on the copper layer, and the final plating thickness is between 0.01 microns and 5 microns (preferably between 0.01 microns and 1 micron) A gold layer is on the nickel layer.

[Step 5] After the metal layer 58 is formed, the photoresist layer 56 is subsequently removed. Continuing, the seed layer 54 and the adhesion/barrier layer 52 that are not under the metal layer 58 are removed, as shown in FIG. 3B. The method of removing the adhesion/barrier layer 52 can be divided into dry etching and wet etching, such as sputtering etching using high-pressure argon gas, and in the wet etching, if the adhesion/barrier layer 52 is titanium or titanium. In the case of a tungsten alloy, it can be removed using hydrogen peroxide. Further, when the seed layer 54 is gold, it can be removed by using an iodine-containing etching solution (for example, an etching solution such as potassium iodide).

Referring to FIG. 3C, after forming the metal lines 40, 42, a polymer layer 60 is formed on the metal lines 40, 42 and the polymer layer 48, and the polymer layer is located in the polymer layer 60. The opening 60a exposes the metal lines 40, 42, wherein the polymer layer 60 is selected from the group consisting of polyimide, phenylcyclobutene, polyurethane, epoxy resin, parylene polymer, solder mask material, One of the elastic material or the porous dielectric material, and the method of forming the polymer layer 60 may be by hot pressing dry film or screen printing, and the thickness of the polymer layer 60, in addition to the spin coating method. Between 1 micron and 30 microns.

Finally, a method of forming a tin-containing metal layer 36 and a metal pad 26 in accordance with the first embodiment is described. In this embodiment, a tin-containing metal layer 36 is formed on the metal lines 40, 42 exposed by the polymer layer opening 60a. a metal bump (such as a gold bump) for bonding a wire conductor, a bonding tape, an external circuit, a tin-containing metal layer bonded to an external circuit, or a metal bonded to an external circuit through an anisotropic conductive paste The pads 26, and for the description of this portion, please refer to the related description of the first embodiment, which will not be described in detail herein.

Referring to FIG. 3D, after the above process is completed, the semiconductor substrate 2 can be subsequently cut to form a plurality of semiconductor wafers 62, wherein each semiconductor wafer 62 includes a semiconductor substrate 2, a wiring structure 6, and a plurality of dielectric layers. 12. A protective layer 14, at least one reconfiguration line (such as metal line 40), at least one connection line (such as metal line 42), at least one metal pad 26 and at least one tin-containing metal layer 36, and the like. In addition, a plurality of semiconductor elements 4 (eg, transistors or metal oxide semiconductors, etc.) are located in or above the semiconductor substrate 2, and one of the semiconductor elements 4 is selectively positioned on the metal pad 26 or the tin-containing metal layer 36. In the lower part, two of the semiconductor elements 4 are electrically connected to the metal pad 26 and the tin-containing metal layer 36, respectively. Further, in each of the semiconductor wafers 62, the top of the protective layer 14 may be an oxysulfide compound layer or a ruthenium nitride compound layer.

Each of the semiconductor wafers 62 can be connected to an external circuit through the tin-containing metal layer 36. The external circuit can be a semiconductor wafer, a printed circuit board, a flexible board, a substrate containing a ceramic material, or a passive component formed in advance, wherein the printed circuit board contains Glass fiber, and the soft board comprises a polymer layer having a thickness of between 30 micrometers and 200 micrometers, such as a polyimide.

In addition, through the wire bonding process, one of the metal pads 62 of the semiconductor wafer 62 can be bonded to a wire (for example, a gold wire or a copper wire) to be connected to an external circuit. The external circuit can be a semiconductor chip, a printed circuit board, or a flexible board. A substrate or lead frame containing a ceramic material, wherein the printed circuit board contains glass fibers, and the soft board comprises a polymer layer having a thickness of between 30 micrometers and 200 micrometers, such as a polyimide.

Moreover, by means of tape bonding technology, the metal pads 26 of a semiconductor wafer 62 can be bonded to a tape, which is connected to an external circuit, which can be a semiconductor wafer, a printed circuit board, a flexible board or a ceramic material. The substrate, wherein the printed circuit board contains glass fibers, and the soft board comprises a polymer layer having a thickness of between 30 micrometers and 200 micrometers, such as a polyimide. Additionally, the tape has at least one metal line and at least one polymer layer, and the metal lines connect the metal pads 26, such as metal pads 26 via tin metal or tin-silver alloy.

Moreover, through the thermocompression bonding process, one of the metal pads 62 of the semiconductor wafer 62 can be pressed into the anisotropic conductive paste, and the metal particles located in the anisotropic conductive paste are collected on the metal pads 26 and An indium tin oxide-containing pad is formed between an external circuit (for example, a glass substrate) and a pad containing indium tin oxide electrically connected to the metal pad 26. Further, the external circuit is, for example, a semiconductor wafer, a printed circuit board, a flexible board containing a polymer layer having a thickness of between 30 μm and 200 μm, or a substrate containing a ceramic material.

Moreover, one of the metal pads 62 of the semiconductor wafer 62 can be bonded to a metal bump (for example, a gold bump) to be connected to an external circuit. The external circuit can be a semiconductor wafer, a printed circuit board, a glass substrate, a flexible board, or A substrate of ceramic material, wherein the printed circuit board contains glass fibers, and the soft board comprises a polymer layer having a thickness of between 30 micrometers and 200 micrometers, such as a polyimide.

In this embodiment, before the semiconductor substrate 2 is cut, an external circuit is first connected through the tin-containing metal layer 36. The external circuit may be a semiconductor wafer, a printed circuit board, a flexible board, a substrate containing a ceramic material, or a passive component formed in advance. Where the printed circuit board contains glass fibers, and the soft board comprises a polymer layer having a thickness between 30 microns and 200 microns, such as a polyimide. Next, the semiconductor substrate 2 is diced to form a plurality of semiconductor wafers. Thereafter, the present embodiment can bond a wire bonding wire (using a wire bonding process), a bonding tape (using tape bonding automatic bonding technology), and a metal bump (such as a gold bump) bonded to an external circuit on the metal pad 26 of each semiconductor wafer. Block) bonding a tin-containing metal layer of an external circuit or bonding an external circuit through an anisotropic conductive paste.

By reconfiguring the wiring (e.g., metal line 40 in FIG. 3C), the present embodiment can relocate the location of the pads 46 previously exposed by the opening 44a to a particular location (eg, to the polymer layer opening 60a). The position of the exposed metal line 40), which may be different from the position of the pad 46, as viewed from a top perspective view. Moreover, this embodiment allows the at least two pads 46 exposed by the opening 44a to be joined together through a connection line (e.g., the metal line 42 in FIG. 3C).

In addition, as shown in FIG. 3E, in this embodiment, the metal lines 40 and 42 may be formed directly on the protective layer 14, and further in the polymer layer opening 60a according to the process steps described in FIGS. 3C to 3D. The tin-containing metal layer 36 and the metal pad 26 are formed on the exposed metal lines 40 and 42. For the details of this part, please refer to the above related description, which will not be described in detail herein. The metal pad 26 includes the metal layer 24, the seed layer 20, and the adhesion/barrier layer 18. The metal layer 24, the seed layer 20, and/or the adhesion/barrier layer 18 can be positioned straight and vertically above the at least one pad 46. For example, FIG. 3E shows that the metal layer 24, the seed layer 20, and/or the adhesion/barrier layer 18 are all located straight on at least two pads 46 and 46. Further, the related application of the semiconductor wafer 62' shown in Fig. 3E is also referred to above, and will not be described here.

Therefore, the present invention can form a metal bump for bonding a wire conductor (such as a gold wire or a copper wire), a bonding tape, and an external circuit for bonding on a re-arrangement line or a connection line of a wafer or a wafer. a block (such as a gold bump), a tin-containing metal layer for bonding an external circuit, or a metal pad that is bonded to an external circuit through an anisotropic conductive paste, and a tin-containing metal formed over the pad where the metal pad is not formed Floor.

In addition, the metal lines 40, 42 may also be a line including a power bus, a signal bus, or a ground bus, which may be opened through the opening of the protective layer 44. 44a is connected to a power line, a signal line, or a ground line under the protective layer 44.

Referring to FIG. 4, it is a schematic cross-sectional view of a multi-chip package structure. As shown, the semiconductor wafer 64 may be a semiconductor wafer 38 or a semiconductor wafer 38' formed in the first embodiment manner, or The semiconductor wafer 62 or semiconductor wafer 62' is formed in a second embodiment, so the semiconductor wafer 64 has two different types of metal pads 68 and 70. The metal pad 68 includes a tin-containing metal layer 36 and a plurality of metal layers (such as the adhesion/barrier layer 28, the seed layer 30 and the diffusion barrier layer 34) located under the tin-containing metal layer 36, and the related tin-containing For a description of the metal layer 36 and these metal layers, please refer to the above. In addition, the metal pad 70 is used to bond the tape. The metal pad 70 can be the metal pad 26 in the first embodiment or the second embodiment. Please refer to the above for related description.

As shown, semiconductor wafer 64 is coupled to semiconductor wafer 66 via metal pads 68. In addition, a polymer 72 is filled between the two semiconductor wafers 64 and 66 and covers the metal pads 68, wherein the polymer 72 is selected from the group consisting of polyimine, phenylcyclobutene, polyurethane, epoxy resin. One of a polyparaxylene polymer, a solder mask material, an elastic material or a porous dielectric material.

In addition, through the thermocompression bonding process, a flexible tape 78 having at least one metal line 74 and a polymer layer 76 is connected to the metal pad 70 through the metal line 74, and the metal line 74 of the soft tape 78 is, for example, The metal pad 70 is bonded via a metal layer 79 (eg, tin metal or tin-silver alloy), wherein the polymer layer 76 is selected from the group consisting of polyimine, phenylcyclobutene, polyurethane, epoxy, and poly. One of a toluene polymer, a welding cap material, an elastic material or a porous dielectric material.

In addition, a polymer 80 covers the metal pad 70 and a portion of the soft tape 78, wherein the polymer 80 is selected from the group consisting of polyimine, phenylcyclobutene, polyurethane, epoxy resin, and parylene. One of a polymer, a welding cap material, an elastic material or a porous dielectric material.

Therefore, the semiconductor wafer 64 is connected to an external circuit through the metal pad 68 (for example, the semiconductor wafer 66, a printed circuit board containing glass fibers, a soft board containing a polymer layer having a thickness of between 30 micrometers and 200 micrometers, or containing ceramics). The substrate of the material), and by the automatic bonding technique of the tape, the metal pad 70 is connected to an external circuit via a flexible tape 78 (for example, a semiconductor wafer, a printed circuit board containing glass fibers, and having a thickness between 30 micrometers and 200 micrometers). A soft layer of a polymer layer or a substrate containing a ceramic material).

Third embodiment:

5A to 5H are schematic cross-sectional views showing a process for forming a tin-containing metal layer and a metal pad on a wafer or wafer in the present embodiment.

After the process of forming the adhesion/barrier layer 18 described in FIG. 2A, then as shown in FIG. 5A, the thickness is formed between 0.005 micrometers and 10 micrometers (preferably, the thickness is between 0.1 micrometers and 2 micrometers). A sub-layer 20' between the micrometers is on the adhesion/barrier layer 18, and the seed layer 20' is formed by means of sputtering, evaporation, physical vapor deposition, electroplating or electroless plating. This seed layer 20' facilitates the subsequent metal bond arrangement, so the material of the seed layer 20' will vary with the metal material that needs to be joined later. For example, when the seed layer 20' needs to be joined with copper metal, the material of the seed layer 20' is preferably copper; when the seed layer 20' needs to be joined with a metal of gold material, the material of the seed layer 20' is preferably gold.

Then, a photoresist layer 82 is formed on the seed layer 20', and the photoresist layer 82 is patterned through the exposure and development process to form the photoresist layer 82a on the seed layer 20' above the first pad 16a, such as As shown in Fig. 5B, in the process of forming the photoresist layer 82a, for example, exposure is performed by a double exposure machine or a scanner. Continuing, the photoresist layer 82a is used as a mask to remove the seed layer 20' and the adhesion/barrier layer 18 which are not under the photoresist layer 82a. The method of removing the adhesion/barrier layer 18 can be divided into dry etching and wet etching, and dry etching is performed by using high-pressure argon gas for sputtering etching, and in wet etching, if the adhesion/barrier layer 18 is titanium or In the case of titanium tungsten alloy, it can be removed using hydrogen peroxide. Further, when the seed layer 20' is gold, it can be removed by using an iodine-containing etching solution (for example, an etching solution such as potassium iodide). Next, after the seed layer 20' and the adhesion/barrier layer 18 are removed, the photoresist layer 82a is removed as shown in Fig. 5C.

Therefore, a metal pad 84 is formed on a first pad 16a exposed by the opening 14a of the protective layer 14. The metal pad 84 is formed by an adhesive/barrier layer 18 and is positioned on the adhesion/barrier layer. A sub-layer 20' is formed on the 18, and the metal pad 84 can be bonded to a wire conductor (such as a gold wire or a copper wire) through a wire bonding process, and a tape is bonded by an automatic bonding technique to engage an external circuit. A metal bump (such as a gold bump), a tin-containing metal layer bonded to an external circuit, or an external circuit through an anisotropic conductive paste. Moreover, taking the seed layer 20' as a gold layer as an example, when the metal pad 84 is bonded to a wire conductor (for example, a gold wire), the thickness of the gold layer is between 0.05 micrometers and 5 micrometers (preferably, the thickness is Between 0.1 microns and 2 microns). In addition, taking the seed layer 20' as a copper layer as an example, when the metal pad 84 is bonded to a wire (for example, a copper wire), the thickness of the copper layer is between 0.05 micrometers and 5 micrometers (preferably, the thickness is Between 0.1 microns and 2 microns).

Referring to FIG. 5D, an adhesion/barrier layer 28 having a thickness between 0.01 micrometers and 3 micrometers (preferably having a thickness between 0.01 micrometers and 1 micrometer) is formed on the protective layer 14 at the opening. 14a is exposed on the second pad 16b and on the metal pad 84. The material of the adhesion/barrier layer 28 is selected from the group consisting of titanium, tungsten, cobalt, nickel, titanium nitride, titanium tungsten alloy, nickel vanadium alloy, tantalum, tantalum nitride, chromium, copper, chromium copper alloy, gold, tantalum, At least one of platinum, palladium, rhodium, iridium, and silver, or at least one of the group consisting of, for example, by sputtering or evaporation.

Further, a sub-layer 30 having a thickness of between 0.005 micrometers and 2 micrometers (preferably having a thickness between 0.1 micrometers and 0.7 micrometers) is formed on the adhesion/barrier layer 28 to form the seed layer 30. Such as sputtering, evaporation, physical vapor deposition, electroplating or electroless plating. This seed layer 30 facilitates the placement of subsequent metal lines, so the material of the seed layer 30 will vary with the material of the subsequent metal lines. For example, when the seed layer 30 is plated to form a metal layer of copper, the material of the seed layer 30 is preferably copper; when the seed layer 30 is plated with a metal layer of gold, the material of the seed layer 30 is made of gold. good.

Continuing, a photoresist layer 32 is formed on the seed layer 30, and the photoresist layer 32 is patterned through the exposure and development process to form the photoresist layer opening 32a in the photoresist layer 32 and exposed to the second pad 16b. The upper seed layer 30 is exposed during the process of forming the photoresist layer opening 32a, for example, by a double exposure machine or scanner.

Next, referring to FIG. 5E, a diffusion barrier layer 34 is formed on the seed layer 30 exposed by the photoresist layer opening 32a, and the diffusion barrier layer 34 is formed by, for example, plating thickness of 0.5. A copper layer between microns and 10 microns is on the seed layer 30, such as copper, and a nickel layer having a thickness between 0.1 microns and 5 microns is finally plated over the copper layer. Therefore, the diffusion barrier layer 34 may be composed of a copper layer and a nickel layer on the copper layer.

Then, a tin-containing metal layer 36 having a thickness between 1 micrometer and 500 micrometers is formed on the diffusion barrier layer 34 in the photoresist layer opening 32a. The preferred thickness of the tin-containing metal layer 36 is 3 The micron to 250 micron, and the formation of the tin-containing metal layer 36 is, for example, electroplated, electroless plating or screen printing. In addition, the tin-containing metal layer 36 is, for example, a tin-lead alloy, a tin-silver alloy, a tin-silver-copper alloy, or a lead-free alloy. Taking tin-lead alloy as an example, the tin/lead ratio can be adjusted according to the demand. The common tin-lead ratio is 90/10, 95/5, 97/3, 99/1, 37/63, etc.

As can be seen from the above, the diffusion barrier layer 34 is under the tin-containing metal layer 36, and the diffusion barrier layer 34 includes, for example, a nickel layer having a thickness between 0.1 μm and 5 μm under the tin-containing metal layer 36, and A copper layer having a thickness between 0.5 microns and 10 microns is below the nickel layer, and the nickel layer and the copper layer are tied above the second pads 16b.

In addition, in this embodiment, a solder adhesion film layer (not shown) may be further formed on the diffusion barrier layer 34 to improve the bonding between the subsequent tin-containing metal layer 36 and the diffusion barrier layer 34. The material of the solder adhesion film layer is, for example, gold, copper, tin, tin-lead alloy, tin-silver alloy, tin-silver-copper alloy or lead-free alloy.

Referring to FIG. 5F, after the tin-containing metal layer 36 is formed, the photoresist layer 32 is subsequently removed. Continuing, the seed layer 30 and the adhesion/barrier layer 28 that are not under the tin-containing metal layer 36 are removed. The method of removing the adhesion/barrier layer 28 can be divided into dry etching and wet etching, and dry etching is performed by using high-pressure argon gas for sputtering etching, and in wet etching, if the adhesion/barrier layer 28 is titanium or In the case of titanium tungsten alloy, it can be removed using hydrogen peroxide.

Referring to FIG. 5G, a reflow process is selectively performed to cause the tin-containing metal layer 36 to reach a melting point and cohesively form a spherical shape. However, in this embodiment, the reflow process may be performed first, so that the tin-containing metal layer 36 reaches the melting point and is internally spherical, and then the seed layer 30 and the adhesion/barrier layer 28 not under the tin-containing metal layer 36 are removed. Alternatively, in this embodiment, the reflow process may not be performed until the tin-containing metal layer 36 is connected to an external circuit, such as a semiconductor wafer, a printed circuit board containing glass fibers, and a thickness. A soft plate having a polymer layer between 30 micrometers and 200 micrometers, a substrate containing a ceramic material, or a passive component formed in advance.

Therefore, the present invention can be formed on the pads 16 exposed by the partial openings 14a of the protective layer 14 for bonding wire bonding wires (such as gold wires or copper wires), for bonding tapes, for bonding an external circuit. a metal bump (such as a gold bump), a tin-containing metal layer for bonding an external circuit, or a metal pad 84 bonded to an external circuit through an anisotropic conductive paste, and the metal pad 84 is not formed. A tin-containing metal layer 36 is formed on the pad 16. In addition, the top of the metal pad 84 may include an adhesive film layer (not shown) for connecting the wire bonding wires, and the adhesion film layer is, for example, a gold layer. Further, a gold layer may be formed on the diffusion barrier layer 34 before the formation of the tin-containing metal layer 36, and then a tin-containing metal layer 36 may be formed on the gold layer. In addition, the tin-containing metal layer 36 in this embodiment may also be replaced by a solder bump.

Referring to FIG. 5H, after the above process is completed, the semiconductor substrate 2 can be subsequently diced to form a plurality of semiconductor wafers 86, wherein each semiconductor wafer 86 includes a semiconductor substrate 2, a wiring structure 6, and a plurality of dielectric layers. 12. A protective layer 14, at least one metal pad 84 and at least one tin-containing metal layer 36, and the like. In addition, a plurality of semiconductor elements 4 (eg, transistors or metal oxide semiconductors, etc.) are located in or above the semiconductor substrate 2, and one of the semiconductor elements 4 is selectively positioned on the metal pad 84 or the tin-containing metal layer 36. In the lower part, two of the semiconductor elements 4 are electrically connected to the metal pad 84 and the tin-containing metal layer 36, respectively. Further, in each of the semiconductor wafers 86, the top of the protective layer 14 may be an oxysulfide compound layer or a ruthenium nitride compound layer.

Each of the semiconductor wafers 86 can be connected to an external circuit through the tin-containing metal layer 36. The external circuit can be a semiconductor wafer, a printed circuit board, a flexible board, a substrate containing a ceramic material, or a passive component formed in advance, wherein the printed circuit board contains Glass fiber, and the soft board comprises a polymer layer having a thickness of between 30 micrometers and 200 micrometers, such as a polyimide.

In addition, through the wire bonding process, a metal pad 84 of a semiconductor chip 86 can be bonded to a wire conductor (such as a gold wire or a copper wire) to connect an external circuit, which can be a semiconductor chip, a printed circuit board, or a soft circuit. A board, a substrate or a lead frame containing a ceramic material, wherein the printed circuit board contains glass fibers, and the soft board comprises a polymer layer having a thickness of between 30 micrometers and 200 micrometers, such as a polyimide.

Furthermore, through the tape bonding technology, a metal pad 84 of a semiconductor wafer 86 can be bonded to an external tape, wherein the external circuit can be a semiconductor wafer, a printed circuit board, a flexible board or a ceramic. A substrate for a material in which the printed circuit board contains glass fibers, and the soft board comprises a polymer layer having a thickness of between 30 micrometers and 200 micrometers, such as a polyimide. In addition, the tape has at least one metal line and at least one polymer layer, and the metal line connects the metal pads 84, for example, by bonding the metal pads 84 via tin metal or tin-silver alloy.

Moreover, through the thermocompression bonding process, one of the metal pads 86 of the semiconductor wafer 86 can be pressed into the anisotropic conductive paste, and the metal particles located in the anisotropic conductive paste are collected on the metal pads 84 and An indium tin oxide-containing pad is formed between an external circuit (for example, a glass substrate) and a pad containing indium tin oxide electrically connected to the metal pad 84 and an external circuit. Further, the external circuit is, for example, a semiconductor wafer, a printed circuit board, a flexible board containing a polymer layer having a thickness of between 30 μm and 200 μm, or a substrate containing a ceramic material.

Moreover, one of the metal pads 86 of the semiconductor wafer 86 can be bonded to a metal bump (such as a gold bump) to connect to an external circuit. The external circuit can be a semiconductor wafer, a printed circuit board, a glass substrate, a flexible board, or A substrate of ceramic material, wherein the printed circuit board contains glass fibers, and the soft board comprises a polymer layer having a thickness of between 30 micrometers and 200 micrometers, such as a polyimide.

In addition, in this embodiment, before the semiconductor substrate 2 is cut, an external circuit is first connected through the tin-containing metal layer 36. The external circuit may be a semiconductor wafer, a printed circuit board, a flexible board, a substrate containing a ceramic material, or formed in advance. A passive component in which the printed circuit board contains glass fibers, and the flexible board comprises a polymer layer having a thickness of between 30 micrometers and 200 micrometers, such as a polyimide. Next, the semiconductor substrate 2 is diced to form a plurality of semiconductor wafers. Thereafter, the present embodiment can bond a wire bonding wire (using a wire bonding process), a bonding tape (using tape bonding automatic bonding technology), and a metal bump (such as gold) bonded to an external circuit on the metal pad 84 of each semiconductor wafer 86. Bump), a tin-containing metal layer bonded to an external circuit or an external circuit through an anisotropic conductive paste.

Referring to FIG. 5I, in this embodiment, a polymer layer 39 may be formed on the protective layer 14, and the polymer layer opening 39a and the polymer layer opening 39b located in the polymer layer 39 are respectively exposed. a pad 16a and a second pad 16b, and then forming a metal pad 84 on the first pad 16a exposed by the polymer layer opening 39a according to the process steps described in FIGS. 5A to 5H, and forming a The tin metal layer 36 is above the second pad 16b exposed by the polymer layer opening 39b. For details of this part, refer to the above related description, which will not be described in detail herein. Wherein, the polymer layer 39 is selected from the group consisting of polyiminoimine, phenylcyclobutene, polyurethane, epoxy resin, parylene polymer, solder mask material, elastic material or porous dielectric material. First, the method of forming the polymer layer 39 may be performed by a hot press dry film method or a screen printing method in addition to the spin coating method, and the thickness of the other polymer layer 39 is between 1 μm and 30 μm. Please refer to the above for the related application of the semiconductor wafer 86' shown in Fig. 5I, and will not be described here.

Furthermore, the present embodiment can also be applied to a reconfiguration line or a connection line as in the second embodiment. Please refer to FIG. 5J and FIG. 5K at the same time. In this embodiment, the metal line 40 as the reconfiguration line and the metal line 42 as the connection line can be simultaneously formed on the semiconductor substrate 2, and the method for forming is as described in the second embodiment. content. Then, according to the process steps described in FIGS. 5A to 5G, the metal pads 84 and the tin-containing metal layer 36 are formed on the metal lines 40 and 42 exposed by the polymer layer opening 60a. The relevant description will not be described in detail here. Further, the related applications of the semiconductor wafer 87 shown in Fig. 5J and the semiconductor wafer 87' shown in Fig. 5K are also referred to above, and will not be described here. However, in the above manner, the present invention can also form only the relocation line or the connection line above the semiconductor substrate 2, and further form the metal pad 84 and the tin-containing metal layer 36 on the relocation line or the connection line.

Fourth embodiment:

6A to 6C are diagrams showing the formation of a metal bump (for example, a gold bump) for bonding a wire bonding wire, bonding an adhesive tape, bonding an external circuit, and bonding a tin-containing metal on a wafer or a wafer. A schematic cross-sectional view of a layer or a plurality of metal pads bonded to an external circuit through an anisotropic conductive paste.

Referring to FIG. 6A, an adhesion/barrier layer 18 having a thickness between 0.01 micrometers and 3 micrometers (preferably having a thickness between 0.01 micrometers and 1 micrometer) is formed on the protective layer 14 and the opening 14a. The exposed pads 16 are exposed. The material of the adhesion/barrier layer 18 is selected from the group consisting of titanium, tungsten, cobalt, nickel, titanium nitride, titanium tungsten alloy, nickel vanadium alloy, tantalum, tantalum nitride, chromium, copper, chromium copper alloy, gold, tantalum, At least one of platinum, palladium, rhodium, iridium, and silver, or at least one of the group consisting of, for example, by sputtering or evaporation.

Next, a copper layer 88 having a thickness between 0.005 micrometers and 2 micrometers (preferably having a thickness between 0.1 micrometers and 0.7 micrometers) is formed on the adhesion/barrier layer 18, and the copper layer 88 is formed, for example. It is a method of sputtering, evaporation, physical vapor deposition, electroplating or electroless plating.

Referring to FIG. 6B, a photoresist layer 22 is formed on the copper layer 88, and then the photoresist layer 22 is patterned through an exposure and development process to form the photoresist layer opening 22a in the photoresist layer 22 and exposed. The copper layer 88 is over the pads 16, and during the process of forming the photoresist layer opening 22a, for example, exposure is performed by a double exposure machine or scanner. Continuing, a copper layer 90 having a thickness between 1 micrometer and 35 micrometers (preferably having a thickness between 8 micrometers and 35 micrometers) is formed on the copper layer 88 exposed by the photoresist layer opening 22a to form The copper layer 90 is formed by electroplating or electroless plating, for example. Further, a nickel layer 92 having a thickness of between 0.1 μm and 10 μm (preferably having a thickness between 0.1 μm and 5 μm) is formed on the copper layer 90, and a nickel layer 92 is formed by, for example, electroplating. Or it is electroless plating. Next, a gold layer 94 having a thickness of between 0.01 micrometers and 10 micrometers (preferably having a thickness between 0.1 micrometers and 2 micrometers) is formed on the nickel layer 92, and the gold layer 94 is formed by, for example, electroplating. Or it is electroless plating.

Referring to FIG. 6C, after the gold layer 94 is formed, the photoresist layer 22 is subsequently removed. Continuing, the copper layer 88 and the adhesion/barrier layer 18 that are not under the copper layer 90 are removed. The method of removing the adhesion/barrier layer 18 can be divided into dry etching and wet etching, and dry etching is performed by using high-pressure argon gas for sputtering etching, and in wet etching, if the adhesion/barrier layer 18 is titanium or In the case of titanium tungsten alloy, it can be removed using hydrogen peroxide.

Therefore, the plurality of metal pads 96 are formed on the plurality of pads 16 exposed by the plurality of openings 14a of the protective layer 14. The metal pads 96 are formed by an adhesion/barrier layer 18 on the adhesion/barrier layer 18. A copper layer 88, a copper layer 90 on the copper layer 88, a nickel layer 92 on the copper layer 90, and a gold layer 94 on the nickel layer 92, and the metal pads 96 Can be used to bond a wire conductor (such as a gold wire), bond a tin-containing metal layer, bond a metal bump to an external circuit, bond tape (using tape bonding technology) or bond an external circuit through an anisotropic conductive paste .

Referring to FIG. 6D, the present embodiment can be bonded to a gold layer 94 of a portion of the metal pads 96 between 1 micrometer and 500 micrometers by a planting process (preferably, the thickness is between A tin-containing metal ball 98 between 3 microns and 250 microns is then connected to a pad 95 of an external circuit 97 through a reflow process. The external circuit is, for example, a semiconductor wafer, a printed circuit board containing glass fibers, a substrate containing a ceramic material, or a passive component formed in advance; and the tin-containing metal ball 98 is, for example, tin-lead alloy, tin-silver alloy, tin-silver. Copper alloy or lead-free alloy. Taking tin-lead alloy as an example, the tin/lead ratio can be adjusted according to the demand. The common tin-lead ratio is 90/10, 95/5, 97/3, 99/1, 37/63, etc.

Alternatively, a tin-containing metal layer 98' may be formed in advance on an external circuit 97', and then the tin-containing metal layer 98' is connected to the gold layer 94 of the metal pad 96 through a reflow process, thereby making the metal The pad 96 is connected to the external circuit 97' as shown in Fig. 6E.

Referring to FIG. 6F, after the above process is completed, the semiconductor substrate 2 can be subsequently cut to form a plurality of semiconductor wafers 99, wherein each semiconductor wafer 99 includes a semiconductor substrate 2, a wiring structure 6, and a plurality of dielectric layers. 12. A protective layer 14 and a plurality of metal pads 96 and the like. In addition, a plurality of semiconductor elements 4 (eg, a transistor or a metal oxide semiconductor, etc.) are located in or above the semiconductor substrate 2, and one of the semiconductor elements 4 is selectively positioned below one of the metal pads 96, Further, these semiconductor elements 4 are respectively connected to the metal pads 96. Further, in each of the semiconductor wafers 99, the top of the protective layer 14 may be an oxon compound layer or a ruthenium nitride compound layer.

Therefore, each of the semiconductor wafers 99 may be bonded to a tin-containing metal ball 98 on a portion of the metal pads 96 to connect an external circuit, or to bond a tin-containing metal layer 98' to an external circuit. The external circuit may be a semiconductor wafer. a printed circuit board, a flexible board, a substrate containing a ceramic material, or a previously formed passive component, wherein the printed circuit board contains glass fibers, and the flexible board comprises a polymer layer having a thickness of between 30 micrometers and 200 micrometers. The layer of matter is, for example, polyimine.

Alternatively, each of the semiconductor wafers 99 may be bonded to a portion of the metal pads 96 by a metal bump (eg, a gold bump) of an external circuit, which may be a semiconductor wafer, a printed circuit board, a glass substrate, a flexible board, A substrate comprising a ceramic material or a passive component formed in advance, wherein the printed circuit board contains glass fibers, and the soft board comprises a polymer layer having a thickness interposed therebetween, such as a polyimide.

In addition, through the wire bonding process, a portion of the metal pads 96 of the semiconductor wafer 99 can be bonded to a wire bonding wire 100 (such as a gold wire or a copper wire) to be connected to an external circuit, and the external circuit can be a semiconductor wafer or a printed circuit. a board, a flexible board, a substrate or a lead frame containing a ceramic material, wherein the printed circuit board contains glass fibers, and the soft board comprises a polymer layer having a thickness of between 30 micrometers and 200 micrometers, such as a polymer layer The imine is shown in Figure 6G.

Furthermore, through the tape bonding technology, a portion of the metal pads 96 of the semiconductor wafer 99 can be bonded to an external tape, wherein the external circuit can be a semiconductor wafer, a printed circuit board, a flexible board or A substrate of ceramic material, wherein the printed circuit board contains glass fibers, and the soft board comprises a polymer layer having a thickness of between 30 micrometers and 200 micrometers, such as a polyimide. Additionally, the tape has at least one metal line and at least one polymer layer, and the metal lines connect the metal pads 96, such as metal pads 96 via tin metal or tin-silver alloy.

Moreover, through the thermocompression bonding process, a metal pad 96 of a semiconductor wafer 99 can be pressed into the anisotropic conductive paste, and the metal particles located in the anisotropic conductive paste are collected on the metal pad 96 and An indium tin oxide-containing pad is formed between an external circuit (for example, a glass substrate) and a pad containing indium tin oxide electrically connected to the metal pad 96 and the external circuit. Further, the external circuit is, for example, a semiconductor wafer, a printed circuit board, a flexible board containing a polymer layer having a thickness of between 30 μm and 200 μm, or a substrate containing a ceramic material.

Therefore, as can be seen from the above, the present embodiment has ten embodiments described below: a tin-containing metal ball 98 or a tin-containing metal layer 98' is bonded to a portion of the metal pads 96 of the semiconductor wafer 99. The external circuitry is connected and a wire conductor is bonded to the metal pad 96 that does not engage the tin-containing metal ball 98 or the tin-containing metal layer 98'.

A tin-containing metal ball 98 or a tin-containing metal layer 98' is bonded to a portion of the metal pads 96 of a semiconductor wafer 99 to be connected to an external circuit, and the tin-containing metal ball 98 or the tin-containing metal layer 98' is not bonded. A metal tape 96 is bonded to a tape.

A tin-containing metal ball 98 or a tin-containing metal layer 98' is bonded to a portion of the metal pads 96 of a semiconductor wafer 99 to be connected to an external circuit, and the tin-containing metal ball 98 or the tin-containing metal layer 98' is not bonded. The metal pad 96 is bonded to an external circuit through an anisotropic conductive paste.

A tape is bonded to a portion of the metal pads 96 of the semiconductor wafer 99 to be connected to an external circuit, and an external circuit is bonded through the anisotropic conductive paste on the metal pads 96 of the unbonded tape.

A tape is bonded to a portion of the metal pads 96 of a semiconductor wafer 99 to be connected to an external circuit, and a wire bond is bonded to the metal pads 96 of the unbonded tape.

A wire bond is bonded to a portion of the metal pads 96 of the semiconductor wafer 99, and an external circuit is bonded through the anisotropic conductive paste on the metal pads 96 of the unbonded wire.

A metal bump of an external circuit is bonded to a portion of the metal pad 96 of the semiconductor wafer 99, and a wire bond is bonded to the metal pad 96 of the metal bump.

A metal bump of an external circuit is bonded to a portion of the metal pads 96 of a semiconductor wafer 99, and a tape is bonded to the metal pads 96 of the metal bumps.

A metal bump of an external circuit is bonded to a portion of the metal pad 96 of the semiconductor wafer 99, and a tin-containing metal ball 98 or a tin-containing metal layer 98' is bonded to the metal pad 96 on which the metal bump is not bonded.

A metal bump of an external circuit is bonded to a portion of the metal pad 96 of the semiconductor wafer 99, and an external circuit is bonded through the anisotropic conductive paste on the metal pad 96 of the unbonded metal bump.

In addition, this embodiment can also be connected to an external circuit by bonding the tin-containing metal ball 98, the tin-containing metal layer 98' or the metal bump after the semiconductor substrate 2 is cut. The external circuit can be a semiconductor wafer or a printed circuit board. a flexible board, a glass substrate, a substrate containing a ceramic material, or a previously formed passive component, wherein the printed circuit board contains glass fibers, and the flexible board comprises a polymer layer having a thickness of between 30 micrometers and 200 micrometers. The layer is, for example, a polyimine. Finally, in this embodiment, the wire bonding wire (using the wire bonding process) and the bonding tape can be bonded on the metal pad 96 of each semiconductor wafer on which the tin-containing metal ball 98, the tin-containing metal layer 98' or the metal bump is not formed. Adhesive tape bonding technology) or an external circuit through an anisotropic conductive paste.

Therefore, the present invention can form a tin-containing metal ball for bonding a tin-containing metal ball on a pad exposed by a part of the opening of the protective layer, for bonding a tin-containing metal layer of an external circuit, and for bonding a wire bonding wire (such as a gold wire). A metal pad 96 for bonding an adhesive tape, for bonding a metal bump, or for bonding an external circuit through an anisotropic conductive paste.

Referring to FIG. 6H, in this embodiment, a polymer layer 39 may be formed on the protective layer 14, and the plurality of polymer layer openings 39a located in the polymer layer 39 expose the plurality of pads 16, and then In the process steps of FIGS. 6A to 6C, the metal pads 96 are formed on the pads 16 exposed by the polymer layer openings 39a. For the details of this part, refer to the above related description, which will not be described in detail herein. Wherein, the polymer layer 39 is selected from the group consisting of polyiminoimine, phenylcyclobutene, polyurethane, epoxy resin, parylene polymer, solder mask material, elastic material or porous dielectric material. First, the method of forming the polymer layer 39 may be performed by a hot press dry film method or a screen printing method in addition to the spin coating method, and the thickness of the other polymer layer 39 is between 1 μm and 30 μm. Please refer to the above for related applications of the semiconductor wafer 99a shown in FIG. 6H, and will not be described here.

Furthermore, the present embodiment can also be applied to a reconfiguration line or a connection line as in the second embodiment. Please refer to FIG. 6I and FIG. 6J at the same time. In this embodiment, the metal line 40 as the reconfiguration line and the metal line 42 as the connection line can be simultaneously formed on the semiconductor substrate 2, and the forming method is referred to the second implementation. content. Then, according to the process steps described in FIG. 6A to FIG. 6C, the metal pads 96 are formed on the metal lines 40 and 42 exposed by the polymer layer opening 60a. For the part, please refer to the above description. Describe in detail. Further, the related applications of the semiconductor wafer 99b shown in FIG. 6I and the semiconductor wafer 99c shown in FIG. 6J are also referred to above, and will not be described here. However, in the above manner, the present invention can also form only the relocation line or the connection line above the semiconductor substrate 2, and further form the metal pad 96 on the relocation line or the connection line.

Fifth embodiment:

Referring to FIG. 7A, after the process step shown in FIG. 2A is completed, a photoresist layer 100 is formed on the seed layer 20, and the photoresist layer 100 is patterned by an exposure and development process to form a photoresist. The layer opening 100a is in the photoresist layer 100 and exposes the seed layer 20 located above the first pad 16a, and is exposed during the process of forming the photoresist layer opening 100a, for example, by a double exposure machine or scanner.

Further, a metal layer 102 having a thickness between 1 micrometer and 200 micrometers (for example, between 1 micrometer and 50 micrometers) is formed on the seed layer 20 exposed by the photoresist layer opening 100a. The preferred thickness is between 2 microns and 30 microns, and the metal layer 102 is formed by electroplating or electroless plating. Alternatively, the metal layer 102 may be a single metal layer structure of gold, copper, silver, palladium, platinum, rhodium, ruthenium, iridium or nickel, or a composite layer composed of the above metal materials. For example, the metal layer 102 may be a gold layer formed by electroplating between 8 micrometers and 35 micrometers or a copper layer formed by electroplating between 8 micrometers and 35 micrometers. . Moreover, the metal layer 102 is formed by, for example, plating a copper layer having a thickness of between 8 μm and 35 μm on a seed layer 20 of, for example, copper, followed by plating between 0.1 μm and 10 μm. A nickel layer (preferably having a thickness between 0.1 micrometers and 5 micrometers) is on the copper layer, and the final plating thickness is between 0.01 micrometers and 10 micrometers (preferably, the thickness is between 0.1 micrometers and 2 micrometers). A gold layer on the nickel layer.

Referring to FIG. 7B, after the metal layer 102 is formed, the photoresist layer 100 is subsequently removed. Continuing, a photoresist layer 104 is formed on the seed layer 20 and the metal layer 102, and the photoresist layer 104 is patterned through the exposure and development process to form the photoresist layer opening 104a in the photoresist layer 104 and exposed. The seed layer 20 is over the second pad 16b, and during exposure of the photoresist layer opening 104a, for example, by exposure to a double exposure machine or scanner. Next, a metal layer 106 having a thickness between 1 micrometer and 20 micrometers (preferably having a thickness between 2 micrometers and 10 micrometers) is formed on the seed layer 20 exposed by the photoresist layer opening 104a, and The manner in which the metal layer 106 is formed is, for example, electroplating or electroless plating. Alternatively, the metal layer 106 may be a single metal layer structure of gold, copper, silver, palladium, platinum, rhodium, ruthenium, iridium or nickel, or a composite layer composed of the above metal materials. For example, the metal layer 106 may be a gold layer formed by electroplating with a thickness between 1 micrometer and 20 micrometers or a copper layer formed by electroplating with a thickness between 1 micrometer and 20 micrometers. . Moreover, the metal layer 106 is formed by, for example, plating a copper layer having a thickness between 1 micrometer and 15 micrometers on a seed layer 20 of, for example, copper, and then plating the thickness between 0.1 micrometers and 5 micrometers. A layer of nickel is on the copper layer, and a gold layer having a thickness between 0.01 micrometers and 3 micrometers is finally plated on the nickel layer. Therefore, the metal layer 102 and the metal layer 106 may be of the following four structures: the metal layer 102 and the metal layer 106 are both of the aforementioned single gold layer structures.

The metal layer 102 and the metal layer 106 are both of the aforementioned copper/nickel/gold structures.

The metal layer 102 is of the single gold layer structure described above, and the metal layer 106 is of the aforementioned copper/nickel/gold structure.

The metal layer 102 is of the aforementioned copper/nickel/gold structure, and the metal layer 106 is of the single gold layer structure described above.

Referring to FIG. 7C, after the metal layer 106 is formed, the photoresist layer 104 is subsequently removed. Continuing, the seed layer 20 and the adhesion/barrier layer 18 that are not under the metal layer 102 and the metal layer 106 are removed. The method of removing the adhesion/barrier layer 18 can be divided into dry etching and wet etching, such as sputtering etching using high-pressure argon gas, and in the wet etching, if the adhesion/barrier layer 18 is titanium or titanium. In the case of a tungsten alloy, it can be removed using hydrogen peroxide. Further, when the seed layer 20 is gold, it can be removed by using an iodine-containing etching solution (for example, an etching solution such as potassium iodide).

Therefore, the metal pads 108 and the metal pads 110 are respectively formed on the first pads 16a and the second pads 16b exposed by the openings 14a of the protective layer 14. The metal pad 108 is composed of an adhesive/barrier layer 18, a sub-layer 20 on the adhesion/barrier layer 18, and a metal layer 102 on the seed layer 20. The metal pad is formed. 108 can be bonded to a wire conductor (such as a gold wire or copper wire), a metal bump (such as a gold bump) bonded to an external circuit, a tin metal layer bonded to an external circuit, and a tin-containing metal ball bonded The ball-laying process), bonding a tape (using tape bonding technology) or bonding an external circuit through an anisotropic conductive paste; in addition, the metal pad 110 is adhered by an adhesive/barrier layer 18, A sub-layer 20 on the barrier layer 18 is formed with a metal layer 106 on the seed layer 20, and the metal pad 110 can be bonded to a wire (such as a gold wire or a copper wire) to engage an external circuit. a metal bump (such as a gold bump), a tin-containing metal layer bonded to an external circuit, a tin-containing metal ball (using a ball-planting process), a bonding tape (using tape bonding technology) or The anisotropic conductive paste is bonded to an external circuit.

For example, when the metal pad 110 is bonded to a wire conductor (such as a gold wire or a copper wire) by a wire bonding process, the metal pad 108 engages a tape using tape bonding technology. Alternatively, when the metal pad 110 is bonded to a wire conductor (such as a gold wire or a copper wire) by a wire bonding process, the metal pad 108 also utilizes a wire bonding process to bond a wire conductor (such as a gold wire or a copper wire). Alternatively, when the metal pad 110 is bonded to a wire conductor (such as a gold wire or a copper wire) by a wire bonding process, the metal pad 108 is bonded to a metal bump (such as a gold bump) of an external circuit. Alternatively, when the metal pad 110 is bonded to a wire conductor (such as a gold wire or a copper wire) by a wire bonding process, the metal pad 108 is bonded to a tin-containing metal layer or a tin-containing metal ball. Alternatively, when the metal pad 110 is bonded to a wire conductor (such as a gold wire or a copper wire) by a wire bonding process, the metal pad 108 is bonded to an external circuit through the anisotropic conductive paste.

For example, when the metal pad 110 engages a metal bump (such as a gold bump) of an external circuit, the metal pad 108 engages a tape using tape-bonding automated bonding techniques. Alternatively, when the metal pad 110 is bonded to a metal bump (such as a gold bump) of an external circuit, the metal pad 108 is bonded to a wire (such as a gold wire or a copper wire) by a wire bonding process. Alternatively, when the metal pad 110 is bonded to a metal bump (such as a gold bump) of an external circuit, the metal pad 108 also engages a metal bump (such as a gold bump) of an external circuit. Alternatively, when the metal pad 110 is bonded to a metal bump (such as a gold bump) of an external circuit, the metal pad 108 is bonded to one of the external circuits containing a tin metal layer or a tin-containing metal ball. Alternatively, when the metal pad 110 is bonded to a metal bump (such as a gold bump) of an external circuit, the metal pad 108 is bonded to an external circuit through the anisotropic conductive paste.

For example, when the metal pad 110 is bonded to a tin-containing metal layer or a tin-containing metal ball, the metal pad 108 is bonded to a metal bump (such as a gold bump) of an external circuit. Alternatively, when the metal pad 110 is bonded to a tin-containing metal layer or a tin-containing metal ball of an external circuit, the metal pad 108 is bonded to the tape by tape bonding. Alternatively, when the metal pad 110 is bonded to a tin metal layer or a tin-containing metal ball of an external circuit, the metal pad 108 is bonded to a wire (such as a gold wire or a copper wire) by a wire bonding process. Alternatively, when the metal pad 110 is bonded to a tin-containing metal layer or a tin-containing metal ball, the metal pad 108 also bonds a tin-containing metal layer or a tin-containing metal ball to an external circuit. Alternatively, when the metal pad 110 is bonded to one of the external circuits containing the tin metal layer or a tin-containing metal ball, the metal pad 108 is bonded to an external circuit through the anisotropic conductive paste.

For example, when the metal pad 108 is bonded to a wire conductor (such as a gold wire or a copper wire) by a wire bonding process, the metal pad 110 engages a tape by tape bonding technology. Alternatively, when the metal pad 108 is bonded to a wire conductor (such as a gold wire or a copper wire) by a wire bonding process, the metal pad 110 also uses a wire bonding process to bond a wire conductor (such as a gold wire or a copper wire). Alternatively, when the metal pad 108 is bonded to a wire conductor (such as a gold wire or a copper wire) by a wire bonding process, the metal pad 110 is bonded to a metal bump (such as a gold bump) of an external circuit. Alternatively, when the metal pad 108 is bonded to a wire conductor (such as a gold wire or a copper wire) by a wire bonding process, the metal pad 110 is bonded to a tin-containing metal layer or a tin-containing metal ball. Alternatively, when the metal pad 108 is bonded to a wire conductor (such as a gold wire or a copper wire) by a wire bonding process, the metal pad 110 is bonded to an external circuit through the anisotropic conductive paste.

For example, when the metal pad 108 is bonded to a metal bump (such as a gold bump) of an external circuit, the metal pad 110 engages a tape using tape bonding technology. Alternatively, when the metal pad 108 is bonded to a metal bump (such as a gold bump) of an external circuit, the metal pad 110 is bonded to a wire conductor (such as a gold wire or a copper wire) by a wire bonding process. Alternatively, when the metal pad 108 is bonded to a metal bump (such as a gold bump) of an external circuit, the metal pad 110 also engages a metal bump (such as a gold bump) of an external circuit. Alternatively, when the metal pad 108 is bonded to a metal bump (such as a gold bump) of an external circuit, the metal pad 110 is bonded to a tin-containing metal layer or a tin-containing metal ball. Alternatively, when the metal pad 108 is bonded to a metal bump (such as a gold bump) of an external circuit, the metal pad 110 is bonded to an external circuit through the anisotropic conductive paste.

For example, when the metal pad 108 is bonded to a tin-containing metal layer or a tin-containing metal ball, the metal pad 110 is bonded to a metal bump (such as a gold bump) of an external circuit. Alternatively, when the metal pad 108 is bonded to a tin-containing metal layer or a tin-containing metal ball, the metal pad 110 is bonded to a tape by tape bonding. Alternatively, when the metal pad 108 is bonded to a tin-containing metal layer or a tin-containing metal ball, the metal pad 110 is bonded to a wire conductor (such as a gold wire or a copper wire) by a wire bonding process. Alternatively, when the metal pad 108 is bonded to a tin-containing metal layer or a tin-containing metal ball, the metal pad 110 also bonds a tin-containing metal layer or a tin-containing metal ball to an external circuit. Alternatively, when the metal pad 108 is bonded to a tin-containing metal layer or a tin-containing metal ball, the metal pad 110 is bonded to an external circuit through the anisotropic conductive paste.

Moreover, taking the metal layer 102 and the metal layer 106 as the gold layer as an example (such as the above four structures of the metal layer 102 and the metal layer 106, the top layer of which is a gold layer), when the metal layer 106 of the metal pad 110 When a gold wire is bonded by a wire bonding process, the metal layer 102 of the metal pad 108 can be bonded to a tape by tape bonding. Alternatively, when the metal layer 106 of the metal pad 110 is bonded to a gold wire by a wire bonding process, the metal layer 102 of the metal pad 108 may also be bonded to a gold wire by a wire bonding process. Alternatively, when the metal layer 106 of the metal pad 110 is connected to a metal bump (such as a gold bump) of an external circuit, the metal layer 102 of the metal pad 108 can be bonded to a tape by tape bonding. Alternatively, when the metal layer 106 of the metal pad 110 is bonded to a metal bump (such as a gold bump) of an external circuit, the metal layer 102 of the metal pad 108 can be bonded to a gold wire by a wire bonding process. Alternatively, when the metal layer 106 of the metal pad 110 is bonded to a metal bump (such as a gold bump) of an external circuit, the metal layer 102 of the metal pad 108 may also be bonded to a metal bump of an external circuit (eg, Gold bumps).

Therefore, in this embodiment, a metal bump for bonding a wire bonding wire, a bonding tape, bonding an external circuit, a tin-containing metal layer for bonding an external circuit, and a bonding include may be respectively formed on the pads exposed by the openings of the protective layer. The tin metal ball or the metal pad 108 and the metal pad 110 of the two different thicknesses of the external circuit are joined by the anisotropic conductive adhesive. In addition, the metal pad 108 and the top of the metal pad 110 may also include an adhesive film layer (not shown) for connecting a wire bonding wire (such as a gold wire), and the adhesion film layer is, for example, a gold layer.

Referring to FIG. 7D, after the above process is completed, the semiconductor substrate 2 can be subsequently diced to form a plurality of semiconductor wafers 112, wherein each semiconductor wafer 112 includes a semiconductor substrate 2, a wiring structure 6, and a plurality of dielectric layers. 12. A protective layer 14, at least one metal pad 108, at least one metal pad 110, and the like. In addition, a plurality of semiconductor elements 4 (eg, transistors or metal oxide semiconductors, etc.) are located in or above the semiconductor substrate 2, and one of the semiconductor elements 4 is selectively positioned on the metal pads 108 or the metal pads 110. Below, two of the semiconductor elements 4 are electrically connected to the metal pads 108 and the metal pads 110, respectively. Further, in each of the semiconductor wafers 112, the top of the protective layer 14 may be an oxonium compound layer or a ruthenium nitride compound layer.

Each semiconductor wafer 112 can be connected to an external circuit through a metal pad 108 and a metal pad 110. The external circuit can be a semiconductor wafer, a printed circuit board, a flexible board, a substrate containing a ceramic material, a glass substrate, or a passive component formed in advance. Where the printed circuit board contains glass fibers, and the soft board comprises a polymer layer having a thickness between 30 microns and 200 microns, such as a polyimide. The connection method comprises the following steps: 1. forming a wire bonding wire (such as a gold wire or a copper wire) through a wire bonding process to bond a metal pad of the semiconductor chip, and then connecting with an external circuit; 2. bonding a tape to the tape by automatic bonding technology to a metal pad of a semiconductor wafer, and further connected to an external circuit, wherein the tape has at least one metal line and at least one polymer layer, and the metal line is connected with a metal pad, for example, a metal bond via a tin metal or a tin-silver alloy Pad; three, using a metal bump (such as gold bumps) to join a metal pad of a semiconductor wafer, and then connected to an external circuit; Fourth, through a thermal compression process, a metal pad of a semiconductor wafer is pressed into In the anisotropic conductive paste, the metal particles in the anisotropic conductive paste are collected between the metal pad and a pad of an external circuit (such as a glass substrate) containing indium tin oxide, thereby being electrically connected. a pad containing an indium tin oxide connecting the metal pad and the external circuit; 5. bonding the metal pad of the semiconductor chip with the tin-containing metal layer or the tin-containing metal ball, and further Circuit.

In addition, in this embodiment, before the semiconductor substrate 2 is diced, the tin-containing metal layer, the tin-containing metal ball or the metal bump (such as a gold bump) is bonded through the metal pad 110, and then an external circuit is connected, and the external circuit can be A semiconductor wafer, a printed circuit board, a flexible board, a glass substrate, a substrate containing a ceramic material, or a previously formed passive component, wherein the printed circuit board contains glass fibers, and the flexible board includes a thickness of between 30 micrometers and 200 micrometers. A polymer layer, such as a polyimide. Next, the semiconductor substrate 2 is diced to form a plurality of semiconductor wafers. Thereafter, in this embodiment, a wire bonding wire (using a wire bonding process), a bonding tape (using tape bonding automatic bonding technology), or an anisotropic conductive paste may be bonded to an external circuit on the metal pad 108 of each semiconductor wafer.

Referring to FIG. 7E, in this embodiment, a polymer layer 39 may be formed on the protective layer 14, and the polymer layer opening 39a and the polymer layer opening 39b located in the polymer layer 39 are respectively exposed. a pad 16a and a second pad 16b, and then forming a metal pad 108 on the first pad 16a exposed by the polymer layer opening 39a, and forming according to the process steps described in FIGS. 7A-7D The metal pad 110 is on the second pad 16b exposed by the polymer layer opening 39b. For details, please refer to the above description, which will not be described in detail. Wherein, the polymer layer 39 is selected from the group consisting of polyiminoimine, phenylcyclobutene, polyurethane, epoxy resin, parylene polymer, solder mask material, elastic material or porous dielectric material. First, the method of forming the polymer layer 39 may be performed by a hot press dry film method or a screen printing method in addition to the spin coating method, and the thickness of the other polymer layer 39 is between 1 μm and 30 μm. Please refer to the above for related applications of the semiconductor wafer 112a shown in FIG. 7E, and will not be described here.

Furthermore, the present embodiment can also be applied to a reconfiguration line or a connection line as in the second embodiment. Please refer to FIG. 7F and FIG. 7G at the same time. In this embodiment, the metal line 40 as the reconfiguration line and the metal line 42 as the connection line can be simultaneously formed on the semiconductor substrate 2, and the method for forming is related to the second implementation. content. Then, according to the process steps described in FIGS. 7A to 7C, the metal pads 108 and the metal pads 110 are formed on the metal lines 40 and 42 exposed by the polymer layer opening 60a. For the related content, refer to the above description. It will not be described in detail here. Please refer to the above for the related applications of the semiconductor wafer 112b shown in FIG. 7F and the semiconductor wafer 112c shown in FIG. 7G, and will not be described here. However, in the above manner, the present invention can also form only the relocation line or the connection line above the semiconductor substrate 2, and further form the metal pad 108 and the metal pad 110 on the relocation line or the connection line.

Sixth embodiment:

Referring to FIG. 8A, after the process step shown in FIG. 2A is completed, a photoresist layer 114 is formed on the seed layer 20, and the photoresist layer 114 is patterned by an exposure and development process to form a photoresist. The layer opening 114a is in the photoresist layer 114 and exposes the seed layer 20 above the pad 16, and is exposed during exposure of the photoresist layer opening 114a, for example, by a double exposure machine or scanner.

Further, a metal layer 116 having a thickness between 1 micrometer and 200 micrometers (for example, between 1 micrometer and 50 micrometers) is formed on the seed layer 20 exposed by the photoresist layer opening 114a. The preferred thickness is between 2 microns and 30 microns, and the metal layer 116 is formed by electroplating or electroless plating. Alternatively, the metal layer 116 may be a single metal layer structure of gold, copper, silver, palladium, platinum, rhodium, ruthenium, iridium or nickel, or a composite layer composed of the above metal materials. For example, the metal layer 116 may be a gold layer formed by electroplating between 8 micrometers and 35 micrometers or a copper layer formed by electroplating between 8 micrometers and 35 micrometers. . Alternatively, the metal layer 116 is formed by, for example, plating a copper layer having a thickness between 8 micrometers and 35 micrometers on a seed layer 20 of, for example, copper, followed by a plating thickness between 0.1 micrometers and 10 micrometers. A nickel layer (preferably having a thickness between 0.1 micrometers and 5 micrometers) is on the copper layer, and the final plating thickness is between 0.01 micrometers and 10 micrometers (preferably, the thickness is between 0.1 micrometers and 2 micrometers). A gold layer is on the nickel layer.

Referring to FIG. 8B, after the metal layer 116 is formed, the photoresist layer 114 is subsequently removed. Continuing, the seed layer 20 and the adhesion/barrier layer 18 that are not under the metal layer 116 are removed. The method of removing the adhesion/barrier layer 18 can be divided into dry etching and wet etching, and dry etching is performed by using high-pressure argon gas for sputtering etching, and in wet etching, when the adhesion/barrier layer 18 is titanium or In the case of titanium tungsten alloy, it can be removed using hydrogen peroxide. Further, when the seed layer 20 is gold, it can be removed by using an iodine-containing etching solution (for example, an etching solution such as potassium iodide).

Thus, a plurality of metal pads 118 of the same thickness are formed on the plurality of pads 16 exposed by the plurality of openings 14a of the protective layer 14. The metal pad 118 is composed of an adhesive/barrier layer 18, a sub-layer 20 on the adhesion/barrier layer 18 and a metal layer 116 on the seed layer 20, and the metal pads 118. Can be used to bond wire conductors (such as gold or copper wires), metal bumps (such as gold bumps) that bond an external circuit, tin-containing metal layers that bond an external circuit, bond tin-containing metal balls, and bond tapes With an automatic bonding technique) or an external circuit through an anisotropic conductive paste.

For example, when a portion of the metal pads 118 are bonded to a wire conductor (such as a gold wire or a copper wire) by a wire bonding process, the remaining metal pads 188 engage a tape using tape bonding techniques. Alternatively, when a portion of the metal pads 118 are bonded to a wire conductor (such as a gold wire or a copper wire) by a wire bonding process, the remaining metal pads 118 engage a metal bump (such as a gold bump) of an external circuit. Alternatively, when a portion of the metal pads 118 are bonded to a wire conductor (such as a gold wire or a copper wire) by a wire bonding process, the remaining metal pads 118 engage a tin-containing metal ball or a tin-containing metal layer of an external circuit. Alternatively, when a portion of the metal pads 118 are bonded to a wire conductor (such as a gold wire or a copper wire) by a wire bonding process, the remaining metal pads 118 are bonded to an external circuit through the anisotropic conductive paste.

For example, when a portion of the metal pads 118 engage a metal bump (such as a gold bump) of an external circuit, the remaining metal pads 118 engage a tape using tape bonding techniques. Alternatively, when a portion of the metal pads 118 are bonded to a metal bump (such as a gold bump) of an external circuit, the remaining metal pads 118 are bonded to a wire conductor (such as a gold wire or a copper wire) by a wire bonding process. Alternatively, when a portion of the metal pads 118 engage a metal bump (such as a gold bump) of an external circuit, the remaining metal pads 118 engage a tin-containing metal ball or a tin-containing metal layer of an external circuit. Alternatively, when a portion of the metal pads 118 are bonded to a metal bump (such as a gold bump) of an external circuit, the remaining metal pads 118 are bonded to an external circuit through the anisotropic conductive paste.

For example, when a portion of the metal pads 118 bond a tin-containing metal ball or a tin-containing metal layer of an external circuit, the remaining metal pads 118 engage a metal bump (such as a gold bump) of an external circuit. Alternatively, when a portion of the metal pads 118 engage a tin-containing metal ball or a tin-containing metal layer of an external circuit, the remaining metal pads 118 utilize a tape automated bonding technique to bond a tape. Alternatively, when a portion of the metal pads 118 are bonded to a tin-containing metal ball or a tin-containing metal layer of an external circuit, the remaining metal pads 118 are bonded to a wire conductor (such as a gold wire or a copper wire) by a wire bonding process. Alternatively, when a portion of the metal pads 118 are bonded to a tin-containing metal ball or a tin-containing metal layer of an external circuit, the remaining metal pads 118 are bonded to an external circuit through the anisotropic conductive paste.

Moreover, taking the top layer of the metal layer 116 as a gold layer (such as the single gold layer structure or the copper/nickel/gold structure described above, the top layer of which is a gold layer), this embodiment can make all or part of the metal pads. The metal layer 116 of 118 is bonded to one of the gold bumps of an external circuit; or the metal layer 116 of all or a portion of the metal pads 118 is bonded to a gold wire by a wire bonding process.

Therefore, in this embodiment, a metal bump for bonding a wire bonding wire, a bonding tape, an external circuit, a tin-containing metal layer for bonding an external circuit, and a tin-containing joint can be formed on the pad exposed by the opening of the protective layer. The metal ball is a plurality of metal pads 118 having the same thickness joined to the external circuit through the anisotropic conductive paste. In addition, the top of the metal pad 118 may also include an adhesive film layer (not shown) for connecting a wire bonding wire (such as a gold wire), and the adhesion film layer is, for example, a gold layer.

Referring to FIG. 8C, after the above process is completed, the semiconductor substrate 2 can be subsequently cut to form a plurality of semiconductor wafers 120, wherein each semiconductor wafer 120 includes a semiconductor substrate 2, a wiring structure 6, and a plurality of dielectric layers. 12. A protective layer 14 and a plurality of metal pads 118 and the like. In addition, a plurality of semiconductor elements 4 (eg, transistors or metal oxide semiconductors, etc.) are located in or above the semiconductor substrate 2, and one of the semiconductor elements 4 is selectively positioned below the metal pads 118, and the semiconductors The components 4 are electrically connected to the metal pads 118, respectively. Further, in each of the semiconductor wafers 120, the top of the protective layer 14 may be an oxonium compound layer or a ruthenium nitride compound layer.

Each semiconductor wafer 120 can be connected to an external circuit through a metal pad 118. The external circuit can be a semiconductor wafer, a printed circuit board, a flexible board, a substrate containing a ceramic material, a glass substrate or a passive component formed in advance, wherein the printed circuit board The glass fiber is included, and the soft board comprises a polymer layer having a thickness of between 30 micrometers and 200 micrometers, such as a polyimide. The connection method includes: forming a wire bonding wire (for example, a gold wire or a copper wire) through a wire bonding process to bond a metal pad 118 of the semiconductor wafer 120 to be connected to an external circuit; and second, bonding a sticker through the tape bonding automatic bonding technology. The metal pad 118 is brought to a semiconductor wafer 120 and is further connected to an external circuit, wherein the tape has at least one metal line and at least one polymer layer, and the metal line connects the metal pads 118, for example via tin metal or tin a silver alloy bonding metal pad 118; three, using a metal bump of an external circuit (such as gold bumps) to join a metal pad 118 of the semiconductor wafer 120, and then connected with an external circuit; four, through the thermal compression process, so that A metal pad 118 of a semiconductor wafer 120 is pressed into the anisotropic conductive paste, and the metal particles in the anisotropic conductive paste are concentrated on the metal pad 118 and an external circuit (such as a glass substrate) containing indium. Between the pads of the tin oxide, the connection between the metal pad 118 and the external circuit containing the indium tin oxide is electrically connected; 5. the bonding of the tin-containing metal layer or the tin-containing metal ball Metal conductor pad 118 of the wafer 120, in turn connected to external circuits.

In addition, in this embodiment, before the semiconductor substrate 2 is cut, a tin-containing metal layer, a tin-containing metal ball or a metal bump (such as a gold bump) may be bonded through all or part of the metal pads 118, thereby connecting an external circuit. The external circuit may be a semiconductor wafer, a printed circuit board, a flexible board, a glass substrate, a substrate containing a ceramic material, or a previously formed passive component, wherein the printed circuit board contains glass fibers, and the flexible board includes a thickness of between 30 micrometers and 200 micrometers. A polymer layer between, such as a polyimine. Next, the semiconductor substrate 2 is diced to form a plurality of semiconductor wafers. Finally, a wire bonding wire (using a wire bonding process), a bonding tape (using tape bonding automatic bonding technology), or an alien object is bonded to each of the semiconductor wafers 120 on which the metal bumps or the tin-containing metal layer are not bonded. The conductive paste is bonded to an external circuit.

Referring to FIG. 8D, in this embodiment, a polymer layer 39 may be formed on the protective layer 14, and the plurality of polymer layer openings 39a located in the polymer layer 39 expose the plurality of pads 16, and then The process steps shown in FIGS. 8A to 8B form a plurality of metal pads 118 on the pads 16 exposed by the polymer layer openings 39a. For details, please refer to the above description, which will not be described in detail herein. Wherein, the polymer layer 39 is selected from the group consisting of polyiminoimine, phenylcyclobutene, polyurethane, epoxy resin, parylene polymer, solder mask material, elastic material or porous dielectric material. First, the method of forming the polymer layer 39 may be performed by a hot press dry film method or a screen printing method in addition to the spin coating method, and the thickness of the other polymer layer 39 is between 1 μm and 30 μm. Please refer to the above for related applications of the semiconductor wafer 120a shown in FIG. 8D, and will not be described here.

Furthermore, the present embodiment can also be applied to a reconfiguration line or a connection line as in the second embodiment. Please refer to FIG. 8E and FIG. 8F at the same time. In this embodiment, the metal line 40 as the reconfiguration line and the metal line 42 as the connection line can be simultaneously formed on the semiconductor substrate 2, and the method for forming is as described in the second embodiment. content. Then, according to the process steps described in FIGS. 8A-8B, the metal pads 118 are formed on the metal lines 40 and 42 exposed by the polymer layer opening 60a. For details, please refer to the above description, and the details are not described here. Add a narrative. Please refer to the above for the related applications of the semiconductor wafer 120b shown in FIG. 8E and the semiconductor wafer 120c shown in FIG. 8F, and will not be described here. However, in the above manner, the present invention can also form only the relocation line or the connection line above the semiconductor substrate 2, and further form the metal pad 118 on the relocation line or the connection line.

Referring to FIG. 9, it is a schematic cross-sectional view of a multi-chip package structure. As shown, the semiconductor wafer 122 may be a semiconductor wafer 112, a semiconductor wafer 112a, a semiconductor wafer 112b or a semiconductor formed in the fifth embodiment. The wafer 112c, or the semiconductor wafer 120, the semiconductor wafer 120a, the semiconductor wafer 120b or the semiconductor wafer 120c formed in the sixth embodiment, so that the semiconductor wafer 122 has a metal pad 126 for bonding the wire bonding wires and for bonding the tape Metal pad 128. In addition, the semiconductor wafer 124 has a metal pad 130 for bonding the wire bonding wires. The structure and material of the metal pad 130 are the same as those of the metal pad 118 described in the sixth embodiment. Moreover, through the wire bonding process, the one wire conductor 132 is bonded to a metal pad 126 and a metal pad 130.

In addition, a polymer 134 covers the metal pads 126 of the semiconductor wafer 122, the semiconductor wafer 124 and the wire bonding wires 132, wherein the polymer 134 is selected from the group consisting of polyimide, phenylcyclobutene, polyurethane, epoxy resin. One of a polyparaxylene polymer, a solder mask material, an elastic material or a porous dielectric material.

Moreover, through the thermocompression bonding process, the flexible tape 78 having at least one metal line 74 and the polymer layer 76 is connected to the metal pad 128 through the metal line 74, and the metal line 74 of the flexible tape 78 is, for example, via a metal layer. 79 (for example, tin metal or tin-silver alloy) is joined to the metal pad 70, wherein the polymer layer 76 is selected from the group consisting of polyimine, phenylcyclobutene, polyurethane, epoxy resin, and parylene polymer. One of a solder mask material, an elastomeric material, or a porous dielectric material. In addition, a polymer 136 covers the metal pad 128 and a portion of the metal line 74, wherein the polymer 136 is selected from the group consisting of polyimine, phenylcyclobutene, polyurethane, epoxy, and parylene. One of a polymer, a welding cap material, an elastic material or a porous dielectric material.

Therefore, as described above, through the tape bonding automatic bonding technology, the metal pad 128 can be connected to an external circuit through a tape, and the external circuit can be a semiconductor wafer, a printed circuit board, a flexible board or a substrate containing a ceramic material, wherein the printed circuit The sheet contains glass fibers, and the soft sheet comprises a polymer layer having a thickness between 30 microns and 200 microns, such as a polyimide.

Seventh embodiment:

Referring to FIG. 10A, after the process step shown in FIG. 2A is completed, a photoresist layer 138 is formed on the seed layer 20, and the photoresist layer 138 is patterned by an exposure and development process to form a photoresist. The layer opening 138a is within the photoresist layer 138 and exposes the seed layer 20 positioned above the first pad 16a, and is exposed during exposure of the photoresist layer opening 138a, for example, by a double exposure machine or scanner.

Further, a metal layer 140 having a thickness of between 1 micrometer and 500 micrometers is formed on the seed layer 20 exposed by the photoresist layer opening 138a, and the metal layer 140 is formed by, for example, electroplating or electroless plating. In addition, the metal layer 140 may be a single metal layer structure of gold, copper, silver, palladium, platinum, rhodium, ruthenium, iridium or nickel, or a composite layer composed of the above metal materials, and the preferred thickness thereof is Between 2 microns and 30 microns. For example, the metal layer 140 may be a gold layer formed by electroplating between 8 micrometers and 35 micrometers or a copper layer formed by electroplating between 8 micrometers and 35 micrometers. . Alternatively, the metal layer 140 is formed by, for example, plating a copper layer having a thickness between 8 micrometers and 35 micrometers on a seed layer 20 of, for example, copper, followed by a plating thickness between 0.1 micrometers and 10 micrometers. A nickel layer (preferably having a thickness between 0.1 micrometers and 5 micrometers) is on the copper layer, and the final plating thickness is between 0.01 micrometers and 10 micrometers (preferably, the thickness is between 0.1 micrometers and 2 micrometers). A gold layer on the nickel layer.

In addition, the metal layer 140 may be replaced by a tin-containing metal in addition to the metal material mentioned above, and the tin-containing metal is a tin-lead alloy, a tin-silver alloy, a tin-silver-copper alloy or a lead-free alloy, and the preferred thickness thereof is Between 3 microns and 250 microns. In addition, when the metal layer 140 is a tin-containing metal layer, a diffusion barrier layer (not shown in the drawing, see the foregoing description) is exposed in the photoresist layer opening 138a before the metal layer 140 is formed. On the seed layer 20, a metal layer 140 is further formed on the diffusion barrier layer, wherein the diffusion barrier layer is, for example, a nickel layer having a thickness of 0.1 μm to 5 μm and a thickness of 0.5 μm to 10 μm. A copper layer with a nickel layer on the copper layer.

Referring to FIG. 10B, after the metal layer 140 is formed, the photoresist layer 138 is subsequently removed. Continuing, the seed layer 20 and the adhesion/barrier layer 18 that are not under the metal layer 140 are removed. The method of removing the adhesion/barrier layer 18 can be divided into dry etching and wet etching, and dry etching is performed by using high-pressure argon gas for sputtering etching, and in wet etching, when the adhesion/barrier layer 18 is titanium or In the case of titanium tungsten alloy, it can be removed using hydrogen peroxide. Further, when the seed layer 20 is gold, it can be removed by using an iodine-containing etching solution (for example, an etching solution such as potassium iodide).

Therefore, a metal pad 142 is formed on a first pad 16a exposed by the opening 14a of the protective layer 14. The metal pad 142 is formed by an adhesive/barrier layer 18 and is located in the adhesion/barrier layer. A sub-layer 20 on the 18 is formed with a metal layer 140 on the seed layer 20, and the metal pad 142 can be bonded to a wire (such as a gold wire or a copper wire) to bond a metal bump of an external circuit. a block (such as a gold bump), a tin-containing metal layer bonded to an external circuit, a tin-containing metal ball (using a ball-planting process), a bonding tape (using tape bonding technology) or anisotropic The conductive paste is bonded to an external circuit.

Referring to FIG. 10C, after the process is completed, the semiconductor substrate 2 can be subsequently cut to form a plurality of semiconductor wafers 144, wherein each of the semiconductor wafers 144 includes a semiconductor substrate 2, a wiring structure 6, and a plurality of dielectric layers. 12. A protective layer 14 and at least one metal pad 142 and the like. In addition, a plurality of semiconductor elements 4 (eg, transistors or metal oxide semiconductors, etc.) are located in or above the semiconductor substrate 2, and one of the semiconductor elements 4 is selectively positioned below the metal pads 142, and the semiconductors One of the components 4 is electrically connected to the metal pad 142. Further, in each semiconductor wafer 144, the top of the protective layer 14 may be an oxonium compound layer or a ruthenium nitride compound layer. Next, after forming the plurality of semiconductor wafers 144, a wire bonding wire 146 (for example, gold wire or copper wire) is formed through the wire bonding process to bond a second pad 16b of the semiconductor wafer 144 where the metal pads 142 are not formed.

Therefore, each semiconductor wafer 144 can be bonded to the external circuit by a wire bonding process on the second pad 16b where the metal pad 142 is not formed, and the external circuit can be connected to the external circuit through the metal pad 142. The external circuit can be a semiconductor wafer or a printed circuit. a circuit board, a flexible board, a substrate containing a ceramic material, a glass substrate or a previously formed passive component, wherein the printed circuit board contains glass fibers, and the flexible board comprises a polymer layer having a thickness of between 30 micrometers and 200 micrometers. The polymer layer is, for example, a polyimide. The method of connecting the external circuit to the metal pad 142 includes: forming a wire bonding wire (for example, a gold wire or a copper wire) through the wire bonding process to bond the metal pad 142, and then connecting with an external circuit; 2. bonding the sticker through the tape bonding automatic bonding technology. Brought to the metal pad 142, and further connected to an external circuit, wherein the tape has at least one metal line and at least one polymer layer, and the metal line connects the metal pad 142, for example, through a tin metal or tin-silver alloy joint metal connection Pad 142; three, using metal bumps (such as gold bumps) to join the metal pads 142, and then connected with an external circuit; Fourth, through the thermal compression process, the metal pads 142 pressed into the anisotropic conductive adhesive The metal particles in the anisotropic conductive paste are collected between the metal pad 142 and a pad of an external circuit (such as a glass substrate) containing indium tin oxide, thereby electrically connecting the metal pads 142. a pad containing an indium tin oxide with an external circuit; 5. bonding the metal pad 142 with a tin-containing metal layer or a tin-containing metal ball, and further connecting with an external circuit.

In addition, in this embodiment, before the semiconductor substrate 2 is cut, a tin-containing metal layer, a tin-containing metal ball or a metal bump (such as a gold bump) is bonded to the metal pad 142, and then an external circuit is connected, and the external circuit can be A semiconductor wafer, a printed circuit board, a flexible board, a substrate containing a ceramic material, or a previously formed passive component, wherein the printed circuit board contains glass fibers, and the flexible board includes a polymer layer having a thickness of between 30 micrometers and 200 micrometers. This polymer layer is, for example, a polyimide. Next, the semiconductor substrate 2 is diced to form a plurality of semiconductor wafers. Finally, the wire bonding wires 146 are bonded by a wire bonding process on the second pads 16b of each of the semiconductor wafers 144 where the metal pads 142 are not formed.

Referring to FIG. 10D, in this embodiment, a polymer layer 39 may be formed on the protective layer 14 and exposed to a polymer layer opening 39a and a polymer layer opening 39b in the polymer layer 39, respectively. A first pad 16a and a second pad 16b are formed, and then a plurality of semiconductor wafers 144a are formed in accordance with the process steps described in FIGS. 10A to 10C. Each of the semiconductor wafers 144a can be connected to the external wiring by using a wire bonding process on the second pads 16b on which the metal pads 142 are not formed, and connected to the external circuit through the metal pads 142. For details, please refer to the above. Detailed description. In addition, the polymer layer 39 is selected from the group consisting of polyimine, phenylcyclobutene, polyurethane, epoxy resin, parylene polymer, solder mask material, elastic material or porous dielectric material. First, the method of forming the polymer layer 39 may be performed by a hot press dry film method or a screen printing method in addition to the spin coating method, and the thickness of the other polymer layer 39 is between 1 μm and 30 μm.

Furthermore, the present embodiment can also be applied to a reconfiguration line or a connection line as in the second embodiment. Referring to FIGS. 10E and 10F, the present embodiment can simultaneously form a metal line 40 as a reconfiguration line and a metal line 42 as a connection line over the semiconductor substrate 2. For the method of forming, please refer to the second implementation. content. Then, according to the process steps described in FIG. 10A to FIG. 10B, the metal pads 142 are formed on the metal lines 40 and 42 exposed by the polymer layer opening 60a. Please refer to the above description for details. Add a narrative. Further, the wire bonding wire 146 is bonded to the bonding pad 46 on which the metal wires 40 and 42 are not formed on the semiconductor wafer 144b (shown in FIG. 10E) or the semiconductor wafer 144c (shown in FIG. 10F), and is passed through the metal. Please refer to the above description for the connection of the external circuit to the pad 142. However, in the above manner, the present invention can also form only the relocation line or the connection line on the semiconductor substrate 2, and further form the metal pad 142 on the reconfiguration line or the connection line, and after being cut into the semiconductor wafer, The wire bonding wires 146 are joined by the wire bonding process on the pads 46 to which the metal wires 40 and 42 are not formed, and the external circuits are connected through the metal pads 142.

Eighth embodiment:

Referring to FIG. 11A, after the process step shown in FIG. 2A is completed, a photoresist layer 148 is formed on the seed layer 20, and the photoresist layer 148 is patterned by an exposure and development process to form a photoresist. The layer opening 148a is within the photoresist layer 148 and exposes the seed layer 20 positioned above the first pad 16a, and is exposed during exposure of the photoresist layer opening 148a, such as by a double exposure machine or scanner.

Referring to FIG. 11B, a metal layer 150 having a thickness between 1 micrometer and 500 micrometers is formed on the seed layer 20 exposed by the photoresist layer opening 148a, and the metal layer 150 is formed by electroplating or It is electroless plating. In addition, the metal layer 150 may be a single metal layer structure of gold, copper, silver, palladium, platinum, rhodium, ruthenium, iridium or nickel, or a composite layer composed of the above metal materials, and the preferred thickness thereof is Between 2 microns and 30 microns. For example, the metal layer 150 may be a gold layer formed by electroplating between 8 micrometers and 35 micrometers or a copper layer formed by electroplating between 8 micrometers and 35 micrometers. . Alternatively, the metal layer 150 is formed by, for example, plating a copper layer having a thickness of between 8 micrometers and 35 micrometers on a seed layer 20 of, for example, copper, followed by plating between 0.1 micrometers and 10 micrometers. A nickel layer (preferably having a thickness between 0.1 micrometers and 5 micrometers) is on the copper layer, and the final plating thickness is between 0.01 micrometers and 10 micrometers (preferably, the thickness is between 0.1 micrometers and 2 micrometers). A gold layer on the nickel layer.

In addition, the metal layer 150 may be replaced by a tin-containing metal in addition to the metal material mentioned above, and the tin-containing metal is a tin-lead alloy, a tin-silver alloy, a tin-silver-copper alloy or a lead-free alloy, and the preferred thickness thereof is Between 3 microns and 250 microns. In addition, when the metal layer 150 is a tin-containing metal layer, a diffusion barrier layer (not shown in the drawing, see the foregoing description) is exposed in the photoresist layer opening 148a before the metal layer 150 is formed. On the seed layer 20, a metal layer 150 is further formed on the diffusion barrier layer, wherein the diffusion barrier layer is, for example, a nickel layer having a thickness of 0.1 μm to 5 μm and a thickness of 0.5 μm to 10 μm. A copper layer with a nickel layer on the copper layer.

Referring to FIG. 11C, after the metal layer 150 is formed, the photoresist layer 148 is removed. Next, a photoresist layer 152 is formed on the seed layer 20, and the photoresist layer 152 is patterned by an exposure and development process to form a photoresist layer 152a on the seed layer 20 above the second pad 16b, as shown in FIG. As shown, in the process of forming the photoresist layer 152a, for example, exposure is performed by a double exposure machine or a scanner. Continuing, as shown in FIG. 11E, the seed layer 20 and the adhesion/barrier layer 18 that are not under the metal layer 150 and under the photoresist layer 152a are removed. The method of removing the adhesion/barrier layer 18 can be divided into dry etching and wet etching, and dry etching is performed by using high-pressure argon gas for sputtering etching, and in wet etching, when the adhesion/barrier layer 18 is titanium or In the case of titanium tungsten alloy, it can be removed using hydrogen peroxide. Further, when the seed layer 20 is gold, it can be removed by using an iodine-containing etching solution (for example, an etching solution such as potassium iodide). Next, after the seed layer 20 and the adhesion/barrier layer 18 are removed, the photoresist layer 152a is removed, as shown in FIG. 11F.

Therefore, a metal pad 154 is formed on a first pad 16a exposed by the opening 14a of the protective layer 14. The metal pad 154 is formed by an adhesive/barrier layer 18 and is located on the adhesion/barrier layer. A sub-layer 20 on the 18 is formed with a metal layer 150 on the seed layer 20, and the metal pad 154 can be bonded to a wire (such as a gold wire or a copper wire) to bond a metal bump of an external circuit. Block (such as gold bumps), bonding a tin-containing metal layer to one of the external circuits, bonding a tin-containing metal ball (using a ball-planting technique), bonding a tape (using tape bonding technology) or by anisotropic The conductive paste is bonded to an external circuit. In addition, a metal pad 156 is formed on a second pad 16b exposed by the opening 14a of the protective layer 14. The metal pad 156 is formed by an adhesive/barrier layer 18 and is positioned on the adhesion/barrier layer. A sub-layer 20 is formed on the 18, and the metal pad 156 can be bonded to a wire (such as a gold wire or a copper wire), a metal bump (such as a gold bump) bonded to an external circuit, and an external circuit is bonded. One of the tin-containing metal layers, a tin-containing metal ball (using a ball-fed technique), a bonding tape (using tape bonding technology) or an external circuit through an anisotropic conductive paste.

Referring to FIG. 11G, after the above process is completed, the semiconductor substrate 2 can be subsequently cut to form a plurality of semiconductor wafers 158, wherein each semiconductor wafer 158 includes a semiconductor substrate 2, a wiring structure 6, and a plurality of dielectric layers. 12. A protective layer 14, at least one metal pad 154, at least one metal pad 156, and the like. In addition, a plurality of semiconductor elements 4 (eg, transistors or metal oxide semiconductors, etc.) are located in or above the semiconductor substrate 2, and one of the semiconductor elements 4 is selectively positioned on the metal pads 154 or the metal pads 156. Below, two of the semiconductor elements 4 are electrically connected to the metal pads 154 and the metal pads 156, respectively. Further, in each of the semiconductor wafers 158, the top of the protective layer 14 may be an oxonium compound layer or a ruthenium nitride compound layer.

In addition, after the plurality of semiconductor wafers 158 are formed, a metal wire 156 of a semiconductor wafer 158 may be bonded by a wire bonding process to form a wire bonding wire (for example, a gold wire or a copper wire). Therefore, each of the semiconductor wafers 158 can be bonded to the metal wires 156 by a wire bonding process and connected to the external circuit through the metal pads 154. The external circuit can be a semiconductor wafer, a printed circuit board, a flexible board, or a ceramic material. a substrate, a glass substrate or a previously formed passive component, wherein the printed circuit board contains glass fibers, and the flexible board comprises a polymer layer having a thickness of between 30 micrometers and 200 micrometers, such as a polyimide layer . The method of connecting the external circuit of the metal pad 154 includes: forming a wire bonding wire (for example, a gold wire or a copper wire) through the wire bonding process to bond the metal pad 154, and then connecting with an external circuit; 2. bonding the sticker through the tape bonding automatic bonding technology. Brought to the metal pad 154, and further connected to an external circuit, wherein the tape has at least one metal line and at least one polymer layer, and the metal line connects the metal pad 154, for example, through a tin metal or tin-silver alloy joint metal connection Pad 154; three, using metal bumps (such as gold bumps) to join the metal pads 154, and then connected to an external circuit; Fourth, through the thermal compression process, the metal pads 154 pressed into the anisotropic conductive adhesive The metal particles in the anisotropic conductive paste are collected between the metal pad 154 and a pad of an external circuit (such as a glass substrate) containing indium tin oxide, thereby electrically connecting the metal pads. 154 and an indium tin oxide-containing pad of the external circuit; 5. The metal pad 154 is bonded by the tin-containing metal layer or the tin-containing metal ball, and further connected to an external circuit.

In addition, the present embodiment can also bond a tin-containing metal layer, a tin-containing metal ball or a metal bump (such as a gold bump) to the metal pad 154 before the semiconductor substrate 2 is cut, thereby connecting an external circuit. A semiconductor wafer, a printed circuit board, a flexible board, a glass substrate, a substrate containing a ceramic material, or a previously formed passive component, wherein the printed circuit board contains glass fibers, and the flexible board includes a thickness of between 30 micrometers and 200 micrometers. A polymer layer, such as a polyimide. Next, the semiconductor substrate 2 is diced to form a plurality of semiconductor wafers 158. Finally, the metal pads 156 of each semiconductor wafer 158 are bonded by wire bonding processes such as gold wires or copper wires.

Referring to FIG. 11H, in this embodiment, a polymer layer 39 may be formed on the protective layer 14 and exposed to a polymer layer opening 39a and a polymer layer opening 39b in the polymer layer 39, respectively. A first pad 16a and a second pad 16b are formed, and then the first pad 16a exposed by the metal pad 154 in the polymer layer opening 39a is formed according to the process steps described in FIGS. 11A to 11F. The above, and the formation of the metal pad 156 on the second pad 16b exposed by the polymer layer opening 39b, please refer to the above description, and will not be described in detail herein. In addition, the polymer layer 39 is selected from the group consisting of polyimine, phenylcyclobutene, polyurethane, epoxy resin, parylene polymer, solder mask material, elastic material or porous dielectric material. First, the method of forming the polymer layer 39 may be performed by a hot press dry film method or a screen printing method in addition to the spin coating method, and the thickness of the other polymer layer 39 is between 1 μm and 30 μm. Please refer to the above for related applications of the semiconductor wafer 158a shown in FIG. 11H, and will not be described here.

Furthermore, the present embodiment can also be applied to a reconfiguration line or a connection line as in the second embodiment. Please refer to FIG. 11I and FIG. 11J at the same time. In this embodiment, the metal line 40 as the reconfiguration line and the metal line 42 as the connection line can be simultaneously formed on the semiconductor substrate 2, and the method for forming is related to the second implementation. content. Next, in accordance with the process steps described in FIGS. 11A-11F, the metal pads 154 are formed on the metal lines 40 exposed by the polymer layer openings 60a and the metal pads 156 are formed exposed in the polymer layer openings 60a. Please refer to the above description for the metal line 42 and the details are not described here. Further, regarding the metal pad 156 of the semiconductor wafer 158b (shown in FIG. 11I) or the semiconductor wafer 158c (shown in FIG. 11J), the wire bonding wire is bonded by a wire bonding process, and the external circuit is connected through the metal pad 154. Please also refer to the above instructions. However, in the above manner, the present invention can also form only the reconfiguration line or the connection line above the semiconductor substrate 2, thereby forming the metal pad 154 and the metal pad 156 on the reconfiguration line or the connection line, and cutting After being a semiconductor wafer, the wire bonding wire is bonded to the metal pad 156 by a wire bonding process, and the external circuit is connected through the metal pad 154.

The above description of the embodiments of the present invention is intended to be understood by those skilled in the art, and the invention may be practiced without departing from the scope of the invention. Equivalent modifications or modifications made by the spirit of the invention should still be included in the scope of the claims described below.

2. . . Semiconductor substrate

4. . . Semiconductor component

6. . . Line structure

8. . . Metal circuit layer

10. . . Metal plug

12. . . Dielectric layer

14. . . The protective layer

14a. . . Opening

16. . . Pad

16a. . . First pad

16b. . . Second pad

18. . . Adhesive/barrier layer

20. . . Seed layer

20’. . . Seed layer

twenty two. . . Photoresist layer

22a. . . Photoresist layer opening

twenty four. . . Metal layer

26. . . Metal pad

28. . . Adhesive/barrier layer

30. . . Seed layer

32. . . Photoresist layer

32a. . . Photoresist layer opening

34. . . Diffusion barrier

36. . . Tin-containing metal layer

38. . . Semiconductor wafer

38’. . . Semiconductor wafer

39‧‧‧ polymer layer

39a‧‧‧ polymer layer opening

39b‧‧‧ polymer layer opening

40‧‧‧Metal lines

42‧‧‧Metal lines

44‧‧‧Protective layer

44a‧‧‧ openings

46‧‧‧ pads/copper pads

48‧‧‧ polymer layer

48a‧‧‧ polymer layer opening

48b‧‧‧ polymer layer opening

52‧‧‧Adhesive/barrier layer

54‧‧‧ seed layer

56‧‧‧Photoresist layer

56a‧‧‧ photoresist layer opening

58‧‧‧metal layer

60‧‧‧ polymer layer

60a‧‧‧ polymer layer opening

62‧‧‧Semiconductor wafer

62’‧‧‧Semiconductor wafer

64‧‧‧Semiconductor wafer

66‧‧‧Semiconductor wafer

68‧‧‧Metal pads

70‧‧‧Metal pads

72‧‧‧ polymer

74‧‧‧Metal lines

76‧‧‧ polymer layer

78‧‧‧Soft tape

79‧‧‧metal layer

80‧‧‧ polymer

82‧‧‧ photoresist layer

82a‧‧‧ photoresist layer

84‧‧‧Metal pads

86‧‧‧Semiconductor wafer

87‧‧‧Semiconductor wafer

87’‧‧‧Semiconductor wafer

88‧‧‧ copper layer

90‧‧‧ copper layer

92‧‧‧ Nickel layer

94‧‧‧ gold layer

95‧‧‧ pads

96‧‧‧Metal pads

97‧‧‧External Circuit

97’‧‧‧External Circuit

98‧‧‧ tin-containing metal ball

98’‧‧‧ tin-containing metal layer

99‧‧‧Semiconductor wafer

99a‧‧‧Semiconductor wafer

99b‧‧‧Semiconductor wafer

99c‧‧‧Semiconductor wafer

100. . . Photoresist layer

100a. . . Photoresist layer opening

102. . . Metal layer

104. . . Photoresist layer

104a. . . Photoresist layer opening

106. . . Metal layer

108. . . Metal pad

110. . . Metal pad

112. . . Semiconductor wafer

112a. . . Semiconductor wafer

112b. . . Semiconductor wafer

112c. . . Semiconductor wafer

114. . . Photoresist layer

114a. . . Photoresist layer opening

116. . . Metal layer

118. . . Metal pad

120. . . Semiconductor wafer

120a. . . Semiconductor wafer

120b. . . Semiconductor wafer

120c. . . Semiconductor wafer

122. . . Semiconductor wafer

124. . . Semiconductor wafer

126. . . Metal pad

128. . . Metal pad

130. . . Metal pad

132. . . Wire thread

134. . . polymer

136. . . polymer

138. . . Photoresist layer

138a. . . Photoresist layer opening

140. . . Metal layer

142. . . Metal pad

144. . . Semiconductor wafer

144a. . . Semiconductor wafer

144b. . . Semiconductor wafer

144c. . . Semiconductor wafer

146. . . Wire thread

148. . . Photoresist layer

148a. . . Photoresist layer opening

150. . . Metal layer

152. . . Photoresist layer

152a. . . Photoresist layer

154. . . Metal pad

156. . . Metal pad

158. . . Semiconductor wafer

158a. . . Semiconductor wafer

158b. . . Semiconductor wafer

158c. . . Semiconductor wafer

Figure 1 is a schematic cross-sectional view of a wafer of the present invention.

2A to 2I are schematic cross-sectional views showing a process of an embodiment of the present invention.

3A to 3E are schematic cross-sectional views showing a process of an embodiment of the present invention.

4 is a cross-sectional view showing a multi-chip package structure according to an embodiment of the present invention.

5A to 5K are schematic cross-sectional views showing a process according to an embodiment of the present invention.

6A to 6J are schematic cross-sectional views showing a process of an embodiment of the present invention.

7A to 7G are schematic cross-sectional views showing a process of an embodiment of the present invention.

8A to 8F are schematic cross-sectional views showing a process of an embodiment of the present invention.

Figure 9 is a cross-sectional view showing a multi-chip package structure according to an embodiment of the present invention.

10A to 10F are schematic cross-sectional views showing a process according to an embodiment of the present invention.

11A to 11J are schematic cross-sectional views showing a process of an embodiment of the present invention.

64. . . Semiconductor wafer

66. . . Semiconductor wafer

68. . . Metal pad

70. . . Metal pad

72. . . polymer

74. . . Metal line

76. . . Polymer layer

78. . . Soft tape

79. . . Metal layer

80. . . polymer

Claims (26)

A chip package structure comprising: a semiconductor substrate; a first copper pad over the semiconductor substrate; a second copper pad over the semiconductor substrate; a first metal line over the semiconductor substrate at the first And a copper pad on the second copper pad, wherein the first metal line contacts an upper surface of the first copper pad and contacts an upper surface of the second copper pad, the first copper pad is connected via the first metal line a second copper pad, the first metal line includes a first adhesion/barrier layer, a first seed layer and a first copper layer, the first seed layer is located on the first adhesion/barrier layer, the first a copper layer is disposed on the first seed layer, the material of the first seed layer comprises copper, the thickness of the first copper layer is between 2 micrometers and 20 micrometers, and the first adhesion/barrier layer is The first seed layer does not contact the sidewall of the first copper layer; a polymer layer is located above the first metal line, wherein a first opening is located in the polymer layer, above the first metal line, at the first Above a copper pad and bit Above the second copper pad; a first metal pad is located on the polymer layer, in the first opening, on the first metal line, above the first copper pad, and on the second copper pad The first metal pad contacts the upper surface of the first metal line under the first opening, and the first metal pad connects the first copper pad and the second copper pad via the first metal line , the first a metal pad includes a second adhesion/barrier layer, a second seed layer and a second copper layer, the second seed layer is located on the second adhesion/barrier layer, and the second copper layer is located at the first On the two seed layers, above the polymer layer, and vertically and vertically above the first copper pad and above the second copper pad, the material of the second seed layer comprises copper, and the second adhesion/barrier The layer and the second seed layer are not in contact with the sidewall of the second copper layer; a polymer material contacting the sidewall of the first metal pad; and a printed circuit board connecting the first metal pad. The wafer package structure of claim 1, wherein the semiconductor substrate is a germanium substrate, a gallium arsenide substrate or a germanium germanium substrate. The chip package structure of claim 1, further comprising an insulating layer over the semiconductor substrate, the first metal line further on the insulating layer, and contacting the upper surface of the insulating layer, the first metal The circuit is connected to the first copper pad via a second opening in the insulating layer and to the second copper pad via a third opening in the insulating layer, the second opening is located above the first copper pad, The third opening is located above the second copper pad, and the first opening is further above the second opening and above the third opening. The wafer package structure of claim 3, wherein the insulating layer comprises an oxonium compound, a cerium compound or a oxynitride compound. The wafer package structure of claim 3, wherein the insulating layer is a polymer. The chip package structure according to claim 1, wherein the The material of an adhesive/barrier layer is selected from the group consisting of titanium, titanium nitride, titanium tungsten alloy, tantalum, tantalum nitride, chromium or chromium copper alloy, and the material of the second adhesive/barrier layer is selected from titanium and nitride. Titanium, titanium tungsten alloy, tantalum, tantalum nitride, chromium or chromium copper alloy. The chip package structure of claim 1, wherein the second copper layer has a thickness of between 8 micrometers and 35 micrometers. The chip package structure of claim 1, wherein the first metal line is connected to a power line or a ground line. The chip package structure of claim 1, wherein the first metal pad further comprises a metal layer above the second copper layer, and the material of the metal layer comprises gold. The chip package structure of claim 1, wherein the first metal pad further comprises a metal layer above the second copper layer, and the material of the metal layer comprises nickel. The chip package structure of claim 1, wherein the first metal pad further comprises a first metal layer and a second metal layer, the first metal layer being above the second copper layer, the first The second metal layer is disposed above the first metal layer, the material of the first metal layer comprises nickel, and the material of the first metal layer comprises gold. The chip package structure of claim 1, further comprising: a third copper pad over the semiconductor substrate; a second metal line over the semiconductor substrate and located at the semiconductor substrate On the third copper pad, the second metal line contacts the upper surface of the third copper pad, the second metal line is at the same level as the first metal line, and the polymer layer is further located above the second metal line, and a second opening is located in the polymer layer and above the second metal line; and a second metal pad is located on the polymer layer, in the second opening, and on the second metal line, The second metal pad contacts the upper surface of the second metal line under the second opening, and the second metal pad is connected to the third copper pad via the second metal line, and the second metal pad is not located Above the third copper pad, the second metal pad comprises a third adhesion/barrier layer, a third seed layer, a third copper layer and a tin-containing metal layer, and the third seed layer is located at the third On the adhesion/barrier layer, the third copper layer is located on the third seed layer, the tin-containing metal layer is located above the third copper layer, the material of the third seed layer comprises copper, and the third adhesion/resistance The barrier layer is not in contact with the third seed layer. The side walls of the copper layer. The chip package structure of claim 1, further comprising a tin-containing metal, the printed circuit board connecting the first metal pad via the tin-containing metal. A chip package structure comprising: a semiconductor substrate; a first copper pad over the semiconductor substrate; a second copper pad over the semiconductor substrate; a third copper pad over the semiconductor substrate; a metal line over the semiconductor substrate and at the a first copper pad, wherein the first metal line contacts an upper surface of the first copper pad, the first metal line includes a first metal layer and a first copper layer, and the first copper layer is located at the first metal layer The material of the first metal layer comprises copper, the thickness of the first copper layer is between 2 micrometers and 20 micrometers, and the first metal layer does not contact the sidewall of the first copper layer; a second metal a circuit, located above the semiconductor substrate, on the second copper pad and on the third copper pad, wherein the second metal line contacts an upper surface of the second copper pad and contacts an upper surface of the third copper pad, the first The second copper pad is connected to the third copper pad via the second metal line, the second metal line is at the same level as the first metal line, and the second metal line comprises a second metal layer and a second copper layer. The second copper layer is located on the second metal layer, the second metal layer is made of copper, the second copper layer has a thickness of between 2 micrometers and 20 micrometers, and the second metal layer is not in contact with the second metal layer. Side wall of the second copper layer; a polymer layer, bit Above the first metal line, above the second metal line and between the first metal line and the second metal line, wherein a first opening in the polymer layer is above the first metal line And a second opening in the polymer layer is located above the second metal line, above the second copper pad and above the third copper pad; a first metal pad is located at the polymer a layer on the first opening and on the first metal line, wherein the first metal pad contacts an upper surface of the first metal line under the first opening, the first a metal pad includes a third metal layer and a third copper layer, the third copper layer is located on the third metal layer, the material of the third metal layer comprises copper, and the third metal layer does not contact the first metal layer a sidewall of the triple copper layer; a second metal pad on the polymer layer, in the second opening, on the second metal line, and vertically and vertically above the second copper pad and at the first Above the three copper pads, wherein the second metal pad contacts an upper surface of the second metal line under the second opening, and the second metal pad connects the second copper pad and the second via the second metal line a third copper pad, the second metal pad comprises a fourth metal layer and a fourth copper layer, the fourth copper layer is located on the fourth metal layer, the material of the fourth metal layer comprises copper, and the fourth The metal layer does not contact the sidewall of the fourth copper layer; and a printed circuit board connecting the first metal pad and the second metal pad. The wafer package structure of claim 14, wherein the semiconductor substrate is a germanium substrate, a gallium arsenide substrate or a germanium germanium substrate. The chip package structure of claim 14, further comprising an insulating layer over the semiconductor substrate, the first metal line and the second metal line being further on the insulating layer and contacting the insulating layer a first metal line connecting the first copper pad via a third opening in the insulating layer, the second metal line connecting the second copper pad via a fourth opening in the insulating layer a first in the insulating layer The fifth opening is connected to the third copper pad, the third opening is located above the first copper pad, the fourth opening is located above the second copper pad, the fifth opening is located above the third copper pad, and the second opening Also located above the fourth opening and above the fifth opening. The wafer package structure of claim 16, wherein the insulating layer comprises an oxonium compound, a cerium compound or a oxynitride compound. The wafer package structure of claim 16, wherein the insulating layer is a polymer. The chip package structure of claim 14, wherein the second metal line is connected to a power line or a ground line. The chip package structure of claim 14, wherein the first metal pad further comprises a fifth metal layer above the third copper layer, and the material of the fifth metal layer comprises gold. The chip package structure of claim 14, wherein the second metal pad further comprises a fifth metal layer above the third copper layer, and the material of the fifth metal layer comprises nickel. The chip package structure of claim 14, wherein the second metal pad further comprises a fifth metal layer and a sixth metal layer, the fifth metal layer being above the fourth copper layer, the first The sixth metal layer is located above the fifth metal layer, the material of the fifth metal layer comprises nickel, and the material of the sixth metal layer comprises gold. The chip package structure of claim 14, wherein the third copper layer has a thickness of between 8 micrometers and 35 micrometers, and the fourth copper layer The thickness of the layer is between 8 microns and 35 microns. The wafer package structure of claim 14, wherein the first metal layer has a thickness of between 0.1 μm and 0.7 μm, and the third metal layer has a thickness of 0.1 μm to 0.7 μm. between. The chip package structure of claim 14, further comprising a polymer material contacting the sidewall of the first metal pad. The chip package structure of claim 14, wherein the first opening and the first metal pad are not located above the first copper pad.