TWI376758B - Chip package and method for fabricating the same - Google Patents

Description

1376758 IX. Description of the Invention: [Technical Field] The present invention relates to a chip package structure and a method of fabricating the same, and more particularly to a chip package structure having different types of metal pads over the same semiconductor substrate and fabrication thereof method. [Prior Art] In today's highly information-based society, the market for multimedia applications is rapidly expanding. The integrated circuit packaging technology also needs to cooperate with the digitalization of electronic devices, the development of network, regional connectivity and the use of humanization. . In order to achieve the above requirements, it is necessary to strengthen the high-speed processing, multi-functioning, accumulating, lightweight and low-cost requirements of electronic components, so that the integrated circuit packaging technology is also becoming miniaturized and high. Density development, so Ball Grid Array 'BGA, Chip_Scale Package, csp, Flip Chip 'F/C and multi-chip module ^Multi- High-density integrated circuit packaging technology such as Chip Module, MCM) has also emerged. For high-density integrated circuit packages, shortening the length of the connection line will increase the speed of signal transmission, so the application of bumps has gradually become the mainstream of high-density packaging. In addition, in these package structures, a solder bump is used as a conductor for electrically connecting a semiconductor crystal to another semiconductor wafer, and also forms a plurality of wires by a wire-bonding process. Wire-bonding wires connect the semiconductor wafer to a printed circuit board. (Printed circuit board) In the conventional technology, the bonding pads on most wafers use aluminum pads (A1 pad), 5 ^76758. Gu-Μ made solder bumps and __ some of the wires used for the wire to make the wire (10) 33 pull the damage 'the reason is; ^ solder & block and Ming must form an adhesion and barrier (barrier) function of the bump underlying metal (1) "over

Metallurgy ' UBM), and the side liquid used in the side of the bump metal usually contains hydrofluoric acid and other buffer solution gamma 〇 1 Qiu 011), hydrogen acid will cause surface damage of the name, and then The welding reliability (reliabilily) of the wire bonding process is not good. SUMMARY OF THE INVENTION It is an object of the present invention to provide a wafer package structure having two different types of metal pads positioned over the same semiconductor substrate. SUMMARY OF THE INVENTION The object of the present invention is to provide a wafer package structure having a pad for connecting one of the tin-containing metal layers and another wire for connecting the wire bonding wires. The L of the present invention is provided with a chip package structure having another pad for connecting one of the tin-containing metal layers and the connection tape. The H of the present invention is provided with a (9) package structure having a junction connecting a tin-containing metal layer and an anisotropic conductive hybrid-external f-path. The purpose of this month is to provide a chip package structure having a pad for bonding an external circuit with an anisotropic conductive paste, and a further pad for attaching the tape. SUMMARY OF THE INVENTION The object of the present invention is to provide a chip package structure having a pad for connecting a wire bonding wire and another connector for connecting the tape. SUMMARY OF THE INVENTION The object of the present invention is to provide a chip package structure having a connection to a wire conductor and an anisotropic conductive hybrid-external circuit (four). 6 1376758 The object of the invention is to provide a (9) package structure having at least two metal pads of different thickness above the same semiconductor substrate. It is an object of the present invention to provide a wafer package structure having a plurality of metal pads of the same thickness above the same semiconductor substrate. For the above purposes, the present invention provides a chip package structure including: a semiconductor substrate; a line structure disposed above the semiconductor substrate and including a first interface and a second pad'-protective layer, Above the line structure, and in the layer - the first opening and the # - second opening respectively expose the first interface and the second pad; - a metal pad, located at The first pad; the tape 'bonds the metal interface; and the tin-containing metal layer is positioned above the second pad. For the above purposes, the present invention provides a wafer package structure comprising: a semiconductor substrate; a wiring structure positioned over the semiconductor substrate and including a first interface and a second interface, the edge layer Above the line structure, a first opening and a second opening in the protective layer respectively expose the first connection and the second difficulty; the metal connection is located on the first φ pad And using an anisotropic conductive paste to connect - an external circuit; and a "tin-containing metal layer" above the splicing pad. - For the above purposes, the present invention proposes a wafer package structure comprising: a semiconductor substrate wiring structure positioned above the semiconductor substrate and comprising a -first junction and a second junction 'protective layer' on the line Above the structure, and the first opening and the first opening in the protective layer respectively expose the first connection and the second connection; the -th metal pad is located on the '~帛 pad, one a second metal joint on the second joint; a tape, joining the 1376758 metal pad; and a wire bonding wire joining the second metal pad. For the above purposes, the present invention provides a chip package structure comprising: a semiconductor substrate and including a first pad and a second pad; a line structure on the pad above the semiconductor substrate; a protective layer, located in Above the line structure, and at the first opening and the second opening respectively exposing the first connection and the second connection; the first metal connection is located on the first pad 'And the green transition joint - external circuit; - two metal joints, located on the second joint; the differential - wire conductor, the second metal joint.

For the purpose of the present invention, the present invention provides a chip package structure comprising: a semiconductor substrate; a line and a structure over the semiconductor substrate, and comprising a first interface and a second pad, a protective layer, Positioned above the line structure, and the first opening and the second opening in the protective layer respectively expose the first pad and the second interface - the metal interface, in the first a pad and an external conductive circuit is bonded by an anisotropic conductive paste; a second metal pad is positioned on the second pad; and a tape is attached to the second metal pad. For the above purpose, the present invention provides a chip package structure comprising: a semiconductor substrate; a line structure disposed above the semiconductor substrate and including a first interface and a second interface; a protective layer located at Above the Weilu structure, the first opening and the first opening π in the protective layer respectively expose the first __ pad and the second rim; the metal pad is connected through the first opening To the first pad; the tape is bonded to the metal pad; and the tin-containing metal layer is connected to the second pad through the second opening. For the purpose of the present invention, the present invention provides a chip package structure comprising: a semiconductor substrate; a line structure disposed above the semiconductor substrate and including a first pad and a pad, and a protective layer disposed thereon a first opening and a second opening respectively in the protective layer, the first pad and the second pad are respectively exposed; a metal pad is connected to the first through the first opening Connecting, and bonding an external circuit with an anisotropic conductive paste; and - a tin-containing metal layer connected to the second pad through the second opening. For the above purpose, the present invention provides a chip package structure comprising: a semiconductor-based circuit structure disposed above the semiconductor substrate and including a first pad and a second pad, and a protective layer disposed thereon Above the circuit structure, a first opening and a first opening in the protective layer respectively expose the first connection and the second connection, and the first connection is connected to the first through the seventh opening a second metal pad connected to the second opening through the second opening. The second interface &gt; tapes the first metal (four); and the wire bonding wire to connect the second metal interface. For the above purposes, the present invention provides a wafer package structure comprising: a semiconductor-via structure disposed above the semiconductor substrate and including a first pad and a second bonding layer over the wiring structure And located in the first opening of the protective layer with The second opening of the P exposes the first pad and the second port respectively; a first metal port is connected to the first port through the opening of the b, and the outer joint is bonded by an anisotropic conductive adhesive a circuit; a - metal interface 'connected to the second age through the second opening °; and - a wire bonding wire connecting the second metal pad. For the above purposes, the present invention provides a chip package structure including a semiconductor-on-line structure positioned over the semiconductor substrate and including an n-pad and a second shielded layer above the line structure. And pulling a first opening in the protective layer and a first opening of 9 1376758 to expose the first pad and the second pad respectively; a first metal pad is connected to the first opening through the first opening a first pad, and an external circuit is bonded by an anisotropic conductive paste, a second metal port is connected to the second pad through the second opening; and a tape is bonded to the second metal pad. For the above purpose, the present invention provides a chip package structure comprising: a semiconductor substrate, a line structure is positioned above the semiconductor substrate, and includes a first pad and a second pad, a protective layer, The first opening and the first opening respectively in the first opening and the first opening of the protective layer respectively expose the first pad and the second pad; a metal pad is connected to the first opening through the first opening a first contact, and the metal pad comprises a gold layer; a tape, bonding the gold layer; and a wire bonding wire connecting the second pad. For the above purpose, the present invention provides a chip package structure comprising: a semiconductor substrate; a line structure is located above the semiconductor substrate and includes a first pad and a second pad, and a protective layer is disposed thereon Above the line structure, and the first opening and the second opening in the protective layer respectively expose the first connection and the second connection; the metal contact is connected to the first through the first opening-opening Connecting, and the metal interface comprises a gold layer and directly connected to the gold layer through an anisotropic conductive paste; and a wire bonding wire connecting the second interface. For the above purpose, the present invention provides a chip package structure comprising: a semiconductor substrate; a line structure is located above the semiconductor substrate and includes a first interface and a second interface; the protective layer is located at Above the circuit structure, and located in the protective layer, the first opening and the second opening respectively expose the first connection and the second connection; the metal pad is connected to the metal through the first opening a first pad' and the metal pad comprises a - gold layer; a metal bump (fertilizer plus 1376758 b,) located on the gold layer; and a wire bonding wire connecting the second pad. The bottom τ borrows (four) time complements the touch _ scale plus the outline, # more to mechanically solve the purpose, technical content, characteristics and the achieved effects of the present invention. [Embodiment] The present invention relates to a semiconductor BsHni (wafer) or a semiconductor (9) (chip) having two kinds of non-type metal pads on the same-semiconductor substrate, and these metal contacts are available. For wire-bonding, metal bump bonding, solder bump bonding, tape aut〇mated b〇nding (ΤΑβ), film polycrystalline bonding or glass In the process of compound bonding and the like. The word "above" means that it is on or in contact with something, or that it is on something but not in contact with it. Each of the structures and methods disclosed in the present invention is constructed on a passivation layer of a semiconductor wafer, and the semiconductor wafer can be diced after construction to form a plurality of semiconductor wafers. Among them, the "up"-line is placed on and in contact with something. The underside of the protective layer includes a semiconductor substrate, and a wiring structure and a plurality of dielectric layers between the protective layer and the semiconductor substrate, and the openings above the semiconductor substrate are exposed through openings located in the protective layer. Structured pads. Therefore, the contents of the semiconductor substrate, the wiring structure, the dielectric layer, the pads, and the protective layer will be described first, followed by the description of various embodiments of the present invention. Referring to FIG. 1 , the semiconductor substrate 2 may be a stellite substrate, an ε-suppressed gallium substrate (GaAs) or a germanium telluride (SiGe) substrate, and a plurality of semiconductor elements 4 are located in or above the semiconductor substrate 2 . among them,. These semiconductor elements 4 include passive elements (such as resistors, capacitors, inductors) or active elements &gt; 11 1376758 pieces, etc., and active elements such as metal oxide semiconductor (MOS) elements, such as P-channel MOS semiconductors. P-channel MOS devices, n-channel MOS devices, biCM devices, Bipolar Junction Transistors, BJT) or complementary metal oxide semiconductor (CMOS). A line structure 6 is located above the semiconductor substrate 2, and the line structure 6 is formed by a plurality of metal circuit layers 8 (having a thickness of, for example, less than 3 μm) and a plurality of metal plugs of "plug" 1 φ, wherein The metal wiring layer 8 and the metal plug 10 are made of copper, or the metal wiring layer 8 is made of aluminum, and the metal plug 10 is made of tungsten. Further, the manner of forming the metal wiring layer 8 includes There is a post-town process (damascene process), electric clock.  An electroplating process or a sputtering process, for example, forming a copper wiring layer 8 by a damascene process, an electric clock process, or a demining process, or forming a metal wiring layer 8 by a sputtering process. A plurality of dielectric layers 12 (having a thickness of, for example, less than 3 micrometers) are positioned over the semi-φ conductor substrate 2, and the metal wiring layers 8 are positioned between the dielectric layers 12 and are transmissive The metal plugs 10 in the dielectric layers U connect the metal wiring layers 8 of the two adjacent layers. In addition, the dielectric layer 12 is generally formed by a chemical vapor deposition (CVD) method, and the dielectric layer 12 is, for example, an oxygen oxide compound (for example, Si〇2), four. Oxide oxide (TEOS) oxide, compound containing %, carbon, oxygen and hydrogen (eg siwCxOyHz), cyclone compound (eg Si3N4), Fluorinated Silicate Glass (FSG), black diamond film ( Black Diamond), silk screen layer (siLK), porous oxidized dream (porous si 1 icon oxide) 12 1376758 or oxynitride compound, or glass formed by spin coating (SOG), polyarylene ether , polyphenyl hydrazine, saliva (p〇iybenzoxaz〇ie, pB〇), or other dielectric constant value (k) is between 1.  Material between 5 and 3. The & layer 14 is above the line structure 6 and the dielectric layer 12, and the protective layer 保护 can protect the semiconductor element 4 and the line structure 6 from moisture and foreign ion contaminants (five _ηί〇η contaminatioii). That is to say, the new layer 14 can continue to move the lining (such as nano-ion) Kmoisture), transition metals (such as gold, silver, copper) and other impurities (impurity) and penetrate the semiconductor under the protective layer 14. Element 4 (for example a transistor, a polycrystalline resistive element or a polysilicon-polysilicon capacitor) or a line structure 6 » .  The protective layer 14 is usually composed of an oxonium compound (for example, SiO 2 ), a phosphorous bismuth glass (P_-teGlass, PSG), a nitrocarburic compound (for example, &amp;amp; or a oxynitride compound, etc. Wei compound Bao Cai Wei recorded the seamless, the thickness of the protective layer 14 - the general system is greater than 〇. 35 micrometers (-), and in the case of a layer comprising a nitrogen compound, the thickness of the nitrogen compound layer is usually greater than 〇·3 μm. The current manufacturing method of the protective layer 14 is about ten different methods, which are as follows. The first type of production layer 14 is the first chemical gas to form a thickness of 0. 2 • Micro to 1. Between the 2 micrometers and the oxidized stone layer, followed by chemical vapor deposition to form a thickness of 0.  A layer of nitriding between 2 micrometers and 1 micrometer is on the layer of oxidized stone. The second method of making the protective layer is to use chemical ammonia phase deposition to form a layer of oxidized stone between 〇2 micrometers and L2 micrometers, and continue to utilize electro-destructive enhanced chemical vapor deposition (Plasma Enhanced Chemical Vapor). D-printed ositi〇n, pEcvD) formed a thickness of between 113 1376758 micrometers to 〇_15 micrometers on the nitrous oxide alone on the oxygen-cut layer, and then _ chemical vapor lancet into a thickness of 2 microns to i.  2 reddish _ - nitrogen cut layer on the record cut reed. The third method for making a protective layer is to first form a layer of arsenic oxide with a thickness between 〇〇5 μm and (U5 μm) by chemical vapor deposition, and continue to use the chemical vapor phase to thicken the lion. · 2 micro red 丨. 2 «(10) - Secret rhyme money oxidation on the conversion, re-use of chemical vapor deposition to form a thickness of 0.  A layer of nitriding layer between 2 microns and L 2 microns is on the oxym layer. • The fourth method of making the protective layer 14 is to first form a thickness of 0 by chemical vapor deposition. 2 microns to 0. The -1 - oxidized stone layer between 5 microns continues to use spin coating (spin c〇a shirt). Forming a thickness between W micrometers and 1 micro--the second oxygen-cut layer on the first layer of oxidized stone, followed by chemical vapor deposition to form a thickness of 0. 2 micro to come. A third layer of oxidized stone between 5 micrometers is layered on the second layer of oxidized stone, and finally formed by chemical vapor deposition to a thickness of between 〇 2 μm and 1.  A layer of nitriding between 2 microns is on the third layer of oxidized stone. The fifth method for fabricating the fiber layer 14 is to form a thickness of 〇 高 Den Den 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、  5 micron to 2 « _ - oxidized pin ' and then paste chemical deposition to form a thickness of 0, 2 microns to 1.  A nitriding dream layer between 2 microns is on the oxidized layer. The sixth method of fabricating the protective layer 14 is to first form a thickness of 0. An undoped silicate glass (USG) between 2 microns and 3 microns continues to form, for example, tetraethoxy decane, borophosphosilicate glass (BPSG) or phosphor bismuth glass. . (phosphosilicate glass, PSG) and the like having a thickness of between 1 μm and 3 μm of a 1376758 insulating layer on the unblended glass layer, followed by chemical vapor deposition to a thickness of between 〇 2 μm and 1.  The r-nitriding layer between 2 microns is on the insulating layer. The seventh _ 倾 层 14 14 14 14 14 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ At 0.  2 micrometers to 2 micro-(four)-oxidized Wei on the arsenic oxynitride layer, and then selectively using chemical vapor deposition to form a second nitrogen having a thickness between 〇〇5 μm and 〇······· The oxidized stone layer is on the oxygen-cut layer, and then formed by chemical vapor deposition to a thickness of 0.  2 microns to! • A layer of nitriding between 2 microns on the second oxidized layer or on the oxidized layer can then be selectively deposited by chemical vapor deposition to a thickness of between 〇 5 μm and 〇.  The 15 um - third nitrous oxide layer is on the nitriding layer and finally deposited by chemical vapor deposition to a thickness of between 〇.  The layer of monoxide between 2 microns and h 2 microns is on the third oxynitride layer or on the tantalum nitride layer. The eighth method for forming the protective layer 14 is to first form a thickness of 〇 2 μm to 1. by chemical vapor deposition.  Between 2 micrometers - the first oxidative complement, __ recording method to form a thickness of u micron to 1 micron _ - second oxide stone M on the first oxygen cut layer, followed by chemical vapor deposition to form a thickness between Hey.  The third oxygen cut layer between 2 micrometers and 2 micrometers is on the second layer of oxide oxide, and then the chemical vapor phase is used to form a thickness of between 〇.  The nitriding pin between 2 micrometers and 12 micrometers is on the third oxidation (four), and finally _ chemical residual deposition to form a thickness between 〇.  2 microns to 1.  A fourth oxidized stone layer between 2 microns is on the tantalum nitride layer. The ninth method of making the protector 14 is that the first high-density chemical gas domain product forms a thickness between 〇.  A first layer of oxidized stone between 5 micro and 2 micro-surgery continues to use chemical vapor deposition 15 1376758 to form a thickness between 〇 2 μm and 2 2 μm - nitriding in the first oxygen cut On the layer, then _ shouting, plasma chemistry, she formed a second yttrium oxide layer with a thickness between G 5 microns and 2 microns on the tantalum nitride layer. The tenth method for making the pour layer 14 is to first form a first-nitridite layer having a thickness between 〇 2 μm and 1, 2 μm by chemical vapor deposition, and continue to form a thickness by chemical vapor deposition. 0. The SiO2 layer between the 2 micro and the L 2 micro-surgery is then deposited on the first nitriding layer by chemical vapor deposition to a thickness of between 〇.  A second layer of tantalum nitride between 2 microns and h 2 microns is on the tantalum oxide layer. 9 Then, as shown in the first embodiment, the opening pad in the protective layer 14 is 16 in which the interface 16 is used for input/output of signals, or is used to connect a power source or ground to form a pad 16 . The method includes an electroplating (electr〇plating) process or a sputtering process, for example, forming a metal or a metal alloy as a pad by a mirror process, or forming a copper as a pinch 16 by a money-making process. 16 is a copper crucible formed by an electric ore process, and has a barrier layer at the bottom and the side of the copper pad. The material ratio of the barrier layer is such as a button (Ta) or tantalum nitride (TaN). . The maximum lateral dimension of the opening 14a is between 5 microns and 40 microns, or between 4 microns and 300 microns. In addition, the shape of the opening i4a may be a circle, a square or a polygon of five or more sides, and the maximum lateral dimension of the opening 14a refers to a straight grip size of the circular opening, a side length dimension of the square opening or a polygonal opening of five or more sides. The longest diagonal size. Further, the shape of the opening 14a may be a rectangle, and the length of the rectangular opening is between 8 〇 micrometers. Between 200 microns and the width dimension is between 40 microns and 11 microns. Alternatively, the semiconductor element 4 may be present under the interface 16 exposed by the opening 14 1376758 or without any semiconductor element 4. A metal top layer (not shown) may be selectively formed over the pads 16 exposed by the openings π 14a in the protective layer 14 to protect the pads 16 from oxidation and damage. The top layer of the metal is, for example, a -, a gold layer, a titanium layer, a titanium tungsten alloy layer, a neodymium nitride layer or a recording layer. For example, when the pad 16 is a copper pad (Cu _, a metal top layer (such as a layer) is needed to protect the copper pad exposed by the opening 14a, so that the copper pad is protected from oxidation and damage. When the top layer of the metal is a layer, a barrier layer is formed between the steel pad and the inscription layer. The barrier layer includes titanium, titanium tungsten alloy, titanium nitride, niobium, and nitrogen. Representation, chromium (Cr) or nickel. The following is only described in the absence of a metal top layer, but those skilled in the art can implement this by bribing the example of the bribe. 2. Related explanations of the circuit structure 6, the dielectric layer 12, the protective layer 14, and the pads 16, etc., respectively, the respective embodiments of the present invention will be sequentially described below. φ First embodiment:  2A to 2H are schematic cross-sectional views showing the process of forming a tin-containing metal layer and a metal pad on a wafer or wafer in the present embodiment. Referring to FIG. 2A, the pad 16 includes a first pad 16a and a second pad 16b, and is formed to have a thickness of 〇.  〇 1 micron to 3 microns (preferably thickness is 0.  A point/barrier layer from 01 μm to 1 μm! ayer) i8 on the protective layer 14 and the first pad 16a and the second pad 16b exposed by the opening 14a. The material of the adhesion/barrier layer 18 17 1376758 is selected from the group consisting of titanium, tungsten, cobalt, nickel, titanium nitride, titanium tungsten alloy, nickel vanadium alloy, button, nitride button, chromium, copper, chrome copper alloy, gold, At least one of a group consisting of ruthenium, platinum, rhodium, ruthenium, osmium, and silver, or formed by, for example, using a Tibetan clock or a steamed shovel. ' Next, the thickness is between 〇.  0 〇 5 μm to 2 μm (the preferred thickness is between 〇丄 micrometers to 0. A seed layer 20 of between 7 microns is formed on the adhesion/barrier layer 18 to form the seed layer 20, such as money plating, evaporation, physical vapor deposition, electricity money, or electroless plating. )The way. This seed layer 20 facilitates the subsequent placement of the metal lines, so the material of the seed layer 20 will vary with the material of the subsequent metal lines. For example, when the seed layer 20 is plated to form a metal layer of copper, the material of the seed layer 20 is made of copper.  When the electric layer of the seed layer 20 forms a metal layer of gold material, the material of the seed layer 2 is preferably gold.  When the seed layer 20 is plated to form a metal layer of palladium material, the material of the seed layer 2 is preferably as good. When the seed layer 20 is plated to form a metal layer of platinum, the material of the seed layer 2 is made of platinum. good.  When the seed layer 20 is plated to form a metal layer of tantalum material, the material of the seed layer 2 is preferably 铑.  When the seed layer 20 is plated to form a metal layer of tantalum material, the material of the seed layer 2 is preferably 钌.  • When the seed layer 20 is plated to form a metal layer of tantalum material, the material of the seed layer 20 is preferably tantalum.  When the seed layer 20 is electrically formed into a metal layer of nickel material, the material of the seed layer 2 is preferably recorded. Referring to FIG. 2B, a photoresist layer 22 is formed on the seed layer 2 and patterned by the exposure and development process to form the photoresist layer 22 to form the photoresist layer opening 22a in the photoresist layer. 22 and exposing the seed layer 2〇 above the first pad 16a, and in the process of forming the photoresist layer opening 22a, for example, by double (10) exposure machine (coffee or (four) or scanners) Then, the metal layer 24 having a thickness between 丨 micrometers and _micrometers (for example, between 1 1376758 micrometers and 50 micrometers) is on the seed layer 2〇 exposed by the photoresist layer opening, the Jinxian 24 The preferred thickness is between 2 micrometers and 3 micrometers to form the metal layer 24, such as electroplating or electroless plating. Alternatively, the metal layer may be gold, copper, silver, Ji, Ming, 铢 or recorded. a single-layer metal layer structure, or a composite layer made of the above-mentioned metal material. The layer, for example, the metal layer 24 may be a gold layer or a crucible having a thickness of between 8 micrometers and 35 micrometers formed by electro-mineralization. a copper layer formed between 8 micrometers and π micrometers thick. For example, a copper layer having a power between 8 micrometers and 35 micrometers is placed on a seed layer 2 of, for example, copper, and then the plating thickness is between (U micrometers to 10 micrometers (preferred thickness). A recording layer between 〇_! microns and 5 microns) is on the copper layer. The final plating thickness is between 〇.  A gold layer of between 1 micrometer and 10 micrometers (preferably having a thickness between micron and 2 micrometers) is on the recording layer. Referring to FIG. 2C, after the metal layer 24 is formed, the photoresist layer 4 is subsequently removed. Continuing, the seed layer 2〇 and the adhesion/barrier layer 18 which are not under the metal layer 24 are removed. Among them, the way to remove the adhesion/barrier layer 18 can be divided into dry etching and wet silver etching (also for sputum), and dry residuals such as high pressure argon gas for scaly side and wet side In the aspect, if the adhesion/barrier layer 18 is titanium or a titanium-tungsten alloy, it can be removed using hydrogen peroxide. Further, if the seed layer 2 is gold, it can be removed by using a liquid engraving liquid containing a dish (for example, a liquid engraving liquid such as potassium). Therefore, a metal pad 26 is formed on a first pad 16a exposed by the opening 14a of the protective layer. The metal interface 26 is formed by a sweet potato/barrier layer 18, which is located in the adhesion/barrier layer. A sub-layer 20 on the 18 is formed with a metal layer 24 on the seed layer 20, and the metal interface 26 can be bonded to a wire conductor (10) such as a gold wire or a copper wire through a wire bonding process, and automatically attached by a tape. 19 1376758 Technically joining a metal strip (such as a gold bump) bonded to an external circuit, a tin-containing metal layer bonded to an external circuit, or an external circuit through an anisotropic conductive paste, wherein the external The circuit may be a semiconductor wafer, a printed circuit board 'PCB', a soft board containing a polymer layer (such as a polyimide) having a thickness between 30 micrometers and 200 micrometers, containing ceramics. The substrate of the material, the glass substrate or the previously formed passive passive device, for example, the metal layer 24 is a gold layer, and when the metal pad 26 is used to bond a wire conductor (for example, a gold wire) The preferred thickness of the layer Between 2 to 10 microns, and when the metal pads 26 for engaging a belt, the preferred thickness of this layer is interposed between the gold 1〇 microns 3〇 microns. • After forming a metal bump for bonding a wire conductor, bonding a tape, bonding an external circuit, • bonding a tin-containing metal layer of an external circuit, or bonding an external circuit through an anisotropic conductive paste, A tin-containing metal layer 36 is then formed over the second pads 16b. Please refer to the figure 2D for the formation of the residence.  An adhesion/barrier layer 28 between 01 micrometers and 3 micrometers (preferably having a thickness between 1 micrometer and 1 micrometer) is exposed on the protective layer 14 at the opening i^a. The connector 16b is on the metal interface 26. The material of the adhesive/barrier layer 28 is 遘自钦,鹤,#, 录, titanium nitride, titanium alloy, nickel hunger alloy, neon, nitrided group, chromium, copper, chrome-copper alloy, gold, town , at least one of or one of the groups of silver and silver, and the form of silver formed by, for example, sputtering or steaming. Then, the thickness is formed to be 0.  Between 005 microns and 2 microns (preferably thickness is between 微1 micron and 0.  The seed layer 30 between the 7 micrometers is on the adhesive/barrier layer, and the square layer forming the seed layer is argon, «, Wei phase deposition, electroplating or no electricity test. 20 = 2_ for the subsequent metal line settings, so the material of _ 3Q will be simplified with the subsequent = line. _, t_ 3Q on the __ quality metal: @ seed layer 3G village system is better with copper; when the seed layer 30 is charged with gold into gold material ^ when the seed layer 30 material fine gold is better. The -* field photoresist layer 32 is on the seed layer 3, and the photoresist layer 32 is patterned through an exposure and development process to form a photoresist layer opening in the photoresist layer 32 and exposed to the second interface. The seed layer above 16b is 3 〇, and during the process of forming the opening of the photoresist layer, for example, it is exposed by double exposure or sweeping. Come again, please participate in the _ 2E riding, forming a diffusion barrier layer (. The f fusion barrier layer 34 is formed on the seed layer 3〇 exposed by the photoresist layer opening 32a, and the manner tb of forming the diffusion barrier layer 34 is such that the thickness of the electric clock is between Q 5 μm and 1 μm. - The copper layer is on the seed layer 3Q of copper, and then the - recording layer having a thickness between Qi microbook and 5 micrometer is in the Jingshang. The @ diffusion layer 34 may be composed of a copper layer and a nickel layer positioned on the copper layer. Next, a tin-containing metal layer 36 having a thickness between 1 micrometer and 500 micrometers is formed on the diffusion barrier layer 34 in the photoresist layer opening 32a. The preferred thickness of the tin-containing metal layer 36 is between 3. The method of forming the tin-containing metal layer 36 between micrometers and 250 micrometers is, for example, an electric clock, an electric powerless boat, or a screen printing. In addition, the tin-containing metal layer 36 is, for example, a tin-lead alloy (^11-1, a 4311〇5〇, a tin-silver alloy, a tin-silver-copper alloy, or a lead-free alloy ( Lead-free alloy. Taking tin-lead alloy as an example, the tin/error ratio can be adjusted according to the demand. The common tin-lead ratio is 90/10, 95/5, 97/3, 99/1, 37/ 63. From the above, the diffusion barrier layer 34 is located below the tin-containing metal layer 36, and the diffusion barrier 21 1376758 layer 34 includes, for example, a thickness of o. A recording layer between 5 micrometers and 5 micrometers is under the tin-containing metal layer and has a thickness of 0. A copper layer between 5 microns and 1 inch is under the nickel layer, and the recording layer and the copper layer are tied above the second pads 16b. In addition, in this embodiment, a solder adhesion layer (not shown) may be formed on the diffusion barrier layer 34 to enhance the subsequent tin-containing metal layer 36 and the diffusion barrier layer 34. The bonding property of the solder-impregnated film layer is, for example, gold, copper, tin, tin-lead alloy, tin-silver alloy, tin-silver-copper alloy or lead-free alloy. • Referring to FIG. 2F, after forming the tin-containing metal layer 36, the photoresist layer 32 is subsequently removed. Continuing, the seed layer 3 and the adhesion/barrier layer 28 that are not under the tin-containing metal layer 36 are removed. Among them, the way to remove the adhesion/blocking I 28 can be divided into dry money and wet side, while the dry side is, for example, argon gas using argon gas, and in the wet side, if the adhesion/transfer layer 28 is titanium or When titanium alloy is used, it can be removed with hydrogen peroxide. Referring to Fig. 2G, a re-welding process is selectively performed to cause the tin-containing metal layer 36 to reach a melting point and cohesively form a spherical shape. However, in this embodiment, the reflow process may be performed first, so that the tin-containing ruthenium layer reaches the melting point and is internally condensed into a spherical shape. Then, the seed layer 30 and the adhesion/barrier layer not under the tin-containing metal layer 36 are removed. 28. Alternatively, the embodiment may not perform the reflow process until then.  The reflow process is performed when the kick-free metal layer 36 is connected to an external circuit, such as a semiconductor wafer, a printed circuit board containing glass fibers, and a polymer having a thickness of between 3 μm and 2 μm. A soft board of a layer, a substrate containing a ceramic material, or a passive component formed in advance. Therefore, the present invention can form 22 Ϊ 376758 on the pads 16 exposed by the partial openings 14a of the protective layer 14 for bonding wire wires (such as gold wires or copper wires) for bonding tapes for bonding. The gold block of the external circuit, the splicing joint-outer (four) (four) tin-containing surface layer or the metal pad 26 of the external circuit through the opposite-junction conductive exposure, and the kick-free metal layer is formed over the joint 16 on which the metal joint 26 is not formed 36. In addition, the top of the metal joint 26 may include a smear layer (峨(四) layer </ ” not shown). The threatening joint is a gold layer. Moreover, before the formation of the tin-containing metal layer 36, a gold layer may also be formed in the diffusion barrier layer. On the 34, a tin-containing gold is then formed; the layer 36 is on the gold layer. In addition, the tin-containing metal layer of the present wealth can also be replaced by a glow bump. Referring to FIG. 2H, after the above process is completed, the semiconductor substrate 2 can be subsequently cut to form a plurality of semiconductor wafers 38'. Each of the semiconductor wafers 38 includes a semiconductor substrate 2, a wiring structure 6, and a plurality of dielectric layers. 12. A protective layer 14, at least one metal pad and at least a tin-containing gold layer 36, and the like. In addition, a plurality of semiconductor elements 4 (eg, transistors or metal oxide semiconductors, etc.) are located in or above the semiconductor substrate 2, and one of the semiconductor elements 4 is selectively positioned on the metal interface 26 or the tin-containing metal layer 36. Below, two of the semiconductor elements 4 are electrically connected to the metal pads 26 and the tin-containing metal layer 36, respectively. Further, in each of the semiconductor wafers 38, the top of the protective layer 14 may be an oxysulfide compound layer or a ruthenium nitride compound layer. Each of the semiconductor wafers 38 can be connected to an external circuit through the tin-containing metal layer 36. The external circuit can be a card conductor chip, a printed circuit board (PCB), or a soft metal.  The board 3 has a substrate of a ceramic material or a discrete passive device in which the printed circuit board contains glass fibers, and the soft board includes a polymer layer having a thickness of between 3 μm and 200 μm. The polymer layer is, for example, a polyimide. 23 1376758 In addition, through a wireb〇nding process, a metal interface 26 of a semiconductor wafer 38 can be bonded to a wire conductor (such as a gold wire or a copper wire) to connect an external circuit, which can be a semiconductor. ", printed circuit board, training, containing (four) storage substrate or lead frame, where the printed circuit board contains glass fiber, and the soft board includes a polymer layer between 3 microns and 2 microns in thickness' The polymer layer is, for example, a polyimide. Further, by using an automatic tape bonding technique, a metal pad 26 of a semiconductor wafer 38 can be bonded to a tape to connect an external circuit. Is a semiconductor wafer, a #printed circuit board, a flexible board or a substrate containing a ceramic material, wherein the printed circuit board contains glass fibers, and the soft board comprises a polymer layer having a residence degree of between 30 micrometers and 200 micrometers. The layer ratio is known as polyimine. In addition, the tape has at least one metal line and at least one polymer layer, and gold. The wire is connected to the metal pads 26, for example by bonding the metal pads 26 via tin metal or tin-silver alloy. Moreover, a metal pad 26 of a semiconductor wafer 38 can be pressed into an anis tropic conductive film (ACF or anis 〇 tr〇 pic conductive paste, ACP) through a thermal compression bonding process. The metal particles in the anisotropic conductive paste are gathered on the pads of the gold-based interface 26 and an external circuit (such as a glass substrate) containing indium tin oxide.  Between the use of electrical connection metal pads 26. A pad containing indium tin oxide with an external circuit. Alternatively, the external circuit may be a semiconductor wafer, a printed circuit board, a flexible board containing a polymer layer having a thickness of between 30 micrometers and 200 micrometers, or a substrate containing a ceramic material. Moreover, one of the metal pads 38 of the semiconductor wafer 38 can be bonded to a metal bump (such as a gold bump) to connect to an external circuit. The external circuit can be a semiconductor wafer, a printed circuit board, a glass substrate, a flexible board, or A substrate of ceramic material, wherein the printed circuit board contains glass fibers, 24 1376758 and the soft board comprises a polymer layer having a thickness of between 3 micrometers and 200 micrometers, such as a polyimide. In this embodiment, before the semiconductor substrate 2 is cut, an external circuit is first connected through the tin-containing metal layer 36. The external circuit may be a semiconductor wafer, a circuit board, a soft board, a substrate containing a ceramic material, or a passive formation in advance. An element in which the printed circuit board contains glass fibers, and the flexible board comprises a polymer layer having a thickness of between 30 micrometers and 2 micrometers, such as a polyimine. Next, the semiconductor substrate 2 is diced to form a plurality of semiconductor wafers. Finally, the present embodiment can be used to bond wire bonds (using a wire bonding process), bond tapes (using tape bonding automated bonding techniques), and metal bumps of the bonding-external circuit on the metal pads 26 of each semiconductor wafer (eg, Gold convex . Block), the tin-containing metal layer of the bonding-external circuit or the external circuit through the external recording. Referring to FIG. 21, in this embodiment, a polymer layer 39 may be formed on the protective layer 14, and the polymer layer opening and the polymer layer opening in the polymer layer 39 are respectively exposed. a first interface 16a and a second interface 16b, and then forming a metal interface 26 on the first interface exposed by the polymer layer opening 3 according to the process steps described in FIG. 2A to FIG. And forming the tin-containing metal layer 36 on the second interface 16b exposed by the polymer layer open ship: for the related content, please refer to the above description, which will not be described in detail herein. Among them, the polymer layer is evil. Selecting one of polyaniline, phenylcyclobutanide, polyurethane, epoxy resin, parylene polymer, tan mask material, elastic material or porous dielectric material to form polymer layer In addition to the spin coating method, the method of 39 can also use the dry film method or the screen printing method, and the thickness of the polymer layer 39 is between! Between microns and 3 microns. The related application of the semiconductor wafer 38' shown in Fig. 21 is also referred to the above, and will not be repeated here. 25 q / () 758 Second Embodiment: This month also applies the first embodiment to the reconfiguration line (re_distributi〇n layer, muscle) or connecting line (interconnecting trace). The reconfiguration line and the connection line are formed on the semiconductor substrate at the same time as an embodiment. However, only the reconfiguration line or connection is formed on the substrate base by the following method. The circuit is connected to form a metal interface and a tin-containing metal layer on the reconfiguration line or the connection line.咕Shen Xianqing 3G rides π, as her metal line 4 () and the metal line 42 as the connection line % road are formed above a protective layer 44, respectively The exposed joints are connected, and the protective layer 44. Regarding the material and structure of the pad 46, please refer to the descriptions of the protective layer 14 and the interface 16, respectively, and no further discussion will be made here. In addition, the maximum lateral dimension of the opening 44a in the protective layer 44 may be the same as the maximum lateral dimension of the opening 14a located in the protective layer 14, or less than the opening in the protective layer, the maximum lateral dimension. For example, the maximum lateral dimension of the opening 44a may be between 0.  Between 05 micrometers and 25 micrometers, the preferred size is between 1 micrometer and 権, and the opening 44a is shaped like a circle, a square, a rectangle or a polygon of five or more sides and the opening ^ is the largest The lateral dimension is the diameter dimension, the square length of the square port is long: the longest side length of the shape opening or the most fiberline of the butterfly opening above five sides and the other: the mouth of the mouth 44a is 46 4, or not suitable] There are any semiconductor components 4. , A does not listen to the production of reconfiguration Wei and Lianlinguan profile 26 households 376758 Figure 'as shown in the figure 'a polymer layer 48 formed on the protective layer 44, and located in the polymer layer 48 of hydration The layer openings 48a, 48b expose the interface 46 exposed by the opening 44a, wherein the polymer layer 48 is selected from the group consisting of polyimine, phenylcyclobutene, polyurethane, epoxy, parylene One of the polymer-like polymer, the welding cap material, the elastic material or the porous dielectric material, and the method of forming the polymer layer 48 can be performed by a hot-pressing dry film method or a screen printing method in addition to the spin coating method. The thickness of the additional polymer layer 48 is between 1 micrometer and 30 micrometers. Next, the metal lines 40, 42 are formed over the polymer layer 48 and joined to the pads 46 exposed by the polymer layers φ ports 48a, 48b. The method of forming the metal lines 4, 42 is described as follows: [Step 1].  . Forming an adhesion/barrier layer 52 having a thickness between 〇_01 μm and 3 μm (preferably between 0 μm and 1 μm) on the polymer layer 48 in the polymer layer The pads 46 are exposed by the openings 48a, 48b. The material of the adhesion/barrier layer 52 is selected from the group consisting of titanium, tungsten, drill, recording, titanium nitride, titanium tungsten alloy, hunger alloy, group, nitride group, chromium, copper, chrome-copper alloy, gold, town, At least one of platinum, ruthenium, rhodium, ruthenium, and silver, or φ, formed by, for example, using a bond or vapor deposition. [Step 2] The thickness is formed to be 0. Between 005 microns and 2 microns (the preferred thickness is between 〇. A sub-layer 54 of between micrometers and 〇7 micrometers is on the adhesion/barrier layer 52, and the seed layer 30 is formed by means of binding: ore, steaming, physical vapor deposition, electroplating or electroless plating. the way. This seed layer 54 facilitates the placement of subsequent metal lines, so the material of the seed layer 54 will vary with the material of the subsequent metal lines. For example, when the seed layer 54 is plated to form a metal layer of copper, the material of the seed layer 27 I376758 is preferably copper; when the seed layer 54 is plated to form a metal layer of gold, the material of the seed layer 54 is gold. It is better. [Step 3] Form a photoresist layer 56 in the seed layer. At the 54th, the photoresist layer 56 is patterned by exposure and development to form the photoresist layer opening 56a in the photoresist layer 56 and expose the seed layer %, and in the process of forming the photoresist layer opening 56a, for example. Exposure is performed with a double exposure machine or scanner. [Step 4] • Form a metal layer between 1 μm and 50 μm thick. The preferred thickness of the metal layer 58 is between 1 micron and 35 microns on the seed layer 54 exposed by the photoresist layer opening 56a.  The manner in which the metal layer 58 is formed is, for example, electroplating or electroless plating. In addition, the metal layer 58.  It may be a single-layer metal layer structure of gold, copper, silver, palladium, platinum, rhodium, ruthenium, iridium or nickel, or a composite layer composed of the above-mentioned metal materials. For example, the metal layer 58 may be formed by electroplating to a thickness of between j microns and 35 microns (preferably between 2 microns and 12 microns), or by electricity money. A copper layer is formed having a thickness between 1 micrometer and 35 micrometers (preferably between 2 micrometers and 20 micrometers thick). Further, the metal layer 58 is formed by, for example, a copper layer having an electron microscope thickness of between 2 μm and 20 μm on a seed layer 54 of, for example, copper, and then the thickness of the bond is between 〇.  Between 1 micron and 10 micron (preferably thickness is between 〇.  A nickel layer between 5 microns and 5 microns. On the copper layer, the final clock thickness is between 1 micrometer and 5 micrometers (preferably thickness is between 〇.  A gold layer of between 1 micron and 1 micron is on the nickel layer. [Step 5] 28 Ϊ 376758 After the metal layer 58 is formed, the photoresist layer 56 is subsequently removed. Continuing, the seed layer 54 and the adhesion/barrier layer 52, which are not under the metal layer 58, are removed, as shown in Fig. 3B. The method of removing the adhesion/barrier layer 52 can be divided into dry etching and wet etching, and dry etching is performed by using high-pressure argon gas, for example, in the case of wet etching, if the adhesion/barrier layer 52 is titanium. Or titanium-tungsten alloy, can be extracted with hydrogen peroxide. When the recording sub-layer 54 is gold, the paste-containing side liquid (for example, an etching liquid such as potassium iodide) may be removed. Referring to the S 3C diagram, after the metal lines 4, 42 are formed, a polymer layer 60 is formed on the metal lines 40, 42 and the polymer layer 48, and the polymer layer 60 is polymerized. The layer opening 60a exposes the metal lines 40, 42, wherein the polymer layer 6 is selected from the group consisting of polyfluorene-imine-based cyclobutene polyurethane, epoxy resin, poly-p-xylene polymer, and soldering. The cover material, the elastic material or the porous media can be used. The form of the silk layer 6G can be used in addition to the spin coating method, or the hot polymer film or screen printing method can be used. The thickness of the crucible is between 1 micrometer and 30 micrometers. Finally, a method of forming a tin-containing metal layer 36 and a metal pad 26 in accordance with an embodiment of the present invention, the present embodiment can form a tin-containing gold-based layer 36 in the metal line 4 exposed by the polymer layer opening 60a. And forming a metal bump (such as a gold bump) for bonding wire bonding wires, bonding tapes, bonding-external circuits, a tin-containing metal layer for bonding-external circuits, or bonding through an anisotropic conductive paste - external The metal touch 26 of the circuit, and for the outline of this part, please refer to the related description of the first embodiment, which will not be described in detail herein. Referring to FIG. 3D, after the above process is completed, the semiconductor substrate 2 can be subsequently cut to form a plurality of semiconductor wafers 62, wherein each of the semiconductor wafers 62 includes a semiconductor substrate 29 1376758, a line structure 6, and a plurality of dielectric layers. The electrical layer 12, a protective layer η, at least a reconfigurable line (such as the gold line 40), at least one sling line (such as the metal line 42), at least one metal pad π and at least one tin-containing metal layer 36, and the like. In addition, a plurality of semiconductor elements 4 (eg, transistors or metal oxide semiconductors, etc.) are located in or above the semiconductor substrate 2, and one of the semiconductor elements 4 is selectively positioned on the metal pad 26 or the tin-containing metal layer 36. Below the other, the semiconductor element 4 is electrically connected to the metal interface 26 and the tin-containing metal layer 36. Further, in each of the semiconductor wafers 62, the top of the protective layer 14 may be an oxysulfide compound layer or a ruthenium nitride compound layer. φ Each semiconductor wafer 62 can be connected to an outer crucible through a tin-containing metal layer 36. The circuit, which may be a semiconductor wafer, a printed circuit board, a flexible board, a substrate containing a ceramic material, or a passive component formed in advance. Where the printed circuit board contains glass fibers, and the soft board comprises a polymer layer having a thickness between 3 Å and 200 microns, such as a polyimide. In addition, through the wire bonding process, one of the metal pads 62 of the semiconductor wafer 62 can be bonded to a wire (for example, a gold wire or a copper wire) to be connected to an external circuit. The external circuit can be a semiconductor chip, a printed circuit board, or a flexible board. A substrate or lead frame containing a ceramic material, wherein the printed circuit φ plate contains glass fibers' and the soft plate comprises a polymer layer having a thickness of between 30 micrometers and 200 micrometers, such as a polyimide. Moreover, by means of tape bonding technology, the metal pads 26 of a semiconductor wafer 62 can be bonded to a tape and then connected to an external circuit, which can be a semiconductor wafer, a printed circuit board, a flexible board or a ceramic material. The substrate, wherein the printed circuit board contains glass fibers, and the soft board comprises a polymer layer having a thickness of between 30 micrometers and 200 micrometers. The polymer layer is preferably a polyimide. In addition, the tape has at least one metal line and at least one polymer layer, and the metal wire 30 1376758 is connected to the metal pad 26, for example, by bonding the metal pad 26 via tin metal or tin-silver alloy. Moreover, through a thermocompression bonding process, a semiconductor wafer can be obtained. 62 one of the metal pads 26 is pressed into the anisotropic conductive paste 'to allow the metal particles in the anisotropic conductive kick to gather on the metal interface 26 and the external circuit (such as a glass substrate) containing tin oxide Between the pads of the object, the connection between the metal-free interface 26 and the external circuit containing the tin oxide is electrically connected. In addition, the external circuit is, for example, a semiconductor wafer, a printed circuit board, a "soft board of a polymer layer having a thickness of between 3 μm and 2 μm, or a substrate containing a ceramic material, etc.. One of the metal pads 26 can be bonded to a metal bump (such as a gold bump) and thus to an external f path. The external circuit can be a semiconductor ", a printed circuit board, . The glass substrate and the soft domain comprise a substrate of a ceramic recording material, the printing printed circuit board contains glass fiber, and the soft board comprises a polymer layer having a thickness of between 30 micrometers and 1 200 micrometers, and the polymer layer is, for example, a brewing layer. The present embodiment can also be connected to an external circuit through the tin-containing metal layer 36 before the semiconductor bottom layer 2. The external circuit can be a semiconductor wafer, a printed circuit board, a flexible board, or the like. A substrate or a passive component formed in advance, wherein the printed circuit board contains glass fibers, and the flexible board comprises a polymer layer having a thickness of between 30 micrometers and 2 micrometers, such as a polyimide. Next, the conductive conductor substrate 2 is cut to form a plurality of semiconductor wafers. Thereafter, the metal pad 26 of the body w is bonded to the wire bonding wire (fine wire bonding process), the bonding tape (using the tape bonding automatic bonding technique), the metal bumps (for example, gold bumps) for bonding an external circuit, and the bonding-external circuit. The tin-containing gold touches or the external circuit through the heterogeneous conductive county. 31 ^ 376758 By reconfiguring the line (such as the metal line 4 in Figure 3C), this embodiment can relocate the position of the pad 46 previously exposed by the opening 44a to a specific location (such as layout to polymer) The layer opens the location of the metal line that is exposed in the county, and the position of the financial position 46 can be viewed from a top perspective view. Further, in the present embodiment, at least two of the contacts exposed by the opening 44a are connected through the metal line 42) in the Lianxian Road ^^3(4). In addition, as shown in FIG. 3E, this embodiment can also form the metal lines 40, 42 ′ directly on the protective layer 14 and further in the polymer layer opening 6 according to the process steps described in FIGS. 3C to 3D. The metal-containing metal layer % and metal interface % are formed on the metal lines 4 and 42 exposed by 〇a. For the details of this part, please refer to the above related descriptions, which will not be described in detail here. In addition, the semiconductor W 62, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Therefore, the present invention can form a metal bump for bonding a wire bonding wire (such as a gold wire or a copper wire), for bonding a tape, for bonding an external circuit, on a re-wiring line or a connection line of a wafer or a wafer. a block (such as gold (10)), a tin-containing metal layer for bonding an external circuit, or a metal pad for bonding an external circuit through an anisotropic conductive paste, and a tin-containing metal layer formed over the interface where the metal pad is not formed . In addition, the 'metal lines 40, 42 may also be a line including a power bus (ρ· _, a signal bus or a ground bus), which may be via the protective layer 44 The opening σ 44a is connected to the power line, the channel or the ground line under the protective layer 44. Referring to FIG. 4, it is a schematic cross-sectional view of the multi-chip package structure. As shown, the semiconductor wafer 64 may be The semiconductor wafer 38 or the semiconductor crystal 32 1376758 formed in the first embodiment or the semiconductor wafer 62 or the semiconductor wafer formed in the embodiment of the second embodiment has two different types of metal pads 68 and . The metal interface 68 includes a tin-containing metal layer 36 and a plurality of metal layers (such as an adhesion/barrier layer 28, a seed layer 3 () and a diffusion barrier layer) underneath the tin-containing metal layer, and For the contact of the tin-containing metal layer % and the two metal layers, please use the above-mentioned phase coffee. Alternatively, the metal pad may be the metal pad in the first embodiment or the second embodiment. Please also refer to the above for instructions. The illustrated swivel wafer 64 is connected to the semiconductor wafer 66 via a metal interface 68. In addition, the mouthpiece 72 is filled between the two semiconductor wafers 64 and 66 and covers the metal contacts, wherein the poly 72 is selected from the group consisting of One of polyaniline, phenylcyclobutene, polyurethane, epoxy resin, parylene polymer, welding cap material, miscellaneous material or multi-layer dielectric material. A flexible rib tape 78 having at least one metal line 74 and a polymer layer 76 is connected to the tiling (4) via a gold escape 74, and the metal line 74 of the smear tape 78 is, for example, via a metal layer (eg, Tin metal or tin-silver alloy twisted metal joint 7〇, wherein polymer layer 76 is selected from the group consisting of polyaniline, phenylcyclobutene, polyurethane, epoxy resin, parylene polymer, welding One of a cover material, an elastic material or a porous dielectric material. Further, the polymer 80 covers the metal pad 70 and a portion of the soft tape 78, wherein the polymer 80 is selected from the group consisting of polyimine and phenyl. Cyclobutane, polyurethane, epoxy resin, parylene = molecule, hood material, bomb The semiconductor wafer 64 is connected to an external circuit through a metal pad 68 (for example, a semiconductor crystal 33 1376758 piece 66, a printed circuit board containing glass fibers, and having a thickness of 3 μm to 2 〇〇 micro-polymer board soft board or ceramic substrate containing substrate, and using tape bonding technology, metal pad 70 is connected to an external circuit via flexible tape 78 (eg semiconductor wafer, A printed circuit board containing glass fiber, comprising a soft board of a polymer layer having a thickness between 3Q micrometers and a micrometer micrometer or a substrate containing a ceramic material.

5A to 5H are schematic cross-sectional views showing a process for forming a tin-containing metal layer and a metal pad on a wafer or wafer in the present embodiment. After the process of forming the adhesion/barrier layer 18 described in FIG. 2A, the thickness of the film is between 0. 005 micrometers and 1 micrometer micrometer (preferably, the thickness is between 〇 and 参阅, as shown in FIG. · [Micron to 2 micron) - seed layer 2 〇, on the adhesion / barrier layer 18, and form a seed layer 2 〇, such as _, inspection, physical gas her, electroplating or no electricity The way. This seed layer 20 facilitates the subsequent metal bond arrangement, so that the material of the seed layer 2 〇 will vary depending on the metal material to be joined. For example, when the layer 2q is required to be bonded to the copper metal, the material of the seed layer 20' is preferably steel; and when the seed (four) is a metal of the tantalum alloy, the material of the seed layer 20' is preferably gold. Then, the formation-photoresist layer 82 is on the seed layer 2, and the photoresist layer 82' is patterned through the exposure and development process to form the photoresist layer 82a on the seed layer above the first pad, such as = As shown in the figure, the process of moving into the photoresist layer 82a is performed by, for example, exposing the exposure machine or scanning, ordering the exposure, and using the photoresist layer 82a as a mask (for example, removing the photoresist layer that is not in the photoresist layer) 34 1376758 The seed layer 20 below has a barrier layer π. Among them, the way to remove the adhesion/cholester barrier layer 18 can be divided into dry etching and wet thinning, while dry copper is used for high silver gas for miscellaneous silver engraving. In the wet side, if the adhesion/barrier layer 18 is a Chin or a Chinhe alloy, it can be removed by using hydrogen peroxide. In addition, if the seed layer 20 is gold, it can be used to contain the side liquid (for example, cracking). The etchant is removed and removed. Next, after removing the seed layer 2, the photoresist layer 82a is removed after the adhesion/barrier layer 18 as shown in Fig. 5C. Therefore, a metal pad 84 is formed on the protective layer. 14 on a first pad 16a exposed by one of the openings 14a, the metal pad 84 is adhered to the adhesion/barrier layer 18 The seed layer 20' on the barrier layer 18 is formed, and the metal turn 84 can be bonded to a wire conductor (such as a gold wire or a copper wire) through a wire bonding process, and a tape is bonded by an automatic bonding technique. a metal bump (such as a gold bump) of an external circuit, a tin-containing metal layer bonded to an external circuit, or an anisotropic conductive knee joint-external circuit. Further, with a seed layer 2, a gold layer is For example, when a metal joint 84 is bonded to a wire (for example, a gold wire), the thickness of the gold layer is between 微米 and 5 μm (preferably between 〇1 μm and 2 μm) In addition, the seed layer is added, and the case is a copper layer. When the metal (four) 84 is bonded to a single wire (for example, a copper wire), the thickness of the copper layer is between 0.05 micrometers and 5 micrometers (the preferred thickness is 〇1 micron to 2 microns). See Figure 5D, forming a thickness between 微米. 〇 1 micron to 3 microns (preferably thickness is between ο. οι micron to i micron) a bonding/barrier layer 28 on the protective layer 14 on the second pad 16b exposed by the opening 14a and in the metal interface % The material of the adhesive/barrier layer 28 is selected from the group consisting of titanium, tungsten, drill, recording, titanium nitride, titanium tungsten alloy, hunger alloy, neonitriding group, chromium, steel, copper alloy, gold, bismuth, Turning, turning, smashing, recording, and silver, or at least one of the groups of 35 1376758, formed by means of a cuckoo clock or an evaporation method. A sub-layer 30 of between microns and 2 microns (preferably having a thickness between 〇jm and 0.7 microns) is on the adhesion/barrier layer 28, and the manner in which the seed layer is formed is, for example, sputtering. , vapor deposition, physical vapor deposition, electroplating or electroless plating. This seed layer 30 facilitates the subsequent arrangement of the metal lines, so the material of the seed layer 3〇 will vary with the material of the subsequent metal lines. For example, when the seed layer 3 is plated to form a metal layer of copper material, the material of the seed layer 30 is preferably copper; when the seed layer 30 is plated to form a gold genus layer of gold material, the material of the seed layer 30 is It is better to use gold. Continuing, a photoresist layer 32 is formed on the seed layer 30, and the photoresist layer 32 is patterned through the exposure and development process to form the photoresist layer opening 32a in the photoresist layer 32 and exposed to the second pad 16b. The upper seed layer 30 is exposed during the process of forming the photoresist layer opening 32a, for example, by a double exposure machine or scanner. Next, referring to FIG. 5E, a diffusion barrier layer 34 is formed on the seed layer 30 exposed by the photoresist layer opening 32a, and the diffusion barrier layer 34 is formed by, for example, the thickness of the electric clock. A copper layer between 5 microns and 10 microns is on the seed layer go, for example steel, and a recording layer having a thickness of between 1 micrometer and 5 micrometers on the copper layer. Therefore, the diffusion barrier layer 34 may be composed of a steel layer and a nickel layer on the copper layer. Then, a tin-containing metal layer 36 having a thickness between 1 micrometer and 500 micrometers is formed on the diffusion barrier layer 34 in the photoresist layer opening 32a. The preferred thickness of the tin-containing metal layer 36 is 3 The micron to 250 micron, and the formation of the tin-containing metal layer 36 is, for example, electroplated, electroless plating or screen printing. In addition, the tin-containing metal layer 36 is, for example, a tin-lead alloy, a tin-silver alloy, a tin-silver 36 1376758 copper alloy or a lead-free alloy. Taking tin-lead alloy as an example, the tin/error ratio can be adjusted according to the demand. The more common tin-lead ratio is 90/10, 95/5, 97/3, 99/1, 37/63, etc. As can be seen from the above, the diffusion barrier layer 34 is under the tin-containing metal layer 36, and the diffusion barrier layer 34 includes, for example, a nickel layer having a thickness of between 0.1 μm and 5 μm under the tin-containing metal layer. And a copper layer having a thickness between 0.5 micrometers and 1 micrometer is below the nickel layer and the recording layer and the copper layer are tied above the second pad 16b. In addition, in this embodiment, a fresh film adhesion layer (not shown) may be formed on the diffusion barrier layer 34 to improve the bonding between the subsequent tin-containing metal layer and the diffusion barrier layer. The solder a &quot; know I material layer of the material such as gold, copper, tin, Weng σ, tin-silver alloy, kick silver alloy or error-free alloy. ° Refer to Figure 5F. - No, after forming the tin-containing metal layer 36, the first resist layer 32 is removed. Go ahead and take the exam with the adhesion/barrier layer 28.罝+ χ ^ 30 ”, the way to remove the adhesion/barrier layer 28 can be divided into dry etching and wet etching, but the burning knife is engraved, and in the wet name, the H ratio/high gas is used. The splashing shaft can be removed by using hydrogen peroxide (4). When the barrier layer 28 is titanium or a material alloy, please refer to the 5G image + 3β m for the re-freshing process to make the tin-containing metal layer 36 reach the melting point and $ The soldering process 'makes the tin-containing metal layer 36 advanced and removes the ball layer 30 and the adhesion/barrier layer 28 which are not under the tin-containing metal layer 36. ^ The process of reflowing is not carried out until the tin-containing metal layer 36 is connected to the external circuit of 37 1376758. The external circuit is, for example, a semiconductor wafer, a printed circuit board containing glass fiber, and a thickness a soft board of one polymer layer between 3Q micrometers and 200 micrometers, a substrate containing a ceramic material, or a 'pre-formed passive component, etc. Therefore, the present invention can be exposed to a portion of the opening 14a of the protective layer 14. 16 formed on the wire for bonding wires (such as gold wire or copper wire) a metal bump (such as a gold bump) for bonding an external circuit, a tin-containing metal layer for bonding an external circuit, or a φ-transparent conductive vine joint The metal interface of the external circuit is 84, and the metal layer 36 is formed on the pad 16 on which the metal pad 84 is not formed. Alternatively, the top of the metal pad 84 may include an adhesive film layer (not shown). For connecting the wire bonding wire, the adhesion film layer is, for example, a gold layer and before forming the tin-containing metal layer 36, a gold layer may be formed on the diffusion barrier layer 34, and then the tin-containing metal layer 36 is formed. In addition, the tin-containing metal layer 36 in this embodiment can also be replaced by a fresh material bump (so der bump). Referring to the 帛5H diagram, after the above process is completed, the semiconductor substrate 2 can be subsequently cut. φ to form a plurality of semiconductor wafers 86' each of which includes a semiconductor substrate 2, a wiring structure 6 'plural dielectric layer 12, a protective layer 14, at least one metal pad (10) and at least - tin-containing metal Layer 36, etc. Another 'plural swivel element 4 (such as a transistor or gold An oxide semiconductor or the like is located in or above the semiconductor substrate 2, and one of the semiconductor elements 4 is selectively positioned under the metal pad 84 or the tin-containing metal layer 36, and two of the semiconductor elements 4 The metal pads 84 and the tin-containing metal layer 36 are respectively electrically connected. Further, at the top of each of the semiconductor crystals 86, the protective layer 14 may be a monolithic compound layer or a nitrile compound layer β 38 1376758 per The semiconductor wafer 86 can be connected to an external circuit through the tin-containing metal layer 36. The external circuit can be a semiconductor wafer, a printed circuit board, a flexible board, a substrate containing a ceramic material or a passive component formed in advance. The printed circuit board contains glass. The fiber, and the soft board comprises a polymer layer having a thickness of between 3 micrometers and 200 micrometers, such as a polyimide. In addition, through the wire bonding process, one of the metal pads 86 of the semiconductor wafer 86 can be bonded to a wire (for example, a gold wire or a copper wire) to further connect an external circuit, and the external circuit can be a semiconductor wafer, a printed circuit board, or a soft a board, a substrate or a lead frame containing a ceramic material, wherein the printed circuit board contains glass fibers' and the soft board comprises a polymer layer having a thickness of between 30 micrometers and 200 micrometers. The polymer layer is, for example, a polymer. Yttrium. Furthermore, through the tape bonding technology, a metal pad 84 of a semiconductor wafer 86 can be bonded to an external circuit, wherein the external circuit can be a semiconductor wafer, a printed circuit board, a flexible board or A substrate comprising a ceramic material wherein the printed circuit board contains glass fibers, and the soft board comprises a polymer layer having a thickness of between 30 micrometers and 200 micrometers, such as a polyimide. In addition, the tape has at least one metal line and at least one polymer layer, and the metal line connects the metal pads 84, for example, by bonding the metal pads 84 via tin metal or tin-silver alloy. In addition, through the thermocompression bonding process, a metal pad 84 of a semiconductor wafer 86 can be pressed into the anisotropic conductive paste, and the metal particles located in the anisotropic conductive paste are gathered on the metal pad and one. An indium tin oxide-containing pad is formed between an external circuit (for example, a glass substrate) and a pad containing indium tin oxide electrically connected to the metal pad 84 and an external circuit.丨: This external circuit is, for example, a semiconductor wafer, a printed circuit board, a soft board containing a polymer layer having a thickness of between 30 μm and 2 μm, or a substrate containing a ceramic material. 39 1376758 In addition, a metal pad 84 of a semiconductor wafer 86 can be bonded to a metal bump (such as a gold bump) to connect an external circuit, which can be a semiconductor wafer, a printed circuit board, a glass substrate, or a soft board. Or a substrate comprising a ceramic material, wherein the printed circuit board contains glass fibers, and the soft board comprises a polymer layer having a thickness of between 30 micrometers and 200 micrometers, such as a polyimide. In addition, this embodiment can also connect an external circuit through the tin-containing metal layer 36 before cutting the semiconductor substrate 2. The external circuit can be a semiconductor wafer, a printed circuit board, a flexible board, or a base material containing a shouting material. A red-shaped element having a sharp-edged plate containing glass fibers, and the soft plate comprising a polymer layer having a thickness of between 30 micrometers and 200 micrometers, such as a poly-imine. Next, the semiconductor substrate 2 is diced to form a plurality of semiconductor wafers. Then, this embodiment can bond the wire bonding wires (using the wire bonding process) and the bonding tapes (using the tape bonding automatic bonding technology) to the metal tabs 84 of each semiconductor wafer 86 to engage metal bumps of an external circuit (for example, Gold bumps), a tin-containing metal layer bonded to an external circuit or an external circuit through an anisotropic conductive paste. Referring to FIG. 51, in this embodiment, a polymer layer 39' may be formed on the protective layer 14 and the polymer layer located in the polymer layer 39 is opened. a first interface 16a and a second interface 16b, and then forming a metal pad 84 on the first connection smear exposed by the polymer layer opening 39a in accordance with the winding step described in FIGS. 5A to 5h, and The formation of the tin-containing metal layer 36 is performed on the side of the polymer layer opening 39b, which is described in detail. == is selected from the group consisting of polyacrylonitrile, styrene butyl sulphate, polyurethane, epoxy resin, polyparaxylene polymer welding cap material, elastic material or porous dielectric material to form a polymer The layer 39 is formed in a manner different from the seaming method, and the thickness of the other polymer layer 39 is between 1 micrometer and 30 micrometers. The related application of the semiconductor wafer 86' shown in Fig. 51 is also referred to the above, and will not be repeated here. Furthermore, the present embodiment can also be applied to a reconfiguration line or a connection line as in the second embodiment. Please refer to FIG. 5J and FIG. 5K at the same time. In this embodiment, the Jinguan Road 42 which is the connecting line of the Jinxian Road 4 of the Kixian Road can be formed at 7 o'clock above the semiconductor substrate 2, and Please refer to the second implementation for the law. Then, according to the process steps of the fifth drawing to the sun riding, the metal pads 84 and the tin-containing metal layer 36 are formed on the metal lines 40 and 42 exposed by the polymer layer opening, please refer to the above. For related instructions, the description will not be repeated here. Further, the related applications of the semiconductor chip 87' shown in the fifth chip and the fifth chip shown in Fig. 5 are also referred to above, and will not be described here. However, in the above manner, the present invention can also form only the relocation line or the connection line above the semiconductor substrate 2, thereby forming the metal interface 84 and the tin-containing metal layer % on the relocation line or the connection line. • Fourth Embodiment: - Figure 6C is a metal bump (such as gold) on the wafer or crystal of the present invention that is bonded to the bonding wire, the bonding tape, and the bonding of an external circuit. A process profile diagram of a bump, a layer of a person, or a plurality of metal pads that are joined to an external circuit through an anisotropic conductive knee. "See Figure 6. An adhesive/barrier layer 18 having a thickness between 微米1 μm and 3 μm (preferably a thickness of 1376758 between 0.01 μm and 1 μm) is formed. On the protective layer 14 and the opening 16 exposed by the opening 14a. The material of the adhesive barrier layer 8 is selected from the group consisting of Qin, crane, record, lock, titanium nitride, titanium tungsten alloy, miscellaneous alloy, new At least one of a group consisting of nitrogen, copper, copper, chrome-copper alloy, gold, town, turn, handle, sputum, record, and silver, formed by sputtering or Evaporation method. Next, 'the formation of a copper layer 88 having a thickness between 005·005 micrometers to 2 micrometers (preferably having a thickness between 〇丨micrometers and 0.7 micrometers) is on the adhesion/barrier layer 18, The method of forming the copper layer 88 is, for example, sputtering, vapor deposition, physical vapor deposition, electroplating, or electroless plating. Referring to FIG. 6B, a photoresist layer 22 is formed on the copper layer 88. Then, the photoresist layer 22 is patterned through the exposure and the etch process to form the photoresist layer opening 22a in the photoresist layer 22 and exposed. 6 above the copper layer 88, and in the process of forming the photoresist layer opening 22a, for example, by exposure to a double exposure machine or scanner. Continue to form a thickness between 丨 micrometers to 祀 micrometers (better thickness system) A copper layer 9 between 8 microns and 35 microns is placed on the photoresist layer opening 2 to expose the copper layer 88, and the copper layer 90 is formed by electroplating or electroless plating. Forming a town layer 92 having a thickness between 微米1 μm and 1 μm (preferably having a thickness between 微米. [micron to 5 μm) on the copper layer 90, forming a nickel layer 92 The method is, for example, electric money or ... is electroless ore. Next, the thickness is formed between 0.01 μm and 1 μm (preferably the thickness is between 0·1 μm and 2 μm) - The gold layer 94 is on the recording layer 92, and the gold layer 94 is formed by electroplating or electroless plating. Referring to FIG. 6C, after the gold layer 94 is formed, the photoresist layer is subsequently removed. Continue, remove The copper layer 88 and the adhesion/barrier layer 18» which are not under the copper layer 90, the manner of removing the adhesion/resistance 42 i^/b758 -18 can be divided into Dry rotten and wet _, and silk engraving, for example, using high-money gas to splatter the butterfly's another wet side, if the adhesive barrier layer 18 is a Qin or Titanium alloy, it can be removed with hydrogen peroxide. Metal pads 96 are formed on the plurality of contacts 16 exposed by the plurality of openings 14a of the protective layer 14. These metal pads 96 are formed by an adhesion/barrier layer μ, a copper layer on the adhesion/barrier layer 18. The layer 88, a copper layer on the copper layer 88 is formed on the copper layer 一 a recording layer 92 and a gold layer 94 located on the recording layer 92 ±, and the metal interface % can be used for connection _ A wire-bonding wire (such as a gold wire), a metal bump that joins a tin-containing metal layer, and an external circuit is joined. Adhesive tape (using tape bonding technology) or an external electrode through an anisotropic conductive paste. Please refer to 帛6D diagram*, through the planting process, this embodiment can be bonded on the gold layer 94 of some metal pads 96 from i micro to 5 〇〇 micron (more) The tin-containing metal ball 98 is preferably between 3 micrometers and 250 micrometers thick, and then the tin-containing metal ball 98 is connected to an interface 95 of the external circuit 97 through a reflow process. Wherein, the external circuit is, for example, a semi-calling conductor chip, a printed circuit board containing glass fiber, a substrate containing a Tauman material, or a passive component such as a pre-formed shape; and a tin-containing metal ball 98 such as a tin-lead alloy, Tin-silver alloy, tin-silver-copper-gold or residual alloy. With the alloy paste, its tin/gauge can be visually demanded: #破破, the more common tin-lead ratio is 90/10 '95/5, 97/3, 99/1, 37/63 and so on. Alternatively, a tin-containing metal layer 98 may be formed in advance, and the gold layer of the tin-containing metal layer 98' is connected to the metal pad 96 by an external circuit 97, followed by a through-reflow process, so as to make a metal pad. 96 is connected to the external circuit 97 as shown in Fig. 6E. 43 1376758 Referring to FIG. 6F, after the above process is completed, the semiconductor substrate 2 can be subsequently cut to form a plurality of semiconductor crystals 99', wherein each semiconductor wafer 99 includes a semiconductor substrate 2, a line structure 6, and a plurality a dielectric layer 12, a protective layer 14 and a plurality of metal pads 96, etc., a plurality of semiconductor elements 4 (such as transistors or metal oxide semiconductors, etc.) are located in or above the semiconductor substrate 2, and wherein the semiconductor elements 4 are One of the selective locations is below one of these metal pads, and the semiconductor elements 4 are respectively connected to the metal pads 96. Further, in each of the semiconductor wafers 99, the top of the protective layer 14 may be a layer of a monolithic compound or a layer of a niobium compound. Therefore, each of the semiconductor wafers 99 may be bonded to a portion of the metal pads 96 by a tin-containing metal ball. 98 to connect an external circuit or to bond a tin-containing metal layer 98' to an external circuit. The external circuit may be a semiconductor. a wafer, a printed circuit board, a flexible board, a substrate containing a ceramic material, or a previously formed passive component, wherein the printed circuit board contains glass fibers, and the flexible board includes a polymer layer having a thickness of between 30 micrometers and 200 micrometers. The polymer layer is, for example, a polyimide. Or 'each semiconductor wafer 99 can be bonded to an external circuit on a portion of the metal pads 96. One of the metal bumps (eg, gold bumps)' may be a semiconductor wafer, a printed circuit board, a glass substrate, a soft board A substrate comprising a ceramic material or a previously formed passive component, wherein the printed circuit board contains glass fibers' and the flexible board comprises a polymer layer having a thickness between, such as a polyimide. In addition, through the wire bonding process, a portion of the metal pads 96 of the semiconductor wafer 99 can be bonded to a wire bonding wire 100 (such as a gold wire or a copper wire), thereby connecting an external circuit, and the external circuit can be a semiconductor wafer or a printed circuit. a board, a flexible board, a substrate or lead frame containing a ceramic material, wherein the 44 1376758 printed circuit board contains glass fibers, and the soft board comprises a polymer layer having a thickness of between 30 micrometers and 200 micrometers, such as a polymer layer such as It is a polyimine, as shown in Figure 6G. Moreover, through the tape bonding technology, a part of the metal interface 96 of the semiconductor chip 99 can be bonded to a tape, and then connected to an external circuit, wherein the external circuit can be a semiconductor wafer, a printed circuit board, a flexible board or A substrate of ceramic material in which the printed circuit board contains glass fibers, and the soft board comprises a polymer layer having a thickness of between 30 micrometers and 200 micrometers, such as a polyimide. Alternatively, the tape has at least one metal line and at least one polymer layer, and the metal-rubber line connects the metal pads 96, for example, by bonding the metal pads via tin metal or tin-silver alloy. Moreover, through the thermocompression bonding process, a metal pad 96 of a semiconductor wafer 99 can be pressed into the anisotropic conductive knee, and the metal particles located in the anisotropic conductive paste are concentrated on the metal interface. • An external circuit (such as a glass substrate) containing a pad of indium tin oxide between the metal pads 96 and an external circuit containing indium tin oxide pads. Further, the external circuit is, for example, a germanium semiconductor wafer, a printed circuit board, a flexible board containing a polymer layer having a thickness of between 2 and 10, or a substrate containing a ceramic material. • As can be seen from the above, the present embodiment has ten embodiments as described below: - Bonding on a portion of the metal interface 96 of a semiconductor wafer 99 - tin-containing metal ball 98 or tin-containing metal layer 98 And connected to the external circuit, and a wire bonding wire is bonded to the metal pad 96 of the uncoated tin metal ball 98 or the tin-containing metal layer 98. - a tin-containing metal ball (10) or a tin-containing metal layer 98' is bonded to a portion of the metal pads 96 of the semiconductor wafer 99 to be connected to an external circuit, and the tin-containing metal ball 98 or the tin-containing metal layer 98 is not bonded. The metal is connected with a tape on the shame. 45 1376758 Three 'bonding a tin-containing metal ball 98 or a tin-containing metal layer 98 to a portion of the metal pad 96 of the semiconductor wafer 99, and being connected to an external circuit, and not bonding the tin-containing metal ball 98 or the tin-containing metal The layer 98, the metal pad 96 is bonded to an external circuit through the anisotropic conductive paste. 4. Bonding-bonding to a portion of the metal pads 96 of the semiconductor wafer 99 and attaching to the metal portion of the bonding pad and bonding an external circuit through the anisotropic conductive paste on the metal interface 96 of the unbonded tape. • 5. Bonding-bonding a portion of the metal pads 96 of the semiconductor wafer 99 to an external circuit and bonding a wire conductor to the metal pads 96 of the unbonded tape. • A bonding of a wire conductor to a portion of the metal interface 96 of the semiconductor wafer 99 and bonding of an external circuit through the anisotropic conductive paste on the metal 96 of the unbonded wire conductor. 7. A metal bump of an external circuit is bonded to a portion of the metal pads 96 of the semiconductor wafer 99, and a wire bond is bonded to the metal pads 96 that are not bonded to the metal bumps. • A metal bump of an external circuit is bonded to a portion of the metal pads 96 of the semiconductor wafer 99, and a tape is bonded to the metal pads 96 that are not bonded to the metal bumps. 9. Bonding a metal bump of an external circuit to a portion of the metal pad 96 of the semiconductor wafer, and bonding a tin-containing metal ball 98 or a tin-containing metal layer to the metal pad 96 on which the metal bump is not bonded. 98', 10. A metal bump of an external circuit is bonded to a portion of the metal pad 96 of the semiconductor wafer 99, and the anisotropic conductive 46 1376758 is bonded to the metal pad 96 of the unbonded metal bump. An external circuit. In addition, this embodiment can also be connected to an external circuit by bonding a tin-containing metal ball 98, a tin-containing metal layer 98, or a metal bump after cutting the semiconductor substrate 2. The external circuit can be a semiconductor wafer or a printed circuit board. a flexible board, a glass substrate, a substrate containing a ceramic material, or a previously formed passive component, wherein the printed circuit board contains glass fibers, and the flexible board comprises a polymer layer having a thickness of between 30 micrometers and 200 micrometers. The layer is, for example, a heteroimine. Finally, the present invention can be used to bond the wire bonding wires on the metal pads 96 of the semiconductor wafer which do not form the tin-containing metal balls 98, the tin-containing metal layers 98' or the metal bumps (using the bonding process bonding tape) With automatic bonding technology) or by anisotropic conductive adhesive bonding - external circuit.. Therefore, the invention can be formed on the _ exposed by the opening of the protective layer to bond the tin-containing metal ball, the lining - External circuit - tin-plated gold, metal wire for bonding wire (such as gold wire), for bonding tape, for bonding metal bumps or for bonding an external circuit through an anisotropic conductive paste » see As shown in FIG. 6H, in this embodiment, a polymer layer 39' can be formed on the protective layer 14 and the plurality of polymer layer openings 39a in the polymer layer 39 expose the plurality of pads 16, and then 6A to 6C, in the process of forming a metal interface 96 on the exposed surface of the polymer layer opening, please refer to the above description for details. , polymer layer 39 is selected from Juanya , phenylcyclobutylene, polyurethane, epoxy wax, polydimethylene polymer, material, miscellaneous material or porous dielectric material - in the form of polymer layer 39 in addition to spin coating In addition to the method, it can also be used by hot pressing, film or screen printing, and the thickness of the polymer | 39 is between 47 1376758 and μm to 3 μm. The material shown in Fig. 6H For related applications of the chip 99a, please refer to the above description, and the present embodiment will not be described here. Furthermore, the embodiment can also be applied to the reconfiguration line or the connection line as in the second embodiment. Please refer to FIG. 61 at the same time.帛6J riding, this solid complement can be formed on the semiconductor substrate 2 at the same time as the metal line 4〇 of the reconfiguration line and the metal line as the connection line, and the method of forming please refer to the second implementation. Then, according to the 6A The preparation step described in the figure to Fig. 6c forms a metal junction 96 on the metal lines 4〇, φ 42 exposed by the polymer layer opening 60a. For the content of P, please refer to the above related description, and no longer Detailed description. In addition, regarding the 61st map The semiconductor wafer 99b and the semiconductor wafer 99 shown in FIG. 6J are also related to the application. Please refer to the above, and the description will not be repeated here. However, the present invention can also be used on the semiconductor substrate 2 by the above method. Only the reconfiguration line or the connection line is formed, and the metal pad 96 is formed on the reconfiguration line or the connection line. Fifth Embodiment: 0 Refer to FIG. 7A, after completing the process steps shown in FIG. 2A Then, a photoresist layer 100 is formed on the seed layer 20, and the photoresist layer 1 is patterned through an exposure and development process to form a photoresist layer opening 1〇〇3 in the photoresist layer 1〇〇 and exposed. The seed layer 20' located above the first pad 16a is exposed during the process of forming the photoresist layer opening i〇〇a, for example, by a double exposure machine or scanner. Further, a metal layer 102 having a thickness between 1 micrometer and 200 micrometers (for example, between 1 micrometer and 50 micrometers) is formed on the seed layer 2〇 exposed by the photoresist layer opening iOOa, the metal layer 48 1376758 The preferred thickness of 102 is between 2 microns and 3 microns, and the manner in which the metal layer 1〇2 is formed is, for example, an electric clock or electroless plating. In addition, the metal layer 1〇2 may be a single-layer metal layer structure of gold, copper, silver, palladium, platinum, erbium, ytterbium, ytterbium or nickel, or a composite layer composed of the above-mentioned metal materials. For example, 'the metal layer 1 〇 2 may be a gold layer formed by electroplating between 8 micrometers and 35 micrometers thick or a thickness formed by electroplating between 8 micrometers and 35 micrometers. Copper layer. Moreover, the manner of forming the metal layer 1〇2 is, for example, by plating thickness between 8 micrometers and 35 degrees.

Between the micro- and the _ seed layer 20, then the thickness of the ridge is between 1 μm and 10 μm (the preferred thickness is between 〇1 and 5 μm) The layer is on the copper layer, and finally the electroconductive layer is between 微. 01 micro to 1 〇 micron (preferably, the thickness is between 〇. 丄 to 2 micrometers) - the gold layer is on the nickel layer . Referring to FIG. 7B, after the metal layer 1〇2 is formed, the photoresist layer 1〇〇 is subsequently removed. Continuing to form a photoresist layer 104 on the seed layer 2 and the metal layer 1 2, and then through the exposure and development process, the photoresist layer 104 is formed to form a photoresist layer opening in the implant layer (10) and exposed to The second layer 16b is over the seed layer 2G, and during the process of forming the photoresist layer, the exposure is performed, for example, by a double exposure machine or a scanner. Next, a metal layer (10) having a thickness of between micrometers and 20 micrometers (preferably having a thickness of between 2 micrometers and 1 micrometer) is formed on the seed layer 2Q of the photoresist layer π. The manner in which the metal layer (10) is formed is, for example, electrowinning or electroless plating. In addition, the metal layer gamma may be gold, copper, silver, handle, face, 姥, 舒' 铢 or recorded a single layer of exhausted structure, or the price of the gold yelled, for example, the metal layer m may be The form of a gold layer formed by the electric energy type between 丨 micrometers and 2 〇 micrometers or the manner in which the thickness of the dirty layer is between the micro-discrimination and the metal layer 106 For example, if the electricity is between i micrometers and still ==, the surface is, for example, _seed (four), and the _ wealth is between G.i micrometers and micrometers. The gold layer of the strip from 01 to 3 microns is on this layer. Therefore, the metal layer ι 2 and the metal layer (10) may be of the following four structures: The metal layer 102 and the metal layer 1Q6 are both the aforementioned single-gold layer structure. Both the metal layer 102 and the metal layer are both of the aforementioned copper/nickel/gold structures. The metal layer 1〇2 is the single gold layer structure described above, and the metal layer is the aforementioned copper/record/gold structure. The 'four metal layer 102 is the aforementioned copper/recording/gold structure' and the metal layer 106 is of the single gold layer structure described above. * Referring to FIG. 7C_, after forming the metal layer (10), the photoresist layer 104 is subsequently removed. Next, only the seed layer 2〇 and the adhesion/barrier layer 18 which are not under the metal layer 1〇2 and the metal layer 1〇6 are removed. Among them, the method of removing the transfer/transfer layer 18 can be divided into the side of the wire and the side of the wet side. The dry silver engraving is better than that of the argon gas of the sorghum, and the other side of the brain is engraved. If the adhesion/barrier layer ls is titanium or titanium When tungsten alloy is used, it can be removed by using hydrogen peroxide. Further, when the seed layer 2 is gold, it can be removed by using an etchant containing iodine (for example, an etching solution such as potassium iodide). Therefore, the metal pads 108 and the metal pads 110 are respectively formed on the first and second pads 16a and 16b exposed by the opening Ua of the protective layer 14. Wherein, the metal interface (10) is composed of an adhesion/barrier layer 18, a sub-layer 2〇 on the adhesion/barrier 18, and a metal layer 102 on the seed layer, and the metal interface (10) It is possible to bond a wire conductor (such as a gold wire or 50 1376758 copper wire), a metal bump (such as a gold bump) bonded to an external circuit, a tin metal layer bonded to an external circuit, and a tin-containing metal ball. (Using a ball-planting process), joining a tape (using tape bonding technology) or joining an external circuit through an anisotropic conductive adhesive; in addition, the metal pad is made by a glue/resistance 18 The seed layer 2 () on the adhesion/barrier layer 18 is formed with a metal layer 106 on the seed layer 2', and the metal pad 110 can be bonded to a wire (such as a gold wire or a copper wire). ), bonding - external circuit - metal bumps (such as gold bumps), bonding one of the external circuits containing a tin metal layer, bonding - tin metal balls (_ ball), bonding - tape (lion tape) From the φ dynamic bonding technique) or through an anisotropic conductive paste to bond an external circuit. Gradually, when the metal interface 110 _ wire bonding process engages a wire conductor (such as gold wire or copper wire), the metal pad (10) uses a tape bonding technology to join a tape. Alternatively, when the metal interface 110 is bonded by a wire bonding process (such as a gold wire or a copper wire), the metal pads 1〇8 are also joined by a wire bonding process such as a gold wire or a copper wire. Alternatively, when the metal connection 塾ιι〇 is bonded by a wire bonding process (such as a gold wire or a copper wire), the metal interface 108 is bonded to a metal bump of an external circuit (such as a gold bump). Or, when the metal pad 11〇 is bonded by a wire bonding process to a dozen wire conductors (such as gold wire or copper wire), the metal connector 1〇8 is bonded - the external circuit - the tin-containing metal layer or the - tin-containing metal ball. Alternatively, when the metal pad 110 _ wire bonding process engages a wire conductor (such as a gold wire or a steel wire), the metal pad 108 is bonded to an external circuit through the anisotropic conductive paste. For example, when the metal pad 110 engages a metal bump (such as a gold bump) of an external circuit, the metal turn 108 engages a tape using tape-bonding automated bonding techniques. Alternatively, when the metal pads 11 接合 are bonded to the metal &amp; block (such as gold bumps) of the external circuit, the metal contacts 1 〇 8 are bonded by a wire bonding process (such as a gold wire or a copper wire). Alternatively, when the metal interface 11 is bonded to a metal &amp; block (such as a gold bump) of an external circuit 51, the metal pad 108 also engages an external circuit - a metal bump (such as a gold bump) or a bump. When the metal pad m is bonded to a metal bump of an external circuit (such as a gold bump, the metal interface is bonded to an external circuit - a tin-containing metal layer or a tin-containing metal ball. Or, when the metal 11G is bonded - an external circuit - Metal bumps (such as gold _ when all 塾 1G8 through the anisotropic joint dance _ external circuit. For example, when the metal is connected (four) 〇 joint - external circuit - tin metal layer or - tin metal ball, Metal pad 1 () 8 is bonded - one of the external circuit metal bumps (such as gold bumps). Or, when the Lu metal. pad 110 is bonded - one of the external circuits contains a tin metal layer or a tin-containing metal ball , metal joints. 108 use the tape automatic bonding technology to join a tape. Or, when the metal is connected (four) to connect one. One of the external circuits contains a tin metal layer or a tin-containing metal bar metal interface 1〇8 utilization Wire-to-wire • Bonding—wire wire (such as gold wire or copper wire). Or, when metal joints are joined - External circuit - When tin-containing or bismuth-containing gold, the metal pad (10) is also bonded - one of the external circuits contains a tin metal layer or a tin-containing metal ball. Or, when the metal pad 11 is bonded to an external One of the circuits contains a tin metal layer or a tin-containing metal material, and the metal pads (10) are bonded to the outer φ portion circuit through the anisotropic conductive paste. For example, the metal pads 108 are bonded by a wire bonding process to a wire conductor (such as a gold wire). Or steel wire), the mating mat 110 is attached with an automatic joining technique-bonding tape, or when the metal joint is made by a wire bonding process-wire bonding wire (such as a gold wire or a steel wire), the metal pad 110 The wire bonding process is also used to bond a wire (such as a gold wire or a copper wire). Alternatively, when the metal pad (10) is bonded to a wire conductor (such as a gold wire or a copper wire) by a wire bonding process, the metal pad 110 is bonded to an external circuit. a metal bump (such as a gold bump) or a metal pad 108 bonding a wire conductor (such as 52 1376758 gold wire or copper wire) by a wire bonding process, the metal pad 110 bonding one of the external circuits containing tin metal Layer or a tin-containing metal ball. Or 'metal joint 108 side hit When the wire process is bonded to a wire conductor such as a gold wire or a copper wire, the metal pad 110 is bonded to an external circuit through the anisotropic conductive paste.

For example, when the metal pad 108 is bonded to a metal bump (such as a gold bump) of an external circuit, the metal pad no is bonded using a tape-bonding technique. Alternatively, when the metal pads 1 〇 8 are bonded - the metal bumps (such as gold bumps) of the external circuit, the metal contacts 11 〇 are bonded by a wire bonding process - a wire wire (such as a gold wire or a copper wire). Alternatively, when the metal pads 1 〇 8 are bonded to a metal bump (such as a gold bump) of an external circuit, the metal pad 110 is hybridized with a metal bump (such as a gold bump) of an external circuit. Alternatively, when the metal interface 108 is bonded to one of the metal bumps (such as gold bumps) of the external circuit, the metal interface 11G is bonded to the external circuit - the tin-containing metal layer or the tin-containing metal ball. Alternatively, when the metal pad 108 is bonded to one of the metal bumps (e.g., gold bumps) of the external circuit, the metal interface (10) is bonded to an external circuit through the anisotropic conductive ridge. When the port is electrically tinned with a tin metal layer or a tin-containing metal j, the metal is bonded to the external circuit - a metal bump (such as a gold bump). Alternatively, when the pad (10) is bonded to an external circuit - a tin-containing metal layer or a tin-containing metal ball, the metal bond is bonded to the tape by an automatic bonding technique. Or, if the gold is connected to the external-electrical and - tin-containing metal layer or a tin-containing metal ball, the metal is connected to the 塾 ι 〇 using a wire bonding process - a wire conductor (such as a gold wire). Alternatively, the metal interface (10) is bonded to a layer of an external circuit or a tin-containing fabric, and the gold pad nG is also bonded to the surface of the circuit - or the tin-containing layer (10) is bonded to the surface. - When a tin-containing metal ball is used, the metal pad η_ anisotropy is said to be joined, the circuit.曰^ 53 1376758 In addition, the four structures of the metal and the metal layer 1〇6 of the metal dynasty are topped with gold layers. When the metal is connected to the metal layer of ιι〇 (10), the wire bonding process is used. When joining the gold wire, the metal that is picked up by the metal can be joined by the ship with automatic joining technology. Alternatively, when the metal layer (10) of the metal pad 11 is bonded to a gold wire by a wire bonding process, the metal layer 1〇2 of the metal interface (10) may also be bonded to a gold wire by a wire bonding process. Or 'when the metal layer (10) of the metal pad 11G is connected - the external circuit - the metal is as full as the outline, the metal layer of the metal (10) is attached to the tape by an automatic bonding technique. Alternatively, when the metal layer (10) of the metal pad 11G is bonded to a metal bump (such as a gold bump) of the external circuit, the metal layer 102 of the metal pad can be bonded to a gold wire by a wire bonding process. Alternatively, when the metal layer (10) of the metal pad m is bonded to one of the metal pads of the external circuit (such as a gold bump), the metal of the metal pad 108 may also be bonded - the external circuit - the metal bump (such as gold) Bump). Therefore, in this embodiment, a tin-containing metal layer for bonding a wire bonding wire, a bonding tape, a bonding-external circuit, a bonding-external circuit, and a bonding may be respectively formed on the interface exposed by the opening of the protective layer. The age of the ball; or the two different thicknesses of the metal joint (10) and the metal through the heterogeneous conductive hybrid circuit are difficult to 11〇. In addition, the metal pad (10) and the top of the metal interface 110 may also include a --adhesive layer (not shown) for connecting a wire bonding wire (such as a gold wire), and the adhesion film layer is, for example, a gold layer. Referring to the 7D circle, after the above process is completed, the semiconductor substrate 2 can be subsequently cut to form a plurality of semiconductor crystals>1 112', wherein each of the wafers 112 includes a semiconductor substrate line, a structure 6, and a plurality The dielectric layer 12, the protective layer η, at least the metal pads 1〇8 and the metal contacts 110, and the like. Another 'complex semiconductor component 4 (such as transistor or metal oxide 54 1376758 semiconductor, etc.) is located above the bottom of the drunken county 2, and this is reported in the element 4 - selective position in the metal interface 1 () 8 Or, under the metal pad 11Q, two of the semiconductor elements 4 are electrically connected to the metal pads 1〇8 and the metal pads ιι. Further, at the top of each of the semiconductor wafers 112, the top of the protective layer 14 may be a layer of a monolithic compound or a layer of a nitrogen-containing compound. - each semiconductor wafer 112 can be connected to an external circuit through a metal interface 1〇8 and a metal pad no. The external circuit can be a semiconductor wafer, a printed circuit board, a flexible board, a substrate containing a ceramic material, and a "subtraction" A silk red shaft member whose towel has a glass fiber, and the soft plate comprises a polymer layer having a thickness of between 30 micrometers and 2 micrometers, such as a phthalocyanine. The connection method includes: - forming a wire bonding wire (such as a gold wire or a copper wire) through a wire bonding process to bond a metal pad of a semiconductor chip, and then connecting with an external circuit; 2. bonding through an automatic tape bonding technique - taped to - a gold pad of a semiconductor wafer, which in turn is connected to an outer 4 circuit. The tape has at least - gold and at least - polymerized, and the metal lines are connected to the metal pads, for example via tin metal or tin-silver alloy. a metal pad; three, using a metal bump (such as gold bumps) to bond a metal pad of the semiconductor chip, and then connected to an external circuit; four, through a thermal integration process, a metal wafer of a semiconductor chip Into the anisotropic conductive gel, the metal particles in the anisotropic conductive knee are gathered on the metal pad and the external circuit (such as a glass substrate) containing a pad of indium tin oxide. Indirectly, by electrically connecting the metal interface and the external circuit with the indium tin oxide-containing pad; five, using a tin-containing metal layer or a tin-containing metal ball to bond a metal pad of the semiconductor wafer, and thereby An external circuit is connected. In addition, the present embodiment can also bond a tin-containing metal layer, a tin-containing metal ball or a metal bump (such as a gold bump) through the metal pad 110 before the semiconductor substrate 2 is cut, and then connect an external 55 1376758 circuit. The circuit may be a semiconductor wafer, a printed circuit board, a flexible board, a glass substrate, a substrate containing a ceramic material or a passive component formed in advance. The ten printed circuit board contains glass fibers and the soft board comprises a thickness of between 30 micrometers and 200 micrometers. A polymer layer between, such as a polyimine. Next, the semiconductor substrate 2 is diced to form a plurality of semiconductor wafers. Then, in this embodiment, a wire bonding wire (using a wire bonding process), a bonding tape (using tape bonding automatic bonding technology) or an anisotropic conductive adhesive bonding an external circuit may be bonded to the metal pad 108 of each semiconductor wafer. Referring to FIG. 7E, 'this embodiment can also form a polymer layer 39 on the protective layer 14 first, and the polymer layer 39 is located in the polymer layer and is open to the polymer layer. Exposing the first pad 16a and the second pad i6b, and then forming a metal pad 108 on the first interface exposed by the polymer layer opening 39a according to the process steps described in FIGS. 7A-7D. And forming the metal interface 110 on the second interface brush exposed by the polymer layer. For the related content, please refer to the above-mentioned saying that the sun and the moon are not described in detail herein. Wherein, the polymer layer (10) is selected from the group consisting of polyaniline, phenylcyclobutene, polyurethane, epoxy resin, polyparaxylene polymer, welding cover, 'material, elastic material or porous dielectric material One of them, and the way to form the polymer layer is not only the spin coating method, but also the hot press dry film method or the screen printing method, and the thickness of the polymer layer 39 is 1 micron. Between 30 microns. Regarding the semiconductor wafer ma shown in Figure 7E, please refer to it for details. Further, the present embodiment can also be applied to a reconfiguration line or a connection line as in the second embodiment. Referring to FIGS. 7F and 7G, the present embodiment can simultaneously form a metal line 4 作为 as a reconfiguration line and a metal line as a connection line over the semiconductor substrate 2. 56 1376758. Second, implement relevant content. Then, according to the process steps described in FIG. 7A to FIG. 3, the metal pads 108 and the metal pads 110 are formed on the metal lines 40 and 42 exposed by the polymer layer opening 6〇a. The description will not be described in detail here. The related semiconductor chips 112b shown in Fig. 7F and the semiconductor wafer U2c shown in Fig. 7G are not to be described here. However, the present invention can also form only the relocation line or the connection line above the semiconductor substrate 2 by the above-described method, and further form the metal pad 108 and the metal pad 11 on the relocation line or the connection line. Sixth Embodiment: Referring to FIG. 8A, after completing the process step shown in FIG. 2A, a photoresist layer 114 is formed on the seed layer 20, and the photoresist layer is patterned through an exposure and development process. 114, to form the photoresist layer opening 114a in the photoresist layer 114 and expose the seed layer 2〇 located above the pad 16, and in the process of forming the photoresist layer opening 114a, for example, to double the exposure machine. Or the scanner is exposed. Then, a metal layer 116 having a thickness between 1 micrometer and 200 micrometers (for example, between 1 micrometer and 5 micrometers) is formed on the seed layer 2 of the photoresist layer opening n4a. The preferred thickness is between 2 microns and 30 microns. The manner in which the metal layer 116 is formed is, for example, electroplating or electroless plating. Alternatively, the metal layer 116 may be a single layer metal layer structure of gold, steel, silver, palladium, platinum, ruthenium, iridium, chain or nickel, or a composite layer composed of the above metal materials. For example, the metal layer 116 may be a gold layer formed by electroplating between 8 micrometers and 35 micrometers or a layer formed by electroplating having a thickness between 8 micrometers and 35 micrometers. Copper layer. Or 'forming the metal layer 116 by, for example, plating a copper layer having a thickness between 8 micrometers and 35 micrometers on a seed layer 2 of, for example, copper, and then having a thickness of 〇丨 micron to 10 A nickel layer between the micrometers (preferably having a thickness of between 1 micrometer and 5 micrometers) is on the copper layer - the final bond thickness is between 〇1 μm and 10 μm (preferably thickness) A layer of gold between 0 micrometers and 2 micrometers is on the recording layer. Referring to FIG. 8B, after the metal layer ι16 is formed, the photoresist layer 114 is subsequently removed. Continuing, the seed layer 2〇 and the adhesion/barrier layer 18 which are not under the metal layer Π6 are removed. Among them, the way to remove the adhesion/barrier layer 18 can be divided into dry silver etching and wet etching, while dry money etching uses high pressure argon gas for splashing silver etching, and in wet etching, when bonding/blocking When layer 18 is titanium or titanium tungsten, it can be removed using hydrogen peroxide. Further, when the seed layer 2 is gold, it can be removed by using an etchant containing iodine (e.g., an etching solution such as potassium peroxide). Thus, a plurality of metal pads 118 of the same thickness are formed on the plurality of pads 16 exposed by the plurality of openings of the protective layer 14. The metal pad 118 is composed of an adhesion/barrier layer 18, a sub-layer 2 on the adhesion/barrier layer 18, and a metal layer ι6 on the seed layer 2'. The pad 118 can be used to bond a wire conductor (such as a gold wire or a copper wire), a metal bump (such as a gold bump) that engages an external circuit, a tin-containing metal layer of the bonding-external circuit, a bonded tin-containing metal ball, and a bonding tape. (Using tape bonding technology) or joining an external circuit through an anisotropic conductive paste. For example, when a portion of the metal joint 118 is joined by a wire bonding process (e.g., a gold wire or a steel wire), the remaining metal joints 188 are joined by a tape bonding technique. Or, when some of the metal pads 118 paste the wire bonding process - the county line (such as gold wire or copper wire), the remaining gold 58 ^ / 6758 is the pad 118 joint - one of the external circuit metal bumps (such as gold Bump). Alternatively, when a portion of the metal interface 118$ is bonded to a wire-bonding wire (such as a gold wire or a copper wire), the remaining metal pads are connected to a tin-containing metal layer containing a metal ball or an external circuit. Alternatively, when a portion of the metal connection 118 is bonded by a wire bonding process (such as a gold wire or a copper wire), the remaining metal contacts 118 - are joined to an external circuit through the anisotropic conductive paste. For example, when a portion of the metal pads 118 engage a metal bump (e.g., a gold bump) of an external circuit, the remaining metal pads 118 engage a tape using tape bonding techniques. Or when some of the metal joints 118 are joined to the external circuit-metal bumps (such as gold bumps), the remaining metal joints 118 are made by wire-bonding-wire wires (such as gold wire or copper wire or When a portion of the metal is bonded to the metal bump (such as a gold bump), the remaining metal pads 118 are bonded to a -3 tin metal ball or an external circuit - a tin-containing metal layer. When a part of the metal interface is connected to one of the metal bumps (such as gold bumps), the remaining metal pads 118 are connected to the external circuit through the anisotropic conductive adhesive. U Rutian. When the metal pad 118 is bonded to a tin-containing metal ball or one of the external circuits contains a tin metal layer, the remaining metal contacts 118 are bonded - external circuits - metal bumps (such as gold bumps). When the metal interface 118 is bonded to a tin-containing metal ball or a tin-containing metal layer of one of the external circuits, the remaining metal connector 118 is bonded to the tape by the tape bonding automatic bonding technique. When the tin-containing metal ball or the external circuit-containing the tin-gold eyebrow layer, the remaining metal joints are connected to the wire-punching process. Wire wire (such as gold wire _ wire). Or, when the metallized joint 118 joins a tin-containing metal ball or an external circuit-containing tin metal layer, the remaining metal _ 118 is bonded through the anisotropic conductive rubber External circuit 59 1376758 Again, the top layer of the metal layer 116 is a gold layer (such as the single nickel/gold structure described above, the dome screen is aa, ^ structure or copper / ', 曰 = ... 曰), this In an embodiment, all or a portion of the metal-bonded metal layer 116 may be bonded to a gold bump of an external circuit _ π circuit, or may be bonded by a wire-bonding process of a metal age 118 butterfly - gold wire.

Therefore, in this embodiment, a metal warfare for bonding a wire bonding wire, a bonding tape, bonding an external circuit, a tin-containing metal layer of a bonding-external circuit, and a bonding age can be formed on a pad exposed by the opening σ of the protective layer. A ball or a plurality of metal pads 118 having the same thickness joined to the external circuit by an anisotropic conductive paste. In addition, the top of the metal pad 118 may also include an adhesive film layer (not shown) for connecting a wire bonding wire (such as a gold wire), and the adhesion film layer is, for example, a gold layer.曰 第 第 第 第 第 第 第 第 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于 于The plurality of dielectric layers 12, a protective layer 14, and a plurality of metal contacts U8. In addition, a plurality of semiconductor elements 4 (such as transistors or metal oxide semiconductors) are located in or above the semiconductor substrate 2, and one of the semiconductor elements 4 is selectively positioned below the metal pads 118, and the semiconductors The components 4 are electrically connected to the metal pads 118, respectively. Further, in each of the semiconductor crystals &gt;! 120, the top of the protective layer 14 may be an oxonium compound layer or a ruthenium oxide compound layer. Each semiconductor wafer 120 can be connected to an external circuit through a metal pad 8 , which can be a semiconductor wafer, a printed circuit board, a flexible board, a substrate containing a ceramic material, a glass substrate or a passive component formed in advance, wherein the printed circuit board Containing glass fibers, and the soft board comprises a polymer layer having a thickness of between about 30 micrometers and 200 micrometers, such as polylactide, which is formed by a wire bonding process to form a wire conductor (such as gold wire or copper). The connection method includes: a metal pad 118 of the semiconductor wafer 120, and then connected to the external circuit; 2. bonding and bonding to the metal pad 118 of the semiconductor wafer 120 by the tape bonding technology, and further The circuit connection 'the tape has at least a metal line and at least a polymer layer and the metal line connects the metal interface 118, for example, by bonding a metal interface 118' via a tin metal or a tin-silver alloy - using a metal of an external circuit Bumps (such as gold bumps) are bonded—the metal pads 118' of the semiconductor wafer 12 are further connected to external circuits; and fourth, through a thermocompression bonding process, - Crystal Semiconductor

The metal interface 118 of the sheet 120 is pressed into the anisotropic conductive paste, so that the metal particles in the anisotropic conductive paste are concentrated on the metal interface 118 and the external circuit (such as a glass substrate) contains indium tin oxide. Between the pads of the object, the metal is connected to the external circuit to contain the tin oxide-containing interface, and the metal pad 118 of the semiconductor chip is bonded by the tin-containing metal layer or the tin-containing metal ball. Furthermore, it is connected to an external circuit. In addition, in this embodiment, before the semiconductor substrate 2 is cut, the tin-containing metal layer, the tin-containing metal lining or the metal bump (such as a gold bump) may be bonded through all or part of the metal interface 118, and the external circuit is connected. 'This external circuit can be a semiconductor wafer, a printed circuit board, a flexible board, a glass substrate, a substrate containing a germanium material or a passive component formed in advance, the printed circuit board of the towel contains glass fibers, and the flexible board includes a thickness of 3Q to A polymer-layer between coffee micrometers, such as a pro-imine. Next, the semiconductor substrate 2 is patterned to form a 'multiple semiconductor wafer. Finally, 'bonding the wire (using the wire bonding process) to the unbonded metal bump or the metal pad 118 of the tin-containing metal layer of each semiconductor wafer 12's bonding tape (using tape bonding technology) or transmitting The square conductive paste is bonded to an external circuit. 61 1376758 Please refer to FIG. 8D. 'This embodiment may also form a polymer layer 39 on the protective layer 14, and the plurality of polymer layer openings 39a located in the polymer layer 39 expose the plurality of interfaces 16, Then, according to the process steps described in FIG. 8A to FIG. 8B, a plurality of metal contacts are formed on the pads 16 exposed by the polymer layer opening 39a. For details, please refer to the above description. Add a narrative. Wherein, the polymer layer 39 is selected from the group consisting of polyimine, phenylcyclobutene, polyurethane, epoxide, poly(p-phenylene), solder mask material, elastic material or porous dielectric The material layer 39 can be formed by using a thermocompression dry φ film method or a screen printing method in addition to the spin coating method, and the thickness of the other polymer layer 39 is between 1 micrometer and 3 〇 between the micrometers. Please refer to the above for related applications of the semiconductor wafer 120a shown in FIG. 8D, and will not be described here. Furthermore, the present embodiment can also be applied to a reconfiguration line or a connection line as in the second embodiment. Please refer to FIG. 8E and FIG. 8F at the same time, this embodiment can simultaneously form a metal line 4〇 as a reconfiguration line and a metal line as a connection line on the semiconductor substrate 2, and the second method is described. related information. Next, according to the steps 8A to 8B, the metal pad 118 is formed on the metal lines 4〇, ·_42 exposed by the polymer layer opening σ 60a. I will not repeat the details here. Please refer to the above-mentioned Neigu for the related applications of the semiconductor wafers and the material wafers shown in Figure 8F. However, in the above manner, the present invention can also form only the re-distribution line or the connection line on the semiconductor substrate 2, and further form the metal pad 118 on the reconfiguration line or the connection line. Illustrated as a cross-sectional view of a multi-chip package structure, as shown, 62 1376758 semiconductor wafer 122 may be formed by the fifth embodiment of semiconductor wafer 112, semiconductor wafer 11.2a, semiconductor wafer 112b or semiconductor wafer 112c, Or the semiconductor wafer $12G, the semiconductor crystal i20a, the semiconductor wafer 12Gb or the semiconductor wafer 120c' formed in the sixth embodiment. Therefore, the semiconductor wafer 122 has metal pads 126 for bonding wire bonding wires and for-bonding tapes. The metal substrate 128 has a metal pad 130 for bonding the wire bonding wire. The structure and material of the metal pad 130 are the same as those of the metal interface 118 described in the sixth embodiment. Moreover, through the wire bonding process, the wire bonding wires 132 are bonded to a metal interface 126 g and a metal pad 13 . The first compound 134 covers the metal interface 126 of the semiconductor wafer 122 , the semiconductor wafer 124 and the wire bonding wire 132 ' The polymer 134 is selected from the group consisting of polyimine, benzoin, polyurethane, % oxygen resin, xylene polymer, enamel material, heteromaterial or porous dielectric material. Moreover, through the heat bonding process, the flexible tape 78 having at least the metal line 74 and the polymer layer 76 is connected to the metal interface 128 through the metal line 74, and the metal line _74 of the soft tape π is, for example, via a metal. The layer 79 (for example, tin metal or tin-silver alloy) is joined to the metal joint, wherein the layer is selected from the group consisting of polyimine, phenyl ring, polyether, epoxy resin, poly(p-dimethylene) One of a polymer, a welding cap material, an elastic material or a porous dielectric material. In addition, a poly 136 covers the metal interface 128 and a portion of the metal line %, wherein the polymer (10) is selected from the group consisting of an imine phenyl% butene, a polyurethane, an epoxy resin, a parylene polymer, and a solder. Cover _ One of materials, elastomeric materials or porous dielectric materials. As described above, the metal interface (10) can be connected to an external circuit through the tape 63 by the tape bonding automatic bonding technology. The external circuit can be a semiconductor wafer, a printed circuit board, a flexible board or a substrate containing a ceramic material. The circuit board contains glass fibers, and the soft board comprises a polymer layer having a thickness of between 30 micrometers and 200 micrometers, such as a polyimide. - Seventh embodiment: Referring to FIG. 10A, after the process step shown in FIG. 2A is completed, a photoresist layer 138 is formed on the seed layer 20, and the photoresist layer is patterned through an exposure and development process. 138, forming a photoresist layer opening 138a in the photoresist layer 138 and exposing the seed layer 20' located above the first pad i6a, and in the process of forming the photoresist layer opening 138a, for example, double exposure Machine or scan, the machine is exposed. Further, a metal layer 140 having a thickness of between 1 μm and 500 μm is formed on the seed layer 20 exposed by the photoresist layer opening 138a, and the metal layer 14 is formed by, for example, electroplating or electroless plating. In addition, the metal layer 14〇 may be a single layer metal layer structure of gold, copper, silver, palladium, platinum, rhodium, bismuth, ruthenium or ruthenium, or a composite layer composed of the above metal materials, and the thickness thereof is more favorable. Between 2 micron and 3 〇 micro-between. For example, the metal layer may be formed by an electric clock in a gold layer having a thickness of between 8 micrometers and 35 micrometers or formed by electroplating - the thickness of the layer is between 8 micrometers and 35 micrometers. a copper layer. Alternatively, the metal layer 140 is formed by, for example, plating a copper layer having a thickness of between 8 μm and 35 μm on a seed layer 20 of, for example, copper, followed by a plating thickness of between 0.1 μm and 1 μm. A layer of nickel between the micrometers (preferably having a thickness between 〇1 μm and 5 μm) is on the copper layer, and finally the thickness of the clock is between 〇1 μm and 1 μm (preferably A layer of gold having a thickness of between 1 μm and 2 μm is on the layer. 64 1376758 In addition, the metal layer 140 may be replaced by a tin-containing metal in addition to the metal material mentioned above, and the tin-containing metal is a tin-tin alloy, a tin-silver alloy, a tin-silver-copper alloy or an age-free gold, and Good thickness; | between 3 microns and 250 microns. In addition, when the metal layer 140 is a tin-containing metal layer, • a diffusion barrier layer may be formed before forming the metal layer 140 (not shown in the drawing, please refer to the above description) in the photoresist layer opening 138a. The exposed seed layer 2 is further formed on the diffusion barrier layer, wherein the diffusion barrier layer is, for example, a recording layer having a thickness of 1 micro to 5 micrometers and a thickness of 〇 A copper layer of 5 microns to 1 μm and a layer of nickel on the copper layer.曰 Referring to FIG. 10B, after the metal layer 14 is formed, the photoresist layer 138 is subsequently removed. • Continue, removing the seed layer 20 without/barrier layer 18 that is not under the metal layer 140. Among them, the way to remove the 7-turn layer 18 can be divided into the domain _ and the wet side, while the rest is sprayed and etched using high voltage extinction, and in the wet etching, when the adhesion/barrier layer 18 is Qin or Qinhe alloy. When used, it can be removed with hydrogen peroxide. Further, when the seed layer 2 is made of gold, it can be removed by using an etchant containing ruthenium (e.g., an etchant such as potassium iodide). _ Therefore, the metal pad 142 is formed on the first layer 16a of the protective layer 14 which is exposed by the opening. The metal interface 142 is formed by an adhesive/barrier layer 18, which is in the adhesion/resistance. The seed layer 2〇 on the barrier layer 18 is formed with a metal layer 14〇 on the seed layer 2〇, and the metal pad 142 can be bonded to a wire conductor (such as a gold wire or a copper wire) and bonded. One of the external circuits is a metal. (10) such as a gold bump), an external circuit is bonded—a tin-containing metal layer, a tin-containing metal ball is bonded (using a ball-planting process), and a joint-gull tape is used (using an automatic tape bonding technique). Or an external circuit is bonded through an anisotropic conductive paste. 65 1376758 Please refer to the following description, after completing the above process, the semiconductor substrate 2 can be bonded to form a plurality of semiconductor wafers 144, wherein each semiconductor wafer 144 includes a semiconductor substrate 2, a wiring structure 6, and a plurality of dielectrics. The layer 12, a protective layer 14 and at least one metal interface 142 - and the like. Further, a plurality of semiconductor elements 4 (for example, an electric (10) or a metal oxide semiconductor, etc.) are located in or above the semiconductor substrate 2, and the semiconductor elements 4 are selectively positioned below the metal pads 142. These semiconductor elements 4 are electrically connected to the metal contacts 142. Further, in each of the semiconductor wafers 144, the top of the protective layer 14 may be an oxy-Wei-compound layer or a nitrogen-N hybrid layer. Next, after forming the plurality of semiconductor wafers 144, a wire bonding wire 146 (e.g., gold wire or copper wire) is bonded through the wire bonding process to bond a second pad i6b of the half chip 144 which is not formed with the metal interface 142. Therefore, each semiconductor wafer 144 can be bonded to the external wiring by a wire bonding process on the second interface of the metal pad 142, and the external circuit can be connected through the metal pad 142. , printing secret board, city, the substrate containing the shouting, the lion component of the Boli domain, the printing board of the board contains the face age, and the soft board ♦ includes a polymerization thickness between 30 microns and 200 microns. The layer of the polymer, such as a polyimine. The method of connecting the external circuit of the metal interface 142 includes: forming a wire wire (for example, a gold wire or a copper wire) to join the metal pad 142 through a wire bonding process, and then connecting with an external circuit; Bonding a tape to the metal pad 142 to be connected to an external circuit, wherein the tape has at least one metal line and at least one polymer layer, and the metal line connects the metal pads 142, for example via tin metal or tin-silver alloy Bonding the metal pad 142 3. Using metal bumps (such as gold bumps) to bond the metal pads 142, and then connecting with an external circuit; Fourth, through the heat 66 1376758 waste process "press the metal interface 142 into the alien In the conductive adhesive, the metal particle residual metal pad 142 in the anisotropic conductive paste is electrically connected to the indium tin oxide-containing pad of an external circuit (such as a glass substrate). The metal interface 142 is connected to the external circuit with a nano oxide; and the metal interface 142 is bonded by a tin-containing metal layer or a tin-containing metal ball, and is further connected to an external circuit. In addition, in this embodiment, before the semiconductor substrate 2 is cut, a tin-containing metal layer, a tin-containing metal ball or a metal bump (such as a gold bump) is bonded to the metal pad 142, and then an external circuit is connected, and the external circuit is connected. It may be a semiconductor (9), a printed circuit board, a flexible board, a substrate containing a ceramic material, or a previously formed passive component, wherein the printed circuit board contains glass fibers, and the flexible board includes a thickness between 30 micrometers and 200 micrometers - A polymer layer, such as a polynymine. e, the semiconductor substrate 2 is turned into a plurality of semiconductors. Finally, the wire bonding wires 146 are joined by a wire bonding process on the second pad of each of the semiconductor wafers 144 where the metal pads 142 are not formed. 10D shows that this embodiment can also form a polymer layer 39 on the protective layer 14, and a polymer layer opening 39a and a polymer layer opening 39b in the polymer layer 39 are respectively exposed. The first interface '16a and the second pad 16b' are then formed into a plurality of semiconductor wafer faces according to the process steps described in FIGS. 1A to 10C. Each of the semiconductor wafers may be formed without a metal interface 142. The second interface 16b is connected to the wire bonding wire 146 by a wire bonding process, and is connected to the external circuit through the metal interface 142. For the related description, please refer to the above content, and the table will not be described in detail. , selected from the group consisting of polyaniline, phenylcyclobutylene, polyurethane, epoxy resin, polyparaxylene polymer, welding cap material, and elastic material puncturing dielectric (4) _, 67

Further, the present embodiment can also be applied to a reconfiguration line or a connection line as in the second embodiment. Please refer to the second paste and the figure as shown in the figure. In this embodiment, the metal line 4 () which is a re-distribution line and the metal line as the connection line can be simultaneously formed on the semiconductor substrate 2, and the formation method can be referred to. Second, implement relevant content. Then, according to the gas path step described in the first to the first drawings, the metal joint 142 is formed on the metal line 40 42 exposed by the opening of the polymer layer. [Related contents, please refer to the above description. Said. Further, the wire bonding wire 146 is joined by the wire bonding process on the pad 46 on which the metal wires 40 and 42 are not connected to the wafer transfer substrate of the semiconductor wafer 14 (shown as _), and the external circuit is connected through the metal interface 142. Please contact us for your comments. However, in the above manner, the present invention can also form a metal interface (4) on the reconfiguration line or the connection line on the reconfigurable line or the connection line only after the alkali is reconfigured or connected on the substrate 2, and after being cut into a semiconductor wafer, The bonding process is performed on the pads 46 which are not connected to the metal wires 4G and 42.

The wire 146 is connected to the external circuit through the metal pad 142. Eighth Embodiment: «Month Referring to FIG. 11A' After completing the process steps shown in FIG. 2A, a photoresist layer 148 is formed on the seed layer 20 and the photoresist layer is patterned through an exposure and development process. 148, to form the photoresist layer opening 148a in the photoresist layer 148 and expose the seed layer 20' located above the first interface, and in the process of forming the photoresist layer 14, for example, double Exposure machine or scan 68 1376758 machine for exposure. Please refer to Figure 11B for the thickness formed! A metal layer 150 between micrometers and 5 micrometers is formed on the seed layer 2 of the photoresist layer opening 148a, and the metal layer 15 is formed in a manner such as a key or an electric clock. In addition, the metal layer 150 may be a single layer metal layer structure of gold 'copper, silver', #, 钌, 钌, 銶 or recorded, or a composite layer composed of the above metal materials, and its preferred thickness is Between 2 microns and 30 micro-bets. For example, the metal layer 15 can be formed by electroplating with a gold layer having a thickness of between 8 micrometers and 35 micrometers or by electrical volts forming between 8 micrometers and 35 micrometers. A copper layer. Alternatively, the metal layer 150 is formed by, for example, plating a copper layer having a degree of between 8 micrometers and 35 micrometers on a seed layer 20 of, for example, copper, followed by a plating thickness of 0.1 micron to A nickel layer between 10 micrometers (preferably ♦ thickness between 1 micrometer and 5 micrometers) is on the copper layer, and the final bond thickness is between 0.01 micrometers and 10 micrometers. A gold layer between 0 1 micron and 2 microns is on the town layer. In addition, in addition to the metal material mentioned above, the metal layer 150 may also be replaced by a tin-containing metal, which is a tin-lead alloy, a tin-silver alloy, a tin-silver-copper alloy or a lead-free alloy, and The thickness is between 3 microns and 250 microns. In addition, when the metal layer 150 is a tin-containing metal layer, a diffusion barrier layer may be formed before forming the metal layer (not shown in the drawing, as described in the foregoing), in the photoresist layer opening 148a. The exposed seed layer 20 is then further formed with a metal layer 丄5 on the diffusion barrier layer, wherein the diffusion barrier layer is, for example, a nickel layer having a thickness of between micrometers and 5 micrometers and a thickness of between 〇.5. A copper layer of micron to 1 〇 micron, and the recording layer is on the copper layer 0 69 1376758 months&gt; As shown in the figure of lie, after the metal layer 15 is formed, the photoresist layer is removed. Next, a light P layer 152 is formed on the seed layer 20, and the photoresist layer 152' is patterned by an exposure and development process to form a photoresist layer 152a on the seed layer 2 of the second junction (4) b as shown in the (10) figure. 'In the process of forming the photoresist layer 152a, for example, the exposure pin is performed by a doubler or a scanner. Please refer to the seed under the metal layer 15〇 and the photoresist layer as shown in Fig. 11E. Layer 20 and adhesion/barrier layer 18. Among them, the way to remove the adhesion/barrier layer can be divided into the dry side and the wet butterfly', and the dry butterfly, for example, makes the (four) pressure into the machine side, and in the case of the secret engraving, the persuasion/barrier layer ls is titanium. Or titanium dioxide alloy, can be removed with hydrogen peroxide. In addition, when the right seed layer 2 is gold, you can use the side liquid (such as hardening and unloading money • engraving) fans. After the I, the county hetero-layer 2G and the lin/pj# layer 18, the photoresist layer 152a is removed, as shown in the upper figure. Therefore, the metal interface 154 is formed on a first contact 16a exposed by the opening 14a of the protective layer 14. The metal pad 154 is formed by an adhesive/barrier layer 18 on the adhesion/barrier layer 18. The upper-seed layer 20 is formed with a -metal layer 150 on the seed layer 20, and the metal # pads I54 can be bonded to a wire conductor (such as a gold wire or a copper wire), and a metal bump of an external circuit is bonded. Blocks (such as gold bumps), joint-external circuits - tin-containing metal layers, bonding a tin-containing metal ball (using ball-planting techniques), bonding a tape (adhesive tape bonding technology) or by anisotropic Conductive adhesive. Engage an external circuit. In addition, a metal pad 156 is formed on a second pad 16b exposed by the opening 14a of the protective layer 14. The metal pad 156 is formed by an adhesive/barrier layer 18 and is positioned on the adhesion/barrier layer. A sub-layer 20 is formed on the 18, and the metal pad 156 can be bonded to a wire (such as a gold wire or a copper wire), a metal bump (such as a gold bump) bonded to an external circuit, and a 1376758 combination. One of the external circuits contains a tin metal layer, a tin-containing metal ball (using a ball-fed technique), a bonding tape (using tape bonding technology), or an external circuit through an anisotropic conductive paste. Referring to FIG. 11G, after the above process is completed, the semiconductor substrate 2 can be subsequently cut to form a plurality of semiconductor crystals 158, wherein each semiconductor wafer 158 includes a semiconductor substrate 2, a line structure 6, and a plurality of dielectric layers. The layer 12, a protective layer 14, at least one metal pad 154 and at least a metal. In addition, a plurality of semiconductor elements 4 (such as a transistor or a metal oxide semiconductor) are located in or above the semiconductor substrate 2, and one of the semiconductor elements 4 is selectively placed on the metal pad 154 or the metal pad. Below the 156, two of the semiconductor elements 4 are electrically connected to the metal pads 154 and the metal pads 156, respectively. In addition, at the top of each semiconductor wafer 158+, the top of the protective layer 14 may be a layer of a monolithic compound or a layer of a nitrogen compound. Further, after the formation of the plurality of semiconductor wafers 158, the metal pads 156 of the semiconductor wafer 158 can be bonded through a wire bonding process-forming wire (e.g., gold wire or copper wire). Therefore, each half of the wafer 158 can be bonded to the metal wire 156 by a wire bonding process and connected to the external circuit through the metal interface 154. The external circuit can be a semiconductor chip, a printed circuit board, a soft board, or a ceramic. a substrate, a glass substrate or a previously formed passive component, wherein the printed circuit board contains glass fibers, and the flexible board comprises a polymer layer having a thickness of between 30 micrometers and 200 micrometers. Imine. The method of connecting the external circuit of the Golden Auditorium 154 includes: - forming a wire conductor (such as a gold wire or a copper wire) through the wire bonding process to join the metal connector 154' and then connecting with the external circuit; 2. Bonding a sticker through the tape bonding automatic bonding technique The tape is connected to the external circuit, wherein the tape has at least one metal line and at least one poly-sigma layer and the metal line connects the metal interface 154, for example, via tin metal or tin-silver alloy bonding 71 1376758 metal pad 154; three, paste metal bumps (such as gold bumps) joint metal pads 154, and then connected to the external circuit; four, through the heat of the process, the metal interface 154 dust into the anisotropy Conductive. In the middle of the raft, the metal particles that make the position in the anisotropic conduction are concentrated between the metal interface 154 and an external circuit (such as a bismuth glass substrate) containing indium tin oxide. The connection between the metal connection 154 and the external circuit containing the tantalum oxide; and the use of the tin-containing metal layer or the tin-containing metal ball to bond the metal pad 154 to be connected to an external circuit. In addition, in this embodiment, before the semiconductor substrate 2 is cut, the tin-containing metal layer, the tin-containing metal ball or the metal bump (such as a gold bump) may be bonded to the metal interface 154, and then an external circuit is connected, and the external portion is electrically connected. The material is a semiconductor crystal #, a printed circuit board, a soft board, a substrate, a substrate containing a ceramic material, or a wire-like object, the towel board contains a glass Weiwei, and the soft board includes a thickness of 30 A polymer layer between micrometers and 200 micrometers, such as a polymerized polyimide. The semiconductor substrate 2 is then diced to form a plurality of body wafers 158. Finally, the metal pads 156 of each of the semiconductor wafers 158 are bonded by wire bonding processes (e.g., gold wires or copper wires). • Referring to the figure η, the embodiment may also form a polymer layer 39 on the protective layer 14 and a polymer layer opening 39a and a polymer layer opening 3% in the polymer layer 39. Exposing a first pad 16a and a second pad 16b respectively, and then forming a first connection of the metal pad 154 exposed in the polymer layer opening 39a according to the process steps described in FIG. 1 to FIG. The pad 16a and the metal pad 156 are formed on the second 'pad' 16b exposed by 3% of the opening of the polymer layer. Please refer to the above for related description, which will not be described in detail herein. In addition, the polymer layer 39 is selected from the group consisting of polyimine, phenylcyclobutene 'polyurethane, epoxy resin, polyparaxylene, high 72!376758 molecules, welding cap material, elastic material or porous media. One of the electrical materials, and the manner in which the polymer layer 39 is formed, in addition to the manner, can also be used in a dry or a screen printing manner. The thickness of the other polymer layer 39 is between 1 micrometer and 30 micrometers. between. Please refer to the above for the related application of the semiconductor wafer 15 shown in Fig. 11H, and will not be described here. - The present embodiment can also be as shown in the second embodiment of the striker in the reconfiguration line or the connection line month, as shown in FIG. 111 and the 11th circle. This embodiment can be used as the Wei line at the same time above the semiconductor substrate 2. The metal line 4 () and the metal line as a wire path are committed, and the method of formation is referred to the second embodiment. Next, in accordance with the process steps described in FIGS. 11A to 11F, the metal pads 154 are formed on the metal lines exposed on the polymer layer, and the metal contacts 156 are formed in the polymer layer openings. For the metal wire and road 42 exposed, please refer to the above description for details. It will not be described in detail here. In addition, on the metal pad 156 of the semiconductor wafer 158b (shown in FIG. 111) or the face of the material wafer (shown in the figure), the wire bonding process is used to bond the wire and the wire, and the external circuit is connected through the metal interface (5). Please also refer to the related content. However, this issue can be used in a diligent manner, in the semi-guided warship 2 rules, tearing, (four) _ spicy road or connection •, the formation of metal difficult 154 and metal joint 156 on the line, and in the _ riding conductor W After that, the wire bonding process is combined with the wire bonding process on the metal interface I56, and the external circuit is connected through the metal connector (5). The above description of the present invention is made by way of examples, and the purpose of the invention is to enable the skilled person to understand the invention and to implement the invention, and not to limit the scope of the invention. Equivalent modifications or modifications made by the spirit of the present invention should still be included in the scope of the patent application described in the No. 73 1376758. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic cross-sectional view showing a wafer of the present invention. 2D to 21 are schematic cross-sectional views showing a process of an embodiment of the present invention. 3D to 3D are schematic views of a light cross section of an embodiment of the present invention. Figure 4 is a cross-sectional view showing a multi-chip package structure in accordance with an embodiment of the present invention. 5A to 5D are schematic cross-sectional views showing a process according to an embodiment of the present invention. 6A to 6J are schematic cross-sectional views showing a process of an embodiment of the present invention. 7A to 7G are schematic cross-sectional views showing a process of one embodiment of the present invention. 8A to 8F are schematic cross-sectional views showing a process according to an embodiment of the present invention. Figure 9 is a cross-sectional view showing a multi-chip package structure according to an embodiment of the present invention. 10A to 10F are schematic cross-sectional views showing a process according to an embodiment of the present invention. Lu 11th to 11th are schematic cross-sectional views of a process according to an embodiment of the present invention. Description of the drawings: 4 semiconductor component 8 metal wiring layer 12 dielectric layer 14a opening 2 semiconductor substrate 6 wiring structure 10 metal plug 14 protective layer 1376758 16 pad 16b second pad 20 seed layer 22 photoresist layer 24 metal layer 28 Adhesive/barrier layer 32 photoresist layer φ 34. diffusion barrier layer 38 semiconductor wafer 39 polymer layer 39b polymer layer opening 42 metal line 44a opening 48 polymer layer ^ 48b polymer layer opening 54 seed layer 56a photoresist layer Opening 60 polymer layer '62 semiconductor wafer' 64 semiconductor wafer 68 metal pad 16a first pad 18 adhesion/barrier layer 20' seed layer 22a photoresist layer opening 26 metal pad 30 seed layer 32a photoresist layer opening 36 Tin-containing metal layer 38' semiconductor wafer 39a polymer layer opening 40 metal line 44 protective layer 46 pad 48a polymer layer opening 52 adhesion/barrier layer 56 photoresist layer 58 metal layer 60a polymer layer opening 62' semiconductor wafer 66 Semiconductor wafer 70 metal pad 75 1376758 72 polymer 76 polymer layer 79 metal layer 82 photoresist layer 84 metal pad 87 semiconductor wafer 88 copper layer g 92 nickel layer 95 pad 97 external circuit 98 tin metal ball * 99 semiconductor Sheet 99b semiconductor wafer 100 photoresist layer I. 102 metal layer 104a photoresist layer opening 108 metal pad 112 semiconductor wafer 112b semiconductor wafer - 114 photoresist layer 116 metal layer 74 metal line 78 soft tape 80 polymer 82a photoresist layer 86 semiconductor wafer 87' semiconductor wafer 90 copper layer 94 gold layer 96 metal pad 97' external circuit 98' tin-containing metal layer 99a semiconductor wafer 99c semiconductor wafer 100a photoresist layer opening 104 photoresist layer 106 metal layer 110 metal pad 112a Semiconductor wafer 112c semiconductor wafer 114a photoresist layer opening 118 metal pad 76 1376758 120 semiconductor wafer 120b semiconductor wafer 122 semiconductor wafer 126 metal pad 130 metal pad 134 polymer 138 photoresist layer g 140 metal layer 144 semiconductor wafer 144b semiconductor wafer 4 146 wire conductor i 148a photoresist layer opening 152 photoresist layer 154 metal pad φ 158 semiconductor wafer 158b semiconductor wafer 120a semiconductor wafer 120c semiconductor wafer 124 semiconductor wafer 128 metal pad 132 wire conductor 136 polymer 138a photoresist layer opening 142 Metal pad 144a semiconductor wafer 144c semiconductor wafer 148 photoresist layer 150 metal layer 15 2a photoresist layer 156 metal pad 158a semiconductor wafer 158c semiconductor wafer 77

Claims (1)

1376758 Patent application No. 096,107,214, Chinese patent application, replacement of this patent (September 100) X. Patent application scope|丨(四)月” 曰修(发发)本本1. A circuit component, including: glass substrate; soft board, Including a polymer material; a passive component; and a semiconductor wafer including a semiconductor substrate, a wiring structure over the semiconductor substrate, a dielectric layer over the wiring structure, a plurality of aluminum-containing pads over the dielectric layer, The circuit structure and the protective layer above the dielectric layer and the plurality of metal pads above the protective layer, wherein the circuit structure comprises a metal circuit layer made of copper, the dielectric layer having a thickness of less than 3 micrometers, the protection The layer contacts the upper surface and the sidewall of each of the aluminum-containing pads, the protective layer containing a nitrogen cerium compound, a oxynitride compound or an oxonium compound, each of the metal pads including an adhesion/barrier layer and the adhesion layer a first metal layer over the barrier layer, the adhesion/barrier layer not contacting the sidewall of the first metal layer, and the first metal connection in the metal pads The pad is connected to the pad of the glass substrate, and the first metal pad is connected to the first aluminum-containing pad in the aluminum-containing pads via a first opening in the protective layer, where the first metal pad is located Between the protective layer and the pad of the glass substrate, the top of the first metal pad does not include or contact 143038-1000922.doc 日日修(史,,正二—......... tin Metal, the first metal pad is not connected to the pad of the glass substrate via tin metal, a second metal pad of the metal pads is connected to the passive component, and the second metal pad is located via the protective layer a second opening is connected to the second aluminum-containing pad of the aluminum-containing pads, a third metal pad of the metal pads is connected to the soft plate, and the third metal pad is located at the protective layer The third opening is connected to the third aluminum-containing pad of the aluminum-containing pads. 2. The circuit component of claim 1, wherein the metal pads have gold ends at their tips. Such as the circuit component described in claim 1, wherein each of the metal pads A second metal layer is disposed between the adhesion/barrier layer and the first metal layer, the first metal layer contacting an upper surface of the second metal layer, the first metal layer having a thickness of 8 micrometers to 35 Between the micrometers, the thickness of the second metal layer is between 0.005 micrometers and 2 micrometers. 4. The circuit component of claim 1, wherein the first metal interface and the second metal interface And the third metal pad has the same composition. The circuit component of claim 1, wherein the semiconductor wafer further comprises a polymer layer on the protective layer, and the metal The pads are also located above the polymer layer 143038-1000922.doc 1376758 'year month e ...' Ben. 6. The circuit component of claim 1, wherein the first metal layer is a copper layer. 7. The circuit component of claim 6, wherein the copper layer has a thickness of between 8 microns and 3 microns. 8. The circuit component of claim 6, wherein each of the metal pads further comprises a gold layer, and the gold layer is over the copper layer. 9. The circuit component of claim 8 wherein the gold layer has a thickness between 0.1 microns and 2 microns. 1 . The circuit component of claim 8, wherein each of the metal pads further comprises a nickel layer, and the nickel layer is between the copper layer and the gold layer. The circuit component of claim 1, wherein the first metal layer has a thickness of between 8 micrometers and 35 micrometers. The circuit component of claim 1, wherein the first metal layer comprises a gold layer. The circuit component according to claim 1, wherein the adhesion/barrier layer comprises a zirconia, an illuminating titanium, a titanium alloy, a group, a nitrided group, a complex or a copper alloy. The circuit component of claim 1, further comprising a tin-containing metal, and the second metal pad connects the passive component via the tin metal containing 143038-1000922.doc 1376758. 15. The circuit component of claim 14, wherein the top end of the metal pads comprises gold. 16. The circuit component of claim 1, claim 14, or claim 15, further comprising an anisotropic conductive paste, and the first metal pad is connected via metal particles in the anisotropic conductive paste The pad of the glass substrate. The circuit component according to claim 1, wherein the pad of the glass substrate contains indium tin oxide. The circuit component of claim 1, wherein the metal pads contact an upper surface of the protective layer, the first metal pad is located above the first aluminum-containing pad, the second metal The pad is located above the second aluminum-containing pad, and the third metal pad is located above the third aluminum-containing pad. The circuit component of claim 1, further comprising another semiconductor wafer, and the fourth metal pad of the metal pads is connected to the other semiconductor wafer. 20. A circuit component comprising: a glass substrate; a flexible board comprising a polymeric material; a passive component; and a semiconductor wafer comprising a semiconductor substrate, a wiring structure over the semiconductor substrate, located at the wiring structure 143038-1000922.doc 1376758 An upper dielectric layer, a plurality of aluminum-containing pads over the dielectric layer, a protective layer over the circuit structure and the dielectric layer, and a plurality of metals on the protective layer and the aluminum-containing pads a circuit and a plurality of metal pads on the metal lines, wherein the circuit structure comprises a metal circuit layer made of copper, the dielectric layer having a thickness of less than 3 micrometers, the protective layer contacting each of the aluminum-containing pads The upper surface and the sidewall, the protective layer containing a nitrogen cerium compound, a oxynitride compound or an oxonium compound, each of the metal lines comprising a first metal layer, each of the metal pads comprising a second metal layer, a first metal line in the metal line is connected to the first aluminum-containing pad in the aluminum-containing pads via a first opening in the protective layer, the metal lines The second metal line is connected to the second aluminum-containing pads of the aluminum-containing pads via a second opening in the protective layer, and the third metal line of the metal lines is via the first layer located in the protective layer a third opening is connected to the third aluminum-containing pads of the aluminum-containing pads, wherein the first metal pads of the metal pads are connected to the pads of the glass substrate, and the first metal is connected via the first metal line An aluminum pad, the first metal pad is located between the protective layer and the pad of the glass substrate, the top of the first metal pad does not include or contact tin metal, and the first metal pad does not pass through the tin metal 143038-1000922.doc 1376758 connecting the pad of the glass substrate, a second metal pad of the metal pads connecting the passive component, and connecting the second aluminum-containing pad via the second metal line, a third metal pad in the metal pad is connected to the flexible board, and the third aluminum-containing interface is connected via the third metal line. 21. The circuit component according to claim 20, wherein the metal Top of the pad Including gold. 2. The circuit component of claim 20, wherein each of the metal pads further comprises a third metal layer under the second metal layer, the second metal layer contacting the third metal layer The upper surface, the second metal layer has a thickness of between 8 micrometers and 35 micrometers, the third metal layer has a thickness of between 0.005 micrometers and 2 micrometers, and the third metal layer does not contact the second metal layer Side wall. 2. The circuit component of claim 20, wherein the first metal pad, the second metal pad, and the third metal pad have the same composition. 24. The circuit component of claim 20, wherein the semiconductor wafer further comprises a polymer layer on the protective layer, and the metal lines are further on the polymer layer. 25. The line component as described in claim 20, 143038-1000922.doc 1376758 26. 27. 28. 29. 30. 3 1 . 32. The semiconductor wafer further includes a polymer layer over the protective layer and the metal lines, the polymer layer contacting an upper surface and sidewalls of the metal lines. The circuit component of claim 20, wherein the first metal line is connected to the fourth aluminum-containing pad in the aluminum-containing pads via a fourth opening in the protective layer, the first metal connection The pad is connected to the fourth aluminum-containing pad via the first metal line, and the first aluminum-containing pad is connected to the fourth aluminum-containing pad via the first metal line. The circuit component of claim 20, wherein the third metal line is a power bus, and the power bus is connected to a power line under the protection layer. The circuit component of claim 20, wherein the second metal layer is a copper layer. The circuit component of claim 28, wherein the copper layer has a thickness of between 8 microns and 35 microns. The circuit component of claim 28, wherein each of the metal interfaces further comprises a gold layer, and the gold layer is located above the copper layer. The circuit component of claim 30, wherein the gold layer has a thickness of between 0.1 micrometers and 2 micrometers. The circuit component of claim 30, wherein each of the metal pads further comprises a nickel layer, and the nickel layer 143038-1000922.doc 1376758 is located between the copper layer and the gold layer. 33. The thickness of the second metal layer in the line element of claim 20 is between 8 microns and between. 34. The second metal layer of the line element of claim 20, comprising the gold layer. 35. Each of the metal pads of the circuit element of claim 20 further comprising an adhesion/barrier layer under the first layer, the adhesion/barrier titanium, titanium nitride, titanium alloy , group, nitrided group chrome-copper alloy. 36. The line element of claim 20, comprising a tin-containing metal, and the second metal pad is connected to the passive component via a tin metal. 3 7. The top of the metal pads in the line elements described in claim 36 of the patent application includes gold. 38. The circuit component of claim 20, claim 36 or claim, further comprising an anisotropic conductive paste. The first metal pad connects the pad of the glass substrate via the anisotropic conductive adhesive inner particle. 39. The contact pad of the glass substrate in the circuit element according to claim 20 of claim 20 contains indium tin oxide. 40. According to the line element 143038-1000922.doc according to claim 20, 35 a micro-piece, the member of which has two metal layers including, a network or a member, and also includes the member, the item 37, and the metal member, which does not have 0 pieces, wherein the metal wires of the 1376758 contact the protective layer The thickness of the first metal layer in the line element as described in claim 20 is between 2 micrometers and between. 4. The article of claim 20, wherein the first metal layer comprises a copper layer. 4. The first metal layer comprises a gold layer in the line element of claim 20 of the patent application. 44. The line element of claim 1 includes another semiconductor wafer, and the metal is connected to the fourth metal pad to connect the other semiconductor wafer 45. As described in claim 20 The first metal layer in the line element includes a copper layer, and the second gold layer includes a gold layer 143038-1000922.doc. Piece, its 20 micron line component, its components, and the components in the pad,