TWI236722B - Chip structure - Google Patents

Abstract

A chip structure includes a semiconductor substrate, multiple thin film dielectric layers, multiple thin film circuit layers, a passivation layer, a metal circuit layer and at least a bump. The semiconductor substrate has multiple electronic devices arranged in the surface layer thereof. The thin film dielectric layers are positioned over the semiconductor substrate and have multiple via holes. Each of the thin film circuit layers is positioned on one of the thin film dielectric layers. The thin film circuit layers are electrically connected with each other through the via holes and electrically connected to the electronic devices. The passivation layer is disposed over the thin film dielectric layers and the thin film circuit layers. The metal circuit layer is disposed over the passivation layer. The bump is arranged on the metal circuit layer or on a contact of the thin film circuit layer, wherein the bump is not adapted to be reflowed. In an embodiment, the metal circuit layer has a metal layer, such as gold layer, with a thickness larger than 1 micrometer. The material of the bump includes gold.

Description

1236722 14012twf.doc IX. Description of the invention: [Technical field to which the invention belongs] The present invention relates to a wafer structure, and more particularly to a wafer structure having a metal circuit layer and a bump. [Previous technology] With the rapid advancement of information product technology, it is not difficult for human beings to obtain information thousands of miles away. It is an advantage for companies to gain timeliness through competition. This can be achieved by building efficient information products. . ^ With the integration of new and innovative product design and various circuit designs, the latest single film ^ 片 | provides more features than ever before. Due to the rapid development of semiconductor technology: the mass production of the φ 'copper process, coupled with the integration of circuits, most of the signal transmission can be in the same single chip, so that the signal transmission path can be shortened ^ chip performance can be improved. In the application of liquid crystal display panels, generally, a gold bump is formed on a driving chip first, and then a flexible board containing inner and outer pins is used to connect the gold bump and the substrate on the wafer so that the wafer can pass through the soft board. The method of electrically connecting to the substrate, in which internal bumps are bonded with gold bumps, is gold_gold (() 〇1 (1 _ = _ G () ld) eutectic bonding or gold-to-tin (Gold-to -Tin) solder joint, that is, a gold layer or a tin layer is plated on the inner pin first, and the gold layer or tin layer plated on the inner pin can be used with the gold bump on the driver chip. Bonding. Alternatively, an anisotropic conductive paste (ACP) or an anisotropic conductive film (ACF) can be formed on a glass substrate or a thin film substrate, and then the gold bumps are pressed. Into the anisotropic conductive adhesive or conductive film, the cluster of metal particles in the anisotropic conductive adhesive or conductive film can electrically connect the driving chip to a glass substrate or a thin substrate. As described above, Gold bumps are not joined to the soft by refl0w , Glass substrate, or thin film. 5 1236722 14012twf.doc However, the material of the bumps is not suitable for the re-soldering step: "For example, in the technical field of gold bumps, no circuit is formed in the driver chip. As other specific functions, the use of space is not in line with efficiency. [Summary of the Invention] In view of this, the object of the present invention is to provide a wafer structure which is not suitable for re-soldering. In the technical field of the step, since gold is formed on the protective layer of the semiconductor wafer, it can be used as a power plane or a ground plane for signal transmission, so the workshop on the protective layer is more efficient in use.-本 ίίΐί An object of the present invention is to provide a wafer structure including a substrate, a plurality of thin film dielectric layers, a plurality of thin circuit layers, a protective layer, a metal circuit layer, and at least one bump. A semiconductor substrate and There are many electronic components. The electronic components are arranged on a semiconductor substrate-a sheet ^ thin ^ arranged on a swivel substrate, and the thin film dielectric has a large number of conductions. ;, The age of the mother-phase circuit layer is placed on its towel-film dielectric layer, and the circuit layers are electrically connected to each other through the vias, and are electrically connected to the electronic and electrical layers on the Langlin road layer; Jin Qi The circuit layer is located on layer 1. The bumps are located on the metal circuit layer or the contacts of the thin film circuit layer. The bumps are materials that are not suitable for the reflow step. Among them: the production includes metal layers made of gold. The thickness of the metal layer is greater than 1 micron, for example, and the material f of the bump includes gold, for example. Zhu Qiao's f 'bump material is a technique that is not suitable for the reflow step =! The structure can have a metal circuit layer, which can be used as a signal transmission wheel or as a power plane or connection plane. So the space on the protective layer is more efficient in use. In order to make the above and other purposes, features, and advantages of this month more obvious 1236722 14012twf.doc

It, a preferred embodiment is enumerated below. Detailed description will be given in conjunction with the accompanying drawings. [Embodiment] The structure of the bump sheet is mainly characterized in that it is more practical in use alone! Efficiency II on the protective layer makes the space on the protective layer and the metal circuit layer is located in the protective layer. The layer aims at the function of the metal circuit layer, with the first reality of the structure; in the first embodiment of the wafer structure, the bumps are located on the metal circuit layer, and the following are several possible implementation scenarios: 1. Metal circuit layer Gu Yue as the signal transmission in the chip Refer to Figures 1 and 2, which show the cross-section diagram of the first implementation of the wafer structure according to the present invention, where the metal circuit layer 150 is used as a §iU tiger transmission in the chip, for example. use. The wafer structure 100 includes a semiconductor substrate 110, a plurality of thin film dielectric layers 122, 124, 126, a plurality of thin film circuit layers 132, 134, 136, and a protective layer 140. The semiconductor substrate 110 has a plurality of electronic components H2, and the electronic component η] is disposed on a surface layer of the semiconductor substrate 110. The semiconductor substrate 110 is, for example, a silicon substrate, and pentavalent or trivalent ions are doped, such as boron ions. Or phosphorus ions, thereby forming a plurality of electronic components 112 on the surface layer of the semiconductor substrate 110. The electronic components 112 are, for example, metal oxide semiconductors or transistors. Multiple thin-film dielectric layers 122, 124, and 126 are disposed on the semiconductor substrate 110. The thin-film dielectric layers 122, 124, and 126 are, for example, an oxy-silicon compound, a nitrogen-silicon compound, or an oxy-silicon compound. Each thin-film circuit layer 132 , 134, and 136 are respectively disposed on one of the thin film dielectric layers 122, 124, and 126, and the materials of the thin film circuit layers 132, 134, and 136 include aluminum, copper, or silicon, for example. Thin 1236722 14012twf.doc The thin film dielectric layers 122, 124, 126 have a plurality of via holes 12b, 123, 125, and the thin film circuit layers 132, 134, 136 can pass through the thin film dielectric layers 122, 124, 126 through the vias 121, 123 and 125 are electrically connected to each other and are electrically connected to the electronic component 112. The protective layer 140 is disposed on the thin film dielectric layers 122, 124, 126 and the thin film circuit layers 132 ^ 014, 136, wherein the thickness of the protective layer 14o The ratio is greater than 0.35 micrometers and the junction of the protective layer 140 is more specifically a diazite compound layer, an oxygen silicon compound layer, a phosphosilicate glass layer, or a composite layer composed of at least one of the foregoing materials. The protective layer 140 has a plurality of openings 14 ?, and exposes the thin film circuit layer 136 located in the reed. 9 The metal circuit layer 150 is located on Baoshuo | 14o, and is electrically connected to the thin film circuit layer 136 through the opening 142 of the protective layer 14o. One of the electronic components (e.g., the electronic component 112a) is suitable for outputting an electronic signal. The electronic signal is transmitted to the metal circuit layer 150 through the thin film circuit layers 132, 134, and 136 and passes through the protective layer 140. It then passes through the protective layer 14 and is transmitted to at least one of the other electronic components 112 (for example, the electronic component 112b) via the circuit layers 136, 134, and 132. In this way, the metal circuit layer ⑽ can be used for signal transmission in the chip. ♦ The bumps 160a and 16% are located on the queen line layer 150. •: 60a is a material suitable for the reflow step. Also? The sub-signal that is also output by the electronic component through the convex is transmitted to it = Bujie circuit components (not 纟 ㈣; through the bump 160b, two; ^, # 9 ^ the electronic signal I and the bump secret 5 electrons from the connected external electric wire; "received by 妾 h by external circuit components connected to the bump 16% (1), glass-based: or thin = circuit structure shown) such as a soft board in Figure 1 In the metal circuit layer 15 (H system is formed directly on the protective layer 14o, 1236722 14012twf.doc However, the metal circuit layer 150 may not be formed directly on the protective layer 14o, as shown in FIG. 2, one of which is polymerized. The physical layer 170 is formed on the protective layer 14o, the polymer layer 170 has a plurality of openings 172, and is roughly aligned with the opening 142 of the protective layer 14o, and the metal wiring layer 150 is formed on the polymer layer HO, and Via the opening 172 of the polymer layer 170 and the protective layer] ^ 0, the opening 142 can be connected to the thin film circuit layer 136. The material of the polymer layer 170 is, for example, polyimide (PI), phenylcyclobutadiene ( benzoCyCi〇butene (BCB), polyarylene ether (parylene), porous dielectric material or elastomer, etc.— 2. Metal circuit layer as a reconfiguration layout Please refer to FIG. 3 and FIG. 4, which are schematic cross-sectional views of a first embodiment of a wafer structure according to the present invention. The metal circuit layer 15 is used as a reconfiguration layout, for example. In the wafer structure 100 of FIG. 3 and FIG. 4, the portion below the protective layer 140 is the same as the portion of the wafer structure 100 of FIG. 1 and FIG. 2 below the protective layer 140, and the same portion is here. The main difference lies in the configuration of the metal circuit layer 150, which can be used for reconfiguration layout. Please refer to FIG. 3 and FIG. 4. The protective layer 14 has openings 142a and 142b, exposing the topmost thin film circuit layer. One of the contacts 135a, 135b of 136, the metal circuit layer 150 is located on the protective layer 14o, and is connected to the contacts 135a, 135b of the thin film circuit layer 136. A plurality of bumps 16a, 160b are located on the metal circuit. On the layer 150 and electrically connected to the contacts 135a and 135b of the thin film circuit layer 136 via the metal circuit layer 150 respectively, wherein the layout position of the bump 160a is different from the layout position of the contact 135a of the thin film circuit layer 136, Layout of bump 16b It is the same layout position as the contact point 135b of the thin film circuit layer 136. As mentioned above, the metal circuit layer 150 can be used for reconfiguration layout, that is, the bumps i6〇a and i6〇b can be adjusted by the metal circuit layer 150. Placement, or adjust the pin assignment of the bumps 160a and 160b. It is worth noting that the bumps 160a and 160b are materials that are not suitable for the reflow step. 1236722 14012twf.doc penetrates the bump 160a 160b can connect the wafer structure 100 to an external circuit component (not shown), such as a tape, a glass substrate, or a thin film substrate. In FIG. 3, the metal circuit layer 150 is directly formed on the protective layer 140; however, the metal circuit layer 150 may not be directly formed on the protective layer 140, as shown in FIG. 4, where a polymer layer 170 is formed on On the protective layer MO, the polymer layer 170 has a plurality of openings 172, which are generally aligned with the openings 142 of the protective layer 140. The metal circuit layer 150 is formed on the polymer layer 170 and passes through the openings 172 and 172 of the polymer layer 170. The opening M2 of the protective layer 140 may be connected to the thin film circuit layer 136. The material of the polymer layer 170 is, for example, polyimide (PI), benzocyclobutene (BCB), polyarylene ether (parylene), porous dielectric material, or elastomer. 3. Use of metal circuit layer as power plane Please refer to FIG. 5 and FIG. 6, which are schematic cross-sectional views of a first embodiment of a wafer structure according to the present invention. Metal circuit layer 150 is used as a power plane, for example. In the wafer structure 100 of FIG. 5 and FIG. 6, the portion below the protective layer 14 is the same as the portion of the wafer structure 100 of FIG. 1 and FIG. 2 that is below the protective layer 14. The same portion is not included here. More details. The main difference lies in the configuration of the metal wiring layer 150, which can be used as a power plane. 5 and 6, the protective layer 140 has a plurality of openings 142, and the contacts 135 of the topmost thin film circuit layer 136 are exposed. The metal circuit layer 15 includes a power plane 152, which is electrically connected to the top thin film circuit layer 136 through the opening 142 of the protective layer 140. The thin film power plane 134 is, for example, one of the multilayer thin film circuit layers, and the power The plane 250 is electrically connected to the thin film power plane 134. The bumps 160a and 160b are located on the metal circuit layer 150. The bumps 160a and 160b are not suitable for the re-soldering step. The wafer structure can be connected to an external circuit component through the bumps 160a and 160b ( (Not shown), such as a tape, glass substrate, or film substrate. 1236722 14012twf.doc The bump 160a can be connected to the power plane of the external circuit component; In addition, the chip structure 1GG can transmit electronic signals to the external circuit component connected to the bump through the bump, or can receive the external circuit component connected to the bump_ Electronic signals from connected external circuit components. In FIG. 5, the 'metal circuit layer 150 is formed directly on the protective layer 14o; however, the' metal circuit layer 150 may not be formed directly on the protective layer 14o, as shown in FIG. 6 'where-the polymer layer m is The polymer layer 170 is formed on the protective layer 140. The polymer layer 170 has multiple openings 172 ′, and the opening 142 of the protective layer 14 is substantially aligned. The metal circuit layer 150 is formed on the polymer layer 170 and passes through the polymer layer 170. The opening 172 and the opening 142 of the protective layer 14 may be connected to the thin film circuit layer 136. The material of the polymer layer 170 is, for example, polyimide (PI), phenylcyclobutene (BCB), polyarylene ether (parylene), porous dielectric material, or elasticity.体 等。 Body and so on. 4. Use of the metal circuit layer as a ground plane Please refer to FIG. 7 and FIG. 8, which are schematic cross-sectional views of the first embodiment of the wafer structure according to the present invention. The metal circuit layer 15 is used as a ground plane, for example. In the wafer structure 100 of FIG. 7 and FIG. 8, the protection layer 14 or lower is the same as the portion of the wafer structure 100 of FIG. 1 and FIG. 2 located below the protection layer 140, and the same portion is I will not repeat them here. The main difference lies in the configuration of the metal wiring layer 150, which can be used as a ground plane. Referring to FIG. 7 and FIG. 8, the protective layer 14 has a plurality of openings 142, exposing the contacts 135 of the topmost thin film circuit layer 136. The metal circuit layer 150 includes a ground plane 152, which is electrically connected to the top thin film circuit layer 136 through the opening 142 of the protective layer 140. The thin film ground plane 134 is, for example, one of a plurality of thin film circuit layers, and the ground plane The 250 series is electrically connected to the thin film ground plane 134. The bumps 160a and 160b are located on the metal circuit layer 150. Among them, the bumps 160a and 160b are materials that are not suitable for the reflow step. 11 1236722 14012twf.doc quality. The wafer structure can be connected through the bumps 160a and 160b. To an external circuit component (not shown) 'is, for example, a tape, a glass substrate, or a thin film substrate. The bump 160a can be connected to the ground plane of the external circuit component. In addition, the chip structure 100 can transmit electronic signals to the external circuit component connected to the bump i60b through the bump 160b, or can receive the external circuit component connected to the bump 160b. Electronic signals from connected external circuit components. In FIG. 7, the metal circuit layer 150 is formed directly on the protective layer 14; however, the metal circuit layer 150 may not be formed directly on the protective layer 14 as shown in FIG. 8, and one of the polymer layers 17 Is formed on the protective layer, the polymer layer 170 has a plurality of openings 142 which are substantially aligned with the protective layer 14o_, and the metal circuit layer 150 is formed on the polymer layer 17o, and The opening 172 of the polymer layer 170 and the opening M2 of the protective layer 14 can be connected to the thin film circuit layer 136. The material of the polymer layer 170 is, for example, polyimide (PI), benz CyCiobutene, parylene, porous dielectric material, or elastomer. 5. The metal circuit layer is used for signal transmission lines, planes or ground planes of external circuit components. Refer to FIG. 9 and FIG. 10, which are green cross-sectional diagrams of the first embodiment of the wafer structure according to the present invention. The circuit layer is used for signal transmission lines, power planes, or ground planes of φ components of external circuits. In the wafer structure of Fig. 9 and Fig. 10, the protective layer 14 and below are the same as those in Fig. I and Fig. 2 The part of the structure 100 that is below the protection layer 14 is not repeated here. The main difference is that the configuration of the metal circuit layer ⑼ can be used as a signal transmission line and power plane for external circuit components (not shown). 9 and 10, the metal circuit layer 150 is located on the protective layer, and the metal circuit layer 150 includes a region 152, and the thin film circuit layer 132, 12 1236722 14012twf.doc Between 134 and 136, there is a state of electrical disconnection. The bumps 16 plus, 6%, and i60c are materials that are not suitable for the reflow step. The bumps 16a and 16% are located on the metal circuit layer 160. This area 152. The area 152 of the metal circuit layer 160 can be electrically connected to an external circuit component (not shown) through the bumps 160a, 160b, such as a glass substrate, a thin film substrate, or a tape. In practical applications, this area 152 of the metal circuit layer 150 can be used as a # transmission line for external circuit components. When the metal circuit layer 15 is connected to external circuit components, a signal is suitable for passing through the external circuit components and one of them. The bump (for example, the bump 160a) is transmitted to this area 152 of the metal circuit layer 150, and then transmitted to other circuit components through other bumps (for example, the bump 160b). In addition, in practical applications, the metal circuit layer 150 This area 152 can also be used as the power plane or ground plane for external circuit components. At this time, this area 152 of the metal circuit layer 15 is suitable for connecting to the power or ground terminal of external circuit components. Through the bump 160c, the chip junction 100 can transmit electronic signals to external circuit components connected to the bump 160c, or can receive electronic signals from external circuit components connected to the bump 160c. In Figure 9, the metal circuit The layer 150 is directly formed on the protective layer 14; however, the metal circuit layer 150 may not be directly formed on the protective layer 14: As shown in FIG. 10, a polymer layer 170 is formed on the protective layer 14o. The polymer layer 170 has a plurality of openings 172, which are substantially aligned with the openings 142 of the protective layer 140. The metal circuit layer 150 is formed on the polymer layer 170, and passes through the openings 172 and the protection of the composite layer 170. The opening 142 of the layer 14 may be connected to the thin film circuit layer 136. The material of the polymer layer 170 is, for example, polyimide 'PI, benzocyclobutene (BCB), parylene, porous dielectric material, or elastomer. 2. Second Embodiment of the Wafer Structure In the second embodiment of the wafer structure, the metal circuit layer 250 is located on the protective layer of Bao 13 1236722 14012twf.doc, and the bump 26 (M is located on the top layer of the thin film circuit layer, middle, The parts below the protective layer 140 are the same as those in the drawings and Figure 2 below the protective layer, and will be elaborated here. For the function of the circuit layer, the following are several possible implementation scenarios: 1. Metal Please refer to FIG. 11 to FIG. 23 for the circuit layer for signal transmission in the chip. It is a schematic cross-sectional view of a second embodiment of the wafer structure according to the present invention. The metal circuit layer 25 is used for signal transmission in the chip. The metal circuit layer 25 is located on the protective layer 14 and is electrically connected to the thin film circuit layer 136 through the opening 142 of the protective layer 140. One of the electronic components 112 (for example, the electronic component 112 &) is suitable for ❿ An electronic sfl signal is output. The electronic signal passes through the thin film circuit layers 132 and 134 and passes through the protective layer 140, and then is transmitted to the metal circuit layer 25. Then, it passes through the protective layer 140 and passes through the thin film circuit layer Π6. , 134, 132 are transmitted to at least one of the other electronic components 140 (such as the electronic component U2b). In this way, the metal circuit layer 250 can be used for signal transmission in the chip. The protective layer 140 has an opening 142, exposing the top layer. The contacts 135 of the thin film circuit layer 136, in this embodiment, the bumps 260 suitable for electrical connection with a tape, a glass substrate or a thin film substrate (not shown) are, for example, thin film circuits formed directly on the top layer. On the contact 135 of the layer 136, the bump 260 is made of a material that is not suitable for the collapse and reflow step. In FIG. 11 and FIG. 12, the metal circuit layer 250 is exposed and is directly formed on the protective layer 140. It is worth noting that, in FIG. 11, the thickness of the bump 260. is the same as the thickness of the metal circuit. The thickness of the layer 250 is 4; in FIG. 12, the thickness t of the bump 260 is greater than the thickness of the metal circuit layer 250. The thickness d .. In FIG. 13 and FIG. 14, the metal circuit layer 250 is directly formed on the protective layer 140, and a polymer layer 280 is formed on the metal circuit layer 250 and is not in contact with the convex household 260. It is worth noting that, in FIG. 13, 14 1236722 1401 of the bump 260 2twf.doc The thickness t is the same as the thickness d of the metal circuit layer 250 and is smaller than the combined thickness (d + q) of the metal circuit layer 250 and the polymer layer 280; in FIG. 14, the thickness t of the bump 26θ〇 Is greater than the combined thickness (d + q) of the metal circuit layer 250 and the polymer layer 28. In FIGS. 15, 16 and 17, the polymer layer 270 is located on the protective layer 140 and the polymer layer 270 There are a plurality of openings 272, which are generally aligned with the openings 142 of the protective layer 140. The metal circuit layer 250 is formed on the polymer layer 270, and is connected through the openings 272 of the polymer layer 270 and the openings 142 of the protective layer 140. To thin film circuit layer 136. The bump 260 is directly formed on the contact 135 of the thin film circuit layer 136 on the top layer, and does not contact the polymer layer 27. It is important to note that in FIG. 15, the thickness t of the bump 260 is the same as the thickness d of the metal circuit layer 250 and is less than the total thickness (d + p) of the metal circuit layer 250 and the polymer layer 270. ), The thickness t of the bump 260 in FIG. 16 is substantially the same as the total thickness (d + p) of the metal circuit layer 250 and the polymer layer 270; in FIG. 17, the thickness t of the bump 260 is It is larger than the combined thickness (d + p) of the metal circuit layer 250 and the polymer layer 270. In FIGS. 18 and 19, the polymer layer 270 is located on the protective layer 140. The polymer layer 270 has a plurality of openings 272, which are generally aligned with the openings 142 of the protective layer 140. The metal circuit layer 250 is formed on The polymer layer 270 is connected to the thin film circuit layer 136 in parallel and through the opening 272 of the polymer layer 270 and the opening 142 of the protective layer 140. The polymer layer 280 is located on the metal circuit layer 250. The bump 160 is directly formed on the contact 135 of the thin film circuit layer 136 on the top layer, and does not contact the polymer layers 270 and 280. It is worth noting that in FIG. 18, the thickness t of the bump 260 is the same as the thickness d of the metal circuit layer 250, and is smaller than the total thickness (d + P +) of the metal circuit layer 250 and the polymer layers 270 and 280. q); In FIG. 19, the thickness t # of the bump 260 is greater than the combined thickness (d + p + q) of the metal circuit layer 250 and the polymer layers 270 and 280. 15 1236722 14012twf.doc In Figure 20 and Figure 21, the polymer layer 270 is located on the protective layer 14o. The polymer layer 270 has a plurality of openings 272, which are generally aligned with the openings 142 of the protective layer 14o. The metal circuit layer 250 is formed on the polymer layer 270 and is connected to the thin film circuit layer 136 through the opening 272 and the protective layer 1101 opening 142 of the polymer layer 270. The bump 260 is directly formed on the contact 135 of the top thin film circuit layer 136, and a part of the bump 260 is located in the opening 272 of the polymer layer 270. The bump 260 has an upper layer portion 262, Located outside the opening 272 of the polymer layer 270. It should be noted that, in FIG. 20, the thickness tu of the upper layer portion 262 of the bump 260 is the same as the thickness d of the metal circuit layer 25. In FIG. 21, the thickness tu of the upper portion 262 of the bump 260 is greater than The thickness d of the metal wiring layer 250. In FIGS. 22 and 23, the polymer layer 270 is located on the protective layer 14o. The polymer layer 270 has a plurality of openings 272, which are generally aligned with the openings 142 of the protective layer 14o, and the metal circuit layer 250 is formed. The polymer layer 270 is connected to the thin film circuit layer 136 through the opening 272 of the polymer layer 270 and the opening 142 of the protective layer 14. The polymer layer 280 is located on the metal circuit layer 250. The bumps 260 are formed directly on the contacts 135 of the thin film circuit layer ι36 on the top layer, and a part of the bumps 260 are located in the openings 272 of the polymer layer 270. The bumps 260 have an upper layer portion 262, located at The polymer layer 270 is outside the opening 272. It is worth noting that in FIG. 22, the thickness tu of the upper layer portion 262 of the bump 260 is the same as the thickness d of the metal circuit layer 250 and smaller than the total thickness (d +) of the metal circuit layer 250 and the polymer layer 280. q); In FIG. 23, the thickness tu of the upper layer portion 262 of the bump 260 is greater than the combined thickness (d + q) of the metal circuit layer 250 and the polymer layer 280. In the above-mentioned embodiments of FIGS. 13 to 23, the materials of the polymer layers 270 and 280 are, for example, polyimide (PI), benzocyclobutene (BCB), and polyarylene ether (paryiene). ), Porous 1236722 14012twf.doc dielectric materials or elastomers. 2. Use of the metal circuit layer as a power plane Referring to FIGS. 24 to 36, there are shown schematic cross-sectional views of the first embodiment of the wafer structure according to the present invention, in which the metal circuit layer 250 is used as a power plane, for example. The protective layer 140 has a plurality of openings H2, and the topmost thin film circuit layer 136 is exposed. The power plane 250 is electrically connected to the top thin film circuit layer 136 through the opening 142 of the protective layer 140. The thin film power plane 134 is, for example, located in multiple layers. One of the thin film circuit layers, and the power plane 250 is connected to the thin film power plane 134. The opening 142 of the protective layer 140 also exposes the contact point 135 of the top thin film circuit layer 136. The bump 26o is located on the contact 135 of the thin film circuit layer 136 of the ^ φ layer, of which the bump 260 is not suitable for The material of the re-soldering step can be electrically connected to external circuit components through the bump 260, such as a tape, a glass substrate, or a thin film substrate. In Figs. 24 and 25, the power plane 250 is exposed to the outside and is directly formed on the protective layer 14o. It should be noted that, in FIG. 24, the thickness t of the bump 26 0 is the same as the thickness d of the power plane 250; in FIG. 25, the thickness t of the bump 260 is greater than the thickness d of the power plane 250. In Figs. 26 and 27, the power plane 250 is directly formed on the protective layer 140, and a polymer layer 28o is formed on the power plane 250 and does not contact the bump 260. It is worth noting that, in FIG. 26, the thickness t of the bump 26 is the same as the thickness d of the power plane 250 and is smaller than the combined thickness (d + q) of the power plane 250 and the polymer layer 280; In 27, the thickness t of the bump 260 is greater than the combined thickness (d + q) of the power plane 250 and the polymer layer 280. In FIG. 28, FIG. 29, and FIG. 30, the polymer layer 270 is located on the protective layer 140. The polymer layer 270 has a plurality of openings 272, which are generally aligned with the openings 142 of the protective layer 140, and the power plane 250 is It is formed on the polymer layer 270 and is connected to the thin film circuit layer 136 through the opening 272 of the polymer layer 270 and the opening 142 17 1236722 14012twf.doc of the protective layer HO. The bumps 260 are directly formed on the contacts 135 of the thin film circuit layer 136 on the top layer and do not contact the polymer layer 27. It is worth noting that 'in FIG. 28, the thickness t of the bump 260 is the same as the thickness d of the power plane 250, and is less than the combined thickness (d + p) of the power plane 250 and the polymer layer 27. In FIG. 29, the thickness t of the bump 260 is substantially the same as the total thickness (d + p) of the power plane 250 and the polymer layer 270; in FIG. 30, the thickness t of the bump 260 is greater than the power plane 250 Total thickness (d + p) with the polymer layer 270. In FIGS. 31 and 32, the polymer layer 270 is located on the protective layer 140. The polymer layer 270 has a plurality of openings 272, which are roughly aligned with the openings 142 of the protective layer. The power plane 250 is formed on The polymer layer 270 is connected to the thin film circuit layer 136 through the opening 272 of the polymer layer 270 and the opening 142 of the protective layer 14. The polymer layer 280 is located on the power plane 25. The bump 160 is directly formed. It is on the top contact point 135 of the thin film circuit layer 136 and does not contact the polymer layers 270 and 280. It is worth noting that in FIG. 31, the thickness t of the bump 260 is the same as the thickness d of the power plane 250 And less than the combined thickness (d + p + q) of the power plane 250 and the polymer layers 270, 280; in FIG. 32, the thickness t of the bump 260 is greater than the power plane 25 and the polymer layers 270, 280 The total thickness (d + p + q) is added. In FIGS. 33 and 34, the polymer layer 270 is located on the protective layer 14 and the polymer layer 270 has a plurality of openings 272, which are generally aligned and protected. The opening 142 of the layer 14 and the power plane 250 are formed on the polymer layer 270 and pass through the opening 272 of the polymer layer 270. And the opening 142 of the protective layer 140 is connected to the thin film circuit layer 136. The bump 260 is directly formed on the contact 135 of the top thin film circuit layer 136, and a part of the bump 260 is located at the opening of the polymer layer 270 In 272, the bump 260 has an upper layer portion 262, which is located outside the opening 272 of the polymer layer 270. It is worth noting that in FIG. 33, the thickness tu of the upper layer portion 262 of the 1236722 bump 260 is the same as the power plane 250 In FIG. 34, the thickness tu of the upper layer portion 262 of the bump 260 is greater than the thickness d of the power plane 250. In FIGS. 35 and 36, the polymer layer 270 is located on the protective layer 140, and the polymer The layer 270 has a plurality of openings 272, which are generally aligned with the openings 142 of the protective layer 14. The power plane 250 is formed on the polymer layer 270, and is connected through the openings 272 of the polymer layer 270 and the openings 142 of the protective layer 140. To the thin film circuit layer 136, the polymer layer 280 is located on the power plane 250. The bumps 260 are directly formed on the top thin film circuit layer 36 at the contacts 135, and a part of the bumps 260 are located in the polymer In the opening 272 of the material layer 270, the bump 260 is An upper layer portion 262 is located outside the opening 272 of the polymer layer 270. It is worth noting that, in FIG. 35, the thickness tu of the upper layer portion 262 of the bump 260 is the same as the thickness d of the power plane 250 and smaller than the power plane 250. The combined thickness (d + q) of 250 and the polymer layer 280; in FIG. 36, the thickness tu of the upper layer portion 262 of the bump 26o is greater than the combined thickness (d) of the power plane 250 and the polymer layer 280 + q). In the above-mentioned embodiments of FIGS. 26 to 36, the materials of the polymer layers 27 and 28 are, for example, polyimide (Pomlyide) and phenylcyclobutene (Bentrocycline, BCB). , Polyarylene ether (parylene), porous dielectric material or elastomer. 3. Use of metal circuit layer as ground plane Please refer to Fig. 37 to Fig. 49. The cross-sectional schematic diagrams of the second embodiment are used for the plane. The protective layer 140 has a plurality of openings 142,

9 'which shows the first of the wafer structures according to the present invention in which the metal circuit layer 250 is used as the ground through the opening 142 of the protective layer 140. The thin film ground plane 134 is one layer, and the ground plane 250 is 19 1236722 14012twf.doc, which is sexually connected to the film. Ground plane 134. The opening 142 of the protective layer 140 also exposes the contacts 135 of the top thin film circuit layer 136. The bumps 260 are located on the contacts 135 of the top thin film circuit layer 136. The bumps 260 are not suitable for the reflow step. In this way, the bumps 260 can be electrically connected to an external circuit component, such as a tape, a glass substrate, or a thin film substrate. In FIGS. 37 and 38, the ground plane 250 is exposed to the outside and is directly formed on the protective layer 140. It is worth noting that in FIG. 37, the thickness t of the bump 260 is the same as the thickness d of the ground plane 250; in FIG. 38, the thickness t of the bump 260 is greater than the thickness d of the ground plane 250. In Figs. 39 and 40, the ground plane 250 is directly formed on the protective layer 140, and a polymer layer 28o is formed on the ground plane 25o without contacting the bumps 260. It is worth noting that in FIG. 39, the thickness t of the bump 260 is the same as the thickness d of the ground plane 250, and is less than the combined thickness (d + q) of the ground plane 250 and the polymer layer 280; Here, the thickness t of the bump 260 is greater than the combined thickness (d + q) of the ground plane 250 and the polymer layer 280. In FIGS. 41, 42 and 43, the polymer layer 270 is located on the protective layer H0. The polymer layer 270 has a plurality of openings 272, which are generally aligned with the openings 142 of the protective layer 140, and the ground plane 250 is formed. The polymer layer 270 is connected to the thin film circuit layer 136 through the opening 272 of the polymer layer 270 and the opening 142 of the protective layer 140. The bumps 260 are formed directly on the contacts 135 of the thin film circuit layer 136 on the top layer and do not contact the polymer layer 270. It is worth noting that in FIG. 41, the thickness t of the bump 260 is the same as the thickness d of the ground plane 250, and is less than the combined thickness (d + p) of the ground plane 250 and the polymer layer 270; In FIG. 43, the thickness t of the bump 260 is substantially the same as the total thickness (d + p) of the ground plane 250 and the polymer layer 270. In FIG. 43, the thickness t of the bump 260 is greater than the thickness of the ground plane 250 and the polymer layer 270. The total thickness (d + p) of the object layer 270. 20 1236722 14012twf.doc In Figures 44 and 45, the polymer layer 270 is located on the protective layer 140. The polymer layer 270 has a plurality of openings 272, which are generally aligned with the openings 142 of the protective layer 140, and the ground plane 250. The polymer layer 270 is formed on the polymer layer 270 and is connected to the thin film circuit layer 136 through the opening 272 of the polymer layer 270 and the opening 142 of the protective layer 140. The polymer layer 280 is located on the ground plane 250. The bump 160 is directly formed on the contact 135 of the thin film circuit layer 136 on the top layer and does not contact the polymer layers 270 and 280. It is worth noting that in FIG. 44, the thickness t of the bump 260 is the same as the thickness d of the ground plane 250 and is smaller than the total thickness (d + p + q) of the ground plane 250 and the polymer layers 270 and 280. In FIG. 45, the thickness t of the bump 260 is greater than the combined thickness (d + p + q) of the ground plane 250 and the polymer layers 270, 280. In FIGS. 46 and 47, the polymer layer 270 is located on the protective layer 140. The polymer layer 270 has a plurality of openings 272, which are generally aligned with the openings 142 of the protective layer 140. The ground plane 250 is formed on the polymer. On the layer 270 and connected to the thin film circuit layer 136 through the opening 272 of the polymer layer 270 and the opening 142 of the protective layer 140. The bump 260 is directly formed on the contact 135 of the thin film circuit layer 136 on the top layer, and a part of the bump 260 is located in the opening 272 of the polymer layer 270. The bump 260 has an upper layer portion 262, which is located at The polymer layer 270 is outside the opening 272. It is worth noting that in FIG. 46, the thickness tu of the upper layer portion 262 of the bump 260 is the same as the thickness d of the ground plane 250; in FIG. 47, the thickness tu of the upper layer portion 262 of the bump 260 is greater than the ground plane 250. The thickness d. In FIGS. 48 and 49, the polymer layer 270 is located on the protective layer 140. The polymer layer 270 has a plurality of openings 272, which are generally aligned with the openings 142 of the protective layer 140. The ground plane 250 is formed on the polymer. The layer 270 is connected to the thin film circuit layer 136 through the opening 272 of the polymer layer 270 and the opening 142 of the protective layer 140. The polymer layer 280 is located on the ground plane 250. 21 1236722 14012twf.doc The bump 260 is directly formed on the contact 135 of the thin film circuit layer ι36 on the top layer, and a part of the bump 260 is located in the opening 272 of the polymer layer 27. The bump 260 has An upper layer portion 262 is located outside the opening 272 of the polymer layer 27. It is worth noting that in FIG. 48, the thickness tu of the upper layer portion 262 of the bump 260 is the same as the thickness d of the ground plane 250, and is smaller than the combined thickness (d + q) of the ground plane 250 and the polymer layer 280. In FIG. 49, the thickness of the upper layer portion 262 of the bump 260 is greater than the combined thickness (d + q) of the ground plane 25 and the polymer layer 28. In the embodiments shown in FIG. 39 to FIG. 49, the materials of the polymer layers 270 and 280 are, for example, polyimide (poliminide, p), benzocyclobutene (BCB), and polyarylene. Ether (paryiene), porous dielectric material, or elastomer. 4. The metal circuit layer is used as a signal transmission line, power plane or ground plane. Among them, the metal circuit layer is connected to the bump 1 by using the thin film circuit layer on the top layer. Referring to FIGS. 50 to 62, it shows a wafer structure according to the present invention. First, the cross-sectional schematic diagram of the embodiment, wherein the metal circuit layer 25 is a top layer, the circuit layer 136 is connected to the bump 260, and the metal circuit layer 250 is used as an I tiger transmission line, a power plane, or a ground plane, for example. The metal circuit layer 25 is located on the protective layer 14 and is electrically connected to the thin film circuit layer 136 through the opening 1C of the protective layer 14. In addition, a bump 260 suitable for connection with a tape, a glass substrate, or an f-film substrate (not shown) is, for example, directly formed on the top two: the contact point 135 of the film line layer 136, where the projection The block 260 is a material that is not suitable for the soldering step, and the bump 260 can be electrically connected to the metal circuit layer 25 through a thin film line of the top layer = 136. In a better case, between the bump ^ 60 and the metal circuit layer 25G The shortest distance s is, for example;% is between 1 micro H micron. When the metal circuit layer 250 is used as one of the signal transmission, Japanese, and electronic components 112 (such as the electronic component U2a) 22 1236722 14012twf.doc, the electronic signal can pass through the thin film circuit layers 132, 134, 136 and pass through the protection After the layer 140, it is transmitted to the metal circuit layer 250, then passes through the protective layer 140, and is transmitted to the bump 260 through the thin film circuit layer 136. Alternatively, the electronic signal received by the bump 260 may be transmitted through the protective layer ho to the thin film circuit layer 136, then transmitted through the protective layer 140 to the metal circuit layer 250, and then through the protective layer 140 and through the thin film. The circuit layers 136, 134, and 132 are transmitted to at least one of the electronic components 112 (for example, the electronic component 112a). When the metal circuit layer 250 is used as a power plane, the metal circuit layer 250 may be connected to a power terminal of a tape, a film substrate, or a glass substrate via a thin film circuit layer 136 and a bump 260 on the top layer. When the metal circuit layer 250 is used as a ground plane, for example, the metal circuit layer 250 may be connected to a ground terminal of a tape, a thin film substrate, or a glass substrate via the thin film circuit layer 136 and the bump 260 on the top layer. In FIG. 50 and FIG. 51, the metal wiring layer 250 is exposed to the outside and is directly formed on the protective layer 140. It should be noted that in FIG. 50, the thickness t of the bump 260 is the same as the thickness d of the metal wiring layer 250; in FIG. 51, the thickness t of the bump 260 is greater than the thickness d of the metal wiring layer 250. In FIGS. 52 and 53, the metal circuit layer 250 is directly formed on the protective layer 140, and a polymer layer 280 is formed on the metal circuit layer 250 without contacting the bumps 260. It is worth noting that in FIG. 52, the thickness t of the bump 260 is the same as the thickness d of the metal circuit layer 250, and is less than the combined thickness (d + q) of the metal circuit layer 250 and the polymer layer 280; In FIG. 53, the thickness t of the bump 260 is greater than the combined thickness (d + q) of the metal circuit layer 250 and the polymer layer 280. In FIG. 54, FIG. 55, and FIG. 56, the polymer layer 270 is located on the protective layer 140. The polymer layer 270 has a plurality of openings 272, which are generally aligned with the openings 142 of the protective layer 140. The metal circuit layer 250 is It is formed on the polymer layer 27023 1236722 14012twf.doc and is connected to the thin film circuit layer 136 through the opening 272 of the polymer layer 270 and the opening 142 of the protective layer 140. The bumps 260 are formed directly on the contacts 135 of the thin film circuit layer 136 on the top layer, and do not contact the polymer layer 270. It is worth noting that in FIG. 54, the thickness t of the bump 260 is the same as the thickness d of the metal circuit layer 250 and is smaller than the combined thickness (d + p) of the metal circuit layer 250 and the polymer layer 270; In FIG. 55, the thickness t of the bump 260 is substantially the same as the total thickness (d + p) of the metal circuit layer 250 and the polymer layer 270; in FIG. 56, the thickness t of the bump 260 is larger than the metal circuit. The combined thickness (d + p) of layer 250 and polymer layer 270. In FIGS. 57 and 58, the polymer layer 270 is located on the protective layer 140. The polymer layer 270 has a plurality of openings 272, which are generally aligned with the openings 142 of the protective layer 14. The metal circuit layer 250 is formed on the protective layer 140. The polymer layer 270 is connected to the thin film circuit layer 136 through the opening 272 of the polymer layer 270 and the opening 142 of the protective layer 14. The polymer layer 280 is located on the metal circuit layer. The bumps 160 are directly formed on the contacts of the thin film circuit layer on the top layer, and do not contact the polymer layers 270, 280. It is worth noting that in FIG. 57, the thickness t of the bump 260 is the same as the thickness d of the metal circuit layer 25 and is smaller than the total thickness (d + p) of the metal circuit layer 250 and the polymer layers 270 and 280. + q). In FIG. 58, the thickness t of the bump 260 is larger than the combined thickness (d + p + q) of the metal circuit layer 25 and the polymer layers 270 and 280. In FIGS. 59 and 60, the polymer layer 270 is located on the protective layer 140. The polymer layer 270 has a plurality of openings 272, which are roughly aligned with the openings 142 of the protective layer ι40. The metal circuit layer 250 is formed. The polymer layer 270 is connected to the thin film circuit layer 136 through the opening 272 of the polymer layer 270 and the opening 142 of the protective layer 14. The bump 260 is formed directly on the contact 135 of the thin film circuit layer 136 on the top layer, and a part of the bump 260 is located in the opening 272 of the polymer layer 270. The bump 260 has an upper layer portion 262, 24 1236722 14012twf.doc is located outside the opening 272 of the polymer layer 270. It is worth noting that in FIG. 59, the thickness tu of the upper layer portion 262 of the bump 260 is the same as the thickness d of the metal circuit layer 250; in FIG. 60, the thickness tu of the upper portion 262 of the bump 260 is larger than the metal circuit. The thickness d of the layer 250. In FIGS. 61 and 62, the polymer layer 270 is located on the protective layer 140. The polymer layer 270 has a plurality of openings 272, which are generally aligned with the openings 142 of the protective layer “0”, and the metal circuit layer 250 is formed. The polymer layer 270 is connected to the thin film circuit layer 136 through the opening 272 of the polymer layer 270 and the opening 142 of the protective layer 140, and the polymer layer 280 is located on the metal circuit layer 25. The bump 260 is directly formed On top of the contact 135 of the thin film circuit layer 136, a part of the bump 260 is located in the opening 272 of the polymer layer 270. The bump 260 has an upper portion 262, which is located on the polymer layer 27. Outside the opening 272. It is worth noting that in FIG. 61, the thickness tu of the upper layer portion 262 of the bump 26o is the same as the thickness d of the metal circuit layer 25o, and is smaller than the metal circuit layer 250 and the polymer layer 28. The added thickness (d + q); in the illustration, the thickness tu of the upper layer portion 262 of the bump 260 is larger than the combined thickness (d + q) of the metal circuit layer and the polymer layer 280. In the above embodiments of FIGS. 52 to 62, the polymer layers 27 and 28 are made of polyimide, for example, polyimide. (P〇lyimide, ρι), benzocyclobutene (BCB), Zhan, Qiu dielectric materials or elastomers, such as parylene, porous 5. Metal circuit layer as external circuit components + plane or Please refer to Figure 63 to Figure 68 for the ground plane's transmission line and power supply. 'It is shown in accordance with the schematic cross-section diagrams, in which the metal circuit layer; such as = = 2 Si signal transmission line, power plane Or for grounding. The metal circuit layer 25G is located on the protective layer 且, and it is in an electrically disconnected state with the film 25 1236722 14012twf.doc. 'Metal circuit layer film USP circuit circuit components, pumping glass Base plate, thin 222, 3 board sound, etc. In practical applications, the metal circuit layer 250 can form a signal transmission line of Jit. When the metal circuit layer 250 and == tr :, the tank can be transmitted via external circuit components ,, 9th, then pass the part from the other end of the metal circuit layer 250. In addition, in practical applications, the metal circuit layer] is the power plane of the external circuit component, at this time the metal circuit layer 250 is the power terminal of the external circuit component. , The metal circuit layer 250… takes 彳 as the ground plane of the external circuit components. At this time, the metal circuit layer 205 is the ground terminal of the external circuit components. The block 26 is directly formed on the contact of the thin film circuit layer w on the top layer. The bump 260 is a material that is not suitable for the resuming step. The wafer structure 200 can be electrically connected to the outer #circuit component through the bump, such as It is a flexible board (taPe), a glass substrate, or a thin film substrate. In FIG. 63, the metal circuit layer 250 is exposed to the outside and is directly formed on the thickening layer M0, and the bump 260 is directly formed on the contact 135 of the thin film circuit layer 136 on the top layer, in which the bump 26o The thickness t is the same as the thickness d of the metal and wiring layer 25. In FIG. 64, a polymer layer 270 is located on the protective layer 140, and a metal wiring layer 250 is formed on the polymer layer 270. The bump 26o is a contact 135i of the thin film circuit layer 136 formed directly on the top layer, and does not contact the polymer layer 270. The thickness of the bump 26o is substantially the same as that of the metal circuit layer 250 and the polymer. The total thickness (d + ρ) added by layer 270. In FIG. 65, the polymer layer 270 is located on the protective layer 140, and the metal circuit layer 250 is formed on the polymer layer 270. The polymer layer 270 has an opening 26 1236722 14012twf.doc 272, which is generally aligned with the protective layer. 140 的 口 142。 140 openings 142. The bump 260 is directly formed on the contact 135 of the thin film circuit layer 136 on the top layer, and a part of the bump 260 is located in the opening 272 of the polymer layer 270. The bump 260 has an upper layer portion 262, which is located at The polymer layer 270 is outside the opening 272. Wherein, the thickness tu of the upper layer portion 262 of the bump 260 is the same as the thickness d of the metal circuit layer 250. In FIG. 66, the metal circuit layer 250 is exposed to the outside and is directly formed on the protective layer 140. The bump 265 is The metal circuit layer 250 is formed on the metal circuit layer 250. The metal circuit layer 250 can be electrically connected to an external connection member through the bump 265, such as a tape, a glass substrate, or a thin film substrate. The material of the bump 265 can also be Material not suitable for reflow step. The bumps 260 are directly formed on the contacts 135 of the thin film circuit layer 136 on the top layer, and the thickness t of the bumps 26 is substantially the same as the total thickness of the metal circuit layer 25 and the bumps 265 (d + b). In FIG. 67, the polymer layer 270 is located on the protective layer 14o, the metal circuit layer 250 is formed on the polymer layer 27o, and the bump 265 is formed on the metal circuit layer 250. The metal circuit layer 250 penetrates the protrusions. The block 265 may be electrically connected to an external connection member, such as a tape, a glass substrate, or a thin film substrate. The material of the bump 265 may also be a material that is not suitable for the re-soldering step. The bump 260 is formed directly on the contact 135 of the thin film circuit layer 136 on the top layer and does not contact the polymer layer 270. Among them, the thickness t of the bump 260 is substantially the same as the total thickness (b + d + p) of the bump 265, the metal circuit layer 250, and the polymer layer 270. In FIG. 68, the polymer layer 270 is located on the protective layer 140, the metal circuit layer 250 is formed on the polymer layer 270, the bump 265 is formed on the metal circuit layer 250, and the metal circuit layer 250 penetrates the bump 265 It can be electrically connected to external connection members, such as tape, glass substrate or film substrate, etc. 27 1236722 14012twf.doc The material of the bump 265 can also be a material that is not suitable for the re-soldering step. The polymer layer 270 has an opening 272, which is generally aligned with the opening 142 of the protective layer 140. The bump 260 is directly formed on the contact 135 of the thin film circuit layer 136 on the top layer, and a part of the bump 260 is located at In the opening 272 of the polymer layer 270, the bump 260 has an upper portion 262, which is located outside the opening 272 of the polymer layer 270. Among them, the thickness tu of the upper layer portion 262 of the bump 260 is, for example, substantially the same as the total thickness (b + d) of the bump 265 and the metal circuit layer 250. In FIG. 64, FIG. 65, FIG. 67, and FIG. 68 described above, In the embodiment, the materials of the polymer layers 270 and 280 are, for example, polyimide (pioyimide), benzocyclobutene (BCB), polyarylene ether (paiylene), porous media Electrical material or elastomer. 3. Size and material of the metal circuit layer The metal circuit layers 15 and 25 of the first and second embodiments are formed by depositing an adhesion / barrier layer and at least one metal layer. The detailed structure is As described below. 1. First Structure of Metal Circuit Layer Please refer to FIG. 69, which is a schematic cross-sectional view showing the first structure of the metal circuit layer according to the first embodiment and the second embodiment of the present invention. The aforementioned metal circuit layers 150 and 250 include, for example, an adhesion / barrier layer 311 and a metal layer 312. The adhesion / barrier layer 311 is, for example, formed directly on the aforementioned protective layer 14 or the polymer layers Π0 and 27. 'The metal layer 312 is located on the adhesive / barrier layer buckle, and the material of the adhesive / barrier layer 311 is, for example, titanium crane alloy, titanium nitrogen compound, group or group nitrogen compound, and the material f of the metal layer 312 is It is gold. In a preferred case, the thickness of the metal layer 312 is, for example, greater than 1 μm. 2. The second structure of the metal circuit layer Please refer to FIG. 7G, which is a cross-sectional view of the second structure of the metal circuit shape according to the first embodiment and the second embodiment of the present invention. 28 1236722 14012twf.doc The secret road layers 150, 250 include, for example, an adhesion / barrier layer 321 and ",14;-wherein the material of the adhesion / barrier layer 321 is, for example, titanium or a compound, or the adhesion / barrier layer 321 It can also be formed by sequentially depositing a chromium layer and an alloy layer, the material of which is chrome copper alloy = production " I is, for example, copper, in a better case; in the case, 'the degree a2 of the metal layer 322 is greater than丨 microns. 3. Third structure of metal circuit layer Please refer to FIG. 71, which is a schematic cross-sectional view showing a third structure of the first metal circuit layer according to the present invention. The aforementioned 50 and 250, for example, include an adhesion / barrier layer% full sound 332, 333, and the adhesion / barrier layer 331, such as the second metal layer polyimide layer 17 °, 270, where adhesion / barrier == titanium Titanium-tungsten alloy, titanium-nitrogen compound, button or button-nitrogen compound, etc. The early layer 331 can also be formed by sequentially depositing a chromium layer and a chromium-copper alloy. The chromium-copper alloy layer is located on the chromium layer. The metal layer 332 is located on the barrier layer 331. In the case of the material ratio of the 'metal layer 332, the thickness of the metal layer 332 * a3 is, for example, greater than i micrometer. Gold = is located on the metal layer 332, in which the material of the metal layer 333 is, for example, the third structure of the metal circuit layer, please refer to FIG. 72, which shows the fourth example of the circuit layer according to the first example of the present invention. A schematic cross-sectional view of this structure. The aforementioned road layers 150 and 250 include, for example, an adhesive / barrier layer 341 and three layers of 342, 343, and 344. The adhesive / barrier layer 341 is formed directly on the front layer ^ 29 1236722 14012twf.doc or the polymer On the layers 170 and 270, the material of the adhesion / barrier layer 341 is, for example, titanium, titanium tungsten alloy, titanium nitrogen compound, surface or group nitrogen compound, etc., or the adhesion / barrier layer 341 can also be sequentially deposited by chromium Layer and ^ copper alloy layer, wherein the chrome copper alloy layer is located on the chromium layer. The metal layer 342 is located on the adhesion / barrier layer 341. The material of the metal layer 342 is, for example, copper. In a preferred case, the thickness of the metal layer 342 is, for example, greater than 1 μm. The metal layer 343 is located on the metal layer 342, and the material of the metal layer 343 is, for example, nickel. The metal layer 344 is located on the metal layer 343, and the material of the metal layer 3 is, for example, gold. 14. The size of the bumps. In FIGS. 1 to 10, the bumps 16 of the first embodiment are formed by depositing a single-layer metal layer, for example, the material f of the metal layer is It is gold, and the thickness t of the metal layer forming the bump 160 is, for example, greater than 5 microns. In FIGS. 11 to 68, the bump 26 of the second embodiment includes, for example, an adhesion / barrier layer 411 and a metal layer 412. As shown in FIG. 73, the edge of the bump 26 according to the second embodiment of the present invention Schematic cross-section of the block. The adhesion / barrier layer 4ΐι ratio is as follows: ^ is located on the top riding layer, the metallization is located at the adhesion / ^ early, 411 soil ’, and the material of the adhesion / barrier layer 411 is, for example, titanium crane.

The material of the metal layer 412 is better than that of Lit, Nitrogen, or Nitrogen Compound, etc. In a better case, the thickness of the metal layer 412 is greater than that shown in FIG. 66 to FIG. 68, and is formed on the metal line% f ^ 5th day The thickness b of the block 265 is, for example, greater than 5 microns. Mutual-, Ben-Mao tomorrow ’s construction of the soap seed seal 30 1236722 14012twf.doc Electrical connection of the board 'is commonly known as tape automated bonding (TAB) packaging technology, in which the inner pin is bonded to a gold bump The most commonly used is Gold-to-Gold eutectic bonding or Gold-to-Tin solder bonding, that is, a gold or tin layer is first plated on the inner pins. The gold or tin layer on the inner pin of the clock can be bonded to the gold bump on the driver chip; alternatively, the chip structure can be made of anisotropic conductive paste (ACP) or Anisotropic conductive film (ACF) is bonded to the glass substrate and is electrically connected to the glass substrate. Generally, it is a packaging technology called chip on giass (COG); or ' The gold bumps of the wafer structure can be joined by gold-gold (Goll-to-Goll) eutectic bonding or gold-tin (0〇1 (1-1; 〇-1 ^ 11) solder joint). Method, which is electrically connected to a thin film substrate, which is generally called a chip on film (COF) packaging technology. The structure of the wafer structure of the first and second embodiments applied to the above-mentioned packaging technology will be explained more clearly with the illustration. 1. The wafer structures of the first and second embodiments are applied to flexible board automatic bonding ( For the configuration of TAB), please refer to FIG. 74 and FIG. 75, which show the cross-sectional schematic diagrams of the first embodiment and the second embodiment, respectively, where the wafer structure is applied to the automatic bonding of the flexible board. In the first embodiment and the second embodiment, In the wafer structure of the embodiment, the arrangement of the metal circuit layers 150 and 250 and the bumps 160 and 260 are as described above, and will not be described again here. What about the wafers of the first and second embodiments described above? The structure can be applied to the structure of the automatic bonding and packaging technology of the flexible board. The flexible board has a polymer layer 512, an adhesive layer 514, a solder mask layer 516, and a plurality of connection lines 52. The connection line 520 is adhered by adhesion. The layer 514 is attached to the polymer layer 512, and the solder mask layer 516 covers the connection line 52. The material of the polymer layer 512 is, for example, polyurethane. The flexible board 51 has an opening 502 for connection. The inside of the line 520 extends into the opening 502, The inner pin 522 is formed. The aforementioned wafer 31 1236722 14012twf.doc structure 100, 200 is aligned with the opening 502 of the flexible board 510, and is connected to the inner pin 522 of the flexible board 510 through the bumps 160, 260. The protection of the polymer The body 530 covers the inner pins 522 and the bumps 160 and 260 to protect the electrical connection between the wafer structure 100 and 2000 and the flexible board 510. 2. The wafer structure of the first embodiment and the second embodiment is applied to the bonding of a glass substrate (COG). Please refer to FIG. 76 and FIG. 77, which show the first and second embodiments, respectively. The cross-section of the structure applied to the structure of bonding the glass substrate is schematically shown. In the wafer structures 100 and 2000 of the first embodiment and the second embodiment, the configuration of the metal circuit layers 150 and 250 and the bumps 160 and 260 are as described above, and will not be repeated here. The wafer structures 100 and 200 of any of the foregoing first and second embodiments can be applied to a structure for bonding a glass substrate 600. Anisotropic conductive adhesive (ACP) or anisotropic conductive film 610 (ACF> ^ is located between the wafer structure 100, 200 and the glass substrate 600, and the bumps 160, 260 are transparent to the household. ACP) or one of the metal particles 612 in the anisotropic conductive film 61 (ACF) is electrically connected to the circuit layer 602 of the glass substrate 600. 3. The wafer structure of the first and second embodiments is applied to a bonding film substrate (COF) structure, Please refer to FIG. 78 and FIG. 79, which are schematic cross-sectional views showing the structure of the wafer structure of the first embodiment and the second Shilu embodiment applied to a bonding film substrate, respectively. In the wafer structures of one embodiment and the second embodiment, the arrangement of the metal circuit layers 15 (), 250 and the bumps 160, 260 are as described above, and will not be repeated here. Any of the foregoing first embodiments and Both the wafer structures 100 and 2000 of the second embodiment can be applied to a structure for bonding a thin film substrate 700. The thin film substrate 700 includes a polymer layer 710, a circuit layer 720, a solder mask layer 730, and a circuit layer 720. It is located on the polymer layer 710, and the solder mask layer 73 covers the circuit layer 720, in which the polymer layer 710 The material is, for example, polyurethane 32 1236722 14012twf.doc amine. It is known that the cap layer 730 has a plurality of openings 732, exposing the circuit layer 720, and the bumps 160 and 260 located on the wafer structures 100 and 200 can pass through the solder cap layer 730. The opening 732 is connected to the wiring layer 720. The method for connecting the bumps 160 and 260 to the wiring layer 720 is, for example, the use of a gold-to-gold eutectic bonding method or a gold-to-tin solder bonding In this way, a gold layer or a tin layer is first plated on the circuit layer 72o, and the gold layer or tin layer plated on the circuit layer 72o can be bonded to the gold layers of the bumps 160 and 260. In conclusion, in the wafer structure of the present invention, the bump material is technically unsuitable for the reflow step. Since the metal circuit layer can be formed on the layer of the semiconductor wafer, it is used for signal transmission. Use, or can be used as a power plane or ground plane, so the empty application on the protective layer is efficient. Although the present invention has been disclosed as above with a preferred embodiment, bran is not used in two = = away from the present invention _ When attached to the application Therefore, the scope of protection of the present invention is as follows [illustration of the diagram]-Mapping === Road: Actual = 2 33 1236722 14012twf.doc For the use of line, power plane or ground plane. Figures 11 to ^ 3 Sectional schematic diagram of the second embodiment of the wafer structure of the invention. The Chinese metal circuit layer is used as the signal transmission wheel in the wafer: Figure 24 to, = 6 shows a schematic sectional diagram of the second embodiment of the wafer structure according to the invention. The line layer is used as a power plane. 37 to 37 are schematic cross-sectional views showing a second embodiment of a wafer structure according to the present invention, in which a metal circuit layer is used as a ground plane. The figure shows the first section of the present invention. The cross section of the embodiment shows that the L 2 line circuit is a thin film circuit layer connected to the bumps by using the top layer. The metal circuit layer is used as a signal transmission line, power plane, or interface. . Fig. 63 / ^^ shows that the SUif circuit layer according to the second embodiment of the hairpin structure is used as a signal transmission line, a power plane, or a ground plane for external circuit components. Fig. 69 shows the first and second types of metal wiring layers in the first and second embodiments of the present invention. Schematic sectional view. Fig. 2 is a schematic cross-sectional view of a second structure of a metal wiring layer in the first embodiment and the second embodiment of the present invention. Fig. 2 is a schematic cross-sectional view of the second structure of the metal line layer in the first embodiment and the second embodiment of the invention. Fig. 72 is a schematic cross-sectional view of a fourth structure of the metal line layer in the first embodiment and the second embodiment of the present invention. FIG. 73 is a schematic cross-sectional view of a bump according to a second embodiment of the present invention. Fig. 74 and Fig. Show the wafers of the first and second embodiments, respectively. Fig. 7 shows the structure of the wafer applied to the automatic bonding of flexible boards. The first embodiment, the wafer t 7 of the second embodiment. The cross section i of the glass substrate is intended. The structure should be connected to the wafer of the second embodiment. 34 1236722 14012twf.doc [Description of the main component symbols] 100: Wafer structure 110: Semiconductor substrate 112, 112a, 112b: Electronic components 121, 123, 125: Vias 122, 124, 126 Thin film dielectric layers 132, 134, 136: thin film circuit layers 135, 135a, 135b: top-layer thin film circuit layer contacts 140: protective layers 142, 142a, 142b: protective layer openings 150: metal circuit layers 152: Lines 160, 160a, 160b, and 160c of the metal circuit layer: bump 170: polymer layer 172: opening of the polymer layer 200: wafer structure 250: metal circuit layer 260: bump 262 : Bump 270 · polymer layer 272: opening of polymer layer 280: polymer layer 311: adhesion / barrier layer 312: metal layer 321: adhesion / barrier layer 322: metal layer 331: adhesion / barrier layer 332: metal layer 35 1236722 14012twf.doc 333: metal layer 341: adhesion / barrier layer 342: metal layer 343: metal layer 344 ... metal layer 411: adhesion / barrier layer 412: metal layer 502 ... Opening 510: Flexible board 512: Polymer layer 514: Adhesive layer 516: Welding mask layer 520: connection line 522: pins inside the connection line 530: protective body 600: glass substrate 610: anisotropic conductive adhesive or anisotropic conductive film 612: anisotropic conductive adhesive or metal particles in the anisotropic conductive film 700: film substrate 710: polymer layer 720: wiring layer 730: solder mask layer 732: openings of solder mask layer al, a2, a3, a4: thickness of metal layer of metal circuit layer b: thickness of bump d: metal Circuit layer thickness p: polymer layer thickness q: polymer layer thickness s: protective layer thickness 36 1236722 14012twf.doc t: bump thickness tU: bump layer thickness tg: bump metal Layer thickness

37

Claims (1)

1236722 14012twfl.doc / 006 Revised date 93.12.13 X. Patent application scope: 1. A wafer structure including: a semiconductor substrate with a plurality of electronic components, the electronic components are arranged on a surface layer of the semiconductor substrate; A plurality of thin-film dielectric layers are disposed on the bottom of the semiconductor layer, and the thin-film dielectric layers have a plurality of vias; each of the thin-film circuit layers is disposed in each of the thin-film dielectric layers. On the electrical layer, and the thin circuit layers are electrically connected to each other through the vias, and are electrically connected to the electronic components; A protective layer is disposed on the thin film dielectric layers and the thin film circuit layers. A metal circuit layer is disposed on the protective layer. The metal circuit layer includes a first metal layer. The material of the first metal layer includes Gold; and at least one bump on the metal circuit layer, the bump including a second metal layer, the top surface of the bump is provided by the surface of the second metal layer, the second metal layer The material includes gold. 2. The wafer structure according to item 1 in the scope of the patent application, wherein the metal layer is also a transfer / transfer layer, and the -metal layer is located on the adhesion / barrier layer, wherein the adhesion / barrier Material of the layer includes titanium tungsten alloy, titanium nitride Substance, button or button nitrogen compound. 3 · = The wafer structure described in item 1 of the scope of the patent application, wherein the protective layer has a plurality of openings, and the metal circuit layer is electrically connected to the thin film circuit layers through the openings of the protective layer, and the electrons One of the components is suitable for output-electronic signals. The electronic signals pass through the thin film circuit layers and pass through the protective layer, and then are transmitted to the metal circuit layer, and then pass through the protective layer and pass through the thin film circuit layers. Transfer to other electronic components ^^ 38 1236722 14012twfl .doc / 006: The wafer structure described in the item of patent application scope, = layer has-openings, exposing the topmost layer of the thin film protective bump It is electrically connected through the metal circuit layer and the contact of a, this position is different from the layout to the miscellaneous point, the layout is called ^ the scope of patent application! The wafer structure of the wafer structure described in the item has several openings, and the topmost layer of the thin film line and the protective contact are exposed. The metal circuit layer includes the power supply plane and several thin points for electrical connection. Money and materials should be connected to these 6. The wafer structure described in item 1 of the patent scope, 中 ~ :: There are a number of openings, exposing the topmost film ground plane, and the metal circuit layer. The layer includes a point electrically connected to the thin film ground plane. …, The connection 7. The wafer structure as described in the patent application No. 丨, ^, including a region 'at least two of the bumps are located on the region of the metal core' the metal circuit The area of the layer is connected through the bump layers-the external circuit component 'the missed' circuit layer 'of the metal circuit layer and a signal suitable for transmission through the outer-the bumps to the metal circuit The layer is then transmitted to the external circuit component through at least one of the bumps. The wafer structure described in item 1 of the secret patent scope, wherein the metal _ 'the bump is located on the metal circuit layer. On the area, = is a line-shaped area that is electrically connected to an external electrical connection through the convexity. The area of the road layer is not connected to the top-layer thin film circuit layer. A power plane for the material circuit component 39 1236722 14012twfl.doc / 006 with a revised date of 93.12.13. 9. The wafer structure according to item 1 of the patent application scope, wherein the gold circuit layer includes a region, and the bump system is Located in the ^ region 2 of the metal circuit layer "is the metal The area of the circuit layer is suitable for electrically connecting the two-way components through the bump, and the area of the metal circuit layer is not connected to the top thin wire electrical layer, wherein the area of the metal circuit layer is suitable as A ground plane of the external electrical structure. 10. The wafer structure described in item 丨 of the scope of patent application, further comprising a t-layer, located on the layer, and the metal circuit layer is located in the polymer layer. 11. A wafer structure in which the thickness of the rhenium metal layer is greater than 1 micron. 12. The wafer structure according to item 1 of the scope of patent application, and the thickness of the metal layer is greater than 5 microns. 〃 w — 13. The wafer structure according to item 丨 of the patent application, wherein the second metal layer is in direct contact with the first metal layer. / 'μ — 14. The wafer structure described in item i of the scope of patent application, suitable for bonding with a flexible board (Tape), the flexible board having-openings and at least-connecting lines, the connecting lines extending into the openings 'The wafer structure is aligned with the opening of the flexible board and is bonded to the connection line through the bump. It is suitable for electrical connection with a thin film substrate 15. The wafer structure and film substrate (Film) described in the first item of the patent application scope, the crystal 4 structure is a transmissive bump and is electrically connected to it. '16. The wafer structure described in item 4 of patent 4 is suitable for bonding with a glass substrate. 'The w-structure money still bump is electrically connected to the glass plate 1236722 14012twfI.d〇c / 006 Modified date 93.12 .13 Π • The wafer structure described in item 1 of the scope of patent application, wherein the thickness of the protection 2 is greater than 0.35 micrometers, and the structure of the lye layer is a nitrogen oxide layer, a silicon oxide compound layer 1, a phosphosilicate glass layer or a composite layer composed of at least one of the foregoing materials. 18. A type of wafer structure, including a semiconductor substrate having a plurality of electronic components, the electronic components being disposed on a surface layer of the semiconductor substrate; and a plurality of thin film dielectric layers disposed on the semiconductor substrate In the above, the thin-film electrical layers have a plurality of via holes; layers, and film circuit layers, and each of the thin-film circuit layers is respectively disposed on the medium thin film dielectric layers, and the thin-film circuits The layers are electrically connected through the vias, and are electrically connected to the electronic components. -M is disposed on the thin film dielectric layers and the thin film circuit layers;-^ the circuit layer is located on the healthy layer And a Chu bump, which is located on the metal circuit layer, wherein the bump includes a first one of the first metal layer, a top surface of the first metal layer, and a 19 ^ layer. It is made of materials that are not suitable for the reflow step. The block includes an adhesive layer thereon. The adhesion / barrier layer is good. A metal layer is located on the adhesion / barrier layer. The nitrogen compound includes a titanium crane alloy, a titanium nitrogen compound, or a thickness. The material of the metal layer larger than 5 micrometers includes gold, and the first metal layer 20, such as the scope of the patent application, the circuit layer includes-the wafer structure described in item 18, wherein the metal is located earlier in the adhesion / transfer layer. : And-the second metal layer, the material of the second metal layer of gold, titanium nitrogen compound, ^ '^ adhesion / barrier layer includes titanium crane compound-secondary button lice compound, the material layer of the second metal layer is 1236722 14012twfl. doc / 006 amendment date 93.12 < 13 including gold, and the thickness of the second metal layer is more than half. 2L The wafer structure according to item 18 of the scope of the patent application, wherein the all-line circuit layer includes an adhesion / barrier layer and a second metal layer, and the second metal booth is located on the Hao Zhu / transfer layer. The material of the adhesion / transfer layer includes titanium, titanium alloy, titanium nitrogen compound, chromium, chromium copper alloy, button or tantalum nitrogen compound. The material of the second metal layer includes copper, and the thickness of the second metal layer is greater than 丨Microns. '22. The wafer structure according to item 18 of the scope of the patent application, wherein the metal circuit layer includes an adhesion / barrier layer, a second metal layer and a third metal layer, and the second metal material is located at the adhesion On the barrier layer, the third metal layer is located on the second metal layer, and the material of the adhesion / barrier layer includes titanium, titanium tungsten alloy, titanium nitrogen compound, chromium, chromium copper alloy, tantalum or button. Nitrogen compounds. The material of the second metal layer includes copper and the thickness of the second metal layer is greater than i micrometer. The material of the third metal layer includes nickel. 23. The wafer structure as described in claim 18, wherein the metal circuit layer includes an adhesion / barrier layer, a second metal layer, a third metal layer, and a fourth metal layer, and the second metal The layer is located on the adhesion / barrier layer, the third metal layer is located on the second metal layer, and the fourth metal layer is located on the third metal layer, wherein the The material includes titanium, titanium tungsten alloy, titanium nitrogen compound, chromium, chrome copper alloy, button or button nitrogen compound. The material of the second metal layer includes copper and the thickness of the second metal layer is greater than 丨 micron. The third metal The material of the layer includes nickel, and the material of the fourth metal layer includes gold. 24. The wafer structure according to item 18 of the scope of patent application, wherein the metal circuit layer includes a second metal layer, the material of the second metal layer includes gold, and the thickness of the second metal layer is greater than 1 micron. 25. The wafer structure described in item 18 of the scope of the patent application, wherein the gold 42 1236722 14012twfl .doc / 006 revision date 93.12.13 belongs to the circuit layer including a second metal layer, the material of the second metal layer includes steel, The thickness of the second metal layer is greater than 1 micron. 26. The wafer structure according to item 18 of the scope of patent application, wherein the thickness of the metal layer # 1 is greater than 5 microns. '27. The wafer structure as described in item μ of the patent application scope, wherein a metal layer is in direct contact with the metal circuit layer. 28. The wafer structure according to item 18 of the scope of the patent application, wherein the diffused layer has a plurality of openings, and the metal circuit layer is through the protective sound, = the openings are electrically connected to the thin film circuit layers, the electrons The “two of the components” are suitable for outputting an electronic signal. The electronic signal passes through the protective layer through the thin films, is transmitted to the metal circuit layer, and then passes through the layer, and passes through the thin film circuits. The layer transfers to one of the others. —Electrical components to 29—The wafer junction protective layer described in item 18 of the scope of patent application has an opening, exposing the top two of the thin film circuit layer, and the β-Hami bump passes through the metal circuit layer. Electrically connected to the contact, the point, and the local position are different from the layout position of the contact. χ 鬼 布 30. The wafer crust layer described in item 18 of the patent application scope has a large number of π, exposing the topmost shape of the film ^ the protection of contacts, the metal circuit layer includes-a plane, the: Most of them include a thin power plane, the electrical surface of the metal circuit layer = the circuit layer encapsulation point, which is electrically connected to the shaft power plane. ~ From these packages, the wafer structure described in item 18 of the patent scope, and the f-layer has a plurality of openings, exposing the top-most contacts of the protection circuit. The metal circuit layer includes a ground plane. Two of the majority 43 1236722 14012twfl.doc / 006 Revision date 93.12.13 The contact is electrically connected to the film ground plane. 32. The wafer structure according to item 18 of the scope of the patent application, which is a circuit layer including a region, at least two of the bumps are located on the region of the gold wire layer, and the region of the metal circuit layer. It is suitable to connect an external circuit component through the bumps, the area of the metal circuit layer is not connected to the thin film circuit layer of the wheel layer, and a signal is suitable to pass through the external circuit component and one of the bumps. The block is transferred to the area of the metal circuit layer, and then is transferred to the external circuit component through at least one other bump. 2. 33. The wafer structure according to item 18 of the scope of the patent application, wherein the metal circuit layer includes a region, and the bump is located on the region of the metal circuit layer. The region of the metal circuit layer is The bump is suitable for electrically connecting the second and second boundary circuit components. The area of the metal circuit layer is not connected to the top layer of the circuit layer. The area of the circuit layer is suitable as the external circuit. The wafer structure described in item 18, 1 belongs to a circuit layer including a region, the bump is located on the metal, and the region of the metal circuit layer is adapted to be electrically connected through the bump = two, circuit component ' The area of the metal circuit layer is not connected to the area of the top metal circuit layer ^ 35. The wafer structure as described in item 18 of the patent application scope is located on the protective layer, and the metal circuit layer It is located in the polymer ^ ㈣3Γ6. The wafer structure described in item 18 of the patent scope is suitable for a right board (ape; ^ 5, the soft board has an opening and at least-the connection line is light, the open σ towel, the "The structural scale of this soft board = 44 1236722 14012twfl.doc / 006 Amendment date 93.12.13 Open and join the connection line through the bump. ^ 37. The wafer structure described in item 18 of the scope of patent application is suitable for joining with a thin film substrate (Film), The wafer structure is electrically connected to the base through the bump. 38. The wafer structure described in item 18 of the scope of the patent application is suitable for bonding a glass substrate, and the wafer structure passes the bump and the substrate. Electrical connection 39. The chip structure described in item 18 of the scope of patent application, i moderately similar to 0.35 micron, and the structure of the protective layer is a ^ ^ :: -may compound layer, -_ A glass layer or a composite layer composed of at least one of the above materials λ 40. A type of wafer structure, including a semiconductor substrate with a plurality of electronic components arranged at the bottom of the semiconductor layer-the surface layer; There are several thin-film dielectric layers arranged on the semiconductor substrate. The dielectric layer has a plurality of via holes on the semiconductor substrate. A / special film a middle layer f film circuit layer. It is arranged on the thin electrical layers, and the thin road layers are The vias are electrically connected to each other, and are electrically connected to the electronic components; a protective layer is disposed on the thin film dielectric layers and the thin film circuit layers, at least one of which exposes the thin film circuit layer on the top layer. On the wire layer, the golden riding layer includes a Monsanto layer, and the material of the first metal layer includes gold; and, a few bumps-'located on the contact', the bumps include-a second metal Layer, "The surface of the convex dragon is provided by the surface of the second metal layer. The second 45 1236722 14012twfl .doc / 006 amendment date 93.12.13 The material of the metal layer includes gold. 41. The wafer structure according to claim 40 of the stated patent scope, wherein the metal wire layer has a first adhesion / barrier layer, and the first metal layer is located on the first: adhesion / barrier layer ' The bump has a second adhesion / barrier layer, the second metal layer is located on the second adhesion / transition layer, and the occupancy of the layer of the first adhesion / barrier layer is substantially the same as the The thickness of the second adhesion / barrier layer. The wafer structure described in item 40 of the continued patent scope, wherein the metal circuit layer has a -th-adhesive / barrier layer, the metal-adhesive / barrier layer is on, and the convex metal layer is located in violation of the first ^ The bump has a second adhesion / barrier layer, and the second gold second-grandson i η is on the adhesion / barrier layer, wherein the first adhesion / barrier layer is: Degree: Material of the adhesive Γ barrier layer 'The first-adhesive / barrier layer is a sound of Lu and Zr: the thickness of the second adhesive / barrier layer in head 5 and 5h, the thickness of the first gold material is the same as the thickness of the second metal layer. On the block package, the adhesive transfer layer; the layer is located on the adhesive / barrier layer button or button nitrogen compound. Be c includes titanium tungsten alloy, titanium nitrogen compound, 44. If the patent application scope belongs to the circuit layer includes-adhesion /, the wafer structure described above, where the gold barrier layer, where the adhesion / barrier ;; t: The metal layer is located at the adhesion / resistor, knob or histidine compound. Materials include titanium tungsten alloy, titanium nitride 45. If the patent application scope belongs to the circuit layer via the protective layer, the structure described above, wherein the gold thin film circuit layer, the electronic elements and the openings are electrically connected to the Some signals, the electronic signal is suitable for outputting an electronic signal through the secret line—the 溥 circuit layer passes through the protective layer, and is transmitted to the metal circuit layer through 46 1236722 14012twfl.doc / 006, and then passes through the protection. = 期 _ At least two of the transmission from the line layer to the other electronic components are described by these thin layers instead of 4G items_continued item, [Zhongli companion layer has several of these open σ, exposing For most of these contacts, the metal circuit layer includes the wire of the most circuit layer: the layer includes a thin film power plane, and the metal circuit :: is electrically connected to the thin film power plane through the contacts. The 4 source plane system protective layer has a mostly sheet structure, wherein the plurality of contacts and the metal wires are included; the circuit layer includes a thin-film ground plane, and the thin layers of gold are electrically connected to the film through the contacts. Ground plane. The ground plane is 48. The chip circuit layer described in item 4 () of the scope of patent application includes-the area is suitable for electrical connection-the external electrical second: the area of the gold ^ circuit layer is not connected to the top layer of the Thin film line # 1, the gold II is transmitted to the metal via the external circuit component; the signal is suitable for transmission to the external circuit component. Area, and then retransmit the wafer structure described in item 4G of the system, Fuzhong W belongs to the circuit layer and the area is not connected to the top film edge η 'The gold: the area of the circuit layer is suitable as the The external circuit structure ": 50. If the patent application scope No. 40 belongs to the circuit layer includes-area, suitable for electrical properties __ ^^ 'Where the metal circuit layer is not connected to the thin film circuit layer of the top layer, and the middle ★ Hai 2, the area of the gold is a ground plane metal circuit layer suitable for the external circuit component 47 1236722 14012twfl.doc / 006 Date of amendment 93.12.13 51. According to the wafer structure described in item 4G of the scope of patent application, The thickness of the metal circuit layer is substantially equal to the thickness of the bump. "52. The wafer structure described in item 4G of the patent application scope, wherein the thickness of the metal circuit layer is smaller than the thickness of the bump. 53. The wafer structure described in item 40 of the patent application scope, further comprising a A polymer layer is located on the protective layer, and the metal circuit layer is located on the polymer layer, wherein the thickness of the bump is greater than the total thickness of the metal circuit layer plus the polymer layer. The wafer structure described in item 4G further includes a polymer layer on the protective layer, and the metal circuit layer is on the polymer layer, wherein the thickness of the bump is smaller than the metal circuit layer plus the polymer layer. The total thickness of the material layer. 55. The wafer structure according to item 40 of the patent application scope, further comprising a polymer layer on the protective layer, and the metal circuit layer on the polymer layer, wherein the bumps The thickness is approximately equal to the total thickness of the metal, circuit layer and the polymer layer. 56. The wafer structure described in item 40 of the patent application scope further includes a polymer layer on the protective layer, the The circuit layer is located on the polymer layer. The polymer layer has at least -open σ, and the contact is exposed. The bump is located on the opening of the protective layer and the opening of the polymer layer. On the exposed contact, and the bump protrudes beyond the opening of the polymer layer, the thickness is substantially equal to the thickness of the metal circuit layer. 57. The wafer structure described in item 40 of the scope of patent application, It also includes a polymer layer on the protective layer, and the metal circuit layer is on the polymer layer, wherein the polymer layer has at least one opening to expose the contact, and the bump is located on the protective layer. The thickness of the contact Jl 'which is exposed by the opening of the polymer layer and the opening of the polymer layer 48 1236722 14012twfl.doc / 006 is 93.12.13, and the thickness of the bump protruding beyond the opening of the polymer layer is Greater than the thickness of the metal circuit layer. 58. The wafer structure as described in item 4 () of the patent application scope, further comprising a polymer layer on the metal circuit layer. ^ 59 · As stated in the patent application scope item 40 The wafer structure, wherein the projection It is electrically connected to the metal circuit layer through the thin film circuit layer on the top layer. M • The wafer structure according to item 59 of the patent application scope, wherein the shortest distance between the convex t and the plane of the metal layer is between 丨Micron to · Micron 61 · The wafer structure as described in item 4 () of the Zhongji patent range, further including to v — the first bump, which is located on the metal circuit layer. The wafer structure according to item 61, wherein the total thickness of the first bump and the metal circuit layer is approximately equal to one of the bump 63. The wafer structure according to claim 61, wherein The block j includes a second metal layer, and the top surface of the second bump is provided by the first and second layers. The material of the third metal layer includes gold. -64. The wafer structure described in item 63 of the scope of patent application, the thickness of the two metal layers in the basin is greater than 5 microns. I 65 · The wafer structure described in item 40 of the scope of the patent application, further comprising a two-to-one polymer layer, the polymer is located on the protective layer; it is pure on the recording joint, and the material is convex. % 66. The wafer structure according to item 65 of the scope of the patent application, wherein the -bump, money > | The degree is roughly J 49 1236722 14012twfl.doc / 006 Date of amendment 93.12.13 67. The wafer structure as described in the patent scope of Shenyan 其中 65, wherein the first bump includes a third metal layer and the second bump The top surface of the block is provided by the surface of the third metal layer, and the material of the third metal layer includes gold. 68. The wafer structure as described in item 帛 M of the Shenjing patent, wherein the thickness of the third metal layer is greater than 5 microns. 69. The wafer structure described in claim 40 of the Patent Application, wherein the thickness of the first metal layer is greater than 1 micron. 70. The wafer structure according to item 40 of the Shenjing patent scope, wherein the thickness of the first metal layer is greater than 5 microns. 71. The wafer structure described in item 4 () of the patent application scope is suitable for bonding with a flexible board (Tape), which has an opening and at least one connection line that extends to the towel, The crystal structure aligns the opening of the flexible board and is connected to the connection line through the bump. * 72. The wafer structure described in item 4 () of the towel patent range is suitable for bonding with a ^ (Fllm). The wafer structure is electrically connected to the film substrate through the bump. 73. The wafer structure described in item 4 () of the scope of the patent application is suitable for bonding a glass substrate, and the wafer structure is electrically connected to the shaft glass substrate through the bump. 74. According to the wafer structure described in Item 40 of the scope of the patent application, the thickness of the protective layer is greater than 0.35 micrometers, and the structure of the protective layer is H, a compound layer, a silicon oxide compound layer, and a phosphorus silicon. A glass layer or a composite layer composed of at least one element. 75. A kind of wafer structure, including: a semiconductor substrate with a plurality of electronic components, which are arranged on a surface layer of the semiconductor substrate; a few pieces are 50 1236722 14012twfl.doc / 006 most layers are thin The electrical layer is arranged in a wide period of 93.12 · 13. The dielectric layer has a large number of vias; ... on the Dow's, the thin films, the upper and lower layers, and the thin-film circuit layers are respectively arranged on the surface: ΐί 'is disposed on the thin films On the dielectric layer and the thin film circuits, a metal circuit layer is located on the protective layer; and an acoustic block is located on the contact, where the bump includes-the first-gold ^ one of the bumps. The surface is made of the surface of the first metal layer, and the metal layer is made of a material that is not suitable for the reflow step. -76. The wafer block described in item 75 of the scope of patent application has a first-adhesive transfer layer, the first-gold layer is on the first barrier layer, and the metal circuit layer has a second-adhesion / barrier layer And two I-based layers 'The second metal layer is located on the second adhesion / barrier layer, and the material of the first adhesion / barrier layer is the material of the third adhesion / transfer layer,' and the The thickness of the first adhesion / barrier layer is substantially the same as the thickness of the second adhesion / barrier layer. 77. The wafer structure according to item 75 of the patent application, wherein the bump has a -first-adhesive / barrier layer, the first metal layer is located on the first adhesive / barrier layer, and the metal circuit The layer has a second adhesion / barrier layer and a second metal layer. The delta metal second metal layer is located on the second adhesion / barrier layer, and the material of the first adhesion / barrier layer is the same as Quality of the second adhesion / barrier layer: and the thickness of the first adhesion / barrier layer is substantially the same as that of the second barrier, and the material of the first metal layer is the same as that of the second metal layer 51 1236722 14012twfl .doc / 006 Revision date 93.12.13 Second, the thickness of the first-metal rhenium is approximately the same as the thickness of the first metal layer 78. The wafer structure described in item 75 of the patent application, bean The middle block includes -㈣ / transfer layer, the first-metal · bit Qianlin shirt barrier exhibition: the material of the adhesion / barrier layer includes titanium crane alloy, titanium nitrogen compound, button nitrogen compound, the first metal layer The material of the material includes gold, and the thickness of the first layer is greater than 5 microns. ^ ^ 79. The wafer structure described in item 75 of the scope of the patent application, wherein the eight-line circuit layer includes-an adhesion / barrier layer and-a second metal layer, and the second metal is in the adhesion / resistance On the barrier layer, wherein the material of the adhesion / barrier layer includes titanium alloy, titanium nitrogen compound, button or tantalum nitrogen compound, the material of the second metal layer includes gold, and the thickness of the second metal layer is greater than 丨 microns . 80. The wafer structure according to item 75 of the scope of patent application, wherein the circuit layer includes an adhesion / barrier layer and a second metal layer, and the third metal / chip is located in the adhesion / barrier layer The material of the adhesion / barrier layer includes titanium, titanium alloy, titanium nitrogen compound, chromium, chromium-copper alloy, button or tantalum nitrogen compound. The material of the second metal layer includes copper, and the material of the second metal layer The thickness is greater than 丨 micron. '81. The wafer structure according to item 75 of the scope of patent application, wherein the metal circuit layer includes an adhesion / barrier layer, a second metal layer and a third metal layer, and the second metal layer is located in the On the adhesion / barrier layer, the second property is located on the second, where the material of the adhesion layer = layer = Yan alloy, titanium nitrogen compound, chromium, chromium copper alloy, button or button nitrogen compound, The material of the second metal layer includes copper and the thickness of the second metal layer is greater than 1 μm. The material of the third metal layer includes nickel. 82. The wafer structure described in item 75 of the scope of the patent application, wherein the gold 52 1236722 14012twfl.doc / 006 amendment_3.12.13 The metal circuit layer includes an adhesion / barrier layer, a second metal layer, a third And a fourth metal layer, the second metal layer is located on the adhesion / barrier layer, the second metal layer is located on the second metal layer, and the fourth metal layer is located # ^ third metal On the layer, wherein the material of the adhesion / barrier layer includes Chin, Qinheren / Z titanium nitrogen compound, chromium, chrome copper alloy, or new nitrogen compound, the material of the layer includes copper and the thickness of the second metal layer is The material of the two metal layer larger than i micrometer includes antimony. The material of the fourth metal layer includes gold. j 83. The u-structure described in item 75 of the patent application, I belongs to the line, the layer includes a second metal layer, the material of the second metal layer includes two, and the thickness of the second metal layer is greater than 1 micron. 84. According to the wafer structure described in item 75 of the patent scope, the circuit layer includes a second metal layer, the second gold _ = gold, and the thickness of the second metal layer is greater than i micrometer. Material copper, 85. As described in the application for full-time ㈣75, the chip belongs to the circuit layer through the majority of the electrical protection of the protective layer = thin-film circuit layer, one of the electronic components: ^ connected to the No., the electronic signal is transmitted to the metal circuit layer through the thin film circuit layer electronic signals, and then passes through the J layer, and the transmission line layer is transmitted to other electronic components at least ^ by the thin films 86. For example, the scope of patent application is 7. The protective layer has a plurality of these, and the M, wherein the plurality of the contacts, the circuit layer of the metal circuit layer, the circuit layer includes a thin film power plane, the metal wire = thousands of faces, and the films pass through the These contacts are electrically connected to the plane of the thin film power source / the plane of the source of the money. 87. For example, the protective cover of item 75 of the patent has a plurality of openings. Take out the top layer of the thin film circuit layer 53 1236722 14012twfl.doc / 006 The ground plane electrically connected to the thin circuit layer through the contacts is 88. As for the Japanese film described in the scope of the application for patent «75, Shifang Gan The f circuit layer includes a region, which is suitable for electrically transmitting the film circuit layer through the external circuit component—the signal is suitable for transmission to the external circuit component. & The area of the circuit layer 'Retransmission 89. For example, if the scope of patent application 帛 7 belongs to the area of the circuit layer including-area, suitable for New Zealand ==', where the area of the metal circuit layer is not connected to external circuit components, The metal circuit layer is composed of a thin film circuit layer of ¾ series and θ, wherein the gold surface. ° £ or the wafer structure described in item 75 of a power-supply flat patent range suitable for the external circuit component, wherein the all-inclusive circuit layer includes a region, which is suitable for electrically connecting the thin-film circuit layer in an outer layer. Its + the metal line: a domain is suitable as a ground plane for the external circuit component. Wherein the thickness of the metal layer of the wafer structure 'described in the patent scope item 75 is greater than 5 microns. The wafer structure described in item 75 of the patent application scope of Core 9々2f, the thickness of the circuit layer is substantially equal to the thickness of the bump. 93. For example, if the scope of patent application: 75, the thickness of the circuit layer is smaller than the thickness of the bump. Said film ... Structure 94. If the scope of the patent application is No .: the compound layer is 'on the protective layer, the metal = two = cladding = on the layer', where the thickness of the bump is greater than the metal circuit layer plus 54 1236722 14012twfl .doc / 006 Revised date 93.12.13 The total thickness of the layer. 95. The wafer structure described in item 75 of the scope of patent application, further comprising a polymer layer 'on the protective layer, and the metal circuit layer system is located in the figure = total = the thickness of the bump is less than the metal circuit 96. The wafer structure described in item 75 of the scope of patent application, further comprising a polymer layer 'located on the protective layer, and the metal circuit layer is located on the polymer layer' of the far-bumped The thickness is approximately equal to the total thickness of the plus polymer layer. 97. The wafer structure described in item 75 of the scope of patent application, further comprising a polymer layer 'on the protective layer' and the metal circuit layer is located on the second layer of the polymer L with at least one opening 'exposing the contact The bump is located on the contact exposed by the opening of the engraved pure layer and the opening of the polymer layer, and the degree of the convex-junction hybrid layer is substantially equal to that of the metal circuit layer. thickness. The outer thickness is 98. As described in the scope of the patent application No. 75, wafer one = object two = protective layer, the metal circuit layer is located on the poly-pure day, and the material layer has at least one opening, The contact point is exposed, the bump is located on the secret point exposed by the opening, the polymer-like opening, and the protrusion of the bump is greater than that of the metal circuit layer. thickness. Outside; 99. The crystalline polymer layer as described in the scope of application patent No. 75 is located on the metal circuit layer. Retrogression 100. According to the wafer structure described in item 75 of the patent application scope, the block in the basin is electrically connected to the metal wire through the thin film circuit layer on the top layer. The wafer structure described in item _ of the scope of the patent application, wherein the 55 1236722 amendment date is 93.12.13 14012twfl.doc / 006. The shortest distance between the bump and the metal circuit layer is between 丨 micrometer and 500 micrometers. between. 102. The wafer structure described in item 75 of the patent application scope further includes at least one second bump located on the metal circuit layer. 々103. The wafer structure according to item 102 of the scope of patent application, wherein the combined thickness of the second bump and the metal circuit layer is substantially equal to the thickness of the bump. ^ 104. The wafer structure described in claim 102, wherein the second bump includes a second metal layer, and a top surface of the second bump is provided by a surface of the second metal layer. The second metal layer is made of a material that is not suitable for the re-soldering step. 105. The wafer structure as described in claim 104, wherein the material of the second metal layer includes gold. 々 〇106. The wafer structure according to item 104 of the patent application scope, wherein the thickness of the metal layer is greater than 5 microns. 107. The wafer structure as described in the scope of the patent application: 75 items, further comprising: a second bump and a polymer layer, the polymer is located on the protective layer, and the metal circuit layer is located in Mohe On the object layer, the second bump is located on the metal circuit layer. ★ ι〇8. The wafer structure according to item 107 of the scope of patent application, wherein the total thickness of the first bump, the metal circuit layer, and the polymer layer is substantially equal to the thickness of the bump . ^ 109. The wafer structure as described in claim 107, wherein the second bump includes-a second metal layer. The top surface of one of the second bumps is provided by a surface of the second metal layer. The second metal layer is made of a material that is not suitable for the re-soldering step. 56 1236722 14012twfl.doc / 006 Date 93i2.I3 110. The wafer structure described in item 109 of the patent application scope, wherein the material of the second metal layer includes gold. 'M 1U. The wafer structure according to item 109 of the patent application scope, wherein the thickness of the first metal layer is greater than 5 microns. 'Person 112. As described in the patent application, the wafer structure described in the first item, a flexible board (Tape) bonding, the flexible board has an opening and at least one connection failure line extends into the opening, the wafer structure is aligned The soft extension is opened, and is connected to the connection line through the bump. The 113. The wafer structure described in item 75 of the patent application is suitable for disk-bonding. The wafer structure is the wafer structure described in item 7 / item of the patent scope of the thin film glass through the bump, which is suitable for A connection Γ. ‘The wafer structure is the wafer structure described in item 75 of the range of the electrical protection layer of the glass substrate through the bumps, wherein the warranty 2: the compound one: the compound layer, the glass layer, or at least-the above material 57