TWI460820B - Integrated circuit (ic) chip and method for fabricating the same - Google Patents

Description

Integrated circuit (IC) chip and its process

The present invention relates to a wiring structure and a process thereof, and more particularly to an integrated circuit (IC) wafer and a process therefor.

In the process of plating metal over a protective layer of a wafer, an under bump metal (UBM) layer is formed by sputtering, which is composed of two metal layers, and the first layer is a An adhesion/barrier layer, such as a layer of titanium-tungsten alloy, which serves to provide a good adhesion between the pad and the subsequent plated metal and to prevent a diffusion reaction between the pad and the plated metal material; The second metal layer serves as a seed layer for electroplating in addition to the conductive layer during electroplating. Then, a metal layer is formed on the underlying metal layer by forming a patterned photoresist layer on the underlying metal layer and plating the metal into the opening of the photoresist layer.

However, when the pad is an aluminum pad or the metal cap above the pad contains aluminum metal, and a layer of titanium-tungsten alloy layer as an adhesion/barrier layer is plated to form a gold layer. In the high-temperature process, the gold atoms of the gold layer penetrate the titanium-tungsten alloy layer to form an intermetallic compound (IMC) with the aluminum under the titanium-tungsten alloy layer, thereby causing embrittlement of the structure and affecting the structure. Reliability.

It is an object of the present invention to provide an IC chip and a process thereof which have good barrier and adhesion capabilities.

An object of the present invention is to provide an IC chip and a process thereof for preventing formation of a metal intermetallic compound (IMC) by an aluminum metal under an adhesion/barrier layer, thereby causing embrittlement and influence of the structure. Structural reliability.

An object of the present invention is to provide an integrated circuit chip and a process thereof, wherein the adhesion/barrier layer is composed of two layers of a titanium-containing metal layer, and the first layer of the titanium-containing metal layer is subjected to a tempering process. The titanium metal layer causes the gold layer on the adhesion/barrier layer to be in a high temperature process, and the gold atoms cannot penetrate the adhesion/barrier layer to form a metal intermetallic compound (IMC) with the aluminum metal under the adhesion/barrier layer, and further Causes embrittlement of the structure and affects the reliability of the structure.

For the above purposes, the present invention provides an integrated circuit chip (IC chip) comprising a semiconductor substrate; a wiring structure positioned above the semiconductor substrate; a protective layer positioned above the wiring structure and located at One opening in the protective layer exposes one of the pads of the circuit structure; a first titanium-containing metal layer is located above the pad exposed by the opening; and a second titanium-containing metal layer is located in the first a titanium-containing metal layer on the protective layer; and a first metal layer on the second titanium-containing metal layer.

For the above purposes, the present invention provides an integrated circuit wafer comprising a semiconductor substrate; a wiring structure positioned above the semiconductor substrate; a first polymer layer positioned above the wiring structure and located in the One of the first polymer layer openings in the first polymer layer exposes one of the wiring structures; a first titanium-containing metal layer is located above the pad exposed by the opening of the first polymer layer; a second titanium-containing metal layer on the first titanium-containing metal layer; and a first metal layer on the second titanium-containing metal layer.

For the above purpose, the present invention provides an integrated circuit wafer comprising a semiconductor substrate; a wiring structure positioned above the semiconductor substrate; and a first titanium-containing metal layer positioned on one of the wiring structures Upper, the first titanium-containing metal layer comprises a surface layer containing nitrogen, and the surface layer has a thickness of less than 2,500 angstroms; and a first metal layer is located above the first titanium-containing metal layer.

For the above purposes, the present invention provides an integrated circuit wafer comprising a semiconductor substrate; a wiring structure positioned over the semiconductor substrate; a nitrogen-containing metal layer positioned over one of the pads of the wiring structure, and The nitrogen-containing metal layer has a thickness of less than 2,500 angstroms; and a first metal layer is positioned above the nitrogen-containing metal layer.

For the above purpose, the present invention provides an integrated circuit wafer comprising a semiconductor substrate; a wiring structure positioned above the semiconductor substrate; and a first titanium-tungsten alloy layer positioned above one of the wiring structures a second titanium-tungsten alloy layer on the first titanium-tungsten alloy layer; and a first metal layer on the second titanium-tungsten alloy layer.

For the above purposes, the present invention provides an integrated circuit wafer comprising a semiconductor substrate; a wiring structure positioned above the semiconductor substrate; and a titanium nitride (TiN) layer positioned on one of the wiring structures. a titanium-containing metal layer on the titanium nitride layer; and a first metal layer on the titanium-containing metal layer.

For the above purposes, the present invention provides an integrated circuit wafer comprising a semiconductor substrate; a wiring structure positioned above the semiconductor substrate; a titanium-containing metal layer positioned above the wiring structure; a titanium layer, On the titanium-containing metal layer; and a first metal layer on the titanium layer.

For the above purposes, the present invention provides an integrated circuit wafer process comprising the steps of: providing a semiconductor substrate having a line structure over the semiconductor substrate and a protective layer over the line structure and located in the protective layer An opening in the inner portion exposes one of the pads of the circuit structure; forming a first titanium-containing metal layer above the pad; and performing an atmosphere on the first titanium-containing metal layer in an environment containing nitrogen (N ₂ ) An annealing process; after the tempering process, forming a second titanium-containing metal layer on the first titanium-containing metal layer; forming a first metal layer on the second titanium-containing metal layer; forming a first photoresist layer is on the first metal layer, and a first photoresist layer opening in the first photoresist layer exposes the first metal layer; forming a second metal layer in the first The first metal layer is exposed on the photoresist layer opening; the first photoresist layer is removed; and the first metal layer and the second titanium-containing metal layer not under the second metal layer are removed.

For the above purposes, the present invention provides an integrated circuit wafer process comprising the steps of: providing a semiconductor substrate having a line structure over the semiconductor substrate and a protective layer over the line structure and located in the protective layer An opening therein exposes one of the wiring structures; a titanium nitride (TiN) layer is formed over the pad; a titanium-containing metal layer is formed on the titanium nitride layer; and a first metal layer is formed Forming a first photoresist layer on the first metal layer, and forming a first photoresist layer in the first photoresist layer to expose the first metal layer; forming a second metal layer on the first metal layer exposed by the opening of the first photoresist layer; removing the first photoresist layer; and removing the first metal layer not under the second metal layer Containing a titanium metal layer.

For the above purposes, the present invention provides an integrated circuit wafer process comprising the steps of: forming a first metal layer over a semiconductor substrate; and performing a tempering process on the first metal layer in an atmosphere containing nitrogen; And after the tempering process, a second metal layer is formed on the first metal layer.

For the above purposes, the present invention provides an integrated circuit wafer process comprising the steps of: forming a titanium nitride (TiN) layer on a metal layer over a semiconductor substrate; and forming a titanium-containing metal layer in the nitridation On the titanium layer.

The purpose, technical contents, features and effects achieved by the present invention will be more readily understood by the detailed description of the embodiments and the accompanying drawings.

Referring to FIG. 1A, a semiconductor substrate 2 is, for example, a germanium substrate, a gallium arsenide (GaAs) substrate, or a germanium telluride (SiGe) substrate, and the semiconductor substrate 2 may also be a blank wafer. The blank wafer is, for example, a silicon wafer, a gallium arsenide wafer, or a germanium telluride wafer. The plurality of semiconductor elements 4 are located in or above the semiconductor substrate 2, and the semiconductor elements 4 include passive elements (such as resistors, capacitors or inductors) or active elements, etc., wherein the active elements are, for example, metal oxide semiconductor (MOS) elements, the gold oxide The semiconductor elements are, for example, p-channel MOS devices, n-channel MOS devices, biCMOS devices, and bi-carrier connections. Bipolar Junction Transistor (BJT) or Complementary Metal Oxide Semiconductor (CMOS). In addition, the term "above" in the present invention means that it is located on and in contact with something, or that it is located on something but not in contact with it.

A line structure 6 is located above the semiconductor substrate 2, and the line structure 6 may be composed of a plurality of metal layers 8 (having a thickness of, for example, less than 3 μm, for example, between 0.2 μm and 2 μm) and a plurality of metal plugs (metal Plug) 10 is composed. For example, the metal layers 8 and the metal plugs 10 are mainly made of copper, and the thickness of the metal layers 8 is, for example, less than 3 micrometers (for example, between 0.2 micrometers and 2 micrometers); or, these metal layers The material of 8 is mainly aluminum-containing metal (such as aluminum or aluminum alloy), and the metal plug 10 is mainly made of tungsten, wherein the thickness of the metal layer 8 is, for example, less than 3 micrometers (for example, between 0.2 micrometers and 2 Between microns). In addition, the manner of forming the metal layer 8 includes a damascene process, an electroplating process, and a sputtering process, for example, forming a metal layer 8 as a metal layer 8 by a damascene process, an electroplating process, or a sputtering process, or Aluminum or an aluminum alloy is formed as the metal layer 8 by a sputtering process. Alternatively, the line structure 6 may also include a coil (not shown).

For example, in the case of the damascene process, the metal layer 8 is formed by first depositing an inorganic protective layer on the upper surface of a dielectric layer 12 by means of chemical vapor deposition (CVD). The material of the inorganic protective layer is selected from the group consisting of a nitrogen ruthenium compound, a oxynitride compound or a carbon ruthenium compound, and then a photoresist layer is formed on the inorganic protective layer, and the inorganic protective layer is etched by using the photoresist layer opening in the photoresist layer. Forming an opening composed of a trench and a via hole with the dielectric layer 12, and then depositing a barrier layer on the lower surface and the sidewall of the opening and the upper surface of the inorganic protective layer by sputtering or chemical vapor deposition The material of the barrier layer is selected from the group consisting of tantalum (Ta), tantalum nitride (TaN), cobalt (Co), nickel (Ni), tungsten (W), tungsten nitride (WN), niobium (Nb). , one of aluminum silicate, titanium nitride (TiN), and titanium germanium nitride (TiSiN), or an alloy formed from the above materials; again using sputtering or chemical vapor deposition Depositing a layer of a seed such as copper on the barrier layer and continuing to plate a copper On the seed layer, the copper metal, the seed layer and the barrier layer outside the opening are removed by chemical mechanical polishing (CMP) until the upper surface of the inorganic protective layer is exposed. The barrier layer, the seed layer and the copper metal formed in the trench in this manner are the metal layer 8, and the metal layer 8 can pass through the metal plug 10 in the via hole to connect the metal layer between the adjacent two layers. 8 is either connected to the semiconductor component 4.

Moreover, the method of forming the metal layer 8 is to first sputter an aluminum alloy layer (which includes 90 wt% or more of aluminum and 10 wt% or less of copper) on a dielectric layer 12 by a sputtering process, and then pass through the micro layer. The aluminum etching layer is patterned by a shadow etching process.

The plurality of dielectric layers 12 are positioned above the semiconductor substrate 2, and the metal layer 8 is disposed between the dielectric layers 12, and is connected to the adjacent two layers through the metal plugs 10 located in the dielectric layers 12. Metal layer 8. The dielectric layer 12 is generally formed by chemical vapor deposition (CVD), and the dielectric layer 12 is, for example, an oxonium compound (for example, SiO ₂ ) or an oxide of tetraethoxy decane (TEOS). , silicon, carbon, oxygen compounds to hydrogen (e.g., _{Si w C x O y H z} ) containing, nitrogen-silicon compound (e.g., Si ₃ N _4), oxynitride silicon compound, a fluorine silicon glass (Fluorinated Silicate glass, FSG), Silk screen layer (SiLK), Black Diamond film, Borophosphosilicate Glass (BPSG), polyarylene ether, porous silicon oxide, polybenzoxazole , PBO), a material having a dielectric constant value (k) between 1.5 and 3 or a glass formed by spin coating (Spin-On Glass, SOG; Chinese can also be translated as spin-on glass). Alternatively, the thickness of the dielectric layer is, for example, less than 3 microns, such as between 0.3 microns and 2.5 microns or between 0.3 microns and 3 microns.

A protective layer 14 is positioned over the wiring structure 6 and the dielectric layer 12. The protective layer 14 protects the semiconductor component 4 and the wiring structure 6 from moisture and foreign ion contamination, that is, It is said that the protective layer 14 can prevent mobile ions (such as sodium ions), moisture, transition metals (such as gold, silver, copper) and other impurities from penetrating, and damage the semiconductor components under the protective layer 14. 4 (for example a transistor, a polysilicon resistor or a polysilicon-polysilicon capacitor) or a line structure 6. In addition, the term "below" is used in the present invention to mean that it is underneath and in contact with something, or that it is underneath something but not in contact with it.

The protective layer 14 is usually composed of an oxonium compound (for example, SiO ₂ ), Phosphosilicate Glass (PSG), a nitrogen cerium compound (for example, Si ₃ N ₄ ) or an oxynitride compound, and the thickness of the protective layer 14 Typically, it is greater than 0.3 microns (μm), for example, the thickness of the protective layer 14 is between 0.3 microns and 1.5 microns. Further, in the case where the protective layer 14 includes a layer of a ruthenium nitride compound, the thickness of the ruthenium nitride compound layer is usually more than 0.3 μm. Next, the manner of manufacturing the protective layer 14 will be described, which is about ten different methods, which are respectively described below.

The first method of forming the protective layer 14 is to first form a layer of germanium oxide having a thickness of between 0.2 μm and 1.2 μm by chemical vapor deposition (CVD), followed by chemical vapor deposition (CVD) to form a thickness between A layer of tantalum nitride between 0.2 micrometers and 1.2 micrometers is on the tantalum oxide layer. Among them, the word "upper" in the present invention means that it is placed on and in contact with something.

The second method of forming the protective layer 14 is to first form a niobium oxide layer having a thickness of between 0.2 μm and 1.2 μm by chemical vapor deposition (CVD), and continue to utilize plasma enhanced chemical vapor deposition (Plasma Enhanced Chemical). Vapor Deposition (PECVD) forms a layer of bismuth oxynitride between 0.05 μm and 0.15 μm on the yttrium oxide layer, followed by chemical vapor deposition (CVD) to form a thickness between 0.2 μm and 1.2 μm. A tantalum nitride layer is on the niobium oxynitride layer.

A third method of forming the protective layer 14 is to first form a layer of bismuth oxynitride having a thickness of between 0.05 μm and 0.15 μm by chemical vapor deposition (CVD), and continue to form a thickness by chemical vapor deposition (CVD). A layer of germanium oxide between 0.2 μm and 1.2 μm is deposited on the hafnium oxynitride layer, followed by chemical vapor deposition (CVD) to form a tantalum nitride layer having a thickness between 0.2 μm and 1.2 μm in the hafnium oxide layer. on.

A fourth method of forming the protective layer 14 is to first form a first ruthenium oxide layer having a thickness of between 0.2 μm and 0.5 μm by chemical vapor deposition (CVD), and continue to form a thickness by spin-coating. a second ruthenium oxide layer between 0.5 micrometers and 1 micrometer on the first ruthenium oxide layer, followed by chemical vapor deposition (CVD) to form a third ruthenium oxide having a thickness between 0.2 micrometers and 0.5 micrometers The layer is on the second hafnium oxide layer, and finally a chemical vapor deposition (CVD) is used to form a tantalum nitride layer having a thickness of between 0.2 μm and 1.2 μm on the third hafnium oxide layer.

The fifth method for forming the protective layer 14 is to form a germanium oxide layer having a thickness of between 0.5 μm and 2 μm by using High Density Plasma Chemical Vapor Deposition (HDP-CVD). A layer of tantalum nitride having a thickness of between 0.2 micrometers and 1.2 micrometers is formed on the tantalum oxide layer by chemical vapor deposition (CVD).

The sixth method for forming the protective layer 14 is to first form an undoped silicate glass (USG) having a thickness between 0.2 μm and 3 μm, and continue to form, for example, tetraethoxy decane, borophosphorus. An insulating layer having a thickness of between 0.5 μm and 3 μm, such as borophosphosilicate glass (BPSG) or phosphosilicate glass (PSG), on an undoped bismuth glass layer, followed by chemical vapor deposition (CVD) forming a tantalum nitride layer having a thickness of between 0.2 μm and 1.2 μm on the insulating layer.

A seventh method of fabricating the protective layer 14 is to selectively form a first layer of bismuth oxynitride having a thickness between 0.05 micrometers and 0.15 micrometers by chemical vapor deposition (CVD), and continue to utilize chemical vapor deposition (CVD). Forming a ruthenium oxide layer having a thickness between 0.2 microns and 1.2 microns on the first ruthenium oxynitride layer, and then selectively using chemical vapor deposition (CVD) to form a thickness between 0.05 microns and 0.15 microns a second layer of bismuth oxynitride on the yttrium oxide layer, followed by chemical vapor deposition (CVD) to form a tantalum nitride layer having a thickness between 0.2 microns and 1.2 microns on the second layer of bismuth oxynitride or On the ruthenium oxide layer, a third bismuth oxynitride layer having a thickness of between 0.05 μm and 0.15 μm can be selectively formed on the tantalum nitride layer by chemical vapor deposition (CVD), and finally the chemical gas is used. Phase deposition (CVD) forms a hafnium oxide layer having a thickness between 0.2 microns and 1.2 microns on the third hafnium oxynitride layer or on the tantalum nitride layer.

The eighth method for forming the protective layer 14 is to first form a first ruthenium oxide layer having a thickness of between 0.2 μm and 1.2 μm by chemical vapor deposition (CVD), and continue to form a thickness of 0.5 μm by spin coating. A second ruthenium oxide layer between 1 micron is on the first ruthenium oxide layer, followed by chemical vapor deposition (CVD) to form a third ruthenium oxide layer having a thickness between 0.2 micrometers and 1.2 micrometers in the second oxidation On the ruthenium layer, a layer of tantalum nitride having a thickness of between 0.2 μm and 1.2 μm is formed on the third yttria layer by chemical vapor deposition (CVD), and finally formed by chemical vapor deposition (CVD). A fourth layer of ruthenium oxide having a thickness between 0.2 microns and 1.2 microns is on the tantalum nitride layer.

The ninth method for fabricating the protective layer 14 is to first form a first ruthenium oxide layer having a thickness of between 0.5 μm and 2 μm by high-density plasma chemical vapor deposition (HDP-CVD), and continue to utilize chemical vapor deposition. (CVD) forming a tantalum nitride layer having a thickness between 0.2 μm and 1.2 μm on the first tantalum oxide layer, followed by high-density plasma chemical vapor deposition (HDP-CVD) to a thickness of 0.5 μm A second layer of tantalum oxide between 2 microns is on the tantalum nitride layer.

The tenth method for fabricating the protective layer 14 is to first form a first tantalum nitride layer having a thickness of between 0.2 μm and 1.2 μm by chemical vapor deposition (CVD), and continue to form a thickness by chemical vapor deposition (CVD). A layer of germanium oxide between 0.2 micrometers and 1.2 micrometers is on the first tantalum nitride layer, followed by chemical vapor deposition (CVD) to form a second nitride having a thickness between 0.2 micrometers and 1.2 micrometers. The ruthenium layer is on the ruthenium oxide layer.

The present invention exposes one of the pads 16 of the wiring structure 6 through an opening 14a in the protective layer 14. The thickness t of the pad 16 is, for example, between 0.4 micrometers and 3 micrometers or between 0.5 micrometers. Between 3 microns. The method of forming the pad 16 is, for example, forming a silicon or aluminum alloy as a pad 16 (having a thickness of, for example, between 0.5 micrometers and 3 micrometers) by a sputtering process, or forming copper as a pad 16 by an electroplating process (its The thickness is, for example, between 0.5 micrometers and 3 micrometers or between 0.4 micrometers and 3 micrometers, and when the pad 16 is a copper pad formed by an electroplating process, there are A barrier layer material such as tantalum (Ta) or tantalum nitride (TaN). Therefore, the pad 16 may be a metal layer (also referred to as an aluminum pad) having a thickness of between 0.5 micrometers and 3 micrometers and a material mainly comprising aluminum, or a thickness of between 0.5 micrometers and 3 micrometers or A metal layer (also known as a copper pad) that is between 0.4 micrometers and 3 micrometers and whose material mainly comprises copper.

The maximum lateral dimension d of the opening 14a is between 2 microns and 30 microns, or between 30 microns and 300 microns. In addition, the shape of the opening 14a may be a circle, a square or a polygon of five or more sides, and the maximum lateral dimension of the opening 14a refers to the diameter dimension of the circular opening, the side length dimension of the square opening or the polygonal opening of five or more sides. The longest diagonal size. Also, the shape of the opening 14a may be a rectangle, and the width of the rectangular opening is between 2 micrometers and 40 micrometers.

Referring to FIG. 1B, the present invention can optionally form a metal cap 18 on a pad 16 exposed by an opening 14a of the protective layer 14 to protect the pad 16 from oxidation. damage. The metal protective cover 18 includes, for example, a barrier layer on the pad 16 exposed by the opening 14a, and an aluminum-containing metal layer (eg, an aluminum layer, having a thickness of between 0.4 micrometers and 3 micrometers, An Al-Cu alloy layer or an Al-Si-Cu alloy layer is on the barrier layer, wherein the barrier layer is a titanium layer or a titanium layer. a tungsten alloy layer, a titanium nitride layer, a tantalum layer, a tantalum nitride layer, a chromium (Cr) layer or a nickel layer, and the like, and the thickness is between 0.01 micrometers and 0.5 micrometers. For example, when the material of the pad 16 mainly includes copper metal, the pad 16 usually has a metal protective cover 18, so that the pad 16 (or copper pad) mainly containing copper metal is protected from oxidation and erosion. The metal protective cover 18 includes, for example, a germanium-containing metal layer (for example, a germanium layer or a tantalum nitride layer) on the pad 16, and an aluminum-containing metal layer (for example, an aluminum layer or an aluminum alloy layer). Located on this ruthenium containing metal layer. The bottom portion is described with the absence of the metal protective cover 18 on the pad 16, and those skilled in the art can implement it by means of the following embodiments, with the metal protection cover 18 on the pad 16.

Thus, the related descriptions of the semiconductor substrate 2, the semiconductor device 4, the wiring structure 6, the dielectric layer 12, the protective layer 14, the pad 16 and the metal protective cover 18 are completed, and the structure 20 represents the protective layer in FIGS. 1A and 1B. The structure below, that is, the structure 20 includes the semiconductor substrate 2, the semiconductor element 4, the wiring structure 6 (including the metal layer 8 and the metal plug 10) and the dielectric layer 12 in FIGS. 1A and 1B.

First embodiment

2A to 2Q are schematic cross-sectional views showing a process of an embodiment of the present invention. In the present embodiment, the pad 16 is a metal layer (or aluminum pad) whose material mainly includes aluminum. However, those skilled in the art can use the pad 16 as a material mainly including copper metal by the following description. The layer (or referred to as a copper pad) is implemented in a manner that is implemented with a metal protective cover 18 above the pad 16.

Please refer to FIG. 2A to form a polymer layer 22 on the protective layer 14 and pass through the patterned polymer layer 22 to form at least one polymer layer opening 22a in the polymer layer 22 and At least one pad 16 is exposed. As shown in FIGS. 2B and 2C, the polymer layer opening 22a may expose a pad 16 and the polymer layer 22 also covers a portion of the pad 16 (as shown in FIG. 2B). As shown, either the polymer layer opening 22a exposes the entire upper surface of a pad 16 and exposes the upper surface of the protective layer 14 positioned around the pad 16 (as shown in FIG. 2C). Alternatively, the thickness of the polymer layer 22 is, for example, between 3 microns and 26 microns or between 3 microns and 25 microns.

In addition, the description of the second embodiment to the second embodiment of the present embodiment is described in such a manner that the polymer layer opening 22a exposes a pad 16 and the polymer layer 22 also covers a portion of the pad 16 . It can be implemented by exposing the entire upper surface of the pad 16 and exposing the upper surface of the protective layer 14 around the pad 16 with the polymer layer opening 22a by the following description.

The polymer layer 22 is, for example, selected from the group consisting of polyimide (PI), benzocyclobutane (BCB), polyurethane, epoxy resin, polyparaxylene polymer, and solder. One of a cover material, an elastomer, or a porous dielectric material. Further, the manner of forming the polymer layer 22 includes spin-on coating, lamination, or screen printing. Forming a polyiminoimine layer on the protective layer 14 and patterning the content of the polyimide layer as an example of forming and patterning the polymer layer 22, as those skilled in the art can use the following description It is based on other polymer materials such as phenylcyclobutene or epoxy resin.

For example, the manner in which the polymer layer 22 is formed and patterned is to first spin-coat a photosensitive thickness between 3 microns and 50 microns (preferably between 6 microns and 24 microns) using a spin coating process. (photo sensitive) the polyimide layer is on the protective layer 14, and then the polyimide layer is patterned by baking, exposure and development processes to form at least one opening. At least one pad 16 is exposed in the polyimide layer, and in the process of patterning the polyimide layer, for example, a one-time (1X) stepper or a double (1X) pair is used. A contact aligner exposes the polyimide layer. Finally, in a nitrogen atmosphere or an oxygen-free environment, the polyimide layer is hardened by a curing process at a temperature between 250 ° C and 400 ° C (the time of the hardening process is between 10 minutes and 200 minutes). The thickness of the hardened polyimide layer is between 3 microns and 26 microns. In addition, after hardening the polyimide layer, the plasma residue containing the oxygen ion (O ₂ plasma) or the plasma containing the fluoride ion concentration of less than 200 PPM and oxygen ions may be used to remove the polymer residue on the upper surface of the pad 16 or Other foreign objects.

Referring to FIG. 2D, after forming the polymer layer 22, a titanium-containing metal layer having a thickness of between 0.005 micrometers and 1 micrometer (preferably, a thickness of between 0.01 micrometers and 0.7 micrometers) is formed. 24 on the polymer layer 22 and above the pad 16 exposed by the polymer layer opening 22a, wherein the titanium-containing metal layer 24 is, for example, a titanium-tungsten alloy layer or a titanium nitride layer, and the formation includes sputtering. With chemical vapor deposition (CVD) and other methods.

For example, the titanium-containing metal layer 24 may be a titanium-tungsten alloy layer formed by sputtering to a thickness of between 0.1 micrometers and 1 micrometer (preferably having a thickness of between 0.3 micrometers and 0.5 micrometers). The material layer 22 and the polymer layer opening 22a are exposed to the material mainly comprising the aluminum pad 16; or the sputtering method is formed to a thickness of between 0.005 micrometers and 1 micrometer (the preferred thickness is a titanium-tungsten alloy layer between 0.01 μm and 0.7 μm on the polymer layer 22 and the material of the polymer layer opening 22a exposed to the main aluminum-containing pad 16; or, by sputtering Forming a titanium nitride layer having a thickness between 0.01 micrometers and 0.7 micrometers (preferably having a thickness between 0.01 micrometers and 0.2 micrometers or between 0.05 micrometers and 0.1 micrometers) in the polymer layer 22 The material exposed on the polymer layer opening 22a is mainly composed of the aluminum-containing pad 16; or the thickness formed by the chemical vapor deposition (CVD) method is between 0.005 micrometers and 0.1 micrometers (preferably thickness) a titanium nitride layer between 0.01 microns and 0.05 microns is on the polymer layer 22 and the polymer layer The main material 22a has exposed contact pads 16 of aluminum.

For example, the titanium-containing metal layer 24 may be a titanium-tungsten alloy layer formed by sputtering to a thickness of between 0.1 micrometers and 1 micrometer (preferably having a thickness of between 0.3 micrometers and 0.5 micrometers). The thickness of the layer 22 on the layer 22 opposite to the polymer layer opening 22a is mainly above the copper-containing pad 16; or the thickness formed by the sputtering method is between 0.005 micrometers and 1 micrometer (preferably, the thickness is a titanium-tungsten alloy layer between 0.01 micrometers and 0.7 micrometers is over the polymer layer 22 and the main material copper-containing pads 16 exposed by the polymer layer opening 22a; or, by sputtering Forming a titanium nitride layer having a thickness between 0.01 micrometers and 0.7 micrometers (preferably having a thickness between 0.01 micrometers and 0.2 micrometers or between 0.05 micrometers and 0.1 micrometers) in the polymer layer 22 The material exposed on the polymer layer opening 22a is mainly over the copper-containing pad 16; or the chemical vapor deposition (CVD) method is formed to a thickness of between 0.005 micrometers and 0.1 micrometers (preferably thickness) a titanium nitride layer between 0.01 μm and 0.05 μm on the polymer layer 22 and polymerized Layer exposed by the opening 22a of the material containing mainly copper pad 16 upward.

For example, the titanium-containing metal layer 24 may be a titanium-tungsten alloy layer formed by sputtering to a thickness of between 0.1 micrometers and 1 micrometer (preferably having a thickness of between 0.3 micrometers and 0.5 micrometers). The material layer 22 and the polymer layer opening 22a are exposed on an aluminum-containing metal layer above the copper-containing pad 16; or the thickness formed by sputtering is between 0.005 micrometers and 1 micrometer. a titanium-tungsten alloy layer between (between 0.01 and 0.7 micron) is on the polymer layer 22 and is exposed above the polymer layer opening 22a. On the aluminum-containing metal layer; or, the thickness formed by sputtering is between 0.01 micrometers and 0.7 micrometers (preferably, the thickness is between 0.01 micrometers and 0.2 micrometers or between 0.05 micrometers and 0.1 micrometers) The titanium nitride layer is on the polymer layer 22 and an aluminum-containing metal layer above the copper-containing pad 16 exposed by the polymer layer opening 22a; or by chemical vapor deposition The thickness of the (CVD) method is between 0.005 micrometers and 0.1 micrometers (the preferred thickness is between 0.01 micrometers) A titanium nitride layer of between meters and 0.05 microns is on the polymer layer 22 and an aluminum-containing metal layer over the pads 16 of the material primarily exposed to the polymer layer opening 22a.

In addition, the titanium-containing metal layer 24 may also be replaced by a tantalum nitride (TaN) layer, for example, by sputtering to a thickness of between 0.01 micrometers and 0.2 micrometers (preferably, the thickness is between 0.05 micrometers and 0.1 micrometers). a layer of tantalum nitride on the polymer layer 22 above the pad 16 exposed by the polymer layer opening 22a (for example, the polymer layer opening 22a is exposed to a material mainly comprising aluminum on the pad 16, polymerized The material exposed by the layer opening 22a is mainly composed of a copper-containing pad 16 or a material of the polymer layer opening 22a exposed by a copper-containing pad 16 (or an aluminum-containing metal layer); or, Phase deposition (CVD) to form a tantalum nitride layer having a thickness between 0.005 micrometers and 0.1 micrometers (preferably having a thickness between 0.01 micrometers and 0.05 micrometers) on the polymer layer 22 and opening the polymer layer 22a is exposed above the pad 16 (for example, the material exposed to the polymer layer opening 22a is mainly composed of the aluminum-containing pad 16, the polymer layer opening 22a is exposed to the material mainly containing the copper pad 16 or polymerized. The material exposed by the layer opening 22a is mainly composed of an aluminum-containing gold above the copper-containing pad 16. Floor).

Referring to FIG. 2E, a photoresist layer 26 is formed on the titanium-containing metal layer 24 by spin-on coating, and the photoresist layer 26 is patterned by exposure and development processes. To form a photoresist layer 26a on the titanium-containing metal layer 24 above the pads 16, as shown in FIG. 2F. In the process of patterning the photoresist layer 26, for example, exposure is performed by using a double (1X) stepper or a double (1X) contact aligner.

Referring to FIG. 2G, the titanium-containing metal layer 24 not under the photoresist layer 26a is removed, wherein the removal is performed by etching, for example, and the etching method includes dry etching and wet etching (wet). Etching), for example, by reactive ion etching (RIE) process etching to remove the titanium-containing metal layer 24 (such as a titanium-tungsten alloy layer or a titanium nitride layer) not under the photoresist layer 26a. ). Referring to FIG. 2H, after removing the titanium-containing metal layer 24 that is not under the photoresist layer 26a, the photoresist layer 26a is subsequently removed. In addition, after removing the photoresist layer 26a, it is optional to use a plasma (for example, a plasma containing oxygen ions or a plasma containing a fluoride ion concentration of less than 200 PPM and oxygen ions) to clean the photoresist residue on the upper surface of the titanium-containing metal layer 24. Things.

In addition, the structure shown in Fig. 2H can also be achieved in the following manner. First, a hard mask layer is formed on the titanium-containing metal layer 24, wherein the hard mask layer is, for example, a gold layer having a thickness of 1,000 angstroms. Then, spin-on coating forms a photoresist layer on the hard mask layer, and continues to pattern the photoresist layer through exposure and development processes to form a photoresist layer opening in the photoresist layer. A hard mask layer is exposed in the layer, wherein in the process of patterning the photoresist layer, for example, using a double (1X) stepper or a double (1X) contact aligner exposure. Then, the hard mask layer exposed by the opening of the photoresist layer is removed, wherein the removal method is removed by etching, for example, and the etching method includes dry etching and wet etching, for example, when the hard mask layer is a gold layer. The etchant containing iodine (such as an etchant containing potassium iodide) can be used to etch away the gold layer exposed by removing the opening of the photoresist layer. After removing the hard cap layer exposed by the opening of the photoresist layer, the photoresist layer is then removed to form a patterned hard cap layer on the titanium-containing metal layer 24 over the pads 16. Continuing, the titanium-containing metal layer 24 that is not under the patterned hard mask layer is removed, and the removal is performed, for example, by etching (including dry etching and wet etching), for example, when the titanium-containing metal layer 24 is a titanium-tungsten alloy layer. The titanium-containing metal layer 24 not under the patterned hard mask layer can be removed by a reactive ion etching (RIE) process or a solution containing hydrogen peroxide (H ₂ O ₂ ). Finally, the patterned hard mask layer is removed, and the removal method is removed by, for example, etching (including dry etching and wet etching). For example, when the hard mask layer is a gold layer, an ion milling process or an ion implantation process may be used. An etchant of iodine (for example, an etchant containing potassium iodide) is etched to remove the gold layer.

After completing the step of FIG. 2H, then in the environment containing nitrogen (N ₂ ) purity greater than 99% (preferably greater than 99.99%), the titanium-containing metal layer 24 (eg, titanium-tungsten alloy layer or titanium nitride) Layer) performing an annealing process in which the temperature of the tempering process is between 300 ° C and 410 ° C (preferably between 350 ° C and 400 ° C) and the tempering process is performed. The time is between 20 minutes and 150 minutes (the preferred time is between 50 minutes and 100 minutes). Thus, the titanium-containing metal layer 24 includes a surface layer containing one of nitrogen, and the thickness of the surface layer is less than 2,500 angstroms, for example, between 5 angstroms and 500 angstroms. That is, a surface layer of the titanium-containing metal layer 24 is a nitrogen-containing metal layer having a thickness of less than 2,500 angstroms (for example, between 5 angstroms and 500 angstroms), and the nitrogen-containing metal layer includes titanium (Ti). For example, when the titanium-containing metal layer 24 is a titanium-tungsten alloy layer, then the nitrogen-containing metal layer includes titanium and includes tungsten.

Referring to FIG. 2I, a titanium-containing metal layer 28 having a thickness of between 0.02 micrometers and 0.5 micrometers is formed on the polymer layer 22 and the titanium-containing metal layer 24, and the titanium-containing metal layer 28 is used as a sputtering layer. An adhesion layer that serves to provide a good adhesion between the titanium-containing metal layer 24 and the metal material. Further, the titanium-containing metal layer 28 is, for example, a titanium layer or a titanium-tungsten alloy layer, and the titanium-containing metal layer 28 may be formed by evaporation or the like. For example, the titanium-containing metal layer 28 may be a titanium layer sputtered on the polymer layer 22 and a tempered process of a titanium layer; or a titanium layer is sputtered on the polymer layer 22 and passed back. a titanium-tungsten alloy layer of a fire process; or a titanium layer is sputtered on the polymer layer 22 and a tempered titanium nitride layer; or a titanium layer is sputtered to form a polymer a layer 22 is formed with a tempering process of a tantalum nitride (TaN) layer; or a titanium-tungsten alloy layer is sputtered on the polymer layer 22 and a tempered process of a titanium layer; or, A titanium-tungsten alloy layer is sputtered on the polymer layer 22 and a tempering process of a titanium-tungsten alloy layer; or a titanium-tungsten alloy layer is sputter-deposited on the polymer layer 22 and a tempered process On the titanium nitride layer; or a titanium-tungsten alloy layer is sputtered on the polymer layer 22 and a tempered tantalum nitride (TaN) layer.

Continuing to refer to FIG. 2J, a metal layer 30 having a thickness between 0.05 micrometers and 0.3 micrometers is formed by sputtering on the titanium-containing metal layer 28, which serves as a conductive layer and a seed layer during plating ( Seed layer). Alternatively, the metal layer 30 may be formed by vapor deposition, physical vapor deposition, or electroless plating. Since the metal layer 30 can facilitate the formation of the subsequent metal layer, the material of the metal layer 30 may vary depending on the material of the subsequent metal layer, such as when the metal layer of gold is electroplated on the metal layer 30, the metal layer The material of 30 is preferably gold.

For example, when the titanium-containing metal layer 28 is formed by sputtering in a titanium layer having a thickness of between 0.02 micrometers and 0.5 micrometers, the metal layer 30 may be a gold having a thickness of between 0.05 micrometers and 0.3 micrometers. The layer is sputtered on the titanium layer; or, when the titanium-containing metal layer 28 is formed by sputtering, a titanium-tungsten alloy layer having a thickness of between 0.02 micrometers and 0.5 micrometers, the metal layer 30 may be thick. A gold layer between 0.05 microns and 0.3 microns is sputtered onto the titanium tungsten alloy layer.

Referring to FIG. 2K, a spin-on coating forms a photoresist layer 32 (eg, a positive-type photoresist layer) having a thickness between 3.5 micrometers and 30 micrometers. On the layer 30, next to the process shown in FIG. 2L, the photoresist layer 32 is patterned by exposure and development processes to form a photoresist layer opening 32a in the photoresist layer 32 and expose the metal. Layer 30. In the process of patterning the photoresist layer 32, for example, exposure is performed by using a double (1X) stepper or a double (1X) contact aligner. In addition, after the development, the metal layer 30 exposed by the photoresist layer opening 32a may be cleaned by using a plasma (for example, a plasma containing oxygen ions or a plasma containing a fluoride ion concentration of less than 200 PPM and oxygen ions) to remove the metal. A photoresist residue or other foreign matter on the upper surface of layer 30.

Referring to Figure 2M, a metal layer 34 having a thickness between 3 microns and 25 microns is formed by electroplating on the metal layer 30 exposed by the photoresist layer opening 32a. For example, a gold layer having a thickness of between 3 micrometers and 25 micrometers is formed by electroplating with a cyanide plating solution on the metal layer 30 of the gold material exposed by the photoresist layer opening 32a; or Electroplating solution containing gold (Au) and sulfite ion is used to form a metal layer having a thickness of between 3 micrometers and 25 micrometers and a gold layer exposed in the opening 32a of the photoresist layer. At 30, the concentration of gold in the plating solution is between 1 gram/liter (g/l) and 20 gram/liter (preferably between 5 gram/liter and 15 gram/liter), and further contains sulfite ions. The concentration is from 10 g / liter to 120 g / liter (preferably between 30 g / liter and 90 g / liter), and the plating solution is, for example, a solution of gold (Na ₃ Au(SO ₃ ) ₂ ) metal or ammonium sulfite _{((NH 4) 3 [Au} (SO 3) 2]) solution, which is plated operating parameters as follows: [1] a temperature of the plating solution is between 30 deg.] C to 70 ℃, more The temperature of the plating solution is between 45 ° C and 65 ° C. That is, when the temperature of the plating solution is between 30 ° C and 70 ° C (preferably between 45 ° C and 65 ° C), electroplating forms a metal layer exposed in the photoresist layer opening 32a. 30 on.

[2]. The current density is between 1 mA/cm ² to 10 mA/cm 2 , and the preferred current density is between 4 mA/cm 2 ( mA/cm ² ) to 6 mA/cm 2 .

[3]. The pH value of the plating solution is between 6 and 9, and the pH value of the plating solution is preferably between 7 and 8.5. That is, when the acid-base (pH) value of the plating solution is between 6 and 9 (preferably between 7 and 8.5), electroplating forms a metal layer exposed to the metal exposed in the photoresist layer opening 32a. On layer 30.

Referring to FIG. 2N, after the metal layer 34 is formed, the photoresist layer 32 is subsequently removed, and the photoresist layer 32 is removed by, for example, using an organic solvent containing an amide. In addition, after removing the photoresist layer 32, the metal layer 34 and the metal layer 30 may be cleaned by using a plasma (for example, a plasma containing oxygen ions or a plasma containing a fluoride ion concentration of less than 200 PPM and oxygen ions) to remove the metal. A photoresist residue on the upper surface of layer 30 and the upper surface of metal layer 34.

Continuing to refer to FIG. 2O, the metal layer 30 and the titanium-containing metal layer 28 that are not under the metal layer 34 are sequentially removed. The method for removing the metal layer 30 and the titanium-containing metal layer 28 not under the metal layer 34 is removed by etching, for example, and the etching method can be further divided into dry etching and wet etching, and the dry etching includes chemical electricity. Slurry etching, splash etching and chemical gas etching. For example, in the wet etching, when the titanium-containing metal layer 28 is a titanium-tungsten alloy, it can be removed by etching using a solution containing hydrogen peroxide, and when the titanium-containing metal layer 28 is titanium, it can be removed by etching using a solution containing cyanofluoric acid. When the metal layer 30 is gold, it can be removed by etching using an iodine-containing etching solution (for example, an etchant containing potassium iodide); in the dry etching, when the titanium-containing metal layer 28 is titanium or a titanium-tungsten alloy, chlorine can be used. The plasma etching is removed or removed by a reactive ion etching (RIE) process. When the metal layer 30 is gold, it can be removed by ion milling or by argon sputtering. Etching) process etching removal.

Thus, the present invention can form a metal trace 36 over the polymer layer 22 and over the pads 16, and the metal lines 36 are comprised of a titanium-containing metal layer 24 in the titanium-containing metal layer 24 (e.g., titanium tungsten). a titanium-containing metal layer 28 (such as a titanium-tungsten alloy layer or a titanium layer) on the alloy layer or the titanium nitride layer, a metal layer 30 on the titanium-containing metal layer 28, and a metal layer 30 (for example, a gold layer) A metal layer 34 (for example, a gold layer) is formed.

Referring to FIG. 2P, after removing the metal layer 30 and the titanium-containing metal layer 28 that are not under the metal layer 34, a polymer layer 38 may be selectively formed on the polymer layer 22 and the metal line 36. At least one polymer layer opening 38a on the metal layer 34 and located within the polymer layer 38 exposes the metal layer 34 of the metal line 36. Wherein, the polymer layer 38 is, for example, selected from the group consisting of polyimine, phenylcyclobutene, polyurethane, epoxy resin, polyparaxylene polymer, welding cap material, elastomer (elastomer) or porous media. One of the electrical materials, and the thickness of the polymer layer 38 is, for example, between 3 microns and 26 microns or between 3 microns and 25 microns, and the formation includes spin-on coating, Lamination or screen printing. Bottom to form a polyimine layer on the metal layer 34 and the polymer layer 22, and to pattern the content of the polyimide layer as an example of forming and patterning the polymer layer 38, but the skilled person It can be carried out in the form of other polymer materials (e.g., phenylcyclobutene or epoxy resin) by the following examples.

For example, the polymeric layer 38 is formed and patterned by spin coating a spin coating having a thickness between 3 microns and 50 microns (preferably between 6 microns and 24 microns). The polyimine layer is patterned on the metal layer 34 (for example, a gold layer) and the polymer layer 22, followed by a process of baking, exposing and developing a polyimine layer to form at least one opening in the polyfluorene layer. The metal layer 34 of the metal line 36 is exposed within the imide layer, and in the process of patterning the polyimide layer, for example, a double (1X) stepper or a double (1X) pair is utilized. A contact aligner exposes the polyimide layer. Finally, in a nitrogen atmosphere or an oxygen-free environment, the polyimide layer is hardened by a curing process at a temperature between 250 ° C and 400 ° C (the time of the hardening process is between 10 minutes and 200 minutes). The thickness of the hardened polyimide layer is between 3 microns and 26 microns. In addition, after hardening the polyimide layer, the plasma residue containing the oxygen ion (O ₂ plasma) or the plasma containing the fluoride ion concentration of less than 200 PPM and oxygen ions may be used to remove the polymer residue on the upper surface of the metal layer 34 or Other foreign objects.

Alternatively, the position of the metal line 36 exposed by the polymer layer opening 38a may be different from the position of the pads 16 to which the metal line 36 is connected, as viewed from a top perspective view.

After the step shown in the above FIG. 2P is completed, the present embodiment completes one of the semiconductor wafers formed by the above steps. Next, the semiconductor wafer is diced to form a plurality of integrated circuit (IC) wafers (or semiconductor wafers). Continuing to refer to FIG. 2Q, in this embodiment, one end of a wire conductor 40 (material including gold or copper) may be bonded to one of the polymer layer openings 38a of an IC chip by a wire bonding process. The exposed metal line 36 is on the metal layer 34, and the other end is connected to a lead of a leadframe or a pad, which may be one of the other semiconductor wafer pads. a pad above the other semiconductor substrate, a pad above the organic substrate, a pad above the ceramic substrate, a pad above the substrate, a pad above the glass substrate, or a soft board One of the upper pads, and the soft plate comprises a polymer layer having a thickness between 30 microns and 200 microns. In addition, the wire bonding strength used in the wire bonding process of the present invention is, for example, between 100 millinewtons (mN) and 1,000 millinewtons, between 200 millinewtons and 1,000 millinewtons, or between 200 millinewtons and 500 millimeters. Between Newton. Finally, after the wire bonding process shown in FIG. 2Q is completed, a polymer material such as epoxy resin or polyimide is formed to coat the wire bonding wires 40.

Alternatively, after the step shown in FIG. 2P is completed, a tin-containing metal layer having a thickness of between 1 micrometer and 500 micrometers is formed over the metal layer 34 exposed by the polymer layer opening 38a, which includes The tin metal layer preferably has a thickness between 3 microns and 250 microns, and the tin metal layer is formed by electroplating, electroless plating or screen printing. In addition, the tin-containing metal layer is, for example, a tin-lead alloy, a tin-silver alloy, a tin-silver-copper alloy or a lead-free alloy. . Therefore, a semiconductor wafer is formed by the above steps. Next, the semiconductor wafer is diced to form a plurality of integrated IC chips.

Referring to FIG. 2R, the embodiment may not form a polymer layer 22 on the protective layer 14 and directly form a thickness between 0.005 micrometers and 1 micrometer (preferably, the thickness is between 0.01 micrometers and 0.7 micrometers). A titanium-containing metal layer 24 between the micrometers is on the protective layer 14 and the pad 16 (the material mainly comprises aluminum or copper), that is, no 2A to 2B or 2A and 2C are not performed. For the steps shown in the figure, the steps described in the 2D to 2P drawings are directly performed. For details, refer to the descriptions of the above 2D to 2P, and the detailed description thereof will not be repeated here. Thus, a semiconductor wafer is formed by the above-described steps, followed by dicing the semiconductor wafer to form a plurality of integrated circuit (IC) wafers (or semiconductor wafers). Then, as shown in FIG. 2Q, after forming a plurality of integrated IC chips, one end of a wire bonding wire (material including gold or copper) is bonded to an IC chip by a wire bonding process. One of the polymer layer openings 38a is exposed on the metal layer 34 of the metal line 36, and the other end is connected to a lead of a lead frame or a pad. For details, please refer to the above 2Q diagram. Or a metal layer 34 formed by a tin-containing metal layer having a thickness between 1 micrometer and 500 micrometers (preferably having a thickness between 3 micrometers and 250 micrometers) in the polymer layer opening 38a. Above, the semiconductor wafer is then diced to form a plurality of integrated IC chips. For details, please refer to the above description, which will not be described in detail.

In addition, as described in the first paragraph of the embodiment, the above content can also be used in the case where the metal protection cover 18 is provided above the pad 16, as briefly described below. Referring to FIG. 2S, the polymer layer 22 is formed on the protective layer 14, and an opening 22a in the polymer layer 22 exposes the metal protective cover 18 on the pad 16 to form a polymer. The manner in which the layer 22 and the opening 22a are described can be referred to the contents of FIGS. 2A to 2C. The material of the pad 16 mainly includes copper (that is, the pad 16 is a copper pad), and the metal protection cover 18 includes a layer of a ruthenium-containing metal (for example, a layer of tantalum or a layer of tantalum nitride). A pad 16 and an aluminum-containing metal layer (e.g., an aluminum layer or an aluminum alloy layer) are positioned on the base metal-containing layer. Next, as described in FIGS. 2D-2H, a titanium-containing metal layer 24 (for example, one having a thickness of between 0.005 micrometers and 1 micrometer (preferably having a thickness of between 0.01 micrometers and 0.7 micrometers) is formed. The titanium tungsten alloy layer or the titanium nitride layer is on the aluminum-containing metal layer of the metal protective cover 18 exposed by the opening 22a. For details, refer to FIGS. 2D to 2H. Continuing, the steps described in Figures 2I through 2P are performed. Further, the semiconductor wafer is diced to form a plurality of integrated circuit (IC) wafers (or semiconductor wafers). Next, as shown in FIG. 2Q, a wire bonding process is used to bond one end of a wire conductor 40 (whose material includes gold or copper) to the metal exposed by the polymer layer opening 38a of one of the IC chip. The metal layer 34 of the line 36, and the other end is connected to an external circuit; or, a thickness of between 1 micrometer and 500 micrometers (preferably between 3 micrometers and 250 micrometers) The tin metal layer is over the metal layer 34 exposed by the polymer layer opening 38a, and then the semiconductor wafer is diced to form a plurality of integrated circuit chips (IC chip). For details, please refer to the above description, and the details are not added here. Narrative.

Moreover, in the case where a polymer layer 22 is not formed on the protective layer 14, the content of the present embodiment for the metal protective cover 18 above the pad 16 is briefly described as follows. Forming a titanium-containing metal layer 24 (eg, a titanium tungsten) having a thickness between 0.005 micrometers and 1 micrometer (preferably having a thickness between 0.01 micrometers and 0.7 micrometers) as described in FIGS. 2D-2H An alloy layer or a titanium nitride layer is on the aluminum-containing metal layer of the metal protective cover 18, wherein the metal protective cover 18 comprises a tantalum-containing metal layer (for example, a tantalum layer or a tantalum nitride layer). The pad 16 (i.e., the pad 16 is a copper pad) and an aluminum-containing metal layer (e.g., an aluminum layer or an aluminum alloy layer) are positioned thereon. Continuing, the steps described in Figures 2I through 2P are performed. Further, the semiconductor wafer is diced to form a plurality of integrated circuit (IC) wafers (or semiconductor wafers). Next, as shown in FIG. 2Q, a wire bonding process is used to bond one end of a wire conductor 40 (whose material includes gold or copper) to the metal exposed by the polymer layer opening 38a of one of the IC chip. a metal layer 34 of the line 36, and the other end is connected to an external circuit; or a tin containing a thickness of between 1 micrometer and 500 micrometers (preferably between 3 micrometers and 250 micrometers) The metal layer is over the metal layer 34 exposed by the polymer layer opening 38a, and then the semiconductor wafer is diced to form a plurality of integrated IC chips. For details, please refer to the above description, and the detailed description thereof will not be repeated here. .

Second embodiment

3A to 3I are schematic cross-sectional views showing a process of an embodiment of the present invention. In the present embodiment, the pad 16 is a metal layer (or aluminum pad) whose material mainly includes aluminum. However, those skilled in the art can use the pad 16 as a material mainly including copper metal by the following description. The layer (or referred to as a copper pad) is implemented in a manner that is implemented with a metal protective cover 18 above the pad 16.

Referring to FIG. 3A, after completing the step shown in FIG. 2P, a metal layer 42 having a thickness of between 0.02 μm and 0.5 μm is formed by sputtering on the polymer layer 38 and the polymer layer is opened. 38a is exposed on the metal layer 34 of the metal line 36, the metal layer 42 acts as an adhesion/barrier layer, and serves to provide a good adhesion between the metal layer 34 and the metal material, and A diffusion reaction between the metal layer 34 and the metal material is prevented. In addition, the material of the metal layer 42 is selected from titanium, tungsten, cobalt, nickel, titanium nitride, titanium tungsten alloy, nickel vanadium alloy, tantalum, tantalum nitride, chromium, copper, chromium copper alloy, gold, rhodium, platinum. At least one of palladium, rhodium, ruthenium, and silver, or a group of the same, and the metal layer 42 may be formed by vapor deposition or the like. For example, a titanium layer having a thickness of between 0.02 micrometers and 0.5 micrometers is sputtered onto the metal layer 34 of the polymer layer 38 and the gold layer exposed by the polymer layer opening 38a; or, sputtering is formed to a thickness A titanium-tungsten alloy layer between 0.02 microns and 0.5 microns is on the polymer layer 38 and the metal layer 34 of gold material exposed by the polymer layer opening 38a.

Referring to FIG. 3B, a metal layer 44 having a thickness of between 0.05 micrometers and 0.3 micrometers is formed by sputtering on the metal layer 42, which serves as a conductive layer and a seed layer during electroplating. Alternatively, the metal layer 44 may be formed by vapor deposition, physical vapor deposition, or electroless plating. Since the metal layer 44 can facilitate the formation of the subsequent metal layer, the material of the metal layer 44 varies with the material of the subsequent metal layer, such as when the metal layer formed of gold is formed on the metal layer 44 by electroplating, the metal layer The material of 44 is preferably gold; when the metal layer formed of copper is formed on the metal layer 44 by electroplating, the material of the metal layer 44 is preferably copper.

For example, when the metal layer 42 is formed by sputtering in a titanium layer having a thickness of between 0.02 micrometers and 0.5 micrometers, the metal layer 44 may be a gold layer splash having a thickness of between 0.05 micrometers and 0.3 micrometers. Plating on the titanium layer; or, when the metal layer 42 is formed by sputtering, a titanium-tungsten alloy layer having a thickness of between 0.02 micrometers and 0.5 micrometers, the metal layer 44 may have a thickness of 0.05 micrometers. a gold layer between 0.3 microns is sputtered onto the titanium tungsten alloy layer; or, when the metal layer 42 is formed by sputtering, a titanium layer having a thickness between 0.02 microns and 0.5 microns The metal layer 44 may be a copper layer having a thickness of between 0.05 micrometers and 0.3 micrometers sputtered on the titanium layer; or, when the metal layer 42 is formed by sputtering, the thickness is between 0.02 micrometers and 0.5 micrometers. When a titanium-tungsten alloy layer is interposed, the metal layer 44 may be a copper layer having a thickness of between 0.05 micrometers and 0.3 micrometers sputtered on the titanium-tungsten alloy layer.

Referring to FIG. 3C, a spin-on coating forms a photoresist layer 46 (eg, a positive photoresist layer) having a thickness between 3.5 microns and 30 microns in the metal layer 44 (eg, gold). On the layer or copper layer, then, as shown in FIG. 3D, the photoresist layer 46 is patterned through a process such as exposure and development to form a photoresist layer opening 46a in the photoresist layer 46 and expose the metal layer 44 ( For example, gold or copper). In the process of patterning the photoresist layer 46, for example, exposure is performed by using a double (1X) stepper or a double (1X) contact aligner. In addition, after development, the metal layer 44 (for example, a gold layer) exposed by the photoresist layer opening 46a may be cleaned by using a plasma (for example, a plasma containing oxygen ions or a plasma containing a fluoride ion concentration of less than 200 PPM and oxygen ions). Or a copper layer) to remove photoresist residues or other foreign matter on the upper surface of the metal layer 44.

Referring to Figure 3E, a metal layer 48 having a thickness between 3 microns and 25 microns is formed by electroplating on the metal layer 44 exposed by the photoresist layer opening 46a. For example, a gold layer having a thickness of between 3 micrometers and 25 micrometers is formed by electroplating with a cyanide plating solution on the metal layer 44 of the gold material exposed by the photoresist layer opening 46a; or A gold layer having a thickness of between 3 micrometers and 25 micrometers is formed by electroplating with a gold (Au) and sulfite ion to form a gold layer exposed in the photoresist layer opening 46a. At 44, the plating solution contains gold in a concentration ranging from 1 g/liter (g/l) to 20 g/liter (preferably between 5 g/liter and 15 g/liter), and further contains sulfite ions. The concentration is from 10 g / liter to 120 g / liter (preferably between 30 g / liter and 90 g / liter), and the plating solution is, for example, a solution of gold (Na ₃ Au(SO ₃ ) ₂ ) metal or ammonium sulfite _{((NH 4) 3 [Au} (SO 3) 2]) solution, which is plated operating parameters as follows: [1] a temperature of the plating solution is between 30 deg.] C to 70 ℃, more The temperature of the plating solution is between 45 ° C and 65 ° C. That is, when the temperature of the plating solution is between 30 ° C and 70 ° C (preferably between 45 ° C and 65 ° C), electroplating forms a metal layer exposed by the photoresist layer opening 46 a. 44.

[2]. The current density is between 1 mA/cm ² to 10 mA/cm 2 , and the preferred current density is between 4 mA/cm 2 ( mA/cm ² ) to 6 mA/cm 2 .

[3]. The pH value of the plating solution is between 6 and 9, and the pH value of the plating solution is preferably between 7 and 8.5. That is, when the acid-base (pH) value of the plating solution is between 6 and 9 (preferably between 7 and 8.5), plating forms a metal layer exposed to the metal in the photoresist layer opening 46a. On layer 44.

Alternatively, the metal layer 48 may be formed by plating a copper layer on the metal layer 44 of the copper material exposed by the photoresist layer opening 46a, plating a nickel layer on the copper layer, and plating a gold layer or electroless plating. Formed on this nickel layer.

Referring to FIG. 3F, after the metal layer 48 is formed, the photoresist layer 46 is subsequently removed, for example, by removing the photoresist layer 46 by using an organic solvent containing an amide. In addition, after removing the photoresist layer 46, the metal layer 48 (eg, gold layer) and the metal layer may be cleaned first by using a plasma such as a plasma containing oxygen ions or a plasma containing a fluoride ion concentration of less than 200 PPM and oxygen ions. 44 (for example, a gold layer or a copper layer) to remove photoresist residues on the upper surface of the metal layer 48 and the upper surface of the metal layer 44.

Continuing to refer to FIG. 3G, the metal layer 44 and the metal layer 42 that are not under the metal layer 48 are sequentially removed. Wherein, the manner of removing the metal layer 44 (eg, a gold layer or a copper layer) not under the metal layer 48 (eg, a gold layer) and the metal layer 42 (eg, a titanium layer or a titanium-tungsten alloy layer) is removed, for example, by etching. The etching method can be further divided into dry etching and wet etching, and dry etching includes chemical plasma etching, splash etching and chemical gas etching. For example, in the wet etching, when the metal layer 42 is a titanium-tungsten alloy, it can be removed by etching using a solution containing hydrogen peroxide, and when the metal layer 42 is titanium, it can be removed by etching using a solution containing cyanofluoric acid, and the metal layer is additionally used. When 44 is gold, it can be removed by etching using an iodine-containing etching solution (for example, an etching solution containing potassium iodide). When the material of the metal layer 44 is copper, it can be removed by etching using an etching solution containing ammonium hydroxide (NH ₄ OH); In the dry etching, when the metal layer 42 is titanium or titanium tungsten alloy, it may be removed by plasma etching using chlorine or by reactive ion etching (RIE) process etching, and when the metal layer 44 is gold, Etching is removed using an ion milling process or by an Ar sputtering etching process.

Therefore, the present invention can form a metal line 50 on the polymer layer 38 and the metal layer 34 (for example, a gold layer) exposed by the polymer layer opening 38a, and the metal line 50 is formed by a metal layer 42. A metal layer 44 on the metal layer 42 (e.g., a titanium layer or a titanium tungsten alloy layer) is formed with a metal layer 48 on the metal layer 44.

Referring to FIG. 3H, after removing the metal layer 44 and the metal layer 42 not under the metal layer 48, the metal layer of the polymer layer 52 on the polymer layer 38 and the metal line 50 may be selectively formed. At least one of the polymer layer openings 52a located in the polymer layer 52 exposes the metal layer 48 of the metal line 50. The polymer layer 52 is, for example, selected from the group consisting of polyimine, phenylcyclobutene, polyurethane, epoxy resin, polyparaxylene polymer, solder mask material, elastomer (elastomer) or porous media. One of the electrical materials, and the thickness of the polymer layer 52 is, for example, between 3 microns and 26 microns or between 3 microns and 25 microns, and the formation includes spin-on coating, Lamination or screen printing. Bottom to form a polyimine layer on the metal layer 48 and the polymer layer 38, and to pattern the content of the polyimide layer as an example of forming and patterning the polymer layer 52, but the skilled person It can be carried out in the form of other polymer materials (e.g., phenylcyclobutene or epoxy resin) by the following examples.

For example, the manner in which the polymer layer 52 is formed and patterned is to first spin-coat a photosensitive thickness between 6 microns and 52 microns (preferably between 6 microns and 24 microns) using a spin coating process. The polyimide layer is patterned on the metal layer 48 and the polymer layer 38, and then sequentially patterned by baking, exposing and developing to form at least one opening in the polyimide layer. The metal layer 48 of the metal line 50 is exposed in the amine layer, and in the process of patterning the polyimide layer, for example, a one-time (1X) stepper or one-time (1X) alignment is utilized. A contact aligner exposes the polyimide layer. Finally, in a nitrogen atmosphere or an oxygen-free environment, the polyimide layer is hardened by a curing process at a temperature between 250 ° C and 400 ° C (the time of the hardening process is between 10 minutes and 200 minutes). The thickness of the hardened polyimide layer is between 3 microns and 26 microns. In addition, after hardening the polyimide layer, the polymer residue containing the oxygen ion (O ₂ plasma) or the plasma containing the fluoride ion concentration of less than 200 PPM and oxygen ions may be used to remove the polymer residue on the upper surface of the metal layer 48 or Other foreign objects.

Alternatively, the position of the metal layer 48 exposed by the polymer layer opening 52a may be different from the location of the metal layer 34 exposed by the polymer layer opening 38a, as viewed from a top perspective view.

After completing the steps shown in FIG. 3H above, this embodiment completes one of the semiconductor wafers formed by the above steps. Next, the semiconductor wafer is diced to form a plurality of integrated circuit (IC) wafers (or semiconductor wafers). Referring to FIG. 3I, in this embodiment, one end of a wire conductor 54 (the material of which includes gold or copper) is bonded to the polymer layer opening 52a of one of the integrated circuit chips (IC chip) by a wire bonding process. The metal layer 48 of the metal line 50 is formed on the metal layer 48 (for example, a gold layer), and the other end is connected to a lead of a lead frame or a pad. The pad may be another semiconductor chip. One of the pads, one of the pads above the other semiconductor substrate, one of the pads above the organic substrate, one of the pads above the ceramic substrate, one of the pads above the substrate, and one of the pads above the glass substrate Or a pad above a soft board, and the board includes a polymer layer having a thickness between 30 microns and 200 microns. Finally, after the wire bonding process shown in FIG. 31 is completed, a polymer material such as epoxy resin or polyimide is formed to coat the wire bonding wires 54.

Alternatively, after completing the step shown in FIG. 3H above, a metal layer 48 (eg, a gold layer) exposed by the tin-containing metal layer having a thickness between 1 micrometer and 500 micrometers at the polymer layer opening 52a is formed. Above, the tin-containing metal layer preferably has a thickness between 3 microns and 250 microns, and the tin-containing metal layer is formed by electroplating, electroless plating or screen printing. In addition, the tin-containing metal layer is, for example, a tin-lead alloy, a tin-silver alloy, a tin-silver-copper alloy or a lead-free alloy. . Therefore, a semiconductor wafer is formed by the above steps. Next, the semiconductor wafer is diced to form a complex integrated circuit (IC) wafer.

Referring to FIG. 3J, the embodiment may not form a polymer layer 22 on the protective layer 14 and directly form a thickness between 0.005 micrometers and 1 micrometer (preferably, the thickness is between 0.01 micrometers and 0.7 micrometers). A titanium-containing metal layer 24 (for example, a titanium-tungsten alloy layer or a titanium nitride layer) on the protective layer 14 and the pad 16 (whose material mainly includes aluminum or copper), that is, no 2A Go to the steps shown in FIG. 2B or FIGS. 2A and 2C, and directly perform the steps described in FIGS. 2D to 2P and FIGS. 3A to 3H. For details, refer to the above description. No more detailed description. Thus, a semiconductor wafer is formed by the above-described steps, followed by dicing the semiconductor wafer to form a plurality of integrated circuit (IC) wafers (or semiconductor wafers). Then, as shown in FIG. 3I, after forming a plurality of integrated IC chips, one end of a wire bonding wire (material including gold or copper) is bonded to an IC chip by a wire bonding process. One of the metal layer 48 of the metal line 50 exposed by the polymer layer opening 52a (for example, a gold layer), and the other end is connected to a lead of a lead frame or a pad. Referring to the description of FIG. 3I above; or forming a tin-containing metal layer having a thickness between 1 micrometer and 500 micrometers above the metal layer 48 (eg, a gold layer) exposed by the polymer layer opening 52a, followed by cutting The semiconductor wafer is formed to form a plurality of integrated circuit chips (IC chip). For details, please refer to the above description, which will not be described in detail herein.

In addition, as described in the first paragraph of the embodiment, the above content can also be applied to the case where the metal protection cover 18 is provided above the pad 16, and the content thereof is briefly described as follows. Referring to FIG. 3K, the polymer layer 22 is formed on the protective layer 14, and an opening 22a in the polymer layer 22 exposes the metal protective cover 18 on the pad 16 to form a polymer. The manner in which the layer 22 and the opening 22a are described can be referred to the contents of FIGS. 2A to 2C. The material of the pad 16 mainly includes copper (that is, the pad 16 is a copper pad), and the metal protection cover 18 includes a layer of a ruthenium-containing metal (for example, a layer of tantalum or a layer of tantalum nitride). A pad 16 and an aluminum-containing metal layer (e.g., an aluminum layer or an aluminum alloy layer) are positioned on the base metal-containing layer. Next, as described in FIGS. 2D-2H, a titanium-containing metal layer 24 (for example, one having a thickness of between 0.005 micrometers and 1 micrometer (preferably having a thickness of between 0.01 micrometers and 0.7 micrometers) is formed. The titanium tungsten alloy layer or the titanium nitride layer is on the aluminum-containing metal layer of the metal protective cover 18 exposed by the opening 22a. For details, refer to FIGS. 2D to 2H. Continuing, the steps described in FIGS. 2I to 2P and FIGS. 3A to 3H are performed. Further, the semiconductor wafer is diced to form a plurality of integrated circuit (IC) wafers (or semiconductor wafers). Next, as shown in FIG. 3I, a wire bonding process is used to bond one end of a wire conductor 54 (the material of which includes gold or copper) to the metal exposed by the polymer layer opening 52a of one of the IC chip. The metal layer 48 of the line 50, and the other end is connected to an external circuit; or a tin containing a thickness of between 1 micrometer and 500 micrometers (preferably between 3 micrometers and 250 micrometers) The metal layer is over the metal layer 48 exposed by the polymer layer opening 52a, and then the semiconductor wafer is diced to form a plurality of integrated IC chips. For details, please refer to the above description, and the detailed description thereof will not be repeated here. .

Moreover, in the case where a polymer layer 22 is not formed on the protective layer 14, the content of the present embodiment for the metal protective cover 18 above the pad 16 is briefly described as follows. Forming a titanium-containing metal layer 24 (eg, a titanium tungsten) having a thickness between 0.005 micrometers and 1 micrometer (preferably having a thickness between 0.01 micrometers and 0.7 micrometers) as described in FIGS. 2D-2H An alloy layer or a titanium nitride layer is on the aluminum-containing metal layer of the metal protective cover 18, wherein the metal protective cover 18 comprises a tantalum-containing metal layer (for example, a tantalum layer or a tantalum nitride layer). The pad 16 (i.e., the pad 16 is a copper pad) and an aluminum-containing metal layer (e.g., an aluminum layer or an aluminum alloy layer) are positioned thereon. Continuing, the steps described in FIGS. 2I to 2P and FIGS. 3A to 3H are performed. Further, the semiconductor wafer is diced to form a plurality of integrated circuit (IC) wafers (or semiconductor wafers). Next, as shown in FIG. 3I, a wire bonding process is used to bond one end of a wire conductor 54 (the material of which includes gold or copper) to the metal exposed by the polymer layer opening 52a of one of the IC chip. The metal layer 48 of the line 50, and the other end is connected to an external circuit; or a tin containing a thickness of between 1 micrometer and 500 micrometers (preferably between 3 micrometers and 250 micrometers) The metal layer is over the metal layer 48 exposed by the polymer layer opening 52a, and then the semiconductor wafer is diced to form a plurality of integrated IC chips. For details, please refer to the above description, and the detailed description thereof will not be repeated here. .

Third embodiment

4A to 4I are schematic cross-sectional views showing a process of an embodiment of the present invention. In the present embodiment, the pad 16 is a metal layer (or aluminum pad) whose material mainly includes aluminum. However, those skilled in the art can use the pad 16 as a material mainly including copper metal by the following description. The layer (or referred to as a copper pad) is implemented in a manner that is implemented with a metal protective cover 18 above the pad 16.

After completing the step shown in FIG. 2D, then in the environment containing nitrogen (N ₂ ) purity greater than 99% (preferably greater than 99.99%), the titanium-containing metal layer 24 (eg, titanium-tungsten alloy layer or nitrogen) The titanium layer) is subjected to an annealing process in which the temperature of the tempering process is between 300 ° C and 410 ° C (preferably between 350 ° C and 400 ° C) and tempering The process time is between 20 minutes and 150 minutes (the preferred time is between 50 minutes and 100 minutes). Thus, the titanium-containing metal layer 24 includes a surface layer containing one of nitrogen, and the thickness of the surface layer is less than 2,500 angstroms, for example, between 5 angstroms and 500 angstroms. That is, a surface layer of the titanium-containing metal layer 24 is a nitrogen-containing metal layer having a thickness of less than 2,500 angstroms (for example, between 5 angstroms and 500 angstroms), and the nitrogen-containing metal layer includes titanium (Ti). For example, when the titanium-containing metal layer 24 is a titanium-tungsten alloy layer, then the nitrogen-containing metal layer includes titanium and includes tungsten.

Continuing to refer to FIG. 4A, a titanium-containing metal layer 28 having a thickness of between 0.02 micrometers and 0.5 micrometers is formed on the titanium-containing metal layer 24, and the titanium-containing metal layer 28 serves as an adhesion layer. ), the role of which is to provide a good adhesion between the titanium-containing metal layer 24 and the metal material. Alternatively, the titanium-containing metal layer 28 may be a titanium layer or a titanium-tungsten alloy layer, and the titanium-containing metal layer 28 may also be formed by evaporation or the like. For example, the titanium-containing metal layer 28 may be a titanium layer sputtered on a titanium layer that has been subjected to a tempering process; or a titanium layer is sputtered on a titanium-tungsten alloy layer that has been subjected to a tempering process; a titanium layer is sputtered on a titanium nitride layer subjected to a tempering process; or a titanium layer is sputtered to form a tantalum nitride (TaN) layer in a tempering process; or a titanium tungsten The alloy layer is sputtered on a titanium layer which is subjected to a tempering process; or a titanium-tungsten alloy layer is sputtered on a titanium-tungsten alloy layer which is subjected to a tempering process; or a titanium-tungsten alloy layer is sputtered. Formed on a titanium nitride layer subjected to a tempering process; or a titanium-tungsten alloy layer is sputtered to form a tantalum nitride (TaN) layer in a tempering process.

Referring to FIG. 4B, a metal layer 30 having a thickness of between 0.05 μm and 0.3 μm is formed by sputtering on the titanium-containing metal layer 28, which serves as a conductive layer and a seed layer during plating. Layer). Alternatively, the metal layer 30 may be formed by vapor deposition, physical vapor deposition, or electroless plating. Since the metal layer 30 can facilitate the formation of the subsequent metal layer, the material of the metal layer 30 may vary depending on the material of the subsequent metal layer, such as when the metal layer formed of gold is formed on the metal layer 30 by electroplating, the metal layer The material of 30 is preferably gold.

For example, when the titanium-containing metal layer 28 is formed by sputtering in a titanium layer having a thickness of between 0.02 micrometers and 0.5 micrometers, the metal layer 30 may be a gold having a thickness of between 0.05 micrometers and 0.3 micrometers. The layer is sputtered on the titanium layer; or, when the titanium-containing metal layer 28 is formed by sputtering, a titanium-tungsten alloy layer having a thickness of between 0.02 micrometers and 0.5 micrometers, the metal layer 30 may be thick. A gold layer between 0.05 microns and 0.3 microns is sputtered onto the titanium tungsten alloy layer.

Referring to FIG. 4C, a photoresist layer 32 (such as a positive photoresist layer) having a thickness between 3.5 micrometers and 30 micrometers is formed on the metal layer 30, followed by spin-on coating. Referring to FIG. 4D, the photoresist layer 32 is patterned by exposure and development processes to form a photoresist layer opening 32a in the photoresist layer 32 and expose the metal layer 30 (eg, a gold layer). In the process of patterning the photoresist layer 32, for example, exposure is performed by using a double (1X) stepper or a double (1X) contact aligner. In addition, after the development, the metal layer 30 exposed by the photoresist layer opening 32a may be cleaned by using a plasma (for example, a plasma containing oxygen ions or a plasma containing a fluoride ion concentration of less than 200 PPM and oxygen ions) to remove the metal. A photoresist residue or other foreign matter on the upper surface of layer 30.

Referring to Figure 4E, a metal layer 34 having a thickness between 3 microns and 25 microns is formed by electroplating on the metal layer 30 exposed by the photoresist layer opening 32a. For example, a gold layer having a thickness of between 3 micrometers and 25 micrometers is formed by electroplating with a cyanide plating solution on the metal layer 30 of the gold material exposed by the photoresist layer opening 32a; or Electroplating solution containing gold (Au) and sulfite ion is used to form a metal layer having a thickness of between 3 micrometers and 25 micrometers and a gold layer exposed in the opening 32a of the photoresist layer. At 30, the concentration of gold in the plating solution is between 1 gram/liter (g/l) and 20 gram/liter (preferably between 5 gram/liter and 15 gram/liter), and further contains sulfite ions. The concentration is from 10 g / liter to 120 g / liter (preferably between 30 g / liter and 90 g / liter), and the plating solution is, for example, a solution of gold (Na ₃ Au(SO ₃ ) ₂ ) Or ammonium sulfite gold ((NH ₄ ) ₃ [Au(SO ₃ ) ₂ ])), the operating parameters when electroplating are: [1]. The temperature of the plating solution is between 30 ° C and 70 ° C, The temperature of the plating solution is between 45 ° C and 65 ° C. That is, when the temperature of the plating solution is between 30 ° C and 70 ° C (preferably between 45 ° C and 65 ° C), electroplating forms a metal layer exposed in the photoresist layer opening 32a. 30 on.

[2]. The current density is between 1 mA/cm ² to 10 mA/cm 2 , and the preferred current density is between 4 mA/cm 2 ( mA/cm ² ) to 6 mA/cm 2 .

[3]. The pH value of the plating solution is between 6 and 9, and the pH value of the plating solution is preferably between 7 and 8.5. That is, when the acid-base (pH) value of the plating solution is between 6 and 9 (preferably between 7 and 8.5), electroplating forms a metal layer exposed to the metal exposed in the photoresist layer opening 32a. On layer 30.

Referring to FIG. 4F, after the metal layer 34 is formed, the photoresist layer 32 is subsequently removed, and the photoresist layer 32 is removed by, for example, using an organic solvent containing an amino compound. In addition, after removing the photoresist layer 32, the metal layer 34 (eg, gold layer) and the metal layer may be cleaned first by using a plasma such as a plasma containing oxygen ions or a plasma containing a fluoride ion concentration of less than 200 PPM and oxygen ions. 30 (for example, a gold layer) by which the photoresist residue on the upper surface of the metal layer 30 and the upper surface of the metal layer 34 is removed.

Continuing to refer to FIG. 4G, the metal layer 30, the titanium-containing metal layer 28, and the titanium-containing metal layer 24 that are not under the metal layer 34 are sequentially removed. Wherein, a metal layer 30 (eg, a gold layer), a titanium-containing metal layer 28 (eg, a titanium layer or a titanium-tungsten alloy layer), and a titanium-containing metal layer 24 (eg, a titanium-tungsten alloy) that are not under the metal layer 34 (eg, a gold layer) are removed. The method of layer or titanium nitride layer is removed by etching, for example, dry etching and wet etching, and dry etching includes chemical plasma etching, splash etching and chemical gas etching. For example, in the wet etching, when the titanium-containing metal layer 28 and the titanium-containing metal layer 24 are titanium-tungsten alloy, the solution may be removed by using a solution containing hydrogen peroxide, and when the titanium-containing metal layer 28 is titanium, the cerium-containing fluorine may be used. The acid solution is removed by etching, and when the metal layer 30 is gold, it can be removed by etching using an iodine-containing etching solution (for example, an etching solution containing potassium iodide); in the dry etching, when the titanium-containing metal layer 28 is titanium or titanium tungsten alloy When it is removed by plasma etching using chlorine or by reactive ion etching (RIE) process etching, when the titanium-containing metal layer 24 is titanium tungsten alloy or titanium nitride, reactive ion etching (RIE) can be utilized. The process etching is removed. When the metal layer 30 is gold, it may be removed by an ion milling process or by an Ar sputtering etching process.

Thus, the present invention can form a metal line 56 over the polymer layer 22 and over the pads 16, and the metal lines 56 are from a titanium-containing metal layer 24, in the titanium-containing metal layer 24 (e.g., a titanium-tungsten alloy layer or nitrogen). a titanium-containing metal layer 28 (such as a titanium layer or a titanium-tungsten alloy layer) on the titanium layer), a metal layer 30 (such as a gold layer) on the titanium-containing metal layer 28, and a layer on the metal layer 30 A metal layer 34 (for example, a gold layer) is formed.

Referring to FIG. 4H, in this embodiment, after removing the metal layer 30, the titanium-containing metal layer 28, and the titanium-containing metal layer 24 that are not under the metal layer 34, a polymer layer 38 may be selectively formed on the metal layer 34. At least one polymer layer opening 38a on the polymer layer 22 and located in the polymer layer 38 exposes a metal layer 34 (e.g., a gold layer) of the metal line 56. Wherein, the polymer layer 38 is, for example, selected from the group consisting of polyimine, phenylcyclobutene, polyurethane, epoxy resin, polyparaxylene polymer, welding cap material, elastomer (elastomer) or porous media. One of the electrical materials, and the thickness of the polymer layer 38 is, for example, between 3 microns and 26 microns or between 3 microns and 25 microns, and the formation includes spin-on coating, Lamination or screen printing. Bottom to form a polyimine layer on the metal layer 34 and the polymer layer 22, and to pattern the content of the polyimide layer as an example of forming and patterning the polymer layer 38, but the skilled person It can be carried out in the form of other polymer materials (e.g., phenylcyclobutene or epoxy resin) by the following examples.

For example, the polymeric layer 38 is formed and patterned by spin coating a spin coating having a thickness between 3 microns and 50 microns (preferably between 6 microns and 24 microns). The polyimine layer is patterned on the metal layer 34 (for example, a gold layer) and the polymer layer 22, followed by a process of baking, exposing and developing a polyimine layer to form at least one opening in the polyfluorene layer. The metal layer 34 of the metal line 56 is exposed within the imide layer, and in the process of patterning the polyimide layer, for example, a one-time (1X) stepper or a double (1X) pair is utilized. A contact aligner exposes the polyimide layer. Finally, in a nitrogen atmosphere or an oxygen-free environment, the polyimide layer is hardened by a curing process at a temperature between 250 ° C and 400 ° C (the time of the hardening process is between 10 minutes and 200 minutes). The thickness of the hardened polyimide layer is between 3 microns and 26 microns. In addition, after hardening the polyimide layer, the plasma residue containing the oxygen ion (O ₂ plasma) or the plasma containing the fluoride ion concentration of less than 200 PPM and oxygen ions may be used to remove the polymer residue on the upper surface of the metal layer 34 or Other foreign objects.

Alternatively, the position of the metal layer 34 exposed by the polymer layer opening 38a may be different from the location of the pads 16 to which the metal line 56 is connected, as viewed from a top perspective view.

After completing the steps shown in FIG. 4H above, this embodiment completes one of the semiconductor wafers formed by the above steps. Next, the semiconductor wafer is diced to form a plurality of integrated circuit (IC) wafers (or semiconductor wafers). Continuing to refer to FIG. 4I, in this embodiment, one end of a wire bonding wire 40 (whose material includes gold or copper) may be bonded to a polymer layer opening 38a of an integrated circuit chip (IC chip) by a wire bonding process. The exposed metal line 56 is on the metal layer 34, and the other end is connected to a lead of a leadframe or a pad, which may be one of the other semiconductor wafer pads. a pad above the other semiconductor substrate, a pad above the organic substrate, a pad above the ceramic substrate, a pad above the substrate, a pad above the glass substrate, or a soft board One of the upper pads, and the soft plate comprises a polymer layer having a thickness between 30 microns and 200 microns. Finally, after the wire bonding process shown in FIG. 4I is completed, a polymer material such as epoxy resin or polyimide is formed to coat the wire bonding wires 40.

Alternatively, after completing the step shown in FIG. 4H above, a metal layer 34 (eg, a gold layer) exposed by the tin-containing metal layer having a thickness between 1 micrometer and 500 micrometers at the polymer layer opening 38a is formed. Above, the tin-containing metal layer preferably has a thickness between 3 microns and 250 microns, and the tin-containing metal layer is formed by electroplating, electroless plating or screen printing. In addition, the tin-containing metal layer is, for example, a tin-lead alloy, a tin-silver alloy, a tin-silver-copper alloy or a lead-free alloy. . Therefore, a semiconductor wafer is formed by the above steps. Next, the semiconductor wafer is diced to form a complex integrated circuit (IC) wafer.

Referring to FIG. 4J, the embodiment may not form a polymer layer 22 on the protective layer 14 and directly form a thickness between 0.005 micrometers and 1 micrometer (preferably, the thickness is between 0.01 micrometers and 0.7 micrometers). A titanium-containing metal layer 24 between the micrometers is directly on the protective layer 14 and the pad 16, that is, without performing the steps shown in FIGS. 2A to 2B or 2A and 2C. For the steps described in FIG. 2D and FIGS. 4A to 4H, please refer to the descriptions of FIG. 2D and FIGS. 4A to 4H for details, and the detailed description thereof will not be repeated here. Thus, a semiconductor wafer is formed by the above-described steps, followed by dicing the semiconductor wafer to form a plurality of integrated circuit (IC) wafers (or semiconductor wafers). Then, as shown in FIG. 4I, after forming a plurality of integrated IC chips, one end of a wire bonding wire (material including gold or copper) is bonded to an IC chip by a wire bonding process. One of the polymer layer openings 38a is exposed on the metal layer 34 of the metal line 56, and the other end is connected to a lead of a lead frame or a pad. For details, please refer to the above figure 4I. Or a metal layer 34 formed by a tin-containing metal layer having a thickness between 1 micrometer and 500 micrometers (preferably having a thickness between 3 micrometers and 250 micrometers) in the polymer layer opening 38a. Above, the semiconductor wafer is then diced to form a plurality of integrated IC chips. For details, please refer to the above description, which will not be described in detail.

In addition, as described in the first paragraph of the embodiment, the above content can also be used in the case where the metal protection cover 18 is provided above the pad 16, as briefly described below. Referring to FIG. 4K, the polymer layer 22 is formed on the protective layer 14, and an opening 22a in the polymer layer 22 exposes the metal protective cover 18 on the pad 16 to form a polymer. The manner in which the layer 22 and the opening 22a are described can be referred to the contents of FIGS. 2A to 2C. The material of the pad 16 mainly includes copper (that is, the pad 16 is a copper pad), and the metal protection cover 18 includes a layer of a ruthenium-containing metal (for example, a layer of tantalum or a layer of tantalum nitride). A pad 16 and an aluminum-containing metal layer (e.g., an aluminum layer or an aluminum alloy layer) are positioned on the base metal-containing layer. Next, as described in FIG. 2D, a titanium-containing metal layer 24 (eg, a titanium-tungsten alloy layer) having a thickness between 0.005 micrometers and 1 micrometer (preferably having a thickness between 0.01 micrometers and 0.7 micrometers) is formed. Or a titanium nitride layer) on the polymer layer 22 and the aluminum-containing metal layer of the metal protective cover 18 exposed by the opening 22a, as described in FIG. 2D. Continuing, the steps described in Figures 4A through 4H are performed. Further, the semiconductor wafer is diced to form a plurality of integrated circuit (IC) wafers (or semiconductor wafers). Next, as shown in FIG. 4I, a wire bonding process is used to bond one end of a wire conductor 40 (the material of which includes gold or copper) to the metal exposed by the polymer layer opening 38a of one of the IC chip. a metal layer 34 of the line 56, and the other end is connected to an external circuit; or a tin-containing layer having a thickness of between 1 micrometer and 500 micrometers (preferably having a thickness between 3 micrometers and 250 micrometers) The metal layer is over the metal layer 34 exposed by the polymer layer opening 38a, and then the semiconductor wafer is diced to form a plurality of integrated IC chips. For details, please refer to the above description, and the detailed description thereof will not be repeated here. .

Moreover, in the case where a polymer layer 22 is not formed on the protective layer 14, the content of the present embodiment for the metal protective cover 18 above the pad 16 is briefly described as follows. As shown in FIG. 2D, a titanium-containing metal layer 24 (eg, a titanium-tungsten alloy layer or a layer having a thickness between 0.005 micrometers and 1 micrometer (preferably having a thickness between 0.01 micrometers and 0.7 micrometers) is formed. The titanium nitride layer is on the protective layer 14 and the aluminum-containing metal layer of the metal protective cover 18, wherein the metal protective cover 18 comprises a germanium-containing metal layer (for example, a germanium layer or a tantalum nitride layer). The copper pad 16 (i.e., the pad 16 is a copper pad) and an aluminum-containing metal layer (e.g., an aluminum layer or an aluminum alloy layer) are disposed thereon. Continuing, the steps described in Figures 4A through 4H are performed. Further, the semiconductor wafer is diced to form a plurality of integrated circuit (IC) wafers (or semiconductor wafers). Next, as shown in FIG. 4I, a wire bonding process is used to bond one end of a wire conductor 40 (the material of which includes gold or copper) to the metal exposed by the polymer layer opening 38a of one of the IC chip. a metal layer 34 of the line 56, and the other end is connected to an external circuit; or a tin-containing layer having a thickness of between 1 micrometer and 500 micrometers (preferably having a thickness between 3 micrometers and 250 micrometers) The metal layer is over the metal layer 34 exposed by the polymer layer opening 38a, and then the semiconductor wafer is diced to form a plurality of integrated IC chips. For details, please refer to the above description, and the detailed description thereof will not be repeated here. .

Fourth embodiment

5A to 5I are schematic cross-sectional views showing a process of an embodiment of the present invention. In the present embodiment, the pad 16 is a metal layer (or aluminum pad) whose material mainly includes aluminum. However, those skilled in the art can use the pad 16 as a material mainly including copper metal by the following description. The layer (or referred to as a copper pad) is implemented in a manner that is implemented with a metal protective cover 18 above the pad 16.

Referring to FIG. 5A, after completing the step shown in FIG. 4H, a metal layer 42 having a thickness of between 0.02 μm and 0.5 μm is formed by sputtering on the polymer layer 38 and the polymer layer is opened. 38a is exposed on the metal layer 34 of the metal line 56, the metal layer 42 acts as an adhesion/barrier layer, and serves to provide a good adhesion between the metal layer 34 and the metal material, and A diffusion reaction between the metal layer 34 and the metal material is prevented. In addition, the material of the metal layer 42 is selected from titanium, tungsten, cobalt, nickel, titanium nitride, titanium tungsten alloy, nickel vanadium alloy, tantalum, tantalum nitride, chromium, copper, chromium copper alloy, gold, rhodium, platinum. At least one of palladium, rhodium, ruthenium, and silver, or a group of the same, and the metal layer 42 may be formed by vapor deposition or the like. For example, a titanium layer having a thickness of between 0.02 micrometers and 0.5 micrometers is sputtered onto the metal layer 34 of the polymer layer 38 and the gold layer exposed by the polymer layer opening 38a; or, sputtering is formed to a thickness A titanium-tungsten alloy layer between 0.02 microns and 0.5 microns is on the polymer layer 38 and the metal layer 34 of gold material exposed by the polymer layer opening 38a.

Referring to FIG. 5B, a metal layer 44 having a thickness of between 0.05 micrometers and 0.3 micrometers is formed on the metal layer 42 as a conductive layer and a seed layer during electroplating. Alternatively, the metal layer 44 may be formed by vapor deposition, physical vapor deposition, or electroless plating. Since the metal layer 44 can facilitate the formation of the subsequent metal layer, the material of the metal layer 44 varies with the material of the subsequent metal layer, such as when the metal layer formed of gold is formed on the metal layer 44 by electroplating, the metal layer The material of 44 is preferably gold; when the metal layer formed of copper is formed on the metal layer 44 by electroplating, the material of the metal layer 44 is preferably copper.

For example, when the metal layer 42 is formed by sputtering in a titanium layer having a thickness of between 0.02 micrometers and 0.5 micrometers, the metal layer 44 may be a gold layer splash having a thickness of between 0.05 micrometers and 0.3 micrometers. Plating on the titanium layer; or, when the metal layer 42 is formed by sputtering, a titanium-tungsten alloy layer having a thickness of between 0.02 micrometers and 0.5 micrometers, the metal layer 44 may have a thickness of 0.05 micrometers. a gold layer between 0.3 microns is sputtered onto the titanium tungsten alloy layer; or, when the metal layer 42 is formed by sputtering, a titanium layer having a thickness between 0.02 microns and 0.5 microns The metal layer 44 may be a copper layer having a thickness of between 0.05 micrometers and 0.3 micrometers sputtered on the titanium layer; or, when the metal layer 42 is formed by sputtering, the thickness is between 0.02 micrometers and 0.5 micrometers. When a titanium-tungsten alloy layer is interposed, the metal layer 44 may be a copper layer having a thickness of between 0.05 micrometers and 0.3 micrometers sputtered on the titanium-tungsten alloy layer.

Referring to FIG. 5C, a spin-on coating forms a photoresist layer 46 (such as a positive photoresist layer) having a thickness between 3.5 microns and 30 microns in the metal layer 44 (eg, gold). On the layer or the copper layer, then, as shown in FIG. 5D, the photoresist layer 46 is patterned through a process such as exposure and development to form a photoresist layer opening 46a in the photoresist layer 46 and expose the metal layer 44 ( For example, gold or copper). In the process of patterning the photoresist layer 46, for example, exposure is performed by using a double (1X) stepper or a double (1X) contact aligner. In addition, after development, the metal layer 44 (for example, a gold layer) exposed by the photoresist layer opening 46a may be cleaned by using a plasma (for example, a plasma containing oxygen ions or a plasma containing a fluoride ion concentration of less than 200 PPM and oxygen ions). Or a copper layer) to remove photoresist residues or other foreign matter on the upper surface of the metal layer 44.

Referring to Figure 5E, a metal layer 48 having a thickness between 3 microns and 25 microns is formed by electroplating on the metal layer 44 exposed by the photoresist layer opening 46a. For example, a gold layer having a thickness of between 3 micrometers and 25 micrometers is formed by electroplating with a cyanide plating solution on the metal layer 44 of the gold material exposed by the photoresist layer opening 46a; or A gold layer having a thickness of between 3 micrometers and 25 micrometers is formed by electroplating with a gold (Au) and sulfite ion to form a gold layer exposed in the photoresist layer opening 46a. At 44, the plating solution contains gold in a concentration ranging from 1 g/liter (g/l) to 20 g/liter (preferably between 5 g/liter and 15 g/liter), and further contains sulfite ions. The concentration is from 10 g / liter to 120 g / liter (preferably between 30 g / liter and 90 g / liter), and the plating solution is, for example, a solution of gold (Na ₃ Au(SO ₃ ) ₂ ) Or ammonium sulfite gold ((NH ₄ ) ₃ [Au(SO ₃ ) ₂ ])), the operating parameters when electroplating are: [1]. The temperature of the plating solution is between 30 ° C and 70 ° C, The temperature of the plating solution is between 45 ° C and 65 ° C. That is, when the temperature of the plating solution is between 30 ° C and 70 ° C (preferably between 45 ° C and 65 ° C), electroplating forms a metal layer exposed by the photoresist layer opening 46 a. 44.

[2]. The current density is between 1 mA/cm ² to 10 mA/cm 2 , and the preferred current density is between 4 mA/cm 2 ( mA/cm ² ) to 6 mA/cm 2 .

[3]. The pH value of the plating solution is between 6 and 9, and the pH value of the plating solution is preferably between 7 and 8.5. That is, when the acid-base (pH) value of the plating solution is between 6 and 9 (preferably between 7 and 8.5), plating forms a metal layer exposed to the metal in the photoresist layer opening 46a. On layer 44.

Alternatively, the metal layer 48 may be formed by plating a copper layer on the metal layer 44 of the copper material exposed by the photoresist layer opening 46a, plating a nickel layer on the copper layer, and plating a gold layer or electroless plating. Formed on this nickel layer.

Referring to FIG. 5F, after the metal layer 48 is formed, the photoresist layer 46 is subsequently removed, and the photoresist layer 46 is removed by, for example, using an organic solvent containing an amide. In addition, after removing the photoresist layer 46, the metal layer 48 (eg, gold layer) and the metal layer may be cleaned first by using a plasma such as a plasma containing oxygen ions or a plasma containing a fluoride ion concentration of less than 200 PPM and oxygen ions. 44 (for example, a gold layer or a copper layer) to remove photoresist residues on the upper surface of the metal layer 48 and the upper surface of the metal layer 44.

Continuing to refer to FIG. 5G, the metal layer 44 and the metal layer 42 that are not under the metal layer 48 are sequentially removed. Wherein, the manner of removing the metal layer 44 (eg, a gold layer or a copper layer) not under the metal layer 48 (eg, a gold layer) and the metal layer 42 (eg, a titanium layer or a titanium-tungsten alloy layer) is removed, for example, by etching. The etching method can be further divided into dry etching and wet etching, and dry etching includes chemical plasma etching, splash etching and chemical gas etching. For example, in the wet etching, when the metal layer 42 is a titanium-tungsten alloy, it can be removed by etching using a solution containing hydrogen peroxide, and when the metal layer 42 is titanium, it can be removed by etching using a solution containing cyanofluoric acid, and the metal layer is additionally used. When 44 is gold, it can be removed by etching using an iodine-containing etching solution (for example, an etching solution containing potassium iodide). When the material of the metal layer 44 is copper, it can be removed by etching using an etching solution containing ammonium hydroxide (NH ₄ OH); In the dry etching, when the metal layer 42 is titanium or titanium tungsten alloy, it may be removed by plasma etching using chlorine or by reactive ion etching (RIE) process etching, and when the metal layer 44 is gold, Etching is removed using an ion milling process or by an Ar sputtering etching process.

Therefore, the present invention can form a metal line 50 on the polymer layer 38 and the metal layer 34 (for example, a gold layer) exposed by the polymer layer opening 38a, and the metal line 50 is formed by a metal layer 42. A metal layer 44 on the metal layer 42 (e.g., a titanium layer or a titanium tungsten alloy layer) is formed with a metal layer 48 on the metal layer 44.

Referring to FIG. 5H, after removing the metal layer 44 and the metal layer 42 not under the metal layer 48, a polymer layer 52 may be selectively formed on the metal layer 48 and the polymer layer 38, and At least one polymer layer opening 52a in the polymer layer 52 exposes the metal layer 48 of the metal line 50. The polymer layer 52 is, for example, selected from the group consisting of polyimine, phenylcyclobutene, polyurethane, epoxy resin, polyparaxylene polymer, solder mask material, elastomer (elastomer) or porous media. One of the electrical materials, and the thickness of the polymer layer 52 is, for example, between 3 microns and 26 microns or between 3 microns and 25 microns, and the formation includes spin-on coating, Lamination or screen printing. Bottom to form a polyimine layer on the metal layer 48 and the polymer layer 38, and to pattern the content of the polyimide layer as an example of forming and patterning the polymer layer 52, but the skilled person It can be carried out in the form of other polymer materials (e.g., phenylcyclobutene or epoxy resin) by the following examples.

For example, the manner in which the polymer layer 52 is formed and patterned is to first spin-coat a photosensitive thickness between 6 microns and 52 microns (preferably between 6 microns and 24 microns) using a spin coating process. The polyimide layer is patterned on the metal layer 48 (for example, a metal layer containing gold) and the polymer layer 38, and then sequentially patterned by baking, exposing and developing to form at least one layer. Opening in the polyimide layer and exposing the metal layer 48 of the metal line 50, and in the process of patterning the polyimide layer, for example, using a double (1X) stepper or double ( The contact aligner of 1X) exposes the polyimide layer. Finally, in a nitrogen atmosphere or an oxygen-free environment, the polyimide layer is hardened by a curing process at a temperature between 250 ° C and 400 ° C (the time of the hardening process is between 10 minutes and 200 minutes). The thickness of the hardened polyimide layer is between 3 microns and 26 microns. In addition, after hardening the polyimide layer, the polymer residue containing the oxygen ion (O ₂ plasma) or the plasma containing the fluoride ion concentration of less than 200 PPM and oxygen ions may be used to remove the polymer residue on the upper surface of the metal layer 48 or Other foreign objects.

Alternatively, the position of the metal layer 48 exposed by the polymer layer opening 52a may be different from the location of the metal layer 34 exposed by the polymer layer opening 38a, as viewed from a top perspective view.

After completing the steps shown in FIG. 5H above, this embodiment completes one of the semiconductor wafers formed by the above steps. Next, the semiconductor wafer is diced to form a plurality of integrated circuit (IC) wafers (or semiconductor wafers). Referring to FIG. 5I, the present embodiment can utilize a wire bonding process to expose one end of a wire conductor 54 (whose material including gold or copper) to a polymer layer opening 52a of one of the integrated IC chips. The metal layer 48 of the metal line 50 is connected, and the other end is connected to a lead of a leadframe or a pad, which may be a pad of another semiconductor chip, a pad above the other semiconductor substrate, a pad above the organic substrate, a pad above the ceramic substrate, a pad above the substrate, a pad above the glass substrate or a soft board One of the pads, and the flexible board comprises a polymer layer having a thickness of between 30 microns and 200 microns. Finally, after the wire bonding process shown in FIG. 5I is completed, a polymer material such as epoxy resin or polyimide is formed to coat the wire bonding wires 54.

Alternatively, after the step shown in FIG. 5H is completed, a tin-containing metal layer having a thickness of between 1 micrometer and 500 micrometers is formed over the metal layer 48 exposed by the polymer layer opening 52a, which includes The tin metal layer preferably has a thickness between 3 microns and 250 microns, and the tin metal layer is formed by electroplating, electroless plating or screen printing. In addition, the tin-containing metal layer is, for example, a tin-lead alloy, a tin-silver alloy, a tin-silver-copper alloy or a lead-free alloy. . Therefore, a semiconductor wafer is formed by the above steps. Next, the semiconductor wafer is diced to form a complex integrated circuit (IC) wafer.

Referring to FIG. 5J, the embodiment may not form a polymer layer 22 on the protective layer 14 and directly form a thickness between 0.005 micrometers and 1 micrometer (preferably, the thickness is between 0.01 micrometers and 0.7 micrometers). A titanium-containing metal layer 24 between the micrometers is on the protective layer 14 and the pad 16 (the material mainly comprises aluminum or copper), that is, no 2A to 2B or 2A and 2C are not performed. The steps shown in the figure, and the steps described in the 2D, 4A, 4H, and 5A to 5H are directly performed. For details, refer to the above description, and the detailed description thereof will not be repeated here. Thus, a semiconductor wafer is formed by the above-described steps, followed by dicing the semiconductor wafer to form a plurality of integrated circuit (IC) wafers (or semiconductor wafers). Then, as shown in FIG. 5J, after forming a plurality of integrated circuit chips (IC chips), one end of a wire bonding wire (material including gold or copper) is bonded to an IC chip by a wire bonding process. One of the polymer layer openings 52a is exposed on the metal layer 48 of the metal line 50, and the other end is connected to a lead of a lead frame or a pad. For details, please refer to the above figure 5I. Or a tin-containing metal layer having a thickness between 1 micrometer and 500 micrometers is formed over the metal layer 48 exposed by the polymer layer opening 52a, and then the semiconductor wafer is diced to form a complex integrated circuit. For the details of the IC chip, please refer to the above description, which will not be described in detail here.

In addition, as described in the first paragraph of the embodiment, the above content can also be applied to the case where the metal protection cover 18 is provided above the pad 16, and the content thereof is briefly described as follows. Referring to FIG. 5K, the polymer layer 22 is formed on the protective layer 14, and an opening 22a in the polymer layer 22 exposes the metal protective cover 18 on the pad 16 to form a polymer. The manner in which the layer 22 and the opening 22a are described can be referred to the contents of FIGS. 2A to 2C. The material of the pad 16 mainly includes copper (that is, the pad 16 is a copper pad), and the metal protection cover 18 includes a layer of a ruthenium-containing metal (for example, a layer of tantalum or a layer of tantalum nitride). A pad 16 and an aluminum-containing metal layer (e.g., an aluminum layer or an aluminum alloy layer) are positioned on the base metal-containing layer. Next, as described in FIG. 2D, a titanium-containing metal layer 24 (eg, a titanium-tungsten alloy layer) having a thickness between 0.005 micrometers and 1 micrometer (preferably having a thickness between 0.01 micrometers and 0.7 micrometers) is formed. Or a titanium nitride layer) on the polymer layer 22 and the aluminum-containing metal layer of the metal protective cover 18 exposed by the opening 22a, as described in FIG. 2D. Continuing, the steps described in FIGS. 4A to 4H and FIGS. 5A to 5H are performed. Further, the semiconductor wafer is diced to form a plurality of integrated circuit (IC) wafers (or semiconductor wafers). Next, as shown in FIG. 5I, a wire bonding process is used to bond one end of a wire conductor 54 (the material of which includes gold or copper) to the metal exposed by the polymer layer opening 52a of one of the IC chip. The metal layer 48 of the line 50, and the other end is connected to an external circuit; or a tin containing a thickness of between 1 micrometer and 500 micrometers (preferably between 3 micrometers and 250 micrometers) The metal layer is over the metal layer 48 exposed by the polymer layer opening 52a, and then the semiconductor wafer is diced to form a plurality of integrated IC chips. For details, please refer to the above description, and the detailed description thereof will not be repeated here. .

Moreover, in the case where a polymer layer 22 is not formed on the protective layer 14, the content of the present embodiment for the metal protective cover 18 above the pad 16 is briefly described as follows. As shown in FIG. 2D, a titanium-containing metal layer 24 (eg, a titanium-tungsten alloy layer or a layer having a thickness between 0.005 micrometers and 1 micrometer (preferably having a thickness between 0.01 micrometers and 0.7 micrometers) is formed. The titanium nitride layer is on the protective layer 14 and the aluminum-containing metal layer of the metal protective cover 18, wherein the metal protective cover 18 comprises a germanium-containing metal layer (for example, a germanium layer or a tantalum nitride layer). The copper pad 16 (i.e., the pad 16 is a copper pad) and an aluminum-containing metal layer (e.g., an aluminum layer or an aluminum alloy layer) are disposed thereon. Continuing, the steps described in FIGS. 4A to 4H and FIGS. 5A to 5H are performed. Further, the semiconductor wafer is diced to form a plurality of integrated circuit (IC) wafers (or semiconductor wafers). Next, as shown in FIG. 5I, a wire bonding process is used to bond one end of a wire conductor 54 (the material of which includes gold or copper) to the metal exposed by the polymer layer opening 52a of one of the IC chip. The metal layer 48 of the line 50, and the other end is connected to an external circuit; or a tin containing a thickness of between 1 micrometer and 500 micrometers (preferably between 3 micrometers and 250 micrometers) The metal layer is over the metal layer 48 exposed by the polymer layer opening 52a, and then the semiconductor wafer is diced to form a plurality of integrated IC chips. For details, please refer to the above description, and the detailed description thereof will not be repeated here. .

The above description of the embodiments of the present invention is intended to be understood by those skilled in the art, and the invention may be practiced without departing from the scope of the invention. Equivalent modifications or modifications made by the spirit of the invention should still be included in the scope of the claims described below.

2. . . Semiconductor substrate

4. . . Semiconductor component

6. . . Line structure

8. . . Metal layer

10. . . Metal plug

12. . . Dielectric layer

14. . . The protective layer

14a. . . Opening

16. . . Pad

18. . . Metal protection cover

20. . . structure

twenty two. . . Polymer layer

22a. . . Polymer layer opening

twenty four. . . Titanium-containing metal layer

26. . . Photoresist layer

26a. . . Photoresist layer

28. . . Titanium-containing metal layer

30. . . Metal layer

32. . . Photoresist layer

32a. . . Photoresist layer opening

34. . . Metal layer

36. . . Metal line

38. . . Polymer layer

38a. . . Polymer layer opening

40. . . Wire thread

42. . . Metal layer

44. . . Metal layer

46. . . Photoresist layer

46a. . . Photoresist layer opening

48. . . Metal layer

50. . . Metal line

52. . . Polymer layer

52a. . . Polymer layer opening

54. . . Wire thread

56. . . Metal line

Schematic description:

1A and 1B are schematic cross-sectional views of a wafer, respectively.

2A to 2S are schematic cross-sectional views showing a process according to an embodiment of the present invention.

3A to 3K are schematic cross-sectional views showing a process according to an embodiment of the present invention.

4A to 4K are schematic cross-sectional views showing a process according to an embodiment of the present invention.

5A to 5K are schematic cross-sectional views showing a process according to an embodiment of the present invention.

14. . . The protective layer

14a. . . Opening

16. . . Pad

18. . . Metal protection cover

20. . . structure

twenty two. . . Polymer layer

22a. . . Polymer layer opening

twenty four. . . Titanium-containing metal layer

28. . . Titanium-containing metal layer

30. . . Metal layer

34. . . Metal layer

38. . . Polymer layer

38a. . . Polymer layer opening

42. . . Metal layer

44. . . Metal layer

48. . . Metal layer

52. . . Polymer layer

52a. . . Polymer layer opening

Claims (89)

An integrated circuit chip comprising: a semiconductor substrate; a dielectric layer over the semiconductor substrate; a first metal layer over the dielectric layer; a protective layer over the first metal layer, wherein The opening is located in the protective layer and above a pad region of the first metal layer; a first titanium-containing metal layer is located on the pad region; and an aluminum-containing metal layer is disposed on the first titanium-containing metal layer And a second titanium-containing metal layer above the aluminum-containing metal layer; an adhesive layer on the second titanium-containing metal layer, wherein the adhesive layer is made of metal; and a second a metal layer on the adhesive layer. The integrated circuit chip of claim 1, wherein the semiconductor substrate comprises germanium. The integrated circuit chip of claim 1, further comprising a metal oxide semiconductor (MOS) device connected to the first metal layer. The integrated circuit chip of claim 1, wherein the material of the first metal layer mainly comprises aluminum. The integrated circuit chip of claim 1, wherein the material of the first metal layer mainly comprises copper. The integrated circuit chip of claim 1, further comprising a barrier layer located under the bottom of the first metal layer and outside the sidewall. The integrated circuit chip of claim 6, wherein the material of the barrier layer comprises germanium. The integrated circuit chip of claim 1, wherein the protective layer comprises a silicon oxide, a silicon nitride or a silicon oxynitride. The integrated circuit chip of claim 1, wherein the protective layer has a thickness of between 0.3 micrometers and 1.5 micrometers. The integrated circuit chip of claim 1, wherein the first titanium-containing metal layer has a thickness of between 0.01 micrometers and 0.5 micrometers. The integrated circuit chip according to claim 1, wherein the first titanium-containing metal layer is a titanium layer, a titanium-tungsten alloy layer or a titanium nitride layer. The integrated circuit wafer of claim 1, wherein the second titanium-containing metal layer has a thickness of between 0.005 micrometers and 1 micrometer. The integrated circuit chip of claim 1, wherein the second titanium-containing metal layer is a titanium-tungsten alloy layer or a titanium nitride layer. The integrated circuit chip of claim 1, wherein the adhesive layer has a thickness of between 0.02 micrometers and 0.5 micrometers. The integrated circuit chip of claim 1, wherein the second metal layer comprises a gold layer. The integrated circuit chip of claim 1, further comprising a third metal layer on the second metal layer, wherein the third metal layer has a thickness of between 3 micrometers and 25 micrometers. The integrated circuit chip of claim 16, wherein the third metal layer comprises gold. The integrated circuit chip according to claim 1, wherein the aluminum-containing metal layer is an aluminum layer, an aluminum-copper alloy (Al-Cu alloy) layer or an aluminum-bismuth-copper alloy (Al-Si). -Cu alloy) layer. The integrated circuit chip of claim 1, further comprising a polymer layer on the protective layer, the polymer layer contacting an upper surface of the protective layer, the adhesive layer being further located on the polymer layer, The adhesive layer contacts the upper surface of the polymer layer, and the second metal layer is also located above the polymer layer. The integrated circuit chip of claim 1, further comprising a polymer layer on the protective layer and above the second titanium-containing metal layer, the polymer layer contacting the upper surface of the protective layer. The integrated circuit wafer of claim 20, wherein the polymer layer has a thickness of between 3 microns and 25 microns. The integrated circuit chip of claim 1, further comprising a tin-containing metal layer above the second metal layer. The integrated circuit chip according to claim 22, wherein the tin-containing metal layer comprises a tin-lead alloy, a tin-silver alloy, and a tin-silver alloy. -copper alloy) or lead-free alloy. The integrated circuit chip of claim 1, further comprising an inductor above the semiconductor substrate and under the protective layer. An integrated circuit chip comprising: a semiconductor substrate; a dielectric layer over the semiconductor substrate; a first metal layer over the dielectric layer; a protective layer is disposed above the first metal layer, wherein an opening is located in the protective layer and above a pad region of the first metal layer; a second metal layer is located on the pad region; a metal layer on the second metal layer and over the pad region; a first titanium-containing metal layer on the aluminum-containing metal layer; and a second titanium-containing metal layer on the first titanium-containing metal layer And a third metal layer on the second titanium-containing metal layer. The integrated circuit chip of claim 25, wherein the semiconductor substrate comprises germanium. The integrated circuit chip of claim 25, further comprising a metal oxide semiconductor (MOS) device connected to the first metal layer. The integrated circuit chip of claim 25, wherein the material of the first metal layer mainly comprises copper. The integrated circuit chip of claim 25, further comprising a barrier layer located under the bottom of the first metal layer and outside the sidewall. The integrated circuit chip of claim 29, wherein the material of the barrier layer comprises germanium. The integrated circuit wafer of claim 25, wherein the protective layer comprises an oxonium compound, a hydrazine compound or a oxynitride compound. The integrated circuit chip of claim 25, wherein the protective layer has a thickness of between 0.3 micrometers and 1.5 micrometers. The integrated circuit chip of claim 25, wherein the second metal layer is a germanium-containing metal layer. The integrated circuit wafer according to claim 33, wherein the ruthenium-containing metal layer is a tantalum layer or a tantalum nitride layer. The integrated circuit wafer of claim 25, wherein the first titanium-containing metal layer has a thickness of between 0.005 micrometers and 1 micrometer. The integrated circuit chip according to claim 25, wherein the first titanium-containing metal layer is a titanium-tungsten alloy layer or a titanium nitride layer. The integrated circuit wafer of claim 25, wherein the second titanium-containing metal layer has a thickness of between 0.02 micrometers and 0.5 micrometers. The integrated circuit chip of claim 25, wherein the second titanium-containing metal layer is a titanium layer or a titanium-tungsten alloy layer. The integrated circuit chip of claim 25, wherein the third metal layer comprises a gold layer. The integrated circuit chip of claim 25, further comprising a fourth metal layer on the third metal layer, wherein the fourth metal layer has a thickness of between 3 micrometers and 25 micrometers. The integrated circuit wafer of claim 40, wherein the fourth metal layer comprises gold. The integrated circuit chip of claim 25, wherein the aluminum-containing metal layer is an aluminum layer or an aluminum alloy layer. The integrated circuit chip of claim 25, further comprising a polymer layer on the protective layer, the polymer layer contacting an upper surface of the protective layer, the second titanium-containing metal layer being further located in the polymerization On the object layer, the second titanium-containing metal layer contacts the upper surface of the polymer layer, and the third metal layer further Located above the polymer layer. The integrated circuit chip of claim 25, further comprising a polymer layer on the protective layer and above the first titanium-containing metal layer, the polymer layer contacting the upper surface of the protective layer. The integrated circuit chip of claim 25, further comprising a tin-containing metal layer above the third metal layer. The integrated circuit wafer according to claim 45, wherein the tin-containing metal layer comprises a tin-lead alloy, a tin-silver alloy, a tin-silver-copper alloy or a lead-free alloy. The integrated circuit chip of claim 25, further comprising an inductor above the semiconductor substrate and under the protective layer. An integrated circuit chip comprising: a semiconductor substrate; a dielectric layer over the semiconductor substrate; a first metal layer over the dielectric layer; a protective layer over the first metal layer, wherein The opening is located in the protective layer and above a pad region of the first metal layer; a second metal layer is located on the pad region; an aluminum-containing metal layer is located on the second metal layer and the pad Above the region; a titanium-containing metal layer on the aluminum-containing metal layer; a polymer layer on the protective layer and contacting the upper surface of the protective layer; an adhesive layer on the titanium-containing metal layer and located Polymer layer And contacting the upper surface of the titanium-containing metal layer and the upper surface of the polymer layer, wherein the adhesive layer is made of a metal; and a tin-containing metal layer is located above the adhesive layer. The integrated circuit chip of claim 48, wherein the semiconductor substrate comprises germanium. The integrated circuit chip of claim 48, further comprising a metal oxide semiconductor (MOS) device connected to the first metal layer. The integrated circuit chip of claim 48, wherein the material of the first metal layer mainly comprises copper. The integrated circuit chip of claim 48, further comprising a barrier layer located under the bottom of the first metal layer and outside the sidewall. The integrated circuit chip of claim 52, wherein the material of the barrier layer comprises germanium. The integrated circuit wafer according to claim 48, wherein the protective layer comprises an oxonium compound, a cerium compound or a oxynitride compound. The integrated circuit wafer of claim 48, wherein the protective layer has a thickness of between 0.3 micrometers and 1.5 micrometers. The integrated circuit chip of claim 48, wherein the second metal layer is a germanium-containing metal layer. The integrated circuit wafer according to claim 56, wherein the ruthenium-containing metal layer is a tantalum layer or a tantalum nitride layer. The integrated circuit wafer of claim 48, wherein the titanium-containing metal layer has a thickness of between 0.005 micrometers and 1 micrometer. An integrated circuit chip as described in claim 48, wherein The titanium-containing metal layer is a titanium tungsten alloy layer or a titanium nitride layer. The integrated circuit wafer of claim 48, wherein the adhesive layer has a thickness of between 0.02 micrometers and 0.5 micrometers. The integrated circuit chip of claim 48, wherein the adhesive layer comprises titanium. The integrated circuit chip of claim 48, wherein the aluminum-containing metal layer is an aluminum layer or an aluminum alloy layer. The integrated circuit chip of claim 48, wherein the tin-containing metal layer comprises a tin-lead alloy, a tin-silver alloy, a tin-silver-copper alloy or a lead-free alloy. The integrated circuit chip of claim 48, further comprising an inductor above the semiconductor substrate and under the protective layer. The integrated circuit chip of claim 48, further comprising an electroplated metal layer between the adhesive layer and the tin-containing metal layer. An integrated circuit wafer process includes the steps of: providing a semiconductor substrate, a dielectric layer, a first metal layer, and a protective layer, wherein the dielectric layer is over the semiconductor substrate, and the first metal layer is located at the dielectric layer Above the electrical layer, the protective layer is located on the first metal layer, and an opening in the protective layer exposes a pad region of the first metal layer; forming a second metal layer exposed in the opening Forming an aluminum-containing metal layer on the second metal layer and over the pad region; Forming a titanium-containing metal layer on the aluminum-containing metal layer; forming an adhesive layer on the titanium-containing metal layer; and forming a third metal layer on the adhesive layer. The integrated circuit wafer process of claim 66, wherein the semiconductor substrate comprises germanium. The integrated circuit wafer process of claim 66, wherein the protective layer comprises an oxonium compound, a hydrazine compound or a oxynitride compound. The integrated circuit wafer process of claim 66, wherein the protective layer has a thickness between 0.3 microns and 1.5 microns. The integrated circuit wafer process of claim 66, wherein the forming of the first metal layer comprises an electroplating process. The integrated circuit wafer process of claim 66, wherein the material of the first metal layer mainly comprises copper. The integrated circuit wafer process of claim 66, wherein the second metal layer is a germanium-containing metal layer. The integrated circuit wafer process of claim 72, wherein the germanium-containing metal layer is a germanium layer or a tantalum nitride layer. The integrated circuit wafer process of claim 66, wherein the aluminum-containing metal layer is an aluminum layer or an aluminum alloy layer. The integrated circuit wafer process of claim 66, wherein the titanium-containing metal layer has a thickness of between 0.005 micrometers and 1 micrometer. As described in claim 66, the integrated circuit wafer system The step of forming the titanium-containing metal layer includes a sputtering process. The integrated circuit wafer process of claim 66, wherein the step of forming the titanium-containing metal layer comprises a chemical vapor deposition process. The integrated circuit wafer process of claim 66, wherein the titanium-containing metal layer is a titanium-tungsten alloy layer or a titanium nitride layer. The integrated circuit wafer process as described in claim 66, further comprising: after the step of forming the titanium-containing metal layer, performing the titanium-containing metal layer in an environment containing nitrogen (N ₂ ) An annealing process followed by the step of forming the adhesive layer. The integrated circuit wafer process of claim 66, wherein the step of forming the adhesive layer comprises a sputtering process. The integrated circuit wafer process of claim 66, wherein the adhesive layer is a titanium-containing metal layer. The integrated circuit wafer process of claim 81, wherein the titanium-containing metal layer is a titanium layer or a titanium-tungsten alloy layer. The integrated circuit wafer process of claim 66, wherein the step of forming the third metal layer comprises a sputtering process. The integrated circuit wafer process of claim 66, further comprising forming a tin-containing metal layer over the third metal layer after the step of forming the third metal layer. The integrated circuit wafer process of claim 66, further comprising forming a polymer layer over the protective layer and the third metal layer after the step of forming the third metal layer. The integrated circuit wafer process of claim 66, further comprising plating a fourth metal layer on the third metal layer after the step of forming the third metal layer. The integrated circuit wafer process as described in claim 66, further comprising plating the plating solution containing one of gold (Au) and sulfite ion after the step of forming the third metal layer. A gold layer is on the third metal layer. The integrated circuit wafer process as described in claim 87, wherein the plating solution comprises a solution of sodium sulfite (Na ₃ Au(SO ₃ ) ₂ ) or ammonium sulfite ((NH ₄ ) ₃ [Au(SO) ₃ ) ₂ ]) Solution. The integrated circuit wafer process as described in claim 87, further comprising forming a polymer layer over the gold layer after the step of plating the gold layer.