TWI353652B - Integrated circuit and method for fabricating the - Google Patents

Integrated circuit and method for fabricating the Download PDF

Info

Publication number
TWI353652B
TWI353652B TW96122418A TW96122418A TWI353652B TW I353652 B TWI353652 B TW I353652B TW 96122418 A TW96122418 A TW 96122418A TW 96122418 A TW96122418 A TW 96122418A TW I353652 B TWI353652 B TW I353652B
Authority
TW
Taiwan
Prior art keywords
layer
metal
wafer
metal layer
line
Prior art date
Application number
TW96122418A
Other languages
Chinese (zh)
Other versions
TW200802714A (en
Inventor
Mou Shiung Lin
Jin Yuan Lee
Original Assignee
Megica Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Megica Corp filed Critical Megica Corp
Publication of TW200802714A publication Critical patent/TW200802714A/en
Application granted granted Critical
Publication of TWI353652B publication Critical patent/TWI353652B/en

Links

Landscapes

  • Formation Of Insulating Films (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Description

1353652 九、發明說明: 【發明所屬之技術領域】 本發明係有關一種結構及其製程,特別是有關一種積 體電路結構及其製程。 【先前技術】 改善半導體元件效能的方法通常是藉由縮小積體電路 的幾何尺寸,上述之結果可以使單位晶粒(per die)成本下 降,並同時改善半導體元件之某些方面的效能。連接積體 電路與其他電路之間或積體電路與系統元件之間的金屬連 -接(metal connection)變得相對地重要,且隨著積體電路的 更加微型化,對於線路效能的負面影響也隨之增加。當金 屬内連線之寄生電容(parasitic capacitance)與電阻增加,將 意味著昴片效能的下降。其中,最值得關切的是沿著電源 匯流排(power buses)與接地匯流排(ground buses)之間的壓 降(voltage drop),以及關鍵訊號路徑之電阻電容延遲(RC delay)。為了解決這個問題.,便發展使用低電阻之金屬(例 如銅)做為導線,並使用低介電常數(low-k)之介電材料於訊 號線之間。 從積體電路(Integrated Circuit,1C)連接金屬歷史的觀 點來看,濺鍍鋁從60年代後巳成為jc連接金屬材料之主 流。薄膜鋁經由濺鍍來覆蓋整片晶圓,接下來以黃光微影 製程及乾蝕刻或濕蝕刻的製程將鋁金屬圖案化。就成本及 濺鍍應力考量而言,要製作厚度超過2微米(μιη)之鋁金屬 線路技術是很困難且成本很昂貴。大約在1995年,鑲喪銅 (Damascene)成為另一種可用於]連接之金屬。就嵌铜 (Damascene)鋼而言,在絕緣層圖案化之後,藉由電鍍可以 形成銅層及藉由化學機械研磨(CN1p)可以將位於絕緣層開 口外之銅層除掉,將銅金屬連線形成於絕緣層開孔中。在 整片晶圓上電鍍厚金屬會造成大的應力,且鑲嵌銅 (Damascene copper)的厚度通常是由絕緣層厚度來決定,故 絕緣層一般如化學氣相沉積(Chemical Vapor Deposition, CVD)氧化物,由於應力及成本上之考量無法提供太厚之厚 度,也就是說要形成厚度超過2微米之銅金屬連線,在技 術上有其困難且成本昂貴。 【發明内容】 本發明之一目的,係在提供一種積體電路結構及其製 程,其可改善積體電路的性能。 本發明之一目的,係在提供一種積體電路結構及其製 程,其可在保護層(passivation layer)的下方形成一 厚金屬連接結構(coarse metal interconnection scheme)於細金屬連接結構(fine line metal interconnection scheme)上方0 為了上述之目的,本發明提出一種積體電路結構,其 係包括一半導體基底;一金屬線路,位在該半導體基底上 方,且該金屬線路的厚度介於5微米至27微米'之間;苡及-二 一保護層,包括一氮石夕化合物(silicon nitride)層位在該金… 屬線路上與該半導體基底上方,以及一氧矽化-合物(silicon — *** ~*~ 一· - — ••〜 oxide)層位在該氮矽化合物層上。 …一 1353652 為了上述之目的,本發明提出一種積體電路結構,其 係包括一半導體基底;一金屬線路,位在該半導體基底上 方,且該金屬線路的厚度介於5微米至27微米之間;以及 、蒦層括氮氧夺化合物(silicon oxynitride)層位在 該金屬線路上與該半導體基底上方,以及二氧#化—合物 (silicon 0Xide)層位在該氮氧矽化合物層上。 為了上述之目的,本發明提出一種製作積體電路結構 的方法,其步驟包括形成一第一金屬層在一半導體基底上 方;形成一第一光阻層在該第一金屬層上,且位在該第一 光阻層内之一第一光阻層開口暴露出該第一金屬層;形成 厚度介於5微米至25微米之間的一第二金屬層在該第―光 阻層開口所暴露出之該第—金屬層上;絲該第一光阻 層;去除未在該第二金屬層下方的該第一金屬層;形成— 氮梦化合物層在該第二金屬層上與該半導體基底上方;以 及形成一氧矽化合物層在該氮矽化合物層上。 為了上述之目的,本發明提出—種製作積體電路結構 的方法,其㈣包括形成―第―金屬料—半導體 方;形成ϋ阻層在該第—金屬層上且位在該第— 光阻層内之一第一光阻層開口暴露出該第 厚度介於5微米至25微米之間的—第二 θ,形成 阻層開口所暴露出之該第__金屬層上/層在該第—光 層;去除未在該第二金屬層下方的該第第一光阻 氮氧梦化合物層在該第二金屬層上與該半導體::一 J班二總氧矽化合物漘4-—二’ 1353652 — 底下藉由具體實施例配合所附的圖式詳加說明,當更 容易瞭解本發明之目的、技術内容、特點及其所達成之功 效0 【實施方式】 本發明所揭露的每一種結構及方法皆是建構在一半導 體基底(semiconductor substrate)的上方或是一半導體晶圓 的上方。其中,「上方」一詞在本發明中是表示位在某物上 面並與之接觸,或是表示位在某物上面但未與之接觸。 請參閱第1圖所示,一半導體基底2的上方包括有複 數半導體元件(semiconductor device)4、一線路結構6以及 複數介電層(dielectric layer)8。底下將先欽述有關半導體 基底2、半導體元件4、線路結構6以及介電層8等内容, 接著再進行實施例說明》 一半導體基底2比如是矽(Si)基底、砷化鎵(GaAs)棊 底或矽化鍺(SiGe)基底,另外半導體基底2也可以是一半 導體晶圓’而此半導體晶圓比如是矽晶圓(silicon wafer) ' 砷化鎵晶圓或矽化鍺晶圓《•複數半導體元件4位在半導體 基底2内或上方。其中,這些半導體元件4包括被動元件(例 如電阻、電容或電感)或主動元件等,而主動元件比如是金 氧半導體(MOS)元件,此金氧半導體元件例如是p通道-金 氧半導體(p-channel MOS)元件、η通道金氧半導體 (n-channel MOS)元件、雙載子互補式金氧半導體(BiCMOS) 元件、_雙載子連接電晶體(Bipolar Junction.Tr往nsistor ’ BJT)二 二_~一· 7 ---, - . . - .一·,· ---—^ -r—.· - ——*&gt; 8 1353652 或互補金屬氡化半導體(CMOS)。 一線路結構6位在半導體基底2上方,此線路結構6 可以是由複數金屬層1〇(其厚度比如是小於3微米)與複數 • 金屬插塞(metal plug)12所構成,其中這些金屬層1〇與這 , 些金屬插塞12的材質比如是銅,或是這些金屬層的材 質為鋁或鋁合金’而這些金屬插塞12的材質為鎢。此外, 形成金屬層.10的方式包括有鑲嵌(damascene)製程、電穿p (electroplating)製程或藏鏡(sputtering)製程,例如以鑲嵌製 零 程形成銅作為金屬層10,或是以濺鍍製程形成鋁或鋁合金 作為金屬層10。 例如就鑲嵌製程而言,形成金屬層10的方式係先利用 化學氣相沉積(Chemical Vapor Deposition,CVD)的方式沈 積一無機保護層在一介電層(dielectric layer)8的上表面 上’此無機保護層的材質係選自氮矽化合物、氮氧矽化合 物或碳矽化合物,接著形成一光阻層在無機保護層上,並 利用位在光阻層内的光阻層開口蝕刻無機保護層與介電層 8而形成由溝渠與導通孔所組成的開口,接著利用濺鏟或 化學氣相沉積的方式沈積一阻障層在此開口内的下表面與― 側壁上以及無機保護層的上表面上,其中此阻障層的材質 係選自鈕(Ta)、氮化鈕(TaN)、鈷(Co)、鎳(Ni)、鎢(W)、氮 化鵠、銳(ΝΪ&gt;)、石夕酸鋁(aluminum silicate)、氮化鈦(TilvJ)— 及氮化叾夕鈦(TiSiN)其中之一者,或者是上述材料所形成之 合金;再來同樣利用濺鍍或化學氣相沉積的方式沈積一層— ’◊….··^^就史^鋼材質之種子層在阻障扈丄’繼續電:韓一:辞金-屬在二-:二 .·· &lt;·Ι I |· 一- III M •一·· ·*··-·— ~ .·. _ 厂.1 —* ·· · . . 一 ^ · _ ' _ i 1353652 種子曰上取後和用化學機械研磨(Chemical Mechanical1353652 IX. Description of the Invention: TECHNICAL FIELD OF THE INVENTION The present invention relates to a structure and a process thereof, and more particularly to an integrated circuit structure and a process thereof. [Prior Art] A method for improving the performance of a semiconductor element is generally to reduce the cost per unit die by reducing the geometry of the integrated circuit, and at the same time improving the performance of some aspects of the semiconductor device. Metal connection between the integrated circuit and other circuits or between the integrated circuit and the system components becomes relatively important, and with the miniaturization of the integrated circuit, the negative impact on the line performance It also increases. When the parasitic capacitance and resistance of the metal interconnects increase, it will mean a decrease in the performance of the cymbal. Among them, the most concern is the voltage drop between the power bus and the ground bus, and the RC delay of the critical signal path. In order to solve this problem, a low-resistance metal (e.g., copper) is used as a wire, and a low-k dielectric material is used between the signal lines. From the point of view of the metal history of the integrated circuit (1C), the sputtered aluminum has become the main stream of jc-connected metal materials since the 1960s. The thin film aluminum covers the entire wafer by sputtering, and then the aluminum metal is patterned by a yellow lithography process and a dry etching or wet etching process. In terms of cost and sputtering stress considerations, it is difficult and costly to fabricate aluminum metal line technology with thicknesses in excess of 2 microns. In about 1995, Damascene became another metal that could be used to connect. In the case of Damascene steel, after the insulating layer is patterned, a copper layer can be formed by electroplating and the copper layer outside the opening of the insulating layer can be removed by chemical mechanical polishing (CN1p) to connect the copper metal The wire is formed in the opening of the insulating layer. Plating thick metal on the entire wafer causes large stresses, and the thickness of the damascene copper is usually determined by the thickness of the insulating layer. Therefore, the insulating layer is generally oxidized by chemical vapor deposition (CVD). Because of the stress and cost considerations, it is impossible to provide too thick thickness, that is, to form a copper metal wire having a thickness of more than 2 micrometers, which is technically difficult and expensive. SUMMARY OF THE INVENTION An object of the present invention is to provide an integrated circuit structure and a process thereof which can improve the performance of an integrated circuit. It is an object of the present invention to provide an integrated circuit structure and a process thereof for forming a coarse metal interconnection scheme under a passivation layer in a fine metal metal structure (fine line metal) Above the ground, for the above purposes, the present invention provides an integrated circuit structure comprising a semiconductor substrate; a metal line over the semiconductor substrate, and the thickness of the metal line is between 5 microns and 27 microns 'Between; 苡 and - 21 protective layer, including a silicon nitride layer on the gold line and above the semiconductor substrate, and a bismuth-compound (silicon - *** ~*~ One - - • • • oxide) The layer is on the layer of the ruthenium compound. ...1353532 For the above purposes, the present invention provides an integrated circuit structure comprising a semiconductor substrate; a metal line positioned above the semiconductor substrate, and the metal line having a thickness between 5 microns and 27 microns And a layer of silicon oxynitride on the metal line and the semiconductor substrate, and a silicon 0Xide layer on the layer of the oxynitride compound. For the above purposes, the present invention provides a method of fabricating an integrated circuit structure, the method comprising: forming a first metal layer over a semiconductor substrate; forming a first photoresist layer on the first metal layer, and a first photoresist layer opening in the first photoresist layer exposes the first metal layer; and a second metal layer having a thickness between 5 micrometers and 25 micrometers is exposed in the opening of the first photoresist layer Extracting the first metal layer; removing the first photoresist layer; removing the first metal layer not under the second metal layer; forming a nitrogen compound layer on the second metal layer and the semiconductor substrate Upper; and forming an oxonium compound layer on the yttrium compound layer. For the above purposes, the present invention provides a method of fabricating an integrated circuit structure, wherein (4) includes forming a "metal-semiconductor" side; forming a germanium resist layer on the first metal layer and at the first photoresist One of the first photoresist layer openings in the layer exposes the second θ having a first thickness between 5 μm and 25 μm, and the first __metal layer/layer exposed by the opening of the resist layer is in the first a light layer; removing the first photoresist film under the second metal layer on the second metal layer and the semiconductor:: a J-band total oxime compound 漘4--two </ RTI> <RTI ID=0.0># </ RTI> </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; The structures and methods are all constructed over a semiconductor substrate or over a semiconductor wafer. Here, the term "upper" in the present invention means that it is located above and in contact with something, or that it is located above or not in contact with something. Referring to Fig. 1, a semiconductor substrate 2 includes a plurality of semiconductor devices 4, a wiring structure 6, and a plurality of dielectric layers 8. The semiconductor substrate 2, the semiconductor device 4, the wiring structure 6, and the dielectric layer 8 will be described below, and then the embodiment will be described. A semiconductor substrate 2 such as a germanium (Si) substrate or gallium arsenide (GaAs) is used. a germanium or germanium germanium (SiGe) substrate, and the semiconductor substrate 2 may also be a semiconductor wafer, and the semiconductor wafer is, for example, a silicon wafer, a gallium arsenide wafer or a germanium wafer. The semiconductor element 4 is located in or above the semiconductor substrate 2. The semiconductor component 4 includes a passive component (such as a resistor, a capacitor or an inductor) or an active component, and the active component is, for example, a metal oxide semiconductor (MOS) component, such as a p-channel-metal oxide semiconductor (p). -channel MOS) component, n-channel MOS device, bi-carrier complementary metal-oxide semiconductor (BiCMOS) device, _bi-carrier connected transistor (Bipolar Junction.Tr to nsistor 'BJT) II Two _~1·7 ---, - . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A line structure 6 is located above the semiconductor substrate 2. The line structure 6 may be composed of a plurality of metal layers 1 (having a thickness of, for example, less than 3 μm) and a plurality of metal plugs 12, wherein the metal layers are formed. 1〇 and the metal plug 12 is made of copper, or the metal layer is made of aluminum or aluminum alloy, and the metal plug 12 is made of tungsten. In addition, the manner of forming the metal layer .10 includes a damascene process, an electroplating process, or a sputtering process, such as forming a copper layer as a metal layer 10 by inlaying, or sputtering. The process forms aluminum or an aluminum alloy as the metal layer 10. For example, in the case of a damascene process, the metal layer 10 is formed by first depositing an inorganic protective layer on the upper surface of a dielectric layer 8 by means of chemical vapor deposition (CVD). The material of the inorganic protective layer is selected from the group consisting of a nitrogen ruthenium compound, a oxynitride compound or a carbon ruthenium compound, and then a photoresist layer is formed on the inorganic protective layer, and the inorganic protective layer is etched by using the photoresist layer opening in the photoresist layer. Forming an opening composed of a trench and a via hole with the dielectric layer 8, and then depositing a barrier layer on the lower surface of the opening and the sidewall and the inorganic protective layer by means of a spatter or chemical vapor deposition On the surface, the material of the barrier layer is selected from the group consisting of a button (Ta), a nitride button (TaN), cobalt (Co), nickel (Ni), tungsten (W), tantalum nitride, and sharp (ΝΪ>). One of aluminum silicate, titanium oxide (TilvJ), and titanium nitride (TiSiN), or an alloy formed from the above materials; again using sputtering or chemical vapor deposition Way to deposit a layer - '◊....··^^ The seed layer of the history ^ steel material is in the barrier 扈丄 'Continue electricity: Han Yi: Resignation of gold - belongs to the second -: two. · · &lt;·Ι I |· I-III M • 一···*·· -·· ~ .·. _ Factory.1 —* ·· · . . . ^ ^ _ ' _ i 1353652 Seed 曰 after taking and chemical mechanical polishing (Chemical Mechanical

PoHsh,CMP)的方式去除位在此開口外的銅金屬、種子層 及阻障層,直到曝露出無機保護層的上表面為止。以此種 方式在溝渠内所形成的阻障層、種子層及銅金屬係為金屬 層1〇 ’且15些金屬層10可以透過導通孔内的金屬插塞12 連通相鄰兩層之間的金屬層1〇或者是連接至半導體元件 4 〇 又,形成金屬層10方式比如是先利用濺鍍製程濺鍍一 鋁合金層(其係包括90 wt %以上的鋁及1〇 wt %以下的銅) 在一介電層8上’接著再透過微影蝕刻製程圖案化此鋁合 金層。、 複數介電層8(其厚度比如是小於3微米)位在半導體 基底2上方’且上述之金屬層1〇是位在這些介電層8之 間’並透過位在這些介電層8内的金屬插塞12連接相鄰兩 層之金屬層10。介電層8 —般是利用化學氣相沉積(CVD) 的方式所形成’而介電層8比如是氧矽化合物(例如Si02)、 四乙氧基矽烷(TE0S)之氧化物、含矽、碳、氧與氫之化合 物(例如SiwCxOyHz)、氮矽化合物(例如Si3N4)、氟矽玻璃 (Fluorinated Silicate Glass,FSG)、黑鑽石薄膜(Black Diamond)·、絲.印層(SiLK)、多孑L 性氧化梦(porous silicon 0\心6)、氮氧石夕化合物、聚芳基醋(卩〇]^716.肢.:.6化61*)、.聚---苯0惡°坐化〇1&gt;^61120\&amp;2〇16,?30)、介電常數.值(1&lt;;)介於1.5 至3之間的材質或者是以旋塗方式形成之.玻璃(Spin-On Glass,SOG ;中文亦可譯為旋塗式玻璃)。 _ . - _ - — _ - ·_— . - · - .^―- — — - — -· 一 .二· _ 一-. 圓— •二 10 1353652 •至此完成半導體基底2、半導體元件4、線路結構6 與介電層8等相關解說,接著進行實施例說明。 請參閱第2A圖所示,形成一含矽介電層14在線路結 構6上方及介電層8上方’且位在含矽介電層14内之至少 一開口 14a暴露出線路結構6的金屬層1〇。其中,含矽介 電層14比如是一氮矽化合物(silic〇n nitride)層或是—氮氡 矽化合物(silicon oxynitride)層,而含矽介電層14的厚度 比如是介於0.1微米(μιη)至05微米之間。故,含矽介電 層14可以是厚度介於〇.丨微米至〇 5微米之間的一氮矽化 合物層,且開口 14a暴露出材質包括銅的金屬層1〇;或者, 含矽介電層14可以是厚度介於〇1微米至〇5微米之間的 一氮氧矽化合物層,且開口 14a暴露出材質包括銅的金屬 層10 ;或者,含矽介電層14可以是厚度介於〇丨微米至 0.5微米之間的一氮矽化合物層,且開口 14a暴露出材質包 括鋁的金屬層10;或者’含矽介電層14可以是厚度介於 〇.1微米至0.5微米之間的一氮氧矽化合物層,且開口 14狂 暴露出材質包括鋁的金屬層1〇。此外,形成含矽介電層14 的方式比如是利用電製加強型化學氣相沉積(朽狀咖The PoHsh, CMP) removes the copper metal, seed layer and barrier layer outside the opening until the upper surface of the inorganic protective layer is exposed. The barrier layer, the seed layer and the copper metal formed in the trench in this manner are the metal layer 1' and the 15 metal layers 10 can pass through the metal plug 12 in the via hole to communicate between the adjacent two layers. The metal layer 1 is connected to the semiconductor device 4, and the metal layer 10 is formed by sputtering an aluminum alloy layer (including 90 wt% or more of aluminum and 1 wt% or less of copper) by a sputtering process. The aluminum alloy layer is patterned on a dielectric layer 8 by a photolithography process. a plurality of dielectric layers 8 (having a thickness of, for example, less than 3 micrometers) are positioned above the semiconductor substrate 2 and the metal layer 1 is positioned between the dielectric layers 8 and is transmissive in the dielectric layers 8 The metal plug 12 connects the adjacent two layers of the metal layer 10. The dielectric layer 8 is generally formed by chemical vapor deposition (CVD), and the dielectric layer 8 is, for example, an oxonium compound (for example, SiO 2 ), an oxide of tetraethoxy decane (TEOS), or Carbon, oxygen and hydrogen compounds (for example SiwCxOyHz), nitrogen bismuth compounds (such as Si3N4), Fluorinated Silicate Glass (FSG), Black Diamond film, Silk. Printed layer (SiLK), multi-turn L-oxidative dream (porous silicon 0\heart 6), oxynitride compound, polyaryl vinegar (卩〇]^716. limbs::66 61*), poly---benzene 0 evil ° sit 〇1&gt;^61120\&2〇16,? 30), dielectric constant. Value (1 &lt;;) between 1.5 and 3 materials or formed by spin coating. Glass (Spin-On Glass, SOG; Chinese can also be translated as spin-on glass) . _ . - _ - - _ - · _ - . - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - The line structure 6 is explained in relation to the dielectric layer 8 and the like, and then the embodiment is explained. Referring to FIG. 2A, a metal containing a germanium dielectric layer 14 over the wiring structure 6 and above the dielectric layer 8 and having at least one opening 14a in the germanium containing dielectric layer 14 exposes the wiring structure 6. Layer 1〇. The germanium-containing dielectric layer 14 is, for example, a silic〇n nitride layer or a silicon oxynitride layer, and the germanium-containing dielectric layer 14 has a thickness of, for example, 0.1 micron ( Ιιη) to between 05 microns. Therefore, the germanium-containing dielectric layer 14 may be a layer of a ruthenium nitride compound having a thickness between 〇. 丨 micrometer and 〇 5 micrometers, and the opening 14a exposes a metal layer 1 made of copper; or The layer 14 may be a layer of oxynitride compound having a thickness between 〇1 μm and 〇5 μm, and the opening 14a exposes the metal layer 10 made of copper; or the germanium-containing dielectric layer 14 may have a thickness between a layer of a ruthenium nitride compound between 〇丨 micrometers and 0.5 micrometers, and the opening 14a exposes a metal layer 10 made of aluminum; or the dielectric layer 14 containing ruthenium may have a thickness of between 0.1 micrometers and 0.5 micrometers. A layer of oxynitride compound, and the opening 14 is madly exposed to a metal layer of material including aluminum. In addition, the manner of forming the germanium-containing dielectric layer 14 is, for example, using an electrically enhanced chemical vapor deposition (corrosive coffee).

Enhanced Chemical Vapor Deposition,PECVD)形成。 另,有關形成至少一開口 14a在含矽介電層14内的方 式敘述如下,首先請參閱第2B圖蛴示,形成一.光阻層15 在含矽介電層14上,並透過曝光與顯影等製程圖案化光阻 層15,以形成至少一光阻層開口 15a在光阻層15内並暴 H竟,形成光阻層15的方式例如是Enhanced Chemical Vapor Deposition (PECVD) formation. In addition, the manner of forming at least one opening 14a in the germanium-containing dielectric layer 14 is as follows. First, referring to FIG. 2B, a photoresist layer 15 is formed on the germanium-containing dielectric layer 14 and exposed through exposure. The developing process or the like patterning the photoresist layer 15 to form at least one photoresist layer opening 15a in the photoresist layer 15 and exposing the photoresist layer 15 to form the photoresist layer 15 is, for example,

—二:· 1 . ‘:.···一:._ ----~一-•一, : 二一:一、二 -J 1353652 以旋塗(spin coating)製程形成或是以壓合(laminati〇n)製程 形成,而在圖案化光阻層15的過程中比如是利用一倍(ιχ) 之曝光機(stepper)進行曝光或是利用一倍(1幻之對準曝光 機(contact aligner)進行曝光。接著,請參閱第2C圖所示, 去除光阻層開口 15a所暴露出之含矽介電層14,以形成開 口 14a在含矽介電層14内並暴露出金屬層1〇。其中,去 除光阻層開口 15a所暴露出之含矽介電層14的方式比如是 以蝕刻(etching)方式去除,並以乾蝕刻(dry etching)方式蝕 刻去除光阻層開口 15a所暴露出之+矽介電層14為較佳方 式’例如利用反應性離子钱刻(Reactive I〇n Etching,RIE) 製程姓刻去除.光阻層開口 15&amp;所暴露出之含梦介電層14。 最後,去除光阻層15,如第2A圖所示,而去除光阻層15 的方式比如疋利用含有氧離子之電漿(〇2 piasina)去除或是 利用有機溶劑(例如含有氨基化合物(amide)之有機溶劑)去 除。此外,在去除光阻層15之後,可利用電漿(例如是含 有氧離子之電漿或是含有氟離子濃度小於200PPM與氧離 子之電漿)清洗金屬層10,藉以去除金屬層1〇上表面之光 阻殘留物或其它異物。 __ 再來,於完成第2A圖所示之製程步驟後,利用一氬 氣濺擊(Ar sputtering)蝕刻製程或是一離子研磨(i〇n milling)製程#刻去除開口 14a所暴露出之金屬層1〇的氧 化層。 請參閱第2D圖所示,利用濺鍍方式形成一黏著/擴散 阻障層(adhesion/diffusion barrier layer)上6、矣含石夕介黨層 12 1353652 14上與開口 14a所暴露出之金屬層10上,其中「上」一 字在本發明t是表示位在某物上面並與之接觸。黏著/擴散 阻障層16的材質比如是選自鈦(Ti)、鈦鎢合金(TiW)、氮 化鈦(TiN)、鉻(Cr)、銘(Co)、财火金屬(refractory metal) 或是财火金屬合金(refractory metal-alloy)其中之一或所組 成之群組的至少其中之一者,且黏著/擴散阻障層16的厚 度比如是介於0.03微米至0.5微米之間。另,耐火金屬係 指具有高熔點及高度之化學安定性等特性的金屬,如钽 (tantalum,Ta)、鉬(molybdenum,Mo)或鶴(tungsten,W) 等金屬。 例如,黏著/擴散阻障層16可以是厚度介於0.03微米 至0.5徵米之間的一鈦層濺鍍在氮矽化合物層上與開口 14a所暴露出之材質包括銅的金屬層10上;或者,黏著/ 擴散阻障層16可以是厚度介於0.03微米至0.5微米之間 的一鈦層濺鍍在氮氧矽化合物層上與開口 14a所暴露出之 材質包括銅的金屬層10上;或者,黏著/擴散阻障層16可 以是厚度介於0.03微米至0.5微米之間的一鈦層濺鍍在氮 矽化合物層上與開口 14a所暴露出之材質包括鋁的金屬層_ 10上;或者,黏著/擴散阻障層16可以是厚度介於0.03微 米至0.5微米之間的一鈦層濺鍍在氮氧矽化合物層上與開 口’14a所|露出之材質包括铭的金屬層10上;或.者,黏著 /擴散阻障層16可以是厚度介於0.03微米至0.5微米之間 的一鈦鎢合金層濺鐘在氮矽化合物層上與開口 14a所暴露 出之材質包括碑岣金屬層__1卫..上.惑煮丄著/擴散阻障層 Z - — -_. -·ΐ·:_「-”:·一—π_ · — — 1 - - ·-* — · · · ' ' &quot;&quot;&quot; · ·.〜.-··二 ~ -·· - · ~ —· ~ · !353652 16可以是厚度介於0.03微米至〇 5微米之間的一鈦鎢合金 層濺鍍在氮氡矽化合物層上與開口 14a所暴露出之材質包 括銅的金屬層10上;或者,黏著/擴散阻障層16可以是厚 度介於0.03微米至0.5微米之間的一鈦鎢合金層濺鍍在氮 矽化合物層上與開口 14a所暴露出之材質包括鋁的金屬層 10上;或者,黏著/擴散阻障層16可以是厚度介於〇 〇3微 求至0.5微米之間的一鈦鎢合金層濺鍍在氮氧矽化合物層 上與開口 14a所暴露出之材質包括鋁的金屬層1〇上。 請參閱第2E圖所示,形成一金屬層18在黏著/擴散阻 障層16上’此金屬層18係作為電鍍時的導電層以及種子 層(seed layer),且厚度比如是介於〇 〇5微米至1徽米之 間,另外形成金屬層18的方式比如是濺鍍、蒸鍍、物理氣 相/儿積或者疋無電電鍍(electr〇less piating)等方式。由於金 屬層18可有利於後續金屬層的設置,因此金屬層18的材 質會隨後續金屬層的材質而有所變化,如當電鍍形成材質 為金(Au)的金屬層在金屬層18上時,金屬層18的材質係 以金為佳;當電鍍形成材質為銅(Cu)的金屬層在金屬層18. 上時,金屬層18的材質係以銅為佳。 一 综上所述’當黏著/擴散阻障層16是以濺鍍方式所形 成之厚度介於0.03微米至〇.5微米之間的一鈦層時,金屬 層I8可以是厚度介於〇.〇5微米至丨.被来之間的一金層濺 鍍在此鈦層上;或是,當黏著/擴散阻障層16是以濺鍍方 式所形成之厚度介於〇·〇3微米至0.5微米之間的一钛層 以彖厚度介於〇.〇5微米至1微米之間的 、 · ♦- ------一^^.... ·二r·..—.. · 一— 二二 1353652 一銅層濺鍍在此鈦層上;或是,當黏著/擴散阻障層16是 以濺鍍方式所形成之厚度介於0.03微米至0.5微米之間的 一鈦鎢合金層時,金屬層18可以是厚度介於0.05微米至 1微米之間的一金層濺鍍在此鈦鎢合金層上;或是,當黏 著/擴散阻障層16是以濺鍍方式所形成之厚度介於0.03微 米至0.5微米之間的一鈦鎢合金層時,金屬層18可以是厚 度介於0.05微米至1微米之間的一銅層濺鍍在此鈦鎢合金 層上。 請參閱第2F圖與第2G圖所示,形成一光阻層20在 金屬層18上,並透過曝光與顯影等製程圖案化光阻層20, 以形成至少一光阻層開口 20a在光阻層20内並暴露出金屬 層18(包括暴露出位在開口 14a所暴露出之金屬層10上方 的金屬層18)。其中,第2G圖係為第2F圖沿著具有線路 圖形之光阻層開口 20a的橫斷面側視圖。 形成光阻層20的方式例如是以旋塗(spin coating)製 程形成或是以壓合(lamination)製程形成,而在圖案化光阻 層20的過程中比如是利用一倍(IX)之曝光機(stepper)曝光 光阻層20或是利用一倍(IX)之對準曝光機(contact .aligner) 曝光光阻層20。另,在顯影後可利用電漿(例如是含有氧 離子之電漿或是含有氟離子濃度小於200PPM與氧離子之 電漿)清洗光阻層開口 20a所暴露出之金屬層18,藉以去 除金屬層18上表面之光阻殘留物或其它異物。 請參閱第2H圖所示,電鍍形成厚度介於5微米至25 微米之間的一金屬層22在光阻層開口 参g串m 15 1353652 層18上。金屬層22包括銅、鎳或金其中之一或所組成之 群組的至少其中之一者,例如金屬層22可以是一金層之單 層金屬結構、一銅層之單層金屬結構、一銅層與一錄層位 在此銅層上所組成之複合層金屬結構(銅/鎳),或是一銅 層、一錄層位在此銅層上以及一金層位在此鎳層上所組成 之複合層金屬結構(銅/鎳/金)。另外,形成金屬層22的方 式亦可包括無電電鍍(electroless plating)製程。 以電鍍製程形成金屬層22為例,金屬層22可以利用 下例四種方式形成: a. 以含有硫酸銅(CuS04)溶液之電鍍液電鍍厚度介於5微 米至25微米之間的一銅層在材質比如是銅的金屬層18 上。 b. 以含有硫酸銅(CuS04)溶液之電鍍液電鍍一銅層在材 質比如是銅的金屬層18上,再來以含有硫酸鎳(NiS04) 溶液之電鍍液電鍍一鎳層在此銅層上。其中,銅層的 厚度比如是介於4微米至25微米之間,而鎳層的厚度 比如是介於0.5微米至3微米之間。 c. 以含有硫酸銅(CuS04)溶液之電鍍液電鍍一銅層在材_ 質比如是銅的金屬層18上,繼續以含有硫酸鎳(NiS04) 溶液之電鍍液電鍍一鎳層在此銅層上,再來以含有亞 硫酸鈉金(Na3Au(S03)2)溶液之電鍍液電鍍一金層在此 錄層上。其中,銅層的厚度比如是介於4微米至25微 米之間,鎳層的厚度比如是介於0.5微米至3微米之 一;,而金層的_厚_度比如是介於〇.〇5微米至0.2微生之 16 1353652 間。 d.以含有亞硫酸鈉金(Na3Au(S03)2)溶液之電鍍液電鏟厚 度介於5微米至25微米之間的一金層在材質比如是金 的金屬層18上。 請參閱第21圖所示,在形成金屬層22之後,接著去 除光阻層20,而去除光阻層20的方式比如是利用含有氧 離子之電漿(02 plasma)去除或是利用有機溶劑(例如含有 氨基化合物之有機溶劑)去除。此外,在去除光阻層20之 後,可以利用電漿(例如是含有氧離子之電漿或是含有氟離 子濃度小於200PPM與氧離子之電漿)清洗金屬層22與金 屬層18,藉以去除金屬層22上表面與金屬層18上表面之 光阻殘留物或其它異物。 繼續請參閱第2J圖所示,去除未在金屬層22下方的 金屬層18與黏著/擴散阻障層16。其中,去除未在金屬層 22下方之金屬層18與黏著/擴散阻障層16的方式比如是 以钱刻方式去除,而#刻方式可分為乾截刻(dry etching) 與濕钱刻(wet etching)兩種。文,乾姓刻為姓刻去除黏著/ 擴散阻障層16的最佳方式,其係包括化學電漿蝕刻、濺擊 蝕刻(如使用高壓氬氣進行濺擊蝕刻)與化學氣體蝕刻。 例如,在去除金屬層18方面,可以透過濕式化學(wet chemical)钱刻製程、錢擊钱刻(sputtering etching)製程或離 子研磨(ion milling)製程#刻去除。又,當金屬層18的材 質為金時,可利用含有碘之蝕刻液(例如含有碘化鉀之蝕刻 液)蝕刻去除,另當金屬層18的材質為銅時,可利用含有 一 · - I I 圓如. 圓 _ , , ^^^»圓圓_ · ** · · — - · 一 - » *&gt; , _ _ ·— : ·— 17 1353652 氫氧化銨(NH4〇H)之蝕刻液蝕刻去除。在去除黏著/擴散阻 障層16方面,則比如是透過反應性離子银刻(RIE)製程、 濺擊蝕刻製程或離子研磨製程蝕刻去除。 •因此,本發明可形成至少一金屬線路24在含矽介電層 , 14上與開口 1扣所暴露之金屬層10上,此金屬線路24是 由一黏著/擴散阻障層16、位在黏著/擴散阻障層16上的一 金屬層18與位在金屬層18上的—金屬層22所構成,且厚 度tl係介於5微米至27微米之間。 鲁 於去除未在金屬層22下方的金屬層18與黏著/擴散阻 障層16之後,接著形成一保護層32在金屬線路24上與含 矽介電層14上,並可透過位在保護層.32内之一開口 32a 暴露出金屬線路24,而形成保護層32及開口 32a的方法 敘述如下。惟,本發明也可以沒有任何開口 32a形成在保 護層32内而暴露出金屬線路24。 第1種形成保護層及開口的方法 請參閱第3A圖所示’先利用電漿加強型化學氣相沉 積(PECVD)形成厚度介於〇.丨微米至〇· 5微米之間的一氮矽 化合物層26在金屬線路24上與含矽介電層丨4(例如氮矽 化合物層或氮氧矽化合物層)上,接著再利用電漿加強型化 學氣相沉積(PECVD)形成厚度介於〇 j微米至〇 5微米之間 的一氧石夕化合物(silicon oxide)層28在氮矽化合物層26 上,最後利用電漿加強型化學氣相沉積(PEcVD)形成厚度 介於0.5微米至1.5微米之間的一氮矽化合物層3〇在氧矽 生令物層28 ° 18 1353652 因此,保護層32是由一氮矽化合物層26、一氧矽化 合物層28與一氮矽化合物層30所構成。另,有關形成至 少一開口 32a在保護層32内並暴露出金屬線路24(例如暴 露出金屬線路24的銅層、鎳層或金層)的方式敘述如下。 第一種形成開口 32a的方式請參閱第3B圖至第3D圖 所示。首先請參閱第3B圖所示,形成一光阻層34在保護 層32之氮矽化合物層30上,接著透過曝光與顯影等製程 圖案化光阻層34,以形成至少一光阻層開口 34a在光阻層 34内並暴露出金屬線路24上方的氮矽化合物層30。其中, 形成光阻層34的方式比如是以旋塗(spin coating)製程形 成或是以麼合(lamination)製程形成,而在圖案化光阻層34 的過举中比如是利用一倍(IX)之曝光機(stepper)進行曝光 或是利用一倍(IX)之對準曝光機(contact aligner)進曝光。 請參閱第3C圖所示,依序去除光阻層開口 34a下方 的氮矽化合物層30、氧矽化合物層28與氮矽化合物層26, 以形成至少一開口 32a在保護層32内並暴露出金屬線路 24(例如暴露出金屬線路24的銅層、鎳層或金層)。其中, 去除光阻層開口 34a下方的氮矽化合物層30、氧矽化合物 層28與氮矽化合物層26之方式比如是以蝕刻方式去除, 並以反應性離子蝕刻(RIE)製程蝕刻去除為較-佳方式。· 再來請參閱第3D圖所示,去除光阻層34,而去除光 阻層34的方式比如是利用含有氧離子之電漿(〇2 plasma) 去除或是利用有機溶劑(例如含有氨基化合物之有機溶劑) 去除。此外,在去除H厚34—之彳4」jrm垔处彳如是 Γ Τ-1—1 &quot;* w- τ—_ _ ·. · — ·. · ~ — - - «- · — — * — · .·. **-·»** 了,. 19 1353652 含有氧離子之電漿或是含有氟離子濃度小於200PPM與氧 離子之電漿)清洗開口 32a所暴露出之金屬線路24,藉以 去除金屬線路24上表面之光阻殘留物或其它異物。 第二種形成開口 32a的方式請參閱第3E圖至第3F圖 所示。首先請參閱第3E圖所示,旋塗(spin coatiiig)形成一 聚合物層36在保護層32之氮矽化合物層30上,接著透過 供烤(baking)、曝光(exposure)與顯影(development)等製程 圖案化聚合物層36,以形成至少一聚合物層開口 36a在聚 合物層36内並暴露出金屬線路24上方的氮矽化合物層 30。在圖案化聚合物層36的過程中比如是利用一倍(IX) 之曝光機(stepper)進行曝光或是利用一倍(1X)之對準曝光 機(contact aligner)進曝光。再來,於氮氣環境或無氧環境 中,利用硬化(curing)製程在溫度介於200°C至290°C之 間、介於290°C至330°C之間或是介於330°C至400。(:之間 硬化聚合物層36,且進行硬化製程的時間係介於30分鐘 至2小時之間。其中,聚合物層36比如是選自聚醯亞胺 (polyimide,PI)、苯基環丁烯(benzocyclobutane,BCB)、 聚氨脂、環氧樹脂(epoxy resin)、聚對二甲苯類高分子、焊 罩材料、彈性材料或多孔性介電材料其中之一,且硬化後 的聚合物層36厚度比如是介於5微米至30微求-之間.,例 如聚合物層36可以是厚度介於5微米至30微米之間的一 聚醯亞胺層或是厚度介於5微米至30微米之間的一笨基環 丁烯層。 請參閱第3F圖所示,依序去除聚合物層開口 36a下方 - · - ** - — · - 一 · ·響 --------------., , — · '* ~ . 子 —.圓 圓·. 圓 *^^**^^ * I _ I IM· , I 圓· ·- ·*_» V - — ~ ~ ' ---·-·*τϊ- . - — '一 · 1 &quot; - ·· - · · - · — _了 _ -- .. — .r~iz 20 1353652 的氮矽化合物層30、氧矽化合物層28與氮矽化合物層26, 以形成至少一開口 32a在保護層32内並暴露出金屬線路 24(例如暴露出金屬線路24的銅層、鎳層或金層)。其中-, 去除聚合物層開口 36a下方的氮矽化合物層30、氧矽化合 物層28與氮矽化合物層26之方式比如是以蝕刻方式去 除,並以反應性離子蝕刻(RIE)製程蝕刻去除為較佳方式。 另,上述的氮矽化合物層26亦可由氮氧矽化合物層取 代,亦即利用電漿加強型化學氣相沉積(PECVD)形成厚度 介於0.1微米至0.5微米之間的一氮氧矽化合物層在金屬 線路24上與含矽介電層14(例如氮矽北合物層或氮氧矽化 合物層)上,接著再利用電漿加強型化學氣相沉積(PECVD) 形成厚度介於0.1微米至0.5微米之間的一氧矽化合物層 28在此氮氧矽化合物層上,繼續利用電漿加強型化學氣相 沉積(PECVP)形成厚度介於〇.5微米至1.5微米之間的一氮 矽化合物層3〇在氧矽化合物層28上,再來進行上述第3B 圖至第3D圖所述之步驟或是進行上述第3E圖至第3F圖 所述之步驟,在此不再詳加說明,然熟習該技術者當可藉 由上述的說明而據以實施。 第2種形成保護屉及朗〇的卞争 請參閱第4A圖所示,先利用電漿加強型化學氣相沉 積(PECVD)形成厚度介於〇丨微米至〇 5微米之間的一氮矽 化合物層38在金屬線路24上與含矽介電層i4(例如氮矽 化合物層或It氧發化合物層)上,繼續利用電漿加強型化學 形成厚度介於0.1微米至0.5微米之間的 21 1353652 一氧矽化合物層40在氮矽化合物層38上,接著形成一旋 塗式玻璃(SOG)層42在氧矽化合物層40上。繼續,利用 一蝕刻製程蝕刻旋塗式玻璃層42,以暴露出氧矽化合物層 40。再來,利用電漿加強型化學氣相沉積(PECVD)形成厚 度介於0.5微米至1.5微米之間的一氮矽化合物層44在旋 塗式玻璃層42上與暴露出的氧矽化合物層40上。 因此,保護層32是由一氮矽化合物層38、一氧矽化 合物層40、一旋塗式玻璃層42與一氮矽化合物層44所構 成。另,有關形成至少一開口 32a在保護層32内並暴露出 金屬線路24(例如暴露出金屬線路24的銅層、鎳層或金層) 的方式敘述如下。 第一種形成開口 32a的方式請參閱第4B圖至第4E)圖 所示。首先請參閱第4B圖所示,形成一光阻層46在保護 層32之氮矽化合物層44上,接著透過曝光與顯影等製程 _案化光阻層46,以形成至少一光阻層開口 46a在光阻層 46内並暴露出金屬線路24上方的氮矽化合物層44。其中, 形成光阻層46的方式tb如是以旋塗(spin coating)製程形 成或是以壓合(lamination)製程形成,而在圖案化光阻層46 程中比如疋利用—倍(IX)之曝光機(stepper)進行曝光 用倍(1X)之斟準曝光機(contact aligner)進曝光。 請參閱第4C圖斛_ 热备 W不,依序去除光阻層開口 46a下方 、氮矽化合物層44、 以左,1 %矽化合物層40與氮矽化合物層38, 乂形成至少一開口 2aCu, , &amp;在保護層32内並暴露出金屬線路 ^暴露出金屬錄狄、 二,Λ . 〜''~'~~~'^.一''— -ά.〜% 24的銅層、錄層或金層)。其中, 22 1353652 去除光阻層開口 46a下方的氮矽化合物層44、氧矽化合物 層40與氮矽化合物層38之方式比如是以蝕刻方式去除, 並以反應性離子蝕刻(RIE)製程蝕刻去除為較佳方式。 再來請參閱第4D圖所示,去除光阻層46,而去除光 阻層46的方式比如是利用含有氧離子之電漿(〇2 plasma) 去除或是利用有機溶劑(例如含有氨基化合物之有機溶劑) 去除。此外,在去除光阻層46之後,可利用電漿(例如是 含有氧離子之電漿或是含有氟離子濃度小於200PPM與氧 離子之電漿)清洗開口 32a所暴露出之金屬線路24,藉以 去除金屬線路24上表面之光阻殘留物或其它異物。 第二種形成開口 32a的方式請參閱第4E圖至第4F圖 所示。首先請參閱第4E圖所示,旋塗形成一聚合物層48 在保護層32之氮矽化合物層44上,接著透過烘烤、曝光 與顯影等製程圖案化聚合物層48,以形成至少一聚合物層 開口 48a在聚合物層48内並暴露出金屬線路24上方的氮 矽化合物層44。在圖案化聚合物層48的過程中比如是利 用一倍(IX)之曝光機(stepper)進.行曝光或是利用一倍(IX) 之對準曝光機(contact aligner)進曝光。再來,於氮氣環境: 或無氧環境中,利用硬化(curing)製程在溫度介於200°C至 290°C之間、介於290°C至330°C之間或是介於330°C至400 °C之間硬化聚合物層48,且進行硬化製程的時間係介於30 分鐘至2小時之間。其中,聚合物層48比如是選自聚醯亞 胺(PI)、苯基環丁烯(BCB)、聚氨脂、環氧樹脂(epoxy Lesin)、聚對二甲苯類高命t、_5旱生科、_f」t生材料或多孔 , — . ,1 I ·— - Ύ - - - ' : — - - - - . - - · ·- - ‘ · * ' * -— __ -_** * •…二-—'— 23 1353652 性介電材料其中之一,且硬化後的聚合物層48厚度比如是 介於5微米至30微米之間,例如聚合物層48可以是厚度 介於5微米至30微米之間的一聚醯亞胺層或是厚度介於5 微米至30微米之間的一苯基環丁烯層。 請參閱第4F圖所示,依序去除聚合物層開口 48a下方 的氮矽化合物層44、氧矽化合物層40與氮矽化合物層38, 以形成至少一開口 32a在保護層32内並暴露出金屬線路 24(例如暴露出金屬線路24的銅層、鎳層或金層)。其中, 去除聚合物層開口 48a下方的氮矽化合物層44、氧矽化合 物層40與氮矽化合物層38之方式比如是以蝕刻方式去 除,並以反應性離子蝕刻(RIE)製程蝕刻去除為較佳方式。 另,上述的氮矽化合物層38亦可由氮氧矽化合物層取 代,亦即利用電漿加強型化學氣相沉積(PECVD)形成厚度 介於0.1微米至0.5微米之間的一氮氧矽化合物層在金屬 線路24上與含矽介電層14(例如氮矽化合物層或氮氧矽化 合物層)上,繼續利用電衆加強型化學氣相沉積(PECVD) 形成厚度介於0.1微米至0.5微米之間的一氧矽化合物層 40在此氮氧矽化合物層上,接著形成一旋塗式玻璃(800) 層42在氧矽化合物層40上,繼續利用一蝕刻製程蝕刻旋 塗式玻璃層42,以暴露出氧矽化合物層40,再來形成厚度 介於0.5微米呈1.5微米之間的一氮矽化合物層44在旋塗 式玻璃層42上與暴露出的氧矽化合物層40上,接著進行 上述第4B圖至第4D圖所述之步驟或是進行上述第4E圖 至第4F圖所述之步驟,在此不再詳加說明,然熟習該技 24 1353652 術者當可藉由上述的說明而據以實施。 第3種形成保護層及開口的方法 請參閱第5圖所示,先利用電漿加強型化學氣相沉積 (PECVD)形成厚度介於0.1微米至0.5微米之間的一氮矽化 合物層38在金屬線路24上與含矽介電層14(例如氮矽化 合物層或氮氧矽化合物層)上,繼續利用電漿加強型化學氣 相沉積(PECVD)形成厚度介於0.1微米至0.5微米之間的一 氧矽化合物層40在氮矽化合物層38上。接著,旋塗形成 一聚合物層50在氧矽化合物層40上,並於氮氣環境或無 氧環境中,利用硬化(curing)製程在溫度介於200°C至290 °C之間、介於290°C至330°C之間或是介於330°C至400°C 之間硬化聚合物層50,其中進行硬化製程的時間係介於30 分鐘至2小時之間,且聚合物層50比如是聚醯亞胺(PI)或 苯基環丁烯(BCB)。繼續,利用一蝕刻製程蝕刻聚合物層 50,以暴露出氧矽化合物層40。再來,利用電漿加強型化 學氣相沉積(PECVD)形成厚度介於0.5微米至1.5微米之間 的一氮矽化合物層44在聚合物層50上與暴露出的氧矽化 合物層40上。 因此,保護層32是由一氮矽化合物層38、一氧砍化 合物層40、一聚合物層50與一氮碎化合物層44所構成。 此外,有關形成至少一開口 32a在保護層32内並暴露出金 屬線路24(例如暴露出金屬線路24的銅層、鎳層或金層) 的方式,請參閱上述第4B圖至第4F圖的相關說明,在此 不再詳加敘述°_ — — ________ 25 1353652 另,上述的氮石夕化合物層38亦可由氮氧石夕化合物層取 代’亦即利用電漿加強型化學氣相沉積(PECVD)形成厚度 介於0.1微米至0.5微米之間的一氮氧矽化合物層在金屬 線路24上與含矽介電層14(例如氮矽化合物層或氮氧矽化 合物層)上,繼續利用電漿加強型化學氣相沉積(PECVD) 形成厚度介於0.1微米至0.5微米之間的一氧矽化合物層 4〇在此氮氧矽化合物層上,接著形成一聚合物層5〇在氧 石夕化合物層40上,之後利用一蝕刻製程蝕刻聚合物層5〇, 以暴露出氧矽化合物層40,再來利用電漿加強型化學氣相 沉積(PECVD)形成厚度介於〇.5微米至1.5微米之間的一氮 石夕化合物層44在聚合物層50上與暴露出的氧矽化合物層 40上,最後進行上述第4B圖至第4D圖所述之步驟或是 進行上述第4E圖至第4F圖所述之步驟,在此不再詳加說 明’然熟習該技術者當可藉由上述的說明而據以實施。 第4種形成保護層及閩口热古法—二:· 1 . ':.···一:._ ----~一-•一, :二一:一,二-J 1353652 Formed by spin coating process or pressed (laminati〇n) process formation, and in the process of patterning the photoresist layer 15, for example, using a double (stepper) exposure machine or using double (1 magic alignment machine (contact) Exposure is performed. Next, as shown in FIG. 2C, the germanium-containing dielectric layer 14 exposed by the photoresist layer opening 15a is removed to form the opening 14a in the germanium-containing dielectric layer 14 and expose the metal layer 1 The manner of removing the germanium-containing dielectric layer 14 exposed by the photoresist layer opening 15a is, for example, removed by etching, and is exposed by dry etching to remove the photoresist layer opening 15a. The + dielectric layer 14 is preferably a preferred method 'for example, using a reactive ion etch (RIE) process to remove the photoresist layer 14 &amp; exposed to the dream dielectric layer 14 Finally, the photoresist layer 15 is removed, as shown in FIG. 2A, and the photoresist layer 15 is removed. The plasma of aerobic ions (〇2 piasina) is removed or removed by an organic solvent (for example, an organic solvent containing an amide). Further, after the photoresist layer 15 is removed, a plasma (for example, containing oxygen) may be used. The ion plasma or the plasma containing a fluoride ion concentration of less than 200 PPM and oxygen ions is used to clean the metal layer 10, thereby removing photoresist residue or other foreign matter on the upper surface of the metal layer. __ Next, after completing Figure 2A After the process steps shown, the oxide layer of the metal layer 1 暴露 exposed by the opening 14a is removed by an Ar sputtering etching process or an ion milling process. As shown in Fig. 2D, an adhesion/diffusion barrier layer is formed by sputtering, and the metal layer 10 exposed on the opening 14a is formed on the layer of the stone layer 12 1353652 14 Wherein the word "upper" is used in the present invention to indicate that it is on or in contact with something. The material of the adhesion/diffusion barrier layer 16 is selected, for example, from titanium (Ti), titanium tungsten alloy (TiW), and nitride. Titanium (TiN), chromium (Cr), Ming (Co At least one of or a group of refractory metals or refractory metal-alloys, and the thickness of the adhesion/diffusion barrier layer 16 is It is between 0.03 microns and 0.5 microns. Further, the refractory metal refers to a metal having characteristics such as high melting point and high chemical stability, such as tantalum (Ta), molybdenum (Mo) or tungsten (W). For example, the adhesion/diffusion barrier layer 16 may be a titanium layer having a thickness of between 0.03 micrometers and 0.5 millimeters. The titanium layer is sputtered on the layer of the nitrogen-niobium compound and the metal layer 10 of the material including the copper exposed by the opening 14a; Alternatively, the adhesion/diffusion barrier layer 16 may be a titanium layer having a thickness of between 0.03 micrometers and 0.5 micrometers sputtered on the oxynitride compound layer and the metal layer 10 of the material including the copper exposed by the opening 14a; Alternatively, the adhesion/diffusion barrier layer 16 may be a titanium layer having a thickness of between 0.03 micrometers and 0.5 micrometers sputtered on the layer of the nitrogen-niobium compound and the metal layer _ 10 of the material including the aluminum exposed by the opening 14a; Alternatively, the adhesion/diffusion barrier layer 16 may be a titanium layer having a thickness between 0.03 micrometers and 0.5 micrometers sputtered on the oxynitride compound layer and the opening '14a|exposed material including the metal layer 10 of the name Or, the adhesion/diffusion barrier layer 16 may be a titanium-tungsten alloy layer having a thickness of between 0.03 micrometers and 0.5 micrometers. The splashing of the material on the layer of the nitrogen-niobium compound and the opening 14a includes a monumental metal. Layer __1 卫..上.惑煮丄/Diffusion barrier Z - — -_. -·ΐ·:__--:·一—π_ ·———— 1 - - ·-* — · · · ' ' &quot;&quot;&quot; · ·.~.-··二~ - ········ ~ · !353652 16 may be a titanium-tungsten alloy layer having a thickness between 0.03 micrometers and 〇5 micrometers sputtered on the layer of nitrogen-niobium compound and exposed to the opening 14a including copper Or the adhesion/diffusion barrier layer 16 may be a titanium-tungsten alloy layer having a thickness of between 0.03 micrometers and 0.5 micrometers sputtered on the layer of the nitrogen-niobium compound and exposed to the opening 14a. On the metal layer 10 of aluminum; or, the adhesion/diffusion barrier layer 16 may be a titanium-tungsten alloy layer having a thickness between 微3 and 0.5 μm sputtered on the oxynitride compound layer and the opening 14a. The exposed material consists of a metal layer of aluminum. Referring to FIG. 2E, a metal layer 18 is formed on the adhesion/diffusion barrier layer 16. This metal layer 18 serves as a conductive layer and a seed layer for electroplating, and the thickness is, for example, The method of forming the metal layer 18 between 5 micrometers and 1 millimeter meter is, for example, sputtering, vapor deposition, physical gas phase/integral or electroless plating (electr〇less piating). Since the metal layer 18 can facilitate the placement of the subsequent metal layer, the material of the metal layer 18 varies with the material of the subsequent metal layer, such as when a metal layer of gold (Au) is formed on the metal layer 18 by electroplating. The material of the metal layer 18 is preferably gold. When the metal layer formed of copper (Cu) is formed on the metal layer 18. The metal layer 18 is preferably made of copper. In summary, when the adhesion/diffusion barrier layer 16 is formed by sputtering in a thickness of between 0.03 micrometers and 〇.5 micrometers, the metal layer I8 may have a thickness of between 〇. 〇 5 microns to 丨. A gold layer between the layers is sputtered onto the titanium layer; or, when the adhesion/diffusion barrier layer 16 is formed by sputtering, the thickness is between 〇·〇3 μm to A titanium layer between 0.5 micrometers has a thickness of between 〇. 〇 5 micrometers to 1 micrometer, ♦ ------ ------ a ^ ^.... · two r ·..-.. · a 1-23533652 a copper layer is sputtered on the titanium layer; or, when the adhesion/diffusion barrier layer 16 is formed by sputtering, a thickness of between titanium and tungsten is between 0.03 micrometers and 0.5 micrometers. In the alloy layer, the metal layer 18 may be a gold layer having a thickness of between 0.05 μm and 1 μm sputtered on the titanium tungsten alloy layer; or, when the adhesion/diffusion barrier layer 16 is sputtered. When a titanium-tungsten alloy layer having a thickness of between 0.03 μm and 0.5 μm is formed, the metal layer 18 may be a copper layer having a thickness of between 0.05 μm and 1 μm sputtered on the titanium-tungsten alloy layer. Referring to FIGS. 2F and 2G, a photoresist layer 20 is formed on the metal layer 18, and the photoresist layer 20 is patterned by exposure and development processes to form at least one photoresist layer opening 20a in the photoresist. The metal layer 18 is exposed within the layer 20 (including exposing the metal layer 18 above the metal layer 10 exposed by the opening 14a). Here, the 2Gth image is a cross-sectional side view of the 2Fth image along the photoresist layer opening 20a having the line pattern. The method of forming the photoresist layer 20 is formed, for example, by a spin coating process or by a lamination process, and in the process of patterning the photoresist layer 20, for example, by using a double (IX) exposure. The stepper exposes the photoresist layer 20 or exposes the photoresist layer 20 by a double (IX) alignment exposure machine. In addition, after the development, the metal layer 18 exposed by the photoresist layer opening 20a may be cleaned by using a plasma (for example, a plasma containing oxygen ions or a plasma containing a fluoride ion concentration of less than 200 PPM and oxygen ions), thereby removing the metal. A photoresist residue or other foreign matter on the upper surface of layer 18. Referring to Figure 2H, a metal layer 22 having a thickness between 5 microns and 25 microns is formed by electroplating on the photoresist layer opening m 15 1353652 layer 18. The metal layer 22 includes at least one of copper, nickel or gold, or a group of the plurality of layers, for example, the metal layer 22 may be a single layer metal structure of a gold layer, a single layer metal structure of a copper layer, a composite layer metal structure (copper/nickel) composed of a copper layer and a recording layer on the copper layer, or a copper layer, a recording layer on the copper layer, and a gold layer on the nickel layer The composite layer metal structure (copper/nickel/gold) is composed. In addition, the method of forming the metal layer 22 may also include an electroless plating process. Taking the electroplating process to form the metal layer 22 as an example, the metal layer 22 can be formed by the following four methods: a. plating a copper layer having a thickness between 5 micrometers and 25 micrometers in a plating solution containing a copper sulfate (CuS04) solution. On a metal layer 18 of material such as copper. b. plating a copper layer on a metal layer 18 of a material such as copper with a plating solution containing a copper sulfate (CuS04) solution, and then plating a nickel layer on the copper layer with a plating solution containing a nickel sulfate (NiS04) solution. . The thickness of the copper layer is, for example, between 4 μm and 25 μm, and the thickness of the nickel layer is, for example, between 0.5 μm and 3 μm. c. electroplating a copper layer on a metal layer 18 of a material such as copper with a plating solution containing a copper sulfate (CuS04) solution, and continuing to electroplate a nickel layer in the copper layer with a plating solution containing a nickel sulfate (NiS04) solution. Then, a gold layer is electroplated on the recording layer with a plating solution containing a solution of gold sulfite (Na3Au(S03)2). Wherein, the thickness of the copper layer is, for example, between 4 micrometers and 25 micrometers, and the thickness of the nickel layer is, for example, one of 0.5 micrometers to 3 micrometers; and the thickness of the gold layer is, for example, between 〇.〇. 5 microns to 0.2 micros. 16 1353652. d. A gold layer having a thickness of between 5 micrometers and 25 micrometers of electroplating solution containing a solution of sodium sulfite gold (Na3Au(S03)2) is applied to a metal layer 18 of a material such as gold. Referring to FIG. 21, after the metal layer 22 is formed, the photoresist layer 20 is subsequently removed, and the photoresist layer 20 is removed by, for example, removing plasma using oxygen plasma (02 plasma) or using an organic solvent ( For example, an organic solvent containing an amino compound is removed. In addition, after removing the photoresist layer 20, the metal layer 22 and the metal layer 18 may be cleaned by using a plasma (for example, a plasma containing oxygen ions or a plasma containing a fluoride ion concentration of less than 200 PPM and oxygen ions) to remove the metal. A photoresist residue or other foreign matter on the upper surface of the layer 22 and the upper surface of the metal layer 18. Continuing to refer to FIG. 2J, the metal layer 18 and the adhesion/diffusion barrier layer 16 that are not under the metal layer 22 are removed. Wherein, the manner of removing the metal layer 18 and the adhesion/diffusion barrier layer 16 not under the metal layer 22 is removed by a money engraving method, and the engraving method can be divided into dry etching and wet etching ( Wet etching) two kinds. The best way to remove the adhesion/diffusion barrier layer 16 is to include a chemical plasma etch, a splatter etch (such as a high-pressure argon splatter etch), and a chemical gas etch. For example, in the removal of the metal layer 18, it can be removed by a wet chemical etching process, a sputtering process, or an ion milling process. Moreover, when the material of the metal layer 18 is gold, it can be removed by etching using an iodine-containing etching solution (for example, an etching solution containing potassium iodide), and when the material of the metal layer 18 is copper, it can be used with a -·II circle. Round _ , , ^^^» Round _ · ** · · — — · 一 - » *&gt; , _ _ ·—— : · 17 1353652 Ammonium hydroxide (NH4〇H) etching solution is removed by etching. In the removal of the adhesion/diffusion barrier layer 16, for example, it is removed by a reactive ion silver engraving (RIE) process, a sputtering etch process, or an ion milling process. • Therefore, the present invention can form at least one metal line 24 on the germanium-containing dielectric layer 14, 14 and the opening 1 exposed to the metal layer 10, the metal line 24 is formed by an adhesion/diffusion barrier layer 16, A metal layer 18 on the adhesion/diffusion barrier layer 16 and a metal layer 22 on the metal layer 18 are formed, and the thickness tl is between 5 micrometers and 27 micrometers. After removing the metal layer 18 and the adhesion/diffusion barrier layer 16 which are not under the metal layer 22, a protective layer 32 is formed on the metal line 24 and the germanium-containing dielectric layer 14, and is transparent to the protective layer. A method in which the opening 32a exposes the metal line 24 and the protective layer 32 and the opening 32a are formed as follows. However, the present invention may also be formed in the protective layer 32 without any openings 32a exposing the metal lines 24. The first method for forming the protective layer and the opening is as shown in Fig. 3A. First, a plasma-reinforced chemical vapor deposition (PECVD) is used to form a nitrogen arsenic having a thickness ranging from 〇.丨micron to 〇·5 μm. The compound layer 26 is formed on the metal line 24 with a ruthenium-containing dielectric layer (4 (for example, a ruthenium compound layer or a ruthenium oxynitride layer), followed by plasma enhanced chemical vapor deposition (PECVD) to form a thickness of 〇. A silicon oxide layer 28 between j microns and 〇 5 microns is formed on the yttrium compound layer 26 and finally formed by plasma enhanced chemical vapor deposition (PEcVD) to a thickness of between 0.5 μm and 1.5 μm. The layer of the arsenazo compound is in the layer of the oxonium halide 28 ° 18 1353652. Therefore, the protective layer 32 is composed of a layer of a ruthenium compound compound 26, an oxonium compound layer 28 and a ruthenium compound layer 30. . Further, a manner of forming at least one opening 32a in the protective layer 32 and exposing the metal wiring 24 (e.g., a copper layer, a nickel layer or a gold layer exposing the metal wiring 24) will be described below. The first way of forming the opening 32a is shown in Figures 3B to 3D. First, as shown in FIG. 3B, a photoresist layer 34 is formed on the ytterbium compound layer 30 of the protective layer 32, and then the photoresist layer 34 is patterned by exposure and development processes to form at least one photoresist layer opening 34a. A layer of nitrogen bismuth compound 30 over the metal line 24 is exposed within the photoresist layer 34. The method of forming the photoresist layer 34 is formed, for example, by a spin coating process or by a lamination process, and in the overdriving of the patterned photoresist layer 34, for example, doubling (IX) The stepper is exposed or exposed to the exposure using a double (IX) contact aligner. Referring to FIG. 3C, the yttrium compound layer 30, the yttrium compound layer 28 and the yttrium compound layer 26 under the photoresist layer opening 34a are sequentially removed to form at least one opening 32a in the protective layer 32 and exposed. Metal line 24 (e.g., a copper layer, a nickel layer, or a gold layer that exposes metal lines 24). The manner of removing the nitrogen argon compound layer 30, the oxon compound layer 28 and the yttrium compound layer 26 under the photoresist layer opening 34a is, for example, removed by etching, and is removed by reactive ion etching (RIE) process etching. - Good way. · Referring to FIG. 3D, the photoresist layer 34 is removed, and the photoresist layer 34 is removed by, for example, removing plasma using oxygen ions or using an organic solvent (for example, containing an amino compound). Organic solvent) removed. In addition, after removing H-thickness 34-彳4"jrm垔, for example, Γ Τ-1—1 &quot;* w- τ__ _ ·. · — · · · ~ — - - «- · — — * — ···. **-·»**, 19 1353652 Plasma containing oxygen ions or plasma containing fluoride ions with a concentration of less than 200 PPM and oxygen ions) The metal line 24 exposed by the cleaning opening 32a is removed A photoresist residue or other foreign matter on the upper surface of the metal line 24. The second way of forming the opening 32a is shown in Figs. 3E to 3F. First, referring to FIG. 3E, spin coating iii forms a polymer layer 36 on the nitrogen bismuth compound layer 30 of the protective layer 32, followed by baking, exposure, and development. The polymer layer 36 is patterned to form at least one polymer layer opening 36a within the polymer layer 36 and expose the nitrogen bismuth compound layer 30 over the metal line 24. In the process of patterning the polymer layer 36, for example, exposure is performed by a double (IX) stepper or by a double (1X) contact aligner. Further, in a nitrogen atmosphere or an oxygen-free environment, a curing process is used at a temperature between 200 ° C and 290 ° C, between 290 ° C and 330 ° C or between 330 ° C. To 400. (: The polymer layer 36 is hardened between and the hardening process is performed for a period of between 30 minutes and 2 hours. The polymer layer 36 is, for example, selected from the group consisting of polyimide (PI) and phenyl ring. One of benzocyclobutane (BCB), polyurethane, epoxy resin, polyparaxylene polymer, welding cap material, elastic material or porous dielectric material, and hardened polymer The thickness of the layer 36 is, for example, between 5 micrometers and 30 microseconds. For example, the polymer layer 36 may be a polyimide layer having a thickness of between 5 micrometers and 30 micrometers or a thickness of 5 micrometers to A stupid cyclobutene layer between 30 microns. Referring to Figure 3F, the polymer layer opening 36a is removed sequentially - - - ** - - - - · · · - - -------., , — · '* ~ . 子—.圆圆·. Circle *^^**^^ * I _ I IM· , I circle · ·- ·*_» V - — ~ ~ ' ---·-·*τϊ- . - — '一·1 &quot; - ·· - · · - · - ____.. — .r~iz 20 1353652 The yttrium compound layer 30 And an oxonium compound layer 28 and a yttrium compound layer 26 to form at least one The port 32a is in the protective layer 32 and exposes a metal line 24 (e.g., a copper layer, a nickel layer or a gold layer exposing the metal line 24). wherein - the nitrogen bismuth compound layer 30, oxonium under the polymer layer opening 36a is removed. The manner of the compound layer 28 and the nitrogen argon compound layer 26 is, for example, removed by etching, and is preferably removed by reactive ion etching (RIE) process etching. Further, the above-mentioned nitrogen bismuth compound layer 26 may also be composed of a oxynitride compound. Layer substitution, that is, plasma enhanced chemical vapor deposition (PECVD) to form a layer of oxynitride compound having a thickness between 0.1 micrometers and 0.5 micrometers on metal line 24 and a germanium containing dielectric layer 14 (eg, nitrogen) On the bismuth layer or the oxynitride layer, followed by plasma enhanced chemical vapor deposition (PECVD) to form an oxonium compound layer 28 having a thickness between 0.1 μm and 0.5 μm. On the ruthenium compound layer, plasma-reinforced chemical vapor deposition (PECVP) is continuously used to form a ruthenium nitride compound layer 3 having a thickness of between 0.5 μm and 1.5 μm on the oxonium compound layer 28, and then proceeding. Figure 3B above to The steps described in the 3D diagram or the steps described in the above FIG. 3E to FIG. 3F are not described in detail herein, but those skilled in the art can implement the same by the above description. For the protection of drawers and recitations, please refer to Figure 4A, first to form a layer of arsenide compound 38 between 〇丨μm and 〇5μm by plasma enhanced chemical vapor deposition (PECVD). On the metal line 24 and the ruthenium-containing dielectric layer i4 (for example, a ruthenium compound layer or an It oxy-compound layer), the plasma-enhanced chemistry is further used to form 21 1353652 oxygen having a thickness of between 0.1 μm and 0.5 μm. The ruthenium compound layer 40 is on the ruthenium compound layer 38, followed by formation of a spin on glass (SOG) layer 42 on the oxonium compound layer 40. Continuing, the spin-on glass layer 42 is etched using an etch process to expose the oxonium compound layer 40. Further, a nitrogen arsenide compound layer 44 having a thickness of between 0.5 μm and 1.5 μm is formed on the spin-on glass layer 42 and the exposed oxonium compound layer 40 by plasma enhanced chemical vapor deposition (PECVD). on. Therefore, the protective layer 32 is composed of a ruthenium nitride compound layer 38, an oxonium compound layer 40, a spin-on glass layer 42, and a ruthenium nitride compound layer 44. Further, a manner of forming at least one opening 32a in the protective layer 32 and exposing the metal wiring 24 (e.g., a copper layer, a nickel layer or a gold layer exposing the metal wiring 24) will be described below. The first way of forming the opening 32a is shown in Figs. 4B to 4E). First, as shown in FIG. 4B, a photoresist layer 46 is formed on the nitrogen-germanium compound layer 44 of the protective layer 32, and then through a process such as exposure and development to form a photoresist layer 46 to form at least one photoresist layer opening. 46a is within the photoresist layer 46 and exposes the nitrogen bismuth compound layer 44 above the metal line 24. Wherein, the manner tb of forming the photoresist layer 46 is formed by a spin coating process or by a lamination process, and in the patterned photoresist layer 46, for example, using — (IX) The exposure machine (stepper) performs exposure with a double (1X) contact aligner to expose the exposure. Please refer to FIG. 4C 热 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ , , &amp; in the protective layer 32 and expose the metal line ^ exposed metal recorded Di, two, Λ. ~ ''~~~~~'^. a ''--ά.~% 24 copper layer, Record layer or gold layer). Wherein, 22 1353652 removes the yttrium compound layer 44, the yttrium compound layer 40 and the yttrium compound layer 38 under the photoresist layer opening 46a, for example, by etching, and is removed by reactive ion etching (RIE) process etching. Is the preferred way. Referring to FIG. 4D, the photoresist layer 46 is removed, and the photoresist layer 46 is removed by, for example, removing plasma using oxygen ions or using an organic solvent (for example, containing an amino compound). Organic solvent) removed. In addition, after removing the photoresist layer 46, the metal line 24 exposed by the opening 32a may be cleaned by using a plasma (for example, a plasma containing oxygen ions or a plasma containing a fluoride ion concentration of less than 200 PPM and oxygen ions). The photoresist residue or other foreign matter on the upper surface of the metal line 24 is removed. The second way of forming the opening 32a is shown in Figs. 4E to 4F. First, as shown in FIG. 4E, a polymer layer 48 is spin-coated to form a polymer layer 48 on the protective layer 32, and then the polymer layer 48 is patterned by baking, exposure and development to form at least one. The polymer layer opening 48a is within the polymer layer 48 and exposes the nitrogen bismuth compound layer 44 above the metal line 24. In the process of patterning the polymer layer 48, for example, a one-time (IX) stepper is used for exposure or a double (IX) contact aligner is used for exposure. Further, in a nitrogen atmosphere: or an anaerobic environment, a curing process is used at temperatures between 200 ° C and 290 ° C, between 290 ° C and 330 ° C or between 330 °. The polymer layer 48 is hardened between C and 400 ° C, and the hardening process is carried out for a period of between 30 minutes and 2 hours. Wherein, the polymer layer 48 is, for example, selected from the group consisting of polyimine (PI), phenylcyclobutene (BCB), polyurethane, epoxy Lesin, polyparaxylene, high fat t, _5 drought Bios, _f"t raw material or porous, — . , 1 I ·- - Ύ - - - ' : - - - - - - - - · · - - ' · * ' * - - __ -_** * • Two--'- 23 1353652 one of the dielectric materials, and the thickness of the hardened polymer layer 48 is, for example, between 5 micrometers and 30 micrometers, for example, the polymer layer 48 may be 5 micrometers thick. A layer of polyamidene between 30 microns or a layer of phenylcyclobutene having a thickness between 5 microns and 30 microns. Referring to FIG. 4F, the yttrium compound layer 44, the yttrium compound layer 40 and the yttrium compound layer 38 under the polymer layer opening 48a are sequentially removed to form at least one opening 32a in the protective layer 32 and exposed. Metal line 24 (e.g., a copper layer, a nickel layer, or a gold layer that exposes metal lines 24). The manner of removing the nitrogen argon compound layer 44, the oxon compound layer 40 and the yttrium compound layer 38 under the polymer layer opening 48a is, for example, removed by etching, and is removed by reactive ion etching (RIE) process etching. Good way. In addition, the above-mentioned nitrogen bismuth compound layer 38 may also be replaced by a oxynitride compound layer, that is, a plasma reinforced chemical vapor deposition (PECVD) is used to form a oxynitride compound layer having a thickness of between 0.1 μm and 0.5 μm. On the metal line 24 and the germanium-containing dielectric layer 14 (for example, a layer of a cerium nitride compound or a layer of oxynitride compound), the use of enhanced plasma chemical vapor deposition (PECVD) continues to form a thickness of between 0.1 micrometers and 0.5 micrometers. An inter-phosphonium compound layer 40 is on the oxynitride compound layer, followed by a spin-on glass (800) layer 42 on the oxon compound layer 40, and the spin-on glass layer 42 is further etched using an etching process. Exposing the oxonium compound layer 40 to form a ruthenium nitride compound layer 44 having a thickness of between 0.5 μm and 1.5 μm on the spin-on glass layer 42 and the exposed oxon compound layer 40, followed by The steps described in the above 4B to 4D or the steps described in the above 4E to 4F are not described in detail herein, but the skilled person can Explain and implement accordingly. The third method for forming the protective layer and the opening is as shown in FIG. 5, first forming a layer of a nitrogen arsenide compound having a thickness of between 0.1 μm and 0.5 μm by plasma enhanced chemical vapor deposition (PECVD). On the metal line 24 and the germanium-containing dielectric layer 14 (for example, a layer of a cerium nitride compound or a layer of oxynitride compound), plasma-reinforced chemical vapor deposition (PECVD) is continuously used to form a thickness between 0.1 μm and 0.5 μm. The oxonium compound layer 40 is on the yttrium compound layer 38. Next, spin coating forms a polymer layer 50 on the oxon compound layer 40, and in a nitrogen atmosphere or an oxygen-free environment, using a curing process at a temperature between 200 ° C and 290 ° C, The polymer layer 50 is hardened between 290 ° C and 330 ° C or between 330 ° C and 400 ° C, wherein the hardening process is carried out for a period of between 30 minutes and 2 hours, and the polymer layer 50 For example, polyimine (PI) or phenylcyclobutene (BCB). Continuing, the polymer layer 50 is etched using an etching process to expose the oxonium compound layer 40. Further, a ruthenium nitride compound layer 44 having a thickness of between 0.5 μm and 1.5 μm is formed on the polymer layer 50 and the exposed oxonium compound layer 40 by plasma enhanced chemical vapor deposition (PECVD). Therefore, the protective layer 32 is composed of a ruthenium nitride compound layer 38, an oxygen chopped compound layer 40, a polymer layer 50 and a nitrogen pulverized compound layer 44. In addition, regarding the manner in which at least one opening 32a is formed in the protective layer 32 and the metal line 24 is exposed (for example, a copper layer, a nickel layer or a gold layer exposing the metal line 24), please refer to the above FIG. 4B to FIG. 4F. The related description will not be described in detail here. ___________ 25 1353652 In addition, the above-mentioned nitrogen compound layer 38 may also be replaced by a oxynitride compound layer, that is, by plasma enhanced chemical vapor deposition (PECVD). Forming a layer of oxynitride compound having a thickness between 0.1 μm and 0.5 μm on the metal line 24 and the germanium-containing dielectric layer 14 (for example, a layer of a ruthenium compound or a layer of oxynitride compound), continuing to utilize the plasma Enhanced chemical vapor deposition (PECVD) to form an oxonium compound layer having a thickness of between 0.1 μm and 0.5 μm on the oxynitride compound layer, followed by formation of a polymer layer 5 〇 in the oxygen stone compound On layer 40, the polymer layer 5 is then etched using an etching process to expose the oxonium compound layer 40, and then plasma-reinforced chemical vapor deposition (PECVD) is used to form a thickness of between 0.5 μm and 1.5 μm. Nitrogen The compound layer 44 is formed on the polymer layer 50 and the exposed oxon compound layer 40, and finally the steps described in the above FIGS. 4B to 4D or the steps described in the above 4E to 4F are performed. It is not described in detail here, however, those skilled in the art can implement it by the above description. The fourth type of protective layer and the hot mouth method

請參閱第6A圖所示,先利用電漿加強型化學氣相沉 積(PECVD)形成厚度介於〇.丨微米至〇 5微米之間的一氮矽 化合物層52在金屬線路24上與含矽介電層14(例如氮矽 化合物層或氮氧矽化合物層)上,繼續利用電漿加強型化學 氣相沉積(PECVD)形成厚度介於〇丨微米至〇 5微米之間的 一氧矽化合物層54在氮矽化合物層52上,接著形成一旋 塗式玻璃(SOG)層56在氧矽化合物層54上之後利用一Referring to FIG. 6A, first, a plasma enhanced chemical vapor deposition (PECVD) is used to form a layer of a ruthenium nitride compound 52 having a thickness between 〇.丨micron and 〇5 micrometers on the metal line 24 and containing germanium. On the dielectric layer 14 (for example, a layer of a ruthenium compound or a layer of oxynitride compound), plasma-enhanced chemical vapor deposition (PECVD) is continued to form an oxonium compound having a thickness of between 〇丨micrometers and 〇5 micrometers. Layer 54 is on the yttrium compound layer 52, followed by formation of a spin on glass (SOG) layer 56 on the oxon compound layer 54.

蝕刻製程蝕刻旋塗式玻璃層56,以暴露出氧矽化合物層 二气形成厚 26 1353652 度介於0·2微米至0.5微米之間的氧碎化合物層58在旋 塗式玻璃層56上與暴露出之氧矽化合物層54上。再來, 利用電漿加強型化學氣相沉積(PECVD)形成厚度介於〇.5 微米至1.5微米之間的一氮矽化合物層60在氧矽化合物層 58上。 因此,保護層32是由一氮矽化合物層52、一氧矽化 合物層54、一旋塗式玻璃層56、一氧矽化合物層58與一 氮矽化合物層60所構成。另,有關形成至少一開口 32a 在保護層32内並暴露出金屬線路24(例如暴露出金屬線路 24的銅層.、錄層或金層)的方.式敘述如下。 第一種形成開口 32a的方式請參閱第6B圖至第6D圖 所示。首先請參閱第6B圖所示,形成一光阻層62在保護 層32之氮石夕化合物層60上,接著透過曝光與顯影等製程 圖案化光阻層62,以形成至少—光阻層開口 62a在光阻層 62内並暴露出金屬線路24上方的氮矽化合物層6〇。其中, 形成光阻層62的方式比如是以旋塗(spin c〇aUng)製程形 成或是以壓合(lamination)製程形成,而在圖案化光阻層62 龉過程中比如是利用—倍(丨χ)之曝光機(stepper)進行曝光 或·疋利用.倍(IX)之對準曝光機(c〇ntact aligner)進曝光。 請參閲第6C圖所示,依序去除光阻層開口 62&amp;下方 的氮矽化合物層60、氡矽化合物層58、氧矽化合物層w 與氮石夕化合物層52’以形成至少一開〇 32a在保護層h 内並暴露出金屬線路24(例如暴露出金屬線路24的铜層、 :去除光阻層開口 02a下方的氮矽各a ----------.-½. / 27 1353652 物層60、氧矽化合物層58、氧矽化合物層54與氮矽化合 物層52之方式比如是以蝕刻方式去除,並以反應性離子蝕 刻(RIE)製程蝕刻去除為較佳方式。 再來請參閲第6D圖所示,去除光阻層62,而去除光 阻層62的方式比如是利用含有氧離子之電漿(02 plasma) 去除或是利用有機溶劑(例如含有氨基化合物之有機溶劑) 去除。此外,在去除光阻層62之後,可利用電漿(例如是 含有氧離子之電漿或是含有氟離子濃度小於200PPM與氟 離子之電漿)清洗開口 32a所暴露出之金屬線路24,藉以 去除金屬線路24上表面之光阻殘留物或其它異物。 第二種形成開口 32a的方式請參閱第6E圖至第6F圖 所示。首先請參閱第6E圖所示,旋塗形成一聚合物層64 在保護層32之氮矽化合物層60上,接著透過烘烤、曝光 與顯影等製程圖案化聚合物層64,以形成至少一聚合物層 開口 64a在聚合物層64内並暴露出金屬線路24上方的氮 矽化合物層60。在圖案化聚合物層64的過程中比如是利 用一倍(IX)之曝光機(stepper)進行曝光或是利用一倍(IX) 之對準爆—光機(contact aligner)進曝光。再來」-於—氮:氣篇境 或無氧環境中,利用硬化(curing)製程在溫度介於200°C至 290°C之間、介於290°C至330°C之間或是介於330°C至400 °C之間硬化聚合物層64,且進行硬化製程的時間係介於30 分鐘至2小時之間。其中,聚合物層64比如是-選自聚醯亞 胺(PI)、苯基環丁烯(BCB)、聚氨脂、環氧樹脂(epoxy resin)、聚對二甲苯類高分子 ' 焊罩材料、梦性蛘料或多孔 28 1353652 性介電材料其中之一,且硬化後的聚合物層64厚度比如是 介於5微米至30微米之間,例如聚合物層64可以是厚度 介於5微米至30微米之間的一聚醯亞胺層或是厚度介於5 微米至30微米之間的一苯基環丁烯層。 請參閱第6F圖所示,依序去除聚合物層開口 64a下方 的氮矽化合物層60、氧矽化合物層58、氧矽化合物層54 與氮矽化合物層52,以形成至少一開口 32a在保護層32 内並暴露出金屬線路24(例如暴露出金屬線路24的銅層、 錦層或金層)。其中,去除聚合物層開口 64a下方的氮矽化 合物層60、氧矽化合物層58、氧石夕化合物層54與氮矽化 合物層52之方式比如是以蝕刻方式去除,並以反應性離子 蝕刻(RIE)製程蝕刻去除為較佳方式。 另,上述的氮矽化合物層52亦可由氮氧矽化合物層取 代,亦即利用電漿加強型化學氣相沉積(PECVD)形成厚度 介於0.1微米至0.5微米之間的一氮氧矽化合物層在金屬 線路24上與含矽介電層14(例如氮矽化合物層或氮氧矽化 合物層)上,繼讀利用電漿加強型化學氣相沉積(PECVD) 形成厚度介於0.1微米至0.5微米之間的一氡梦化洽物層 . - - 54在此氮氧矽化合物層上,接著形成一旋塗式玻璃(SOG) 層56在氧矽化合物層54上,之後利用一蝕刻製程蝕刻旋 塗式玻璃層56,以暴露出氧矽化合物層54,繼續利用電漿 加強型化學氣相沉積(PECVD)形成厚度介於0.2微米至0.5 微米之間的一氧矽化合物層58在旋塗式玻璃層56上與暴 露出之氧矽化合物層54上,再參利用電漿加鱼g坐學氣相 29 1353652 沉積(PECVD)形成厚度介於0.5微米至1.5微米之間的一氮 矽化合物層60在氧矽化合物層58上,最後進行上述第6B 圖至第6D圖所述之步驟或是進行上述第6E圖至第6F圖 所述之步驟,在此不再詳加說明,然熟習該技術者當可藉 由上述的說明而據以實施。 _ 第5種形成保護層及開口的方法 請參閱第7圖所示,先利用電漿加強型化學氣相沉積 (PECVD)形成厚度介於0.1微米至0.5微米之間的一氮矽化 合物層52在金屬線路24上與含矽介電層14(例如氮矽化 合物層或氮氧矽化合物層)上,繼續利用電漿加強型化學氣 相沉積(PECVD)形成厚度介於0.1微米至0.5微米之間的一 氧矽化合物層54在氮矽化合物層52上。接著,旋塗形成 一聚合物層66在氧矽化合物層54上,並於氮氣環境或無 氧環境中,利用硬化(curing)製程在溫度介於200°C至290 °C之間、介於290°C至330°C之間或是介於330°C至400°C 之間硬化聚合物層66,其中進行硬化製程的時間係介於30 分鐘至2小時之間,且聚合物層66比如是聚醯亞胺(PI)或 苯墓環丁烯(BCB)。之後,利用一蝕刻製程T姓刻聚舍物層 66,以暴露出氧矽化合物層54。繼續,利用電漿加強型化 學氣相沉積(PECVD)形成厚度介於0.2微米至0.5微米之間 的一氧矽化合物層58在聚合物層66上與暴露出的氧矽化 合物層54上。再來,利用電漿加強型化學氣相沉積(PECVD) 形成厚度介於0.5微米至1.5微米之間的一氮矽化合物層 £0在冬—石夕化會物層58上。 30 1353652 -因此,-保護層32是由一氮石夕化合物層52、一氧石夕化 合物層54、一聚合物層66、一氧梦化合物層58與一氮發 化合物層60所構成。有關形成至少一開口 32a在保護層 32内並暴露出金屬線路24(例如暴露出金屬線路24的銅 層、鎳層或金層)的方式,請參閱上述第6B圖至第6F圖 的相關說明,在此不再詳加說明。 另,上述的氮碎化合物層52亦可由氮氡石夕化合物層取 代,亦即利用電槳加強型化學氣相沉積(PECVD)形成厚度 介於0.1微米至0.5微米之間的一氮氧矽化合物層在金屬 線路24上與含矽介電層14(例如氮矽化合物層或氮氧矽化 合物層)上,繼續利用電漿加強型化學氣相沉積(PECVD) 形成厚度介於0.1微米至0.5微米之間的一氧矽化合物層 54在此氮氧硬化合物層上,接著形成一聚合物層66在氧 矽化合物層54上,之後利用一蝕刻製程蝕刻聚合物層66, 以暴露出氧矽化合物層54,繼續利用電漿加強型化學氣相 沉稂(PECVD)形成厚度介於0.2微米至0.5微米之間的一氧 矽化合物層58在聚合物層66上與暴露出之氧矽化合物層 54上,再來利用電漿加強型化學氣相沉積(PECVD)形成厚 度介於0.5微米至1.5微米之間的一氮矽化合物層60在氧 矽化合物層58上,最後進行上述第6B圖至第6D圖所述 之步驟或是進行上述第6E圖至第6F圖所述之步驟,在此 不再詳加說明,然熟習該技術者當可藉由上述的說明而據 以實施。 色6種形成保嗖上竺支步 —一— 31 1353652 請參閱第8A圖所示,利用電漿加強型化學氣相沉積 (PECVD)形成厚度介於0.5微米至1.5微米之間的一氮矽化 合物層68在金屬線路24上與含矽介電層14(例如氮矽化 合物層或氮氧梦化合物層)上。 因此,保護層32是由一氮矽化合物層68所構成。另, 有關形成至少一開口 32a在保護層32内並暴露出金屬線路 24(例如暴露出金屬線路24的銅層、鎳層或金層)的方式敘 述如下。 第一種形成開口 32a的方式請參閱第8B圖至第8D圖 所示。首先請參閱第8B圖所示,形成一光阻層70在氮矽 化合物層68上,接著透過曝光與顯影等製程圖案化光阻層 70,以形成至少一光阻層開口 70a在光阻層70内並暴露出 金屬線路24上方的氮矽化合物層68。其中,形成光阻層 70的方式比如是以旋塗(spin coating)製程形成或是以壓合 (lamination)製程形成,而在圖案化光阻層70的過程中比 如是利用一倍(IX)之曝光機(stepper)進行曝光或是利用一 倍(IX)之對準曝光機(contact aligner)進曝光。 請參閱第8C圖所示,去除光阻層開口 7_0a下-方的氮 矽化合物層68,以形成至少一開口 32a在保護層32内並 暴露出金屬線路24。其中,去除光阻層開口 70a下方的氮 矽化合物層68之方式比如是以银刻方式去除,並以反應性 離子蝕刻(RIE)製程蝕刻去除為較佳方式。 再來請參閱第8D圖所示,去除光阻層70,而去除光 阻層70的方式比如是利用含考氧,子之電一赛p]_asjna}_ 32 1353652 去除或是利用有機溶劑(例如含有氨.基化合物之有機溶劑) 去除。此外,在去除光阻層70之後,可利用電漿(例如是 含有氧離子之電漿或是含有氟離子濃度小於200PPM與氧 離子之電漿)清洗開口 32a所暴露出之金屬線路24,藉以 去除金屬線路24上表面之光阻殘留物或其它異物。 第二種形成開口 32a的方式請參閱第8E圖至第8F圖 所示。首先請參閱第8E圖所示,旋塗形成一聚合物層72 在氮矽化合物層68上,接著透過烘烤、曝光與顯影等製程 圖案化聚合物層72,以形成至少一聚合物層開口 72a在聚 合物層72内並暴露出金屬線路24上方的氮矽化合物層 68。在圖案化聚合物層72的過程中比如是利用一倍(IX) 之曝光機(stepper)進行曝光或是利用一倍(1父)之對準曝光 機(contact aligner)進曝光。再來,於氮氣環境或無氧環境 中,利用硬化(curing)製程在溫度介於200°C至290°C之 間、介於290°C皇330°C之間或是介於330°C至400°C之間 硬化聚合物層72,且進行硬化製程的時間係介於30分鐘 至2小時之間。其中,聚合物層72比如是選自聚醯亞胺 (PI)、苯基環丁烯(BCB)、聚氨脂、環氧樹脂(epoxy resin)、 聚對二曱苯類高分子、焊罩材料、彈性材料或多孔性介電 材料其中之一,且硬化後的聚合物層72厚度例如是介於-5 微米至30微米之間,例如聚合物層72可以是厚度介於5 微米至30微米之間的一聚醯亞胺層或是厚度介於5微米至 30微米之間的一苯基環丁烯層。 ____讀參閱第8F歷戶斤$,去除聚合物層開口 72a下方的氮 33 1353652 矽化合物層68,以形成至少一開口 32a在保護層32内並 暴露出金屬線路24 »其中,去除聚合物層開口 72a下方的 氮矽化合物層68之方式比如是以蝕刻方式去除,並以反應 娃離子蝕刻(RIE)製程蝕刻去除為較佳方式。 综上所述’一保護層32形成在金屬線路24上與含矽 介電層14(例如氮矽化合物層或氮氧矽化合物層)上,此保 護層32可以保護半導體元件4、線路結構6與金屬線路24 免於受到濕氣與外來離子污染物(foreign ion contamination)的破壞’也就是說佯護層32可以防止移動 離子(比如疋鈉離子)、水氣(m〇isture)、過渡金屬(比如是 金、銀、銅)及其他雜質(impurity)穿透,而損壞保護層32 下方的半導體元件4(例如電晶體、多晶妙電阻元件或多晶 石夕-多晶♦電容元件)、線路結構6或金屬線路%。其中,「下 方」-詞在本發明中是表示位在某物下面並與之接觸,或 是表示位在某物下面但未與之接觸。 開口 32a的最大橫向尺寸比如是介於2微米至%微米 之間’或是介於30微米至300微米之間。此外,開口 32&amp; 的形狀可以是圓形、正方形或五邊以上之多邊形,具上述 開口 8a的最大橫向尺寸是指圓形開口的直徑尺寸、正方形 開口的邊長尺寸或五邊以上之多邊形開口的最長對角線尺 寸。又’開π 32a的形狀也可以是長方形,且此長方形開 口的寬度尺寸是介於2微米至40微米之間。 另,畲金屬線路24為一重配置線路(re distributi〇n 口 32a 所拳葶出之 _ 34 1353652 金屬線路24的位置係不同於開口 14a所暴露出之金屬層 10的位置。 又,金屬線路24也可以是一連接線路(interconnecting metal trace),所以本發明可經由金屬線路24連接兩開口 14a或兩開口 14a以上所暴露出之金屬層10,形成方式敘 述如下。首先請參閱第9A圖所示,以第2A圖所述之内容, 形成一含梦介電層14(例如氮梦化合物層或氮氧碎化合物 層)在線路結構6上方及介電層8上方,且含矽介電層14 内至少有二開口 14a分別暴露出線路結構6的至少二金屬 層10,而有關含矽介電層14、開口 14a以及形成含矽介電 層14與開口 14a等相關内容,請參閱上述第2A圖至第2C 圖的說明,在此不再詳加說明。 請參閱第9B圖所示,以第2D圖至第2E圖所述之内 容,形成一黏著/擴散阻障16在含矽介電層14(例如氮矽化 合物層或氮氡矽化合物層)上與二開口 14a分別所暴露出 之二金屬層10上,以及形成一金屬層18在黏著/擴散阻障 層16上,而有關黏著/擴散阻障16與金屬層18的敘述, 請參閱第2D圖至第2E圖的說明,在此不再詳加說明。 請參閱第9C圖所示,形成一光阻層74在金屬層18 上,並透過曝光與顯影等製程圖案化光阻層74,以_形_成一 光阻層開口 74a在光阻層74内並暴露出金屬層18(包括暴 露出位在二開口 14a分別所暴露出之二金屬層10上方的金 屬層18)。其中,形成光阻層74的方式例如是以旋塗(spin coating)製程形成查矣見壓合(lamination}製程形成,而在 35 1353652 圖案化光阻層74的過程中比如是利用一倍(l-Χ)之-曝光機 (stepper)進行曝光或是利用一倍(IX)之對準曝光機(contact aligner)進行曝光。另,在顯影後可利用電漿(例如是含有 氧離子之電漿或是含有氟離子濃度小於200PPM與氧離子 之電漿)清洗光阻層開口 74a所暴露出之金屬層18,藉以 去除金屬層18上表面之光阻殘留物或+其它異物。 請參閱第9D圖所示,以第2H圖所述之内容,形成厚 度t2介於5微米至25微米之間的一金屬層22在光阻層開 口 74a所暴露出之金屬層18上,而有關金屬層22的敘述, 請參閱第2H圖的說明,在此不再詳加說明。 請參閱第9E圖所示,在形成金屬層22之後,接著去 除光阻層74,而去除光阻層74的方式比如是利用含有氧 離子之電漿(〇2 plasma)去除或是利用有機溶劑(例如含有 氨基化合物之有機溶劑)去除。此外,在去除光阻層74之 後,可利用電漿(例如是含有氧離子之電漿或是含有氟離子 濃度小於200PPM與氧離子之電漿)清洗金屬層22與金屬 層18,藉以去除金屬層22上表面與金屬層18上表面之光 阻殘留物或其它異物。 請參閱第9F圖所示,去除未在金屬層22下方的金屬 層18與黏著/擴散阻障層16。其中,有關去除未在金屬層 22下方之金屬層18與黏著/擴散阻障層16的方式請參閱 第2J圖的說明,在此不再詳加說明。 因此,本發明可形成連接兩開口 14a或兩開口 14a以 上所暴露出之金屬層1 〇_的_ 一金屬線路· Jl_.,全邊線_路24 —· &quot;' .·1 二一- -V—; .. ^ . 一一- 二_ . .·., —— — - 二 :-· V.-; ·- ·' . ... . * 36 1353652 疋由一黏^著/擴散阻障層16、位耷黏著/擴散阻障層16上的 金屬層18與位在金屬層18上的一金屬層22所構成,且 厚度t3介於5微米至27微米之間。 接著,於去除未在金屬層22下方的金屬層18與黏著/ 擴散阻障層16之後,形成一保護層32在金屬線路%上與 含矽介電層14(例如氮矽化合物層或氮氧矽化合物層)上, 並可透過位在保護層32内之至少一開口 32a暴露出金屬線 路24,或是保護層32内沒有任何開口 32a暴露出金屬線 路24。形成保護層32與開口 32a的方法,請參閱上述6 種「形成保護層及開口的方法」之說明,第9G圖係以盖 及開口的方法.形成.保護層32在金屬線路24 上與含矽介電層14上,且保護層32内沒有開口 3仏暴露 出此金屬線路24,然熟習該技術者當可藉由上述的說明, 以上述6種「形成保護層及開口的方法」之内容來據以實 施’且保護層32内亦可形成至少一開口 32a.暴露出金屬線 路24,進而連接外部電路,其中連接外部電路的方式比如 是利用一打線製程接合一打線導線(例如一金線或銅線)之 一端至開所暴露之金屬線路24上,而另一端則連接― 至外部電路。另,此外部電路可以是半導體晶片、印刷電 路板、軟板、含有陶瓷材料之基板、事先形成之被動元 件(discrete passive device)或玻璃基板,而印刷電路 板含有玻璃纖維,軟板則包括厚度介於3〇微米至2〇〇微米 之間的一聚合物層(例如聚醯亞胺)。 —的方式,本發明 37 1353652 亦可形成一接墊在一開口 14a所暴露出之金屬層10上,並 透過上述6種「形成保護層及開口的方法」形成一保護層 32在接墊上與含矽介電層14上,且位在保護層32内之一 開口 32a暴露出一接墊,而形成方式敘述如下。首先請參 閱第10A圖所示,以第2A圖、第2D圖與第2E圖所述之 内容,形成一含石夕介電層14(例如氮碎化合物層或氮氧石夕 化合物層)在線路結構6上方及介電層8上方,且位在含矽 介電層14内之至少一開口 14a暴露出線路結構6的至少一 金屬層10,而有關含碎介電層14、開口 14a以及形成含石夕 介電層14與開口 14a等相關内容,請參閱上述第2A圖至 第2C圖的說明,在此不再詳加說明。 接著,形成一黏著/擴散阻障16在含矽介電層14(例如 氮矽化合物層或氮氧矽化合物層)上與開口 14a所暴露出 之金屬層10上,以及形成一金屬層18在黏著/擴散阻障層 16上,而有關黏著/擴散阻障16與金屬層18的敘述,請 參閱第2D圖至第2E圖的說明,在此不再詳加說明。 請參閱第10B圖所示,形成一光阻層76在金屬層18 上,並透過曝光與顯敎等製程圖案化光阻層76」^_形成至 少一光阻層開口 76a在光阻層76内並暴露出位在開口 14a 所暴露出之金屬層10上方的金屬層18。其中,形成光阻 層76的方式例如是以旋塗(spin coating)製程形成或是以 屋合(lamination)製程形成,而在圖案化光阻層76—的-過程 中比如是利用一倍(IX)之曝光機(stepper)進行曝光或是利 —一倍(1X)之對準曝光機(contact aligner) it行曝光。另:― 38 1353652 在顯影後可利用電漿(例如是含有氧離子之電漿或是含有 氣離子濃度小於20〇PPM與氧‘子之電漿)清洗光阻層開 口 76a所暴露出之金屬層18,藉以去除金屬層18上表面 • 之光阻殘留物或其它異物。 • 請參閱第10C圖所示,以第2H圖所述之内容,形成 厚度介於5微米至25微米之間的一金屬層22在光阻層開 口 76a所暴露出之金屬層18上,而有關金屬層22的敘述, 明參閱第2H圖的說明,在此不再詳加說明。 請參閱第10D圖所示’在形成金屬層22之後,接著 去除光阻層76,而去除光阻層76的方式比如是利用含有 氧離子之電漿(〇2 plasma)去除或是利用有機溶劑(例如含 有氣基化合物之有機溶劑)去除。此外,在去除光阻層76 之後,可利用電漿(例如是含有氧離子之電漿或是含有氟離 子濃度小於200PPM與氧離子之電漿)清洗金屬層22與金 屬層18,藉以去除金屬層22上表面與金屬層18上表面之 • 光阻殘留物或其它異物。 請參閱第10E圖所示,去除未在金屬層22下方的金 屬層18與黏著/擴散阻障層16。其中,有關去除未在金屬 層22下方之金屬層18與黏著/擴散阻障層μ的方式請參 閱第2J圖的說明’在此不再詳加說明。 因此,本發明可形成用於連接外部電路的至少―接塾 78在開口 14a所暴露出之金屬層10上,此接墊78是由一 點著/擴散阻障層16、位在黏著/擴散阻障層16上的一金屬 與位在金屬層18上的一金屬層22所構成,且晟疮各 — ' ~------」~;,·_ ' — —r-r~一二 二;:;•二〜〜 _ 39 1353652 於5微米至27微米之間。其中,此外部電路可以是半導體 晶片、印刷電路板、軟板、含有陶瓷材料之基板、事先 形成之被動元件(discrete passive device)或玻璃 基板,而印刷電路板含有玻璃纖維,軟板則包括厚度介於 3〇微米至200微米之間的一聚合物層(例如聚醯亞胺)。 接著’於去除未在金屬層22下方的金屬層18與黏著/ 擴散阻障層16之後’形成一保護層32在接墊78上與含石夕 介電層14(例如氮矽化合物層或氮氧石夕化合物層)上,並透 過仅在保護層32内之一開口 32a暴露出接墊78。而形成 保護層32與開口 32a的方法,請參閱上述6種「形成保護 層及開口的方法」之說明,第10F圖係以第1種彬点 形成一保護層32在接墊78上與含石夕介電 層14上’且位在保護層32内之一開口 32a暴露出此接墊 78 ’然熟習該技術者當可藉由上述的說明,以上述6種「形 成保護層及開口的方法」之内容來據以實施。 另’透過接合打線導線至開口 32a所暴露出之接塾78 或是形成含鱗金屬層或金屬凸塊(例如金凸塊)於開口 32a 所暴露出之接塾78上方等方式,可使接塾78連接外部電 路,其中此外部電路可以是半導體晶片、印刷電路板、軟 板、含有陶瓷材料之基板、事先形成之被動元件 (discrete passive device)或玻璃基板,而印刷電路板 含有玻璃纖維,軟板則包括厚度介於3〇微米至2〇〇微米之 間的一聚合物層(例如聚醯亞胺)。 發上月_於^去述形成详羞層3_2感開的舟崎 1353652 後,接著可進行下列三種製程,敘述如下: 第一種製程 ~ 於完成上述保護層32或開口 32a的步驟後,接著切割 半導體基底2,以形成複數晶片,且這些晶片可進一步透 過打線製程接合一打線導線(其材質包括金、銅或鋁)之一 端至位在保護層32内之一開口 32a所暴露出之金屬線路 24(例如金屬線路24的銅層、鎳層或金層)上,而另一端則 連接至一導線架(leadframe)之一引腳(lead)或是一接墊,此 接墊可以是另一半導體晶片之一接墊、另一半導體基底上 方之一接墊、一有機基板上方之一接墊、一陶瓷基板上方 之一接墊、一矽基板上方之一接墊、一玻璃基板上方之一 接墊或一軟板上方之一接墊,且此軟板包括厚度介於30 辦米至200微米之間的一聚合物層。 本發明之打線製程所使用的打線強度比如是介於1〇〇 毫牛頓(mN)至1,000毫牛頓之間、介於200毫牛頓至1,000 毫牛頓之間或是介於200毫牛頓至500毫牛頓之間。最後, 在完成打線製程後,形成一聚合物材料,例如環氧樹脂或 聚醯亞胺,包覆打線導線。另,當金屬線路24為一重配置 線路(RDL)時,從俯視透視圖觀之,打線導線接合至金屬 線路24的位置係不同於開口 14a所暴露出之金屬層10的 位置。 第二種製程 於完成上述保護層32或開口 32a的步驟後,本發明可 形成另一金屬線路在保護層32上方並連接開口 32 a所暴 --一— 1 ~~. 1- · —: ·- : ~ 1353652 出之金屬.線路24,底下以「金屬線路24包括二連接線路 24a、24b」及「保護層32係~透ά笫1種形成保謨層及開口 的方式形成i的方式來進行說明,然熟習該技術者當可藉 由下列的說明,以上述6種「形成保護層及開口的方法」 之内容來據以實施,且金屬線路24亦不限定為二連接線 路。 請參閱第11A圖所示,形成厚度介於2,000埃 (angstrom)至5,000埃之間(較佳厚度則是介於2,500埃至 3,500埃之間)的一金屬層80在聚合物層36上與二聚合物 層開口 36a分別所暴露出之二連接線路24a、24b上,而此 金屬層80係作為黏著_/阻障層(adhesion/barrier layer),其 作用在於提供連接線路24a、24b與金屬材料間良好之接著 力,並可防止連接線路24a、24b與金屬材料間的擴散 (diffusion)反應。金屬層80的材質比如是選自鈦、鶴、姑、 錄、氮化鈦、鈦鶴合金、錄鈒合金、组、氮化组、絡、銅、 絡銅合金、金、鎮、始、把、釕、姥以及銀其中之一或所 組成之群組的至少其中之一者,而形成方式比如是利用濺 鍵或蒸鐘(evaporation)等方式。 例如,金屬層80可以是厚度介於2,000埃至5,000埃 之間(較佳厚度則是介於2,500埃至3,500埃之間)的一鈦層_ 藏鐘在聚合物層36上與二聚合物層開口 36a分別所暴露出 之二連接線路24a、24b的銅層上;或者,金屬層80可以 是厚度介於2,000埃至5,000埃之間(較佳厚度則是介於 2,500埃至3,500埃之間)的一鈦層濺鍍在聚合物層36上與 ==— ------- — · - - . - . . ' T Γ*·.: ~- · · - — ~—'T1--1—' ·'' ··* * - -1ν 42 1353652 二聚ΐ物層開σ 3 6a分別所暴露出之二連接線路24a、24b 的錄層上;或者’金屬層8G可以是厚度介於2,_埃至-5,〇〇〇埃之間(較佳厚度則是介於2,·埃至3,5〇〇埃之間) 的-鈦層韻在聚合物層36上與二聚合物層開口恤分別 所暴露出之二連接線路施、24b的金層上;或者金屬層_ 80可以是厚度介於2,咖埃至5,咖埃之_佳厚度則是 2 2,500埃至3,5⑼埃之_ —關合金層⑽在聚合 6上與—聚合物層開σ 36a分別所暴露出之二連接線 路仏、24'的銅層上;或者,金屬層8〇可以是厚度介於 2,〇〇〇埃至5’〇〇〇埃之間(較佳厚度則是介於2 5⑼埃至 3,500埃之間)的一鈦鎢合金層濺鍍在聚合物層36上鱼二 聚合㈣開口严分別所暴露出之二連接線路2二 的錄層上,或者’金屬I 80可以是厚度介於2’_埃至 5,_埃之間(較佳厚度則是介於2 5⑽埃至3,_埃之門 的一鈦鎢合金層賤鍍在聚合物層36上與二聚合物層開口 36a分別所暴露出之二連接線路他、的金層上。 繼績,形成厚度介於5〇〇埃至2,_埃之間(較隹厚度 則疋介於75G埃至15⑽埃之⑷的—金屬層七在金屬^ 8〇上,此金屬層82係作為電鍵時的導電層以及種子】 (seed layer)。形成金屬層82的方式比如是濺鍍蒸錢、= 理氣相沉積或者是無電電鐘(eleetrMess plating)等方式。由 於金屬層82可有利於後續金屬層的設置,因此金屬層82 的材質會隨後續金屬層的材質而有所變化,如當電鍍形成 驗.M 8出丄金屬層82㈣ ' - . _ —* ** 1353652 質係以銅為隹;當電鍍形成材質為金(Au)的金屬,在金屬 層82上時,金屬層82的材質係以金為佳;#電鍍形成材 質為鈀的金屬層在金屬層82上時,金屬層82的材質係以 鈀為佳;當電鏟形成材質為鉑的金屬層在金屬層82上時, 金屬層82的材質係以鉑為佳;當電鏟形成材·質為铑的金屬 層在金屬層82上時,金屬層82的材質係以铑為佳;當電 鍍形成材質為釕的金屬層在金屬層82上時,金屬層82的 材質係以釕為佳;當電鍍形成材質為銖的金屬層在金屬層 82上時,金屬層82的材質係以銖為佳;當電鍍形成材質 為鎳的金屬層在金屬層82上時,金屬層82的材質係以鎳 為佳。An etch process etches the spin-on glass layer 56 to expose the oxonium compound layer to form a etched compound layer 58 having a thickness of 26 1353652 degrees between 0 and 2 microns to 0.5 microns on the spin-on glass layer 56. The exposed oxonium compound layer 54 is on. Further, a ruthenium compound layer 60 having a thickness of between 0.5 μm and 1.5 μm is formed on the oxonium compound layer 58 by plasma enhanced chemical vapor deposition (PECVD). Therefore, the protective layer 32 is composed of a ruthenium nitride compound layer 52, an oxonium compound layer 54, a spin-on glass layer 56, an oxonium compound layer 58, and a ruthenium nitride compound layer 60. Further, a method of forming at least one opening 32a in the protective layer 32 and exposing the metal wiring 24 (e.g., a copper layer, a recording layer or a gold layer exposing the metal wiring 24) is as follows. The first way of forming the opening 32a is shown in Figs. 6B to 6D. First, referring to FIG. 6B, a photoresist layer 62 is formed on the nitriding compound layer 60 of the protective layer 32, and then the photoresist layer 62 is patterned by exposure and development processes to form at least a photoresist layer opening. 62a is within the photoresist layer 62 and exposes the nitrogen bismuth compound layer 6〇 above the metal line 24. The method of forming the photoresist layer 62 is formed by, for example, a spin coating process or a lamination process, and in the process of patterning the photoresist layer 62, for example,丨χ) The exposure machine (stepper) performs exposure or 疋 疋 (IX) alignment exposure machine (c〇ntact aligner) into the exposure. Referring to FIG. 6C, the yttrium compound layer 60, the yttrium compound layer 58, the oxonium compound layer w and the nitriding compound layer 52' under the photoresist layer opening 62 &amp; are sequentially removed to form at least one opening. 〇32a is in the protective layer h and exposes the metal line 24 (for example, the copper layer exposing the metal line 24, and removing the nitrogen argon under the photoresist layer opening 02a) a ----------. / 27 1353652 The method of the layer 60, the yttrium compound layer 58, the yttrium compound layer 54 and the yttrium compound layer 52 is, for example, removed by etching, and is preferably removed by reactive ion etching (RIE) process etching. Referring to FIG. 6D, the photoresist layer 62 is removed, and the photoresist layer 62 is removed by, for example, removing plasma using oxygen plasma (02 plasma) or using an organic solvent (for example, containing an amino compound). In addition, after removing the photoresist layer 62, the plasma 32 (for example, a plasma containing oxygen ions or a plasma containing a fluoride ion concentration of less than 200 PPM and fluorine ions) may be used to clean the opening 32a. Metal line 24 to remove metal lines 24 The photoresist residue or other foreign matter on the surface. The second way of forming the opening 32a is shown in Figures 6E to 6F. First, as shown in Figure 6E, spin coating to form a polymer layer 64 in the protective layer. The polymer layer 64 is patterned on a layer of nitrogen bismuth compound 60, followed by baking, exposure and development to form at least one polymer layer opening 64a in the polymer layer 64 and exposing the nitrogen above the metal line 24. The ruthenium compound layer 60. During the process of patterning the polymer layer 64, for example, exposure with a double (IX) stepper or doubling (IX) alignment aligner Into the exposure. Come again - in the nitrogen: in a gaseous or anaerobic environment, using a curing process at temperatures between 200 ° C and 290 ° C, between 290 ° C and 330 ° C The polymer layer 64 is hardened between 330 ° C and 400 ° C, and the hardening process is carried out for a period of between 30 minutes and 2 hours. The polymer layer 64 is, for example, selected from the group consisting of polyfluorene. Imine (PI), phenylcyclobutene (BCB), polyurethane, epoxy resin, polyparadimethylene One of the polymer type 'welding material, the dream material or the porous 28 1353652 dielectric material, and the thickness of the hardened polymer layer 64 is, for example, between 5 micrometers and 30 micrometers, for example, the polymer layer 64. It may be a layer of polyamidene having a thickness of between 5 micrometers and 30 micrometers or a layer of phenylcyclobutene having a thickness of between 5 micrometers and 30 micrometers. See Figure 6F, in order The nitrogen argon compound layer 60, the oxonium compound layer 58, the oxonium compound layer 54 and the yttrium compound layer 52 under the polymer layer opening 64a are removed to form at least one opening 32a in the protective layer 32 and expose the metal line 24 ( For example, a copper layer, a gold layer or a gold layer of the metal line 24 is exposed. Wherein, the manner of removing the nitrogen argon compound layer 60, the oxonium compound layer 58, the oxygen oxysulfide compound layer 54 and the nitrogen argon compound layer 52 under the polymer layer opening 64a is, for example, removed by etching and reactive ion etching ( RIE) Process etching removal is the preferred mode. In addition, the above-mentioned nitrogen argon compound layer 52 may also be replaced by a oxynitride compound layer, that is, a plasma reinforced chemical vapor deposition (PECVD) is used to form a oxynitride compound layer having a thickness of between 0.1 μm and 0.5 μm. On the metal line 24 and the germanium-containing dielectric layer 14 (for example, a layer of a cerium nitride compound or a layer of oxynitride compound), the subsequent reading is formed by plasma enhanced chemical vapor deposition (PECVD) to a thickness of 0.1 μm to 0.5 μm. An ambiguity between the layers of -4 on this oxynitride compound layer, followed by formation of a spin-on-glass (SOG) layer 56 on the oxonium compound layer 54, followed by an etching process etch The glass layer 56 is coated to expose the oxonium compound layer 54 and continue to form a ruthenium compound layer 58 having a thickness of between 0.2 μm and 0.5 μm by plasma enhanced chemical vapor deposition (PECVD). On the glass layer 56 and the exposed oxonium compound layer 54, a layer of a ruthenium ruthenium compound having a thickness of between 0.5 μm and 1.5 μm is formed by plasma deposition of a gas chromatograph 29 1353652 (PECVD). 60 on the oxonium compound layer 58 and finally The steps described in the above 6B to 6D or the steps described in the above 6E to 6F are not described in detail here, but those skilled in the art can use the above description. To implement. _ The fifth method for forming the protective layer and the opening is as shown in Fig. 7, first forming a layer of a ruthenium nitride compound layer having a thickness of between 0.1 μm and 0.5 μm by plasma enhanced chemical vapor deposition (PECVD). On the metal line 24 and the germanium-containing dielectric layer 14 (for example, a layer of a cerium nitride compound or a layer of oxynitride compound), plasma-reinforced chemical vapor deposition (PECVD) is continuously used to form a thickness of 0.1 μm to 0.5 μm. The inter-monooxon compound layer 54 is on the nitrogen hydrazine compound layer 52. Next, spin coating forms a polymer layer 66 on the oxon compound layer 54 and in a nitrogen atmosphere or an oxygen-free environment, using a curing process at a temperature between 200 ° C and 290 ° C, between The polymer layer 66 is hardened between 290 ° C and 330 ° C or between 330 ° C and 400 ° C, wherein the hardening process is carried out for a period of between 30 minutes and 2 hours, and the polymer layer 66 For example, polyimine (PI) or benzene tombenbutene (BCB). Thereafter, an etching layer T is used to etch the layer 66 to expose the oxon compound layer 54. Continuing, a layer of oxonium compound 58 having a thickness of between 0.2 microns and 0.5 microns is formed on the polymer layer 66 and the exposed oxonium compound layer 54 by plasma enhanced chemical vapor deposition (PECVD). Further, a layer of a ruthenium nitride compound layer having a thickness of between 0.5 μm and 1.5 μm is formed by plasma-enhanced chemical vapor deposition (PECVD) on the winter-rocky layer 58. 30 1353652 - Thus, the protective layer 32 is composed of a nitrile compound layer 52, a oxonite compound layer 54, a polymer layer 66, an oxygen compound layer 58, and a nitrogen compound layer 60. For the manner of forming at least one opening 32a in the protective layer 32 and exposing the metal line 24 (for example, a copper layer, a nickel layer or a gold layer exposing the metal line 24), please refer to the relevant descriptions of FIGS. 6B to 6F above. It will not be explained in detail here. In addition, the above-mentioned nitrogen compound layer 52 may also be replaced by a yttrium-deuterium compound layer, that is, an iammonia compound having a thickness of between 0.1 μm and 0.5 μm is formed by paddle-type chemical vapor deposition (PECVD). The layer continues on the metal line 24 with the germanium containing dielectric layer 14 (eg, a layer of a ruthenium nitride compound or a layer of oxynitride compound) and continues to form a thickness between 0.1 micron and 0.5 micron by plasma enhanced chemical vapor deposition (PECVD). An oxonium compound layer 54 is disposed on the oxynitride compound layer, followed by formation of a polymer layer 66 on the oxonium compound layer 54, followed by etching the polymer layer 66 using an etching process to expose the oxonium compound. Layer 54, continues to utilize plasma enhanced chemical vapor deposition (PECVD) to form an oxonium compound layer 58 having a thickness between 0.2 microns and 0.5 microns on the polymer layer 66 and the exposed oxonium compound layer 54. Then, a plasma reinforced chemical vapor deposition (PECVD) is used to form a ruthenium nitride compound layer 60 having a thickness of between 0.5 μm and 1.5 μm on the oxonium compound layer 58 and finally subjected to the above-mentioned FIG. 6B to The steps described in the 6D diagram 6E for the first or second step of the FIGS FIG 6F, which is not described in detail, those skilled in the art that when then can be described by the above-described embodiment and accordingly. 6 kinds of formation of the upper layer of the protective layer -1 - 31 1353652 Please refer to Figure 8A, using plasma enhanced chemical vapor deposition (PECVD) to form a nitrogen bismuth thickness between 0.5 microns and 1.5 microns Compound layer 68 is on metal line 24 with a ruthenium containing dielectric layer 14 (e.g., a ruthenium compound layer or a nitroxanthine compound layer). Therefore, the protective layer 32 is composed of a nitrogen argon compound layer 68. Further, a manner of forming at least one opening 32a in the protective layer 32 and exposing the metal wiring 24 (e.g., a copper layer, a nickel layer or a gold layer exposing the metal wiring 24) will be described below. The first way of forming the opening 32a is shown in Figs. 8B to 8D. First, referring to FIG. 8B, a photoresist layer 70 is formed on the ytterbium compound layer 68, and then the photoresist layer 70 is patterned by exposure and development processes to form at least one photoresist layer opening 70a in the photoresist layer. A layer of nitrogen ruthenium compound 68 over metal line 24 is exposed within 70. The method of forming the photoresist layer 70 is formed, for example, by a spin coating process or by a lamination process, and is used in the process of patterning the photoresist layer 70, for example, by doubling (IX). The stepper is exposed or exposed to the exposure using a double (IX) contact aligner. Referring to Fig. 8C, the underlying nitrogen ruthenium compound layer 68 of the photoresist layer opening 7_0a is removed to form at least one opening 32a in the protective layer 32 and expose the metal line 24. Among them, the manner of removing the nitrogen ruthenium compound layer 68 under the photoresist layer opening 70a is, for example, removed by silver etching, and is preferably removed by reactive ion etching (RIE) process etching. Referring to FIG. 8D, the photoresist layer 70 is removed, and the photoresist layer 70 is removed by, for example, using an oxygen-containing, sub-electricity p]_asjna}_32 1353652 to remove or utilize an organic solvent ( For example, an organic solvent containing an amino group-based compound is removed. In addition, after removing the photoresist layer 70, the metal line 24 exposed by the opening 32a may be cleaned by using a plasma (for example, a plasma containing oxygen ions or a plasma containing a fluoride ion concentration of less than 200 PPM and oxygen ions). The photoresist residue or other foreign matter on the upper surface of the metal line 24 is removed. The second way of forming the opening 32a is shown in Figs. 8E to 8F. First, as shown in FIG. 8E, a polymer layer 72 is spin-coated to form a polymer layer 72 on the yttrium compound layer 68, followed by a process of baking, exposing and developing to form a polymer layer 72 to form at least one polymer layer opening. 72a is within polymer layer 72 and exposes a layer of nitrogen bismuth compound 68 over metal line 24. In the process of patterning the polymer layer 72, for example, exposure is performed by a double (IX) stepper or by a double (1 parent) contact aligner. Further, in a nitrogen atmosphere or an oxygen-free environment, a curing process is used at a temperature between 200 ° C and 290 ° C, between 290 ° C and 330 ° C or between 330 ° C. The polymer layer 72 is hardened to between 400 ° C and the hardening process is carried out for a period of between 30 minutes and 2 hours. The polymer layer 72 is, for example, selected from the group consisting of polyimine (PI), phenylcyclobutene (BCB), polyurethane, epoxy resin, polyparaphenylene phthalate polymer, and welding cap. One of a material, an elastic material or a porous dielectric material, and the thickness of the hardened polymer layer 72 is, for example, between -5 micrometers and 30 micrometers, for example, the polymer layer 72 may have a thickness of 5 micrometers to 30 micrometers. A layer of polyamidene between the micrometers or a layer of phenylcyclobutene having a thickness of between 5 micrometers and 30 micrometers. ____ Read the reference to the 8F calendar $, remove the nitrogen 33 1353652 矽 compound layer 68 under the polymer layer opening 72a to form at least one opening 32a in the protective layer 32 and expose the metal line 24 » wherein the polymer is removed The manner of the nitrogen argon compound layer 68 under the layer opening 72a is, for example, removed by etching and removed by a reactive silicon ion etching (RIE) process. In summary, a protective layer 32 is formed on the metal line 24 and the germanium-containing dielectric layer 14 (for example, a layer of a cerium nitride compound or a layer of oxynitride compound), and the protective layer 32 can protect the semiconductor element 4 and the wiring structure 6 And the metal line 24 is protected from the damage of moisture and foreign ion contamination 'that is, the protective layer 32 can prevent moving ions (such as sodium ions), water gas (m〇isture), transition metal (such as gold, silver, copper) and other impurities penetrate, and damage the semiconductor component 4 under the protective layer 32 (such as a transistor, a polycrystalline resistive element or a polycrystalline sinusoidal poly capacitor) , line structure 6 or metal line %. Here, the "lower"-word means in the present invention that it is located under and in contact with something, or that it is located underneath something but is not in contact therewith. The maximum lateral dimension of the opening 32a is, for example, between 2 microns and % microns or between 30 microns and 300 microns. In addition, the shape of the opening 32 &amp; may be a circle, a square or a polygon of five or more sides, and the maximum lateral dimension of the opening 8a refers to the diameter dimension of the circular opening, the side length dimension of the square opening or the polygonal opening of five or more sides. The longest diagonal size. Further, the shape of the opening π 32a may be a rectangle, and the width of the rectangular opening is between 2 μm and 40 μm. In addition, the base metal line 24 is a reconfigurable line (redistributed to the port 32a). 34 1353652 The position of the metal line 24 is different from the position of the metal layer 10 exposed by the opening 14a. The invention can also be an interconnecting metal trace. Therefore, the metal layer 10 exposed by the two openings 14a or the two openings 14a can be connected via the metal line 24, and the manner of formation is as follows. First, please refer to FIG. 9A. Forming a dream dielectric layer 14 (eg, a nitrogen compound layer or a oxynitride compound layer) above the wiring structure 6 and above the dielectric layer 8 and containing the germanium dielectric layer 14 as described in FIG. 2A. At least two openings 14a respectively expose at least two metal layers 10 of the line structure 6, and regarding the germanium-containing dielectric layer 14, the opening 14a, and the formation of the germanium-containing dielectric layer 14 and the opening 14a, please refer to the above 2A. The description of the figure to FIG. 2C will not be described in detail here. Referring to FIG. 9B, an adhesive/diffusion barrier 16 is formed in the ytterbium-containing dielectric as described in FIGS. 2D to 2E. Layer 14 (eg, nitrogen evolution) a metal layer 10 on the layer or the yttrium compound layer) and the two openings 14a are respectively exposed, and a metal layer 18 is formed on the adhesion/diffusion barrier layer 16 with respect to the adhesion/diffusion barrier 16 and For the description of the metal layer 18, please refer to the description of FIG. 2D to FIG. 2E, which will not be described in detail herein. Referring to FIG. 9C, a photoresist layer 74 is formed on the metal layer 18, and is exposed through exposure. Developing a patterned photoresist layer 74, such as forming a photoresist layer opening 74a in the photoresist layer 74 and exposing the metal layer 18 (including exposing the two metal layers 10 exposed at the two openings 14a, respectively) The upper metal layer 18), wherein the photoresist layer 74 is formed, for example, by a spin coating process to form a lamination process, and the photoresist layer 74 is patterned at 35 1353652. For example, the exposure is performed by a double (l-Χ)-stepper or by a double (IX) contact aligner. Alternatively, the plasma can be utilized after development ( For example, a plasma containing oxygen ions or containing a fluoride ion concentration of less than 200 PPM and oxygen The plasma of the ion) cleans the metal layer 18 exposed by the photoresist layer opening 74a, thereby removing the photoresist residue or other foreign matter on the upper surface of the metal layer 18. See Figure 9D, as shown in Figure 2H. For example, a metal layer 22 having a thickness t2 between 5 micrometers and 25 micrometers is formed on the metal layer 18 exposed by the photoresist layer opening 74a. For the description of the metal layer 22, please refer to the description of FIG. 2H. It will not be explained in detail here. Referring to FIG. 9E, after the metal layer 22 is formed, the photoresist layer 74 is removed, and the photoresist layer 74 is removed by, for example, removing plasma using oxygen ions or using an organic solvent. Removal (for example, an organic solvent containing an amino compound). In addition, after removing the photoresist layer 74, the metal layer 22 and the metal layer 18 may be cleaned by using a plasma (for example, a plasma containing oxygen ions or a plasma containing a fluoride ion concentration of less than 200 PPM and oxygen ions) to remove the metal. A photoresist residue or other foreign matter on the upper surface of the layer 22 and the upper surface of the metal layer 18. Referring to Figure 9F, the metal layer 18 and the adhesion/diffusion barrier layer 16 which are not under the metal layer 22 are removed. For the manner of removing the metal layer 18 and the adhesion/diffusion barrier layer 16 which are not under the metal layer 22, please refer to the description of FIG. 2J, which will not be described in detail herein. Therefore, the present invention can form a metal line 1 〇 _ _ a metal line J J _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ V—; .. ^ . 一一-二_ . . . . , —————— Two:-· V.-; ·- ·' . . . * * 36 1353652 疋 by a sticky / diffusion resistance The barrier layer 16 is formed of a metal layer 18 on the adhesion/diffusion barrier layer 16 and a metal layer 22 on the metal layer 18, and has a thickness t3 of between 5 micrometers and 27 micrometers. Next, after removing the metal layer 18 and the adhesion/diffusion barrier layer 16 which are not under the metal layer 22, a protective layer 32 is formed on the metal line % and the germanium-containing dielectric layer 14 (for example, a nitrogen-nenetium compound layer or nitrogen oxide). On the ruthenium compound layer, the metal line 24 may be exposed through at least one opening 32a located in the protective layer 32, or the metal layer 24 may be exposed without any opening 32a in the protective layer 32. For the method of forming the protective layer 32 and the opening 32a, please refer to the above descriptions of the "methods for forming the protective layer and the opening", and the ninth embodiment is formed by the method of the cover and the opening. The protective layer 32 is formed on the metal line 24 and The metal layer 24 is exposed on the dielectric layer 14 and there is no opening 3 in the protective layer 32. However, those skilled in the art can use the above-mentioned six methods of "forming a protective layer and opening" by the above description. The content can be implemented accordingly, and at least one opening 32a can be formed in the protective layer 32. The metal circuit 24 is exposed to connect an external circuit, wherein the external circuit is connected by, for example, using a wire bonding process to bond a wire (for example, a gold wire). One end of the wire or copper wire is connected to the exposed metal line 24, and the other end is connected to the external circuit. In addition, the external circuit may be a semiconductor wafer, a printed circuit board, a flexible board, a substrate containing a ceramic material, a previously formed passive passive device or a glass substrate, and the printed circuit board contains glass fibers, and the flexible board includes a thickness. A polymer layer (eg, polyimine) between 3 microns and 2 microns. In a manner, the present invention 37 1353652 can also form a pad on the metal layer 10 exposed by the opening 14a, and form a protective layer 32 on the pad through the above six methods of forming a protective layer and opening. An opening 32a of the germanium-containing dielectric layer 14 and located in the protective layer 32 exposes a pad, and the manner of formation is as follows. First, as shown in FIG. 10A, a stone-containing dielectric layer 14 (for example, a nitrogen compound layer or a oxynitride layer) is formed in the contents of FIGS. 2A, 2D, and 2E. Above the wiring structure 6 and above the dielectric layer 8, and at least one opening 14a in the germanium-containing dielectric layer 14 exposes at least one metal layer 10 of the wiring structure 6, and the associated dielectric layer 14, the opening 14a and For the description of the formation of the stone-containing dielectric layer 14 and the opening 14a, please refer to the descriptions of FIGS. 2A to 2C above, and the detailed description thereof will not be repeated here. Next, an adhesion/diffusion barrier 16 is formed on the metal layer 10 exposed on the germanium-containing dielectric layer 14 (for example, a layer of a cerium nitride compound or a layer of oxynitride compound) and the opening 14a, and a metal layer 18 is formed. The adhesion/diffusion barrier layer 16 and the description of the adhesion/diffusion barrier 16 and the metal layer 18 are described in the description of FIGS. 2D to 2E, and will not be described in detail herein. Referring to FIG. 10B, a photoresist layer 76 is formed on the metal layer 18, and at least one photoresist layer opening 76a is formed on the photoresist layer 76 by patterning the photoresist layer 76 through exposure and display processes. The metal layer 18 is positioned inside the metal layer 10 exposed by the opening 14a. Wherein, the method of forming the photoresist layer 76 is formed, for example, by a spin coating process or by a lamination process, and in the process of patterning the photoresist layer 76, for example, using one time ( The IX) stepper performs exposure or a double-fold (1X) contact aligner. Another: ― 38 1353652 After the development, the plasma exposed by the photoresist layer opening 76a can be cleaned by using a plasma (for example, a plasma containing oxygen ions or a plasma containing a gas ion concentration of less than 20 〇 PPM and oxygen'). Layer 18 is used to remove photoresist residues or other foreign matter from the upper surface of metal layer 18. • Referring to FIG. 10C, a metal layer 22 having a thickness between 5 micrometers and 25 micrometers is formed on the metal layer 18 exposed by the photoresist layer opening 76a, as described in FIG. 2H. For a description of the metal layer 22, refer to the description of FIG. 2H, which will not be described in detail herein. Referring to FIG. 10D, after the metal layer 22 is formed, the photoresist layer 76 is removed, and the photoresist layer 76 is removed, for example, by using a plasma containing oxygen ions to remove or using an organic solvent. Removal (for example, an organic solvent containing a gas-based compound). In addition, after removing the photoresist layer 76, the metal layer 22 and the metal layer 18 may be cleaned by using a plasma (for example, a plasma containing oxygen ions or a plasma containing a fluoride ion concentration of less than 200 PPM and oxygen ions) to remove the metal. Resist residue or other foreign matter on the upper surface of layer 22 and the upper surface of metal layer 18. Referring to Fig. 10E, the metal layer 18 and the adhesion/diffusion barrier layer 16 which are not under the metal layer 22 are removed. For the manner of removing the metal layer 18 and the adhesion/diffusion barrier layer μ which are not under the metal layer 22, please refer to the description of Fig. 2J, which will not be described in detail. Therefore, the present invention can form at least the interface 78 for connecting an external circuit on the metal layer 10 exposed by the opening 14a. The pad 78 is formed by a point/diffusion barrier layer 16 and is located in the adhesion/diffusion barrier. A metal on the barrier layer 16 and a metal layer 22 on the metal layer 18, and each of the hemorrhoids - '~------" ~;, _ ' - rr ~ one two two; :;• Two ~ ~ _ 39 1353652 between 5 microns and 27 microns. The external circuit may be a semiconductor wafer, a printed circuit board, a flexible board, a substrate containing a ceramic material, a previously formed passive passive device or a glass substrate, and the printed circuit board contains glass fibers, and the flexible board includes a thickness. A polymer layer (eg, polyimine) between 3 microns and 200 microns. Then, after removing the metal layer 18 and the adhesion/diffusion barrier layer 16 which are not under the metal layer 22, a protective layer 32 is formed on the pad 78 and the silicon-containing dielectric layer 14 (for example, a nitrogen-niobium compound layer or nitrogen). The matte layer is exposed on the oxygen oxide compound layer and through only one opening 32a in the protective layer 32. For the method of forming the protective layer 32 and the opening 32a, please refer to the above-mentioned six "methods for forming a protective layer and an opening". The 10F is a protective layer 32 formed on the pad 78 by the first type of bin. The above-mentioned six kinds of "forming the protective layer and the opening" are formed by the above-mentioned description by the opening 32a of the stone layer 14 and located in the opening 32a of the protective layer 32. The content of the method is implemented accordingly. Alternatively, the interface 78 exposed by the bonding wire to the opening 32a or the formation of a scaly metal layer or a metal bump (for example, a gold bump) over the interface 78 exposed by the opening 32a can be used. The 塾78 is connected to an external circuit, wherein the external circuit may be a semiconductor wafer, a printed circuit board, a flexible board, a substrate containing a ceramic material, a previously formed passive passive device or a glass substrate, and the printed circuit board contains glass fibers. The flexible board then comprises a polymer layer (e.g., polyimide) having a thickness between 3 Å and 2 Å. After the last month _ _ ^ to describe the formation of the shy layer 3_2 sensation of the boat akisaki 1353652, then the following three processes can be carried out, described as follows: The first process ~ after the completion of the above protective layer 32 or opening 32a step, then cut The semiconductor substrate 2 is formed to form a plurality of wafers, and the wafers may be further bonded to a metal line exposed by one of the openings 32a of the protective layer 32 by one end of a wire bonding wire (the material of which includes gold, copper or aluminum) through a wire bonding process. 24 (for example, a copper layer, a nickel layer or a gold layer of the metal line 24), and the other end is connected to a lead of a leadframe or a pad, which may be another One of the semiconductor wafer pads, one of the pads above the other semiconductor substrate, one of the pads above the organic substrate, one of the pads above the ceramic substrate, one of the pads above the substrate, and one of the upper of the glass substrate A pad or a pad above a soft board, and the board includes a polymer layer having a thickness between 30 and 200 microns. The wire bonding strength used in the wire bonding process of the present invention is, for example, between 1 〇〇 millinewton (mN) to 1,000 millinewtons, between 200 millinewtons to 1,000 millinewtons, or between 200 millimeters. Newton to between 500 millinewtons. Finally, after the wire bonding process is completed, a polymer material, such as epoxy or polyimide, is formed to coat the wire. Further, when the metal line 24 is a reconfigurable line (RDL), the position at which the wire bonding wire is bonded to the metal line 24 is different from the position of the metal layer 10 exposed by the opening 14a from a top perspective view. After the second process is completed by the step of forming the protective layer 32 or the opening 32a, the present invention can form another metal line over the protective layer 32 and connect the opening 32a to the violent one--- 1 ~~. 1- · -: ·- : ~ 1353652 The metal. Line 24, under the "Metal line 24 includes two connecting lines 24a, 24b" and "Protective layer 32 system ~ through a type of formation of the protective layer and opening to form i way For the sake of explanation, those skilled in the art can implement the above-described six methods of "forming a protective layer and opening" by the following description, and the metal line 24 is not limited to the two connecting lines. Referring to FIG. 11A, a metal layer 80 having a thickness between 2,000 angstroms and 5,000 angstroms (preferably having a thickness of between 2,500 angstroms and 3,500 angstroms) is formed on the polymer layer 36. The two polymer layer openings 36a are respectively exposed on the two connecting lines 24a, 24b, and the metal layer 80 serves as an adhesion/barrier layer, and functions to provide the connecting lines 24a, 24b and the metal. Good adhesion between the materials and prevents diffusion reactions between the connecting lines 24a, 24b and the metallic material. The material of the metal layer 80 is, for example, selected from the group consisting of titanium, crane, abundance, titanium nitride, titanium alloy, titanium alloy, group, nitride group, complex, copper, copper alloy, gold, town, beginning, and At least one of 钌, 姥, 姥, and silver, or a group formed by, for example, by means of a splash bond or an evaporation. For example, the metal layer 80 may be a titanium layer having a thickness of between 2,000 angstroms and 5,000 angstroms (preferably having a thickness of between 2,500 angstroms and 3,500 angstroms) on the polymer layer 36 and the second polymer. The layer openings 36a are respectively exposed on the copper layers of the two connection lines 24a, 24b; alternatively, the metal layer 80 may have a thickness of between 2,000 angstroms and 5,000 angstroms (preferably, the thickness is between 2,500 angstroms and 3,500 angstroms). A titanium layer is sputtered onto the polymer layer 36 with ==- ------- - · - - - - . . ' T Γ*·.: ~- · · - - ~ - 'T1 --1—' ·'' ··* * - -1ν 42 1353652 The dimerized layer opens σ 3 6a on the recording layers of the two connecting lines 24a, 24b respectively exposed; or 'the metal layer 8G may be the thickness - Titanium layer between 2, _ Å to -5, 〇〇〇 (better thickness is between 2, Å to 3, 5 Å) on the polymer layer 36 The two polymer layer opening shirts are respectively exposed on the two connection lines, the gold layer of 24b; or the metal layer _80 may have a thickness of 2, 559 to 5, and the thickness of the café is 2 2,500 angstroms. To 3,5 (9) angstroms - off alloy layer (10) in polymerization 6 is on the copper layer of the two connection lines 24, 24' exposed by the polymer layer opening σ 36a respectively; or, the metal layer 8 〇 may have a thickness of 2, 〇〇〇 to 5' 〇〇〇 A titanium-tungsten alloy layer between angstroms (preferably having a thickness of between 2 5 (9) angstroms and 3,500 angstroms) is sputtered on the polymer layer 36. The fish is polymerized (four) and the openings are respectively exposed by two connecting lines 2 On the recording layer, or 'metal I 80 can be between 2'_ Å to 5, _ Å (preferably the thickness is between 2 5 (10) angstroms to 3, _ Ai's door of a titanium-tungsten alloy layer The ruthenium is plated on the polymer layer 36 and the two polymer layer openings 36a are respectively exposed on the gold layer of the connection line. The success is formed to a thickness of between 5 angstroms and 2 angstroms (more) The thickness of the crucible is between 75 G and 15 (10) angstroms (4) - the metal layer 7 is on the metal layer 8 , and the metal layer 82 is used as a conductive layer and a seed layer for the electric bond. The manner of forming the metal layer 82 For example, sparking steam, = CVD or eleetrMess plating, etc. Since the metal layer 82 can be beneficial to the subsequent metal layer Therefore, the material of the metal layer 82 may vary with the material of the subsequent metal layer, such as when the plating is formed. The M 8 out of the metal layer 82 (4) ' - . _ —* ** 1353652 The system is made of copper; The metal is formed of gold (Au), and the metal layer 82 is made of gold. When the metal layer of the palladium is formed on the metal layer 82, the material of the metal layer 82 is formed. Palladium is preferred; when the shovel forms a metal layer of platinum on the metal layer 82, the material of the metal layer 82 is preferably platinum; when the shovel is formed of a metal layer of tantalum in the metal layer 82 In the upper case, the material of the metal layer 82 is preferably 铑; when the metal layer of the enamel is formed on the metal layer 82 by electroplating, the material of the metal layer 82 is preferably 钌; when the metal layer is formed by plating When the metal layer 82 is used, the material of the metal layer 82 is preferably ruthenium; when the metal layer formed of nickel is plated on the metal layer 82, the material of the metal layer 82 is preferably nickel.

綜上所述,當金屬層80是以濺鍍方式所形成之厚度介 於2,000埃至5,000埃之間(較佳厚度則是介於2,500埃至 3,500埃之間)的一鈦層時,金屬層82可以是厚度介於500 埃至2,000埃之間(較佳厚度則是介於750埃至1,500埃之 間)的一金層濺鍍在此鈦層上;或是,當金屬層80是以濺 鍍方式所形成之厚度介於2,000埃至5,000埃之間(較佳厚 度則是介於2,500埃至3,500埃之間)的一鈦鎢合金層時, · · 金屬層82可以是厚度介於500埃至2,000埃之間(較佳厚 度則是介於750埃至1,500埃之間)的一金層濺鍍在此鈦鎢 合金層上;或是,當金屬層80是以濺鍍方式所形成之厚度 介於2,000埃至5,000埃之間(較佳厚度則是介於2,500埃 至3,500埃之間)的一鈦層時,金屬層82可以是厚度介於 —500埃至2,000埃之間(較佳厚度則是介於750埃至Γ,50(Τ _In summary, when the metal layer 80 is formed by sputtering, the thickness of the titanium layer is between 2,000 angstroms and 5,000 angstroms (preferably, the thickness is between 2,500 angstroms and 3,500 angstroms). The layer 82 may be a gold layer having a thickness between 500 angstroms and 2,000 angstroms (preferably having a thickness between 750 angstroms and 1,500 angstroms) on the titanium layer; or, when the metal layer 80 is When a titanium-tungsten alloy layer having a thickness of between 2,000 angstroms and 5,000 angstroms (preferably having a thickness of between 2,500 angstroms and 3,500 angstroms) is formed by sputtering, the metal layer 82 may be thick. a gold layer between 500 angstroms and 2,000 angstroms (preferably having a thickness of between 750 angstroms and 1,500 angstroms) is sputtered onto the titanium tungsten alloy layer; or, when the metal layer 80 is splashed When the plating method forms a titanium layer having a thickness of between 2,000 angstroms and 5,000 angstroms (preferably, the thickness is between 2,500 angstroms and 3,500 angstroms), the metal layer 82 may have a thickness of between -500 angstroms and 2,000 Å. Between angstroms (better thickness is between 750 angstroms to Γ, 50 (Τ _

44 1353652 埃_之間)的一銅層濺鍍在此鈦層上;或是,當金屬層80是 以濺鍍方式所形成之厚度介於2,000埃至5,000埃之間(較 佳厚度則是介於2,500埃至3,500埃之間)的一鈦鎢合金層 時,金屬層82可以是厚度介於500埃至2,000埃之間(較 佳厚度則是介於750埃至1,500埃之間)的一銅層藏鍍在此 欽鶴合金層上。 請參閱第11B圖所示,形成一光阻層84在金屬層82 上,並透過曝光(exposure)與顯影(development)等製程圖案 化光阻層84,以形成一光阻層開口 84a在光阻層84内並 暴露出位在二連接線路24a、24b上方及部分聚合物層36 上方的金屬層82。其中,光阻層84比如是一正型 (positive-type)光阻層,另形成光阻層84的方式例如是以 旋塗(spin coating)方式形成,而在圖案化光阻層84的過程 中比如是利用倍(IX)之曝光機(stepper)或一倍(IX)之對 準曝米機(contact aligner)進行曝光。此外,在顯影後可以 利用電漿(例如是含有氧離子之電漿或是含有氟離子濃度 小於200PPM與氧離子之電漿)清洗光阻層開口 84a所暴露 出之金屬層82,藉以去除金屬層82上表©之光阻殘留物 或其它異物。44 1353652 A copper layer is sputtered on the titanium layer; or, when the metal layer 80 is formed by sputtering, the thickness is between 2,000 angstroms and 5,000 angstroms (the preferred thickness is When a titanium-tungsten alloy layer is between 2,500 angstroms and 3,500 angstroms, the metal layer 82 may have a thickness of between 500 angstroms and 2,000 angstroms (preferably, a thickness of between 750 angstroms and 1,500 angstroms). A copper layer is deposited on the layer of the alloy. Referring to FIG. 11B, a photoresist layer 84 is formed on the metal layer 82, and the photoresist layer 84 is patterned by exposure and development processes to form a photoresist layer opening 84a in the light. A metal layer 82 is disposed within the resist layer 84 over the two connecting lines 24a, 24b and over the portion of the polymer layer 36. The photoresist layer 84 is, for example, a positive-type photoresist layer, and the photoresist layer 84 is formed by a spin coating method, for example, in the process of patterning the photoresist layer 84. For example, exposure is performed by using a stepper of double (IX) or a contact aligner of one time (IX). In addition, after development, the metal layer 82 exposed by the photoresist layer opening 84a may be cleaned by using a plasma (for example, a plasma containing oxygen ions or a plasma containing a fluoride ion concentration of less than 200 PPM and oxygen ions) to remove the metal. Residual photoresist or other foreign matter on the layer 82 on the surface of the layer 82.

例如,本發明形成光阻層84與圖案化光阻層84的方 法可以是藉由旋塗厚度介於5微米至30微米之間(較佳厚 度則是介於7微米至15微米之間)的一正型光阻層在金屬 層82上,再利用一倍(IX)之曝光機(stepper)以含有G線與 Η線二種波^長+、含有G線與1」線土種波悬3有Η缚與一I 45 ^53652 線二穆竦長或悬含有G線、Η線與I線三穠波長之光源照 射正型光阻層進行曝光’接著透過顯影製程顯影正型光阻 層’以將電鍍的圖形顯現出來而形成光阻層開口 84a在光 阻層84内並暴露出位在二連接線路24a、24b上方及部分 聚合物層36上方的金屬層82 ^其中,G線的波長範圍係 介於434奈米(nano)至438奈米之間’ Η線的波長範圍係 介於403奈米至407奈米之間,I線的波長範圍係介於363 奈米至367奈米之間。 請參閱第11C圖所示,電鍍形成厚度介於!微米至2〇〇 微米之間(例如1微米至50微米之間)的一金屬層%在光 阻層開口 84a所暮露出的金屬層82上》此金屬層86的較 佳厚度係介於2微米至30微米之間,且金屬層86可以是 金、銅、銀、鈀、鉑、铑、釕、銖或鎳之單層金屬結構或 是由上述金屬材質所組成之複合層金屬結構。另,形成金 屬層86的方式亦可包括無電電鍍製程。 例如,金屬層86可以是以電鍍方式所形成之厚度介於 2微米至35微米之間的一金層在光阻層開口 “a所暴露出 之材質例如是金的金屬層82上,或是以電鍍方式所形成之 厚度介於2微米至35微来之間的一銅層在光阻層開口 84a 所暴露出之材質例如是銅的金屬層82上。又,形成此金屬 層86的方式比如是藉由電鐘厚度介於2微米至35微米之 間的一銅層在材質例如是銅的金屬層82上,接著電錢厚度 介於〇.1微米至10微米之間(較佳厚度係介於〇丨微米至5 鎳層在此銅層、上二最後電鍍厚度介於Ό.Ό1 &quot;** . ·*^&quot;^·· · Μ &lt; . - — * - —— 一 I - &quot; * \ — — - - - -- 46 1353652 微半至10微米之間(較佳厚度係介於0.1微米至2徵米之 間)的一金層在此鎮層上。 請參閱第11D圖所示,在形成金屬層86之後,接著 去除光阻層84。此外,在去除光阻層84之後,可以先經 過電漿(例如是含有氧離子之電漿或是含有氟離子-濃度小 於200PPM與氧離子之電漿)清洗金屬層86與金屬層82, 藉以去除金屬層86上表面與金屬層82上表面之光阻殘留 物或其它異物。繼續,請參閱第11E圖所示,去除未在金 屬層86下方的金屬層82與金屬層80。其中,去除未在金 屬層86下方之金屬層82與金屬層80的方式比如是以蝕刻 方式去除,而蝕刻方式可分為乾蝕刻與濕蝕刻,另乾蝕刻 包括化學電漿蝕刻、濺擊蝕刻(如使用高壓氬氣進行濺擊蝕 刻)與化學氣體蝕刻。例如在濕蝕刻方面,當金屬層80為 鈦鎢合金時,可以使用含有雙氧水的溶液蝕刻去除,而當 金屬層80為鈦時,可以使用含有氰氟酸的溶液蝕刻去除, 另當金屬層82為金時,可利用含有碘之蝕刻液(例如含有 碘化鉀之蝕刻液)蝕刻去除;在乾蝕刻方面,當金屬層80 為鈦或鈦鎢合金Bf,可使用含氯的電漿蝕刻去除,而當金 屬層82為金時,可使用高壓氬氣進行濺擊蝕刻去除。 因此,本發明可形成一金屬線路88在聚合物層36上 與二聚合物層開口 36a所暴露出之二連接線路24a、24b 上,用以連接二聚合物層開口 36a所暴露出之二連接線路 24a、24b。此金屬線路88是由一金屬層80、位在金屬層 80上的一金屬層82與位在金屬層82上的一金屬層86所 -- .47 — ’ ·· - — 1353652 構成。 , _ 請參閱第11F圖所示,本發明在去除未在金屬層86 下方的金屬層82與金屬層80之後,可選擇形成一聚合物 層90在金屬線路88上與聚合物層36上,且位在聚合物層 90内之一聚合物層開口 90a暴露出金屬線路88。其中,聚 合物層90比如是選自聚醯亞胺、苯基環丁烯、聚氨脂、環 氧樹脂、聚對二甲苯類高分子、焊罩材料、彈性材料或多 孔性介電材料其中之一,且硬化後的聚合物層90厚度比如 是介於2微米至30微米之間(較佳厚度則是介於3微米至 12微米之間),而形成方式包括有旋塗、熱壓合乾膜或是 網版印刷等方式。底下以形成一聚醯亞胺層在金屬線路88 上與聚合物層36上,並圖案化聚醯亞胺層的内容作為形成 且圖案化聚合物層90的舉例說明,然熟習該技術者當可藉 由下列實施例的說明,以其它聚合物的材料(例如苯基環丁 烯或環氧樹脂)來據β實施。 第一種形成且圖案化聚合物層90的方式,係利用一旋 塗製程旋塗厚度介於4微米至60微米之間(較佳厚度則是 介於6微米至24微米之間)的一感光性聚醯亞胺層在金屬 線路88上與聚合物層36上,接著依序透過烘烤、曝光與 顯影等製程圖案化聚醯亞胺層,以形成至少一聚醯亞胺層 開口在聚醯亞胺層内並暴露出金屬線路88,而在圖案化聚 醯亞胺層的過程中是利用一倍(IX)之曝光機以含有G線 (G-line)、H線(H-line)與I線(I-line)三種波長中至少二者的 光'熨髡趨亞胺層進行曝光,亦即利一傍-之光蜂以 48 1353652 含有 G 線(G-line)與 Η 線(H-line)、含有 G 線(G-line^ 工 線(I-line)、含有Η線(H-line)與I線(I-line)或是含有α線 (G-line)、H線(H-line)與I線(i_nne)的光源照射聚醯亞胺層 進行曝光。最後,於氮氣環境或無氧環境中,利用硬化製 程在溫度介於20(TC至290°C之間、介於290°C至330。(:之 間或是介於330°C至40(TC之間硬化聚醯亞胺層,其中進行 硬化製程的時間係介於30分鐘至2小時之間,而硬化後的 聚醯亞胺層厚度係介於2微米圭30微米之間(較佳厚度則 疋介於3微米至12微米之間)。此外,在硬化聚醯亞胺層 之後,可以利用含有氧離子之電漿(A plasma)或是含有氟 離子濃度小於200PPM與氧離子之電漿去除聚醯亞胺層開 口所暴露出之金屬線路88上表面的聚合物殘留.物或其它 異物。For example, the method of forming the photoresist layer 84 and the patterned photoresist layer 84 of the present invention may be performed by spin coating with a thickness of between 5 micrometers and 30 micrometers (preferably, a thickness of between 7 micrometers and 15 micrometers). A positive-type photoresist layer is on the metal layer 82, and a double (IX) stepper is used to contain two kinds of G-line and Η-line length+, G-line and 1"-line soil wave Hanging 3 has a binding and an I 45 ^53652 line, or a light source with a G-line, a Η line, and an I-line wavelength, illuminating the positive-type photoresist layer for exposure. Then developing the positive-type photoresist through the development process. The layer 'shows the plated pattern to form the photoresist layer opening 84a in the photoresist layer 84 and exposes the metal layer 82 above the two connection lines 24a, 24b and over the portion of the polymer layer 36. The wavelength range is between 434 nm and 438 nm. The wavelength range of the Η line is between 403 nm and 407 nm, and the wavelength range of the I line is between 363 nm and 367. Between the rice. Please refer to Figure 11C for the thickness of the plating to form! A metal layer % between micrometers and 2 micrometers (e.g., between 1 micrometer and 50 micrometers) is on the metal layer 82 exposed by the photoresist layer opening 84a. The preferred thickness of the metal layer 86 is between 2 The micro-layer is between 30 microns and the metal layer 86 may be a single-layer metal structure of gold, copper, silver, palladium, platinum, rhodium, ruthenium, iridium or nickel or a composite layer metal structure composed of the above metal materials. Alternatively, the manner in which the metal layer 86 is formed may also include an electroless plating process. For example, the metal layer 86 may be formed by electroplating to a thickness of between 2 micrometers and 35 micrometers. A gold layer is exposed on the metal layer 82 of the photoresist layer opening "a, such as gold, or A copper layer formed by electroplating having a thickness between 2 micrometers and 35 micrometers is exposed on the photoresist layer opening 84a, such as a copper metal layer 82. Again, the manner in which the metal layer 86 is formed For example, a copper layer having a thickness of between 2 micrometers and 35 micrometers is placed on a metal layer 82 of a material such as copper, and then the thickness of the electricity is between 0.1 micrometers and 10 micrometers (preferably thickness). The system is between 〇丨 micron to 5 nickel layer in this copper layer, the last two plating thickness is Ό.Ό1 &quot;** . ·*^&quot;^·· · Μ &lt; . - — * - —— I - &quot; * \ — — - - - -- 46 1353652 A gold layer between the micro half and 10 microns (preferably between 0.1 microns and 2 mm) is on this town layer. As shown in Fig. 11D, after the metal layer 86 is formed, the photoresist layer 84 is subsequently removed. Further, after the photoresist layer 84 is removed, the plasma may be passed first (for example). The metal layer 86 and the metal layer 82 are cleaned by a plasma containing oxygen ions or a plasma containing a fluoride ion-concentration of less than 200 PPM and oxygen ions, thereby removing photoresist residues on the upper surface of the metal layer 86 and the upper surface of the metal layer 82. Or other foreign matter. Continuing, as shown in FIG. 11E, the metal layer 82 and the metal layer 80 that are not under the metal layer 86 are removed. The manner in which the metal layer 82 and the metal layer 80 are not under the metal layer 86 is removed, for example. It is removed by etching, and the etching method can be divided into dry etching and wet etching, and dry etching includes chemical plasma etching, splash etching (such as sputtering etching using high-pressure argon gas) and chemical gas etching. For example, in wet etching In the aspect, when the metal layer 80 is a titanium-tungsten alloy, it can be removed by etching using a solution containing hydrogen peroxide, and when the metal layer 80 is titanium, it can be removed by etching using a solution containing cyanofluoric acid, and when the metal layer 82 is gold, It can be etched and removed by using an iodine-containing etching solution (for example, an etchant containing potassium iodide); in the dry etching, when the metal layer 80 is titanium or a titanium-tungsten alloy Bf, chlorine-containing electrical etching can be used. The metal layer 82 is removed, and when the metal layer 82 is gold, it can be removed by high-pressure argon gas. Therefore, the present invention can form a metal line 88 on the polymer layer 36 and the two polymer layer openings 36a. The connecting lines 24a, 24b are connected to the two connecting lines 24a, 24b exposed by the two polymer layer openings 36a. The metal lines 88 are formed by a metal layer 80 and a metal layer 82 on the metal layer 80. A metal layer 86 on the metal layer 82 is formed by -47-'--- 1353652. _ See FIG. 11F, the present invention removes the metal layer 82 that is not under the metal layer 86. After the metal layer 80, a polymer layer 90 can be formed over the metal lines 88 and the polymer layer 36, and a polymer layer opening 90a in the polymer layer 90 exposes the metal lines 88. Wherein, the polymer layer 90 is, for example, selected from the group consisting of polyimide, phenylcyclobutene, polyurethane, epoxy resin, polyparaxylene polymer, solder mask material, elastic material or porous dielectric material. One, and the thickness of the hardened polymer layer 90 is, for example, between 2 micrometers and 30 micrometers (preferably, the thickness is between 3 micrometers and 12 micrometers), and the formation includes spin coating and hot pressing. Dry film or screen printing. Bottom to form a polyimine layer on the metal line 88 and the polymer layer 36, and to pattern the content of the polyimide layer as an example of forming and patterning the polymer layer 90, but the skilled person It can be carried out according to the use of other polymer materials (for example, phenylcyclobutene or epoxy resin) according to the following examples. The first method of forming and patterning the polymer layer 90 is by spin coating a spin coating process having a thickness between 4 microns and 60 microns (preferably between 6 microns and 24 microns). The photosensitive polyimide layer is patterned on the metal line 88 and the polymer layer 36, followed by a process of baking, exposing and developing a polyimine layer to form at least one polyimide layer opening. The metal line 88 is exposed in the polyimide layer, and in the process of patterning the polyimide layer, the exposure machine is doubled (IX) to contain G-line and H-line (H- Line) and at least two of the three wavelengths of the I-line (I-line) are exposed to the imine layer, that is, the light bee has a G-line and a plaque at 48 1353652. Line (H-line), containing G line (G-line^I-line, containing H-line and I-line or containing α-line (G-line), The light source of the H-line and the I-line (i_nne) is exposed to the polyimide layer for exposure. Finally, in a nitrogen atmosphere or an oxygen-free environment, the curing process is performed at a temperature of 20 (TC to 290 ° C). Between 290 ° C and 330. (: Or between 330 ° C and 40 (TC hardened polyimide layer, wherein the hardening process is carried out between 30 minutes and 2 hours, and the hardened polyimide layer thickness is between 2 micrometers between 30 micrometers (preferably, the thickness is between 3 micrometers and 12 micrometers). In addition, after hardening the polyimide layer, a plasma containing oxygen ions (A plasma) or containing The plasma having a fluoride ion concentration of less than 200 PPM and oxygen ions removes polymer residues or other foreign matter on the upper surface of the metal line 88 exposed by the opening of the polyimide layer.

第二種形成域案化聚合物;| 9G的方式,係利用旋塗 製程旋塗厚度介於4微米至60微米之間(較佳厚度則是介 於6微米至24微米之間)且感光性的一第一聚醯亞胺層在 金屬線路88上與聚合物層36上,接著依序透過烘烤、曝 光與顯影等製程圖案化第一聚醯亞胺層,以形成至少一第 -聚醯亞胺層開口在第一聚醯亞胺層内並暴露出金屬線路 88,而在圖案化第一聚醯亞胺層的過程中是利用一俨之曝 光機以含有G線(G-line)、Η線(H-line)與丨線⑴如^三種 波長中至少二者的光源照射第一聚醯亞胺層進行曝光。繼 續,於氮氣環境或無氧環境中,利用硬化製程在溫产介於 330 恶^或是介:、 49 1353652 c至4〇(rc之間硬化第一聚醯亞胺層,其中進行硬化製程 的時間係介於30分鐘至2小時之間,而硬化後的第一聚:醯 亞胺層厚度係介於2微米至30微米之間(較佳厚度則是介 於3微米至12微米之間)。另,在硬化第一聚醯亞胺層之 後’可以選擇先湘含有祕子之電漿或是含魏離子濃 度小於200PPM與氧離子之電漿去除第—聚醯亞胺層開&lt;口 所暴露出之金屬線路88上表面的聚合物殘留物或立它昱 物。 ^The second type of domain-forming polymer; | 9G is a spin coating process with a spin coating thickness between 4 microns and 60 microns (preferably between 6 microns and 24 microns) and sensitized a first polyimine layer on the metal line 88 and the polymer layer 36, followed by sequential baking, exposure and development processes to pattern the first polyimide layer to form at least one first - The polyimide layer opens in the first polyimide layer and exposes the metal line 88, and in the process of patterning the first polyimide layer, the exposure machine is used to contain the G line (G- A line of light, at least two of the three wavelengths, H-line and 丨 (1), illuminate the first polyimide layer for exposure. Continue, in a nitrogen atmosphere or an oxygen-free environment, using a hardening process at a temperature of between 330 ^ or 介:, 49 1353652 c to 4 〇 (r hardened the first polyimine layer between the rc, wherein the hardening process is carried out The time is between 30 minutes and 2 hours, and the hardened first poly-imine layer thickness is between 2 microns and 30 microns (preferably between 3 microns and 12 microns) In addition, after hardening the first polyimine layer, it is possible to select a plasma containing a secret or a plasma containing a concentration of less than 200 PPM and oxygen ions to remove the first layer of polyimine. The polymer residue on the upper surface of the metal line 88 exposed or exposed to the mouth.

再來,以形成且圖案化第一聚醯亞胺層的步驟形成一 第二聚醯亞胺層在第一聚醯亞胺層上,並形成至少一第二 聚酿亞胺層開口|第二聚醯亞胺層内且暴露出帛一聚酿亞 胺層開口所暴露出之金屬線路88。因此,聚合物層9〇可 以是由第一聚醯亞胺層與第二聚醯亞胺層所構成,且聚合 物層開口 90a可以是第二聚醯亞胺層開口本身或是由第一 聚醯亞胺層開口與第二聚醯亞胺層開口所構成。最後,在 硬化第二聚醯亞胺層之後,可以利用含有氧離子之電漿或 是含有氟離子濃度小於200PPM與氧離子之電漿去除第L 聚酿亞胺層開口所暴露ϋ{之金屬線路88上表面的聚合物 殘留物或其它異物。 &quot; 第三種形成且圖案化聚合物層9〇的方式,是以第二種 形成且圖案化聚合物層90的方式為基礎,於形成第二聚醯 亞胺層後,以形成第二聚醯亞胺層的方式繼續形成一層或 一層以上的聚醯亞胺層在第二聚醯亞胺層上,亦即形成^Further, the step of forming and patterning the first polyimide layer forms a second polyimide layer on the first polyimide layer and forming at least one second polyimide layer opening | The metal line 88 exposed by the opening of the bismuth iminoimine layer is exposed within the dimeric quinone layer. Therefore, the polymer layer 9 can be composed of the first polyimide layer and the second polyimide layer, and the polymer layer opening 90a can be the second polyimide layer opening itself or by the first The opening of the polyimide layer and the opening of the second polyimide layer are formed. Finally, after hardening the second polyimine layer, the metal containing the oxygen ion or the plasma containing the fluoride ion concentration of less than 200 PPM and the oxygen ion may be used to remove the metal exposed by the opening of the L-polyimine layer. Polymer residue or other foreign matter on the upper surface of line 88. &quot; The third way of forming and patterning the polymer layer 9〇 is based on the second formation and patterning of the polymer layer 90, after forming the second polyimide layer to form a second The polyimine layer continues to form one or more layers of polyimine on the second polyimide layer, ie,

Hi 包多光製程、 • .. r ·-ψ· &gt;. 50 1353652 複數次顯影製程與_複數次硬化製程。其中,在每次硬化製 程之後,皆可選擇利用i有氧離子之電漿或是含有氟離子 濃度小於200PPM與氧離子之電漿去除聚醯亞胺層開口所 暴露出之金屬線路88上表面的聚合物殘留物或其它異 物,或是於最後一次硬化製程之後,再利用含有氧離子之 電漿或是含有氟離子濃度小於200PPM與氧離子之電漿去 除聚醯亞胺層開口所暴露出之金屬線路88上表面的聚合 物殘留物或其它異物。 在完成上述製程之後,接著可切割半導體基底2,以 形成複數晶片。此外,這些晶片可以進一步透遏下列所述 之方式連接外部電路。 a. 這些晶片可以透過打線製程接合一打線導線至聚合物 層開口 90a所暴露出之金屬線路88上而連接外部電路。 b. 於切割半導體基底2之前,形成含錫金屬層在聚合物層 開口 90a所暴露出之金屬線路88的上方,並在切割半導體 基底2形成複數晶片後,透過含錫金屬層使這些晶片連接 外部電路。其中,含錫金屬層比如是錫錯合金(tin-lead alloy)、錫銀.合金(tin-silver alloy)、錫銀銅合金 (tin-silver-copper alloy)或無錯合金(lead-free alloy),以錫 鉛合金為例,其錫/鉛比可視需求而有所調整,較 常見的錫鉛比為90/10、95/5、97/3、37/63等比例。 c. 於切割半導體基底2之前,形成金屬凸塊(metal bump) 在聚合物層開口 90a所暴露出之金屬線路88的上方,並在 切,半f寧基底形名複數晶片,透金屬凸n仓ΐϋ 1353652 凸塊)使這些晶片連接外部電路。 . 雷 . * — ------------. 八 上述的外部電蝽比如是半導體晶片、 含有玻璃纖維的印刷電路板(PCB)、含有厚度介於 30微米至200微米間之一聚合物層(比如是聚醯亞 胺)的軟板、含有陶瓷材料之基板、玻璃基板或事 先 t 成之被動元件(discrete passjve device)。 第三種篕鋥 於兀成上述保護層32或開口 32a的步驟後,接著請參 閱第12A圖所不,形成厚度介於〇〇1微米至3微米之間(較 佳厚度係介於G.G1微米至1微米之間)的-金屬層92在保 護層32上與開口 32a所暴露出之金屬線路24上,其中此 金屬線路24比如是一重配置線路(RDL),且從俯視透視圖 之開口 32a所暴露出之金屬線路24的位置係不同於開 口 所暴露.出之金屬層1〇的位置,另外此金屬層92係 作為黏著/阻障層,其作用在於提供金屬線路與金屬材 料間良好之接著力,並可防止金屬線路2 4與金屬材料間的 擴散反應。金屬層92的材質比如是選自鈦、鎢、始、錄、 氮化鈦、鈦鎢合金、鏵釩合金、鈕、氮化鈕、鉻、銅、鉻 鋼合金、金、鎖、麵、把、釕、錢以及銀其中之一或所組 成之群組的至少其中之一者,而形成方式比如是利用濺鍍 或蒸鍍方式。 例如,金屬層92可以是厚度介於〇.(Π微米至3微升 之間(較佳厚度係介於0.01微米至i微米之間)的一鈦層演 礙赛路24的翁 '* ~--------- -·__ 52 1353652 層上;或者,金屬層92可以是厚度介於0.01微米至3微 米之間(較佳Ϊ度也介於0.01微米至1微米之間)的一鈦層 ' 濺鍍在保護層32上與開口 32a所暴露出之金屬線路24的 鎳層上;或者,金屬層92可以是厚度介於0.01微米至3 微米之間(較佳厚度係介於0.01微米至1微米之間)的一鈦 一 _ 層濺鍍在保護層32上與開口 32a所暴露出之金屬線路24 的金層上;或者,金屬層92可以是厚度介於0.01微米至 3微米之間(較佳厚度係介於0.01微米至1微米之間)的一 鈦鎢合金層濺鍍在保護層32上與開口 32a所暴露出之金屬 線路24的銅層上;或者,金屬層92可以是厚度介於0.01 微米至3微米之間(較佳厚度係介於0.01微米至1微米之 間)的一鈦鎢合金層濺鍍在保護層32上與開口 32a所暴露 出之金屬線路24的鎳層上;或者,金屬層92可以是厚度 介於0.01微米至3微米之間(較佳厚度係介於0.01微米至 1微米之間)的一鈦鎢合金層濺鍍在保護層32上與開口 32a 所暴露出之金屬線路24的金層上。 再來,形成厚度介於0.005微米至2微米之間(較佳厚. 度係介於0.1微米至0.7微米之間)的一金屬層94在金屬層 92上,此金屬層94係作為電鍍時的導電層以及種子層。 形成金屬層94的方式比如是濺鍍、蒸鍍、物理氣相沉積或 者是無電電鍍等方式。由於金屬層94可有利於後續金屬層 的設置,因此金屬層94的材質會隨後續金屬層的材質而有 所變化,如當電鍍形成材質為銅的金屬層在金屬層94上 時,金屬層94的材質係以銅為佳;當電鍍形成材質為金的 53 1353652 金屬層在金屬層94上時,金屬層94的材質係以金為佳。Hi package multi-light process, • .. r ·-ψ· &gt;. 50 1353652 multiple development process and _ complex hardening process. Wherein, after each hardening process, a plasma of i aerobic ions or a plasma containing a fluoride ion concentration of less than 200 PPM and oxygen ions may be selected to remove the upper surface of the metal line 88 exposed by the opening of the polyimide layer. Polymer residue or other foreign matter, or after the last hardening process, using a plasma containing oxygen ions or a plasma containing a fluoride ion concentration of less than 200 PPM and oxygen ions to remove the polyimide layer opening A polymer residue or other foreign matter on the upper surface of the metal line 88. After the above process is completed, the semiconductor substrate 2 can then be diced to form a plurality of wafers. In addition, these wafers can be further connected to external circuits in a manner that is described below. a. These wafers can be connected to an external circuit by bonding a wire conductor to the metal line 88 exposed by the polymer layer opening 90a through a wire bonding process. b. Before cutting the semiconductor substrate 2, forming a tin-containing metal layer over the metal line 88 exposed by the polymer layer opening 90a, and after cutting the semiconductor substrate 2 to form a plurality of wafers, connecting the wafers through the tin-containing metal layer External circuit. Wherein, the tin-containing metal layer is, for example, a tin-lead alloy, a tin-silver alloy, a tin-silver-copper alloy or a lead-free alloy. For example, tin-lead alloys have their tin/lead ratio adjusted according to demand. The common ratio of tin-lead is 90/10, 95/5, 97/3, 37/63. c. Before cutting the semiconductor substrate 2, a metal bump is formed over the metal line 88 exposed by the polymer layer opening 90a, and is cut, and the semiconductor wafer is named as a plurality of wafers. Cangjie 1353652 Bumps) Connect these wafers to external circuits. Ray. * — ------------. 8. The external electrical device mentioned above is, for example, a semiconductor wafer, a printed circuit board (PCB) containing glass fibers, and having a thickness between 30 micrometers and 200 micrometers. A soft plate of a polymer layer (such as polyimide), a substrate containing a ceramic material, a glass substrate or a discrete passjve device. After the third step of forming the protective layer 32 or the opening 32a, please refer to FIG. 12A to form a thickness between 〇〇1 μm and 3 μm (preferably, the thickness is between G. a metal layer 92 of between G1 micrometers and 1 micrometer is on the protective layer 32 and the metal line 24 exposed by the opening 32a, wherein the metal line 24 is, for example, a reconfiguration line (RDL), and is viewed from a top perspective view. The position of the metal line 24 exposed by the opening 32a is different from the position of the metal layer 1〇 exposed by the opening, and the metal layer 92 acts as an adhesion/barrier layer, and functions to provide a metal line and a metal material. Good adhesion and prevent diffusion reaction between the metal line 24 and the metal material. The material of the metal layer 92 is, for example, selected from the group consisting of titanium, tungsten, quartz, titanium nitride, titanium tungsten alloy, niobium vanadium alloy, button, nitride button, chromium, copper, chrome steel alloy, gold, lock, surface, handle At least one of, or a group of, or a group of silver, formed by, for example, sputtering or evaporation. For example, the metal layer 92 may be a titanium layer that affects the thickness of the crucible (between Π micrometers and 3 microliters (preferably, the thickness is between 0.01 micrometers and i micrometers). --------- -·__ 52 1353652 on the layer; or, the metal layer 92 may be between 0.01 microns and 3 microns in thickness (preferably between 0.01 microns and 1 micron) a titanium layer is sputtered on the protective layer 32 on the nickel layer of the metal line 24 exposed by the opening 32a; or the metal layer 92 may be between 0.01 micrometers and 3 micrometers in thickness (preferably thickness) a layer of titanium between 0.01 micrometers and 1 micrometer is sputtered onto the gold layer of the metal line 24 exposed on the protective layer 32 and the opening 32a; alternatively, the metal layer 92 may have a thickness of 0.01 micron to A titanium-tungsten alloy layer between 3 microns (preferably having a thickness between 0.01 microns and 1 micron) is sputtered onto the protective layer 32 and the copper layer of the metal line 24 exposed by the opening 32a; or, metal Layer 92 can be a titanium-tungsten alloy layer having a thickness between 0.01 microns and 3 microns (preferably between 0.01 microns and 1 micron) Sputtered on the protective layer 32 on the nickel layer of the metal line 24 exposed by the opening 32a; alternatively, the metal layer 92 may have a thickness between 0.01 micrometers and 3 micrometers (preferably, the thickness is between 0.01 micrometers and 1 micrometer) A titanium-tungsten alloy layer between the micrometers is sputtered onto the gold layer of the metal line 24 exposed on the protective layer 32 and the opening 32a. Further, the thickness is formed between 0.005 micrometers and 2 micrometers (preferably thick) A metal layer 94 having a degree between 0.1 micrometers and 0.7 micrometers is on the metal layer 92. The metal layer 94 serves as a conductive layer and a seed layer during electroplating. The metal layer 94 is formed by sputtering, for example. Evaporation, physical vapor deposition or electroless plating, etc. Since the metal layer 94 can facilitate the subsequent metal layer setting, the material of the metal layer 94 will vary with the material of the subsequent metal layer, such as when forming materials by electroplating. When the metal layer of copper is on the metal layer 94, the material of the metal layer 94 is preferably copper; when the metal layer of 53 1353652 is formed on the metal layer 94 by electroplating, the material of the metal layer 94 is made of gold. good.

綜上所述,當金屬層92是以濺鍍方式所形成之厚度介 於0.01微米至3微米之間(較佳厚度係介於0.01微米至1 微米之間)的一含鈦金屬層時,金屬層94可以是厚度介於 0.005微米至2微米之間(較佳厚度係介於0·1微米至0.7 微米之間)的一銅層濺鍍在此含鈦金屬層上;或是,當金屬 層92是以濺鍍方式所形成之厚度介於0.01微米至3微米 之間(較佳厚度係介於0.01微米至1微米之間)的一鈦層 時,全屬層94可以是厚度介於0.005微米至2微米之間(較 佳厚度係介於0.1微米至0.7微米之間)的一銅層濺鍍在此 鈦層上;或是,當金屬層92是以濺鍍方式所形成之厚度介 於0.01微米至3微米之間(較佳厚度係介於0.01微米至1 微米之間)的一鈦鎢合金層時,金屬層94可以是厚度介於 0.005微米至2微米之間(較佳厚度係介於0.1微米至0.7 微米之間)的一銅層濺鍍在此鈦鎢合金層上。In summary, when the metal layer 92 is formed by sputtering, the thickness of the titanium-containing metal layer is between 0.01 micrometers and 3 micrometers (preferably, the thickness is between 0.01 micrometers and 1 micrometer). The metal layer 94 may be a copper layer having a thickness between 0.005 micrometers and 2 micrometers (preferably having a thickness between 0. 1 micrometer and 0.7 micrometer) on the titanium-containing metal layer; or, when When the metal layer 92 is formed by sputtering, a thickness of between 0.01 μm and 3 μm (preferably between 0.01 μm and 1 μm), the entire layer 94 may be a thickness layer. a copper layer between 0.005 micrometers and 2 micrometers (preferably having a thickness between 0.1 micrometers and 0.7 micrometers) is sputtered onto the titanium layer; or, when the metal layer 92 is formed by sputtering When a titanium-tungsten alloy layer having a thickness of between 0.01 micrometers and 3 micrometers (preferably having a thickness between 0.01 micrometers and 1 micrometer) is used, the metal layer 94 may have a thickness of between 0.005 micrometers and 2 micrometers. A copper layer having a thickness of between 0.1 micrometers and 0.7 micrometers is sputtered onto the titanium-tungsten alloy layer.

請參閱第12Β圖所示,形成一光阻層96在金屬層94 上,並透過曝光與顯影製程圖案化光阻層96,以形成至少 一光阻層開口 96a在光阻層96内並暴露出開口 32a所暴露 出之金屬線路24上方的金屬層94,而在形成光阻層開口 96a的過程中比如是利用一倍(IX)的曝光機(stepper)或一 倍(IX)的對準曝光機(contact aligner)進行曝光。 再來,請參閲第12C圖所示,形成一擴散阻障層 (diffusion barrier layer)98在光阻層開口 96a所暴露出之金 屬層94上,而形成擴散阻障層98却是藉由電鍍 ·~ · — ~ — - —1 &quot;― 1 —·· - · :..厂. ... — —;*· ~ ~ ^ *~ - -: 54 ....... 1353652 厚度介於0:5_微米至10微米之間的一銅層在材質例如是銅 的金屬層94上’接著電鍍厚度介於01微米至_5微米之間 的一鎳層在銅層上。因此,擴散阻障層98可以是由一銅層 與位在銅層上之一鎳層所構成。 接下來,形成厚度介於1微米至500微米之間的一含 錫金屬層100在光阻層開口 96a内之擴散阻障層98上,此 含錫金屬層100的較佳厚度係介於3微米至25〇微米之 間而形成含錫金屬層1〇〇的方式比如是電鍍、無電電鍍 或者是網板印刷。另,此含錫金屬層100比如是錫鉛合金 (tm Iead all〇y)、錫銀合金(tin-silver alloy)、錫銀銅合金 (Q0pper all〇y)或無紹合金(lead-free alloy)。以錫 2合金為例,其錫/鉛比可梘需求而有所調整,較 常見的錫鉛比為90/10、95/5、97/3、37/63等比例。 由上可知,擴散阻障層98係位在含錫金屬層1〇〇 下方’此擴散阻障層98比如是包括厚度介於G1微米至5 :米之間的—錄層在含錫金屬層⑽下,以及厚度介於0.5 来至10微米之間的_銅層在錄層下,且制與銅層均位 在開口 32a所暴露出之金屬線路24上方。 銲料本發明亦可在擴散阻障層98上再形成- =沾附臈層(so如賊tablelaye卜圖中未示), :::後續含錫金屬層1〇。與擴散阻障層”之間的 錫、。錨粗此銲料沾附膜層之材質比如是金、鋼、 锡錯合金、錫銀人全 口金錫銀銅合金或無鉛合金等。 第12D圖所干,户Λ —成含錫金屬層100之後, . 一 I.. _Τ'- - 釋.辱 ^ 1-^. • · · ·. · . ~τ·- . .1. 一: 55 1353652 接著去除光阻層96。繼續,去除未在含錫金屬層100下方 的金屬層94與金屬層92。其中,去除金屬層94與金屬層 92的方式比如是以蝕刻方式去除,而蝕刻方式可分為乾蝕 刻與濕蝕刻,另乾蝕刻包括化學電漿蝕刻、濺擊蝕刻(如使 用高壓氬氣進行濺擊蝕刻)與化學氣體姑刻。例如在濕蝕刻 方面,當金屬層92為欽鶴合金時,可以使用含有雙氧水的 溶液蝕刻去除,而當金屬層92為鈦時,可以使用含有氰氟 酸的溶液蝕刻去除;在乾蝕刻方面,當金屬層92為鈦或鈦 鎢合金時,可使用含氯的電漿蝕刻去除。 請參閱第12E圖所示,在去除未在含錫金屬層100下 方的金屬層94與金屬層92之後,可選擇進行一迴銲 (reflow)製程,使含錫金屬層100到達熔點而内聚成球形。 惟,本發明亦可先進行迴銲製程,使含錫金屬層100到達 熔點而内聚成球形,接著再去除未在含錫金屬層100下方 的金屬層94與金屬層92;或者,本發明亦可先不進行回 銲製程,直到含錫金屬層100連接外部電路時,才進行回 銲製程。 於完成上述製程之後,接著可切割半導體基底2,以 形成複數晶片,且這些晶片可以透過含錫金屬層1〇〇而連 接外部電路。其中,此外部電路比如是半導體晶片、含有 玻璃纖維之印刷電路板、含有厚度介於30微米至200微米 間之一聚合物層的軟板、含有陶瓷材料之基板或是事先形 成之被動元件等。 以上所述係藉由雩施土J說喝_本_營叼4特點,其目的在 56 1353652 二Γ…使ϋ習該技術者能暸解本發明之内容並據以-實施.,:而非限 -. ·.··-..··· - . · . · _ - _ - . . . .. · · 定本發明之專利範園,故,凡其他未脫離本i明所:揭示之 精神所元成之等效修飾或修改,仍應包含在以下所述之申 請專利範圍中。 【圖式簡單說明】 圖式說明: 第1圖為本發明之一晶圓的剖面示意圖。 第2 A圖至第.2J圖為本發明形成金屬線路的.製程剖面示音 圖。 &quot; 第3A圖至第3F圖為本發明形成保護層及其開口的製程剖 面示意圖。 第4A圖至第4F圖為本發明形成保護層及其開口的製程剖 面示意圖。 第5圖為本發明形成保護層及其開口的製程剖面示意圖。 第6A圖至第6F圖為本發明形成保護層及其開口的製程剖 面示意圖。 第7圖舞本發明形成保護層及其開口的製程剖面示:意圖。 第8A圖至第8F圖為本發明形成保護層及其開口的製程剖 面不意圖。 第9A圖至第9G圖為本發明之一實施例的製程剖面示意 圖。 第10A圖至第10F圖為本發明之一實施例的製程剖面示意 圖。. 1353652 第11AJ至第11芒圖為本發明主一實施例的製程剖J&amp;示意 圖。 ' - 第12A圖至第12E圖為本發明之一實施例的製程剖面示意 圖。 圖號說明:Referring to FIG. 12, a photoresist layer 96 is formed on the metal layer 94, and the photoresist layer 96 is patterned through an exposure and development process to form at least one photoresist layer opening 96a in the photoresist layer 96 and exposed. The metal layer 94 above the metal line 24 exposed by the opening 32a is formed, and in the process of forming the photoresist layer opening 96a, for example, a stepper or a double (IX) alignment is utilized. The exposure aligner is used for exposure. Then, referring to FIG. 12C, a diffusion barrier layer 98 is formed on the metal layer 94 exposed by the photoresist layer opening 96a, and the diffusion barrier layer 98 is formed by using a diffusion barrier layer 98. Plating·~ · — ~ — — —1 &quot;― 1 —·· - · :..厂....... — —*· ~ ~ ^ *~ - -: 54 ....... 1353652 Thickness A copper layer between 0:5 microns and 10 microns is on the metal layer 94 of material, such as copper, and a nickel layer having a thickness between 01 microns and _5 microns is then plated over the copper layer. Therefore, the diffusion barrier layer 98 may be composed of a copper layer and a nickel layer on the copper layer. Next, a tin-containing metal layer 100 having a thickness between 1 micrometer and 500 micrometers is formed on the diffusion barrier layer 98 in the photoresist layer opening 96a. The preferred thickness of the tin-containing metal layer 100 is 3 The manner in which the tin-containing metal layer is formed between micrometers and 25 micrometers is, for example, electroplating, electroless plating, or screen printing. In addition, the tin-containing metal layer 100 is, for example, tin-lead alloy (tm Iead all〇y), tin-silver alloy, tin-silver-copper alloy (Q0pper all〇y) or lead-free alloy (lead-free alloy). ). Taking tin 2 alloy as an example, the tin/lead ratio can be adjusted according to the demand, and the common ratio of tin to lead is 90/10, 95/5, 97/3, 37/63. As can be seen from the above, the diffusion barrier layer 98 is located below the tin-containing metal layer 1'. The diffusion barrier layer 98 includes, for example, a thickness of between G1 micrometers and 5 meters. (10) Next, and a copper layer having a thickness between 0.5 and 10 microns is under the recording layer, and the copper layer is formed over the metal line 24 exposed by the opening 32a. Solder The present invention can also be formed on the diffusion barrier layer 98 - a smear layer (so is not shown in the thief tablelaye), ::: a subsequent tin-containing metal layer 1 〇. The tin between the diffusion barrier layer and the anchor layer is made of gold, steel, tin alloy, tin-silver full-mouth gold-silver-copper-copper alloy or lead-free alloy, etc. Figure 12D Dry, household Λ - after forming a tin-containing metal layer 100, . I.. _Τ'- - Release. Insult ^ 1-^. • · · · · · ~τ·- . .1. A. 55 1353652 Continue The photoresist layer 96 is removed. Continuing to remove the metal layer 94 and the metal layer 92 that are not under the tin-containing metal layer 100. The manner of removing the metal layer 94 and the metal layer 92 is, for example, removed by etching, and the etching method can be divided. For dry etching and wet etching, another dry etching includes chemical plasma etching, splash etching (such as sputtering with high pressure argon) and chemical gas etching. For example, in wet etching, when the metal layer 92 is a Chinhe alloy When the metal layer 92 is titanium, it can be removed by etching using a solution containing cyanofluoric acid; in the dry etching, when the metal layer 92 is titanium or titanium tungsten alloy, it can be used. Chlorine-containing plasma is removed by etching. See Figure 12E for removal. After the metal layer 94 and the metal layer 92 under the tin-containing metal layer 100, a reflow process may be selected to cause the tin-containing metal layer 100 to reach a melting point and cohere into a spherical shape. However, the present invention may also be performed first. The reflow process is such that the tin-containing metal layer 100 reaches the melting point and is internally spherical, and then the metal layer 94 and the metal layer 92 not under the tin-containing metal layer 100 are removed; or the present invention may not be subjected to the reflow process. The reflow process is not performed until the tin-containing metal layer 100 is connected to the external circuit. After the above process is completed, the semiconductor substrate 2 can be subsequently cut to form a plurality of wafers, and the wafers can be connected through the tin-containing metal layer 1 An external circuit, such as a semiconductor wafer, a printed circuit board containing glass fibers, a soft board containing a polymer layer having a thickness of between 30 micrometers and 200 micrometers, a substrate containing a ceramic material, or a preformed surface. Passive components, etc. The above description is based on the characteristics of the drink _ _ _ camp 叼 4, its purpose is 56 1353652 Γ ϋ ϋ 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该To - implement.,: not limited -. ····-..···-. · · · _ - _ - . . . . . . . . . . . . . . . . . . . The equivalent modification or modification of the spirit of the disclosure shall be included in the scope of the patent application described below. [Simple description of the schema] Schematic description: Figure 1 is a crystal of the invention Schematic diagram of a circular cross section. Fig. 2A to Fig. 2J are diagrams showing a process profile of a metal circuit according to the present invention. &quot; Figs. 3A to 3F are schematic cross-sectional views showing a process for forming a protective layer and an opening thereof according to the present invention. . 4A to 4F are schematic cross-sectional views showing a process for forming a protective layer and an opening thereof according to the present invention. Fig. 5 is a schematic cross-sectional view showing a process for forming a protective layer and an opening thereof according to the present invention. 6A to 6F are schematic cross-sectional views showing a process for forming a protective layer and an opening thereof according to the present invention. Figure 7 is a schematic cross-sectional view showing the formation of a protective layer and its opening. 8A to 8F are schematic views of a process section for forming a protective layer and an opening thereof according to the present invention. 9A to 9G are schematic cross-sectional views showing a process of an embodiment of the present invention. 10A to 10F are schematic cross-sectional views showing a process of an embodiment of the present invention. 1353652 11AJ to 11th are schematic views of a process section of a main embodiment of the present invention. ' - 12A to 12E are schematic cross-sectional views showing a process of an embodiment of the present invention. Description of the figure:

2半導體基底 6線終結構 10金屬層 14含矽介電層 15光阻層.2 semiconductor substrate 6-wire final structure 10 metal layer 14 containing germanium dielectric layer 15 photoresist layer.

4半導體元件 8介電層 12金屬插塞 14a 開口 15a光阻層開口 1 8金屬層 20a光阻層開口 24金屬線路 24b連接線路 28氧矽化合物層 32保護層 34光阻層 3 6聚合物層 38氮矽化合物層 42旋塗式玻璃層 46光阻層 48聚合物層 5 0聚合物層 16黏著/擴散阻障層 20光阻層 22金屬層 24a連接線路 26氮矽化合物層 3〇氮矽化合物層 32a 開口 34a光阻層開口 36a聚合物層開口 40氧矽化合物層 44氮矽化合物層 46a光阻+層開口 48a聚合物層開口 13536524 semiconductor element 8 dielectric layer 12 metal plug 14a opening 15a photoresist layer opening 1 8 metal layer 20a photoresist layer opening 24 metal line 24b connecting line 28 oxon compound layer 32 protective layer 34 photoresist layer 3 6 polymer layer 38 arsenide compound layer 42 spin-on glass layer 46 photoresist layer 48 polymer layer 50 polymer layer 16 adhesion/diffusion barrier layer 20 photoresist layer 22 metal layer 24a connection line 26 yttrium compound layer 3 〇 矽Compound layer 32a opening 34a photoresist layer opening 36a polymer layer opening 40 oxon compound layer 44 arsenide compound layer 46a photoresist + layer opening 48a polymer layer opening 1353652

'52…氮硬也二舍氣層—-'52...the nitrogen is hard and the second layer is -

- * ~ , , +r · . *· ·3ΐ^,二 * - «C • . — - . —, . .·: . —r 56旋塗式玻璃層 60氮矽化合物層 62a光阻層開口 64a聚合物層開口 68氮矽化合物層 70a光阻層開口 72a聚合物層開口 74a光阻層開口 76a光阻層開口 80金屬層 8 4光阻層 86金屬層 90聚合物層 92金屬層 96光阻層 98擴散阻障層 54氧砍化合物層 5 8氧梦化合物層 62光阻層 64聚合物層 66聚合物層_ 70光阻層 72聚合物層 74光阻層 76光阻層 78接墊 82金屬層 84a光阻層開口 88金屬線路 90a聚合物層開口 94金屬層 96a光阻層開口 100含錫金屬層- * ~ , , +r · . *· ·3ΐ^, two * - «C • . - - . -, . . . : - r 56 spin-on glass layer 60 nitride compound layer 62a photoresist layer opening 64a polymer layer opening 68 arsenide compound layer 70a photoresist layer opening 72a polymer layer opening 74a photoresist layer opening 76a photoresist layer opening 80 metal layer 8 4 photoresist layer 86 metal layer 90 polymer layer 92 metal layer 96 light Resistive layer 98 diffusion barrier layer 54 oxygen chopping compound layer 58 oxygen dream compound layer 62 photoresist layer 64 polymer layer 66 polymer layer _ 70 photoresist layer 72 polymer layer 74 photoresist layer 76 photoresist layer 78 pad 82 metal layer 84a photoresist layer opening 88 metal line 90a polymer layer opening 94 metal layer 96a photoresist layer opening 100 tin-containing metal layer

Claims (1)

第096122418號專利申請案 _文申請專利範圍替換^〇〇〇年3 十、申請專利範圍Patent application No. 096122418 _Application for patent scope replacement ^〇〇〇年十十, application patent scope 一半導體基底; 一第—介電層, 一線路結構,位 ,位於該半導體基底上方; 包括複數第一金屬層, 位於該第—介電層上方,該線路結構 鍵銅層; 層,該些第一金屬層包括複數電 第二介電層,位於該些第一金屬層之間; 第三介電層,位於該線路結構上方; 位於該第三介電層以及該線路結 一第一金屬線路, 構上方,該第一金屬線路接觸該線路結構的一第一 區域,並且經由位於該第三介電層内的一第一開口 連接该第一區域,該第一金屬線路包括一第二金屬 層以及位於該第二金屬層上方的一第三金屬層,該 第一金屬層與該第三金屬層之間沒有任何的介電 層; 一第二金屬線路,位於該第三介電層以及該線路結 構上方,該第二金屬線路接觸該線路結構的一第二 區域,並且經由位於該第三介電層内的一第二開口 連接該第二區域,該第二金屬線路包括一第四金屬 層以及位於該第四金屬層上方的一第五金屬層,該 第四金屬層與該第五金屬層之間沒有任何的介電 143044-1000331.doc 1353652 一絕緣層,位於該第一金屬線路、該第二金屬線路 以及該第三介電層上方,該絕緣層接觸該第三金屬 層的側壁以及該第五金屬層的側壁,該絕緣層包括 一氮化物層;以及 —第三金屬線路,位於該絕緣層、該第一金屬線路 以及該第二金屬線路上方,該第三金屬線路經由位 於該絕緣層内的一第三開口連接該第一金屬線路, 並且接觸該第一金屬線路的一表面區域’該第三金 屬線路經由位於該絕緣層内的一第四開口連接該第 二金屬線路,並且接觸該第二金屬線路的一表面區 域,該第一金屬線路經由該第三金屬線路連接該第 —金屬線路。 2、如申請專利範圍第1項所述之晶片,其中該半導體基 底為一石夕基底。 3如申明專利範圍第1項所述之晶片,更包括位於該半 導體基底内或上方的至少一金氧半導體(M〇s)元件。 4、 如申請專利範圍第丄項所述之晶片,其中該第二金屬 層僅位於該第二金屬層下方,該第四金屬層僅位於 該第五金屬層下方。 5、 如申請專利範圍第!項所述之晶片,其中該線路結構 更包括連接該些第—金屬層的複數金屬插塞。 6、 如申請專利範圍第i項所述之晶片,其中該第二介電 層包括介電常數值(k)介社5至3之間的材質。 143044-100033I.doc 1353652 • 7、如申請專利範圍第丨項所述之晶片,其中該第二介電 層的材質包括氧矽化合物、氮矽化合物或氮氧矽化 合物。 8 '如申請專利範圍第1項所述之晶片,其中該些第一金 屬層的厚度係小於3微米。 9、如申請專利範圍第1項所述之晶片,其中該些第一金 屬層更包括位於該些電鑛銅層下方的複數阻障層。 • 1〇、如申請專利範圍第9項所述之晶片,其中該些阻障層 的材質係選自鈕、氮化钽或氮化鈦。 11、 如申請專利範圍第1項所述之晶片,其中該第三介電 層包括一氮矽化合物層或一氮氧矽化合物層。 12、 如申請專利範圍第丨項所述之晶片,其中該第一金屬 線路更接觸該線路結構的一第三區域,並且經由位 於該第三介電層内的一第五開口連接該第三區域, 該第一區域經由該第一金屬線路連接該第三區域。 • 13'如申請專利範圍第丨項所述之晶片,其中該第二金屬 層的厚度係介於0.03微米至〇.5微米之間,該第四金 屬層的厚度係介於0.03微米至〇.5微米之間。 14、 如申請專利範圍第丨項所述之晶片,其中該第二金屬 層與該第四金屬層的材質包括鈦、鈦嫣合金、氮化 欽、絡或组。 15、 如申請專利範圍第丨項所述之晶片,其中該第三金屬 層的居·度係介於5微米至25微米之間,該第五金屬層 143044-1000331.doc 1353652 的厚度係介於5微米至25微米之間。 16、 如申請專利範圍第1項所述之晶片,其中該第三金屬 層包括一銅層、一鎳層或一金層。 17、 如申請專利範圍第1項所述之晶片,其中該第五金屬 層包括一電鍍金屬層。 18、 如申請專利範圍第1項所述之晶片,其中該第一金屬 線路與該第二金屬線路接觸該第三介電層的上表 面。 19、 如申請專利範圍第1項所述之晶片,其中該絕緣層更 包括一氧矽化合物層。 20、 如申請專利範圍第1項所述之晶片,其中該氮化物層 為一氮矽化合物層。 21、 如申請專利範圍第1項所述之晶片,更包括位於該絕 緣層與該第三金屬線路之間的一聚合物層。 22、 如申請專利範圍第!項所述之晶片,更包括位於該第 二金屬線路上方的一聚合物層。 23、 如申s青專利範圍第1項所述之晶片’更包括位於該絕 緣層上以及位於該第一金屬線路與該第二金屬線路 之間的一聚合物層。 24、 如申§青專利範圍第1項所述之晶片,其中該第三開口 的最大橫向尺寸係介於2微米至30微米之間,該第四 開口的最大橫向尺寸係介於2微米至30微米之間。 25、 如申請專利範圍第丨項所述之晶片,其中該第三金屬 -4- 143044-1000331.doc 26 線路包括一第六金屬層、位於該第六金屬層上的一 種子層以及位於該種子層上的一第七金屬層,該第 金屬層與該種子層僅位於該第七金屬層下方,該 第七金屬層的厚度係介於2微米至3〇微米之間。 如申請專利範圍第25項所述之晶片,其中該第六金 屬層的材質包括鈦、氮化鈦、鈦鎢合金、钽、氮化 纽、絡或絡銅合金。 27、 28、 29、 30、 31、 32、 33、 如申请專利範圍第25項所述之晶片,其中該種子層 的材質包括銅。 如申請專利範圍第25項所述之晶片,其中該第七金 屬層包括一銅層、一金層或一鎳層。 如申請專利範圍第1項所述之晶片,其中該第三金屬 線路包括·—電鍵金屬層。 如申請專利範圍第29項所述之晶片,其中該電錄金 屬層包括厚度介於2微米至35微米之間的一銅層。 如申請專利範圍第1項所述之晶片,更包括位於該第 二金屬線路上方的一金屬凸塊。 如申請專利範圍第1項所述之晶片,更包括位於該第 —金屬線路上方的·—含錫金屬層。 一種晶片’包括: 一半導體基底; 一第一鎮嵌(Damascene)金屬層,位於該半導體基 底上方,該第一鑲嵌·金屬層包括一銅層; 143044-1000331.doc 1353652 一第二鑲嵌金屬層,位於該半導體基底上方; 一含矽介電層,位於該半導體基底、該第一鑲嵌金 屬層以及該第二鑲嵌金屬層上方; 第一金屬線路,位於該含矽介電層以及該第一鑲 嵌金屬層上方,該第一金屬線路接觸該第一鑲嵌金 屬層的&quot;'表面區域,並且經由位於該含碎介電層内 的一第一開口連接該第一鑲嵌金屬層,該第一金屬 線路包括一第一金屬層以及位於該第一金屬層上方 的第一金屬層,該第一金屬層僅位於該第二金屬 層下方,該第一金屬層與該第二金屬層之間沒有任 何的介電層; 第一金屬線路,位於該含石夕介電層以及該第二鑲 嵌金屬層上方,忒第二金屬線路接觸該第二鑲嵌金 屬層的一表面區域,並且經由位於該含矽介電層内 的一第二開口連接該第二鑲嵌金屬層,該第二金屬 線路包括一第三金屬層以及位於該第三金屬層上方 的第四金屬層,該第三金屬層僅位於該第四金屬 層下方,該第三金屬層與該第四金屬層之間沒有任 何的介電層; -絕緣層,位於該第—金屬線路、該 以及該切介電層上方,該絕緣層包括—金= 層;以及 一第三金屬線路’位於該絕緣層、該第—金屬線路 143044-1000331.doc -6 - 以及該第二金屬線路上方,該第三金屬線路經由位 於該絕緣層内的一第三開口連接該第一金屬線路, 並且接觸該第一金屬線路的一表面區域,該第三金 屬線路經由位於該絕緣層内的一第四開口連接該第 二金屬線路’並且接觸該第二金屬線路的一表面區 域’該第一金屬線路經由該第三金屬線路連接該第 二金屬線路。 34、 如申請專利範圍第33項所述之晶片,其中該半導體 基底為一碎基底。 35、 如申請專利範圍第33項所述之晶片,更包括位於該 半導體基底内或上方的至少一金氧半導體(MOS)元 件。 36、 如申請專利範圍第33項所述之晶片,其中該絕緣層 接觸該第二金屬層的側壁以及該第四金屬層的側 壁。 37、 如申請專利範圍第33項所述之晶片,更包括位於該 半導體基底與該含矽介電層之間的複數第五金屬層 以及複數介電層。 38、 如申請專利範圍第33項所述之晶片’其中該第一鑲 嵌金屬層更包括位於該銅層下方的一阻障層。 39、 如申請專利範圍第38項所述之晶片’其中該阻障層 的材質包括鈕、氮化钽或氮化鈷。 40、 如申請專利範圍第33項所述之晶片,其中該含石夕介 143044-1000331.doc 電層包括一氮矽化合物層或一氮氧矽化合物層。 41、 如中請專利範圍第33項所述之晶片,更包括位於該 半導體基底上方的一第三鑲嵌金屬層,該含矽介電 層位於該第三鑲嵌金屬層上方,該第一金屬線路接 觸該第三鑲嵌金屬層的一表面區域,並且經由位於 該含矽介電層内的一第五開口連接該第三鑲嵌金屬 層,該第一鑲嵌金屬層經由該第一金屬線路連接該 第三鑲嵌金屬層。 42、 如申請專利範圍第33項所述之晶片,其中該第—金 屬層的厚度係介於〇.〇3微米至〇·5微米之間,該第= 金屬層的厚度係介於〇.〇3微米至〇·5微米之間。 43、 如申請專利範圍第33項所述之晶片,其中該第—金 屬層與該第三金屬層的材質包括鈦、鈦鎢合金、氮 化欽、絡或组。 44、 如申請專利範圍第33項所述之晶片,其中該 屬層的厚度係介於5微米至25微米之間,該第四金屬 層的厚度係介於5微米至25微米之間。 45、 如申請專利範圍第33項所述之晶片’其中該 &quot;&quot;&quot;— 屬層包括一銅層、一錄層或一金層》 46、 如申請專利範圍第33項所述之晶片,其中該第四金 屬層包括一電錢銅層。 47、 如申請專利範圍第33項所述之晶片,其中該 — 屬線路與該第二金屬線路接觸該含矽介電層的上表 143044-1000331.doc 48、 如申請專利範圍第33項所述之晶片,其中該絕緣層 更包括一氧妙化合物層。 49、 如申請專利範圍第33項所述之晶片,其中該氮化物 層為一氣碎化合物層。 50、 如申請專利範圍第33項所述之晶片,更包括位於該 絕緣層與該第三金屬線路之間的一聚合物層。 51、 如申請專利範圍第33項所述之晶片,更包括位於該 第三金屬線路上方的一聚合物層。 52、 如申請專利範圍第33項所述之晶片,更包括位於該 絕緣層上以及位於該第一金屬線路與該第二金屬線 路之間的一聚合物層。 5 3、如申請專利範圍第3 3項所述之晶片,其中該第三開 口的最大橫向尺寸係介於2微米至30微米之間,該第 四開口的最大橫向尺寸係介於2微米至3〇微米之間。 54、 如申請專利範圍第33項所述之晶片,其中該第三金 屬線路包括一第五金屬層、位於該第五金屬層上的 一種子層以及位於該種子層上的一第六金屬層,該 第五金屬層與該種子層僅位於該第六金屬層下方, 該第六金屬層的厚度係介於2微米至3〇微米之間。 55、 如申請專利範圍第54項所述之晶片,其中該第五金 屬層的材質包括鈦、氮化鈦、鈦鎢合金、钽、氮化 担、絡或絡銅合金。 143044-l000331.doc -9- 1353652 56、 如申請專利範圍第54項所述之晶片,其中該種子層 的材質包括銅。 57、 如申請專利範圍第54項所述之晶片,其中該第六金 屬層包括一銅層、一金層或一錄層。 58、 如申請專利範圍第33項所述之晶片,其中該第三金 屬線路包括厚度介於2微米至35微米之間的一電鍍銅 層。 59、 如申請專利範圍第33項所述之晶片,更包括位於該 第二金屬線路上方的一金屬凸塊。 60、 如申請專利範圍第33項所述之晶片,更包括位於該 第三金屬線路上方的一含錫金屬層。 10- 143044-1000331.doca semiconductor substrate; a first dielectric layer, a wiring structure, over the semiconductor substrate; a plurality of first metal layers over the first dielectric layer, the wiring structure bonding copper layer; The first metal layer includes a plurality of second dielectric layers between the first metal layers; a third dielectric layer is located above the circuit structure; and the third dielectric layer and the first metal of the circuit Above the line, the first metal line contacts a first area of the line structure, and the first area is connected via a first opening in the third dielectric layer, the first metal line includes a second a metal layer and a third metal layer above the second metal layer, without any dielectric layer between the first metal layer and the third metal layer; a second metal line located in the third dielectric layer And above the circuit structure, the second metal line contacts a second area of the line structure, and the second area is connected via a second opening in the third dielectric layer, the second gold The circuit includes a fourth metal layer and a fifth metal layer above the fourth metal layer, and the dielectric layer 143044-1000331.doc 1353652 is not interposed between the fourth metal layer and the fifth metal layer. Located above the first metal line, the second metal line, and the third dielectric layer, the insulating layer contacts sidewalls of the third metal layer and sidewalls of the fifth metal layer, the insulating layer includes a nitride layer; And a third metal line over the insulating layer, the first metal line and the second metal line, the third metal line connecting the first metal line via a third opening in the insulating layer, and contacting a surface area of the first metal line connecting the second metal line via a fourth opening in the insulating layer and contacting a surface area of the second metal line, the first metal line The first metal line is connected via the third metal line. 2. The wafer of claim 1, wherein the semiconductor substrate is a stone substrate. 3. The wafer of claim 1, further comprising at least one metal oxide semiconductor (M?s) element in or on the semiconductor substrate. 4. The wafer of claim 2, wherein the second metal layer is only under the second metal layer, and the fourth metal layer is only under the fifth metal layer. 5, such as the scope of patent application! The wafer of claim 7, wherein the circuit structure further comprises a plurality of metal plugs connecting the first metal layers. 6. The wafer of claim i, wherein the second dielectric layer comprises a material having a dielectric constant value (k) between 5 and 3. The wafer of claim 2, wherein the material of the second dielectric layer comprises an oxonium compound, a nitrogen hydrazine compound or a oxynitride compound. The wafer of claim 1, wherein the first metal layer has a thickness of less than 3 microns. 9. The wafer of claim 1, wherein the first metal layers further comprise a plurality of barrier layers under the electro-mineralized copper layers. 1. The wafer of claim 9, wherein the barrier layers are selected from the group consisting of a button, tantalum nitride or titanium nitride. 11. The wafer of claim 1, wherein the third dielectric layer comprises a layer of a ruthenium compound or a layer of a ruthenium oxynitride compound. 12. The wafer of claim 2, wherein the first metal line further contacts a third region of the line structure and the third portion is connected via a fifth opening in the third dielectric layer a region, the first region being connected to the third region via the first metal line. The wafer of claim 2, wherein the thickness of the second metal layer is between 0.03 micrometers and 〇.5 micrometers, and the thickness of the fourth metal layer is between 0.03 micrometers and 〇. Between .5 microns. 14. The wafer of claim 2, wherein the material of the second metal layer and the fourth metal layer comprises titanium, titanium tantalum alloy, nitride, or a group. 15. The wafer of claim 3, wherein the third metal layer has a haze system between 5 microns and 25 microns, and the thickness of the fifth metal layer 143044-1000331.doc 1353652 is Between 5 microns and 25 microns. The wafer of claim 1, wherein the third metal layer comprises a copper layer, a nickel layer or a gold layer. 17. The wafer of claim 1, wherein the fifth metal layer comprises a plated metal layer. 18. The wafer of claim 1, wherein the first metal line and the second metal line contact an upper surface of the third dielectric layer. 19. The wafer of claim 1, wherein the insulating layer further comprises an oxonium compound layer. 20. The wafer of claim 1, wherein the nitride layer is a layer of a ruthenium nitride compound. 21. The wafer of claim 1, further comprising a polymer layer between the insulating layer and the third metal line. 22, such as the scope of patent application! The wafer of the item further includes a polymer layer over the second metal line. 23. The wafer of claim 1 further comprising a polymer layer on the insulating layer and between the first metal line and the second metal line. 24. The wafer of claim 1, wherein the third opening has a maximum transverse dimension of between 2 microns and 30 microns, and the fourth opening has a maximum transverse dimension of between 2 microns and Between 30 microns. 25. The wafer of claim 3, wherein the third metal -4- 143044-1000331.doc 26 circuit comprises a sixth metal layer, a sub-layer on the sixth metal layer, and a seventh metal layer on the seed layer, the metal layer and the seed layer being located only below the seventh metal layer, the seventh metal layer having a thickness between 2 microns and 3 microns. The wafer of claim 25, wherein the material of the sixth metal layer comprises titanium, titanium nitride, titanium tungsten alloy, tantalum, nitride, or copper alloy. 27, 28, 29, 30, 31, 32, 33. The wafer of claim 25, wherein the material of the seed layer comprises copper. The wafer of claim 25, wherein the seventh metal layer comprises a copper layer, a gold layer or a nickel layer. The wafer of claim 1, wherein the third metal line comprises a --key metal layer. The wafer of claim 29, wherein the electrographic metal layer comprises a copper layer having a thickness of between 2 microns and 35 microns. The wafer of claim 1, further comprising a metal bump above the second metal line. The wafer of claim 1, further comprising a tin-containing metal layer above the first metal line. A wafer 'comprising: a semiconductor substrate; a first damascene metal layer over the semiconductor substrate, the first damascene metal layer comprising a copper layer; 143044-1000331.doc 1353652 a second damascene metal layer Located above the semiconductor substrate; a germanium-containing dielectric layer over the semiconductor substrate, the first damascene metal layer and the second damascene metal layer; a first metal line on the germanium-containing dielectric layer and the first Above the damascene metal layer, the first metal line contacts the &quot;surface area of the first damascene metal layer, and the first damascene metal layer is connected via a first opening in the shatter-containing dielectric layer, the first The metal line includes a first metal layer and a first metal layer above the first metal layer, the first metal layer is only under the second metal layer, and there is no between the first metal layer and the second metal layer Any dielectric layer; a first metal line over the stone-containing dielectric layer and the second inlaid metal layer, the second metal line contacting the second inlay gold a surface region of the layer and connecting the second damascene metal layer via a second opening in the germanium-containing dielectric layer, the second metal line including a third metal layer and over the third metal layer a fourth metal layer, the third metal layer is only under the fourth metal layer, and there is no dielectric layer between the third metal layer and the fourth metal layer; an insulating layer is located on the first metal line, Above the cut dielectric layer, the insulating layer includes a gold layer; and a third metal line 'is located on the insulating layer, the first metal line 143044-1000331.doc -6 - and the second metal line The third metal line is connected to the first metal line via a third opening in the insulating layer, and contacts a surface area of the first metal line, the third metal line passing through a first layer located in the insulating layer The fourth opening connects the second metal line 'and contacts a surface area of the second metal line'. The first metal line connects the second metal line via the third metal line. 34. The wafer of claim 33, wherein the semiconductor substrate is a broken substrate. 35. The wafer of claim 33, further comprising at least one metal oxide semiconductor (MOS) component located in or above the semiconductor substrate. The wafer of claim 33, wherein the insulating layer contacts a sidewall of the second metal layer and a sidewall of the fourth metal layer. 37. The wafer of claim 33, further comprising a plurality of fifth metal layers and a plurality of dielectric layers between the semiconductor substrate and the germanium containing dielectric layer. 38. The wafer of claim 33, wherein the first inlay metal layer further comprises a barrier layer under the copper layer. 39. The wafer of claim 38, wherein the material of the barrier layer comprises a button, tantalum nitride or cobalt nitride. 40. The wafer of claim 33, wherein the electric layer comprises a layer of a ruthenium compound or a layer of a ruthenium oxynitride compound. 41. The wafer of claim 33, further comprising a third damascene metal layer over the semiconductor substrate, the germanium containing dielectric layer being over the third damascene metal layer, the first metal trace Contacting a surface region of the third damascene metal layer, and connecting the third damascene metal layer via a fifth opening in the germanium-containing dielectric layer, the first damascene metal layer connecting the first metal via Three inlaid metal layers. 42. The wafer of claim 33, wherein the thickness of the first metal layer is between 微米3〇 and 〇·5 microns, and the thickness of the third metal layer is between 〇. 〇 3 microns to 〇 · 5 microns. The wafer of claim 33, wherein the material of the first metal layer and the third metal layer comprises titanium, titanium tungsten alloy, nitrogen oxide, or a group. 44. The wafer of claim 33, wherein the genus layer has a thickness between 5 microns and 25 microns and the fourth metal layer has a thickness between 5 microns and 25 microns. 45. The wafer of claim 33, wherein the &quot;&quot;&quot;--------------------------------------------------------------------------------------- a wafer, wherein the fourth metal layer comprises a layer of electricity copper. 47. The wafer of claim 33, wherein the genus line and the second metal line are in contact with the bismuth-containing dielectric layer 143044-1000331.doc 48, as in claim 33 The wafer, wherein the insulating layer further comprises a layer of an oxygen compound. 49. The wafer of claim 33, wherein the nitride layer is a gas-compounding compound layer. 50. The wafer of claim 33, further comprising a polymer layer between the insulating layer and the third metal line. 51. The wafer of claim 33, further comprising a polymer layer over the third metal line. 52. The wafer of claim 33, further comprising a polymer layer on the insulating layer and between the first metal line and the second metal line. 5. The wafer of claim 3, wherein the third opening has a maximum lateral dimension of between 2 microns and 30 microns, and the fourth opening has a maximum transverse dimension of between 2 microns and Between 3 〇 micron. 54. The wafer of claim 33, wherein the third metal line comprises a fifth metal layer, a sub-layer on the fifth metal layer, and a sixth metal layer on the seed layer. The fifth metal layer and the seed layer are located only under the sixth metal layer, and the sixth metal layer has a thickness of between 2 micrometers and 3 micrometers. 55. The wafer of claim 54, wherein the material of the metal layer comprises titanium, titanium nitride, titanium tungsten alloy, tantalum, nitride, or copper alloy. The wafer of claim 54, wherein the material of the seed layer comprises copper. 57. The wafer of claim 54, wherein the sixth metal layer comprises a copper layer, a gold layer or a recording layer. 58. The wafer of claim 33, wherein the third metal line comprises an electroplated copper layer having a thickness between 2 microns and 35 microns. 59. The wafer of claim 33, further comprising a metal bump above the second metal line. 60. The wafer of claim 33, further comprising a tin-containing metal layer over the third metal line. 10- 143044-1000331.doc
TW96122418A 2006-06-27 2007-06-22 Integrated circuit and method for fabricating the TWI353652B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US80598106P 2006-06-27 2006-06-27

Publications (2)

Publication Number Publication Date
TW200802714A TW200802714A (en) 2008-01-01
TWI353652B true TWI353652B (en) 2011-12-01

Family

ID=44765469

Family Applications (1)

Application Number Title Priority Date Filing Date
TW96122418A TWI353652B (en) 2006-06-27 2007-06-22 Integrated circuit and method for fabricating the

Country Status (1)

Country Link
TW (1) TWI353652B (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI423329B (en) * 2008-12-22 2014-01-11 United Microelectronics Corp Passivation structure and fabricating method thereof
KR102036942B1 (en) * 2012-02-24 2019-10-25 스카이워크스 솔루션즈, 인코포레이티드 Improved structures, devices and methods related to copper interconnects for compound semiconductors
US9893028B2 (en) * 2015-12-28 2018-02-13 Taiwan Semiconductor Manufacturing Company, Ltd. Bond structures and the methods of forming the same

Also Published As

Publication number Publication date
TW200802714A (en) 2008-01-01

Similar Documents

Publication Publication Date Title
US8471388B2 (en) Integrated circuit and method for fabricating the same
US8592977B2 (en) Integrated circuit (IC) chip and method for fabricating the same
TWI330863B (en) Semiconductor chip with coil element over passivation layer
US8723322B2 (en) Method of metal sputtering for integrated circuit metal routing
JP4566325B2 (en) Method for manufacturing a semiconductor device
TWI320219B (en) Method for forming a double embossing structure
US9865555B2 (en) Self-aligned under bump metal
US6426281B1 (en) Method to form bump in bumping technology
US6376353B1 (en) Aluminum and copper bimetallic bond pad scheme for copper damascene interconnects
US7825511B2 (en) Undercut-free BLM process for Pb-free and Pb-reduced C4
US8778792B2 (en) Solder bump connections
JP2007500445A (en) Method of forming a conductive structure including a titanium-tungsten base layer and related structures
JP2007500445A5 (en)
TW201133744A (en) Integrated circuit device and packaging assembly
KR100720531B1 (en) Metal line of semiconductor device and method for forming the same
WO1995031829A1 (en) Semiconductor fabrication with contact processing for wrap-around flange interface
TW200913103A (en) Chip assembly
TW200830503A (en) A metallization layer stack without a terminal aluminum metal layer
US6448171B1 (en) Microelectronic fabrication having formed therein terminal electrode structure providing enhanced passivation and enhanced bondability
TW200818355A (en) Methods of forming solder connections and structure thereof
JP2004273591A (en) Semiconductor device and its fabricating process
TWI353652B (en) Integrated circuit and method for fabricating the
CN102386160B (en) The manufacture method of semiconductor device and semiconductor device
TWI813935B (en) Bump structure and method of making the same
US20030164552A1 (en) Under-ball metallic layer

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees