TWI745213B - Semiconductor package structure and manufacturing method thereof - Google Patents

Semiconductor package structure and manufacturing method thereof Download PDF

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TWI745213B
TWI745213B TW110100412A TW110100412A TWI745213B TW I745213 B TWI745213 B TW I745213B TW 110100412 A TW110100412 A TW 110100412A TW 110100412 A TW110100412 A TW 110100412A TW I745213 B TWI745213 B TW I745213B
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pins
lead frame
packaging
pin
conductive material
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TW202228253A (en
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周世文
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南茂科技股份有限公司
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Priority to CN202110251441.9A priority patent/CN114725030A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/49—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions wire-like arrangements or pins or rods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49544—Deformation absorbing parts in the lead frame plane, e.g. meanderline shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

A semiconductor package structure includes a leadframe, a chip, a molding compound and a conductive material layer. The leadframe includes a die pad and a plurality of leads. Each of the leads has a top surface, a first bottom surface, an inner end and an outer end. The inner end faces the die pad, and the outer end has a recess at the first bottom surface, so that the outer end connects the top surface and the first bottom surface with a plane sidewall and an arc-shaped recess surface. The chip is disposed on the die pad and electrically connected to the leads. The molding compound covers the leadframe and the chip. The molding compound has a lower surface and a side surface. The lower surface exposes and is flush with the first bottom surface of each of the leads. The side surface is flush with the plane sidewall of each of the leads and exposes the arc-shaped recess surface. The conductive material layer is disposed on the first bottom surface and the arc-shaped cavity surface of each of the leads.

Description

半導體封裝結構及其製造方法Semiconductor packaging structure and manufacturing method thereof

本發明是有關於一種半導體封裝結構，且特別是有關於一種半導體封裝結構及其製造方法。The present invention relates to a semiconductor packaging structure, and more particularly to a semiconductor packaging structure and a manufacturing method thereof.

近年來，為求實現小型化的封裝，具有較小封裝面積的兩面扁平無引腳(Dual Flat No-lead, DFN)封裝結構以及四面扁平無引腳(Quad Flat No-lead, QFN)封裝結構儼然成為當前封裝製程中的主流。由於兩面扁平無引腳以及四面扁平無引腳的封裝具有較小的封裝體積及優越的散熱性、品質穩定性及電性功能，現已被廣泛地應用於各種不同型式的封裝結構。In recent years, in order to achieve a miniaturized package, a dual flat no-lead (DFN) package structure with a small package area and a quad flat no-lead (QFN) package structure It has become the mainstream in the current packaging process. Since the two-sided flat no-lead and four-sided flat no-lead packages have a smaller package volume, superior heat dissipation, quality stability, and electrical functions, they have been widely used in various types of package structures.

一般來說，兩面扁平無引腳封裝以及四面扁平無引腳封裝僅透過引腳外露的底面作為對外電性連接點。如此情況下，有限的可潤濕面積常無法提供封裝結構與外部元件(例如印刷電路板)足夠的接著強度，進而導致電性異常或失效的問題。因此，將引腳的側壁露出並形成階梯狀結構的可濕潤側翼(Wettable Flank)的技術開始被應用，以增加引腳的可潤濕面積、提升封裝結構電性連接至印刷電路板的接著強度。然而，上述階梯狀的可濕潤側翼仍然受限於其外露於封裝結構的面積，而無法大幅提高引腳電性連接至印刷電路板的接著強度。Generally speaking, the two-sided flat no-lead package and the four-sided flat no-lead package only use the exposed bottom surface of the pin as an external electrical connection point. In this case, the limited wettable area often fails to provide sufficient bonding strength between the package structure and external components (such as printed circuit boards), resulting in electrical abnormalities or failures. Therefore, the technology of exposing the sidewalls of the pins and forming a stepped structure of wettable flanks (Wettable Flank) has begun to be applied to increase the wettable area of the pins and improve the bonding strength of the package structure electrically connected to the printed circuit board. . However, the above-mentioned stepped wettable side wings are still limited by the area exposed to the package structure, and cannot greatly improve the bonding strength of the lead electrically connected to the printed circuit board.

本發明提供一種半導體封裝結構及其製造方法，其引腳具有較佳的接著強度。The invention provides a semiconductor packaging structure and a manufacturing method thereof, the pins of which have better bonding strength.

本發明的半導體封裝結構，包括一導線架、一晶片、一封裝膠體以及一導電材料層。導線架包括一承載座及環繞承載座的多個引腳。各引腳具有彼此相對的一頂面與一第一底面、一內側端及一外側端。內側端面向承載座，而外側端於第一底面處具有一凹穴，使外側端以一平面側壁與一弧狀凹穴表面連接頂面與第一底面。晶片配置於承載座上，並電性連接引腳。封裝膠體覆蓋導線架及晶片。封裝膠體具有一下表面與一側表面。下表面暴露出並切齊於各引腳的第一底面，而側表面切齊於各引腳的平面側壁且暴露出弧狀凹穴表面。導電材料層配置於各引腳的第一底面上以及弧狀凹穴表面上。The semiconductor packaging structure of the present invention includes a lead frame, a chip, a packaging compound, and a conductive material layer. The lead frame includes a bearing seat and a plurality of pins surrounding the bearing seat. Each pin has a top surface, a first bottom surface, an inner end and an outer end opposite to each other. The inner end faces the bearing seat, and the outer end has a recess at the first bottom surface, so that the outer end connects the top surface and the first bottom surface with a flat side wall and an arc-shaped recess surface. The chip is arranged on the carrier and electrically connected to the pins. The packaging glue covers the lead frame and the chip. The packaging gel has a bottom surface and a side surface. The bottom surface is exposed and cut to the first bottom surface of each pin, and the side surface is cut to the plane sidewall of each pin and exposes the arc-shaped cavity surface. The conductive material layer is arranged on the first bottom surface of each pin and on the surface of the arc-shaped cavity.

在本發明一實施例中，上述的弧狀凹穴表面為一粗糙面。In an embodiment of the present invention, the surface of the above-mentioned arc-shaped cavity is a rough surface.

在本發明一實施例中，上述各引腳的內側端於第一底面處具有一凹陷，使內側端以一第一側壁、一第二底面與一第二側壁連接頂面與第一底面。封裝膠體填滿凹陷。In an embodiment of the present invention, the inner end of each pin has a recess at the first bottom surface, so that the inner end connects the top surface and the first bottom surface with a first side wall, a second bottom surface, and a second side wall. The encapsulation gel fills up the recess.

在本發明一實施例中，上述的導電材料層的材質包括無鉛銲料。In an embodiment of the present invention, the material of the aforementioned conductive material layer includes lead-free solder.

本發明的半導體封裝結構的製作方法，其包括以下步驟。提供一封裝半成品。封裝半成品包括一導線架條、多個晶片以及封裝膠體。導線架條具有多個導線架單元及連接導線架單元的多個連接條。各導線架單元包括一承載座及環繞承載座的多個引腳。各引腳的外側端連接至相鄰的連接條的其一。相鄰兩導線架單元的引腳兩兩相對配置並於對應連接的連接條的其一上形成多個連接部。連接部的底部具有凹槽。晶片分別配置於導線架單元的承載座上且電性連接引腳。封裝膠體覆蓋導線架條與晶片，其中封裝膠體填滿連接部的凹槽，且封裝膠體的下表面暴露出並切齊於各引腳的第一底面。對封裝半成品進行蝕刻程序，而於各引腳的第一底面鄰接凹槽的部分形成凹穴。各凹槽中的封裝膠體隔開兩相對配置的引腳的凹穴，且凹穴具有弧狀凹穴表面。移除凹槽中的封裝膠體，而連通兩相對配置的引腳的凹穴，且暴露出連接部的一內表面。形成導電材料層於引腳的第一底面以及弧狀凹穴表面上。進行單分程序，以切割封裝膠體及連接部，而形成各自獨立的半導體封裝結構。半導體封裝結構包括具有承載座及環繞承載座的引腳的導線架、晶片、封裝膠體以及導電材料層。引腳具有彼此相對的頂面及第一底面、內側端及外側端。內側端面向承載座，而外側端於第一底面處具有凹穴，使外側端以平面側壁與覆蓋有導電材料層的弧狀凹穴表面連接頂面與覆蓋有導電材料層的第一底面。封裝膠體的側表面切齊於各引腳的平面側壁且暴露出弧狀凹穴表面。The manufacturing method of the semiconductor package structure of the present invention includes the following steps. Provide a package of semi-finished products. The packaging semi-finished product includes a lead frame bar, multiple chips and packaging glue. The lead frame bar has a plurality of lead frame units and a plurality of connecting bars connected to the lead frame units. Each lead frame unit includes a bearing seat and a plurality of pins surrounding the bearing seat. The outer end of each pin is connected to one of the adjacent connecting bars. The pins of two adjacent lead frame units are arranged opposite to each other, and a plurality of connecting parts are formed on one of the corresponding connecting bars. The bottom of the connecting part has a groove. The chips are respectively arranged on the supporting seat of the lead frame unit and electrically connected to the pins. The packaging glue covers the lead frame bar and the chip, wherein the packaging glue fills the grooves of the connecting portion, and the lower surface of the packaging glue is exposed and cut to the first bottom surface of each pin. An etching process is performed on the package semi-finished product, and a cavity is formed in the portion of the first bottom surface of each pin adjacent to the groove. The packaging glue in each groove separates the cavities of the two oppositely arranged pins, and the cavities have an arc-shaped cavity surface. The packaging glue in the groove is removed, and the cavities of the two oppositely arranged pins are connected, and an inner surface of the connecting portion is exposed. A conductive material layer is formed on the first bottom surface of the pin and the surface of the arc-shaped cavity. Perform a single-dividing process to cut the packaging gel and the connecting parts to form separate semiconductor packaging structures. The semiconductor packaging structure includes a lead frame with a bearing seat and pins surrounding the bearing seat, a chip, a packaging glue, and a conductive material layer. The pin has a top surface, a first bottom surface, an inner end and an outer end opposite to each other. The inner end faces the bearing seat, and the outer end has a recess at the first bottom surface, so that the outer end connects the top surface and the first bottom surface covered with the conductive material layer with a flat sidewall and the arc-shaped recess surface covered with the conductive material layer. The side surface of the encapsulant is aligned with the planar sidewall of each pin and exposes the surface of the arc-shaped cavity.

在本發明一實施例中，上述對封裝半成品進行蝕刻程序的步驟，包括提供一遮罩層，以覆蓋引腳的第一底面的局部；以及以遮罩層作為一蝕刻罩幕，以於各引腳的第一底面形成凹穴。In an embodiment of the present invention, the step of performing the etching process on the semi-finished package includes providing a mask layer to cover a part of the first bottom surface of the pin; and using the mask layer as an etching mask for each The first bottom surface of the pin forms a cavity.

在本發明一實施例中，上述移除凹槽中的封裝膠體之前，移除遮罩層，以暴露出引腳的第一底面。In an embodiment of the present invention, the mask layer is removed before removing the packaging compound in the groove to expose the first bottom surface of the lead.

在本發明一實施例中，上述弧狀凹穴表面為一粗糙面。In an embodiment of the present invention, the surface of the arc-shaped cavity is a rough surface.

在本發明的實施例中，上述各引腳的內側端於第一底面處具有凹陷，使內側端以第一側壁、第二底面與第二側壁連接頂面與第一底面。封裝膠體填滿凹陷。In the embodiment of the present invention, the inner end of each of the above-mentioned pins has a recess at the first bottom surface, so that the inner end is connected to the top surface and the first bottom surface by the first side wall, the second bottom surface, and the second side wall. The encapsulation gel fills up the recess.

在本發明一實施例中，上述導電材料層的材質包括無鉛銲料。In an embodiment of the present invention, the material of the conductive material layer includes lead-free solder.

基於上述，透過本發明的半導體封裝結構的製作方法，在引腳的第一底面鄰接連接部的凹槽的部分(即外側端處)進一步形成凹穴，也就是在引腳的外側端的底部形成向內凹入的凹穴，並在後續移除凹槽中的封裝膠體後，使得兩相對配置的引腳的凹穴以及對應的凹槽相互連通而形成一個大凹洞。接著，將導電材料層至少配置於引腳的凹穴所形成的弧狀凹穴表面及第一底面上。因此，藉由前述弧狀凹穴表面的引腳，可提高導電材料層的接著面積，從而增加引腳上的導電材料層外露於半導體封裝結構的面積，進而提升半導體封裝結構電性連接的接著強度。此外，引腳的弧狀凹穴表面可為一粗糙面，粗糙的弧狀凹穴表面可使導電材料層更佳地附著於弧狀凹穴表面上，在單分程序時，亦可減少金屬毛邊的形成，使本發明的半導體封裝結構具有較佳的結構可靠度。Based on the above, through the manufacturing method of the semiconductor package structure of the present invention, a cavity is further formed on the portion (ie, at the outer end) of the first bottom surface of the pin adjacent to the groove of the connecting portion, that is, at the bottom of the outer end of the pin The concave cavity is recessed inward, and after the packaging glue in the groove is subsequently removed, the cavity of the two oppositely arranged pins and the corresponding groove are connected to each other to form a large cavity. Next, the conductive material layer is arranged at least on the surface of the arc-shaped recess formed by the recess of the pin and the first bottom surface. Therefore, with the pins on the surface of the arc-shaped cavity, the bonding area of the conductive material layer can be increased, thereby increasing the area of the conductive material layer on the pins exposed to the semiconductor package structure, thereby improving the electrical connection of the semiconductor package structure. strength. In addition, the surface of the arc-shaped cavity of the lead can be a rough surface, and the rough surface of the arc-shaped cavity can make the conductive material layer better adhere to the surface of the arc-shaped cavity, and it can also reduce the metal in the single process. The formation of burrs enables the semiconductor package structure of the present invention to have better structural reliability.

為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail in conjunction with the accompanying drawings.

以下將參考圖式來全面地描述本發明的例示性實施例，但本發明還可按照多種不同形式來實施，且不應解釋為限於本文所述的實施例。在圖式中，為了清楚起見，各區域、部位及層的大小與厚度可不按實際比例繪製。為了方便理解，下述說明中相同的元件將以相同之符號標示來說明。The exemplary embodiments of the present invention will be fully described below with reference to the drawings, but the present invention may also be implemented in many different forms and should not be construed as being limited to the embodiments described herein. In the drawings, for the sake of clarity, the size and thickness of each region, location, and layer may not be drawn to actual scale. To facilitate understanding, the same elements in the following description will be described with the same symbols.

圖1A至圖1G是依照本發明的一實施例的半導體封裝結構的製作方法的剖面示意圖。關於本實施例的半導體封裝結構的製作方法，首先，請參考圖1A，提供一封裝半成品10，其中封裝半成品10包括一導線架條LF、多個晶片200以及一封裝膠體300。導線架條LF具有多個導線架單元100及連接導線架單元100的多個連接條500。導線架條LF的導線架單元100例如是呈矩陣式排列並以連接條500分隔開，且每一導線架單元100包括一承載座110及環繞承載座110的多個引腳120。每一引腳120的一外側端124連接至相鄰的連接條500，且相鄰兩導線架單元100的引腳120兩兩相對配置並於對應連接的連接條500上形成多個連接部510。1A to 1G are schematic cross-sectional views of a manufacturing method of a semiconductor package structure according to an embodiment of the present invention. Regarding the manufacturing method of the semiconductor package structure of this embodiment, firstly, referring to FIG. 1A, a package semi-finished product 10 is provided. The package semi-finished product 10 includes a lead frame bar LF, a plurality of chips 200 and a packaging glue 300. The lead frame bar LF has a plurality of lead frame units 100 and a plurality of connecting bars 500 connected to the lead frame units 100. The lead frame units 100 of the lead frame bars LF are, for example, arranged in a matrix and separated by connecting bars 500, and each lead frame unit 100 includes a supporting base 110 and a plurality of pins 120 surrounding the supporting base 110. An outer end 124 of each pin 120 is connected to an adjacent connecting bar 500, and the pins 120 of two adjacent lead frame units 100 are arranged opposite to each other and a plurality of connecting portions 510 are formed on the corresponding connecting bar 500. .

接著，請同時參考圖1A與圖1B，各連接部510的底部具有凹槽G，在本實施例中，各連接部510的凹槽G相互連通而形成沿著連接條500延伸的單個長條型凹槽。然而，在其他未繪示的實施例中，各連接部510的凹槽G可為個別的凹槽，使得連接條500上形成多個彼此分離的凹槽，本發明對於凹槽的形式和數量不加以限制。再者，本實施例的晶片200分別配置於導線架單元100的承載座110上且電性連接引腳120。晶片200與承載座110之間可以用接著劑220固定，其中接著劑220例如為常用的環氧樹脂、銀膠、黏晶膠膜(DAF)等。此處，晶片200是以銲線210電性連接引腳120，但不以此電性連接的方式為限。銲線210的材質例如是金、銅或其他合適之導電材料，於此並不加以限制。Next, referring to FIGS. 1A and 1B at the same time, the bottom of each connecting portion 510 has a groove G. In this embodiment, the grooves G of each connecting portion 510 communicate with each other to form a single strip extending along the connecting bar 500 Type groove. However, in other unillustrated embodiments, the groove G of each connecting portion 510 may be an individual groove, so that a plurality of grooves separated from each other are formed on the connecting strip 500. The present invention is concerned with the form and number of grooves. No restrictions. Furthermore, the chip 200 of this embodiment is respectively disposed on the carrier 110 of the lead frame unit 100 and is electrically connected to the pins 120. The chip 200 and the carrier 110 can be fixed with an adhesive 220, where the adhesive 220 is, for example, commonly used epoxy resin, silver glue, die-bonding film (DAF), and the like. Here, the chip 200 is electrically connected to the pin 120 by the bonding wire 210, but is not limited to the manner of electrical connection. The material of the bonding wire 210 is, for example, gold, copper or other suitable conductive materials, which is not limited herein.

接著，請參考圖1A與圖1B，封裝膠體300覆蓋導線架條LF與晶片200。在本實施例中，各引腳120的內側端122於第一底面120b處具有凹陷128，其中封裝膠體300填滿引腳120的凹陷128以及連接部510的凹槽G，且封裝膠體300的下表面300b暴露出並切齊於引腳120的第一底面120b。封裝膠體300的材質例如為環氧樹脂或其他合適之高分子材料，其可避免水氣或污染物的侵入。藉由封裝膠體300填滿引腳120的凹陷128可將引腳120鎖固於封裝膠體300內，避免引腳120自封裝膠體300中脫落。此外，在本實施例中，封裝膠體300的下表面300b亦暴露出承載座110的底面110b，然而，在其他未繪示的實施例中，承載座110的底面110b可被封裝膠體300所覆蓋而不暴露出。Next, referring to FIG. 1A and FIG. 1B, the packaging compound 300 covers the lead frame bar LF and the chip 200. In this embodiment, the inner end 122 of each pin 120 has a recess 128 at the first bottom surface 120b, wherein the encapsulant 300 fills the recess 128 of the pin 120 and the groove G of the connecting portion 510, and the encapsulant 300 The bottom surface 300b is exposed and is cut in line with the first bottom surface 120b of the pin 120. The material of the encapsulant 300 is, for example, epoxy resin or other suitable polymer materials, which can prevent the intrusion of moisture or pollutants. By filling the recess 128 of the lead 120 with the packaging glue 300, the lead 120 can be locked in the packaging glue 300 to prevent the lead 120 from falling off from the packaging glue 300. In addition, in this embodiment, the lower surface 300b of the encapsulant 300 also exposes the bottom surface 110b of the carrier 110. However, in other embodiments not shown, the bottom surface 110b of the carrier 110 may be covered by the encapsulant 300 Without being exposed.

接著，請參考圖1C，對封裝半成品10進行一蝕刻程序。首先，提供遮罩層M，以覆蓋引腳120的第一底面120b的局部。在本實施例中，遮罩層M亦覆蓋承載座110的底面110b。此處，遮罩層M的材質例如是絕緣光阻材料或金屬材料，其中金屬材料例如金、鈀或其他可供選擇性蝕刻的金屬，可具有較佳的蝕刻選擇性。Next, please refer to FIG. 1C to perform an etching process on the semi-finished package 10. First, a mask layer M is provided to cover a part of the first bottom surface 120b of the pin 120. In this embodiment, the mask layer M also covers the bottom surface 110 b of the supporting base 110. Here, the material of the mask layer M is, for example, an insulating photoresist material or a metal material. The metal material, such as gold, palladium, or other metals that can be selectively etched, may have better etching selectivity.

接著，請同時參考圖1C與圖1D，將整個封裝半成品10置入金屬蝕刻液，例如是銅蝕刻液，以遮罩層M作為蝕刻罩幕，蝕刻引腳120未被遮罩層M所遮蔽的部分，而於引腳120的第一底面120b鄰接凹槽G的部分形成一凹穴C。凹槽G中的封裝膠體300隔開兩相對配置的引腳120的凹穴C，且每一凹穴C具有一弧狀凹穴表面S。此處，弧狀凹穴表面S具體化為一粗糙面，即微觀下如鋸齒狀結構，但不以此為限。Next, referring to FIGS. 1C and 1D at the same time, put the entire package semi-finished product 10 into a metal etching solution, such as a copper etching solution, with the mask layer M as an etching mask, and the etching pins 120 are not covered by the mask layer M A cavity C is formed in the portion of the first bottom surface 120b of the pin 120 adjacent to the groove G. The encapsulant 300 in the groove G separates the cavities C of the two oppositely arranged pins 120, and each cavity C has an arc-shaped cavity surface S. Here, the arc-shaped cavity surface S is embodied as a rough surface, that is, a jagged structure in a microscopic view, but it is not limited to this.

接著，請同時參考圖1D與圖1E，移除遮罩層M，以暴露出引腳120的第一底面120b。緊接著，移除凹槽G中的封裝膠體300，而連通兩相對配置的引腳120的凹穴C，且暴露出連接部510的一內表面512。此處，移除凹槽G中的封裝膠體300的方式，較佳地，是以雷射法燒蝕，但不以此為限。接著，形成一導電材料層400於引腳120的第一底面120b與弧狀凹穴表面S上。進一步來說，導電材料層400可選擇性地形成在連接部510的內表面512及承載座110的底面110b上。此處，導電材料層400的形成方式例如是電鍍或印刷等，而導電材料層400的材質例如是無鉛銲料，但不以此為限。至此，藉由蝕刻引腳120，而在引腳120的第一底面120b鄰接凹槽G的部分(即外側端124處)形成凹穴C，也就是在引腳120的外側端124的底部形成向內凹入的凹穴C，並在後續移除凹槽G中的封裝膠體300後，使得兩相對配置的引腳120的凹穴C以及對應的凹槽G相互連通而形成一個大凹洞。接著，導電材料層400可形成於大凹洞的表面上，如此配置下，可增加導電材料層400與引腳120的接著面積。除此之外，粗糙的弧狀凹穴表面S可使導電材料層400更佳地附著於弧狀凹穴表面S上，且在後續的單分程序時，粗糙的弧狀凹穴表面S也可減少金屬毛邊(burr)的產生。Next, referring to FIG. 1D and FIG. 1E at the same time, the mask layer M is removed to expose the first bottom surface 120b of the pin 120. Then, the encapsulant 300 in the groove G is removed, and the cavities C of the two oppositely arranged pins 120 are connected, and an inner surface 512 of the connecting portion 510 is exposed. Here, the way of removing the encapsulant 300 in the groove G is preferably by laser ablation, but it is not limited to this. Next, a conductive material layer 400 is formed on the first bottom surface 120b of the pin 120 and the surface S of the arc-shaped cavity. Furthermore, the conductive material layer 400 can be selectively formed on the inner surface 512 of the connecting portion 510 and the bottom surface 110b of the supporting base 110. Here, the formation method of the conductive material layer 400 is, for example, electroplating or printing, and the material of the conductive material layer 400 is, for example, lead-free solder, but it is not limited thereto. So far, by etching the pin 120, a cavity C is formed in the portion of the first bottom surface 120b of the pin 120 adjacent to the groove G (ie at the outer end 124), that is, at the bottom of the outer end 124 of the pin 120 Inwardly recessed cavity C, and after the subsequent removal of the encapsulant 300 in the groove G, the cavity C of the two oppositely arranged pins 120 and the corresponding groove G are connected to each other to form a large cavity . Next, the conductive material layer 400 can be formed on the surface of the large cavity. With this configuration, the bonding area between the conductive material layer 400 and the pin 120 can be increased. In addition, the rough arc-shaped cavity surface S can make the conductive material layer 400 better adhere to the arc-shaped cavity surface S, and in the subsequent single-dividing process, the rough arc-shaped cavity surface S is also Can reduce the generation of metal burr.

之後，請同時參考圖1F與圖1G，進行一單分程序，以切割封裝膠體300及連接部510，以使封裝膠體300的一側表面300c切齊於各引腳120的平面側壁124c且暴露出外側端124的弧狀凹穴表面S上的導電材料層400，而形成各自獨立的半導體封裝結構（於圖1G中示意地繪示一個半導體封裝結構20）。至此，已完成半導體封裝結構20的製作。After that, please refer to FIG. 1F and FIG. 1G at the same time to perform a single division process to cut the packaging glue 300 and the connecting portion 510 so that one side surface 300c of the packaging glue 300 is aligned with the planar sidewall 124c of each pin 120 and is exposed The conductive material layer 400 on the surface S of the arc-shaped recess of the outer end 124 is formed to form an independent semiconductor package structure (a semiconductor package structure 20 is schematically shown in FIG. 1G). So far, the fabrication of the semiconductor package structure 20 has been completed.

在結構上，請再參考圖1G，本實施例的半導體封裝結構20包括導線架100’、晶片200、封裝膠體300及導電材料層400。導線架100’包括承載座110及環繞承載座110的引腳120。每一引腳120具有彼此相對的頂面120a與第一底面120b、內側端122及外側端124。內側端122面向承載座110，且每一引腳120的內側端122於第一底面120b處具有凹陷128，使內側端122以第一側壁122a、第二底面122b與第二側壁122c連接頂面120a與第一底面120b。外側端124於第一底面120b處具有凹穴C，使外側端124以平面側壁124c與弧狀凹穴表面S連接頂面120a與第一底面120b。晶片200配置於承載座110上並以例如是銲線210電性連接引腳120，其中晶片200可透過接著劑220而固定於承載座110上。封裝膠體300覆蓋導線架100’及晶片200，且填滿凹陷128。封裝膠體300具有下表面300b與側表面300c，其中下表面300b暴露出並切齊於引腳120的第一底面120b，而側表面300c切齊於引腳120的平面側壁124c且暴露出弧狀凹穴表面S。導電材料層400配置於每一引腳120的第一底面120b上以及弧狀凹穴表面S上。相較於習知具階梯狀結構的引腳，本實施例具弧狀凹穴表面S的引腳120，能夠提高與導電材料層400的接著面積(即增加引腳120的可濕潤面積)，從而提升半導體封裝結構20與外部端子的結合良率。In terms of structure, please refer to FIG. 1G again. The semiconductor packaging structure 20 of this embodiment includes a lead frame 100', a chip 200, a packaging compound 300, and a conductive material layer 400. The lead frame 100' includes a supporting base 110 and pins 120 surrounding the supporting base 110. Each pin 120 has a top surface 120 a and a first bottom surface 120 b, an inner end 122 and an outer end 124 opposite to each other. The inner end 122 faces the carrier 110, and the inner end 122 of each pin 120 has a recess 128 at the first bottom surface 120b, so that the inner end 122 is connected to the top surface by the first side wall 122a, the second bottom surface 122b, and the second side wall 122c 120a and the first bottom surface 120b. The outer end 124 has a cavity C at the first bottom surface 120b, so that the outer end 124 connects the top surface 120a and the first bottom surface 120b with the flat sidewall 124c and the arc-shaped cavity surface S. The chip 200 is disposed on the carrier 110 and is electrically connected to the pins 120 by, for example, bonding wires 210, wherein the chip 200 can be fixed on the carrier 110 through the adhesive 220. The encapsulant 300 covers the lead frame 100' and the chip 200, and fills the recess 128. The encapsulant 300 has a bottom surface 300b and a side surface 300c. The bottom surface 300b is exposed and cut to the first bottom surface 120b of the lead 120, and the side surface 300c is cut to the flat sidewall 124c of the lead 120 and exposes an arc shape. The surface S of the cavity. The conductive material layer 400 is disposed on the first bottom surface 120b of each pin 120 and on the surface S of the arc-shaped cavity. Compared with the conventional lead with a stepped structure, the lead 120 with the arc-shaped concave surface S of this embodiment can increase the area of contact with the conductive material layer 400 (that is, increase the wettable area of the lead 120). Thereby, the bonding yield of the semiconductor package structure 20 and the external terminals is improved.

綜上所述，透過本發明的半導體封裝結構的製作方法，在引腳的第一底面鄰接連接部的凹槽的部分(即外側端處)進一步形成凹穴，也就是在引腳的外側端的底部形成向內凹入的凹穴，並在後續移除凹槽中的封裝膠體後，使得兩相對配置的引腳的凹穴以及對應的凹槽相互連通而形成一個大凹洞。接著，將導電材料層至少配置於引腳的凹穴所形成的弧狀凹穴表面及第一底面上。因此，藉由前述具弧狀凹穴表面的引腳，可提高導電材料層的接著面積，從而增加引腳上的導電材料層外露於半導體封裝結構的面積，進而提升半導體封裝結構電性連接的接著強度。此外，引腳的弧狀凹穴表面可為一粗糙面，粗糙的弧狀凹穴表面可使導電材料層更佳地附著於弧狀凹穴表面上，且在單分程序時，亦可減少金屬毛邊的形成，使本發明的半導體封裝結構具有較佳的結構可靠度。In summary, through the manufacturing method of the semiconductor package structure of the present invention, a cavity is further formed on the first bottom surface of the pin adjacent to the groove of the connecting portion (that is, at the outer end), that is, at the outer end of the pin. An inwardly recessed cavity is formed at the bottom, and after the packaging glue in the groove is subsequently removed, the cavity of the two oppositely arranged pins and the corresponding groove are connected to each other to form a large cavity. Then, the conductive material layer is arranged at least on the surface of the arc-shaped recess formed by the recess of the pin and the first bottom surface. Therefore, with the aforementioned pins with arc-shaped concave surfaces, the bonding area of the conductive material layer can be increased, thereby increasing the area of the conductive material layer on the pins exposed to the semiconductor package structure, thereby improving the electrical connection of the semiconductor package structure Then intensity. In addition, the surface of the arc-shaped cavity of the lead can be a rough surface. The rough surface of the arc-shaped cavity can make the conductive material layer better adhere to the surface of the arc-shaped cavity. The formation of metal burrs enables the semiconductor package structure of the present invention to have better structural reliability.

雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the relevant technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The protection scope of the present invention shall be subject to those defined by the attached patent application scope.

10:封裝半成品 20:半導體封裝結構 100:導線架單元 100’:導線架 110:承載座 110b:底面 120:引腳 120a:頂面 120b:第一底面 122:內側端 122a:第一側壁 122b:第二底面 122c:第二側壁 124:外側端 124c:平面側壁 128:凹陷 200:晶片 210:銲線 220:接著劑 300:封裝膠體 300b:下表面 300c:側表面 400:導電材料層 500:連接條 510:連接部 512:內表面 LF:導線架條 C:凹穴 G:凹槽 M:遮罩層 S:弧狀凹穴表面 10: Packaging semi-finished products 20: Semiconductor package structure 100: Lead frame unit 100’: Lead frame 110: bearing seat 110b: bottom surface 120: pin 120a: top surface 120b: the first bottom surface 122: inside end 122a: first side wall 122b: second bottom surface 122c: second side wall 124: Outer end 124c: flat side wall 128: sunken 200: chip 210: Welding wire 220: Adhesive 300: Encapsulation colloid 300b: lower surface 300c: side surface 400: Conductive material layer 500: connecting bar 510: Connecting part 512: inner surface LF: Lead frame strip C: cavities G: Groove M: Mask layer S: curved concave surface

圖1A至圖1G是依照本發明的一實施例的半導體封裝結構的製作方法的剖面示意圖。1A to 1G are schematic cross-sectional views of a manufacturing method of a semiconductor package structure according to an embodiment of the present invention.

20:半導體封裝結構 20: Semiconductor package structure

100’:導線架 100’: Lead frame

110:承載座 110: bearing seat

120:引腳 120: pin

120a:頂面 120a: top surface

120b:第一底面 120b: the first bottom surface

122:內側端 122: inside end

122a:第一側壁 122a: first side wall

122b:第二底面 122b: second bottom surface

122c:第二側壁 122c: second side wall

124:外側端 124: Outer end

124c:平面側壁 124c: flat side wall

128:凹陷 128: sunken

200:晶片 200: chip

210:銲線 210: Welding wire

220:接著劑 220: Adhesive

300:封裝膠體 300: Encapsulation colloid

300b:下表面 300b: lower surface

300c:側表面 300c: side surface

400:導電材料層 400: Conductive material layer

C:凹穴 C: cavities

S:弧狀凹穴表面 S: curved concave surface

Claims (6)

一種半導體封裝結構的製作方法，包括：提供一封裝半成品，該封裝半成品包括一導線架條、多個晶片以及一封裝膠體，該導線架條具有多個導線架單元及連接該些導線架單元的多個連接條，各該導線架單元包括一承載座及環繞該承載座的多個引腳，各該引腳的一外側端連接至相鄰的該些連接條的其一，相鄰兩該些導線架單元的該些引腳兩兩相對配置並於對應連接的該些連接條的其一上形成多個連接部，各該連接部的底部具有凹槽，該些晶片分別配置於該些導線架單元的該些承載座上且電性連接該些引腳，該封裝膠體覆蓋該導線架條與該些晶片，其中該封裝膠體填滿該些連接部的該些凹槽，且該封裝膠體的一下表面暴露出並切齊於各該引腳的一第一底面；對該封裝半成品進行一蝕刻程序，而於各該引腳的該第一底面鄰接該凹槽的部分形成一凹穴，其中各該凹槽中的該封裝膠體隔開兩相對配置的該些引腳的該些凹穴，且各該凹穴具有一弧狀凹穴表面；移除該些凹槽中的該封裝膠體，而連通兩相對配置的該些引腳的該些凹穴，且暴露出該些連接部的一內表面；形成一導電材料層於該些引腳的該些第一底面以及該些弧狀凹穴表面上；進行一單分程序，以切割該封裝膠體及該些連接部，而形成各自獨立的該些半導體封裝結構，其中各該半導體封裝結構包括 具有該承載座及環繞該承載座的該些引腳的一導線架、各該晶片、該封裝膠體以及該導電材料層，各該引腳具有彼此相對的一頂面及該第一底面、一內側端及該外側端，該內側端面向該承載座，而該外側端於該第一底面處具有該凹穴，使該外側端以一平面側壁與覆蓋有該導電材料層的該弧狀凹穴表面連接該頂面與覆蓋有該導電材料層的該第一底面，該封裝膠體的一側表面切齊於各該引腳的該平面側壁且暴露出該弧狀凹穴表面。 A method for manufacturing a semiconductor packaging structure includes: providing a semi-finished product package, the semi-finished product package including a lead frame bar, a plurality of chips, and a packaging gel, the lead frame bar having a plurality of lead frame units and connecting the lead frame units A plurality of connecting bars, each of the lead frame unit includes a bearing seat and a plurality of pins surrounding the bearing seat, an outer end of each pin is connected to one of the adjacent connecting bars, and two adjacent ones The pins of the lead frame units are arranged opposite to each other, and a plurality of connecting parts are formed on one of the connecting strips correspondingly connected. The bottom of each connecting part has a groove, and the chips are respectively arranged in the The supporting seats of the lead frame unit are electrically connected to the pins, the packaging glue covers the lead frame bars and the chips, wherein the packaging glue fills the grooves of the connecting parts, and the packaging The lower surface of the colloid is exposed and cut to a first bottom surface of each pin; an etching process is performed on the semi-finished package, and a cavity is formed on the first bottom surface of each pin adjacent to the groove , Wherein the packaging gel in each of the grooves separates the cavities of the two oppositely arranged pins, and each of the cavities has an arc-shaped cavity surface; the package in the grooves is removed Colloid, which connects the cavities of the two oppositely arranged pins, and exposes an inner surface of the connecting portion; forming a conductive material layer on the first bottom surfaces and the arcs of the pins On the surface of the cavities; perform a single-division process to cut the packaging gel and the connecting parts to form the independent semiconductor packaging structures, wherein each semiconductor packaging structure includes A lead frame having the bearing seat and the pins surrounding the bearing seat, each of the chips, the packaging compound, and the conductive material layer, each of the pins having a top surface and the first bottom surface opposite to each other, and The inner end and the outer end, the inner end faces the bearing seat, and the outer end has the recess at the first bottom surface, so that the outer end has a flat side wall and the arc-shaped recess covered with the conductive material layer The surface of the cavity connects the top surface and the first bottom surface covered with the conductive material layer, and one side surface of the encapsulant is in line with the planar side wall of each pin and exposes the arc-shaped cavity surface. 如請求項1所述的半導體封裝結構的製作方法，其中對該封裝半成品進行該蝕刻程序的步驟，包括：提供一遮罩層，以覆蓋各該引腳的該第一底面的局部；以及以該遮罩層作為一蝕刻罩幕，以於各該引腳的該第一底面形成該凹穴。 The method for manufacturing a semiconductor package structure according to claim 1, wherein the step of performing the etching procedure on the package semi-finished product includes: providing a mask layer to cover a part of the first bottom surface of each of the pins; and The mask layer serves as an etching mask to form the cavity on the first bottom surface of each pin. 如請求項2所述的半導體封裝結構的製作方法，其中於移除該些凹槽中的該封裝膠體之前，移除該遮罩層，以暴露出該些引腳的該些第一底面。 The manufacturing method of the semiconductor package structure according to claim 2, wherein the mask layer is removed before removing the package glue in the grooves to expose the first bottom surfaces of the pins. 如請求項1所述的半導體封裝結構的製作方法，其中該弧狀凹穴表面為一粗糙面。 The manufacturing method of the semiconductor package structure according to claim 1, wherein the surface of the arc-shaped cavity is a rough surface. 如請求項1所述的半導體封裝結構的製作方法，其中各該引腳的該內側端於該第一底面處具有一凹陷，使該內側端以一第一側壁、一第二底面與一第二側壁連接該頂面與該第一底面，且該封裝膠體填滿該凹陷。 The method for manufacturing a semiconductor package structure according to claim 1, wherein the inner end of each pin has a recess at the first bottom surface, so that the inner end has a first side wall, a second bottom surface, and a first bottom surface. Two sidewalls connect the top surface and the first bottom surface, and the packaging glue fills the recess. 如請求項1所述的半導體封裝結構的製作方法，其中該導電材料層的材質包括無鉛銲料。 The manufacturing method of the semiconductor package structure according to claim 1, wherein the material of the conductive material layer includes lead-free solder.
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Citations (4)

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TW201324639A (en) * 2006-09-06 2013-06-16 Megica Corp Chip package and method for fabricating the same
TW201923990A (en) * 2017-10-06 2019-06-16 美商微晶片科技公司 Systems and methods for improved adhesion between a leadframe and molding compound in a semiconductor device
TW202036824A (en) * 2019-03-22 2020-10-01 日商大口電材股份有限公司 Lead frame
CN111987002A (en) * 2020-09-04 2020-11-24 长电科技（滁州）有限公司 Package forming method

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201324639A (en) * 2006-09-06 2013-06-16 Megica Corp Chip package and method for fabricating the same
TW201923990A (en) * 2017-10-06 2019-06-16 美商微晶片科技公司 Systems and methods for improved adhesion between a leadframe and molding compound in a semiconductor device
TW202036824A (en) * 2019-03-22 2020-10-01 日商大口電材股份有限公司 Lead frame
CN111987002A (en) * 2020-09-04 2020-11-24 长电科技（滁州）有限公司 Package forming method

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