CN114725030A - Semiconductor package structure and manufacturing method thereof - Google Patents

Semiconductor package structure and manufacturing method thereof Download PDF

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Publication number
CN114725030A
CN114725030A CN202110251441.9A CN202110251441A CN114725030A CN 114725030 A CN114725030 A CN 114725030A CN 202110251441 A CN202110251441 A CN 202110251441A CN 114725030 A CN114725030 A CN 114725030A
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China
Prior art keywords
recess
arc
leads
lead frame
encapsulant
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CN202110251441.9A
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Chinese (zh)
Inventor
周世文
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Chipmos Technologies Inc
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Chipmos Technologies Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/49—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions wire-like arrangements or pins or rods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49544—Deformation absorbing parts in the lead frame plane, e.g. meanderline shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

The invention provides a semiconductor packaging structure and a manufacturing method thereof. The semiconductor packaging structure comprises a lead frame, a chip, a packaging colloid and a conductive material layer. The lead frame comprises a bearing seat and a plurality of pins. Each lead has a top surface, a first bottom surface, an inner end and an outer end. The inner end faces the bearing seat, and the outer end is provided with a recess at the first bottom surface, so that the outer end is connected with the top surface and the first bottom surface through the plane side wall and the surface of the arc-shaped recess. The chip is arranged on the bearing seat and is electrically connected with the pins. The packaging colloid covers the lead frame and the chip. The encapsulant has a lower surface and a side surface. The lower surface is exposed and aligned with the first bottom surfaces of the pins. The side surface is aligned with the plane side wall of the pin and exposes the surface of the arc-shaped recess. The conductive material layer is configured on the first bottom surface of the pin and the surface of the arc-shaped recess. The pins of the semiconductor packaging structure and the manufacturing method thereof have better bonding strength.

Description

Semiconductor package structure and manufacturing method thereof
Technical Field
The present invention relates to semiconductor packages, and particularly to a semiconductor package and a method for fabricating the same.
Background
In recent years, to realize a miniaturized package, a Dual Flat No-lead (DFN) package and a Quad Flat No-lead (QFN) package with a smaller package area are the mainstream of the current packaging process. Since the two-sided flat non-leaded and four-sided flat non-leaded packages have smaller package size and superior heat dissipation, quality stability and electrical performance, they are widely used in various types of package structures.
Generally, the two-sided and four-sided flat non-leaded packages are electrically connected to the outside only through the exposed bottom surfaces of the leads. In such cases, the limited wettable area often fails to provide sufficient adhesion between the package structure and external components (e.g., printed circuit board), thereby causing electrical anomalies or failures. Therefore, a technique of exposing the sidewalls of the leads and forming Wettable wings (Wettable fins) in a stepped structure is being applied to increase the Wettable area of the leads and improve the bonding strength of the package structure electrically connected to the printed circuit board. However, the step-shaped wettable wings are still limited by the area exposed out of the package structure, and the bonding strength of the pins electrically connected to the printed circuit board cannot be greatly improved.
Disclosure of Invention
The invention is directed to a semiconductor package structure and a manufacturing method thereof, wherein the pins have better bonding strength.
According to an embodiment of the present invention, a semiconductor package structure includes a leadframe, a chip, an encapsulant, and a conductive material layer. The lead frame comprises a bearing seat and a plurality of pins surrounding the bearing seat. Each pin is provided with a top surface, a first bottom surface, an inner side end and an outer side end which are opposite to each other. The inner end faces the bearing seat, and the outer end is provided with a recess at the first bottom surface, so that the outer end is connected with the top surface and the first bottom surface through the plane side wall and the surface of the arc-shaped recess. The chip is arranged on the bearing seat and is electrically connected with the pins. The packaging colloid covers the lead frame and the chip. The encapsulant has a lower surface and a side surface. The lower surface is exposed and cut to be aligned with the first bottom surface of each pin, and the side surface is cut to be aligned with the plane side wall of each pin and exposed out of the surface of the arc-shaped recess. The conductive material layer is configured on the first bottom surface of each pin and the surface of the arc-shaped recess.
In the semiconductor package structure according to the embodiment of the invention, the surface of the arc-shaped cavity is a rough surface.
In the semiconductor package structure according to the embodiment of the invention, the inner end of each lead has a recess at the first bottom surface, so that the inner end connects the top surface and the first bottom surface through the first side wall, the second bottom surface and the second side wall. The encapsulant fills the recess.
In the semiconductor package structure according to an embodiment of the invention, a material of the conductive material layer includes a lead-free solder.
According to an embodiment of the invention, a method for manufacturing a semiconductor packaging structure comprises the following steps. And providing a packaging semi-finished product. The semi-finished product of the package comprises a lead frame strip, a plurality of chips and a package colloid. The lead frame strip is provided with a plurality of lead frame units and a plurality of connecting strips for connecting the lead frame units. Each lead frame unit comprises a bearing seat and a plurality of pins surrounding the bearing seat. The outer end of each lead is connected to one of the adjacent connecting bars. The pins of two adjacent lead frame units are arranged in pairs and are opposite to each other, and a plurality of connecting parts are formed on one of the correspondingly connected connecting strips. The bottom of the connecting part is provided with a groove. The chips are respectively arranged on the bearing seats of the lead frame units and are electrically connected with the pins. The packaging colloid covers the lead frame strip and the chip, wherein the packaging colloid fills the groove of the connecting part, and the lower surface of the packaging colloid is exposed and aligned with the first bottom surface of each pin. Etching the semi-finished product to form a recess on the first bottom surface of each lead. The encapsulation body in each groove separates two cavities of pins which are arranged oppositely, and the cavities are provided with arc-shaped cavity surfaces. The packaging colloid in the groove is removed, the cavities of the two pins which are oppositely arranged are communicated, and the inner surface of the connecting part is exposed. Forming a conductive material layer on the first bottom surface of the pin and the surface of the arc-shaped recess. And performing a singulation process to cut the encapsulant and the connecting portion to form independent semiconductor package structures. The semiconductor packaging structure comprises a lead frame with a bearing seat and pins surrounding the bearing seat, a chip, a packaging colloid and a conductive material layer. The leads are provided with top surfaces and first bottom surfaces which are opposite to each other, and inner side ends and outer side ends. The inner end faces the bearing seat, and the outer end has a recess at the first bottom surface, so that the outer end is connected with the top surface and the first bottom surface covered with the conductive material layer through the plane side wall and the arc-shaped recess surface covered with the conductive material layer. The side surface of the packaging colloid is aligned with the plane side wall of each pin and exposes out of the surface of the arc-shaped recess.
In the method for fabricating a semiconductor package structure according to an embodiment of the present invention, the step of performing an etching process on the semi-finished package includes providing a mask layer to cover a portion of the first bottom surface of the lead; and forming a recess on the first bottom surface of each lead by using the mask layer as an etching mask.
In the method for fabricating a semiconductor package structure according to an embodiment of the invention, the mask layer is removed to expose the first bottom surfaces of the leads before the encapsulant in the recess is removed.
In the method for manufacturing a semiconductor package structure according to an embodiment of the present invention, the surface of the arc-shaped recess is a rough surface.
In the method for manufacturing a semiconductor package structure according to an embodiment of the present invention, the inner end of each lead has a recess at the first bottom surface, so that the inner end connects the top surface and the first bottom surface through the first sidewall, the second bottom surface and the second sidewall. The encapsulant fills the recess.
In the method for manufacturing a semiconductor package structure according to an embodiment of the present invention, a material of the conductive material layer includes a lead-free solder.
Based on the above, by the manufacturing method of the semiconductor package structure of the present invention, the recess is further formed at the portion (i.e. the outer side end) of the first bottom surface of the lead adjacent to the groove of the connection portion, that is, the inwardly recessed recess is formed at the bottom of the outer side end of the lead, and after the encapsulant in the groove is subsequently removed, the recesses of the two oppositely disposed leads and the corresponding grooves are communicated with each other to form a large cavity. Then, the conductive material layer is at least arranged on the arc-shaped recess surface formed by the recess of the pin and the first bottom surface. Therefore, the bonding area of the conductive material layer can be increased through the pins on the surface of the arc-shaped recess, so that the area of the conductive material layer on the pins exposed out of the semiconductor packaging structure is increased, and the bonding strength of the electrical connection of the semiconductor packaging structure is further improved. In addition, the surface of the arc-shaped recess of the pin can be a rough surface, the rough surface of the arc-shaped recess can make the conductive material layer better attached to the surface of the arc-shaped recess, and the formation of metal burrs can be reduced during the singulation process, so that the semiconductor packaging structure has better structural reliability.
Drawings
Fig. 1A to fig. 1G are schematic cross-sectional views illustrating a method for fabricating a semiconductor package structure according to an embodiment of the invention.
Description of the reference numerals
10: packaging the semi-finished product;
20: a semiconductor package structure;
100: a lead frame unit;
100': a lead frame;
110: a bearing seat;
110 b: a bottom surface;
120: a pin;
120 a: a top surface;
120 b: a first bottom surface;
122: an inner end;
122 a: a first side wall;
122 b: a second bottom surface;
122 c: a second side wall;
124: an outer end;
124 c: a planar sidewall;
128: recessing;
200: a chip;
210: welding wires;
220: an adhesive agent;
300: packaging the colloid;
300 b: a lower surface;
300 c: a side surface;
400: a layer of conductive material;
500: a connecting strip;
510: a connecting portion;
512: an inner surface;
and (4) LF: a lead frame strip;
c: a pocket;
g: a groove;
m: a mask layer;
s: an arc-shaped recess surface.
Detailed Description
Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings and the description to refer to the same or like parts.
Exemplary embodiments of the present invention will be described more fully hereinafter with reference to the accompanying drawings, but the invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. In the drawings, the size and thickness of regions, regions and layers may not be drawn to scale for clarity. For ease of understanding, like elements in the following description will be described with like reference numerals.
Fig. 1A to fig. 1G are schematic cross-sectional views illustrating a method for fabricating a semiconductor package structure according to an embodiment of the invention. Referring to fig. 1A, a semi-finished package 10 is provided, wherein the semi-finished package 10 includes a lead frame strip LF, a plurality of chips 200, and a molding compound 300. The lead frame strip LF has a plurality of lead frame units 100 and a plurality of connection strips 500 connecting the lead frame units 100. The leadframe units 100 of the leadframe strips LF are arranged in a matrix and separated by connecting strips 500, for example, and each leadframe unit 100 includes a carrier base 110 and a plurality of leads 120 surrounding the carrier base 110. The outer end 124 of each lead 120 is connected to the adjacent connecting bar 500, and the leads 120 of two adjacent leadframe units 100 are disposed opposite to each other two by two and form a plurality of connecting portions 510 on the corresponding connecting bars 500.
Next, referring to fig. 1A and fig. 1B, the bottom of each connecting portion 510 has a groove G, and in the present embodiment, the grooves G of the connecting portions 510 are connected to each other to form a single elongated groove extending along the connecting strip 500. However, in other embodiments not shown, the grooves G of each connecting part 510 may be individual grooves, so that a plurality of grooves separated from each other are formed on the connecting strip 500, and the invention does not limit the form and number of the grooves. Furthermore, the chips 200 of the present embodiment are respectively disposed on the supporting bases 110 of the lead frame unit 100 and electrically connected to the leads 120. The chip 200 and the carrier 110 can be fixed by an adhesive 220, wherein the adhesive 220 is, for example, a common epoxy resin, a silver paste, a Die Attach Film (DAF), etc. Here, the chip 200 is electrically connected to the leads 120 by the bonding wires 210, but the electrical connection is not limited thereto. The material of the bonding wire 210 is, for example, gold, copper or other suitable conductive material, which is not limited herein.
Next, referring to fig. 1A and fig. 1B, the encapsulant 300 covers the lead frame strips LF and the chip 200. In the present embodiment, the inner end 122 of each lead 120 has a recess 128 at the first bottom surface 120b, wherein the molding compound 300 fills the recess 128 of the lead 120 and the groove G of the connection portion 510, and the lower surface 300b of the molding compound 300 is exposed and aligned with the first bottom surface 120b of the lead 120. The encapsulant 300 is made of epoxy or other suitable polymer materials, which can prevent the intrusion of moisture or contaminants. The encapsulant 300 fills the recesses 128 of the leads 120 to lock the leads 120 in the encapsulant 300, thereby preventing the leads 120 from falling off the encapsulant 300. In addition, in the embodiment, the bottom surface 300b of the encapsulant 300 also exposes the bottom surface 110b of the carrier 110, however, in other embodiments not shown, the bottom surface 110b of the carrier 110 may be covered by the encapsulant 300 without being exposed.
Next, referring to fig. 1C, an etching process is performed on the semi-finished package 10. First, a mask layer M is provided to cover a portion of the first bottom surface 120b of the lead 120. In the present embodiment, the mask layer M also covers the bottom surface 110b of the carrier 110. The mask layer M is made of, for example, an insulating photoresist material or a metal material, wherein the metal material, such as gold, palladium or other metal capable of being selectively etched, has a better etching selectivity.
Next, referring to fig. 1C and fig. 1D, the whole package semi-finished product 10 is put into a metal etching solution, such as a copper etching solution, and the mask layer M is used as an etching mask to etch the portion of the lead 120 not shielded by the mask layer M, and a cavity C is formed in the portion of the first bottom surface 120b of the lead 120 adjacent to the groove G. The molding compound 300 in the groove G separates two cavities C of the leads 120, which are disposed oppositely, and each cavity C has an arc-shaped cavity surface S. Here, the arc-shaped recess surface S is embodied as a rough surface, i.e., a microscopically saw-toothed structure, but not limited thereto.
Next, referring to fig. 1D and fig. 1E, the mask layer M is removed to expose the first bottom surfaces 120b of the leads 120. Next, the encapsulant 300 in the groove G is removed to connect the cavities C of the two oppositely disposed leads 120 and expose the inner surface 512 of the connecting portion 510. Here, the encapsulant 300 in the groove G is preferably removed by laser ablation, but not limited thereto. Next, a conductive material layer 400 is formed on the first bottom surface 120b of the lead 120 and the arc-shaped cavity surface S. Further, the conductive material layer 400 may be selectively formed on the inner surface 512 of the connecting portion 510 and the bottom surface 110b of the carrier 110. Here, the conductive material layer 400 is formed by, for example, plating or printing, and the material of the conductive material layer 400 is, for example, lead-free solder, but not limited thereto. To this end, by etching the lead 120, a cavity C is formed at a portion (i.e., the outer end 124) of the first bottom surface 120b of the lead 120 adjacent to the groove G, that is, an inwardly recessed cavity C is formed at the bottom of the outer end 124 of the lead 120, and after the encapsulant 300 in the groove G is subsequently removed, the cavities C of the two oppositely disposed leads 120 and the corresponding grooves G are communicated with each other to form a large cavity. Then, the conductive material layer 400 can be formed on the surface of the large cavity, so that the bonding area between the conductive material layer 400 and the lead 120 can be increased. In addition, the rough arc-shaped cavity surface S can make the conductive material layer 400 better adhere to the arc-shaped cavity surface S, and the rough arc-shaped cavity surface S can also reduce the generation of metal burrs (burr) in the subsequent singulation process.
Thereafter, referring to fig. 1F and fig. 1G, a singulation process is performed to cut the encapsulant 300 and the connecting portion 510, so that the side surface 300c of the encapsulant 300 is aligned with the planar side wall 124c of each lead 120 and the conductive material layer 400 on the arc-shaped cavity surface S of the outer end 124 is exposed, thereby forming independent semiconductor package structures (fig. 1G schematically illustrates a semiconductor package structure 20). Thus, the semiconductor package structure 20 is completed.
Referring to fig. 1G, a semiconductor package structure 20 of the present embodiment includes a lead frame 100', a chip 200, a molding compound 300, and a conductive material layer 400. The lead frame 100' includes a carrier 110 and leads 120 surrounding the carrier 110. Each lead 120 has a top surface 120a and a first bottom surface 120b opposite to each other, an inner end 122 and an outer end 124. The inner end 122 faces the carrier base 110, and the inner end 122 of each lead 120 has a recess 128 at the first bottom 120b, such that the inner end 122 connects the top 120a and the first bottom 120b with the first sidewall 122a, the second bottom 122b, and the second sidewall 122 c. The outer end 124 has a cavity C at the first bottom surface 120b, so that the outer end 124 connects the top surface 120a and the first bottom surface 120b with a planar sidewall 124C and an arc-shaped cavity surface S. The chip 200 is disposed on the carrier 110 and electrically connected to the leads 120 by, for example, bonding wires 210, wherein the chip 200 can be fixed on the carrier 110 by an adhesive 220. The encapsulant 300 covers the leadframe 100' and the chip 200 and fills the recess 128. The molding compound 300 has a lower surface 300b and a side surface 300c, wherein the lower surface 300b is exposed and aligned with the first bottom surface 120b of the lead 120, and the side surface 300c is aligned with the planar sidewall 124c of the lead 120 and exposed out of the arc-shaped cavity surface S. The conductive material layer 400 is disposed on the first bottom surface 120b of each lead 120 and on the arc-shaped cavity surface S. Compared with the conventional pin with the step-shaped structure, the pin 120 with the arc-shaped cavity surface S of the present embodiment can increase the bonding area with the conductive material layer 400 (i.e., increase the wettable area of the pin 120), thereby increasing the bonding yield of the semiconductor package 20 and the external terminal.
In summary, according to the manufacturing method of the semiconductor package structure of the present invention, the recess is further formed at the portion (i.e. the outer end) of the first bottom surface of the lead adjacent to the recess of the connecting portion, that is, the recess is formed at the bottom of the outer end of the lead and is recessed inward, and after the encapsulant in the recess is subsequently removed, the recesses of the two oppositely disposed leads and the corresponding recesses are communicated with each other to form a large cavity. Then, the conductive material layer is at least arranged on the arc-shaped recess surface formed by the recess of the pin and the first bottom surface. Therefore, the bonding area of the conductive material layer can be increased through the pin with the arc-shaped recess surface, so that the area of the conductive material layer on the pin exposed out of the semiconductor packaging structure is increased, and the bonding strength of the electrical connection of the semiconductor packaging structure is further improved. In addition, the surface of the arc recess of the pin can be a rough surface, the rough surface of the arc recess can make the conductive material layer better adhere to the surface of the arc recess, and the formation of metal burrs can be reduced during the singulation process, so that the semiconductor packaging structure has better structural reliability.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.

Claims (10)

1. A semiconductor package structure, comprising:
the lead frame comprises a bearing seat and a plurality of pins surrounding the bearing seat, wherein each pin is provided with a top surface, a first bottom surface, an inner side end and an outer side end which are opposite to each other, the inner side end faces the bearing seat, the outer side end is provided with a cavity at the first bottom surface, and the outer side end is connected with the top surface and the first bottom surface through a plane side wall and an arc-shaped cavity surface;
the chip is configured on the bearing seat and is electrically connected with the pins;
an encapsulant covering the lead frame and the chip, the encapsulant having a lower surface exposed and cut flush with the first bottom surface of each of the plurality of leads and a side surface cut flush with the planar sidewall of each of the plurality of leads and exposed out of the surface of the arc-shaped recess; and
the conductive material layer is configured on the first bottom surface of each pin and the surface of the arc-shaped recess.
2. The semiconductor package structure of claim 1, wherein the arc-shaped recess surface is a rough surface.
3. The semiconductor package structure of claim 1, wherein the inner end of each of the plurality of leads has a recess at the first bottom surface, such that the inner end is connected to the top surface and the first bottom surface by a first sidewall, a second bottom surface and a second sidewall, and the encapsulant fills the recess.
4. The semiconductor package structure of claim 1, wherein the material of the conductive material layer comprises a lead-free solder.
5. A method for manufacturing a semiconductor packaging structure is characterized by comprising the following steps:
providing a semi-finished package product, wherein the semi-finished package product comprises a lead frame strip, a plurality of chips and a package colloid, the lead frame strip is provided with a plurality of lead frame units and a plurality of connecting strips connected with the lead frame units, each lead frame unit comprises a bearing seat and a plurality of pins surrounding the bearing seat, the outer end of each pin is connected to one of the adjacent connecting strips, the pins of the adjacent two lead frame units are arranged oppositely in pairs and form a plurality of connecting parts on one of the connecting strips correspondingly connected, the bottom of each connecting part is provided with a groove, the chips are respectively arranged on the bearing seats of the lead frame units and are electrically connected with the pins, the package colloid covers the lead frame strip and the chips, the packaging colloid fills the groove of each of the plurality of connecting parts, and the lower surface of the packaging colloid is exposed and aligned with the first bottom surface of each of the plurality of pins;
etching the semi-finished package to form a recess in a portion of the first bottom surface of each of the plurality of leads adjacent to the recess, wherein the encapsulant in the recess separates the recesses of the plurality of leads disposed opposite to each other, and the recess has an arc-shaped recess surface;
removing the packaging colloid in the groove to communicate the recesses of the two oppositely arranged pins and expose the inner surfaces of the connecting parts;
forming a conductive material layer on the first bottom surface of each of the plurality of leads and the surface of the arc-shaped recess;
performing a singulation process to cut the encapsulant and the connection portions to form a plurality of independent semiconductor package structures, wherein each of the plurality of semiconductor package structures includes a leadframe having the carrier and a plurality of leads surrounding the carrier, one of the plurality of chips, the encapsulant, and the conductive material layer, each of the plurality of leads has a top surface, a first bottom surface, an inner end, and an outer end opposite to each other, the inner end faces the carrier, the outer end has the cavity at the first bottom surface, the outer end connects the top surface with the arc-shaped cavity surface covered with the conductive material layer through a planar sidewall and the arc-shaped cavity surface covered with the conductive material layer, and a side surface of the encapsulant is aligned with the planar sidewall of each of the plurality of leads and the exposed arc-shaped cavity surface.
6. The method of claim 5, wherein the step of performing the etching process on the semi-finished package comprises:
providing a mask layer to cover a portion of the first bottom surface of each of the plurality of leads; and
and forming the recess on the first bottom surface of each of the plurality of leads by using the mask layer as an etching mask.
7. The method of claim 6, wherein the mask layer is removed to expose the first bottom surface of each of the plurality of leads before removing the encapsulant in the recess.
8. The manufacturing method of a semiconductor package according to claim 5, wherein the surface of the arc-shaped cavity is rough.
9. The method of claim 5, wherein the inner end of each of the leads has a recess at the first bottom surface, such that the inner end is connected to the top surface and the first bottom surface by a first sidewall, a second bottom surface and a second sidewall, and the encapsulant fills the recess.
10. The method of claim 5, wherein the conductive material layer comprises a lead-free solder.
CN202110251441.9A 2021-01-06 2021-03-08 Semiconductor package structure and manufacturing method thereof Pending CN114725030A (en)

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TWI395275B (en) * 2006-09-06 2013-05-01 Megica Corp Chip package and method for fabricating the same
US10211131B1 (en) * 2017-10-06 2019-02-19 Microchip Technology Incorporated Systems and methods for improved adhesion between a leadframe and molding compound in a semiconductor device
JP6733940B1 (en) * 2019-03-22 2020-08-05 大口マテリアル株式会社 Lead frame
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