CN114725047A - Lead frame and manufacturing method thereof applied to semiconductor packaging structure - Google Patents

Lead frame and manufacturing method thereof applied to semiconductor packaging structure Download PDF

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Publication number
CN114725047A
CN114725047A CN202110250519.5A CN202110250519A CN114725047A CN 114725047 A CN114725047 A CN 114725047A CN 202110250519 A CN202110250519 A CN 202110250519A CN 114725047 A CN114725047 A CN 114725047A
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CN
China
Prior art keywords
groove
lead frame
pins
width
leads
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
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CN202110250519.5A
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Chinese (zh)
Inventor
古恒安
吴佳蓉
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Chipmos Technologies Inc
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Chipmos Technologies Inc
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Publication of CN114725047A publication Critical patent/CN114725047A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4828—Etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49517—Additional leads
    • H01L23/4952—Additional leads the additional leads being a bump or a wire
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Abstract

The invention provides a lead frame and a manufacturing method thereof applied to a semiconductor packaging structure. The lead frame comprises a plurality of packaging areas and a plurality of connecting parts connected with the packaging areas. Each packaging area comprises a bearing seat and an outer lead part. The outer pin portion surrounds the carrier and includes a plurality of pins extending toward the periphery. Each connecting part is connected with the pins of the two adjacent outer pin parts and defines a first groove and a second groove with the two adjacent pins. The second groove is positioned between the first groove and the corresponding connecting part, and the groove width of the second groove is smaller than that of the first groove. The lead frame and the manufacturing method thereof applied to the semiconductor packaging structure can reduce the generation of burrs and improve the combination of the packaging structure and the outside so as to be beneficial to subsequent quality inspection.

Description

Lead frame and manufacturing method thereof applied to semiconductor packaging structure
Technical Field
The present disclosure relates to lead frames, and particularly to a lead frame and a method for manufacturing the same.
Background
At present, in a Small outline no-lead (SON) package, since the side edge of the package type is filled with a package adhesive material, the package type is only contacted with an external circuit board through a local pin exposed at the bottom of the package structure as an electrical connection path. Therefore, after the connection to the external circuit board, the pins electrically connected to the external circuit board are located at the bottom of the package structure, and the connection between the pins and the external circuit board cannot be confirmed through appearance inspection, which is not favorable for subsequent electrical and quality inspection. In addition, when the package structure of the leadless small-size package is subjected to a cutting process, the cutter needs to cut off the parallel lead frames to form a single package structure. If the metal portion to be cut by the tool is large, the material characteristic factors of the leadframe made of metal material make the cutting edge of the leadframe prone to form metal burrs at the edge due to the rotation of the tool, so that there is a potential risk of electrical short circuit.
Disclosure of Invention
The invention aims at a lead frame and a manufacturing method thereof applied to a semiconductor packaging structure, which can reduce the generation of burrs and improve the combination of the packaging structure and the outside so as to be beneficial to the subsequent quality inspection.
According to an embodiment of the present invention, the lead frame includes a plurality of package regions and a plurality of connection portions connecting the package regions. Each packaging area comprises a bearing seat and an outer pin part surrounding the bearing seat. The outer lead portion includes a plurality of leads extending toward the periphery. Each connecting part is connected with the pins of the two adjacent outer pin parts and defines a first groove and a second groove with the two adjacent pins. The second groove is positioned between the first groove and the corresponding connecting part, and the groove width of the second groove is smaller than that of the first groove.
In an embodiment of the leadframe according to the invention, each of the leads has a top surface and a bottom surface opposite to each other, the first groove extends from the bottom surface to the top surface, and a height of each of the leads is equal to a sum of a depth of the first groove, a depth of the second groove, and a thickness of the corresponding connection portion.
In the leadframe according to an embodiment of the invention, the depth of the first recess is greater than or equal to 1/2, which is the height of each lead.
In the lead frame according to an embodiment of the present invention, a depth of the second groove is less than or equal to 1/3 of a depth of the first groove.
In an embodiment of the leadframe according to the invention, each of the connecting portions has an outer surface and an inner surface opposite to each other, the outer surface is aligned with the top surface of each lead, and the inner surface is the bottom of the second groove.
In the lead frame according to an embodiment of the invention, the bottom surface of each of the leads and the first lower surface of the carrier are aligned with the second lower surface of the encapsulant.
In an embodiment of the leadframe according to the invention, a width of the second groove is less than or equal to a length of the corresponding connection portion.
In an embodiment of the leadframe according to the invention, a width of the first groove is greater than a length of the corresponding connecting portion.
According to an embodiment of the present invention, a method for manufacturing a lead frame for a semiconductor package structure includes the following steps. A lead frame is provided. The lead frame comprises a plurality of packaging areas and a plurality of extending parts connected with the packaging areas. Each packaging area comprises a bearing seat and an outer pin part surrounding the bearing seat. The outer lead portion includes a plurality of leads extending toward the periphery. Each extending part is connected with the pins of the two adjacent outer pin parts, and the two pins and the corresponding extending parts define a first groove. Etching the extension part to form a plurality of connection parts and a second groove between the two pins. Each connecting part is connected with two adjacent pins, and the second groove is positioned between the first groove and the corresponding connecting part. The groove width of the second groove is smaller than that of the first groove. At least one chip is arranged on at least one bearing seat of the lead frame and is electrically connected with the pins. Forming an encapsulation body to cover the lead frame and the chip. The first groove and the second groove are filled with the packaging colloid.
In the method for manufacturing a lead frame for a semiconductor package structure according to an embodiment of the present invention, the first scribe line and the second scribe line are formed on the two leads and the corresponding connecting portion. The width of the first cutting channel is larger than or equal to the groove width of the first groove, and the width of the second cutting channel is larger than or equal to the groove width of the second groove. After the encapsulant is formed to encapsulate the lead frame and the chip, the method further includes the following steps. A first cutting procedure is performed along the first cutting path to remove the encapsulant in the first groove. And performing a second cutting procedure along the second cutting path to remove the encapsulant and the corresponding connecting part in the second groove and separate the pins. A singulated semiconductor structure is formed.
Based on the above, in the design of the lead frame of the present invention, the connecting portion and the two adjacent pins of the lead frame define the first groove and the second groove, which not only can reduce the generation of metal burrs and avoid short circuit during the subsequent two-stage cutting process, but also can improve the contact area with the solder through the formed recess, thereby improving the bonding yield of the semiconductor structure and the external terminal and facilitating the subsequent inspection.
Drawings
Fig. 1A to fig. 1E are schematic cross-sectional views illustrating a method for manufacturing a lead frame for use in a semiconductor package structure according to an embodiment of the present invention.
Description of the reference numerals
10, a semiconductor packaging structure;
100. 100' lead frame;
110, a bearing seat;
110a first upper surface;
110b a first lower surface;
120, an outer pin part;
122, a pin;
122a, a top surface;
122b, a bottom surface;
122c, a side surface;
126 first groove;
128: a second groove;
200, a chip;
210, routing;
300, packaging the colloid;
300a side surface;
300b, a second lower surface;
b1 and B2 are groove widths;
c, connecting part;
c1, a first cutting path;
c2, second cutting path;
d1, D2 depth;
e, an extension part;
e1, S2 inner surface;
g, sinking;
h is height;
l is the length;
r is a packaging area;
s1, outer surface;
t is the thickness.
Detailed Description
Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings and the description to refer to the same or like parts.
Exemplary embodiments of the present invention will now be described more fully hereinafter with reference to the accompanying drawings, but the invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. In the drawings, the size and thickness of regions, regions and layers may not be drawn to scale for clarity. For ease of understanding, like elements in the following description will be described with like reference numerals.
Fig. 1A to fig. 1E are schematic cross-sectional views illustrating a method for fabricating a lead frame for a semiconductor package structure according to an embodiment of the present invention. First, referring to fig. 1A, a lead frame strip 100 is provided. In detail, the lead frame 100 of the present embodiment includes a plurality of package regions (three package regions R are schematically shown) and a plurality of extension portions (two extension portions E are schematically shown) connected to the package regions R. Each package region R includes a carrier 110 and an outer lead portion 120. The outer lead portion 120 surrounds the carrier 110 and includes a plurality of leads 122 extending toward the periphery. Here, each extension E connects the pins 122 of two adjacent outer lead portions 120. The adjacent two pins 122 and the corresponding extending portions E together define a first groove 126. As shown in fig. 1A, the carrier 110 is surrounded by the outer lead portion 120, and the carrier 110 is located between two leads 122 when viewed in a cross-sectional view. Here, the materials of the carrier 110, the outer leads 120 and the extending portions E are the same, such as a metal or a metal alloy, for example, copper or a copper alloy, but not limited thereto. In particular, the plurality of leads 122 of the outer lead portion 120 surround the carrier 110 without being limited to four sides, and in some possible embodiments, the leads 122 may also surround two sides of the carrier 110 in parallel.
Referring to fig. 1A and fig. 1B, after further performing an etching process on the inner surface E1 of the extension portion E, a plurality of connection portions C are formed, and a second groove 128 is formed between the two leads 122. This etching process removes only a portion of the extension E, thereby forming a connection portion C having a shorter distance from the top of the leadframe 100, i.e., a thinner thickness, and a second recess 128 between the two leads 122. As shown in fig. 1B, in the present embodiment, each connection portion C connects the leads 122 of two adjacent outer lead portions 120, and the second recess 128 is located between the first recess 126 and the corresponding connection portion C. In particular, the groove width B2 of the second groove 128 is less than the groove width B1 of the first groove 126. Thus, the lead frame 100' is completed.
In structure, referring to fig. 1B, the lead frame 100' of the present embodiment includes a package region R and a connection portion C connected to the package region R. The package region R includes a carrier 110 and an outer lead portion 120. The outer lead portion 120 surrounds the carrier 110 and includes a lead 122 extending toward the periphery. The carrier 110 has a first lower surface 110b and a first upper surface 110a opposite to the first lower surface 110 b. Each lead 122 has a top surface 122a and a bottom surface 122b opposite to each other, wherein the first bottom surface 110b of the carrier 110 is substantially aligned with the bottom surface 122b of the lead 122. Each connecting part C has an outer surface S1 and an inner surface S2 opposite to each other, and the outer surface S1 of each connecting part C is aligned with the top surface 122a of each lead 122. In particular, each connection portion C connects the leads 122 of the two outer lead portions 120 in two adjacent package regions R, and defines a first groove 126 and a second groove 128 together with the two adjacent leads 122. The first recess 126 extends from the bottom surface 122b of the lead 122 toward the top surface 122a of the lead 122. The second groove 128 is located between the first groove 126 and the corresponding connecting portion C, wherein the inner surface S2 of the connecting portion C is the bottom of the second groove 128.
Referring to fig. 1B again, in the present embodiment, the height H of each lead 122 is, for example, equal to the sum of the depth D1 of the first groove 126, the depth D2 of the second groove 128, and the thickness T of the corresponding connecting portion C. The depth D1 of the first groove 126 is, for example, 1/2 equal to or greater than the height H of each lead 122, and the depth D2 of the second groove 128 is, for example, 1/3 equal to or less than the depth D1 of the first groove 126. The second groove 128 has a groove width B2 that is less than the groove width B1 of the first groove 126. The groove width B2 of the second groove 128 is, for example, equal to or less than the length L of the corresponding connecting portion C, while the groove width B1 of the first groove 126 is greater than the length L of the corresponding connecting portion C. Here, the groove width B2 of the second groove 128 is exemplified by being equal to the length L of the corresponding connecting portion C. It should be noted that, since the length L of the connecting portion C is the portion removed by the cutting tool in the subsequent cutting process, the length L of the connecting portion C may be the same as the groove width of the second groove 128, or the length L of the connecting portion C may be determined according to the width or the cutting track of the second cutting tool in the subsequent cutting process. A typical leadframe 100 is about 150 microns to about 210 microns thick. The height H of each lead 122 is, for example, about 152 microns, while the depth D1 of the first recess 126 is, for example, about 100 microns, and the depth D2 of the second recess 128 is, for example, about 25 microns. In another possible embodiment, the height H of each pin 122 is, for example, 203 microns, the depth D1 of the first groove 126 is, for example, about 134 microns, and the depth D2 of the second groove 128 is, for example, about 34 microns, but is not limited thereto. In another preferred embodiment, the first groove 126 and the second groove 128 may be further plated to form a plated metal layer (not shown) on the surfaces of the grooves, such as tin or tin alloy, for facilitating subsequent soldering of the upper plate.
In application, referring to fig. 1C, at least one chip (schematically, one chip 200 is shown) is disposed on the lead frame 100 ', wherein the chip 200 is disposed on the first upper surface 110a of the carrier base 110 of the lead frame 100' and electrically connected to the outer lead portion 120 by wire bonding 210. Here, the chip 200 may be fixed on the carrier 110 by an adhesive layer (not shown), but is not limited thereto.
Then, referring to fig. 1C and fig. 1D, an encapsulant 300 is formed to encapsulate the lead frame 100', the chip 200 and the wire 210, and to fill the first groove 126 and the second groove 128 of the outer lead portion 120. Here, the material of the encapsulant 300 is, for example, epoxy resin or other suitable encapsulant, but is not limited thereto. As shown in fig. 1D, the bottom surface 122b of each lead 122 and the first lower surface 110b of the carrier 110 are aligned with the second lower surface 300b of the molding compound 300. That is, the second lower surface 300b of the encapsulant 300 is substantially coplanar with the bottom surface 122b of each lead 122 and the first lower surface 110b of the carrier 110.
Finally, referring to fig. 1D and fig. 1E, a first scribe line C1 and a second scribe line C2 are formed on two adjacent leads 122 and corresponding connecting portions C of two adjacent package regions R. Here, the width of the first cut C1 is equal to or greater than the groove width B1 of the first groove 126, and the width of the second cut C2 is equal to or greater than the groove width B2 of the second groove 128. It should be noted that the width of the first cut-off channel C1 and the second cut-off channel C2 is determined by referring to the width of the cutting tool.
Next, a first cutting process is performed along the first cutting path C1 to remove the encapsulant 300 in the first groove 126 of the outer lead portion 120. That is, the first cutting process does not completely separate the leads 122, but a half-cut process is performed to remove the encapsulant 300 in the first groove 126. Thereafter, a second cutting process is performed along the second cutting path C2 to remove the encapsulant 300 in the second groove 128 of the outer lead portion 120, the connection portion C corresponding to the second groove 128, and the encapsulant 300 on the outer surface S1 of the connection portion C, and separate the leads 122 to form the singulated semiconductor package structure 10. At this time, the side surface 300a of the encapsulant 300 is aligned with the side surface 122c of the lead 122, and a recess G is formed between the bottom surface 122b and the side surface 122c of the lead 122 to expose the side surface of the lead 122, thereby increasing the contact area of the subsequent solder, improving the bonding yield and the reliability inspection. Thus, the lead frame 100' of the present embodiment is applied to the fabrication of the semiconductor package structure 10.
In brief, in the leadframe 100' of the present embodiment, the connecting portion C connects the leads 122 of the two adjacent outer lead portions 120 and defines a first groove 126 and a second groove 128 with the two adjacent leads 122. The design of the first groove 126 and the second groove 128 reduces the amount of metal cut by the cutting tool during the subsequent two-stage cutting process, thereby reducing the occurrence of metal burrs and avoiding the risk of short-circuiting. In addition, the first groove 126 and the second groove 128 are designed such that after the subsequent two-stage cutting process, the recess G is formed on the bottom surface 122b and the side surface 122c of the lead 122, which can increase the contact area with the solder, thereby increasing the bonding yield of the semiconductor structure 10 and the external terminal and facilitating the subsequent inspection.
In summary, in the design of the lead frame of the present invention, the connecting portion of the lead frame and the two adjacent leads define the overlapped first groove and the overlapped second groove together, which not only reduces the generation of metal burrs and avoids short circuit during the subsequent two-stage cutting process, but also improves the contact area with the solder through the formed recess, thereby improving the bonding yield of the semiconductor structure and the external terminal and facilitating the subsequent inspection.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.

Claims (10)

1. A leadframe, comprising:
a plurality of package regions, each of the plurality of package regions including a carrier and an outer lead portion surrounding the carrier, the outer lead portion including a plurality of leads extending toward a periphery; and
and the connecting parts are connected with the packaging areas, each of the connecting parts is connected with the pins of two adjacent outer pin parts, a first groove and a second groove are defined by the two adjacent pins, the second groove is positioned between the first groove and the corresponding connecting part, and the groove width of the second groove is smaller than that of the first groove.
2. The lead frame according to claim 1, wherein each of the leads has a top surface and a bottom surface opposite to each other, the first recess extends from the bottom surface toward the top surface, and a height of each of the leads is equal to a sum of a depth of the first recess, a depth of the second recess, and a thickness of the corresponding connection portion.
3. The lead frame of claim 2, wherein the depth of the first recess is greater than or equal to 1/2, the height of each of the plurality of leads.
4. The lead frame of claim 3, wherein the depth of the second recess is less than or equal to 1/3 times the depth of the first recess.
5. The lead frame according to claim 2, wherein each of the plurality of connecting portions has an outer surface and an inner surface opposite to each other, the outer surface is aligned with the top surface of each of the plurality of leads, and the inner surface is a bottom of the second recess.
6. The lead frame according to claim 2, wherein the bottom surface of each of the plurality of leads and the first bottom surface of the carrier are aligned with a second bottom surface of the encapsulant.
7. The lead frame according to claim 1, wherein the width of the second groove is less than or equal to the length of the corresponding connecting portion.
8. The lead frame according to claim 1, wherein the first recess has a width greater than a length of the corresponding connecting portion.
9. A manufacturing method of a lead frame applied to a semiconductor packaging structure is characterized by comprising the following steps:
providing a lead frame, wherein the lead frame comprises a plurality of packaging areas and a plurality of extending parts connected with the plurality of packaging areas, each of the plurality of packaging areas comprises a bearing seat and an outer pin part surrounding the bearing seat, the outer pin part comprises a plurality of pins extending towards the periphery, each of the plurality of extending parts is connected with the plurality of pins of two adjacent outer pin parts, and the two plurality of pins and the corresponding extending parts define first grooves;
etching the plurality of extending parts to form a plurality of connecting parts, and forming a second groove between two pins, wherein each of the plurality of connecting parts is connected with two adjacent pins, the second groove is located between the first groove and the corresponding connecting part, and the groove width of the second groove is smaller than that of the first groove;
arranging at least one chip on at least one bearing seat of the lead frame and electrically connecting the chip with the pins; and
and forming an encapsulation colloid to coat the lead frame and the at least one chip, wherein the encapsulation colloid fills the first groove and the second groove.
10. The method as claimed in claim 9, wherein a first scribe line and a second scribe line are formed on the two leads and the corresponding connecting portions, a width of the first scribe line is greater than or equal to a width of the first groove, a width of the second scribe line is greater than or equal to a width of the second groove, and after the encapsulant is formed to encapsulate the lead frame and the at least one chip, the method further comprises:
performing a first cutting procedure along the first cutting path to remove the encapsulant in the first groove; and
and performing a second cutting procedure along the second cutting path to remove the encapsulant and the corresponding connecting parts in the second groove, and separating the plurality of pins to form a single semiconductor structure.
CN202110250519.5A 2021-01-05 2021-03-08 Lead frame and manufacturing method thereof applied to semiconductor packaging structure Pending CN114725047A (en)

Applications Claiming Priority (2)

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TW110100294A TWI750988B (en) 2021-01-05 2021-01-05 Leadframe strip and its manufacturing method applied to semiconductor package structure

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US9601415B2 (en) * 2014-03-27 2017-03-21 Renesas Electronics Corporation Method of manufacturing semiconductor device and semiconductor device
TWM589900U (en) * 2019-09-27 2020-01-21 長華科技股份有限公司 Semiconductor package element with convex micro pins

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