201044527 六、發明說明： 【發明所屬之技術領域】 本發明係有關於半導體裝置，特別係有關於一種凸塊 化晶片結構及其應用之半導體覆晶裝置 【先前技術】 覆晶接合技術（flip-chip bonding techn〇1〇gy)是將晶 片之主動面的銲墊上設置複數個導電凸塊（或稱為突出 〇 狀電極藉由晶片翻轉方式接合到基板以完成電性連 接。相較於使用打線連接（wire bond)之電性連接方式， 提供了晶片至基板之較短電性連接路徑與適用於高密度 輸出/入接點數量之產品製造，具有良好的高頻訊號的傳 輸品質。 然而’導電凸塊接合在晶片與基板之間係為覆晶間隙 内的點對點結合，一旦受到熱應力與基板翹曲變形將會 導致凸塊斷裂，進而造成晶片與基板之間電氣訊號傳遞 Q 失敗。 目前的覆晶接合技術可分為兩大類，一是使錫錯凸塊 回焊成球形’但錫鉛凸塊不符合無鉛化要求，並且在回 焊的高溫下錫鉛凸塊不具有維持覆晶間隙的功能，相鄰 的锡錯凸塊容易產生焊料橋接，不適用於微間距的覆晶 接〇 °另一是使用金凸塊（Au bump)的接合技術，金凸塊 以熱壓合或是異方性導電膠電性連接至基板。雖然其可 靠性較佳並且不會有回焊成球狀的橋接短路問題，但金 凸塊的材料成本過高，仍亟需發展同等級品質的替代凸 201044527 塊。 近來，有人提出一種亦有使用低成本的導電凸塊來取 代金塊，導電凸塊的全部或是下半部選用較硬的銅為材 料，簡稱為銅凸塊。然而銅凸塊因其較硬之材質相對使 得柔軟度較差，施加於銅凸塊的應力會直接傳遞到鋼凸 塊與Μ片金屬墊的接合界面，導致銅凸塊的底部斷裂或 是造成晶片受損。特別在多個凸塊無法控制相當準確的 〇 等高或是基板與晶片之間的覆晶間隙為非一致（例如基 板翹曲變形時）的狀況時，銅凸塊的底部斷裂問題會變得 更嚴重。此外，銅容易氧化，在凸塊製程必須保持在還 原氣氛’並在凸塊製成之後另作防氧化的保護，製程限 制頗多，並不能有效降低凸塊的製造成本。 【發明内容】 為了解決上述之問題，本發明之主要目的係在於提供 一種具覆膜式金屬凸塊之晶片結構，能符合無鉛化、高 Ο 可靠度與低成本之凸塊要求，更可達成凸塊高密度排 列，以增加晶片與基板間的結合力，進而提升高頻訊號 的傳輸品質。 本發明的目的及解決其技術問題是採用以下技術方 案來實現的。本發明揭示一種具覆膜式金屬凸塊之晶片 結構’主要包括一晶片、複數個凸塊下金屬層、複數個 銀凸塊（Ag bump)以及一抗潛變層。該晶片係具有複數個 銲墊以及一保護層’該保護層係覆蓋於該晶片之一表面 上並具有複數個開孔，以顯露該些銲墊》該些凸塊下金 4 201044527 屬層係設置於該些銲墊上並覆蓋該保護層之該些開孔之 周邊。該些銀凸塊（Ag bunip)係呈柱狀並設置於該些凸塊 下金屬層上’並使該些凸塊下金屬層係具有不被該些銀 凸塊覆蓋之側緣，並且每一銀凸塊係具有一頂面以及一 柱側壁°該抗潛變層係包覆該些銀凸塊之頂面與柱侧 壁’並藉由該抗潛變層之形成而在該些凸塊下金屬層之 側緣形成複數個缺口環’以使該抗潛變層不接觸至該保 護層。 Ο “ 本發明的目的及解決其技術問題還可採用以下技術 措施進一步實現。 在前述之具覆膜式金屬凸塊之晶片結構中，該些缺口 環之寬度係可不大於該些凸塊下金屬層之厚度，以使該 抗潛*變層完全覆蓋該些銀凸塊。 在前述之具覆膜式金屬凸塊之晶片結構中，該抗潛變 層係可局部覆蓋至該些凸塊下金屬層之側緣。 〇 在前述之具覆膜式金屬凸塊之晶片結構中，該些銀凸 塊之材質係可選自於純銀或銀合金。 在前述之具覆膜式金屬凸塊之晶片結構中，該些銀凸 塊係可包含不小於8〇wt%的銀含量。 在前述之具覆膜式金屬凸塊之晶片結構中，該些凸塊 下金屬層係可包含一結合層以及一導電層，該結合層係 貼附於該些銲墊，該導電層係貼附於該結合層。 在前述之具覆膜式金屬凸塊之晶片結構中，該抗潛變 層係可覆蓋至該導電層之側緣而顯露該結合層之側緣。 201044527 在前述之具覆膜式全思π 、金屬凸塊之晶片結構中，該抗潛變 層係可為顯露並具有拉备， ’杭氧化與高導電之特性。 在前述之具覆膜式全思η 1 、金屬凸塊之晶片結構中，該些銀凸 塊之外形係可選自圓杈科 ^ ^ 枉體、方柱體以及長條形體之其中 之一0 在前述之具覆膜式金屬凸塊之晶片結構中’該些銀凸 塊之頂面與柱側壁之間係可為有角度彎曲。 〇 &前述之具覆膜式金屬凸塊之晶片結構中，該抗潛變 層之硬度係可不高於或接近該些銀凸塊之硬度。 在别述之具覆膜式金屬凸塊之晶片結構中，該抗潛變 層係可選自於置換金與還原金之其中之一。 在前述之具覆膜式金屬凸塊之晶片結構中，該些凸塊 下金屬層之側緣係可相對凹入於該些銀凸塊之該些柱側 壁。 本發明另揭示運用前述具覆膜式金屬凸塊之晶片結 〇 構的一種半導體覆晶裝置，另包含一基板，其中該基板 之一表面係設有複數個連接墊，該些銀凸塊係經由該抗 潛變層電性連接至該基板之該些連接墊。 由以上技術方案可以看出’本發明之具覆膜式金屬凸 塊之晶片結構’有以下優點與功效： 一、可藉由銀凸塊、抗潛變層與缺口環之特定組合關係 作為其中一技術手段，由於選用銀凸塊取代習知的 金凸塊’更優於習知的銅四塊’不會有鋼凸塊的底 部斷裂問題，能符合無鉛化、高可靠度與低成本之 201044527 凸塊要求。更由於缺口環之形成，以使抗潛變層不 接觸至保護層，可達成凸塊高密度排列’以增加晶 片與基板間的結合力，進而提升高頻訊號的傳輸品 質。 一、 可藉由銀凸塊與抗潛變層之特定組合關係作為其中 一技術手段，由於抗潛變層係為置換金（或還原金） 並完全覆蓋銀凸塊，故抗潛變的處理時間短、形成 厚度可控制在lem以内，能避免銀凸塊之潛變發 生’不會使銀凸塊的尺寸橫向變大，故在高溫下不 會產生覆晶間隙變化，具有成本更低、厚度更薄之 功效8 二、 可藉由晶片、抗潛變層與缺口環之特定組合關係作 為其中一技術手段’由於所形成的缺口環使得抗潛 變層不接觸至晶片之保護層，藉此產生一緩衝空 間’能控制完整覆蓋銀凸塊之表面卻不會延伸到保 護層’以減少微間距凸塊之間產生電性短路問題， 並預防凸塊因變形擠壓至晶片而從凸塊底部斷開， 影響了整體電性連接效果。 【實施方式】 以下將配合所附圖示詳細說明本發明之實施例，然應 注意的是，該些圖示均為簡化之示意圖，僅以示意方法 來說明本發明之基本架構或實施方法，故僅顯示與本案 有關之元件與組合關係，圖中所顯示之元件並非以實際 實施之數目、形狀、尺寸做等比例繪製，某些尺寸比例 201044527 與其他相關尺寸比例或已誇 ’張或是簡化處理，以提供更 清楚的描述。實際實施之翁 y 数目、形狀及尺寸比例為一種 選置性之設計，詳細之开她 ^凡件佈局可能更為複雜。 依據本發明之一具體音油η 貫施例’一種具覆膜式金屬凸塊 之晶片結構1 〇〇舉例說明於 弟1圖之截面不意圖與第2Α 至2F圖之製程中元件恭而_ 千截面不意圖。該具覆膜式金屬凸塊 之晶片結構100係主要白紅 要包括一晶片110、複數個凸塊下 Ο Ο 金屬層 120(under bumn ,,201044527 VI. Description of the Invention: [Technical Field] The present invention relates to a semiconductor device, and more particularly to a bumper wafer structure and a semiconductor flip chip device therefor. [Prior Art] Flip-chip bonding technology (flip- Chip bonding techn〇1〇gy) is to place a plurality of conductive bumps on the pads of the active surface of the wafer (or referred to as protruding bump electrodes to be bonded to the substrate by wafer flipping to complete the electrical connection. Compared with the use of wire bonding The electrical connection of the wire bond provides a short electrical connection path from the wafer to the substrate and a product suitable for high-density output/input points, and has good transmission quality of high-frequency signals. The conductive bumps are bonded to the point-to-point bond in the flip-chip gap between the wafer and the substrate. Once subjected to thermal stress and warpage deformation of the substrate, the bumps may be broken, thereby causing the electrical signal transmission Q between the wafer and the substrate to fail. The flip chip bonding technology can be divided into two categories, one is to re-weld the tin bumps into a spherical shape, but the tin-lead bumps do not meet the lead-free requirements. And the tin-lead bumps do not have the function of maintaining the flip-chip gap at the high temperature of the reflow, the adjacent tin bumps are prone to solder bridging, and are not suitable for the micro-pitch flip chip. Another is the use of gold bumps. In the bonding technique of Au bump, the gold bumps are electrically connected to the substrate by thermocompression or anisotropic conductive paste. Although the reliability is good and there is no bridging short circuit problem of reflowing into a spherical shape, The material cost of gold bumps is too high, and there is still an urgent need to develop the same grade of quality bumps 201044527. Recently, it has been proposed to use low-cost conductive bumps instead of gold bumps, all or the lower half of the conductive bumps. The harder copper is used as the material, which is referred to as copper bump. However, the copper bump is relatively soft due to its relatively hard material, and the stress applied to the copper bump is directly transmitted to the steel bump and the metal pad. Bonding the interface, causing the bottom of the copper bump to break or damage the wafer. Especially in the case where a plurality of bumps cannot control a fairly accurate crucible contour or the flip-chip gap between the substrate and the wafer is non-uniform (for example, substrate warpage) When deformed The condition of the bottom break of the copper bumps becomes more serious. In addition, the copper is easily oxidized, and must remain in the reducing atmosphere during the bump process and protect the oxidation after the bumps are made. In order to solve the above problems, the main object of the present invention is to provide a wafer structure with a film-type metal bump, which can meet the lead-free and high-grade Reliable and low-cost bump requirements, higher density arrangement of bumps can be achieved to increase the bonding force between the wafer and the substrate, thereby improving the transmission quality of the high-frequency signal. The object of the present invention and solving the technical problem is to adopt the following The invention discloses a wafer structure with a film-type metal bump, which mainly comprises a wafer, a plurality of under bump metal layers, a plurality of silver bumps (Ag bumps) and an anti-dense layer. The wafer has a plurality of pads and a protective layer covering the surface of one of the wafers and having a plurality of openings to expose the pads. The bumps are under the gold 4 201044527 And disposed on the pads and covering the periphery of the openings of the protective layer. The silver bumps are columnar and disposed on the underlying metal layers of the bumps, and the underlying metal layer of the bumps have side edges that are not covered by the silver bumps, and each a silver bump has a top surface and a pillar sidewall. The anti-dip layer covers the top surface of the silver bumps and the pillar sidewalls and is formed by the anti-latent layer. A plurality of notched rings are formed on the side edges of the underlying metal layer such that the anti-dwelling layer does not contact the protective layer. Ο "The object of the present invention and solving the technical problems thereof can be further achieved by the following technical measures. In the above-mentioned wafer structure with a coated metal bump, the width of the notched rings can be no more than the under bump metal The thickness of the layer is such that the anti-submersible layer completely covers the silver bumps. In the foregoing wafer structure with a coated metal bump, the anti-potential layer may partially cover the bumps The side edge of the metal layer. In the foregoing wafer structure with a coated metal bump, the material of the silver bumps may be selected from pure silver or a silver alloy. In the above-mentioned laminated metal bumps In the wafer structure, the silver bumps may comprise a silver content of not less than 8 〇wt%. In the above-mentioned wafer structure with a coated metal bump, the under bump metal layer may comprise a bonding layer. And a conductive layer attached to the bonding pads, the conductive layer is attached to the bonding layer. In the foregoing wafer structure with a coated metal bump, the anti-potential layer can be Covering the side edges of the conductive layer to reveal the side of the bonding layer 201044527 In the above-mentioned wafer structure with a film-type π, metal bump, the anti-potential layer can be exposed and has a pull, 'hang oxidation and high conductivity characteristics. In the wafer structure of the film type 1 1 , the metal bumps, the silver bumps may be selected from the group consisting of a 枉 ^ ^ ^ 枉 , a square cylinder and a long strip body. In the wafer structure of the coated metal bumps, the top surface of the silver bumps and the sidewalls of the pillars may be angularly curved. In the above wafer structure with a coated metal bump, the resistance The hardness of the latent layer may be no higher or closer to the hardness of the silver bumps. In the wafer structure with a coated metal bump, the anti-potential layer may be selected from the replacement gold and the reduced gold. In the above-mentioned wafer structure with a coated metal bump, the side edges of the under bump metal layers may be relatively recessed to the pillar sidewalls of the silver bumps. A semiconductor flip chip device using the foregoing wafer junction structure with a coated metal bump Further comprising a substrate, wherein a surface of one of the substrates is provided with a plurality of connection pads, and the silver bumps are electrically connected to the connection pads of the substrate via the anti-potential layer. The wafer structure of the coated metal bump of the present invention has the following advantages and effects: 1. A specific combination of silver bumps, anti-dense layers and notched rings can be used as one of the technical means, since silver is selected. The bump replaces the conventional gold bump 'better than the conventional copper four block' without the bottom fracture problem of the steel bump, which can meet the lead-free, high reliability and low cost 201044527 bump requirement. The notch ring is formed so that the anti-dense layer does not contact the protective layer, and the high-density arrangement of the bumps can be achieved to increase the bonding force between the wafer and the substrate, thereby improving the transmission quality of the high-frequency signal. The specific combination relationship between the bump and the anti-situ layer is one of the technical means. Since the anti-situ layer is replaced gold (or reduced gold) and completely covers the silver bump, the anti-potential treatment time is short and the thickness can be formed. Within the lem, it can avoid the occurrence of the latent change of the silver bumps 'will not make the size of the silver bumps laterally larger, so there will be no change in the gap between the crystals at high temperatures, and the effect of lower cost and thinner thickness 8 Second, the specific combination relationship of the wafer, the anti-situ layer and the notch ring can be used as one of the technical means 'the gap layer formed so that the anti-dive layer does not contact the protective layer of the wafer, thereby generating a buffer space' It can control the surface of the complete silver bump without extending to the protective layer' to reduce the electrical short circuit between the micro-pitch bumps, and prevent the bump from being broken from the bottom of the bump due to deformation and extrusion to the wafer, affecting The overall electrical connection effect. The embodiments of the present invention will be described in detail below with reference to the accompanying drawings in which Therefore, only the components and combinations related to the case are shown. The components shown in the figure are not drawn in proportion to the actual number, shape and size of the actual implementation. Some size ratios 201044527 are proportional to other related sizes or have been exaggerated or Simplify the process to provide a clearer description. The actual implementation of the y number, shape and size ratio is an optional design, in detail, the layout of the pieces may be more complicated. According to one embodiment of the present invention, a specific kerosene η embodiment of a wafer structure with a film-type metal bump 1 〇〇 exemplifies the section of the diagram of the brother 1 is not intended to be in the process of the second to the 2F diagram. Thousand sections are not intended. The wafer structure 100 with a film-type metal bump is mainly white and red, and includes a wafer 110 and a plurality of under bumps and a metal layer 120 (under bumn,
Ump metallurgy layers, UBM layers)複數個銀凸塊（Ag bump) 130以及一抗潛變層 40該阳片110係具有複數個銲墊111以及一保護層 112,該保護層112係覆蓋於該晶片11〇之一表面m上 並具有複數個開孔114，以顯露該些銲墊Ul。該晶片 11 〇係為半導體材質，例如矽或是ΙΠ_ν族半導體，該表 面113即為該晶片110之主動面，可形成有積體電路元 件，選自於微控制器、微處理器、記憶體、邏輯電路、 特殊應用積體電路（例如顯示器驅動電路）等或上述的任 意組合。該些銲墊丨丨丨係由金屬製成，例如鋁、銅以及 其合金等’可作為該晶片11〇訊號輸出入之端子。該保 護層112係為電絕緣性的表面層’或稱其為鈍化層，材 質可為聚亞醯胺、苯環丁烯（BCB)、磷矽玻璃 (phosphosilicate glass)、氧化石夕（silicon oxide)、氮化石夕 (silicon nitride)或氮化物（nitride)，可藉由化學氣相沉積 (CVD)技術所形成，能提供保護該表面113上之積體電 路元件並使該表面丨丨3更為平坦》在本實施例中，該保 201044527Ump metallurgy layers, UBM layers) a plurality of silver bumps (Ag bumps) 130 and an anti-dense layer 40. The anodes 110 have a plurality of pads 111 and a protective layer 112 covering the wafer. One of the surfaces m has a plurality of openings 114 to expose the pads U1. The wafer 11 is made of a semiconductor material, such as a germanium or a germanium-based semiconductor. The surface 113 is an active surface of the wafer 110, and can be formed with an integrated circuit component selected from a microcontroller, a microprocessor, and a memory. , logic circuit, special application integrated circuit (such as display drive circuit), or the like, or any combination of the above. The pads are made of metal, such as aluminum, copper, and alloys thereof, which can be used as terminals for the output of the wafer 11 signal. The protective layer 112 is an electrically insulating surface layer or a passivation layer, and the material may be polyamidoamine, benzocyclobutene (BCB), phosphosilicate glass, or silicon oxide. ), silicon nitride or nitride, which can be formed by chemical vapor deposition (CVD) techniques, can provide protection of the integrated circuit components on the surface 113 and make the surface 丨丨3 more In the case of flatness, in this embodiment, the guarantee 201044527
❹ 護層112之開孔114係可局部覆蓋該些銲塾lu之周 緣，即該些開孔114之尺寸略小於該些銲塾丨丨丨之尺寸 請參閱第1圖所示，該些凸塊下金屬層12〇係設置於 該些銲墊111上並覆蓋該保護層112之該些開孔114之 周邊。該些凸塊下金屬層120係為墊片狀，以供設置該 些銀凸塊130’而該些銲塾1U係與位置對應的該些凸 塊下金屬層120電性連接。具體而言，該些凸塊下金屬 層120係可包含一結合層121以及一導電層122，用以 增進該些銀凸塊130與該些銲墊lu之間的連結。更進 一步地，該結合層121係貼附於該些銲墊m，可以提 供該些銲墊111與該保護層112良好的黏著性並具有阻 障作用，以防止金屬擴散。該結合層121之材質可為鈦 (Ti)或鶴化鈦（TiW)。該導電層122係貼附於該結合層 121。該導電層122的導電性應高於該結合層i2i並厚度 可更薄’可作為形成該些銀凸塊13〇之電鍍種子層，並 且該導電層122可提供對該些銀凸塊13〇之良好的沾附 性’該導電122之材質可為金(Au)。在本實施例中， 該結合層12 1與該 氣相沉積方式形成 導電層122係可以電鍍、濺鍍或化學 。通常該些凸塊下金屬層12〇係可大 112之 於該保護層112之開孔 對應開孔114之周緣。 114，以延伸至該保護層 請參閱第1圖所示，該些銀凸塊130係呈柱狀並設置 於該些凸塊下金屬層！ 2〇上，並使該些凸塊下金屬層12〇 係具有不被該些銀凸塊13〇覆蓋之側緣123，並且每一 201044527 銀凸塊130係具有一頂面131以及一柱侧壁132。在本 實施例中，該些銀凸塊13〇之頂面131與柱側壁132之 間係可為有角度彎曲，例如約9〇度，用以界定該頂面 131之面積進而有效控制凸塊接合區域，有利於非迴焊 之導電接合。關於該些銀凸塊13〇的柱狀型態，該些銀 凸塊130的高度可大於該些銀凸塊13〇的底部面積之一 直徑或一寬度。該些銀凸塊130之高度係可介於3" m(微 ΟThe opening 114 of the protective layer 112 partially covers the periphery of the soldering pads lu, that is, the sizes of the openings 114 are slightly smaller than the dimensions of the soldering pads. Please refer to FIG. 1 for the convexities. The under-metal layer 12 is disposed on the pads 111 and covers the periphery of the openings 114 of the protective layer 112. The under bump metal layers 120 are shim-shaped for providing the silver bumps 130', and the solder bumps 1U are electrically connected to the bump lower metal layers 120 corresponding to the locations. In particular, the under bump metal layer 120 can include a bonding layer 121 and a conductive layer 122 for enhancing the bonding between the silver bumps 130 and the pads lu. Further, the bonding layer 121 is attached to the pads m, and the pads 111 are provided with good adhesion to the protective layer 112 and have a barrier function to prevent metal diffusion. The material of the bonding layer 121 may be titanium (Ti) or titanium (TiW). The conductive layer 122 is attached to the bonding layer 121. The conductive layer 122 should have a higher conductivity than the bonding layer i2i and can be thinner. The plating layer can be formed as a plating seed layer for forming the silver bumps 13 and the conductive layer 122 can provide the silver bumps 13 Good adhesion. The material of the conductive layer 122 can be gold (Au). In this embodiment, the bonding layer 12 1 and the vapor deposition forming conductive layer 122 may be plated, sputtered or chemically. Generally, the under bump metal layer 12 can be large 112. The opening of the protective layer 112 corresponds to the periphery of the opening 114. 114, extending to the protective layer. As shown in FIG. 1, the silver bumps 130 are columnar and disposed on the underlying metal layers of the bumps! 2, and the under bump metal layer 12 has a side edge 123 not covered by the silver bumps 13 , and each of the 201044527 silver bumps 130 has a top surface 131 and a pillar side Wall 132. In this embodiment, the top surface 131 of the silver bumps 13 and the pillar sidewalls 132 may be angled, for example, about 9 degrees, to define the area of the top surface 131 to effectively control the bumps. The bonding area facilitates non-reflow soldered conductive bonding. Regarding the columnar patterns of the silver bumps 13A, the heights of the silver bumps 130 may be larger than one diameter or a width of the bottom regions of the silver bumps 13A. The height of the silver bumps 130 can be between 3 " m (micro Ο
G 米）到25以m(微米）。在本實施例中，如3A至3C圖所示， 該些銀凸塊130之外形係可選自圓柱體、方柱體以及長 條形體之其中之一。該些銀凸塊13〇之材質係可選自於 純銀或銀合金，其係包含不小於8〇wt%(重量百分比）的 銀含量。較佳地，該些銀凸塊13〇包含不小於99wt%的 銀含量而具有高純度，適合以電鍍方式大量形成，並具 有在電錢製程中達到均質化之功效，不會有因成份散布 不均的缺陷導致凸塊硬度的差異變化。因此，該些銀凸 塊130具有大約與習知金凸塊相同但低於銅凸塊的硬 度並J_導電性與金屬延伸性良好。故該些銀巧塊⑼ 之成本相較於習知之金凸塊具有較低之成I，並符合無 錯化之要求，能在不會影響凸塊的性能與品質下，取代 習知的金凸塊’更優於習知的銅凸塊，不會有習知銅凸 塊的底部斷裂問題。 請參閱第i圖所示，該抗潛變層14〇係包覆該些銀凸 塊130之頂面131與柱側壁132,並藉由該抗潛變層14〇 之形成而在該些凸塊下_ 12〇之側、緣123形成複數 10 201044527 個缺口環150，以使該括概抛 11〇 _ °抗，日變層140不接觸至該保護層 U2。該抗潛變層ι4〇 〜厗度係可介於〇.03 μ m(微米）到 3 μ m(微米），相對於該此 二銀凸塊130的高度，該抗潛變 層140係為一表面覆蓋之笼 復蓋之4層，其厚度控制在該些銀凸 塊之高度在百分之+ 卞以下’不致影響該些銀凸塊130 Ο Ο 的整體結構與硬度等物理特性。在本實施例中，該抗潛 變層140係可為顯露並具有抗氧化與高導電之特性，其 係僅選自於金(Au)或鈀(pd)。較佳地，該抗潛變層"〇 係可選自於置換金（displaeement Au)與還原金（reduced AU)之其中之一，故抗潛變的處理時間短、形成厚度可控 制在1以m(微米）以内（約數十到數百埃），便能避免該些 銀凸塊130之潛變發生，並且不會使該些銀凸塊130的 尺寸橫向變大’故在高溫下不會產生覆晶間隙變化，具 有成本更低、厚度更薄之功效。特別是該抗潛變層 之硬度係可不兩於或接近該些銀凸塊130之硬度，而不 而要有凸塊結構補強之作用，故該抗潛變層14〇的厚度 增加與減少皆不會影響與改變整體凸塊的結構強度。 此外’如第1圖所示，該些缺口環15〇之寬度係可不 大於該些凸塊下金屬層120之厚度，以使該抗潛變層ι4〇 疋全覆蓋該些銀凸塊13〇，故該些銀凸塊13〇不會顯露 :卜八大氣環丨兄直接接觸。在本實施例中，由於該些銀 凸塊130係為全包覆型態，可避免在覆晶接合之後，在 該些銀凸塊13〇之柱側壁132的底部產生該抗潛變層 ^0的崩裂’藉以增進該抗潛變層14〇的抗潛變作用， 201044527 有效降低該些銀凸塊130的潛變發生◊詳細而言，該抗 潛變層140係可局部覆蓋至該些凸塊下金屬層12〇之側 緣123 °例如’該抗潛變層u〇係可覆蓋至該導電層122 之側緣而顯露該結合層i 2丨之側緣。因此，不會使得該 抗潛變層140接觸至該晶片11〇之該保護層112，以達 成凸塊高密度排列’並能增加晶片與基板間的結合力， 進而提升高頻訊號的傳輸品質。更進一步地，亦能藉由 0 該缺口環1 50產生一緩衝空間，能控制該抗潛變層140 完整覆蓋該些銀凸塊130之表面卻不會延伸到該保護層 11 2，以減少凸塊間短路的問題，並可以預防該些銀凸塊 130因變形擠壓至該晶片11〇而從該些銀凸塊13〇底部 斷開，影響了整體電性連接效果。 一般而言，金屬材料在常溫下，受到彈性限度以下之 應力長時間作用時’並不容易發生變化。但在高溫環境 下，受到較低於彈性限度之應力作用時，金屬材料會隨 Ο 著時間漸漸地產生變形，此一現象稱之為潛變（creep)。 由於銀凸塊130的潛變現象會高於金凸塊與銅凸塊，故 本發明必須利用在該些銀凸塊130表面之抗潛變層14〇 的薄膜包覆效果’特別是包覆該些銀凸塊1 3 0的柱側壁 132’避免該些銀凸塊130在長期應力作用下發生潛變而 產生緩慢變形之現象’防止該些銀凸塊13〇往側向變胖 的變形，以維持覆晶間隙並達到有效接合。 請參閱第2A至2F圖所示’本發明進一步說明該具 覆膜式金屬凸塊之晶片結構100之製造方法，以彰顯本 12 201044527 案的功效。 首先’如第2A圖所示’提供一晶片11〇，多個晶片 110在該步驟中可構成於一晶圓，該晶片11〇係具有複 數個銲墊111以及一保護層112，該保護層Π2係覆蓋 於該晶片110之一表面113上並具有複數個開孔114， 以顯露該些銲墊111。 接著，如第2B圖所示’包含上述複數個凸塊下金屬 層120的金屬層係整面覆蓋於該晶片110之保護層U2 上’並覆蓋該些薛墊111。該凸塊下金屬層12〇係可包 含上述之結合層121與導電層122，且可藉由已知半導 體製程之沉積技術形成，例如濺鍍（sputtering)。因此， 尚未界定面積尺寸之凸塊下金屬層120係覆蓋整面的保 護層112以及暴露出之銲墊111。 之後’如第2C圖所示，形成一圖案化遮罩，例如一 光阻層10形成於該金屬層之外表面。一般而言，該光阻 〇 層1〇可選自液態光阻或乾膜光阻，接著進行一曝光顯影 製程’形成複數個開孔11 4 ’以相對應地曝露出各銲塾 111上方預定形成該些凸塊下金屬層120之位置。該些 開孔114係提供作為銀凸塊130與凸塊下金屬層12〇之 形成區域。在本實施例中，該些開孔114係大於對應位 置之該些銲墊111。或者，不受限地，該些開孔114亦 可形成於該些銲墊111之外，並配合RDL(重配置線路層） 製程中因接點配置設計上的需要而需變更接點的位置。 接著，如第2D圖所示，在該些開孔114内以電錄 13 201044527 (electroplating)方式形成複數個銀凸塊13〇。該些銀凸塊 130係接合於包含該些凸塊下金屬層12〇之金屬層上。 接著，如第2E圖所示，移除該光阻層1〇，以使得該 金屬層中不包含該些凸塊下金屬層12〇的部位為外露: 接著，如第2F圖所示，可以蝕刻方式移除部分之該結合 層121以及該導電層122,以形成該些凸塊下金屬層 120,其尺寸係可由該些銀凸塊13〇的底部覆蓋面積所界 Q 疋’並形成上述之側緣123。較佳地’該些凸塊下金屬 層120之側緣123係可相對凹入於該些銀凸塊13〇之該 些柱側壁132，以便於該抗潛變層14〇之外凸形成並使 該些缺口環150之形狀與作用更加明顯（如第丨圖所示）。 最後’如第1圖所示，形成一抗潛變層14〇來包覆該 些銀凸塊130之頂面131與柱侧壁132，並使該抗潛變 層1 40僅覆蓋至該濕潤層122之侧緣而顯露出該結合層 1 2 1之側緣。該抗潛變層丨4 〇可藉由置換金、電鍍或化 〇 學鑛方法形成。利用該抗潛變層140包覆該些銀凸塊 130，能避免該些銀凸塊13〇產生潛變現象。 具體而言，如第3A至3C圖所示，該些銀凸塊130 之外形係可選自方柱體、圓柱體以及長條形體之其中之 一。但不受限制地，亦可為各種形狀之多角柱體。每一 銀凸塊 130、130’、130” 係具有一頂面 131、131，、131” 以及一柱側壁132、132，、132”。較佳地，該些銀凸塊 130开〉狀儀為正四面體結構（tetrag〇nai)’即四方體之上 下表面與側面垂直，具有一定穩定性，可達到耐潛變性 14 201044527 能之提高。該些頂面13 1、13 Γ、1 3 1，，與對應之柱側壁 132、132’、132”之間係為有角度彎折。 Ο ❹ 請參閱第4圖所示’為該具覆膜式金屬凸塊之晶片結 構100運用於一半導體覆晶裝置之截面示意圖。該具覆 膜式金屬凸塊之晶片結構i 00係覆晶接合至一基板2〇， 具有縮短的電傳遞路徑，以提高晶片之效能。在本實施 例中，該半導體覆晶裝置主要包含如前所述之具覆膜式 金屬凸塊之晶片結構1〇〇以及該基板2〇，其中該基板2〇 之一表面21係設有複數個連接墊22，該基板2〇係可為 一種玻璃基板或可為高密度雙面導通之多層印刷電路 板，内部形成有導電跡線（eonductive trace)。該些銀凸 塊130係經由該抗潛變層14〇電性連接至該基板2〇之該 些連接墊22。即該抗潛變層14〇係可壓焊接合至該些連 接墊22 ’便使得該晶片i丨〇與該基板2〇達到電性連接。 該些銀凸塊130經由該抗潛變層14〇電性連接至該基板 20之該些連接墊22的接合方法係可選用超音波鍵合或 熱壓合。即使在间溫下，覆蓋該些柱侧壁丨3 2的該抗潛 變層可保護該銀凸& 13〇不會產生受到應力的潛 變。較佳地’該基板20係可為—玻璃基板，當該具覆膜 式金屬凸塊之晶片結構100在覆晶接合於該基板2〇之 後，可由該基板20的另一表面（相對於該表面21之相反 表面）透過該基板20目視或光學檢測覆蓋在該些銀凸塊 130表面的該抗潛變層140是否有崩裂的現象。 更細部而$ ’如第1辦4菌 弟興4圖所示，該半導體覆晶裝置 15 201044527 可另包含有一底部填充膠30(underfill)，其係形成於該 具覆膜式金屬凸塊之晶片結構1 00與該基板20之間，以 包覆位在該些銀凸塊130之柱侧壁132之該抗潛變層 140並填入該些缺口環150。該底部填充膠3〇係可以先 點塗畫在該晶片11 〇之一側邊或兩侧邊，並利用毛細現 象填滿上述覆晶縫隙，再予以固化處理，用以保護該些 銀凸塊130與該抗潛變層140。由於該底部填充膠3〇係 Q 可填入至該具覆膜式金屬凸塊之晶片結構100之缺口環 150 ’藉以增加該底部填充膠30對該些銀凸塊13〇之固 著效果。因此’能增加該具覆膜式金屬凸塊之晶片結構 100與該基板20之間的結合力，進而提升高頻訊號的傳 輸品質。 請參閱第5圖所示，為該具覆膜式金屬凸塊之晶片結 構100運用於另一半導體覆晶裝置之截面示意圖。在本 實施例中，該具覆膜式金屬凸塊之晶片結構1〇〇可藉由 〇 異方性導電膠（Anis〇tr〇pic Conductive Paste，ACP)40 與該基板20電性連接。該異方性導電膠係可藉由印 刷、黏貼等方式先形成於該基板2〇上，再使該具覆膜式 金屬凸塊之晶片結構1〇〇覆晶接合至該基板2〇。該異方 性導電膠40係包含複數個導電粒子41，部分之該些導 電粒子41係電性接觸該抗潛變層140與該些連接墊22 而達成縱向導電之功效8該些導電粒子41係為等球徑， 其直徑大小可是介於2 # m(微米）至3 /z m(微米）之間，該 些導電粒子41係均勻分散在該異方性導電膠4〇内，以 16 201044527 達到縱向的異方性導電。即該抗潛變層140與該些連接 塾22之間係被部分之該些導電粒子41電性接觸，以使 該基板20與該晶片110達到縱向的電性連通，亦不會有 直接焊接導致金屬擴散（metal diffusion)的問題，也能減 少覆晶接合的應力產生。該異方性導電膠40可更填入至 該具覆膜式金屬凸塊之晶片結構100之缺口環150。 總而言之’本發明之具覆膜式金屬凸塊之晶片結構利 〇用抗潛變層包覆銀凸塊’能避免銀凸塊之潛變發生，故 s 下不會產生覆晶間隙變化的問題，可符合無錯 化、间可靠度與低成本之凸塊要求。因此，銀凸塊可具 體應用於半導體晶片上的柱狀凸塊。更由於缺口環之形 成，以使抗潛變層不會接觸至保護層，可達成銀凸塊高 密X排列，以增加晶片與基板間的結合力，進而提升高 頻訊號的傳輸品質。 X上所述，僅是本發明的較佳實施例而已並非對本 G發月作任何形式上的限制，雖然本發明已以較佳實施例 揭露如上’然、而並非用以限定本發明，任何熟悉本項技 術者在不脫離本發明之技術範圍内，所作的任何簡單 u改冑效性變化與修飾，均仍屬於本發明的技術範圍 内。 L園式簡單說明】 第圖&據本發明之一具體實施例的一種具覆膜式 屬凸塊之晶片結構之局部截面示意圖。 2F圖.依據本發明之一具體實施例的具覆膜 17 201044527 金屬凸塊之晶片結構在製程中元件的截面示意 囷。 第 3 A $ 〇 ^ 圖：依據本發明之一具體實施例的具覆膜式 金屬凸塊之晶片結構之銀凸塊不同變化例之立 體示意圖。 第4圖·依據本發明之一具體實施例的一種具覆膜式金 屬凸塊之晶片結構運用於一半導體覆晶襞置之 截面示意圖。 第5圖.依據本發明之一具體實施例的一種具覆膜式金 屬凸塊之晶片結構運用於另一半導體覆晶裝置 之截面示意圖。 【主要元件符號說明】 10 光阻層 11 開孔 20 基板 21 表面 22 連接墊 30 底部填充膠 40 異方性導電膠 41 導電粒子 100 具覆膜式金屬 凸塊之晶片結構 110 晶片 111 銲墊 112 保護層 113 表面 114 開孔 120 凸塊下金屬層 121 結合層 122 導電層 123 側緣 130 銀凸塊 131 頂面 132 柱側壁 1305 銀凸塊 131， 頂面 132, 柱側壁 13 0” 銀凸塊 131” 頂面 132” 柱側壁 18 201044527 140抗潛變層 1 5 0缺口環G m) to 25 in m (micron). In this embodiment, as shown in Figures 3A to 3C, the outer shape of the silver bumps 130 may be selected from one of a cylinder, a square cylinder, and a long strip. The material of the silver bumps 13A may be selected from sterling silver or a silver alloy containing a silver content of not less than 8 Å by weight. Preferably, the silver bumps 13 〇 have a silver content of not less than 99% by weight and have high purity, are suitable for mass formation by electroplating, and have the effect of homogenizing in the money-making process, and are not dispersed by components. Uneven defects lead to variations in the hardness of the bumps. Therefore, the silver bumps 130 have the same hardness as the conventional gold bumps but lower than the hardness of the copper bumps and have good J_ conductivity and metal extensibility. Therefore, the cost of these silver blocks (9) has a lower I than that of the conventional gold bumps, and meets the requirements of no error, and can replace the conventional gold without affecting the performance and quality of the bumps. The bumps are better than the conventional copper bumps, and there is no problem of bottom breakage of conventional copper bumps. Referring to FIG. 1 , the anti-situ layer 14 is coated on the top surface 131 of the silver bumps 130 and the pillar sidewalls 132 , and the bumps are formed by the anti-situ layer 14 . The side under the block _ 12 、, the edge 123 forms a plurality of 10,044,427 notched rings 150 so that the slabs are not slid into the protective layer U2. The anti-potential layer ι4〇~厗 system may be between 〇.03 μm (micrometer) and 3 μm (micrometer), and the anti-dense layer 140 is the height of the two silver bumps 130. The four layers covered by a surface-covered cage whose thickness is controlled to be less than + 卞 of the height of the silver bumps do not affect the physical properties such as the overall structure and hardness of the silver bumps 130 Ο . In the present embodiment, the anti-dense layer 140 may be exposed and have anti-oxidation and high-conductivity characteristics selected from gold (Au) or palladium (pd). Preferably, the anti-migration layer " lanthanide system is selected from one of displacement gold and reduced AU, so the anti-potential treatment time is short, and the formation thickness can be controlled at 1 Within m (micrometers) (about tens to hundreds of angstroms), the occurrence of creep of the silver bumps 130 can be avoided, and the size of the silver bumps 130 is not made laterally large. It does not produce a change in the flip-chip gap, and has the effect of lower cost and thinner thickness. In particular, the hardness of the anti-potential layer may not be close to or close to the hardness of the silver bumps 130, and the bump structure reinforcement function is not required, so the thickness of the anti-situ layer 14〇 is increased and decreased. Does not affect and change the structural strength of the overall bump. In addition, as shown in FIG. 1 , the width of the notched rings 15 〇 may not be greater than the thickness of the under-bump metal layers 120 such that the anti-potential layer ι4 〇疋 completely covers the silver bumps 13〇. Therefore, the silver bumps 13 will not be revealed: Bu Ba atmospheric ring brother directly contact. In this embodiment, since the silver bumps 130 are in a full cladding state, the anti-latent layer is generated at the bottom of the pillar sidewalls 132 of the silver bumps 13 after the flip chip bonding. 0's cracking' to enhance the anti-potential effect of the anti-situ layer 14〇, 201044527 effectively reduce the occurrence of the latent changes of the silver bumps 130. In detail, the anti-situ layer 140 can partially cover the The side edge 123 of the lower under bump metal layer 12 is, for example, 'the anti-dip layer 可 can cover the side edge of the conductive layer 122 to expose the side edge of the bonding layer i 2 。. Therefore, the anti-dip layer 140 is not brought into contact with the protective layer 112 of the wafer 11 to achieve high-density arrangement of the bumps and can increase the bonding force between the wafer and the substrate, thereby improving the transmission quality of the high-frequency signal. . Further, a buffer space can be generated by the notch ring 150, and the anti-dive layer 140 can be controlled to completely cover the surface of the silver bumps 130 without extending to the protective layer 11 2 to reduce The problem of short circuit between the bumps can prevent the silver bumps 130 from being broken from the bottom of the silver bumps 13 by the deformation of the silver bumps 130, which affects the overall electrical connection effect. In general, when a metal material is subjected to a stress below the elastic limit at a normal temperature for a long period of time, it does not easily change. However, in a high temperature environment, when subjected to stress lower than the elastic limit, the metal material gradually deforms with time. This phenomenon is called creep. Since the latent phenomenon of the silver bumps 130 is higher than that of the gold bumps and the copper bumps, the present invention must utilize the film coating effect of the anti-situ layer 14 on the surface of the silver bumps 130, especially coating. The pillar sidewalls 132' of the silver bumps 130 are prevented from undergoing a latent deformation under the action of long-term stress to cause a slow deformation phenomenon to prevent the silver bumps 13 from being laterally fattened. To maintain the flip-chip gap and achieve effective bonding. Referring to Figures 2A through 2F, the present invention further illustrates the method of fabricating the wafer structure 100 with a clad metal bump to demonstrate the efficacy of the present invention. First, as shown in FIG. 2A, a wafer 11 is provided. The plurality of wafers 110 may be formed in a wafer in this step. The wafer 11 has a plurality of pads 111 and a protective layer 112. The protective layer The Π 2 layer covers a surface 113 of the wafer 110 and has a plurality of openings 114 to expose the pads 111. Next, as shown in Fig. 2B, the metal layer including the plurality of under bump metal layers 120 covers the entire surface of the protective layer U2 of the wafer 110 and covers the plurality of pads 111. The under bump metal layer 12 may comprise the bonding layer 121 and the conductive layer 122 described above, and may be formed by a deposition technique known in the art of semiconductor processes, such as sputtering. Therefore, the under bump metal layer 120, which has not yet defined the area size, covers the entire protective layer 112 and the exposed pads 111. Thereafter, as shown in Fig. 2C, a patterned mask is formed, for example, a photoresist layer 10 is formed on the outer surface of the metal layer. In general, the photoresist layer 1 can be selected from a liquid photoresist or a dry film photoresist, and then an exposure and development process is performed to form a plurality of openings 11 4 to correspondingly expose the pads 111 above. The locations of the under bump metal layers 120 are formed. The openings 114 are provided as regions in which the silver bumps 130 and the under bump metal layers 12 are formed. In the embodiment, the openings 114 are larger than the pads 111 of the corresponding positions. Alternatively, without limitation, the openings 114 may be formed outside the pads 111 and need to change the position of the contacts in accordance with the design of the contact arrangement in the RDL (Reconfigured Circuit Layer) process. . Next, as shown in FIG. 2D, a plurality of silver bumps 13A are formed in the openings 114 by means of an electric recording 13 201044527 (electroplating). The silver bumps 130 are bonded to the metal layer including the under bump metal layers 12A. Next, as shown in FIG. 2E, the photoresist layer 1 is removed such that the portion of the metal layer that does not include the under bump metal layer 12 is exposed: then, as shown in FIG. 2F, The bonding layer 121 and the conductive layer 122 are removed by etching to form the under bump metal layer 120, and the size may be defined by the bottom coverage area of the silver bumps 13〇 and form the above Side edge 123. Preferably, the side edges 123 of the under bump metal layer 120 are relatively recessed to the pillar sidewalls 132 of the silver bumps 13 , so that the anti-dive layer 14 〇 is convexly formed and The shape and effect of the notched rings 150 are made more apparent (as shown in the figure). Finally, as shown in FIG. 1, an anti-substitute layer 14 is formed to cover the top surface 131 of the silver bumps 130 and the pillar sidewalls 132, and the anti-migration layer 140 is only covered to the wet The side edges of the layer 122 reveal the side edges of the bonding layer 112. The anti-situ layer 丨4 形成 can be formed by displacement gold, electroplating or chemical conversion. By coating the silver bumps 130 with the anti-situ layer 140, the creeping phenomenon of the silver bumps 13 can be avoided. Specifically, as shown in Figs. 3A to 3C, the outer shape of the silver bumps 130 may be selected from one of a square cylinder, a cylinder, and an elongated body. However, without limitation, it may be a polygonal cylinder of various shapes. Each of the silver bumps 130, 130', 130" has a top surface 131, 131, 131" and a pillar sidewall 132, 132, 132". Preferably, the silver bumps 130 are open. It is a tetrahedral structure (tetrag〇nai), that is, the lower surface of the tetragonal body is perpendicular to the side surface, and has certain stability, which can achieve the improvement of the latent resistance. The top surface 13 1 , 13 Γ, 1 3 1 , and the corresponding column sidewalls 132, 132', 132" are angularly bent. Ο ❹ Referring to FIG. 4, a schematic cross-sectional view of the wafer structure 100 with the coated metal bumps applied to a semiconductor flip chip device is shown. The wafer structure i 00 with a clad metal bump is flip-chip bonded to a substrate 2 〇 with a shortened electrical transfer path to improve the performance of the wafer. In this embodiment, the semiconductor flip chip device mainly includes the wafer structure 1 覆 with the metal bumps as described above and the substrate 2 〇, wherein one surface 21 of the substrate 2 is provided with a plurality of The connection pad 22, the substrate 2 can be a glass substrate or a multilayer printed circuit board which can be high-density double-sided conduction, and an eonductive trace is formed inside. The silver bumps 130 are electrically connected to the connection pads 22 of the substrate 2 via the anti-migration layer 14 . That is, the anti-situ layer 14 is pressure-bonded to the connection pads 22' to electrically connect the wafers to the substrate 2'. The bonding method of the silver bumps 130 electrically connected to the connection pads 22 of the substrate 20 via the anti-dive layer 14 may be ultrasonic bonding or thermocompression bonding. Even at inter-temperatures, the anti-dense layer covering the side walls of the column 丨3 2 protects the silver bumps from occurring without stressing potential. Preferably, the substrate 20 can be a glass substrate. When the wafer structure 100 with a clad metal bump is bonded to the substrate 2, the other surface of the substrate 20 can be The opposite surface of the surface 21 is visually or optically detected through the substrate 20 to detect whether the anti-dive layer 140 covering the surface of the silver bumps 130 is cracked. Further, as shown in FIG. 1 , the semiconductor flip chip device 15 201044527 may further include an underfill 30 formed on the film-coated metal bump. Between the wafer structure 100 and the substrate 20, the anti-migration layer 140 is disposed on the pillar sidewalls 132 of the silver bumps 130 and filled into the notch rings 150. The underfill 3 can be firstly painted on one side or both sides of the wafer 11 and filled with the chipping gap by capillary phenomenon, and then cured to protect the silver bumps. 130 with the anti-stationary layer 140. Since the underfill 3 can be filled into the notched ring 150' of the wafer structure 100 having the clad-type metal bumps, the fixing effect of the underfill 30 on the silver bumps 13 is increased. Therefore, the bonding force between the wafer structure 100 having the film-type metal bumps and the substrate 20 can be increased, thereby improving the transmission quality of the high-frequency signal. Referring to Fig. 5, a schematic cross-sectional view of the wafer structure 100 with a clad metal bump applied to another semiconductor flip chip device is shown. In this embodiment, the wafer structure 1A with a clad metal bump can be electrically connected to the substrate 20 by an aisotropic conductive paste (ACP) 40. The anisotropic conductive adhesive can be formed on the substrate 2 by printing, pasting, or the like, and the wafer structure with the metal bump can be flip-chip bonded to the substrate 2 . The anisotropic conductive adhesive 40 includes a plurality of conductive particles 41, and some of the conductive particles 41 electrically contact the anti-situ layer 140 and the connection pads 22 to achieve longitudinal conduction. 8 The conductive particles 41 The diameter of the ball is between 2 # m (micrometers) and 3 /zm (micrometers), and the conductive particles 41 are uniformly dispersed in the anisotropic conductive adhesive 4, to 16 201044527 Achieving longitudinal anisotropy conduction. That is, the anti-situ layer 140 is electrically contacted with the conductive particles 41 between the connecting pads 22, so that the substrate 20 and the wafer 110 are electrically connected in a longitudinal direction, and there is no direct soldering. The problem of metal diffusion also reduces the stress generation of flip chip bonding. The anisotropic conductive paste 40 can be further filled into the notch ring 150 of the wafer structure 100 having the film-type metal bumps. In summary, the wafer structure of the coated metal bump of the present invention can be used to cover the silver bumps with the anti-situ layer, so that the latent change of the silver bumps can be avoided, so that the problem of the change of the flip-chip gap does not occur under s. It can meet the requirements of bumps without error, reliability and low cost. Therefore, the silver bumps can be specifically applied to the columnar bumps on the semiconductor wafer. Moreover, due to the formation of the notch ring, the anti-dense layer does not contact the protective layer, and the high-density X arrangement of the silver bumps can be achieved to increase the bonding force between the wafer and the substrate, thereby improving the transmission quality of the high-frequency signal. The above description of the preferred embodiment of the present invention is not intended to limit the scope of the present invention, and the present invention has been disclosed in the preferred embodiments as described above, and is not intended to limit the present invention. It is still within the technical scope of the present invention to make any simple changes and modifications made by those skilled in the art without departing from the technical scope of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a partial cross-sectional view showing a wafer structure having a film-type bump according to an embodiment of the present invention. 2F. A film according to an embodiment of the present invention. 17 201044527 A wafer structure of a metal bump is schematically illustrated in a cross section of a component in a process. 3A A 〇 ^ Figure: A schematic view of a different variation of a silver bump of a wafer structure having a film-type metal bump according to an embodiment of the present invention. Figure 4 is a cross-sectional view showing a wafer structure having a film-type metal bump applied to a semiconductor flip chip device in accordance with an embodiment of the present invention. Fig. 5 is a cross-sectional view showing a wafer structure having a film-type metal bump applied to another semiconductor flip chip device in accordance with an embodiment of the present invention. [Main component symbol description] 10 Photoresist layer 11 Opening 20 Substrate 21 Surface 22 Connection pad 30 Underfill 40 Anisotropic conductive adhesive 41 Conductive particles 100 Wafer-type metal bump wafer structure 110 Wafer 111 Solder pad 112 Protective layer 113 surface 114 opening 120 under bump metal layer 121 bonding layer 122 conductive layer 123 side edge 130 silver bump 131 top surface 132 pillar sidewall 1305 silver bump 131, top surface 132, pillar sidewall 13 0" silver bump 131" top surface 132" column side wall 18 201044527 140 anti-substitute layer 1 50 gap ring
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