200837918 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種封裝基板表面結構及其製法，尤指 一種特別適用於覆晶封裝之封裝基板表面結構及其製法。 5 【先前技術】 隨著電子產業的蓬勃發展，電子產品亦逐漸進入多功 能、高性能的研發方向。為滿足半導體封裝件高積集度 (integration)以及微型化（miniaturization)的封裝要求，提供 10 多數主被動元件及線路連接之電路板，亦逐漸由雙層板演 變成多層板，以使在有限的空間下，藉由層間連接技術 (interlayer connection)擴大電路板上可利用的佈線面積而 配合高電子密度之積體電路（integrated circuit)需求。 一般半導體裝置之製程，首先係由晶片載板製造業者 15 生產適用於該半導體裝置之晶片載板，如基板或導線架。 之後再將該些晶片載板交由半導體封裝業者進行置晶、_打 線、封膠、以及植球等封裝製程，又一般半導體封裝是將 半導體晶片背面黏貼於封裝基板頂面進行打線接合（wke bonding)，或者將半導體晶片之主動面以覆晶接合（Flip chip) 20 方式與封裝基板接合，再於基板之背面植以錫球以供與另 一電路板進行電性連接。 上述覆晶接合封裝方式中，當半導體封裝基板表面結 構線寬及線距縮短時，因接點（joint)強度亦隨著接點尺寸而 5 200837918 =小’所以接點強度不足以承受晶片與基板間的剪應力 (S earStress)，而產生接點斷裂的現象將更加顯著。^ 習知的封裝基板表面結構及製法，請參考圖丨。 5 10 15 20 =I其包括—封裝基板U ’其表面上具有-線路層14, 文路層14具有複數連接塾i4i。該封裝基板上覆蓋一防焊 € 5 ’遠防焊層15具有複數開孔15〇以顯露出該些連接塾 141一。於5亥防焊層15表面先後形成一導電層似—阻層（未 圖不於核層利用曝光顯影方式形成大於該些防焊層15 開孔150之複數阻層開孔，再藉由該導電層16以電鍍方式在 該些阻層開孔内形成複數τ型金屬㈣，該些金屬柱Η的材 料可為銅、錫或鎳/金等等。接著，以電鍍形成焊接材料後 f除該阻層及其下之導電層’或者於移除該阻層及其下之 導電層後再於該些金屬柱17表面經由印刷形成焊接材料， 後經迴焊形成複數預焊料凸塊丨9 (presQlder以啤）。最後以 該些預焊料凸塊19與一晶片進行接合。 上述製程所得之封裝基板表面結構雖可提供與晶片接 合以達到電性連接的目的，然而，因該τ型金屬柱17與預焊 料凸塊19之界面170係為平面式的接觸，一旦受應力形成裂 紋則该裂紋極易延著該Τ型金屬柱17與預焊料凸塊19之界 面傳播，另外，此種結構中該導電層16處因結構強度較弱 亦谷易受應力而發生裂紋，前述兩者皆會使整體之電性連 接結構產生劣化，亦即接點斷裂的現象。在半導體封裝基 板表面結構線寬及線距之縮短之趨勢下，τ型金屬柱17與預 焊料凸塊19或連接墊HI與τ型金屬柱π的接觸面積勢必變 6 200837918 ,ιΐ連產生接點斷裂的現象更加顯著’會造成電 【發明内容】 5 10 15 20 λ极：：上述缺點二本發明之主要目的係在提供-種封裝 ^列、面結構，藉由改變該電性連接結構之幾何形狀， 傳播，強化基板電性連接結構的可靠度。此結構 晶封裝時，因連接晶片舆基板的谭料凸塊承受剪 應力而發生接點斷裂的現象。 雙法。H之3目的係在提供—種封裝基板表面結構的 狀，衣法使卜料凸塊形成能抑制裂紋傳播之幾何形 成《士Si加、⑺口強度’此製法復因其減少製程步驟，其所 、、、口 "、、須於金屬柱與連接墊間配置帝 _ 減少其結構處發生斷裂，而使產品良率上 為達成上述目的，本發明提供—種封裝基板表面結 ?a 基板，其表面上具有-線路層，其"線 4=複數並於該基板表面及該線路層間具有 接墊二二以基=並對 ^ 鱼屬柱，其係配置於該此阶、he :於该叫層表面並形成蕈狀頭部，且該蕈狀頭部 邛份該金屬柱亦顯露出來。 的 該些連上接述塾之結構中，該些防咖 7 200837918 本發明更提供一種封裝基板表面結構之製法，其步驟 包括··提供一基板，其表面具有一導電層，該導電層上覆 盍有一第一阻層，且該第一阻層形成有開口區以顯露部份 該導電層，並於該開口區内所顯露之該導電層上電鍍形成 5有一線路層，該線路層具有複數連接墊；形成一第二阻層 於該基板表面，且該第二阻層形成有複數開孔以顯露該些 連接墊，以電鍍方式於該些開孔各形成一金屬柱，該金屬 柱係咼於該第二阻層表面，且延伸出該開孔外並形成蕈狀 頭部；移除該基板表面之該第二阻層、該第一阻層及被該 10第一阻層覆盍之該導電層；形成一防焊層於該基板表面·， 以及移除部份該防焊層厚度至顯露出該金屬柱之蕈狀頭 部，及顯露出該蕈狀頭部以下的部份該金屬柱，以完成本 發明之封裝基板表面結構。 上述之製法中，該第二阻層開孔之尺寸係小於或等於 15 該些連接墊。 本發明中，此種在表面具有蕈狀之金屬柱的封裝基 板，乃改變金屬柱與預焊料凸塊所構成之電性連接結構的 幾何形狀，從防焊層所顯露出該金屬柱之孽狀頭部，可抑 制直線裂紋的發生，且該輩狀頭部及其以下的部份該金屬 20柱，提供與預谭料凸塊間更大的接合表面積，及賓除電性 連接塾與金屬柱間結構㈣的導電層，而在可#度測試 時，接點之機械強度、抗疲勞伽㈣性質優於習知技術， 可以有效抑制接點斷裂，因此本發明可提高基板電性連接 8 200837918 結構的可靠度，適用於縮短線寬及線距之覆晶封裝基板表 【實施方式】 以下係藉由特定的具體實施例說明本發明之實施方 式’熟習此技藝之人士可由本說明書所揭示之内容輕易地 了解本發明之其他優點與功效。本發明亦可藉由其他不同 的具體實施例加以施行或應用，核明書中的各項細節亦 10 15200837918 IX. Description of the Invention: [Technical Field] The present invention relates to a surface structure of a package substrate and a method for fabricating the same, and more particularly to a surface structure of a package substrate which is particularly suitable for flip chip packaging and a method for fabricating the same. 5 [Prior Art] With the rapid development of the electronics industry, electronic products have gradually entered the direction of multi-functional and high-performance research and development. In order to meet the high integration and miniaturization packaging requirements of semiconductor packages, 10 most active and passive components and circuit-connected circuit boards are gradually evolved from double-layer boards to multi-layer boards to make them limited. In the space, the wiring area available on the circuit board is expanded by an interlayer connection to meet the demand for an integrated circuit of high electron density. In the general semiconductor device process, the wafer carrier manufacturer 15 first produces a wafer carrier, such as a substrate or lead frame, suitable for the semiconductor device. Then, the wafer carrier boards are transferred to a semiconductor package manufacturer for packaging processes such as crystallization, wire bonding, encapsulation, and ball implantation. In general, the semiconductor package is adhered to the top surface of the package substrate for wire bonding (wke Bonding, or bonding the active surface of the semiconductor wafer to the package substrate in a Flip chip 20 manner, and then soldering the solder ball on the back surface of the substrate for electrical connection with another circuit board. In the above flip chip bonding package method, when the surface line width and the line pitch of the semiconductor package substrate are shortened, since the joint strength is also small with the contact size, 5 200837918 = small 'the contact strength is insufficient to withstand the wafer and The shear stress between the substrates (S earStress), and the phenomenon of joint breakage will be more significant. ^ For the surface structure and manufacturing method of the packaged substrate, please refer to Figure 丨. 5 10 15 20 = I includes - the package substrate U' has a - line layer 14 on its surface, and the track layer 14 has a plurality of connections 塾i4i. The package substrate is covered with a solder-proof electrode. The 5 5' remote solder mask 15 has a plurality of openings 15 显 to expose the ports 141 141. A conductive layer-like resist layer is formed on the surface of the 5-well solder mask 15 (the core layer is formed by exposure and development to form a plurality of barrier openings larger than the openings 150 of the solder resist layers 15 The conductive layer 16 forms a plurality of τ-type metals (4) in the openings of the resist layers by electroplating. The materials of the metal pillars may be copper, tin or nickel/gold, etc. Then, after forming a solder material by electroplating, f is removed. The resist layer and the underlying conductive layer ′ or after removing the resist layer and the underlying conductive layer, forming a solder material on the surface of the metal pillars 17 via printing, and then reflowing to form a plurality of pre-solder bumps 丨9 (presQlder is beer). Finally, the pre-solder bumps 19 are bonded to a wafer. The surface structure of the package substrate obtained by the above process can provide bonding with the wafer for electrical connection, however, due to the τ-type metal The interface 170 between the pillar 17 and the pre-solder bump 19 is in a planar contact, and the crack is highly likely to propagate along the interface between the 金属-type metal pillar 17 and the pre-solder bump 19 once the stress is formed by the stress. The structure of the conductive layer 16 is strong in structure It is weak and the valley is susceptible to stress and cracks, both of which cause deterioration of the overall electrical connection structure, that is, the phenomenon of joint breakage. Under the trend of shortening the line width and line pitch of the surface of the semiconductor package substrate The contact area between the τ-type metal pillar 17 and the pre-solder bump 19 or the connection pad HI and the τ-type metal pillar π is bound to change 6 200837918, and the phenomenon that the joint breakage occurs in the ΐ ΐ 更加 更加 ' ' ' ' ' ' ' 5 5 5 5 5 5 15 20 λ pole:: The above disadvantages 2 The main purpose of the present invention is to provide a package structure and a surface structure, and to improve the reliability of the electrical connection structure of the substrate by changing the geometry of the electrical connection structure and propagating. In the case of this crystal package, the junction bump is caused by the tantalum bump connecting the wafer and the substrate. The double method is to provide the surface structure of the package substrate. The formation of the bumps can inhibit the geometrical formation of crack propagation. "Shi Si plus, (7) port strength" is reduced by the process of reducing the process, and the valve, the port, and the connection between the metal column and the connection pad. _ reducing the occurrence of fracture at the structure, so that the product yield to achieve the above purpose, the present invention provides a substrate substrate surface a substrate, which has a - line layer on the surface, and its line 4 = plural and Between the surface of the substrate and the circuit layer, there is a pad of two bases and a column of fish, which is disposed at the step, he: on the surface of the layer and forms a dome-shaped head, and the head is 蕈The metal column is also exposed. Among the structures connected to the cymbal, the anti-coffee 7 200837918 The present invention further provides a method for fabricating the surface structure of the package substrate, the steps comprising: providing a substrate having a surface thereon a conductive layer, the conductive layer is covered with a first resistive layer, and the first resistive layer is formed with an opening region to expose a portion of the conductive layer, and is plated on the conductive layer exposed in the opening region. a circuit layer having a plurality of connection pads; forming a second barrier layer on the surface of the substrate; and the second barrier layer is formed with a plurality of openings to expose the connection pads, and electroplating is performed on the openings Forming a metal column, the metal Hanging on the surface of the second resist layer and extending outside the opening to form a dome-shaped head; removing the second resist layer on the surface of the substrate, the first resist layer, and being covered by the first resist layer a conductive layer; forming a solder resist layer on the surface of the substrate, and removing a portion of the solder resist layer to reveal a dome-shaped head of the metal pillar, and revealing a portion below the braided head The metal column is divided to complete the surface structure of the package substrate of the present invention. In the above method, the size of the second resistive opening is less than or equal to 15 of the connecting pads. In the present invention, the package substrate having the metal pillars having a meandering shape on the surface changes the geometry of the electrical connection structure formed by the metal pillars and the pre-solder bumps, and the metal pillars are exposed from the solder resist layer. The head can suppress the occurrence of linear cracks, and the metal head of the head and the lower part of the head provides a larger joint surface area with the pre-tank bumps, and the guest-removing connection between the metal and the metal The conductive layer of the inter-column structure (4), and the mechanical strength and anti-fatigue gamma (four) properties of the joint are better than the conventional techniques, and the joint breakage can be effectively suppressed, so that the present invention can improve the electrical connection of the substrate. 200837918 The reliability of the structure is applicable to the flip chip package substrate which shortens the line width and the line spacing. [Embodiment] Hereinafter, embodiments of the present invention will be described by way of specific embodiments. Those skilled in the art can disclose the present disclosure. The contents are readily understood to provide additional advantages and benefits of the present invention. The present invention can also be implemented or applied by other different embodiments, and the details in the certificate are also 10 15
20 可基於不同觀點與應用，在不悖離本發明之精神下進行夂 種修飾與變更。 口 請參考圖2A〜2G，此為製作本實施例封裝基板表面結 構之製作流程示意圖。 首先，如圖2A所示，提供一基板21，該基板以表面具 有一導電層22。該導電層22之材料可選用自銅、錫、鎳、 鉻、鈦、銅/鉻合金、以及錫/鉛合金所組成群組其中之一者， 本實施例使用銅作為此導電層22之材料。 於該導電層22上，經由曝光顯影的方式，形成具有開 口區230之第一阻層23，再於第一阻層23之開口區23〇内， 經由電鍍方式形成一線路層24，該線路層24具有複數連接 墊241。再次利用曝光顯影的方式，形成具複數開孔之 第二阻層25。該第一阻層23及第二阻層25可為液態光阻或 乾膜。此外第二阻層25之開孔250對應於該連接墊241，且 本實施例中該開孔250略小於該連接墊241。 9 200837918 接著，如圖2B所示，於該開孔25〇内利用電鍍方式形成 一金屬柱27，該金屬柱27之材料可選用自錫、銀、銅、 金、鉍、銻、鋅、鎳、錘、鎂、銦以及鎵之其中 一者，本實訑例使用銅作為該金屬柱27之材料。在電鍍形 5成該金屬柱27時，當金屬柱W超出第二阻層25之表面高度 後’電鍛便會等向性（isotropic)往周圍方向發展，因此該金 屬柱27可產生有蕈狀頭部27〇。 然後，見圖2C所示，將第二阻層25、第一阻層23及其 所覆蓋之部分該導電層22移除，以顯露出該金屬柱W、該 10 連接墊241以及該基板21表面。 接著，如圖2D所示，為了保護該基板21上的線路層24 «接塾241免於物理或化學性的傷害，全面性的形成一防 焊層28，一般使用綠漆或黑漆作為此防焊層28。本實施例 使用綠漆作為此防焊層28。 15 、、”，如圖沈所示，移除部份該防焊層28，使該防焊層28 :咸少厚度直到顯露該金屬柱27之蕈狀頭部謂，及該輩狀頭 4270以下的部份該金屬柱271，以得到本發明之封 表面結構。 之後，見圖2F所示，在該金屬柱27所顯露出之蕈狀 2〇部27〇及其下的部份該金屬柱271表面形成一金屬接著層 29。此金屬接著層29的材料，較佳可選自錫、銀、鎳、金、 ΪΠ金、鎳7金合金、騰合金、與雜/金合金所組成 之—者，本實施例則使用鎳他合金，形成該金屬 运之方式係可為電鍍、物理沉積及化學沉積之其中一 10 200837918 者，其中，該物理沉積方式係為濺鍍及蒸鍍之其中一 該化學沉積係為無電電鍍。 家後，為形成作為封裝基板與晶片兩者間之電性連 點，如圖2G所示，在該金屬柱27蕈狀頭部27〇及其下的部份 該金屬柱271表面之金屬接著層29上，經由印刷及回焊^ 程，形成一預焊料凸塊30。t亥預焊料凸塊3〇之材料較佳^20 Modifications and variations can be made without departing from the spirit and scope of the invention. Please refer to FIG. 2A to FIG. 2G, which are schematic diagrams showing the manufacturing process of the surface structure of the package substrate of the present embodiment. First, as shown in Fig. 2A, a substrate 21 having a conductive layer 22 on its surface is provided. The material of the conductive layer 22 can be selected from the group consisting of copper, tin, nickel, chromium, titanium, copper/chromium alloy, and tin/lead alloy. This embodiment uses copper as the material of the conductive layer 22. . On the conductive layer 22, a first resist layer 23 having an open region 230 is formed through exposure and development, and a wiring layer 24 is formed by electroplating in the open region 23 of the first resist layer 23, the line Layer 24 has a plurality of connection pads 241. The second resist layer 25 having a plurality of openings is formed by exposure development again. The first resist layer 23 and the second resist layer 25 may be liquid photoresist or dry film. In addition, the opening 250 of the second resist layer 25 corresponds to the connecting pad 241, and the opening 250 is slightly smaller than the connecting pad 241 in this embodiment. 9 200837918 Next, as shown in FIG. 2B , a metal pillar 27 is formed by electroplating in the opening 25 , and the material of the metal pillar 27 can be selected from tin, silver, copper, gold, rhodium, ruthenium, zinc, nickel. One of the hammer, magnesium, indium, and gallium, copper is used as the material of the metal pillar 27. When the metal pillars 27 are plated into the metal pillars 27, when the metal pillars W exceed the surface height of the second barrier layer 25, the electric forging will develop isotropically toward the surrounding direction, so that the metal pillars 27 can be produced with flaws. The head is 27〇. Then, as shown in FIG. 2C, the second resist layer 25, the first resist layer 23 and a portion thereof covered by the conductive layer 22 are removed to expose the metal pillar W, the 10 connection pad 241, and the substrate 21. surface. Next, as shown in FIG. 2D, in order to protect the circuit layer 24 «connector 241 on the substrate 21 from physical or chemical damage, a solder mask 28 is formed in a comprehensive manner, generally using green paint or black paint. Solder mask layer 28. This embodiment uses green paint as the solder resist layer 28. 15、,”, as shown in the figure, remove part of the solder mask 28, so that the solder resist layer 28: salty thickness until the head of the metal pillar 27 is revealed, and the head 4270 The following portion of the metal post 271 is used to obtain the surface structure of the present invention. Thereafter, as shown in Fig. 2F, the metal portion 27 is exposed to the ridged portion 27 and the lower portion of the metal. A metal bonding layer 29 is formed on the surface of the pillar 271. The material of the metal bonding layer 29 is preferably selected from the group consisting of tin, silver, nickel, gold, ruthenium, nickel 7 gold alloy, alloy, and hetero/gold alloy. In this embodiment, a nickel-alloy alloy is used, and the method of forming the metal may be one of electroplating, physical deposition, and chemical deposition, wherein the physical deposition method is sputtering and evaporation. One of the chemical deposition systems is electroless plating. After the home, in order to form an electrical connection point between the package substrate and the wafer, as shown in FIG. 2G, the metal pillar 27 is shaped like a head portion 27〇 and a portion below it. a metal backing layer 29 on the surface of the metal post 271 is formed by printing and reflowing to form a 30.t Hai pre 3〇 of solder bump solder bumps preferred materials ^
10 15 20 :自銅、錫、鉛、鎳、金、銀、鉍及其組成群組合 金其中之一者，本實施例使用之材料為錫。 此外，亦可於先前圖2E所述之製程完成後，直接於該 金屬柱27蕈狀頭部27〇及其下的部份該金屬柱⑺上，經由 印刷，回焊製程，形成_預焊料凸塊3()，而不額外形成金 屬接著層29。因此’前述之預焊料凸塊3〇及金屬接著層μ 可依製程需要選擇性形成之。 本叙明设提供一封裝基板表面結構。如圖2E所示，此 封襄基板表面結構包含—基板21，其表面上具有—線路層 24,該線路層24具有複數連接墊241，該基仙表面及該線 路層24間具有_㈣層22。此外，該基㈣及該線路層^ 上覆蓋有一防焊層28,該防焊層28具有複數開孔對應該些 連接墊241又具有一金屬柱27，其係配置於該些防焊層π 開孔，對應之该連接墊241上，該金屬柱W延伸出該開孔 卜同於"亥防焊層27表面並形成簟狀頭部27〇，且該蕈狀頭 部270以下的部份該金屬柱271亦顯露出來。 本發明所揭示在表面上具有蕈狀頭部金屬柱之封裝基 板的結構及製程’乃改變金屬柱與預焊料凸塊所構成之電 11 200837918 幾何形狀’從防痒層所顯露出該金屬柱之章 =頁和可抑制直線裂紋的發生，且該蕈狀頭部及; 的。P份該金屬柱，提供盥 八卜 積’及省除電性連接墊盥全屬 面 /、孟屬柱間結構較弱的導電層，而 在可罪度測試時，接點之機械強 於習知脸7 ▲ 域抗疲勞(fatigue)性質優 其+技何’可以有效抑制接點斷裂，因此本發明可提 度相於縮短線寬及線距之覆 曰曰封衣基板表面結構。 10 15 上述實施例僅係為了方便說明而舉例而已，本發明所 主張之權職圍自細申請專·圍所 於上述實施例。 非僅限 【圖式簡單說明】 圖1係習知封裝基板表面結構之示意圖。 圖2A〜2G圖係、纟發明一較佳實施例封裝|板表面結構之 製作流程示意圖。10 15 20 : From one of copper, tin, lead, nickel, gold, silver, antimony and a combination thereof, the material used in this embodiment is tin. In addition, after the process described in FIG. 2E is completed, directly on the metal post 27, the head portion 27〇 and the portion of the metal post (7), through the printing and reflow process, the pre-solder is formed. Bumps 3() without additionally forming a metal back layer 29. Therefore, the aforementioned pre-solder bump 3 and metal underlayer μ can be selectively formed in accordance with the process. The present invention provides a package substrate surface structure. As shown in FIG. 2E, the surface structure of the sealing substrate comprises a substrate 21 having a circuit layer 24 on its surface, the circuit layer 24 having a plurality of connection pads 241 having a _(four) layer between the base surface and the circuit layer 24. twenty two. In addition, the base layer (4) and the circuit layer are covered with a solder resist layer 28 having a plurality of openings corresponding to the connection pads 241 and a metal pillar 27 disposed on the solder resist layers π. An opening, corresponding to the connecting pad 241, the metal post W extends out of the opening and is similar to the surface of the solder resist 27 and forms a braided head 27〇, and the portion below the braided head 270 The metal post 271 is also exposed. The structure and process of the package substrate having a dome-shaped metal post on the surface of the present invention change the electrical structure formed by the metal pillar and the pre-solder bump. 20083791818 Geometry 'The metal pillar is exposed from the anti-itch layer The chapter = page and can suppress the occurrence of straight cracks, and the head of the braided head; P part of the metal column, providing the conductive layer of the 盥八卜积' and the province's static-removing connection pad, all of which are weaker, and the structure of the junction is weaker. Knowing the face 7 ▲ The domain's fatigue resistance is excellent, and its technique can effectively suppress the joint breakage. Therefore, the present invention can extract the surface structure of the cover substrate by shortening the line width and the line pitch. The above-described embodiments are merely exemplified for convenience of explanation, and the claims of the present invention are applied to the above embodiments. Not limited to [Simplified description of the drawings] Fig. 1 is a schematic view showing the surface structure of a conventional package substrate. 2A to 2G are schematic views showing a manufacturing process of a package|board surface structure according to a preferred embodiment of the invention.
【主要元件符號說明】 連接墊141 T型金屬柱17 第一阻層23 連接墊241 金屬柱27 基板11 線路層14 防焊層15 導電層16 T型金屬柱表面17 0預焊料凸塊19 基板21 導電層22 開口區230 線路層24 第二阻層25 開孔250 12 200837918 防焊層28 蕈狀頭部270 部份金屬柱271 金屬接著層29 預焊料凸塊30[Main component symbol description] Connection pad 141 T-type metal post 17 First resist layer 23 Connection pad 241 Metal post 27 Substrate 11 Circuit layer 14 Solder mask 15 Conductive layer 16 T-type metal post surface 17 0 Pre-solder bump 19 Substrate 21 Conductive layer 22 Open region 230 Circuit layer 24 Second resist layer 25 Opening 250 12 200837918 Solder mask 28 Braided head 270 Partial metal post 271 Metal back layer 29 Pre-solder bump 30
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