CN104143540A - 薄膜倒装结构、金属凸块结构与形成薄膜倒装结构的方法 - Google Patents

薄膜倒装结构、金属凸块结构与形成薄膜倒装结构的方法 Download PDF

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CN104143540A
CN104143540A CN201410189758.4A CN201410189758A CN104143540A CN 104143540 A CN104143540 A CN 104143540A CN 201410189758 A CN201410189758 A CN 201410189758A CN 104143540 A CN104143540 A CN 104143540A
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layer
metal
alloy
sheath
cap layer
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CN104143540B (zh
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林久顺
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Himax Technologies Ltd
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Himax Technologies Ltd
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Abstract

本发明公开一种薄膜倒装结构、金属凸块结构与形成薄膜倒装结构的方法。薄膜倒装结构包含用来完全覆盖位于金属焊垫上的金属凸块的帽盖层、夹置于金属凸块与帽盖层间的凸块合金层、完全覆盖与聚合材料层连接的引脚层的覆层、直接夹置于引脚层与覆层间的引脚合金层。凸块合金层、引脚合金层与界面合金层分别具有梯度组成。

Description

薄膜倒装结构、金属凸块结构与形成薄膜倒装结构的方法
技术领域
本发明涉及一种薄膜倒装(chip on flex, COF)结构、金属凸块(metalbump)结构及其形成的方法。特别是涉及一种适用于显示器中、使用合金保护的薄膜倒装结构与金属凸块结构，及其形成的方法。
背景技术
在电子电路中，薄膜倒装结构用来让电子装置变的更轻与更小。弹性印刷电路板是薄膜倒装结构的载体。倒装上的金凸块则与弹性印刷电路板上的引脚连结。
一般说来，金是作为金属凸块理想的材料，因为它的化学性质不活泼，而且够软，所以产品相当可靠。然而，一直居高不下的金价使得黄金变的不是划算的材料。所以仍然需要一种用于薄膜倒装结构新颖的解决方法，来降低制造成本。
发明内容
有鉴于此，本发明首先提出一种薄膜倒装结构，其可用于显示器中。此等薄膜倒装结构，基本上在制造时比较便宜，而且更有利的是，在极端环境或是异常环境下不会发生迦凡尼效应(Galvanic effect)。
本发明的薄膜倒装结构，包含金属焊垫、护层、黏着层、金属凸块、帽盖层、凸块合金层、基材与界面合金层。护层位于金属焊垫上，并定义出位于金属焊垫上的凹穴。黏着层完全位于凹穴中、位于金属焊垫上、又部分位于护层上，使得黏着层又直接接触金属焊垫与护层。由第一金属所组成的金属凸块部分位于凹穴中并覆盖黏着层。由第二金属所组成的帽盖层位于金属凸块上并几乎完全并覆盖金属凸块，帽盖层使得金属凸块不会暴露出来。凸块合金层是第一金属与第二金属的第一合金，并具有第一梯度组成。基材用来电连接帽盖层，并包含聚合材料层、引脚层(lead layer)、覆层(cover layer)与引脚合金层。引脚层由第一金属所组成，且直接连接至聚合材料层。覆层由第二金属所组成且完全覆盖引脚层，而使得引脚不会暴露出来。引脚合金层直接夹置于引脚层与覆层之间。引脚合金层是第一金属与第二金属的第二合金，并具有第二梯度组成。界面合金层直接夹置于覆层与帽盖层之间。界面合金层是第一金属与第二金属的第三合金，并具有第三梯度组成。
在本发明一实施方式中，帽盖层自行对准于金属凸块。
在本发明另一实施方式中，帽盖层、黏着层、与护层间具有嵌穴(notch)。
在本发明另一实施方式中，覆层的表面积不小于帽盖层的表面积。
在本发明另一实施方式中，覆层对准于帽盖层。
在本发明另一实施方式中，薄膜倒装结构还包含位于护层与聚合材料层间的树脂，以密封界面合金层、覆层与帽盖层。
本发明另外提出一种形成薄膜倒装结构的方法。首先，制备载体，载体包含金属焊垫、护层、黏着层、金属凸块、帽盖层与凸块合金层。护层位于金属焊垫上，并定义出位于金属焊垫上的凹穴。黏着层完全位于凹穴中、位于金属焊垫上、又部分位于护层上，使得黏着层又直接接触金属焊垫与护层。由第一金属所组成的金属凸块部分位于凹穴中并覆盖黏着层。由第二金属所组成的帽盖层位于金属凸块上并几乎完全并覆盖金属凸块。帽盖层能使得金属凸块不会暴露出来。凸块合金层直接夹置于金属凸块与帽盖层之间，是第一金属与第二金属的第一合金，并具有第一梯度组成。
其次，提供基材，用来电连接帽盖层。基材包含聚合材料层、引脚层、覆层与引脚合金层。引脚层由第一金属所组成，且直接连接至聚合材料层。覆层由第二金属所组成且完全覆盖引脚层，而使得引脚不会暴露出来。引脚合金层直接夹置于引脚层与覆层之间。引脚合金层是第一金属与第二金属的第二合金，并具有第二梯度组成。
然后，将载体连接至基材，而使得覆层直接接触帽盖层。继续，进行连接步骤，而形成直接夹置于覆层与帽盖层间的界面合金层。界面合金层是第一金属与第二金属的第三合金，并具有第三梯度组成。
在本发明一实施方式中，制备载体包含以下的步骤。首先，提供底材，底材包含金属焊垫、护层、黏着层、与图案化光致抗蚀剂。护层位于金属焊垫上，并定义出位于金属焊垫上的凹穴。黏着层位于凹穴中，覆盖并直接接触金属焊垫与护层。图案化光致抗蚀剂位于黏着层上，并包含有开口，此开口暴露位于凹穴中与护层上的黏着层。其次，以金属凸块材料填入开口中。然后，移除图案化光致抗蚀剂，使得金属凸块材料成为位于黏着层上的金属凸块。再来，移除没有被金属凸块材料所覆盖的黏着层，同时部分暴露位于下方的护层。继续，形成覆盖金属凸块的帽盖层。
在本发明另一实施方式中，移除黏着层时，过移除(over-removed)黏着层，以形成位于帽盖层、黏着层、与护层间的嵌穴(notch)。
在本发明另一实施方式中，形成薄膜倒装结构的方法，还包含经由熟化金属凸块以调整金属凸块的硬度。
在本发明另一实施方式中，将基材连接至载体时，覆层对准于帽盖层。
在本发明另一实施方式中，形成薄膜倒装结构的方法，还包含形成位于护层与聚合材料层间的树脂，以密封界面合金层、覆层与帽盖层。
在本发明另一实施方式中，形成薄膜倒装结构的方法，还包含形成位于护层与聚合材料层间的树脂，以密封界面合金层、覆层与帽盖层，树脂并填入嵌穴中。
本发明又提出一种金属凸块结构，其可用于显示器的驱动集成电路(driver IC)中。本发明的金属凸块结构包含金属焊垫、护层、黏着层、金属凸块与帽盖层。护层位于金属焊垫上，并定义出位于金属焊垫上的凹穴。黏着层位于凹穴中、位于金属焊垫上、又部分位于护层上，黏着层又直接接触金属焊垫与护层。包含第一金属的金属凸块部分位于凹穴中并覆盖黏着层。包含第二金属的帽盖层位于金属凸块上、并覆盖金属凸块，而使得金属凸块不会暴露出来。
在本发明一实施方式中，帽盖层自行对准于金属凸块。
在本发明另一实施方式中，帽盖层、黏着层、与护层间具有嵌穴(notch)。
在本发明另一实施方式中，帽盖层还包含外层。
在本发明另一实施方式中，覆层的表面积不小于帽盖层的表面积。
在本发明另一实施方式中，覆层对准于帽盖层。
在本发明另一实施方式中，金属凸块结构还包含位于护层与聚合材料层间的树脂，以密封界面合金层、覆层与帽盖层。
在本发明另一实施方式中，树脂填入位于帽盖层、黏着层、与护层间的嵌穴中。
附图说明
图1至图12C绘示本发明形成薄膜倒装的金属凸块结构方法，其中图8A、图10A、图12A、图12B绘示不同的实施例；
图13A、图13B、图13C、图14A、图14B与图14C绘示本发明薄膜倒装结构与金属凸块结构。
符号说明
1   金属凸块结构
2   薄膜倒装结构
9   绝缘层
10  底材
11  金属焊垫
12  护层
13  黏着层
14  光致抗蚀剂层
14  光致抗蚀剂层’
15  凹穴
16  开口
20’ 金属凸块材料
20  金属凸块
30  嵌穴
40  帽盖层
41  合金
42  内层
43  外层
50  基材
51  聚合材料层
52  引脚层
53  覆层
54  引脚合金层
60  界面合金层
70  封胶
具体实施方式
本发明首先提供一种形成可以用于显示器中的薄膜倒装结构的方法。图1至图12B绘示本发明形成薄膜倒装结构的方法。这种薄膜倒装结构，基本上在制造时比较便宜，而且更有利的是，因为多重梯度合金层与密封树脂的存在，即使在极端环境或是异常环境下也不会发生迦凡尼效应。
首先，制备载体10并提供基材50。本发明的载体10至少包括金属焊垫11、护层12、黏着层13、金属凸块20、帽盖层40与凸块合金层41。基材50用来电连接帽盖层40。基材50包含聚合材料层51、引脚层52、覆层53与引脚合金层54。
一方面，载体10可以使用如下的方式来制备。首先，如图1所绘示，提供底材10。底材10包括金属焊垫11、护层12与黏着层13。
绝缘层9为底材10的基础部分，用来支撑其它的元件，例如用来支撑金属焊垫11、护层12、黏着层13与后续图中的图案化光致抗蚀剂层。金属焊垫11可以是一种质轻的金属材料，例如铝，并经过图案化。但是，其它的金属也可采用，而并不仅限于铝。
护层12即位于金属焊垫11之上，同时还具有定义出凹穴15的图案，使得凹穴15也位于金属焊垫11之上。护层12可以是一种电绝缘的材料，例如是氮化硅、氧化硅或是其组合。通常来说，凹穴15的大小会小于金属焊垫11的大小。
黏着层13又位于凹穴15之中。此外，黏着层13还会覆盖金属焊垫11与护层12，使得黏着层13会直接接触金属焊垫11与护层12。黏着层13用来帮助后续形成的金属凸块材料(图未示)牢牢地附着在凹穴15之中。黏着层13可以是一种合金层，例如钛钨合金层或是钛金属层。
黏着层13的形成方法可以是，利用溅镀一层钛钨合金，与例如铜的晶种层的方法，来均匀地覆盖底材10，例如完全地覆盖金属焊垫11、护层12、与凹穴15的表面。结果例示于图1中。形成图案化光致抗蚀剂层的方式，可以参考如下所示的方式。
如图2所绘示，将一大片光致抗蚀剂层14’整体形成在黏着层13上，并同时填满凹穴15。光致抗蚀剂层14’可以是光敏性的材料，例如是有机的光敏材料。
再来，如图3所绘示，将光致抗蚀剂层14’图案化。图案化光致抗蚀剂层14的方式可以是如下所述。光致抗蚀剂层14形成在黏着层13上来定义出开口16。开口16用来暴露出位于凹穴15中与护层12上的黏着层13，因此，在本发明的一实施例中，开口16会稍微大于凹穴15。换句话说，开口16可以用来定义出后续所形成的金属凸块材料(图未示)所位于的空间，而此空间本身即容置了凹穴15。
然后，整体的光致抗蚀剂层14’又会经过适当的曝光与显影步骤，而转换成图案化光致抗蚀剂层14，而具有曝光与显影所赋与的预定图案。图案是经由开口16所定义出的，其结果即绘示于图3所中。
接下来，如图4所绘示，使用金属凸块材料20’来填入开口16中。请注意，金属凸块材料20’可能仅仅只是「填入」开口16中，而没有「填满」开口16。此时，黏着层13即因此夹置于金属凸块材料20’与金属焊垫11之间，以及夹置于金属凸块材料20’与护层12之间。例如，由于金属焊垫11与黏着层13均为导电性材料，所以金属凸块材料20’可以经由电镀的方式来形成。视情况需要，金属凸块材料20’可以使用钯、银、铜或是金，以寻求优选的导电性，与越低越好的化学活性。
一但将金属凸块材料20’形成好了之后，就不再需要图案化光致抗蚀剂层14了。于是，如图5所绘示，移除图案化光致抗蚀剂层14，使得金属凸块材料20’成为各自独立的金属凸块20。可以使用传统的方式来移除图案化光致抗蚀剂层14。于是，各自独立的金属凸块20，就会完全位于黏着层13之上，并直接接触黏着层13。
由于黏着层13是导电的，这会导致所有的金属凸块20彼此短路，所以多余的黏着层13必须要移除。再来，如图6所绘示，没有被金属凸块20所覆盖的黏着层13经由蚀刻步骤来移除，又部分地暴露出下方的护层12，使得所有的金属凸块20，通过电绝缘材料，也即护层12的隔离，成为彼此电绝缘。如此一来，所有的金属凸块20即自我对准于黏着层13。例如，可以使用过氧化氢来蚀刻黏着层13的钛钨合金。
视情况需要，蚀刻步骤之后还可以进行加热金属凸块20的熟化，来调整金属凸块20达到所需的硬度。例如，在大于300℃或是维持超过90分钟的退火条件。一般说来，较低的硬度需要较高的熟化温度与较短的熟化时间，而较高的硬度需要较低的熟化温度与较长的熟化时间，来将金属凸块20调整到所需的适当硬度，例如不超过130维氏硬度(Hv)，优选的不大于110维氏硬度，更佳的介于50维氏硬度至110维氏硬度之间。
此时可以注意到在图6中，在移除黏着层13时，在金属凸块20、黏着层13、与护层12之间形成了一只嵌穴30，因为蚀刻步骤不只会完全移除没有被金属凸块20所覆盖的黏着层13，蚀刻步骤也可能会更进一步移除没有被金属凸块20所覆盖的黏着层13以外其他的黏着层13，例如，夹置于金属凸块20、与护层12间的黏着层13。而结果是，在金属凸块20、黏着层13、与护层12之间便形成了一只嵌穴30，而成为本发明结构的特征之一。在有嵌穴30存在时，金属凸块20会几乎覆盖所有的黏着层13。另外，嵌穴30则可能横向地深入1微米(μm)-2微米左右的尺寸。
由于各自独立的金属凸块20，仍然可能因为暴露于周围的大气环境中而失之脆弱，所以需要再特意形成帽盖层来尽量覆盖金属凸块20，使得金属凸块20尽量不会暴露于周围的大气环境中。请参考图7所绘示，形成帽盖层40来几乎完全覆盖金属凸块20，而在有嵌穴30的存在下，得到了理想的金属凸块结构1。
帽盖层40可以包含一种或多种保护性的材料。如果是铜制成的金属凸块20，帽盖层40可以包含锡、镍、金、钯其中至少一者。如果是金制成的金属凸块20，帽盖层40可以包含锡、镍、钯其中至少一者。如果是银制成的金属凸块20，帽盖层40可以包含锡。如果是钯制成的金属凸块20，帽盖层40可以包含锡。不过，所形成帽盖层40可能如图7所绘示，只会减小嵌穴30的尺寸，或是如图8或图8A所绘示，因为完全填满了嵌穴30，使得嵌穴30消失不见。所以，形成帽盖层40用来完全覆盖金属凸块20。
例如，请参考图7、图8或图8A所绘示，帽盖层40包含内层42与外层43，其各别可以为单层结构或是多层结构。内层42与外层43可以是相同的材料或是不同的材料，像是锡42/43(相同的材料)、镍42/金43(各别为单层的不同材料)、钯42/金43或镍42/钯+金43(单层结构42与多层结构43的组合)。
优选的，可以经由无电极电镀法来形成帽盖层40，例如可以在小于4的酸碱值、硫酸盐的辅助下进行无电极电镀法。由于护层12是一种电绝缘材料，所以帽盖层40很可能只会特定而专一地形成在金属凸块20上。换句话说，帽盖层40即自我对准在金属凸块20上。
另外，依据无电极电镀法的不同电镀配方或是电镀条件，帽盖层40还可以有不同的厚度与其它的形状。例如，帽盖层40可能是合金41、内层42与外层43的搭配或组合。优选的，帽盖层40含有金，其优点在于有利于重工(re-work)，又可以减低材料的成本。当帽盖层40含钯时，钯层的厚度可以是0.15微米-0.4微米左右。帽盖层40的厚度，可以是在2微米以下，优选的不大于0.1微米，甚至于可以只有0.006微米而已。由于护层为电绝缘材料，帽盖层40只会特定形成在金属凸块20上。表1列举电镀帽盖层40、内层42与外层43的可行步骤与制作工艺参数做为参考。其中在每个步骤之后，均可以再加入纯水洗涤的清洁步骤。
表1
在本发明的一实施例中，又可以引入另一熟化(curing)步骤，使得帽盖层40与金属凸块20形成合金41，称为凸块合金层41。例如，请参考图9、图10或图10A所绘示，形成在金属凸块20上的帽盖层40被加热到，例如在150℃～180℃与30～60分钟的条件下，与金属凸块20形成凸块合金层41。铜与锡在不同的条件下，可以形成多种的合金，例如Cu3Sn、Cu6Sn5、Cu41Sn11、或是Cu10Sn3。在本发明的一优选实施例中，凸块合金层41是一种混合物，并具有第一梯度组成。例如，凸块合金层41的梯度组成可以是Cu3Sn、Cu6Sn5、Cu41Sn11、或是Cu10Sn3。温度与时间通常会影响到形成合金相的速率。一般说来，比较接近铜的合金相含铜率比较高，而比较远离铜的合金相含铜率比较低，所以凸块合金层41可以有梯度组成。
凸块合金层41的形成，刻意用来防止金属凸块20在极端的情形下可能穿过帽盖层40。在帽盖层40的保护下又有合金41，金属凸块20都不会暴露于周围的大气环境中。图9绘示，在嵌穴30的存在下，熟化金属凸块20形成合金41。图10所绘示，熟化金属凸块20形成合金41，但没有嵌穴30。
另一方面，如图11所绘示，基材50可以是市售的，或是预先制得的。基材50至少包含聚合材料层51、引脚层52、覆层53与引脚合金层54。聚合材料层51可以是坚韧又有弹性的有机材料，例如聚酰亚胺。聚合材料层51可以是经过裁切或是未经裁切的卷条(reel)，所以聚合材料层51的形式可以是未经裁切的卷条或是经裁切的长条。
引脚层52可以是由纯金属所制得，例如钯、银、铜、或是金，来追求尽量低的电阻与化学活性。引脚层52直接连接至聚合材料层51。覆层53可以是由保护性的纯金属所制得。如果是铜制成的引脚层52，覆层53可以包含锡、镍、金、钯其中至少一者。如果是金制成的引脚层52，覆层53可以包含锡、镍、钯其中至少一者。如果是银制成的引脚层52，覆层53可以包含锡。如果是钯制成的引脚层52，覆层53可以包含锡。覆层53的厚度可以是0.5微米至1微米。优选的，覆层53完全覆盖引脚层52，而使得引脚层52的引脚不会暴露出来。
类似地，引脚合金层54是来自覆层53与引脚层52的，并夹置在覆层53与引脚层52之间。引脚合金层54是一种混合物，并具有第二梯度组成。例如，引脚合金层54的梯度组成，可以是Cu6Sn5在中间、而Cu3Sn接近凸块或是薄膜倒装(COF)的引脚。
接下来，请参考图12A、图12B或图12C所绘示，将载体10连接至基材50，而使得覆层53直接接触帽盖层40。继续，请参考图13A、图13B或图13C所绘示，进行一连接步骤，而形成直接夹置于覆层53与帽盖层40间的界面合金层60。连接步骤可以是一种超音波连接步骤。例如，超音波连接步骤可以在：器材温度为室温至260℃的范围内、接合施力为15牛顿至300牛顿、阶段温度为室温至150℃的范围内、接合时间为0.5至60秒钟的条件下进行。
界面合金层60也是一种覆层53与帽盖层40的混合物。类似地，界面合金层60具有第三梯度组成。例如，界面合金层60的梯度组成，可以是Cu6Sn5位于中间、而Cu3Sn接近凸块或是薄膜倒装的引脚。图13A绘示载体10可以有嵌穴30。图13B绘示只有内层42填入嵌穴30而外层43覆盖在外。也可能如图13C所绘示，载体10没有嵌穴30是因为帽盖层40填满了嵌穴30。
视情况需要，如图14A、图14B或图14C所绘示，还可以使用封胶70，来密封界面合金层60、覆层53与帽盖层40。封胶70可以是如环氧树脂的底部填充胶(Underfill)。由于封胶70环绕载体10与基材50之间的空间，所以封胶70于是气密性地密封界面合金层60、覆层53与帽盖层40。如果有嵌穴30，封胶70可以填入嵌穴30中，如图14A所绘示。或是，如果没有嵌穴30，也可以是只有内层42填入嵌穴30而外层43覆盖在外，如图14B所绘示。又，也可以是以帽盖层40填满了嵌穴30，如图14C所绘示。
在经过以上的步骤后，就可以得到一种薄膜倒装结构2。本发明的薄膜倒装结构2，适合用于薄膜倒装(COF)封装结构，因此可以用于显示器装置(display device)中。请参阅图14A、图14B或图14C，本发明的薄膜倒装结构2包含载体10、基材50与界面合金层60。载体10包括金属焊垫11、护层12、黏着层13、金属凸块20、帽盖层40与凸块合金层41。基材50用来电连接帽盖层40。基材50包含聚合材料层51、引脚层52、覆层53与引脚合金层54。
金属焊垫11可以是一种质轻的金属材料，例如铝，并经过图案化。但是，其它的金属也可采用，而并不限于铝。护层12即位于金属焊垫11之上，同时还具有图案化而定义出的凹穴15，使得凹穴15也位于金属焊垫11之上。护层12可以是一种电绝缘的材料，例如是氮化硅、氧化硅或是其组合。通常来说，凹穴15的大小会小于金属焊垫11的大小。
凹穴15之中完全填有黏着层13。此外，黏着层13还位于金属焊垫11之上，来覆盖并直接接触金属焊垫11。然而，部分的黏着层13位于护层12上，来覆盖并直接接触护层12。黏着层13用来帮助金属凸块20牢牢地附着在凹穴15之中。黏着层13可以是一种合金层，例如钛钨合金层，或是钛金属层。
金属凸块20部分地位于凹穴15中并覆盖黏着层13，使得黏着层13夹置于金属凸块20与金属焊垫11之间，以及夹置于金属凸块20与护层12之间。特别是，金属凸块20会自我对准于黏着层13。视情况需要，金属凸块20的材料可以是钯、银、铜或是金，以寻求较佳的导电性，与越低越好的化学活性。
特别是，如图14A、图14B或图14C所绘示，可以注意到本发明结构的特征之一，在金属凸块20、黏着层13、与护层12之间还可能会有一只嵌穴30，使得嵌穴30可能会是个使得黏着层13部分暴露出来的孔洞。请注意，较厚的帽盖层40可能会减小嵌穴30的尺寸，或是只有内层42填入嵌穴30，或是帽盖层40填满了嵌穴30而使得嵌穴30消失，如图14A、图14B或图14C所绘示。
帽盖层40位于金属凸块20上是用来完全覆盖金属凸块20，使得帽盖层40使得金属凸块20可以免于暴露于大气环境中。换句话说，帽盖层40可以自我对准于金属凸块20。帽盖层40可以包含多种保护性的材料。如果是铜制成的金属凸块20，帽盖层40可以包含锡、镍、金、钯其中至少一者。如果是金制成的金属凸块20，帽盖层40可以包含锡、镍、钯其中至少一者。如果是银制成的金属凸块20，帽盖层40可以包含锡。如果是钯制成的金属凸块20，帽盖层40可以包含锡。
由于帽盖层40是特别形成在金属凸块20上的，帽盖层40即可以自我对准在金属凸块20上。在本发明的一实施例中，在金属凸块20上的帽盖层40与金属凸块20形成合金41，称为凸块合金层41。如图14A、图14B或图14C所绘示。在本发明的一优选实施例中，凸块合金层41是一种混合物，并具有梯度组成。例如，凸块合金层41的梯度组成可以是可以是Cu6Sn5在中间、而Cu3Sn接近凸块或是薄膜倒装(COF)的引脚。
凸块合金层41的形成，刻意用来防止金属凸块20在极端的情形下可能穿过帽盖层40。在帽盖层40的保护下又有凸块合金层41，金属凸块20都不会暴露于周围的大气环境中。图14A绘示，在嵌穴30的存在下，熟化金属凸块20形成合金41。图14B或图14C绘示，熟化金属凸块20形成合金41，但没有嵌穴30。
基材50可以是市售的，或是预先制得的。基材50至少包含聚合材料层51、引脚层52、覆层53与引脚合金层54。聚合材料层51可以是坚韧又有弹性的有机材料，例如聚酰亚胺。聚合材料层51可以是经过裁切或是未经裁切的卷条，所以聚合材料层51的形式可以是卷条或是长条。
引脚层52可以是由纯金属所制得，例如钯、银、铜、或是金，来追求尽量低的电阻与化学活性。引脚层52直接连接至聚合材料层51。覆层53可以是由保护性的纯金属所制得。如果是铜制成的引脚层52，覆层53可以包含锡、镍、金、钯其中至少一者。如果是金制成的引脚层52，覆层53可以包含锡、镍、钯其中至少一者。如果是银制成的引脚层52，覆层53可以包含锡。如果是钯制成的引脚层52，覆层53可以包含锡。覆层53的厚度可以是0.5微米至1微米。优选的，覆层53完全覆盖引脚层52，而使得引脚层52的引脚不会暴露出来。
类似地，覆层53与引脚层52一起形成引脚合金层54，使得引脚合金层54夹置在覆层53与引脚层52之间。引脚合金层54是一种混合物，并具有第二梯度组成。例如，引脚合金层54的梯度组成，可以是Cu6Sn5在中间、而Cu3Sn接近凸块或是薄膜倒装(COF)的引脚。
覆层53与帽盖层40，形成了另一层合金层，称为界面合金层60，所以界面合金层60直接夹置于覆层53与帽盖层40之间。界面合金层60也是一种覆层53与帽盖层40的材料的混合物。类似地，界面合金层60具有第三梯度组成。例如，界面合金层60的梯度组成，可以是Cu6Sn5位于中间、而Cu3Sn接近凸块或是薄膜倒装的引脚。图14A绘示载体10可以有嵌穴30。图14B与图13C绘示，载体10有可能没有嵌穴30。
视情况需要，如图14A、图14B或图14C所绘示，封胶70位于载体10与基材50之间，来密封界面合金层60、覆层53与帽盖层40。封胶70可以是如环氧树脂的底部填充胶。由于封胶70环绕载体10与基材50间的空间，所以封胶70于是气密性地密封界面合金层60、覆层53与帽盖层40。如果有嵌穴30，封胶70可以填入嵌穴30中，如图14A所绘示。或是，如果没有嵌穴30，也可以是只有内层42填入嵌穴30而外层43覆盖在外，如图14B或图14C所绘示。
以上所述仅为本发明的优选实施例，凡依本权利要求范围所做的均等变化与修饰，都应属本发明的涵盖范围。

Claims (21)

1.一种薄膜倒装结构，包含：
金属焊垫；
护层，位于该金属焊垫上，并定义出位于该金属焊垫上的一凹穴；
黏着层，位于该凹穴中、位于该金属焊垫上、又部分位于该护层上，其中该黏着层直接接触该金属焊垫与该护层；
金属凸块，由一第一金属所组成且部分位于该凹穴中并覆盖该黏着层；
帽盖层，由一第二金属所组成、位于该金属凸块上并覆盖该金属凸块，而使得该金属凸块不会暴露出来；
凸块合金层，直接夹置于该金属凸块与该帽盖层间，其中该凸块合金层是该第一金属与该第二金属的一第一合金，并具有一第一梯度组成；
基材，用来电连接该帽盖层，其包含：
聚合材料层；
引脚层，由该第一金属所组成且直接连接至该聚合材料层；
覆层，由该第二金属所组成且完全覆盖该引脚层，而使得该引脚不会暴露出来；
引脚合金层，直接夹置于该引脚层与该覆层间，其中该引脚合金层是该第一金属与该第二金属的一第二合金，并具有一第二梯度组成；以及
界面合金层，直接夹置于该覆层与该帽盖层间，其中该界面合金层是该第一金属与该第二金属的一第三合金，并具有一第三梯度组成。
2.如权利要求1所述的薄膜倒装结构，其中该帽盖层自行对准于该金属凸块。
3.如权利要求1所述的薄膜倒装结构，其中该帽盖层、该黏着层、与该护层间具有一嵌穴。
4.如权利要求1所述的薄膜倒装结构，其中该覆层的表面积不小于该帽盖层的表面积。
5.如权利要求1所述的薄膜倒装结构，其中该覆层对准于该帽盖层。
6.如权利要求1所述的薄膜倒装结构，还包含：
树脂，位于该护层与该聚合材料层间，以密封该界面合金层、该覆层与该帽盖层。
7.一种形成薄膜倒装结构的方法，包含：
制备一载体，其包含：
金属焊垫；
护层，位于该金属焊垫上，并定义出位于该金属焊垫上的一凹穴；
黏着层，位于该凹穴中、位于该金属焊垫上又部分位于该护层上，其中该黏着层直接接触该金属焊垫与该护层；
金属凸块，由一第一金属所组成且部分位于该凹穴中并覆盖该黏着层；
帽盖层，由一第二金属所组成、位于该金属凸块上并覆盖该金属凸块，而使得该金属凸块不会暴露出来；
凸块合金层，直接夹置于该金属凸块与该帽盖层间，其中该凸块合金层是该第一金属与该第二金属的一第一合金，并具有一第一梯度组成；
提供一基材，包含：
聚合材料层；
引脚层，由该第一金属所组成且直接连接至该聚合材料层；
覆层，由该第二金属所组成且完全覆盖该引脚层，而使得该引脚不会暴露出来；以及
引脚合金层，直接夹置于该引脚层与该覆层间，其中该引脚合金层是该第一金属与该第二金属的一第二合金，并具有一第二梯度组成；
将该基材连接至该载体，而使得该覆层直接接触该帽盖层；以及
进行一连接步骤，而形成直接夹置于该覆层与该帽盖层间的一界面合金层，其中该界面合金层是该第一金属与该第二金属的一第三合金，并具有一第三梯度组成。
8.如权利要求7所述的形成薄膜倒装结构的方法，其中制备该载体包含：
提供一底材，包含：
金属焊垫；
护层，位于该金属焊垫上，并定义出位于该金属焊垫上的一凹穴；
黏着层，位于该凹穴中、覆盖并直接接触该金属焊垫与该护层；以及
图案化光致抗蚀剂，位于该黏着层上，并包含暴露位于该凹穴中与该护层上的该黏着层的一开口；
以一金属凸块材料填入该开口中；
移除该图案化光致抗蚀剂，使得该金属凸块材料成为位于该黏着层上的一金属凸块；
移除没有被该金属凸块材料所覆盖的该黏着层，以部分暴露位于下方的该护层；以及
形成该第二金属的一帽盖层，以完全覆盖该金属凸块。
9.如权利要求8所述的形成薄膜倒装结构的方法，其中移除该黏着层时，过移除该黏着层，以形成位于该帽盖层、该黏着层、与该护层间的一嵌穴。
10.如权利要求8所述的形成薄膜倒装结构的方法，还包含：
经由熟化该金属凸块以调整该金属凸块的硬度。
11.如权利要求7所述的形成薄膜倒装的方法，其中将该基材连接至该载体时，该覆层对准于该帽盖层。
12.如权利要求7所述的形成薄膜倒装结构的方法，还包含：
形成一树脂，位于该护层与该聚合材料层间，以密封该界面合金层、该覆层与该帽盖层。
13.如权利要求7所述的形成薄膜倒装结构的方法，还包含：
形成一树脂，位于该护层与该聚合材料层间，以密封该界面合金层、该覆层与该帽盖层，并填入该嵌穴中。
14.一种金属凸块结构，其用于一驱动集成电路中并包含：
金属焊垫；
护层，位于该金属焊垫上，并定义出位于该金属焊垫上的一凹穴；
黏着层，位于该凹穴中、位于该金属焊垫上、又部分位于该护层上，其中该黏着层直接接触该金属焊垫与该护层；
金属凸块，包含一第一金属且部分位于该凹穴中并覆盖该黏着层；
帽盖层，包含一第二金属、位于该金属凸块上并完全覆盖该金属凸块，而使得该金属凸块不会暴露出来。
15.如权利要求14所述的金属凸块结构，其中该帽盖层自行对准于该金属凸块。
16.如权利要求14所述的金属凸块结构，其中该帽盖层、该黏着层、与该护层间具有一嵌穴。
17.如权利要求14所述的金属凸块结构，其中该帽盖层还包含一外层。
18.如权利要求14所述的金属凸块结构，其中该覆层的表面积不小于该帽盖层的表面积。
19.如权利要求14所述的金属凸块结构，其中该覆层对准于该帽盖层。
20.如权利要求14所述的金属凸块结构，还包含：
树脂，位于该护层与该聚合材料层间，以密封该界面合金层、该覆层与该帽盖层。
21.如权利要求20所述的金属凸块结构，其中该树脂填入位于该帽盖层、该黏着层、与该护层间的该嵌穴中。
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Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2709160B1 (en) * 2012-09-14 2016-03-30 ATOTECH Deutschland GmbH Method for metallization of solar cell substrates
US10128175B2 (en) * 2013-01-29 2018-11-13 Taiwan Semiconductor Manufacturing Company Packaging methods and packaged semiconductor devices
US20180053737A1 (en) * 2015-03-10 2018-02-22 Mitsubishi Electric Corporation Power semiconductor device
KR102663140B1 (ko) 2016-06-24 2024-05-08 삼성디스플레이 주식회사 디스플레이 장치
KR102508527B1 (ko) 2016-07-01 2023-03-09 삼성전자주식회사 필름형 반도체 패키지
KR102420586B1 (ko) 2017-07-24 2022-07-13 삼성전자주식회사 반도체 장치, 반도체 패키지 및 반도체 패키지의 제조 방법
IT201700087309A1 (it) * 2017-07-28 2019-01-28 St Microelectronics Srl Dispositivo elettronico integrato con regione di redistribuzione e elevata resistenza agli stress meccanici
IT201700087318A1 (it) 2017-07-28 2019-01-28 St Microelectronics Srl Dispositivo elettronico integrato con regione di redistribuzione e elevata resistenza agli stress meccanici e suo metodo di preparazione
US10522501B2 (en) * 2017-11-17 2019-12-31 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor structure and method of forming the same
US10741482B2 (en) 2017-12-29 2020-08-11 Advanced Semiconductor Engineering, Inc. Semiconductor device package
JP7122593B2 (ja) * 2018-05-08 2022-08-22 パナソニックＩｐマネジメント株式会社 半導体装置の製造方法、半導体装置の製造装置、及び半導体装置
US11469194B2 (en) 2018-08-08 2022-10-11 Stmicroelectronics S.R.L. Method of manufacturing a redistribution layer, redistribution layer and integrated circuit including the redistribution layer
CN110854066A (zh) * 2019-11-28 2020-02-28 无锡微视传感科技有限公司 一种半导体电镀方法
WO2021184188A1 (zh) * 2020-03-17 2021-09-23 元锦生物科技股份有限公司 可拆式接合结构
CN111640722B (zh) * 2020-06-11 2022-07-05 厦门通富微电子有限公司 一种芯片封装方法和芯片封装器件
CN111554582B (zh) * 2020-06-11 2022-07-15 厦门通富微电子有限公司 一种芯片封装方法和芯片封装器件
TWI845940B (zh) * 2022-05-13 2024-06-21 矽品精密工業股份有限公司 電子封裝件及其電子結構

Family Cites Families (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4205099A (en) * 1978-04-14 1980-05-27 Sprague Electric Company Method for making terminal bumps on semiconductor wafers
US5508228A (en) * 1994-02-14 1996-04-16 Microelectronics And Computer Technology Corporation Compliant electrically connective bumps for an adhesive flip chip integrated circuit device and methods for forming same
US5707902A (en) * 1995-02-13 1998-01-13 Industrial Technology Research Institute Composite bump structure and methods of fabrication
JP3968554B2 (ja) * 2000-05-01 2007-08-29 セイコーエプソン株式会社 バンプの形成方法及び半導体装置の製造方法
AU2003269066A1 (en) * 2002-05-16 2003-12-02 Agency For Science, Technology And Research Wafer level electroless copper metallization and bumping process, and plating solutions for semiconductor wafer and microchip
US7008867B2 (en) * 2003-02-21 2006-03-07 Aptos Corporation Method for forming copper bump antioxidation surface
CN1823410A (zh) * 2003-07-16 2006-08-23 皇家飞利浦电子股份有限公司 具有侧壁绝缘层的金属凸起和制造具有该金属凸起的芯片的方法
TWI222198B (en) 2003-09-04 2004-10-11 Fupo Electronics Corp Fine pitch gold bump fabrication process and its package article
JP4718809B2 (ja) 2004-08-11 2011-07-06 ローム株式会社 電子装置およびそれを用いた半導体装置、ならびに半導体装置の製造方法
KR100642765B1 (ko) * 2004-09-15 2006-11-10 삼성전자주식회사 하이브리드 범프를 포함하는 미세전자소자칩, 이의패키지, 이를 포함하는 액정디스플레이장치 및 이러한미세전자소자칩의 제조방법
TWI286454B (en) * 2005-03-09 2007-09-01 Phoenix Prec Technology Corp Electrical connector structure of circuit board and method for fabricating the same
KR100801073B1 (ko) 2005-10-06 2008-02-11 삼성전자주식회사 도전성 입자를 포함하는 범프를 구비하는 반도체 칩 및 이의 제조 방법
US7601566B2 (en) 2005-10-18 2009-10-13 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
US20070267745A1 (en) 2006-05-22 2007-11-22 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device including electrically conductive bump and method of manufacturing the same
JP2007317979A (ja) * 2006-05-29 2007-12-06 Toshiba Corp 半導体装置の製造方法
KR100850212B1 (ko) * 2007-04-20 2008-08-04 삼성전자주식회사 균일한 무전해 도금 두께를 얻을 수 있는 반도체 소자의제조방법
KR20080102545A (ko) 2007-05-21 2008-11-26 주식회사 엘지화학 Ｃｏｆ 실장용 2층 동박 적층판 및 그 제조 방법
US7713861B2 (en) * 2007-10-13 2010-05-11 Wan-Ling Yu Method of forming metallic bump and seal for semiconductor device
TW201019440A (en) * 2008-11-03 2010-05-16 Int Semiconductor Tech Ltd Bumped chip and semiconductor flip-chip device applied from the same
TWI469288B (zh) 2009-06-11 2015-01-11 Chipbond Technology Corp 凸塊化晶片結構及其應用之半導體覆晶裝置
TW201044527A (en) * 2009-06-11 2010-12-16 Int Semiconductor Tech Ltd Chip architecture having film-faced metal bumps and semiconductor flip-chip device applied from the same
KR20110090332A (ko) 2010-02-03 2011-08-10 한양대학교 산학협력단 이방성 전도 필름을 이용하여 기판이 접합된 반도체 소자 및 기판 접합방법
TWM397591U (en) * 2010-04-22 2011-02-01 Mao Bang Electronic Co Ltd Bumping structure
US8298930B2 (en) * 2010-12-03 2012-10-30 International Business Machines Corporation Undercut-repair of barrier layer metallurgy for solder bumps and methods thereof
CN102800599B (zh) * 2011-05-25 2015-03-25 颀邦科技股份有限公司 凸块工艺及其结构
KR20120139115A (ko) * 2011-06-16 2012-12-27 삼성디스플레이 주식회사 표시 장치 및 그 제조 방법
US8643196B2 (en) * 2011-07-27 2014-02-04 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method for bump to landing trace ratio
JP6035714B2 (ja) 2011-08-17 2016-11-30 ソニー株式会社 半導体装置、半導体装置の製造方法、及び、電子機器
US20130193570A1 (en) * 2012-02-01 2013-08-01 Chipbond Technology Corporation Bumping process and structure thereof
US8501614B1 (en) * 2012-03-22 2013-08-06 Chipbond Technology Corporation Method for manufacturing fine-pitch bumps and structure thereof
US9646951B2 (en) * 2013-12-10 2017-05-09 Semiconductor Components Industries, Llc Method of forming a semiconductor device and structure therefor

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US20140327134A1 (en) 2014-11-06
CN104143540B (zh) 2017-05-03
TW201444042A (zh) 2014-11-16
TWI600130B (zh) 2017-09-21
US9450061B2 (en) 2016-09-20
KR20140131876A (ko) 2014-11-14
CN104143539B (zh) 2018-04-10
KR20140131871A (ko) 2014-11-14
US20140327133A1 (en) 2014-11-06
TWI600129B (zh) 2017-09-21
TW201444006A (zh) 2014-11-16
KR101611376B1 (ko) 2016-04-11
TW201444037A (zh) 2014-11-16
TWI573205B (zh) 2017-03-01
KR101641993B1 (ko) 2016-07-22
CN104143538B (zh) 2018-01-02
CN104143543B (zh) 2017-10-03
US10128348B2 (en) 2018-11-13
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CN104143538A (zh) 2014-11-12
KR101611846B1 (ko) 2016-04-12

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