CN110943067A - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

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Publication number
CN110943067A
CN110943067A CN201910221859.8A CN201910221859A CN110943067A CN 110943067 A CN110943067 A CN 110943067A CN 201910221859 A CN201910221859 A CN 201910221859A CN 110943067 A CN110943067 A CN 110943067A
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layer
semiconductor device
opening
forming
insulating layer
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CN201910221859.8A
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CN110943067B (zh
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田岛尚之
下川一生
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Toshiba Corp
Kioxia Corp
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Toshiba Corp
Toshiba Memory Corp
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Abstract

本发明提供半导体装置及其制造方法。半导体装置具备：绝缘层；导电部件，设于所述绝缘层内；芯片，配置于所述绝缘层的第一面上，并连接于所述导电部件；以及电极，经由电阻率比所述导电部件的电阻率高的阻挡层连接于所述导电部件，且至少一部分从所述绝缘层的第二面突出。

Description

半导体装置及其制造方法
技术领域
实施方式涉及半导体装置及其制造方法。
背景技术
以往以来，在印刷基板上层叠多张存储器芯片，制造了由树脂模制而成的半导体装置。在印刷基板的下表面接合凸块，并经由该凸块将半导体装置安装于电子设备等。另一方面，由于近年要求半导体装置的低高度化，因此提出了代替印刷基板而使用再布线层的技术。在再布线层的上表面搭载存储器芯片，在再布线层的下表面接合凸块。
发明内容
实施方式的半导体装置具备：绝缘层；导电部件，设于所述绝缘层内；芯片，配置于所述绝缘层的第一面上，并连接于所述导电部件；以及电极，经由电阻率比所述导电部件的电阻率高的阻挡层连接于所述导电部件，且至少一部分从所述绝缘层的第二面突出。
实施方式的半导体装置的制造方法具备：在支承基板上，形成剥离层、第一阻挡层、导电层以及第二阻挡层的工序；在所述第二阻挡层上形成形成有第一开口部的第一绝缘层的工序；通过将所述第一绝缘层作为掩模实施蚀刻，从而在所述第二阻挡层形成与所述第一开口部连通的第二开口部的工序；在所述第二开口部内及所述第一开口部的下部内形成电极的工序；在所述第一开口部的上部的内表面上形成第三阻挡层的工序；在所述第一开口部的上部内形成第一导块，并且在所述第一绝缘层上形成电阻率比所述第三阻挡层的电阻率低的布线的工序；在所述布线上形成形成有第三开口部的第二绝缘层的工序；在所述第三开口部内形成与所述布线连接的第二导块的工序；将芯片连接于所述第二导块的工序；通过去除所述剥离层来去除所述支承基板的工序；以及去除所述第一阻挡层、所述导电层以及所述第二阻挡层的工序。
附图说明
图1是表示实施方式的半导体装置的剖面图。
图2是表示图1的区域A的局部放大剖面图。
图3是表示图1的区域B的局部放大剖面图。
图4是表示接合有凸块的实施方式的半导体装置的剖面图。
图5是表示图4的区域C的局部放大剖面图。
图6(a)～(d)是表示实施方式的半导体装置的制造方法的剖面图。
图7(a)～(d)是表示实施方式的半导体装置的制造方法的剖面图。
图8(a)～(d)是表示实施方式的半导体装置的制造方法的剖面图。
图9是表示实施方式的半导体装置的制造方法的剖面图。
图10是表示实施方式的半导体装置的制造方法的剖面图。
图11是表示实施方式的半导体装置的制造方法的剖面图。
图12(a)是表示实施方式的半导体装置的制造方法的剖面图，(b)是表示(a)的区域D的局部放大剖面图。
图13(a)是表示实施方式的半导体装置的制造方法的剖面图，(b)是表示(a)的区域E的局部放大剖面图。
图14是表示比较例的半导体装置的剖面图。
具体实施方式
以下，对实施方式进行说明。
图1是表示本实施方式的半导体装置的剖面图。
图2是表示图1的区域A的局部放大剖面图。
图3是表示图1的区域B的局部放大剖面图。
如图1及图2所示，在本实施方式的半导体装置1中设有再布线层10。在再布线层10中，作为基材，例如设有由有机材料构成的绝缘层11，在大致绝缘层11内设有下部导电部件12及上部导电部件13。下部导电部件12及上部导电部件13例如由铜(Cu)等金属材料形成。下部导电部件12配置于再布线层10的下层，上部导电部件13配置于再布线层10的上层。
下部导电部件12的下部为导块(via)14，上部为布线15。导块14及布线15一体地形成。导块14在上下方向上延伸，布线15在水平方向上延伸。导块14及布线15配置于绝缘层11内。
上部导电部件13的下部为导块16，上部为焊盘17。导块16及焊盘17一体地形成。导块16在上下方向上延伸，焊盘17沿水平面扩展。导块16配置于绝缘层11内。焊盘17配置于绝缘层11的上表面11f上。从上方观察时，一般来说，导块16的位置与导块14的位置不同，但也可以有重叠的部分。
在再布线层10还分别设有多个电极18及电极19。电极18及19例如包含镍(Ni)，例如由纯镍构成。电极18设于导块14的下表面上。电极19配置于焊盘17的上表面上。从上下方向观察时，电极18及19的形状也可以是圆形，也可以是四边形，也可以是四边形以外的多边形。
另外，在半导体装置1中，在绝缘层11的上表面11f上设有多个半导体芯片30，并沿上下方向层叠。半导体芯片30例如是三维NAND型存储器芯片。
再布线层10的电极19与最下层的半导体芯片30通过微凸块31而接合。在电极19与微凸块31之间形成有包含焊料成分及镍的金属间化合物层44。另外，相邻的半导体芯片30彼此通过微凸块32而接合。另外，在本说明书中，“接合”是指机械连结并且电连接的状态。在各半导体芯片30内设有贯通导块(未图示)，经由下方的微凸块31或32将从再布线层10输入的信号传递至半导体芯片30的存储单元及更上层的半导体芯片30。
在再布线层10上设有树脂部件36。树脂部件36由树脂材料构成，并覆盖被层叠的半导体芯片30、微凸块31及32。
在再布线层10的下表面搭载有控制用芯片41。控制用芯片41经由微凸块42与再布线层10的电极18接合。即，多个电极18中的一部分经由微凸块42与控制用芯片41接合。微凸块42例如由焊料构成。在电极18与微凸块42之间形成有包含焊料成分及镍的金属间化合物层44。另外，也可以在再布线层10与控制用芯片41之间设有覆盖微凸块42的树脂部件。
如图1～图3所示，在导块14的下表面上及侧面上、以及布线15的下表面上连续地设有钛(Ti)层21。因而，在导块14与绝缘层11之间夹有钛层21。另外，在布线15的下表面与绝缘层11之间也夹有钛层21。在下部导电部件12与钛层21之间设有铜层22。导块14经由铜层22及钛层21与电极18连接。
在导块16的下表面上及侧面上、以及焊盘17的下表面上设有钛层23。在上部导电部件13与钛层23之间设有铜层24。导块16经由铜层24及钛层23与布线15连接。由此，导块16经由布线15与导块14连接。
如图3所示，电极18的上部18b配置于绝缘层11内，下部18a从绝缘层11的下表面11r突出。下部18a从下表面11r突出的突出量例如为100nm(纳米)左右。在未接合有微凸块42的电极18的下部18a的露出面上设有金层25。金层25的厚度例如为50nm左右。
在半导体装置1中，各半导体芯片30经由贯通导块(未图示)、微凸块32及31、电极19、焊盘17、导块16、铜层24、钛层23、布线15、导块14、铜层22、钛层21以及电极18与外部连接。而且，控制用芯片41例如作为对多个半导体芯片30与外部之间的信号的交换进行控制的接口而发挥功能，并且作为对这些半导体芯片30的动作进行控制的控制器而发挥功能。
接下来，对在半导体装置1接合了凸块的情况进行说明。
图4是表示接合有凸块的本实施方式的半导体装置的剖面图。
图5是表示图4的区域C的局部放大剖面图。
如图4及图5所示，在未接合有微凸块42的电极18接合凸块46。凸块46由焊料构成。焊料例如包含锡(Sn)、银(Ag)以及铜。凸块46及微凸块42的熔点比微凸块31及32的熔点低。因此，能够在接合微凸块42及凸块46时避免微凸块31及32再次熔融。
凸块46的直径比微凸块31、32以及42的直径大，例如为300μm(微米)。凸块46与电极18的下部18a的下表面及侧面接触，并覆盖下表面及侧面的至少一部分、例如大致整体。另外，由于将凸块46接合于电极18时的热量导致金层25在凸块46内扩散而消失。然后，在电极18与凸块46之间形成以焊料材料与镍为主要成分的金属间化合物层45。金属间化合物层44及45例如包含镍、锡以及铜，例如包含Ni3Sn4、Cu6Sn5、或Cu3Sn等。金属间化合物层44及45的厚度虽然取决于接合的时间与温度，但大致为1μm左右。金属间化合物层44及45能够通过基于SEM(Scanning Electron Microscope：扫描电子显微镜)的剖面观察、或剖面观察与基于EDX(energy dispersive X-ray spectroscopy：能量色散X射线光谱仪)的组成分析来进行检测。
接下来，对本实施方式的半导体装置的制造方法进行说明。
图6(a)～(d)、图7(a)～(d)、图8(a)～(d)、图9、图10、图11、图12(a)及(b)、图13(a)及(b)是表示本实施方式的半导体装置的制造方法的剖面图。
图12(b)是表示图12(a)的区域D的局部放大剖面图。
图13(b)是表示图13(a)的区域E的局部放大剖面图。
首先，如图6(a)所示，准备支承基板100。支承基板100例如为硅晶片或玻璃基板。接下来，在支承基板100的上表面上形成剥离层101。剥离层101例如为能够溶解于特定的药液的有机材料、或通过光照射而产生分解反应的有机材料、或通过施加一定以上的应力而产生剥离的有机材料或无机材料。
接下来，在剥离层101上连续地形成钛层102(第一阻挡层)，在钛层上连续地形成铜层103(导电层)，在铜层上连续地形成钛层104(第二阻挡层)。钛层102与剥离层101的密合性高。通过钛层102、铜层103以及钛层104来构成晶种层105。
接下来，如图6(b)所示，在晶种层105上例如形成由有机材料构成的绝缘层11a(第一绝缘层)。接下来，例如通过光刻法或激光照射，在绝缘层11a形成导孔11b(第一开口部)。在导孔11b的底面露出晶种层105。
接下来，如图6(c)所示，例如通过实施蚀刻将钛层104中的未被绝缘层11a覆盖的部分去除。其结果，在钛层104形成开口部104a(第二开口部)而露出铜层103。钛层104中的被绝缘层11a覆盖的部分残留。
接下来，如图6(d)所示，通过经由晶种层105实施电解镀覆，使镍堆积。由此，在钛层104的开口部104a内及导孔11b的下部内形成电极18。铜层103由于导电性高，因此能够提高镀覆厚度的均匀性。在电极18中，配置于开口部104a内的部分成为下部18a，配置于导孔11b的下部内的部分成为上部18b。
接下来，如图7(a)所示，例如通过溅射法，使钛堆积于整个面而形成钛层21(第三阻挡层)。接下来，例如通过溅射法，使铜堆积于整个面而形成铜层22。钛层21及铜层22连续地形成于绝缘层11a的上表面上、导孔11b的上部的侧面上、以及电极18的上表面上。
接下来，如图7(b)所示，在铜层22上形成抗蚀剂图案106。在抗蚀剂图案106上通过光刻法形成开口部106a。使得在开口部106a的底面存在导孔11b。由此，开口部106a与导孔11b连通。
接下来，如图7(c)所示，通过经由铜层22电解镀覆铜，在开口部106a内形成下部导电部件12。下部导电部件12与铜层22成为一体。下部导电部件12中的埋入导孔11b的上部内的部分成为导块14，堆积于绝缘层11a上的部分成为布线15。导块14经由铜层22及钛层21与电极18连接。
接下来，如图7(d)所示，去除抗蚀剂图案106。由此，铜层22中的被抗蚀剂图案106覆盖的部分露出。
接下来，如图8(a)所示，例如通过实施蚀刻，将铜层22及钛层21中的未被下部导电部件12覆盖的部分去除。其结果，绝缘层11a再次露出。另一方面，铜层22及钛层21中的被下部导电部件12覆盖的部分残留。
接下来，如图8(b)所示，在绝缘层11a及下部导电部件12上，例如形成由有机材料构成的绝缘层11c(第二绝缘层)。通过绝缘层11a及绝缘层11c形成绝缘层11。接下来，例如通过光刻法或激光照射，在绝缘层11c形成导孔11d(第三开口部)。在导孔11d的底面露出下部导电部件12的布线15。以后，不区分绝缘层11a及绝缘层11c而表示为绝缘层11。
接下来，如图8(c)所示，例如通过溅射法，使钛堆积于整个面而形成钛层23。接下来，例如通过溅射法，使铜堆积于整个面而形成铜层24。钛层23及铜层24连续地形成于绝缘层11的上表面上及导孔11d的内表面上。
接下来，在铜层24上形成抗蚀剂图案108。在抗蚀剂图案108通过光刻法形成开口部108a。使得在开口部108a的底面存在导孔11d。由此，开口部108a与导孔11d连通。
接下来，如图8(d)所示，通过经由铜层24实施铜的电解镀覆，在开口部108a内形成上部导电部件13。上部导电部件13与铜层24成为一体。上部导电部件13中的埋入导孔11d内的部分成为导块16，堆积于绝缘层11上的部分成为焊盘17。导块16经由铜层24及钛层23与布线15连接。接下来，通过经由上部导电部件13电解镀覆镍，在上部导电部件13的焊盘17上形成由镍构成的电极19。接下来，在电极19上进行贵金属、例如金的置换镀覆。由此，镍的一部分从电极19溶出，并且析出金。其结果，在电极19的上表面上形成金层109。
接下来，去除抗蚀剂图案108(参照图8(c))。由此，铜层24中的被抗蚀剂图案108覆盖的部分露出。另外，焊盘17、电极19以及金层109从铜层24突出。
接下来，例如通过实施蚀刻，将铜层24及钛层23中的未被上部导电部件13覆盖的部分去除。其结果，绝缘层11再次露出。铜层24及钛层23中的被上部导电部件13覆盖的部分残留。
接下来，如图9所示，在电极19的上表面经由微凸块31接合半导体芯片30。此时，金层109在微凸块31内扩散而消失，并且新形成以铜、锡以及镍为主要成分的金属间化合物层44(参照图2)。接下来，在该半导体芯片30上，经由微凸块32层叠多个半导体芯片30。由此，在绝缘层11上层叠多个半导体芯片30。多个半导体芯片30经由微凸块32及31、电极19与焊盘17连接。另外，也可以将由预先经由微凸块32而相互接合了的多个半导体芯片30构成的层叠体经由微凸块31而与电极19接合。
接下来，如图10所示，在绝缘层11上，以将由多个半导体芯片30构成的层叠体覆盖的方式对树脂材料进行成形密封，例如以200℃以下的温度使其热固化，从而形成树脂部件36。
接下来，如图11所示，例如通过使用药液使其溶解、或通过由光照射进行分解来去除剥离层101(参照图10)。或者，以超过剥离层101的密接力的力将支承基板100(参照图10)从剥离层101剥离。由此，支承基板100被去除而晶种层105露出。
接下来，如图12(a)及(b)所示，去除晶种层105(参照图11(a)及(b))、即钛层102、铜层103以及钛层104。由此，绝缘层11及电极18的下部18a露出。此时，电极18的下部18a从绝缘层11的下表面11r突出钛层104的厚度的量。
接下来，如图13(a)及(b)所示，进行贵金属、例如金的置换镀覆。由此，镍的一部分从电极18的下部18a溶出，并且析出金。其结果，在电极18的下部18a的侧面上及下表面上形成金层25。通过以上的工序，形成再布线层10。
接下来，如图1及图2所示，在一部分的电极18上经由微凸块42接合控制用芯片41。通过该接合时的加热，金层25在微凸块42内扩散而消失。另外，在电极18的下部18a与微凸块42之间形成以铜、锡以及镍为主要成分的金属间化合物层44。另外，也可以在再布线层10与控制用芯片41之间以覆盖微凸块42的方式形成树脂部件。
接下来，进行切割，将再布线层10及树脂部件36切断。由此，可制造多个半导体装置1。半导体装置1的构成如图1～图3所示。
接下来，对本实施方式的效果进行说明。
在本实施方式中，在图6(a)～图10所示的工序中，在支承基板100上形成由再布线层10、半导体芯片30、树脂部件36等构成的构造体之后，在图11所示的工序中，去除支承基板100。由此，能够经由再布线层10将半导体芯片30连接于凸块46。其结果，与使用印刷基板的情况相比，能够实现半导体装置1的低高度化。
另外，在本实施方式中，在图6(a)所示的工序中形成钛层104，在图6(c)所示的工序中在钛层104形成开口部104a，在图6(d)所示的工序中在开口部104a内形成电极18的下部18a，在图12所示的工序中去除钛层104。由此，如图1及图3所示，在完成后的半导体装置1中，电极18的下部18a从绝缘层11的下表面11r突出钛层104的厚度的量。
其结果，如图4及图5所示，在将凸块46接合于电极18时，凸块46以覆盖电极18的侧面的方式被接合。因此，对于凸块46而言，作为电极18的锚定件(anchor)而发挥作用，凸块46与电极18的接合力变强。特别是，对剪切力、即对水平方向的力的耐性提高。另外，凸块46的露出面的整体呈凸面，在凸块46上未形成变窄部等凹部。因此，能够避免在凸块46产生以凹部为起点的裂纹。其结果，凸块46的可靠性提高。
并且，在本实施方式中，在图6(b)～图11所示的工序中，在铜层103与绝缘层11之间夹设有钛层104。绝缘层11由有机材料构成，钛相对于有机材料的密合性高，因此铜层103与绝缘层11的密合性高。因此，半导体装置1的制造稳定性高。另一方面，由于有机材料与铜的密合性低，因此假设绝缘层11与铜层103直接接触，则可能在界面发生剥离。
进一步，并且，在本实施方式中，在绝缘层11与下部导电部件12之间设置钛层21，并且在绝缘层11与上部导电部件13之间设有钛层23。由此，能够抑制下部导电部件12及上部导电部件13从绝缘层11剥离。
另外，下部导电部件12及上部导电部件13的材料并不限定于铜，为了在凸块46与半导体芯片30之间抑制电阻，优选导电性高的材料。另外，在本实施方式中，示出了设置钛层21及23作为阻挡层的例子，但并不限定于此，也可以设置由其他材料构成的层。但是，优选的是，阻挡层的材料与有机材料的密合性高。一般来说，优选的是，下部导电部件12及上部导电部件13的材料的电阻率比阻挡层的材料低，阻挡层的材料相对于有机材料的密合性比下部导电部件12及上部导电部件13的材料高。经验上来说，由于存在越是熔点高的金属、与有机材料的密合性越高的趋势，因此例如能够使阻挡层的材料为熔点比铜高的金属材料。
另外，也可以根据需要，在接合控制用芯片41之后、进行切割之前，向未与控制用芯片41接合的电极18供给成为凸块46的焊球，并进行加热而接合。通过该接合时的加热，金层25在凸块46内扩散而消失。另外，在电极18的下部18a与凸块46之间形成以铜、锡以及镍为主要成分的金属间化合物层45。由此，能够制造带有凸块46的半导体装置1。
接下来，对比较例进行说明。
图14是表示比较例的半导体装置的剖面图。
图14示出相当于图1的区域B的部分。
如图14所示，在本比较例的半导体装置111中，电极118的下表面位于从绝缘层11的下表面11r凹陷的位置。因此，若将凸块146接合于电极118，则有时会在凸块146中的下表面11r的延长面上形成变窄部146a。其结果，若凸块146被施加例如水平方向的剪切力，则有时会以变窄部146a为起点产生裂纹而凸块146断裂。因此，半导体装置111的凸块146的可靠性低。
根据以上说明的实施方式，能够实现能够提高凸块的接合强度的半导体装置及其制造方法。
以上，对本发明的几个实施方式进行了说明，但这些实施方式是作为例子而提出的，并不意图限定发明的范围。这些新的实施方式能够以其他各种方式来实施，能够在不脱离发明的主旨的范围内，进行各种省略、置换、变更。这些实施方式及其变形包含在发明的范围或主旨内，并且包含在权利要求书所记载的发明及其等效物的范围内。

Claims (15)

1.一种半导体装置，具备：
绝缘层；
导电部件，设于所述绝缘层内；
芯片，配置于所述绝缘层的第一面上，并连接于所述导电部件；以及
电极，经由电阻率比所述导电部件的电阻率高的阻挡层连接于所述导电部件，且至少一部分从所述绝缘层的第二面突出。
2.根据权利要求1所述的半导体装置，其中，
还具备与所述电极接合的凸块。
3.根据权利要求2所述的半导体装置，其中，
所述凸块将所述电极的侧面覆盖。
4.根据权利要求1所述的半导体装置，其中，
所述电极包含镍。
5.根据权利要求1所述的半导体装置，其中，
所述阻挡层设于所述绝缘层与所述导电部件之间。
6.根据权利要求1～5的任一项所述的半导体装置，其中，
所述导电部件具有：
第一导块，连接于所述芯片；
第二导块，连接于所述电极；以及
布线，连接于所述第一导块与所述第二导块之间，
所述阻挡层至少配置于所述第二导块的下表面上及侧面上、以及所述布线的下表面上，所述第二导块经由所述阻挡层而连接于所述电极。
7.一种半导体装置的制造方法，具备：
在支承基板上，形成剥离层、第一阻挡层、导电层以及第二阻挡层的工序；
在所述第二阻挡层上形成形成有第一开口部的第一绝缘层的工序；
通过将所述第一绝缘层作为掩模实施蚀刻，从而在所述第二阻挡层形成与所述第一开口部连通的第二开口部的工序；
在所述第二开口部内及所述第一开口部的下部内形成电极的工序；
在所述第一开口部的上部的内表面上形成第三阻挡层的工序；
在所述第一开口部的上部内形成第一导块，并且在所述第一绝缘层上形成电阻率比所述第三阻挡层的电阻率低的布线的工序；
在所述布线上形成形成有第三开口部的第二绝缘层的工序；
在所述第三开口部内形成与所述布线连接的第二导块的工序；
将芯片连接于所述第二导块的工序；
通过去除所述剥离层来去除所述支承基板的工序；以及
去除所述第一阻挡层、所述导电层以及所述第二阻挡层的工序。
8.根据权利要求7所述的半导体装置的制造方法，其中，
还具备将凸块接合于所述电极的工序。
9.根据权利要求7或8所述的半导体装置的制造方法，其中，
形成所述电极的工序具有经由所述导电层实施电解镀覆的工序。
10.根据权利要求7或8所述的半导体装置的制造方法，其中，
形成所述第一导块及所述布线的工序具有经由所述导电层实施电解镀覆的工序。
11.一种半导体装置的制造方法，具备：
在支承基板上形成形成有第一开口部的导电层、以及形成有与所述第一开口部连通的第二开口部的绝缘层的工序；
在所述第一开口部内及所述第二开口部的下部内形成电极的工序；
在所述第二开口部的上部内及所述绝缘层上形成导电部件的工序；
将芯片连接于所述导电部件的工序；以及
去除所述支承基板及所述导电层的工序。
12.根据权利要求11所述的半导体装置的制造方法，其中，
还具备将凸块接合于所述电极的工序。
13.根据权利要求11所述的半导体装置的制造方法，其中，
形成所述导电层及所述绝缘层的工序具有：
在所述支承基板上连续地形成所述导电层的工序；
在所述导电层上形成形成有所述第二开口部的绝缘层的工序；以及
通过将所述绝缘层作为掩模对所述导电层进行蚀刻，从而形成所述第一开口部的工序。
14.根据权利要求11～13的任一项所述的半导体装置的制造方法，其中，
形成所述电极的工序具有经由所述导电层实施电解镀覆的工序。
15.根据权利要求11～13的任一项所述的半导体装置的制造方法，其中，
形成所述导电部件的工序具有经由所述导电层及所述电极实施电解镀覆的工序。
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