WO2021017011A1 - 显示基板及显示装置 - Google Patents

显示基板及显示装置 Download PDF

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Publication number
WO2021017011A1
WO2021017011A1 PCT/CN2019/098938 CN2019098938W WO2021017011A1 WO 2021017011 A1 WO2021017011 A1 WO 2021017011A1 CN 2019098938 W CN2019098938 W CN 2019098938W WO 2021017011 A1 WO2021017011 A1 WO 2021017011A1
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WO
WIPO (PCT)
Prior art keywords
base substrate
display substrate
layer
power line
organic pattern
Prior art date
Application number
PCT/CN2019/098938
Other languages
English (en)
French (fr)
Inventor
龙跃
黄炜赟
曾超
李孟
黄耀
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to PCT/CN2019/098938 priority Critical patent/WO2021017011A1/zh
Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN201980001239.1A priority patent/CN112602199B/zh
Priority to BR112020000834A priority patent/BR112020000834A2/pt
Priority to MX2020000612A priority patent/MX2020000612A/es
Priority to RU2020101480A priority patent/RU2729699C1/ru
Priority to EP19933245.3A priority patent/EP4009373A4/en
Priority to JP2019569392A priority patent/JP7395359B2/ja
Priority to AU2019279976A priority patent/AU2019279976B1/en
Priority to US17/255,888 priority patent/US11991905B2/en
Priority to TW109126171A priority patent/TWI753513B/zh
Publication of WO2021017011A1 publication Critical patent/WO2021017011A1/zh
Priority to JP2023200957A priority patent/JP2024026201A/ja
Priority to US18/619,330 priority patent/US20240251619A1/en

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/84—Passivation; Containers; Encapsulations
    • H10K50/844—Encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N39/00—Integrated devices, or assemblies of multiple devices, comprising at least one piezoelectric, electrostrictive or magnetostrictive element covered by groups H10N30/00 – H10N35/00
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/87—Passivation; Containers; Encapsulations
    • H10K59/873—Encapsulations

Definitions

  • This application relates to the field of display technology, and in particular to a display substrate and a display device.
  • the display substrate usually includes a plurality of pixel units arrayed in the display area of the base substrate, power traces (generally referred to as VDD traces) for providing positive power signals for each pixel unit, and power traces for the display substrate
  • the cathode layer provides power traces (generally called VSS traces) for the negative power signal.
  • the present application provides a display substrate and a display device, which can improve the problem of water and oxygen erosion of the display substrate in the prior art.
  • the technical solution is as follows:
  • a display substrate is provided, and the display substrate includes:
  • a plurality of pixel units, the plurality of pixel units are located on the base substrate;
  • At least one first power line located on the base substrate
  • a barrier structure surrounds the plurality of pixel units
  • the switching structure includes a first side surface and a second side surface opposite to each other, the first side surface being closer to the plurality of pixel units than the second side surface;
  • the cathode layer is located on the side of the transfer structure away from the base substrate;
  • the first organic pattern is located on the side of the transfer structure away from the base substrate;
  • the at least one first power line includes a first part and a second part, and the first part is located on a side of the blocking structure away from the plurality of pixel units for receiving power signals, and the second part passes through
  • the switching structure is connected to the cathode layer;
  • the second part includes a first connection and a second connection connected to the transition structure, and the distance between the first connection and the blocking structure is greater than that between the second connection and the transition. The spacing between the connection structures.
  • the display substrate has a binding area, and the binding area is located on a side of the blocking structure away from the plurality of pixel units;
  • the first connection is closer to the binding area than the second connection.
  • the orthographic projection of the transfer structure on the base substrate includes a first projection area and a second projection area, and the first projection area and the blocking structure are aligned on the base substrate.
  • the projections do not overlap, and the orthographic projection of the second projection area and the blocking structure on the base substrate includes a first overlap area that overlaps each other;
  • the first projection area is close to the first part relative to the second projection area.
  • the first organic pattern covers at least part of the second side surface.
  • the second side surface includes a portion covered by the first organic pattern and the barrier structure.
  • the switching structure is a ring structure surrounding the plurality of pixel units.
  • the display substrate further includes: at least one second power line;
  • One end of the at least one second power line is located on a side of the blocking structure away from the plurality of pixel units for receiving power signals, and the other end is located between the blocking structure and the plurality of pixel units, and Connected to the cathode layer through the switching structure;
  • the orthographic projection of the first organic pattern and the at least one second power line on the base substrate includes a second overlap area that overlaps each other, and the second overlap area does not overlap with the blocking structure on the substrate.
  • the orthographic projections on the base substrate overlap.
  • one end of the at least one second power line is located in the middle of a side of the blocking structure away from the plurality of pixel units.
  • the distance between the second overlapping area and the orthographic projection of the blocking structure on the base substrate is greater than a distance threshold.
  • the pitch threshold ranges from 80 microns to 150 microns.
  • the display substrate further has: a row driving area between the plurality of pixel units and the barrier structure;
  • the distance between the orthographic projection of the at least one second power line on the base substrate and the row drive region is greater than the orthographic projection of the at least one first power line on the base substrate and the distance between the Spacing between walk-drive areas.
  • the display substrate further includes:
  • An opening is further provided in the passivation layer, the side of the transition structure close to the base substrate is connected to the at least one first power line through the opening, and the transition structure is away from the substrate One side of the substrate is connected to the cathode layer.
  • the blocking structure includes: a first blocking dam and a second blocking dam;
  • the first barrier dam is far away from the plurality of pixel units relative to the second barrier dam, and the thickness of the first barrier dam is greater than the thickness of the second barrier dam;
  • the first barrier dam includes: a first flat layer pattern, a second flat layer pattern, and a second organic pattern arranged in a direction away from the base substrate;
  • the second barrier dam includes: a third flat layer pattern and a third organic pattern arranged in a direction away from the base substrate;
  • the second flat layer pattern and the third flat layer pattern comprise the same material
  • the first organic pattern, the second organic pattern and the third organic pattern comprise the same material
  • the blocking structure includes: a first blocking dam and a second blocking dam;
  • the first barrier dam is far away from the plurality of pixel units relative to the second barrier dam, and the thickness of the first barrier dam is greater than the thickness of the second barrier dam;
  • the first barrier dam includes: a flat layer pattern and a second organic pattern that are sequentially stacked in a direction away from the base substrate;
  • the second barrier dam includes: a third organic pattern provided on the base substrate;
  • the first organic pattern, the second organic pattern and the third organic pattern comprise the same material.
  • the first barrier dam further includes: a fourth organic pattern disposed on a side of the second organic pattern away from the base substrate;
  • the second barrier dam further includes: a fifth organic pattern disposed on a side of the third organic pattern away from the base substrate;
  • the fourth organic pattern and the fifth organic pattern may include the same material.
  • the blocking structure includes: a first blocking dam and a second blocking dam;
  • the first barrier dam is far away from the plurality of pixel units relative to the second barrier dam, and the thickness of the first barrier dam is greater than the thickness of the second barrier dam;
  • the first organic pattern includes a portion directly in contact with the second barrier dam.
  • the first power line includes: a straight portion and an arc portion surrounding the area where the plurality of pixel units are located;
  • the orthographic projection of the portion of the first organic pattern that directly contacts the second barrier dam on the base substrate is located within the orthographic projection of the arc-shaped portion on the base substrate.
  • the second part of the first power line includes: a straight part and an arc part surrounding the area where the plurality of pixel units are located.
  • the first blocking dam is a first ring shape
  • the second blocking dam is a second ring shape
  • the first organic pattern and part of the third organic pattern form a third ring shape, and the orthographic projection of the third ring shape on the base substrate is located in the second ring shape on the substrate In the orthographic projection on the base substrate, the orthographic projection of the second ring on the base substrate is located in the orthographic projection of the first ring on the base substrate;
  • the third ring surrounds the plurality of pixel units.
  • the at least one first power line includes: a first metal layer; the display substrate further includes: an auxiliary metal layer located on a side of the first metal layer away from the base substrate;
  • the side of the auxiliary metal layer away from the first metal layer is in contact with the transition structure.
  • the first metal layer, the passivation layer, the first flat layer pattern, the auxiliary metal layer, the second flat layer pattern, and the first organic pattern in the display substrate are far away from the The direction of the base substrate is stacked.
  • the at least one first power line includes: a first metal layer and a second metal layer arranged in a direction away from the base substrate;
  • the side of the second metal layer away from the first metal layer is in contact with the transition structure.
  • the first metal layer, the first flat layer pattern, the second metal layer, the passivation layer, the second flat layer pattern, and the first organic pattern in the display substrate The direction of the base substrate is laminated.
  • the side surface of the first part of the at least one first power line located at one end of the blocking structure away from the plurality of pixel units is formed with a plurality of tooth-shaped protrusion structures.
  • the orthographic projection of the protrusion structure on the base substrate does not overlap with the orthographic projection of the barrier structure on the base substrate.
  • the display substrate further includes: an encapsulation film layer;
  • the packaging film layer is located on a side of the first power line away from the base substrate, and the packaging film layer covers an area surrounded by the barrier structure.
  • the display substrate further includes: a plurality of third power lines located on the base substrate;
  • the plurality of third power lines are electrically connected to the transistors in the pixel unit.
  • the orthographic projection of at least one of the plurality of third power lines on the base substrate is adjacent to the orthographic projection of the first power lines on the base substrate ;
  • the orthographic projection of the plurality of third power lines on the base substrate and the orthographic projection of the transition structure on the base substrate have an overlapping area, and within the overlapping area, A passivation layer is provided between the plurality of third power lines and the switching structure.
  • a display device in another aspect, includes: the display substrate described in the above aspect.
  • Embodiments of the present disclosure provide a display substrate and a display device.
  • the display substrate includes a base substrate, a plurality of pixel units, at least one first power line, a blocking structure, a transition structure, a cathode layer, and a first organic pattern.
  • the distance between the first connection point of the first part of the at least one first power line and the blocking structure can be larger, the water vapor brought into the first part of the first power line can be reduced.
  • the introduction of hydrophilic materials into a plurality of pixel units ensures the yield of the display substrate, thereby ensuring the display effect of the display substrate.
  • FIG. 1 is a schematic structural diagram of a display substrate provided by an embodiment of the present disclosure
  • FIG. 2 is a cross-sectional view of the display substrate shown in FIG. 1 along the BB direction;
  • FIG. 3 is a schematic diagram of a partial structure of the display substrate shown in FIG. 1;
  • FIG. 4 is a schematic structural diagram of another display substrate provided by an embodiment of the present disclosure.
  • FIG. 5 is a schematic diagram of a partial structure of a display substrate provided by an embodiment of the present disclosure.
  • FIG. 6 is a schematic structural diagram of yet another display substrate provided by an embodiment of the present disclosure.
  • FIG. 7 is a schematic diagram of a partial structure of another display substrate provided by an embodiment of the present disclosure.
  • FIG. 8 is a schematic structural diagram of still another display substrate provided by an embodiment of the present disclosure.
  • FIG. 9 is a schematic structural diagram of still another display substrate provided by an embodiment of the present disclosure.
  • FIG. 10 is a schematic structural diagram of still another display substrate provided by an embodiment of the present disclosure.
  • FIG. 11 is a schematic structural diagram of still another display substrate provided by an embodiment of the present disclosure.
  • FIG. 12 is a partial structural diagram of another display substrate provided by an embodiment of the present disclosure.
  • FIG. 13 is a partial structural diagram of still another display substrate provided by an embodiment of the present disclosure.
  • FIG. 14 is a schematic diagram of a partial structure of still another display substrate provided by an embodiment of the present disclosure.
  • FIG. 15 is a cross-sectional view of the display substrate shown in FIG. 1 along the CC direction;
  • FIG. 16 is a partial structural diagram of still another display substrate provided by an embodiment of the present disclosure.
  • FIG. 17 is a schematic structural diagram of still another display substrate provided by an embodiment of the present disclosure.
  • FIG. 18 is a schematic structural diagram of still another display substrate provided by an embodiment of the present disclosure.
  • FIG. 19 is a schematic structural diagram of still another display substrate provided by an embodiment of the present disclosure.
  • 20 is a schematic structural diagram of still another display substrate provided by an embodiment of the present disclosure.
  • FIG. 21 is a schematic structural diagram of still another display substrate provided by an embodiment of the present disclosure.
  • FIG. 22 is a flowchart of a manufacturing method of a display substrate provided by an embodiment of the present disclosure.
  • the number of power traces entering the package area is usually reduced, so as to further ensure the electrical signal transmission of the power traces, such as to ensure The electrical connection between the cathode VSS trace and the cathode.
  • the dam structure barrier structure
  • FIG. 1 is a schematic structural diagram of a display substrate provided by an embodiment of the present disclosure.
  • FIG. 2 is a cross-sectional view of the display substrate shown in FIG. 1 along the BB direction.
  • the display substrate may be a flexible panel, for example, a foldable panel.
  • the display substrate may include: a base substrate 001, a plurality of pixel units 002, at least one first power line 003, a blocking structure 004, a transition structure 005, a cathode layer 006, and a first An organic pattern 007.
  • the plurality of pixel units 002 may be located on the base substrate 001.
  • a first power line 003 is shown in FIG. 1.
  • the at least one first power line 003 is located on the base substrate 001.
  • the blocking structure (dam structure) 004 may surround a plurality of pixel units 002.
  • the transition structure 005 may include a first side 005a and a second side 005b opposite to each other, and the first side 005a is closer to the plurality of pixel units 002 than the second side 005b.
  • the cathode layer 006 may be located on the side of the transfer structure 005 away from the base substrate 001.
  • the first organic pattern 007 may be located on a side of the transfer structure 005 away from the base substrate 001.
  • the at least one first power line 003 may include a first part 0031 and a second part 0032, and the first part 0031 may be located on a side of the blocking structure 004 away from the plurality of pixel units 002 for receiving power signals .
  • the first part 0031 may be connected to a driver chip for receiving a power signal provided by the driver chip.
  • the second part 0032 can be connected to the cathode layer 006 through the transition structure 005.
  • FIG. 3 is a schematic diagram of a partial structure of the display substrate shown in FIG. 1. 1 and 3, the second part 0032 may include a first connection 0032a and a second connection 0032b connected to the transition structure 005, and the distance between the first connection 0032a and the blocking structure 004 may be greater than the first connection 0032a and the blocking structure 004. The distance between the second junction 0032b and the blocking structure 004.
  • the first connection 0032a of the second part 0032 of the at least one first power line 003 does not contact the blocking structure 004, for example, the orthographic projection of the first connection 0032a on the base substrate 001 and the blocking structure 004
  • the orthographic projections on the base substrate 001 do not overlap, and the second connection location 0032b may be located in the area covered by the barrier structure 004, for example, the second connection location 0032b may be in contact with the barrier structure 004.
  • the cathode layer 006 is not shown in FIG. 1.
  • the distance between the first connection 0032a near the first part 0031 and the blocking structure 004 is larger, the water vapor in the first part 0031 of the at least one first power cord 003 can be reduced.
  • the hydrophilic material in the blocking structure 004 is introduced into the plurality of pixel units 002, the yield of the display substrate is ensured.
  • the second connection point 0032b is far from the first part 0031 relative to the first connection point 0032a, the path for water vapor to enter is longer. Therefore, even if the distance between the second connection point 0032b and the blocking structure 004 is set to be small, The water vapor in the first part 0031 of the first power line 003 will not be introduced into the plurality of pixel units 002 either.
  • the distance between the second connection part 0032b and the blocking structure 004 is set to be small, which can reduce the area of the base substrate 001 occupied by the transition structure 005 and the blocking structure 004, and facilitate the realization of a narrow-frame display substrate .
  • each of the first connection point 0032a and the second connection point 0032b may refer to a part of the second part 0032 of the first power cord 003 that is in contact with the switching structure 005. In the embodiment of the present disclosure, it may refer to the part of the second part 0032 that is in direct contact with the transfer structure 005.
  • the shape of the two joints may be approximately the same as the shape of the overlapping area of the second portion 0032 and the orthographic projection of the transfer structure 005 on the base substrate 001.
  • the embodiments of the present disclosure provide a display substrate, which includes a base substrate, a plurality of pixel units, at least one first power line, a blocking structure, a transfer structure, a cathode layer, and a first organic pattern.
  • a display substrate which includes a base substrate, a plurality of pixel units, at least one first power line, a blocking structure, a transfer structure, a cathode layer, and a first organic pattern.
  • the display substrate may further have a binding area 00a, and the binding area 00a may be located on a side of the blocking structure 004 away from the plurality of pixel units 002.
  • the first junction 0032a is closer to the binding area 00b than the second junction 0032b.
  • closer may refer to the minimum value of the distance between each point on the first connection point 0032a and the binding area 00b, which is greater than the minimum value of the distance between each point on the second connection point 0032b and the binding area 00b.
  • the area where the orthographic projection of the plurality of pixel units 002 on the base substrate 001 is located is the active display area (AA) of the display substrate. Therefore, the blocking structure 004 can be arranged around the AA area.
  • the cathode layer 006 may completely cover the AA area.
  • the orthographic projection of the cathode layer 006 on the base substrate 001 may cover the orthographic projection of a plurality of pixel units 002 on the base substrate 001, and the cathode layer 006 is on the substrate 001
  • the orthographic projection of may be located within the orthographic projection of the area enclosed by the blocking structure 004 on the base substrate 001.
  • FIG. 4 is a schematic structural diagram of another display substrate provided by an embodiment of the present disclosure.
  • 5 is a partial structural diagram of a display substrate provided by an embodiment of the present disclosure.
  • the orthographic projection of the transfer structure 005 on the base substrate 001 may include a first projection area 005c and a first projection area 005c.
  • Two projection area 005d It can be seen in conjunction with FIG. 1 that the first projection area 005c is close to the first portion 0031 relative to the second projection area 005d.
  • the first projection area 005c and the orthographic projection of the barrier structure 004 on the base substrate 001 do not overlap, and the orthographic projection of the second projection area 005d and the barrier structure 004 on the base substrate 001 include a first overlap area 00b that overlaps each other.
  • the organic material made of the barrier structure 004 is a hydrophilic material
  • the first projection area 005c of the orthographic projection of the transfer structure 005 on the base substrate 001 is different from the orthographic projection of the barrier structure 004 on the base substrate 001. Overlapping can prevent the water vapor in the first part 0031 from entering the plurality of pixel units 002 through the hydrophilic material covering the transfer structure 005, thereby further ensuring the display effect of the display substrate.
  • the width of the junction between the switching structure 005 and the first power line 003 can be wider, so as to ensure that the contact resistance between the switching structure 005 and the first power line 003 is as small as possible.
  • the orthographic projection of the overlap on the base substrate 001 is the first projection area 005c, which overlaps the orthographic projection of the first power line 003 on the base substrate 001.
  • the width of the part of the transfer structure 005 far away from the overlap can be narrower, thereby reducing the influence of the capacitive coupling of other signal lines arranged on the side of the transfer structure 005 close to the base substrate 001, for example, the The influence of the capacitive coupling of the data line.
  • the second side surface 005b of the transition structure 005 may be covered by the blocking structure 004. That is, the second side surface 005b of the transition structure 005 of the second projection area 005d may be covered by the blocking structure 004.
  • the area of the base substrate 001 occupied by the transfer structure 005 and the barrier structure 004 can be reduced, which facilitates the realization of a narrow frame display substrate.
  • the second projection area 005d of the transition structure 005 is farther away from the first portion 0031 of the at least one first power cord 003, and is far from the position of the first wire inlet 00c, and the path for water vapor to enter is longer. Even if the second side surface 005b of the transfer structure 005 is covered by the blocking structure 004, water vapor will not enter the pixel unit 002.
  • the part of the blocking structure 004 through which the power cord passes may be called a port (port), for example, the part through which the first power cord 003 passes may be called a first port 00c.
  • the transfer structure 005 may be a ring structure surrounding a plurality of pixel units 002, so that the cathode layer 006 is connected to at least one first power line 003 through the transfer structure 005, and is guaranteed to be the display substrate
  • the power signal provided by the pixel unit 002 is uniform in potential, and the display effect is better.
  • the display substrate may further include: at least one second power line 008.
  • One end 008a of the at least one second power line 008 is located on the side of the barrier structure 004 away from the plurality of pixel units 002 for receiving power signals, and the other end 008b is located between the barrier structure 004 and the plurality of pixel units 002 and passes through
  • the connection structure 005 is connected to the cathode layer 006, so that the second power line 008 can provide a power signal for the cathode layer 006.
  • each second power cord 008 is located outside the area enclosed by the blocking structure 004, and the other end is located within the area enclosed by the blocking structure 004. That is, each second power line 008 can pass through the blocking structure 004 into the area enclosed by the blocking structure 004.
  • the part through which the second power cord 008 passes can be referred to as the second wire inlet 00d.
  • FIG. 1 shows two second power lines 008, and one end 008a of each second power line 008 can be connected to a driving chip for receiving a power signal provided by the driving chip.
  • the first organic pattern 007 can cover at least a part of the second side surface 005b of the transfer structure 005, and the first organic pattern 007 and at least one second power line 008 are on the base substrate.
  • the orthographic projection on 001 includes a second overlapping area 00e that overlaps each other, and the second overlapping area 00e does not overlap with the orthographic projection of the barrier structure 004 on the base substrate 001.
  • the risk of the second side surface 005b of the transfer structure 005 being corroded by water vapor or oxygen due to etching defects can be reduced, thereby ensuring the transfer structure 005 can effectively transmit the power signal from the first power line 003.
  • the organic material used to make the first organic pattern 007 is usually a hydrophilic material
  • the second overlapping area 00e does not overlap the orthographic projection of the barrier structure 004 on the base substrate, that is, the first organic pattern 007 is
  • the barrier structures 004 are arranged at intervals, which can reduce the water vapor brought in by the end 008a of the second power line 008 for receiving power signals through the barrier structure 004 and the first organic pattern 007 to be introduced into the pixel unit 002, ensuring the yield of the display substrate.
  • one end 008a of the at least one second power line 008 may be located in the middle of the side of the blocking structure 004 away from the plurality of pixel units 002, for example, may be located in the middle of the binding area 00a.
  • the middle portion may be the area where the longitudinal axis X of the base substrate is located, and the longitudinal axis X is an axis parallel to the data line on the base substrate 001.
  • the distance between the longitudinal axis X and one side of the display substrate may be substantially equal to the distance between the longitudinal axis X and the other side of the display substrate.
  • the one side and the other side are both substantially parallel to the extending direction of the data line.
  • any one of the two sides that are substantially parallel to the extending direction of the data line in the display substrate, for example, the included angle with the extending direction of the data line may range from 0 degree to 10 degrees.
  • the “approximately” in the embodiments of the present disclosure refers to an allowable error range within 15%. If the distance is “approximately” the same, it can be that the distance deviation between the two is not more than 15%, and the extension direction is “approximately parallel” can be that the angle between the two extension directions is between 0 degrees and 30 degrees, such as 0 degrees to 10 Degrees, 0 degrees to 15 degrees, etc., the shape "approximately” can be the same type, such as rectangle, broken line, arc, strip, "L” shape, etc., the area is "approximately” the same can be two The area deviation does not exceed 15%.
  • the display substrate may include two second power lines 008.
  • the two second power lines 008 may be arranged adjacently in the middle of a side of the blocking structure 004 away from the plurality of pixel units 002.
  • the two second power lines 008 can also be arranged in the middle of the side of the blocking structure 004 away from the plurality of pixel units 002 with the longitudinal axis X of the base substrate as an axisymmetric interval.
  • the embodiment of the present disclosure does not limit the location of the second power cord 008.
  • the two second power lines 008 may be an integral structure.
  • the two second power lines 008 are integrated, that is, when there is one second power line 008, one end 008a of the first power line 008 is located on the side of the blocking structure 004 away from the plurality of pixel units 002
  • the middle part for example, in the middle part of the binding area 00a, may be the distance between one end 008a of the second power cord 008 and the longitudinal axis X is less than the distance between one end 008a of the second power cord 008 and the display substrate substantially parallel to the longitudinal axis X The distance between any of the sides.
  • the folding line of the foldable panel may be perpendicular to the longitudinal axis X.
  • the fold line of the foldable panel may be the vertical line of the longitudinal axis X.
  • the first power cord 003 may include two first parts 0031.
  • the two first parts 0031 may be substantially symmetrically arranged at the edge of the blocking structure 004 on one side away from the plurality of pixel units 002 with the longitudinal axis X of the base substrate 001 as the axis.
  • the first power cord 003 may include two first parts 0031.
  • the two first parts 0031 may be located on both sides of the longitudinal axis X, such as located on both sides of the binding area 00a.
  • the first power cord 003 may include two first parts 0031.
  • the parts of the two first parts 0031 near the first wire inlet 00c are located on both sides of the display substrate, and are also close to two sides parallel to the longitudinal axis X, respectively.
  • the second power line 008 located in the middle and the first power line 003 located at the edge can simultaneously provide power signals to the cathode layer 006 in the display substrate, which can further alleviate the difference caused by the voltage drop.
  • the problem of the large difference in the potential of the power signal loaded by the cathode layer 006 in the region is that the cathode layer 006 has better long range uniformity (LRU) and better display effect.
  • the second power line 008 at the middle and the first power line 003 at the edge can both provide power signals for the cathode layer 006 in the display substrate.
  • the design of the second power cord 008 in the embodiment of the present disclosure can also reduce the corrosion of water and oxygen and ensure good packaging performance.
  • more second power lines 008 can be provided, and more second power lines 008 can provide power signals to the cathode layer 006 to ensure that each area of the cathode layer 006 The uniformity of the potential of the display substrate has a better display effect.
  • the first power line 003 and the second power line 008 are both used to provide power signals for the cathode layer 006, the first power line 003 and the second power line 008 It can also be called a VSS power supply line or a VSS trace.
  • FIG. 2 shows a cross-sectional view of a part of the first power line 003 entering the area surrounded by the blocking structure 004.
  • the hierarchical structure of the portion of the second power line 008 that enters the area surrounded by the blocking structure 004 is the same as the first power line 003.
  • the spacing d between orthographic projections may be greater than the spacing threshold.
  • the pitch threshold may range from 80 micrometers ( ⁇ m) to 150 ⁇ m.
  • the distance threshold may be a threshold that can prevent water vapor from entering the pixel unit 002 that is determined through experiments in advance. That is, when the distance between the second overlapping area 00e and the blocking structure 004 is greater than the distance threshold, it is difficult for water vapor to enter the pixel unit 002 in the display substrate.
  • the distance threshold may be a threshold that can prevent water vapor from entering the pixel unit 002 that is determined through experiments in advance. That is, when the distance between the second overlapping area 00e and the blocking structure 004 is greater than the distance threshold, water vapor will not enter the pixel unit 002 in the display substrate.
  • the display substrate may further have: a row driving area 00f located between the plurality of pixel units 002 and the barrier structure 004.
  • the distance between the orthographic projection of the at least one second power line 008 on the base substrate 001 and the row driving area 00f may be greater than the distance between the orthographic projection of the at least one first power line 003 on the base substrate and the row driving area 00f Pitch.
  • the at least one second power line 008 in the middle is farther away from the row driving area 00f than the at least one first power line 003.
  • the first power line 003, the second power line 008 and the cathode layer 006 are not shown in FIG. 4.
  • the minimum value of the distance between each point on each second power line 008 and the row driving area 00f is greater than the distance between each point on any first power line 003 and the row driving area 00f Minimum value.
  • the distance h1 between the point a1 on the at least one second power line 008 and the row driving area 00f is greater than the distance between the point b1 on the at least one first power line 003 and the row driving area 00f Distance h2.
  • the row driving area 00f may be provided with multiple cascaded shift register units, and the multiple cascaded shift register units may be used to drive each row of pixel units 002.
  • the display substrate may have two row driving regions 00f, and the two row driving regions 00f may be arranged in a plurality of pixel units symmetrically with the longitudinal axis X of the base substrate 001 as an axis. 002 on both sides.
  • the display substrate may further include: a passivation layer 009, and the passivation layer 009 may cover at least one first power line 003.
  • FIG. 7 is a schematic diagram of a partial structure of another display substrate provided by an embodiment of the present disclosure.
  • the passivation layer 009 is also provided with an opening 009a, the side of the transfer structure 005 close to the base substrate 001 can be connected to at least one first power line 003 through the opening 009a, and the transfer structure 005 is away from one side of the base substrate 001.
  • the side may be connected to the cathode layer 006.
  • 009a shown in FIG. 7 is an opening provided in the passivation layer 009. That is, in FIG. 7 except for the area where the opening 009a is located, the remaining areas are covered with the passivation layer 009.
  • the at least one first power line 003 is easily corroded by water vapor or oxygen during the process of preparing the display substrate, by covering the passivation layer 009 on the at least one first power line 003, it can be ensured that when other film layers are subsequently formed , The at least one first power line 003 will not be corroded by water vapor or oxygen, ensuring that the at least one first power line 003 can provide a power signal for the cathode layer 006 to ensure the display effect of the display substrate.
  • the opening in the passivation layer 009 may be a via hole or may be a slot, which is not limited in the embodiment of the present disclosure.
  • the material of the passivation layer 009 may include one or more inorganic oxides such as SiNx (silicon nitride), SiOx (silicon oxide), and SiOxNy (silicon oxynitride). The embodiment of the present disclosure does not limit the material of the passivation layer 009.
  • the passivation layer 009 can also cover the at least one second power line 008 to ensure that the at least one second power line 008 will not be corroded by water vapor or oxygen, and ensure the display substrate display effect.
  • the blocking structure 004 may be a ring structure surrounding a plurality of pixel units 002, and is used to block the display substrate in the area enclosed by the blocking structure 004 The organic layer overflows.
  • the blocking structure 004 may include: a first blocking dam 0041 and a second blocking dam 0042.
  • the first barrier dam 0041 is farther away from the plurality of pixel units 002 than the second barrier dam 0042, and the thickness of the first barrier dam 0041 may be greater than the thickness of the second barrier dam 0042.
  • the blocking structure 004 may also include one blocking dam, or two or more blocking dams, which are not limited in the embodiment of the present disclosure.
  • FIG. 8 is a schematic structural diagram of another display substrate provided by an embodiment of the present disclosure.
  • the first barrier dam 0041 may include: a first flat layer pattern 010, a second flat layer pattern 011, and a second organic pattern 012 arranged in a direction away from the base substrate 001.
  • the second barrier dam 0042 may include: a third flat layer pattern 013 arranged in a direction away from the base substrate 001, and a third organic pattern 014.
  • the second flat layer pattern 011 and the third flat layer pattern 013 may include the same material
  • the first organic pattern 007, the second organic pattern 012, and the third organic pattern 014 may include the same material.
  • the second flat layer pattern 011 and the third flat layer pattern 013 can be made of the same material and made by the same patterning process
  • the first organic pattern 007, the second organic pattern 012 and the third organic pattern 014 can be made of the same material , And made by the same patterning process.
  • the first flat layer pattern 010 may belong to the first flat layer
  • the second flat layer pattern 011 and the third flat layer pattern 013 may belong to the second flat layer
  • the first organic pattern 007, and the second organic pattern 012 and the third organic pattern 014 may belong to a first organic layer
  • the first organic layer may be a pixel definition layer (PDL).
  • the materials for forming the first flat layer, the second flat layer, and the first organic layer may include organic materials such as resin.
  • organic materials such as resin. The embodiment of the present disclosure does not limit this.
  • the first barrier dam 0041 may include: a flat layer pattern 015 and a second organic pattern 012 that are sequentially stacked in a direction away from the base substrate 001.
  • the second blocking dam 0042 may include: a third organic pattern 014 provided on the base substrate 001.
  • the first organic pattern 007, the second organic pattern 012, and the third organic pattern 014 may include the same material.
  • the first organic pattern 007, the second organic pattern 012 and the third organic pattern 014 can be made of the same material and made by the same patterning process.
  • the flat layer pattern 015 may belong to a flat layer
  • the first organic pattern 007, the second organic pattern 012, and the third organic pattern 014 may belong to the first organic layer.
  • the material for making the flat layer may include organic materials such as resin.
  • organic materials such as resin.
  • the embodiment of the present disclosure does not limit this.
  • the opening 015a shown in FIG. 7 is an area not covered by the flat layer pattern 015.
  • the flat layer pattern 015 can cover the boundary of the portion of the first power line 003 in the area surrounded by the blocking structure 004.
  • the opening 009a of the passivation layer 009 is on the base substrate 001.
  • the overlap area between the projection and the overlap area can cover the overlap area between the orthographic projection of the opening 015a of the flat layer pattern 015 on the base substrate and the overlap area. That is, in the overlapping area, the size of the opening 009a of the passivation layer 009 is larger than the size of the opening 015a of the flat layer pattern 015.
  • the first barrier dam 0041 has one more flat layer pattern relative to the second barrier dam 0042, so that the thickness of the first barrier dam 0041 can be greater than the thickness of the second barrier dam 0042. Prevent overflow of the organic layer.
  • FIG. 9 is a schematic structural diagram of still another display substrate provided by an embodiment of the present disclosure.
  • the first barrier dam 0041 may further include: a fourth organic pattern 016 disposed on the side of the second organic pattern 012 away from the base substrate.
  • the second blocking dam 0042 may include: a fifth organic pattern 017 disposed on a side of the third organic pattern 014 away from the base substrate 001.
  • the fourth organic pattern 016 and the fifth organic pattern 017 may include the same material.
  • the fourth organic pattern 016 and the fifth organic pattern 017 can be made of the same material and made by the same patterning process.
  • both the fourth organic pattern 016 and the fifth organic pattern 017 may belong to a second organic layer, and the second organic layer may be a photo spacer (PS).
  • PS photo spacer
  • the material made of the second organic layer may include organic materials such as resin.
  • organic materials such as resin. The embodiment of the present disclosure does not limit this.
  • FIG. 10 is a schematic structural diagram of still another display substrate provided by an embodiment of the present disclosure. It can be seen with reference to FIG. 10 that the first organic pattern 007 may cover the second side surface 005b of the transfer structure 005. 1, 4, 6 and 10, the first blocking dam 0041 may be a first ring shape, and the second blocking dam 0042 may be a second ring shape.
  • Part of the patterns in the first organic pattern 007 and the third organic pattern 014 may form a third ring, and the orthographic projection of the third ring on the base substrate 001 may be located in the orthographic projection of the second ring on the base substrate 001 Inside, the orthographic projection of the second ring on the base substrate 001 may be located within the orthographic projection of the first ring on the base substrate 001.
  • the third ring shape may surround a plurality of pixel units 002.
  • the shape of the third organic pattern 014 may be substantially the same as the shape of the second barrier dam 0042, that is, the third organic pattern 014 is also annular.
  • the partial pattern may be a pattern in the third organic pattern 014 that is located on the side of the first organic pattern 007 close to the plurality of pixel units 002.
  • the partial pattern may be a pattern on the left, upper, and right sides of the third organic pattern 014.
  • the first organic pattern 007 may include a portion directly in contact with the second barrier dam 0042.
  • the first power cord 003 may include two first parts 0031 and one second part 0032.
  • the two first parts 0031 may be symmetrically arranged on both sides of the base substrate 001 about the longitudinal axis X of the base substrate 001.
  • the part of the two first parts 0031 near the first inlet 00c is located on the display substrate.
  • the two sides are close to one of the two sides parallel to the longitudinal axis X.
  • FIG. 4 shows the first inlets 00c of the two first parts 0031.
  • the second part 0032 may surround the plurality of pixel units 002, and two ends of the second part 0032 may be connected to a first part 0031 respectively.
  • first part 0031 and the second part 0032 may be in direct contact, for example, as an integral structure.
  • the second power line 008 may include: a straight portion 0032c and an arc-shaped portion 0032d surrounding the area where the plurality of pixel units 002 are located.
  • the second portion 0032 may include: a straight portion 0032c and an arc portion 0032d surrounding the area where the plurality of pixel units 002 are located.
  • the second portion 0032 of the first power cord 003 may be a non-closed structure.
  • the embodiment of the present disclosure is described with the second portion 0032 surrounding at least two sides of the display substrate.
  • the orthographic projection of the portion of the first organic pattern 007 that is in direct contact with the second barrier dam 0042 on the base substrate 001 may be located within the orthographic projection of the arc-shaped portion 0032d on the base substrate 001. That is, the orthographic projection of the portion of the first organic pattern 007 in direct contact with the second barrier dam 0042 on the base substrate 001 does not exceed the orthographic projection of the arc-shaped portion 0032d on the base substrate 001.
  • the arc-shaped portion 0032d is close to the first portion 0031 of the at least one first power line 003 for receiving power signals relative to the straight side portion 0032c.
  • At least one first power line 003 may include: a first metal layer 003a.
  • the display substrate may further include: an auxiliary metal layer 018 located on a side of the first metal layer 003a away from the base substrate.
  • the side of the auxiliary metal layer 018 away from the first metal layer 003a may be in contact with the transition structure 005, and the orthographic projection of the auxiliary metal layer 018 on the base substrate 001 may be in the same position as the barrier structure 004.
  • the orthographic projections on the base substrate 001 overlap.
  • the orthographic projection of the auxiliary metal layer 018 on the base substrate 001 includes a portion located in the area surrounded by the orthographic projection of the barrier structure 004 on the base substrate 001.
  • FIG. 12 is a partial structural diagram of still another display substrate provided by an embodiment of the present disclosure.
  • the orthographic projection of the auxiliary metal layer 018 on the base substrate 001 includes a portion located within the orthographic projection of the second barrier dam 0042 on the base substrate 001.
  • the side of the first metal layer 003a away from the base substrate 001 is not provided with the auxiliary metal layer 018, that is, the auxiliary metal layer 018 in the region where the barrier structure 004 is located is removed That is, the auxiliary metal layer 018 in the area where the first wire inlet 00c is located is removed.
  • the side of the barrier structure 004 away from the plurality of pixel units 002 may be provided with an auxiliary metal layer 018, and the area surrounded by the barrier structure 004 may also be provided with an auxiliary metal layer 018.
  • the shape of the boundary of the auxiliary metal layer 018 may be approximately the same as the shape of the boundary of the first metal layer 003a, or the shape of the boundary of the auxiliary metal layer 018 may also be different from the shape of the boundary of the first metal layer 003a. The embodiment does not limit this.
  • the power signal received by the first metal layer 003a can be transmitted to the transfer structure 005 through the auxiliary metal layer 018 disposed in the opening of the passivation layer 009.
  • the power signal is transmitted to the cathode layer 006 through the switching structure 005.
  • the side of the auxiliary metal layer 018 away from the base substrate 001 may be covered by a second flat layer including the second flat layer pattern 011 and the third flat layer pattern 013 near the edge.
  • the second flat layer can be used to prevent the sidewall of the auxiliary metal layer 018 from being poorly displayed due to etching defects.
  • the orthographic projection and blocking structure of the auxiliary metal layer 018 on the base substrate 001 can be made The orthographic projection of 004 on the base substrate 001 does not overlap, so that water vapor can be blocked from entering the barrier structure 004 and enter the path of the pixel unit 002 along the second flat layer, ensuring the display effect of the display substrate.
  • FIG. 13 is a partial structural diagram of another display substrate provided by an embodiment of the present disclosure.
  • the orthographic projection of the part of the auxiliary metal layer 018 in contact with the first metal layer 003a on the base substrate 001 can be located within the orthographic projection of the auxiliary metal layer 018 on the base substrate 001, so that The boundary of the first metal layer 003a is separated from the boundary of the auxiliary metal layer 018 to prevent the first metal layer 003a and the auxiliary metal layer 018 from being corroded by water vapor or oxygen.
  • FIG. 14 is a partial structural diagram of still another display substrate provided by an embodiment of the present disclosure. 010a shown in FIG. 14 is an opening provided in the first flat layer.
  • 011a shown in FIG. 14 is an opening provided in the second flat layer. That is, in FIG. 14 except for the area where the opening 011a is located, the remaining areas are covered with the second flat layer.
  • the first metal layer 003a, the passivation layer 009, the first flat layer pattern 010, the auxiliary metal layer 018, the second flat layer pattern 011, and the first organic pattern 007 in the display substrate The direction of the base substrate 001 is laminated. That is, the first power line 003, the passivation layer 009, the first flat layer, the auxiliary metal layer 018, the second flat layer, and the first organic layer in the display substrate may be stacked along the direction of the base substrate 001.
  • both the first metal layer 003a and the auxiliary metal layer 018 may include three metal film layers.
  • the materials of the three metal film layers may be titanium (Ti), aluminum (Al), and Ti in order.
  • FIG. 15 is a cross-sectional view of the display substrate shown in FIG. 1 along the CC direction.
  • the at least one second power line 008 may include: a second metal layer 008c.
  • the display substrate may further include: an auxiliary wiring layer 019 located on a side of the second metal layer 008c away from the base substrate 001.
  • the side of the auxiliary wiring layer 019 away from the second metal layer 008c may be in contact with the transition structure 005, and the orthographic projection of the auxiliary wiring layer 019 on the base substrate 001 may be the same as the barrier structure
  • the orthographic projection of 004 on the base substrate 001 does not overlap.
  • the orthographic projection of the auxiliary wiring layer 019 on the base substrate 001 includes a portion located in an area surrounded by the orthographic projection of the barrier structure 004 on the base substrate 001.
  • FIG. 16 is a partial structural diagram of still another display substrate provided by an embodiment of the present disclosure.
  • the orthographic projection of the auxiliary wiring layer 019 on the base substrate 001 includes a portion located in the area surrounded by the orthographic projection of the second barrier dam 0042 on the base substrate 001.
  • the side of the second metal layer 008c away from the base substrate 001 is not provided with the auxiliary wiring layer 019, that is, the auxiliary wiring layer in the region where the barrier structure 004 is located 019 is removed, that is, the auxiliary wiring layer 019 in the area where the second cable inlet 00d is located is removed.
  • the side of the barrier structure 004 away from the plurality of pixel units may be provided with an auxiliary wiring layer 019, and the area included in the barrier structure 004 may be provided with an auxiliary wiring layer 019.
  • the shape of the boundary of the auxiliary wiring layer 019 may be substantially the same as the shape of the boundary of the second metal layer 008c, or the shape of the boundary of the auxiliary wiring layer 019 may be different from the shape of the boundary of the second metal layer 008c.
  • the embodiment of the present disclosure does not limit this.
  • the at least one first power line 003 includes: a first metal layer 003a and a third metal layer 003b arranged in a direction away from the base substrate 001. A side of the third metal layer 003b away from the first metal layer 003a is in contact with the transfer structure 005.
  • the orthographic projection of the first metal layer 003a on the base substrate 001 and the orthographic projection of the third metal layer 003b on the base substrate 001 may be the same as those of the barrier structure 004 on the base substrate 001.
  • the orthographic projections overlap. That is, the first part 0031 of the first metal layer 003a and the third metal layer 003b away from the plurality of pixel units 002 can both be used to receive power signals, so that they can pass through the first metal layer 003a and the third metal layer 003b.
  • the two metal layers transmit the power signal to the cathode layer 006, which can reduce the resistance, thereby reducing the voltage drop of the power signal.
  • the orthographic projection of the first metal layer 003a on the base substrate 001 may not overlap with the contact area of the third metal layer 003b and the transition structure 005.
  • the orthographic projection of the first metal layer 003a on the base substrate 001 may overlap with the contact area of the third metal layer 003b and the transition structure 005.
  • the first flat layer can cover the other end of the first metal layer 003a close to the plurality of pixel units 002, so as to reduce the other end of the first metal layer 003a from being corroded by oxygen or water vapor, or can reduce the corrosion caused by the side surface of the metal layer.
  • the final display is poor due to defects.
  • the first metal layer 003a, the first flat layer pattern 010, the third metal layer 003b, the passivation layer 009, the second flat layer pattern 011, and the first organic pattern in the display substrate 007 can be stacked in a direction away from the base substrate 001. That is, the first metal layer pattern 003a, the first flat layer, the third metal layer 003b, the passivation layer 009, the second flat layer, and the first organic layer in the display substrate may be stacked along the direction of the base substrate 001 Set up.
  • both the first metal layer 003a and the third metal layer 003b may include three metal film layers.
  • the materials of the three metal film layers may be Ti, Al and Ti in order.
  • the second barrier dam 0042 when the first barrier dam 0041 further includes: a fourth organic pattern 016 disposed on the side of the second organic pattern 012 away from the base substrate, the second barrier dam 0042 further includes: When the fifth organic pattern 017 disposed on the side of the third organic pattern 014 away from the base substrate 001, the second organic layer including the fourth organic pattern 016 and the fifth organic pattern 017 may be disposed on the first organic layer away from the substrate. One side of the substrate 001.
  • FIG. 19 is a schematic structural diagram of still another display substrate provided by an embodiment of the present disclosure.
  • the side surface of the first part 0031 of the at least one first power line 003 located at the end of the blocking structure 004 away from the plurality of pixel units 002 is formed with a plurality of tooth-shaped convex structures, which can be further extended The entry path of water vapor prevents water vapor from being introduced into the multiple pixel units 002.
  • the orthographic projection of the raised structure on the base substrate 001 does not overlap with the orthographic projection of the barrier structure 004 on the base substrate 001.
  • the side surface of the other end of the first part 0031 of the at least one first power line 003 located in the area enclosed by the blocking structure 004 may be flat, that is, the first part 0031 of the at least one first power line 003 is located around the blocking structure 004
  • the side surface of the other end in the formed area does not form a convex structure.
  • the transfer structure 005 is prepared through the processes of exposure, development, and etching in sequence. In the etching process, an etchant is needed to etch the film. If the first part 0031 of the first power line 003 is located in the area enclosed by the barrier structure 004, the side surface of the other end is also set as a tooth-shaped protrusion The structure causes the etchant to remain between the adjacent protruding structures of the first power line 003, so that the sidewall of the other end of the first portion 0031 of the first power line 003 is corroded.
  • the side surface of the other end of the first part 0031 of the first power line 003 located in the area enclosed by the blocking structure 004 is set as a plane, which can avoid the sidewall of the first power line 003 during the manufacturing process of the display substrate. It is corroded and pierces the relatively brittle passivation layer 009 on the side of the first power line 003 away from the base substrate 001 to ensure the quality of the passivation layer 009.
  • the side surface of the first portion 0031 of the at least one first power line 003 away from the end of the plurality of pixel units 002 is also formed with a plurality of tooth-shaped protrusion structures, which can extend the water vapor along the first power line 003 The entry path avoids the introduction of water vapor into the multiple pixel units 002.
  • the side surface of the other end 008b of the at least one first power line 003 in the area enclosed by the blocking structure 004 may be flat.
  • the display substrate may further include a plurality of third power lines 020, and the plurality of third power lines 020 may be located on the base substrate 001.
  • the plurality of third power lines 020 are electrically connected to the transistors in the pixel unit 002 in the display substrate. For example, it may be connected to the source or drain of the transistor in the pixel unit 002.
  • the third power line 020 can be used to provide a positive power signal for the transistor in the pixel unit 002, so the third power line 020 can also be referred to as a VDD power line or a VDD wiring.
  • the plurality of third power lines 020 may be symmetrically arranged on both sides of at least one first power line 003.
  • the display substrate may include: four third power lines 020, of which two third power lines 020 may be located in the middle of a side of the blocking structure 004 away from the plurality of pixel units 002, and the two third power lines 020
  • the power line 020 may be arranged on both sides of the second power line 008 symmetrically with the longitudinal axis X of the base substrate 001 as an axis.
  • the remaining two third power lines 020 may both be located at the edges of the blocking structure on a side away from the plurality of pixel units 002.
  • Each third power line 020 may be located at a side of a first part 0031 of the first power line 003 close to the second power line 008.
  • the side surfaces of the plurality of third power lines 020 located at one end of the blocking structure 004 away from the plurality of pixel units 002 may also be formed with a plurality of tooth-shaped protrusion structures, so as to extend the water vapor along the third power line 020.
  • the entry path avoids the introduction of water vapor into the multiple pixel units 002.
  • the side surface of the other end of the third power line 0200 located in the area enclosed by the blocking structure 004 may be flat.
  • the display substrate may further include: an encapsulation film layer 021.
  • the packaging film layer 021 may be located on a side of the plurality of first power lines away from the base substrate 001, and the packaging film layer 021 may cover the area enclosed by the barrier structure 004.
  • the boundary of the region 00g covered by the encapsulation film layer 021 may be located on the side of the barrier structure 004 away from the plurality of pixel units 002.
  • the packaging film layer 021 may include: a first film layer 0211, a second film layer 0212, and a third film layer 0213 stacked in a direction away from the base substrate 001.
  • the first film layer 0211 and the third film layer 0213 may be made of inorganic materials, and the second film layer 0212 may be made of organic materials.
  • the first film layer 0211 and the third film layer 0213 may be made of one or more inorganic oxides such as SiNx, SiOx, and SiOxNy.
  • the second film layer 0212 may be made of resin material.
  • the resin may be a thermoplastic resin or a thermoplastic resin, the thermoplastic resin may include an acrylic (PMMA) resin, and the thermosetting resin may include an epoxy resin.
  • the second film layer 0212 may be located in the area enclosed by the barrier structure 004, and the first film layer 0211 and the third film layer 0213 may cover the area enclosed by the barrier structure 004 and cover the barrier structure 004. That is, the orthographic projection of the barrier structure 004 on the base substrate 001 is located in the area covered by the packaging film layer 021, thereby ensuring that the packaging film layer 021 effectively encapsulates the various structures in the area enclosed by the barrier structure 004.
  • the second film layer 0212 may be produced by an ink jet printing (IJP) method.
  • the first film layer 0211 and the third film layer 0213 may be made by a chemical vapor deposition (chemical vapor deposition, CVD) method.
  • FIG. 20 is a schematic structural diagram of still another display substrate provided by an embodiment of the present disclosure.
  • a buffer layer 022, a semiconductor layer 023, a gate insulating layer 024, a gate electrode 025, an interlayer dielectric layer 026 and a source-drain layer 027 may be sequentially disposed on the base substrate 001.
  • the layer 027 may include a source electrode 0271 and a drain electrode 0272.
  • the source electrode 0271 and the drain electrode 0272 are spaced apart from each other and may be connected to the semiconductor layer 023 through via holes, respectively.
  • a passivation layer 009, a first flat layer 028, a second flat layer 029, and a light emitting element are sequentially arranged along the direction of the source and drain layer 027 away from the base substrate 001.
  • the light-emitting element may include an anode layer 030, a light-emitting layer 031, and a cathode layer 006 stacked in this order.
  • the anode layer 030 can be electrically connected to the drain electrode 0272 through via holes.
  • the gate 025, the source 0271 and the drain 0272 constitute a transistor, and each light-emitting element and the transistor connected to it can constitute a pixel unit 002.
  • the first metal layer 003a included in the first power line 003 may be provided in the same layer as the source and drain layer 027.
  • the switching structure 005 can be arranged in the same layer as the anode layer 030 of the pixel.
  • the transfer structure 005 may include three film layers.
  • the materials of the three film layers may be: indium tin oxide (ITO), silver (Ag), and ITO in order.
  • FIG. 21 is a schematic structural diagram of still another display substrate provided by an embodiment of the present disclosure.
  • the orthographic projection of the plurality of third power lines 020 on the base substrate 001 may overlap with the orthographic projection of the transition structure 005 on the base substrate 001.
  • a passivation layer 009 may be provided between the plurality of third power lines 020 and the transfer structure 005.
  • the plurality of third power lines 020 are not in contact with the switching structure 005.
  • the embodiments of the present disclosure provide a display substrate, which includes a base substrate, a plurality of pixel units, at least one first power line, a blocking structure, a transfer structure, a cathode layer, and a first organic pattern.
  • a display substrate which includes a base substrate, a plurality of pixel units, at least one first power line, a blocking structure, a transfer structure, a cathode layer, and a first organic pattern.
  • FIG. 22 is a flowchart of a manufacturing method of a display substrate provided by an embodiment of the present disclosure. This method can be used to manufacture the display substrate provided in the above embodiments. It can be seen with reference to FIG. 22 that the method may include:
  • Step 101 Provide a base substrate.
  • Step 102 forming a plurality of pixel units, at least one first power line, a blocking structure, a transition structure, a first organic pattern, and a cathode layer on the base substrate.
  • the at least one first power line 003 includes a first part 0031 and a second part 0032.
  • the first part 0031 may be located on the side of the blocking structure 004 away from the plurality of pixel units 002, and after receiving power information, the second part 0032 may It is connected to the cathode layer 006 through the transition structure 005.
  • the second part 0032 may include a first connection 0032a and a second connection 0032b connected to the transition structure 005, and the distance between the first connection 0032a and the blocking structure 004 is larger than the second connection 0032b and the blocking structure 004 The spacing between.
  • At least one first power line 003 may be formed on the base substrate 001 first, and then the blocking structure 004 and the transfer structure are formed on the side of the first power line 003 away from the base substrate 001. Connect structure 005. Then, a first organic pattern 007 is formed on the side of the transfer structure 005 away from the base substrate 001, and finally a cathode layer 006 is formed on the side of the first organic pattern 007 away from the base substrate 001.
  • the at least one first power line 003 and the source and drain of the thin film transistor in the pixel unit 002 can be formed by a patterning process.
  • the blocking structure 004 can be formed during the formation of the flat layer, the pixel defining layer and the supporting layer.
  • the first organic pattern 005 may be formed during the formation of the pixel defining layer.
  • the transfer structure 005 and the anode layer 030 in the pixel unit 002 can be formed by a patterning process.
  • the embodiments of the present disclosure provide a method for manufacturing a display substrate.
  • the method may include sequentially forming a plurality of pixel units on a base substrate, at least one first power line, a blocking structure, and a transition structure, The first organic pattern, and the cathode layer.
  • the distance between the first connection point of the first part of the at least one first power line and the blocking structure can be larger, the water vapor brought into the first part of the first power line can be reduced.
  • the introduction of hydrophilic materials into a plurality of pixel units ensures the yield of the display substrate, thereby ensuring the display effect of the display substrate.
  • the embodiments of the present disclosure also provide a display device, which may include: the display substrate described in the foregoing embodiment.
  • the display device may be a folding display device, for example, a liquid crystal panel, an electronic paper, an organic light-emitting diode (OLED) panel, an active-matrix organic light-emitting diode (AMOLED) ) Panels, mobile phones, tablet computers, televisions, monitors, notebook computers, digital photo frames, navigators and other products or components with display functions.
  • OLED organic light-emitting diode
  • AMOLED active-matrix organic light-emitting diode

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Abstract

本申请公开了一种显示基板及显示装置，涉及显示技术领域。该显示基板包括衬底基板，多个像素单元，至少一条第一电源线，阻挡结构，转接结构，阴极层，以及第一有机图案。通过将靠近至少一条第一电源线中第一部分的第一区域与转接结构的连接处，与阻挡结构之间的间距设置的较大，可以减少该第一电源线的第一部分带入的水汽，通过阻挡结构中的亲水材料引入至多个像素单元，保证了显示基板的良率，从而确保显示基板的显示效果。

Description

显示基板及显示装置 技术领域
本申请涉及显示技术领域，特别涉及一种显示基板及显示装置。
背景技术
显示基板通常包括阵列排布在衬底基板的显示区域的多个像素单元，用于为每个像素单元提供正极电源信号的电源走线(一般称为VDD走线)，以及用于为显示基板中的阴极层提供负极电源信号的电源走线(一般称为VSS走线)。电源走线在从驱动芯片的一侧进入到封装区域内时，例如从绑定区进入围堰结构靠近像素单元一侧的区域时，也即是围堰结构供电源线穿过的部分(进线口)附近时，存在将水氧引入的风险，封装的性能有待提高。
发明内容
本申请提供了一种显示基板及显示装置，可以改善现有技术中显示基板的水氧侵蚀的问题。所述技术方案如下：
一方面，提供了一种显示基板，所述显示基板包括：
衬底基板；
多个像素单元，所述多个像素单元位于所述衬底基板上；
至少一条第一电源线，位于所述衬底基板上；
阻挡结构，所述阻挡结构围绕所述多个像素单元；
转接结构，包括相对的第一侧面以及第二侧面，所述第一侧面较所述第二侧面更靠近所述多个像素单元；
阴极层，位于所述转接结构远离所述衬底基板的一侧；
第一有机图案，位于所述转接结构远离所述衬底基板的一侧；
其中，所述至少一条第一电源线包括第一部分和第二部分，所述第一部分位于所述阻挡结构远离所述多个像素单元的一侧，用于接收电源信号，所述第二部分通过所述转接结构与所述阴极层连接；
所述第二部分包括与所述转接结构连接的第一连接处和第二连接处，所述 第一连接处与所述阻挡结构之间的间距大于所述第二连接处与所述转接结构之间的间距。
可选的，所述显示基板具有绑定区域，所述绑定区域位于所述阻挡结构远离所述多个像素单元的一侧；
所述第一连接处相对于所述第二连接处更靠近所述绑定区域。
可选的，所述转接结构在所述衬底基板上的正投影包括第一投影区域和第二投影区域，所述第一投影区域与所述阻挡结构在所述衬底基板上的正投影不重叠，所述第二投影区域与所述阻挡结构在所述衬底基板上的正投影包括相互重叠的第一重叠区域；
所述第一投影区域相对于所述第二投影区域靠近所述第一部分。
可选的，所述第一有机图案覆盖所述第二侧面的至少部分。
可选的，所述第二侧面包括被所述第一有机图案和所述阻挡结构覆盖的部分。
可选的，所述转接结构为环绕所述多个像素单元的环状结构。
可选的，所述显示基板还包括：至少一条第二电源线；
所述至少一条第二电源线的一端位于所述阻挡结构远离所述多个像素单元的一侧，用于接收电源信号，另一端位于所述阻挡结构与所述多个像素单元之间，且通过所述转接结构与所述阴极层连接；
所述第一有机图案与所述至少一条第二电源线在所述衬底基板上的正投影包括相互重叠的第二重叠区域，所述第二重叠区域不与所述阻挡结构在所述衬底基板上的正投影重叠。
可选的，所述至少一条第二电源线的一端位于所述阻挡结构远离所述多个像素单元的一侧的中部。
可选的，所述第二重叠区域与所述阻挡结构在所述衬底基板上的正投影之间的间距大于间距阈值。
可选的，所述间距阈值的范围为80微米至150微米。
可选的，所述显示基板还具有：位于所述多个像素单元与所述阻挡结构之间的行驱动区域；
所述至少一条第二电源线在所述衬底基板上的正投影与所述行驱动区域之间的间距，大于所述至少一条第一电源线在所述衬底基板上的正投影与所述行驱动区域之间的间距。
可选的，所述显示基板还包括：
钝化层，覆盖所述至少一条第一电源线；
所述钝化层中还设置有开口，所述转接结构靠近所述衬底基板的一侧通过所述开口与所述至少一条第一电源线连接，所述转接结构远离所述衬底基板的一侧与所述阴极层连接。
可选的，所述阻挡结构包括：第一阻挡坝和第二阻挡坝；
所述第一阻挡坝相对于所述第二阻挡坝远离所述多个像素单元，且所述第一阻挡坝的厚度大于所述第二阻挡坝的厚度；
所述第一阻挡坝包括：沿远离所述衬底基板的方向设置的第一平坦层图案，第二平坦层图案，以及第二有机图案；
所述第二阻挡坝包括：沿远离所述衬底基板的方向设置的第三平坦层图案，第三有机图案；
其中，所述第二平坦层图案和所述第三平坦层图案包括相同材料，所述第一有机图案，所述第二有机图案和所述第三有机图案包括相同材料。
可选的，所述阻挡结构包括：第一阻挡坝和第二阻挡坝；
所述第一阻挡坝相对于所述第二阻挡坝远离所述多个像素单元，且所述第一阻挡坝的厚度大于所述第二阻挡坝的厚度；
所述第一阻挡坝包括：沿远离所述衬底基板的方向依次层叠设置的平坦层图案，以及第二有机图案；
所述第二阻挡坝包括：在所述衬底基板上设置的第三有机图案；
其中，所述第一有机图案，所述第二有机图案和所述第三有机图案包括相同材料。
可选的，第一阻挡坝还包括：设置在所述第二有机图案远离所述衬底基板一侧的第四有机图案；
所述第二阻挡坝还包括：设置在所述第三有机图案远离所述衬底基板一侧的第五有机图案；
所述第四有机图案和所述第五有机图案采用包括相同材料。
可选的，所述阻挡结构包括：第一阻挡坝和第二阻挡坝；
所述第一阻挡坝相对于所述第二阻挡坝远离所述多个像素单元，且所述第一阻挡坝的厚度大于所述第二阻挡坝的厚度；
所述第一有机图案包括与所述第二阻挡坝直接接触的部分。
可选的，所述第一电源线包括：环绕所述多个像素单元所在区域的直边部分以及弧状部分；
所述第一有机图案中与所述第二阻挡坝直接接触的部分在所述衬底基板上的正投影，位于所述弧状部分在所述衬底基板上的正投影内。
可选的，所述第一电源线的第二部分包括：环绕所述多个像素单元所在区域的直边部分以及弧状部分。
所述第一阻挡坝为第一环形，所述第二阻挡坝为第二环形；
所述第一有机图案，与所述第三有机图案中的部分图案围成第三环形，所述第三环形在所述衬底基板上的正投影，位于所述第二环形在所述衬底基板上的正投影内，所述第二环形在所述衬底基板上的正投影，位于所述第一环形在所述衬底基板上的正投影内；
其中，所述第三环形围绕所述多个像素单元。
可选的，所述至少一条第一电源线包括：第一金属层；所述显示基板还包括：位于所述第一金属层远离所述衬底基板的一侧的辅助金属层；
所述辅助金属层远离所述第一金属层的一侧与所述转接结构接触。
可选的，所述显示基板中的所述第一金属层，钝化层，第一平坦层图案，所述辅助金属层，第二平坦层图案，以及所述第一有机图案沿远离所述衬底基板的方向层叠设置。
可选的，所述至少一条第一电源线包括：沿远离所述衬底基板的方向设置的第一金属层和第二金属层；
所述第二金属层远离所述第一金属层的一侧与所述转接结构接触。
可选的，所述显示基板中的所述第一金属层，第一平坦层图案，所述第二金属层，钝化层，第二平坦层图案，以及所述第一有机图案沿远离所述衬底基板的方向层叠设置。
可选的，所述至少一条第一电源线的第一部分位于所述阻挡结构远离所述多个像素单元的一端的侧面形成有多个齿状的凸起结构。
可选的，所述凸起结构在所述衬底基板上的正投影，与所述阻挡结构在所述衬底基板上的正投影不重叠。
可选的，所述显示基板还包括：封装膜层；
所述封装膜层位于所述第一电源线远离所述衬底基板的一侧，所述封装膜层覆盖所述阻挡结构围成的区域。
可选的，所述显示基板还包括：多条第三电源线，位于所述衬底基板上；
所述多条第三电源线与所述像素单元中的晶体管电连。
可选的，所述多条第三电源线中的至少一条所述第三电源线在所述衬底基板上的正投影，与所述第一电源线在衬底基板上的正投影相邻；
所述多条第三电源线在所述衬底基板上的正投影，与所述转接结构在所述衬底基板上的正投影存在交叠区域，且在所述交叠区域内，所述多条第三电源线与所述转接结构之间设置有钝化层。
另一方面，提供了一种显示装置，所述显示装置包括：上述方面所述的显示基板。
本申请提供的技术方案带来的有益效果至少包括：
本公开实施例提供了一种显示基板及显示装置，该显示基板包括衬底基板，多个像素单元，至少一条第一电源线，阻挡结构，转接结构，阴极层，以及第一有机图案。通过将靠近至少一条第一电源线中第一部分的第一连接处，与阻挡结构之间的间距设置的较大，可以减少该第一电源线的第一部分带入的水汽，通过阻挡结构中的亲水材料引入至多个像素单元，保证了显示基板的良率，从而确保显示基板的显示效果。
附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本公开实施例提供的一种显示基板的结构示意图；
图2是图1所示的显示基板沿BB方向的截面图；
图3是图1所示的显示基板的局部结构示意图；
图4是本公开实施例提供的另一种显示基板的结构示意图；
图5是本公开实施例提供的一种显示基板的局部结构示意图；
图6是本公开实施例提供的又一种显示基板的结构示意图；
图7是本公开实施例提供的另一种显示基板的局部结构示意图；
图8是本公开实施例提供的再一种显示基板的结构示意图；
图9是本公开实施例提供的再一种显示基板的结构示意图；
图10是本公开实施例提供的再一种显示基板的结构示意图；
图11是本公开实施例提供的再一种显示基板的结构示意图；
图12是本公开实施例提供的又一种显示基板的局部结构示意图；
图13是本公开实施例提供的再一种显示基板的局部结构示意图；
图14是本公开实施例提供的再一种显示基板的局部结构示意图；
图15是图1所示的显示基板沿CC方向的截面图；
图16是本公开实施例提供的再一种显示基板的局部结构示意图；
图17是本公开实施例提供的再一种显示基板的结构示意图；
图18是本公开实施例提供的再一种显示基板的结构示意图；
图19是本公开实施例提供的再一种显示基板的结构示意图；
图20是本公开实施例提供的再一种显示基板的结构示意图；
图21是本公开实施例提供的再一种显示基板的结构示意图；
图22是本公开实施例提供的一种显示基板的制造方法的流程图。
具体实施方式
为使本发明的目的、技术方案和优点更加清楚，下面将结合附图对本发明实施方式作进一步地详细描述。
相关技术中，为了减少电源走线从封装区域外部进入封装区域带来的水氧风险，通常会减少进入封装区域电源走线的数量，这样为了进一步保证电源走线的电信号传输，如为了保证阴极VSS走线与阴极的电连接，VSS走线的一端进入封装区域后，例如进入围堰结构(阻挡结构)后，需要通过位于衬底基板的封装区域内的转接结构与阴极层连接。但是，发明人发现，如此增加转接结构，如导电金属结构，虽然可以提升阴极与阴极电源线的搭接效果，但是由于转接结构的设置，其侧面可能会存在刻蚀缺陷，这样也给进线口附近增加了水氧侵蚀的风险。
图1是本公开实施例提供的一种显示基板的结构示意图。图2是图1所示的显示基板沿BB方向的截面图。该显示基板可以为柔性面板，例如可以为可折叠面板。结合图1和图2可以看出，该显示基板可以包括：衬底基板001，多个像素单元002，至少一条第一电源线003，阻挡结构004，转接结构005，阴极层006，以及第一有机图案007。该多个像素单元002可以位于衬底基板001上。示例的，图1中示出了一条第一电源线003。
其中，该至少一条第一电源线003位于衬底基板001上。该阻挡结构(围堰结构)004可以围绕多个像素单元002。该转接结构005可以包括相对的第一侧面005a和第二侧面005b，该第一侧面005a较第二侧面005b更靠近多个像素单元002。该阴极层006可以位于转接结构005远离衬底基板001的一侧。第一有机图案007可以位于转接结构005远离衬底基板001的一侧。
参考图1可以看出，该至少一条第一电源线003可以包括第一部分0031和第二部分0032，该第一部分0031可以位于阻挡结构004远离多个像素单元002的一侧，用于接收电源信号。例如，该第一部分0031可以与驱动芯片连接，用于接收该驱动芯片提供的电源信号。该第二部分0032可以通过转接结构005与阴极层006连接。
图3是图1所示的显示基板的局部结构示意图。参考图1和图3，该第二部分0032可以包括与转接结构005连接的第一连接处0032a和第二连接处0032b，该第一连接处0032a与阻挡结构004之间的间距可以大于第二连接处0032b与阻挡结构004之间的间距。也即是，该至少一条第一电源线003的第二部分0032的第一连接处0032a不与阻挡结构004接触，例如该第一连接处0032a在衬底基板001上的正投影与阻挡结构004在衬底基板001上的正投影不重叠，第二连接处0032b可以位于阻挡结构004覆盖的区域内，例如，第二连接处0032b可以与阻挡结构004接触。为了清楚示意第一电源线003和转接结构005的位置关系，图1中未示出阴极层006。
在本公开实施例中，通过将靠近第一部分0031的第一连接处0032a，与阻挡结构004之间的间距设置的较大，可以减少该至少一条第一电源线003的第一部分0031中的水汽，通过阻挡结构004中的亲水材料引入至多个像素单元002中，保证了显示基板的良率。
并且，由于第二连接处0032b相对于第一连接处0032a远离第一部分0031，水汽进入的路径较长，因此，即使将该第二连接处0032b与阻挡结构004之间的间距设置的较小，该第一电源线003的第一部分0031中的水汽也不会引入至多个像素单元002中。并且，将第二连接处0032b，与阻挡结构004之间的间距设置的较小，可以减小该转接结构005和阻挡结构004占用的衬底基板001的面积，便于窄边框显示基板的实现。
其中，该第一连接处0032a和第二连接处0032b中的每个连接处可以是指：第一电源线003的第二部分0032中与转接结构005接触的部分。在本公开实施 例中，可以是指第二部分0032中与转接结构005直接接触的部分。该两个连接处的形状可以与第二部分0032与转接结构005在衬底基板001上的正投影重叠的区域的形状大致相同。
综上所述，本公开实施例提供了一种显示基板，该显示基板包括衬底基板，多个像素单元，至少一条第一电源线，阻挡结构，转接结构，阴极层，以及第一有机图案。通过将靠近至少一条第一电源线中第一部分的第一连接处，与阻挡结构之间的间距设置的较大，可以减少该第一电源线的第一部分带入的水汽，通过阻挡结构中的亲水材料引入至多个像素单元，保证了显示基板的良率，从而确保显示基板的显示效果。
可选的，如图1所示，该显示基板还可以具有绑定区域00a，该绑定区域00a可以位于阻挡结构004远离该多个像素单元002的一侧。第一连接处0032a相对于第二连接处0032b更靠近该绑定区域00b。其中，更靠近可以是指第一连接处0032a上各点与绑定区域00b之间的距离的最小值，大于第二连接处0032b上各点与绑定区域00b之间的距离的最小值。
需要说明的是，在本公开实施例中，多个像素单元002在衬底基板001上的正投影所在的区域为显示基板的有效显示区域(active area，AA)。因此，该阻挡结构004可以围绕该AA区设置。该阴极层006可以整层覆盖该AA区。
可选的，在本公开实施例中，阴极层006在衬底基板001上的正投影可以覆盖多个像素单元002在衬底基板001上的正投影，并且该阴极层006在衬底001上的正投影可以位于该阻挡结构004围成的区域在衬底基板001上的正投影之内。
图4是本公开实施例提供的另一种显示基板的结构示意图。图5是本公开实施例提供的一种显示基板的局部结构示意图，参考图4和图5可以看出，转接结构005在衬底基板001上的正投影可以包括第一投影区域005c和第二投影区域005d。结合图1可以看出，第一投影区域005c相对于第二投影区域005d靠近第一部分0031。该第一投影区域005c与阻挡结构004在衬底基板001上的正投影不重叠，第二投影区域005d与阻挡结构004在衬底基板001上的正投影包括相互重叠的第一重叠区域00b。
由于制成阻挡结构004的有机材料为亲水材料，因此通过将转接结构005在衬底基板001上的正投影的第一投影区域005c与阻挡结构004在衬底基板001上的正投影不重叠，可以使得第一部分0031中的水汽不会通过覆盖在转接结构 005上的亲水材料进入多个像素单元002中，进一步保证显示基板的显示效果。
可选的，转接结构005中与第一电源线003的搭接处的宽度可以较宽，从而可以保证该转接结构005与第一电源线003的接触电阻尽量小。其中，参考图5，该搭接处在衬底基板001上的正投影即为第一投影区域005c，与第一电源线003在衬底基板001上的正投影的重叠区域。该转接结构005远离搭接处的部分的宽度可以较窄，从而可以减小对该转接结构005靠近衬底基板001的一侧设置的其他信号线的电容耦合影响，如可以减小对数据线电容耦合的影响。
在本公开实施例中，转接结构005的第二侧面005b可以被阻挡结构004覆盖。也即是，第二投影区域005d的转接结构005的第二侧面005b可以被阻挡结构004覆盖。
通过将转接结构005的第二侧面005b被阻挡结构004覆盖，可以减小该转接结构005和阻挡结构004占用的衬底基板001的面积，便于窄边框显示基板的实现。并且，转接结构005的第二投影区域005d，与至少一条第一电源线003的第一部分0031之间的间距较远，远离第一进线口00c的位置，水汽进入的路径较长，因此，即使转接结构005的第二侧面005b被阻挡结构004覆盖，水汽也不会进入像素单元002。其中，参考图6，阻挡结构004中供电源线穿过的部分可以称为进线口(port口)，如供第一电源线003穿过的部分可以称为第一进线口00c。
参考图1和图4，转接结构005可以为环绕多个像素单元002的环状结构，从而便于阴极层006通过该转接结构005与至少一条第一电源线003连接，保证为该显示基板的像素单元002提供的电源信号的电位均一性，显示效果较好。
参考图1，该显示基板还可以包括：至少一条第二电源线008。该至少一条第二电源线008的一端008a位于阻挡结构004远离多个像素单元002的一侧，用于接收电源信号，另一端008b位于阻挡结构004与多个像素单元002之间，且通过转接结构005与阴极层006连接，从而可以使得第二电源线008可以为阴极层006提供电源信号。
在本公开实施例中，每条第二电源线008的一端008a位于阻挡结构004围成的区域之外，另一端位于阻挡结构004围成的区域之内。即每条第二电源线008可以穿过阻挡结构004进入该阻挡结构004围成的区域内。其中，供第二电源线008穿过的部分可以称为第二进线口00d。
示例的，图1中示出了两条第二电源线008，每条第二电源线008的一端 008a可以与驱动芯片连接，用于接收该驱动芯片提供的电源信号。
结合图1至图4还可以看出，第一有机图案007可以覆盖转接结构005的第二侧面005b的至少部分，且该第一有机图案007与至少一条第二电源线008在衬底基板001上的正投影包括相互重叠的第二重叠区域00e，该第二重叠区域00e不与阻挡结构004在衬底基板001上的正投影重叠。
通过第一有机图案007覆盖转接结构005的第二侧面005b的至少部分，可以减少转接结构005的第二侧面005b如因刻蚀缺陷而被水汽或氧气腐蚀的风险，保证该转接结构005能够有效传输来自第一电源线003的电源信号。并且，由于制成第一有机图案007的有机材料通常为亲水材料，因此通过使第二重叠区域00e不与阻挡结构004在衬底基板上的正投影重叠，即使得第一有机图案007与阻挡结构004间隔设置，可以减少第二电源线008用于接收电源信号的一端008a带入的水汽通过该阻挡结构004和第一有机图案007引入至像素单元002，保证了显示基板的良率。
参考图1还可以看出，该至少一条第二电源线008的一端008a可以位于阻挡结构004远离多个像素单元002的一侧的中部，例如可以位于绑定区域00a的中部。
其中，该中部可以为衬底基板的纵轴线X所在区域，该纵轴线X为平行于衬底基板001上的数据线的轴线。该纵轴线X与显示基板的一个侧边之间的距离，可以大致等于该纵轴线X与显示基板的另一个侧边之间的距离。该一个侧边和另一个侧边均大致平行于数据线的延伸方向。示例的，该显示基板中与数据线的延伸方向大致平行的两个侧边中的任一侧边，如与数据线的延伸方向的夹角的范围可以为0度至10度。
需要说明的是，本公开实施例中的“大致”指的是可以允许有15％以内的误差范围。如距离“大致”相等，可以是两者的距离偏差不超过15％，延伸方向“大致平行”可以是两者延伸方向的夹角在0度至30度之间，如可以为0度至10度，0度至15度等，形状“大致”相同可以是两者形状为同一类型，如矩形，折线型，弧形，条状，“L”型等，面积“大致”相同可以可以是两者面积偏差不超过15％等。
示例的，参考图1，该显示基板可以包括两条第二电源线008。该两条第二电源线008可以相邻排布在阻挡结构004远离多个像素单元002的一侧的中部。或者，该两条第二电源线008还可以以该衬底基板的纵轴线X为轴对称间隔排 布在阻挡结构004远离多个像素单元002的一侧的中部。本公开实施例对该第二电源线008的设置位置不做限定。
若该两条第二电源线008相邻排布在阻挡结构004远离多个像素单元002的一侧的中部时，该两条第二电源线008可以为一体结构。
示例的，该两条第二电源线008为一体结构时，也即是第二电源线008为一条时，第一电源线008的一端008a位于阻挡结构004远离多个像素单元002的一侧的中部，例如位于绑定区域00a的中部，可以是第二电源线008的一端008a到纵轴线X的距离小于该第二电源线008的一端008a到显示基板上与纵轴线X大致平行的两个侧边中任一侧边的距离。
需要说明的是，若本公开实施例提供的显示基板为可折叠面板时，该可折叠面板的折叠线可以垂直于该纵轴线X。例如，该折叠面板的折叠线可以为该纵轴线X的中垂线。
在本公开实施例中，第一电源线003可以包括两个第一部分0031。该两个第一部分0031可以以衬底基板001的纵轴线X为轴大致对称设置在阻挡结构004远离多个像素单元002的一侧的边缘处。
在本公开实施例中，第以电源线003可以包括两个第一部分0031。例如该两个第一部分0031可以位于纵轴线X的两侧，如位于绑定区域00a的两侧。
在本公开实施例中，第一电源线003可以包括两个第一部分0031。例如该两个第一部分0031在第一进线口00c附近的部分位于显示基板的两侧，又如分别靠近与纵轴线X平行的两个侧边。
本公开实施例中，可以通过位于中部的第二电源线008和位于边缘处的第一电源线003同时为该显示基板中的阴极层006提供电源信号，从而能够进一步缓解因电压降导致为不同区域的阴极层006加载的电源信号的电位差异较大的问题，阴极层006的长程均一性(long range unifinity，LRU)较好，显示效果较好。
本公开实施例中，位于中部的第二电源线008和位于边缘处的第一电源线003均可以为该显示基板中的阴极层006提供电源信号。同时，即使增加中部的第二电源线008，本公开实施例中的第二电源线008的设计，也可以很好的减小水氧的侵蚀，保证良好的封装性能。
需要说明的是，对于尺寸较大的显示基板，还可以设置更多的第二电源线008，通过更多的第二电源线008为该阴极层006提供电源信号，可以确保阴极 层006各区域的电位的均一性，显示基板的显示效果较好。
还需要说明的是，在本公开实施例中，由于该第一电源线003和第二电源线008均用于为阴极层006提供电源信号，因此该第一电源线003和第二电源线008也可以称为VSS电源线或者VSS走线。
在本公开实施例中，图2所示为第一电源线003进入阻挡结构004包围的区域内的部分的剖视图。第二电源线008进入阻挡结构004包围的区域内的部分的层级结构与该第一电源线003相同。参考图2可以看出，第一有机图案007与至少一条第二电源线008在衬底基板001上的正投影相互重叠的第二重叠区域00e，与阻挡结构004在该衬底基板001上的正投影之间的间距d可以大于间距阈值。其中，该间距阈值的范围可以为80微米(μm)至150μm。如可以是90μm，100μm，110μm，120μm，130μm，140μm等。也即是，该第二重叠区域00e与阻挡结构004之间设置有一定的间距。由此，可以避免在第二电源线008的第二进线口00d附近，第一有机图案007与阻挡结构004直接接触，进而可以减少水汽通过该第一有机图案007引入至像素单元002，保证封装效果。其中，该间距阈值可以是预先通过实验确定的能够避免水汽进入像素单元002的阈值。也即是，在第二重叠区域00e与阻挡结构004之间的间距大于该间距阈值时，水汽难以进入该显示基板中的像素单元002中。
其中，该间距阈值可以是预先通过实验确定的能够避免水汽进入像素单元002的阈值。也即是，在第二重叠区域00e与阻挡结构004之间的间距大于该间距阈值时，水汽不会进入该显示基板中的像素单元002中。
参考图4还可以看出，该显示基板还可以具有：位于多个像素单元002与阻挡结构004之间的行驱动区域00f。至少一条第二电源线008在衬底基板001上的正投影与行驱动区域00f之间的间距，可以大于至少一条第一电源线003在衬底基板上的正投影与行驱动区域00f之间的间距。例如，位于中部的至少一条第二电源线008，相较于至少一条第一电源线003，与行驱动区域00f之间的距离更远。为了清楚示意转接结构005与阻挡结构的位置关系，图4中未示出第一电源线003，第二电源线008以及阴极层006。
或者可以理解为，每条第二电源线008上各点与行驱动区域00f之间的距离的最小值，大于该任一条第一电源线003上各点与行驱动区域00f之间的距离的最小值。例如，参考图6，该至少一条第二电源线008上的a1点与行驱动区域00f之间的距离h1，大于该至少一条第一电源线003上的b1点与行驱动区域00f 之间的距离h2。
其中，该行驱动区域00f可以设置有多个级联的移位寄存器单元，该多个级联的移位寄存器单元可以用于驱动各行像素单元002。
示例的，如图4和图6所示，该显示基板可以具有两个行驱动区域00f，该两个行驱动区域00f可以以衬底基板001的纵轴线X为轴对称设置在多个像素单元002的两侧。
在本公开实施例中，参考图2，显示基板还可以包括：钝化层009，该钝化层009可以覆盖至少一条第一电源线003。图7是本公开实施例提供的另一种显示基板的局部结构示意图。该钝化层009中还设置有开口009a，转接结构005靠近衬底基板001的一侧可以通过该开口009a与至少一条第一电源线003连接，转接结构005远离衬底基板001的一侧可以与阴极层006连接。其中，图7中所示的009a为钝化层009中设置的开口。也即是，图7中除了开口009a所在的区域，其余区域均覆盖有钝化层009。
由于在制备显示基板的过程中，该至少一条第一电源线003容易被水汽或氧气腐蚀，因此通过在至少一条第一电源线003上覆盖钝化层009，可以保证在后续形成其他膜层时，该至少一条第一电源线003不会被水汽或氧气腐蚀，保证该至少一条第一电源线003可以为阴极层006提供电源信号，确保显示基板的显示效果。
在本公开实施例中，钝化层009中的开口可以为过孔或者可以为开槽，本公开实施例对此不做限定。制成该钝化层009的材料可以包括：SiNx(氮化硅)、SiOx(氧化硅)和SiOxNy(氮氧化硅)等一种或多种无机氧化物。本公开实施例对制成该钝化层009的材料不做限定。
需要说明的是，在本公开实施例中，该钝化层009还可以覆盖该至少一条第二电源线008，保证该至少一条第二电源线008不会被水汽或氧气腐蚀，确保显示基板的显示效果。
参在本公开实施例中，参考图1，图4和图6，阻挡结构004可以为环绕多个像素单元002的环状结构，用于阻挡显示基板中位于该阻挡结构004围成的区域内的有机层溢流。结合图1至图7，该阻挡结构004可以包括：第一阻挡坝0041和第二阻挡坝0042。该第一阻挡坝0041相对于该第二阻挡坝0042远离该多个像素单元002，且该第一阻挡坝0041的厚度可以大于该第二阻挡坝0042的厚度。
通过设置两个阻挡坝，且远离多个像素单元002的第一阻挡坝0041的厚度大于靠近多个像素单元002的第二阻挡坝0042的厚度，可以进一步防止位于该阻挡结构004围成的区域内的有机层溢流。当然，该阻挡结构004还可以包括一个阻挡坝，或两个以上的阻挡坝，本公开实施例对此不做限定。
作为一种可选的实现方式，图8是本公开实施例提供的又一种显示基板的结构示意图。参考图8可以看出，第一阻挡坝0041可以包括：沿远离衬底基板001的方向设置的第一平坦层图案010，第二平坦层图案011，以及第二有机图案012。该第二阻挡坝0042可以包括：沿远离衬底基板001的方向设置的第三平坦层图案013，以及第三有机图案014。
其中，第二平坦层图案011和第三平坦层图案013可以包括相同材料，第一有机图案007，第二有机图案012和第三有机图案014可以包括相同材料。例如，第二平坦层图案011和第三平坦层图案013可以采用相同材料，并由同一次构图工艺制得，第一有机图案007，第二有机图案012和第三有机图案014可以采用相同材料，并由同一次构图工艺制得。
在本公开实施例中，第一平坦层图案010可以属于第一平坦层，第二平坦层图案011和第三平坦层图案013可以属于第二平坦层，第一有机图案007，第二有机图案012和第三有机图案014可以属于第一有机层，该第一有机层可以为像素界定层(pixel definition layer，PDL)。
可选的，制成该第一平坦层，第二平坦层，以及第一有机层的材料可以包括：树脂等有机材料。本公开实施例对此不做限定。
作为另一种可选的实现方式，参考图2，第一阻挡坝0041可以包括：沿远离衬底基板001的方向依次层叠设置的平坦层图案015，以及第二有机图案012。第二阻挡坝0042可以包括：在衬底基板001上设置的第三有机图案014。
其中，第一有机图案007，第二有机图案012和第三有机图案014可以包括相同材料。例如，第一有机图案007，第二有机图案012和第三有机图案014可以采用相同材料，并由同一次构图工艺制得。
在本公开实施例中，平坦层图案015可以属于平坦层，第一有机图案007，第二有机图案012，以及第三有机图案014可以属于第一有机层。
可选的，制成该平坦层的材料可以包括：树脂等有机材料。本公开实施例对此不做限定。
需要说明的是，图7中所示的开口015a为平坦层图案015未覆盖的区域， 例如，图7所示的区域中，衬底基板001上除了开口015a所在的区域，其余区域均覆盖有平坦层图案015。从图7可以看出，该平坦层图案015可以覆盖第一电源线003位于阻挡结构004包围区域内的部分的边界。
结合图2和图7，对于至少一条第一电源线003在衬底基板001上的正投影与第一投影区域005c的交叠区域，钝化层009的开口009a在衬底基板001上的正投影与该交叠区域的重叠区域，可以覆盖平坦层图案015的开口015a在衬底基板上001的正投影与该交叠区域的重叠区域。也即是，在该交叠区域内，钝化层009的开口009a的尺寸，大于平坦层图案015的开口015a的尺寸。
参考图2和图8可以看出，第一阻挡坝0041相对于第二阻挡坝0042多一层平坦层图案，从而可以使得该第一阻挡坝0041的厚度大于该第二阻挡坝0042的厚度，防止有机层溢流。
图9是本公开实施例提供的再一种显示基板的结构示意图。参考图9可以看出，该第一阻挡坝0041还可以包括：设置在第二有机图案012远离衬底基板一侧的第四有机图案016。该第二阻挡坝0042可以包括：设置在第三有机图案014远离衬底基板001一侧的第五有机图案017。
其中，第四有机图案016和第五有机图案017可以包括相同材料。例如，该第四有机图案016和第五有机图案017可以采用相同材料，并由同一次构图工艺制得。并且，该第四有机图案016和第五有机图案017均可以属于第二有机层，该第二有机层可以为支撑层(photo spacer，PS)。
可选的，制成该第二有机层的材料可以包括：树脂等有机材料。本公开实施例对此不做限定。
图10是本公开实施例提供的再一种显示基板的结构示意图。参考图10可以看出，第一有机图案007可以覆盖转接结构005的第二侧面005b。参考图1，图4，图6和图10，第一阻挡坝0041可以为第一环形，第二阻挡坝0042可以为第二环形。第一有机图案007与第三有机图案014中的部分图案可以围成第三环形，该第三环形在衬底基板001上的正投影，可以位于第二环形在衬底基板001上的正投影内，该第二环形在衬底基板001上的正投影，可以位于第一环形在衬底基板001上的正投影内。其中，该第三环形可以围绕多个像素单元002。该第三有机图案014的形状可以与第二阻挡坝0042的形状大致相同，即该第三有机图案014也为环形。
该部分图案可以为第三有机图案014中位于第一有机图案007靠近多个像 素单元002的一侧的图案。例如，参考图10，该部分图案可以为第三有机图案014的左侧，上侧，以及右侧的图案。
在本公开实施例中，第一有机图案007可以包括与第二阻挡坝0042直接接触的部分。参考图1，图6和图11，第一电源线003可以包括两个第一部分0031和一个第二部分0032。该两个第一部分0031可以以衬底基板001的纵轴线X对称设置在该衬底基板001的两侧，例如该两个第一部分0031在第一进线口00c附近的部分位于显示基板上的两侧，又如靠近与纵轴线X平行的两个侧边中的其中一个侧边。其中，图4中示出了两个第一部分0031的第一进线口00c。该第二部分0032可以环绕该多个像素单元002，且该第二部分0032的两端可以分别与一个第一部分0031连接。
在本公开实施例中，第一部分0031和第二部分0032可以直接接触，例如为一体结构。
在本公开实施例中，第二电源线008可以包括：环绕多个像素单元002所在区域的直边部分0032c以及弧状部分0032d。
在本公开实施例中，该第二部分0032可以包括：环绕多个像素单元002所在区域的直边部分0032c以及弧状部分0032d。并且，该第一电源线003的第二部分0032可以为非封闭结构，本公开实施例以该第二部分0032至少围绕显示基板的两条边进行说明。该第一有机图案007中与第二阻挡坝0042的直接接触的部分在衬底基板001上的正投影，可以位于弧状部分0032d在衬底基板001上的正投影内。也即是，该第一有机图案007与第二阻挡坝0042直接接触的部分在衬底基板001上的正投影，不超出弧状部分0032d在衬底基板001上的正投影。
本公开实施例中，弧状部分0032d相对于直边部分0032c靠近至少一条第一电源线003中用于接收电源信号的第一部分0031。
作为一种可选的实现方式，参考图8，至少一条第一电源线003可以包括：第一金属层003a。显示基板还可以包括：位于该第一金属层003a远离衬底基板的一侧的辅助金属层018。
本公开实施例中，该辅助金属层018远离第一金属层003a的一侧可以与转接结构005接触，且该辅助金属层018在衬底基板001上的正投影可以与阻挡结构004在该衬底基板001上的正投影重叠。例如，该辅助金属层018在该衬底基板001上的正投影包括位于阻挡结构004在该衬底基板001上的正投影所 包围的区域内的部分。
图12是本公开实施例提供的再一种显示基板的局部结构示意图。参考图12，该辅助金属层018在该衬底基板001上的正投影包括位于第二阻挡坝0042在该衬底基板001上的正投影内的部分。
本公开实施例中，在阻挡结构004所在的区域，第一金属层003a远离衬底基板001的一侧未设置该辅助金属层018，即该阻挡结构004所在的区域的辅助金属层018被去除，即该第一进线口00c所在的区域的辅助金属层018被去除。例如，阻挡结构004远离多个像素单元002的一侧可以设置有辅助金属层018，阻挡结构004包围的区域内也可以设置有辅助金属层018。
该辅助金属层018的边界的形状可以与第一金属层003a的边界的形状大致相同，或者，该辅助金属层018的边界的形状也可以与第一金属层003a的边界的形状不同，本公开实施例对此不做限定。
其中，第一金属层003a接收到的电源信号可以通过设置在钝化层009的开口内的辅助金属层018传输至转接结构005。通过该转接结构005将电源信号传输至阴极层006。
本公开实施例中，参考图8，该辅助金属层018远离衬底基板001的一侧可以被包括第二平坦层图案011和第三平坦层图案013的第二平坦层覆盖其靠近边缘的部分以及覆盖其侧边，该第二平坦层可以用于避免该辅助金属层018的侧壁因刻蚀缺陷，而引起的显示不良。
由于制成第二平坦层的有机材料通常为亲水材料，因此为了避免辅助金属层018将水汽引入像素单元002中，可以使得该辅助金属层018在衬底基板001上的正投影与阻挡结构004在该衬底基板001上的正投影不重叠，从而可以阻断水汽从阻挡结构004中进入，并沿第二平坦层进入像素单元002所在区域的路径，保证了显示基板的显示效果。
图13是本公开实施例提供的另一种显示基板的局部结构示意图。参考图13可以看出，辅助金属层018与第一金属层003a接触的部分在衬底基板001上的正投影，可以位于该辅助金属层018在衬底基板001上的正投影内，从而使得该第一金属层003a的边界，与辅助金属层018的边界存在间距，避免该第一金属层003a和辅助金属层018被水汽或氧气腐蚀。图14是本公开实施例提供的再一种显示基板的局部结构示意图。图14中所示的010a为第一平坦层中设置的开口。也即是，图14中除了开口010a所在的区域，其余区域均覆盖有第一 平坦层。图14中所示的011a为第二平坦层中设置的开口。也即是，图14中除了开口011a所在的区域，其余区域均覆盖有第二平坦层。
在该实现方式中，显示基板中的第一金属层003a，钝化层009，第一平坦层图案010，辅助金属层018，第二平坦层图案011，以及第一有机图案007可以沿远离衬底基板001的方向层叠设置。也即是，显示基板中的第一电源线003，钝化层009，第一平坦层，辅助金属层018，第二平坦层，以及第一有机层可以沿衬底基板001的方向层叠设置。
需要说明的是，第一金属层003a和辅助金属层018均可以包括三层金属膜层，例如，该三层金属膜层的材料可以依次为：钛(Ti)，铝(Al)以及Ti。
还需要说明的是，图15是图1所示的显示基板沿CC方向的截面图。参考图15，至少一条第二电源线008可以包括：第二金属层008c。显示基板还可以包括：位于该第二金属层008c远离衬底基板001的一侧的辅助走线层019。
本公开实施例中，该辅助走线层019远离第二金属层008c的一侧可以与转接结构005接触，且该辅助走线层019在该衬底基板001上的正投影可以与阻挡结构004在该衬底基板001上的正投影不重叠。例如，该辅助走线层019在该衬底基板001上的正投影包括位于阻挡结构004在该衬底基板001上的正投影所包围的区域内的部分。
图16是本公开实施例提供的再一种显示基板的局部结构示意图。参考图16，该辅助走线层019在该衬底基板001上的正投影包括位于第二阻挡坝0042在该衬底基板001上的正投影所包围的区域内的部分。
在本公开实施例中，在阻挡结构004所在的区域，第二金属层008c远离衬底基板001的一侧未设置该辅助走线层019，即该阻挡结构004所在的区域的辅助走线层019被去除，即第二进线口00d所在的区域的辅助走线层019被去除。例如，阻挡结构004远离多个像素单元的一侧可以设置有辅助走线层019，阻挡结构004包括的区域内可以设置有辅助走线层019。
该辅助走线层019的边界的形状可以与第二金属层008c的边界的形状大致相同，或者，该辅助走线层019的边界的形状也可以与第二金属层008c的边界的形状不同，本公开实施例对此不做限定。
作为另一种可选的实现方式，参考图17，至少一条第一电源线003包括：沿远离衬底基板001的方向设置的第一金属层003a和第三金属层003b。第三金属层003b远离第一金属层003a的一侧与转接结构005接触。
该第一金属层003a在该衬底基板001上的正投影，以及该第三金属层003b在该衬底基板001上的正投影，可以均与该阻挡结构004在该衬底基板001上的正投影重叠。也即是，该第一金属层003a和该第三金属层003b远离多个像素单元002的第一部分0031可以均用于接收电源信号，从而可以通过第一金属层003a和第三金属层003b的两层金属层向阴极层006传输电源信号，可以减小电阻，进而减小电源信号的电压降。
参考图17，该第一金属层003a在衬底基板001上的正投影，可以与第三金属层003b和转接结构005接触的区域不重叠。
或者，参考图18，该第一金属层003a在衬底基板001上的正投影，可以与第三金属层003b和转接结构005接触的区域重叠。
其中，第一平坦层可以覆盖该第一金属层003a靠近多个像素单元002的另一端，减少该第一金属层003a的另一端被氧气或水汽腐蚀，或者可以减少因为金属层侧面因刻蚀缺陷而引起的最终显示不良。
参考图17和图18可以看出，该显示基板中的第一金属层003a，第一平坦层图案010，第三金属层003b，钝化层009，第二平坦层图案011，第一有机图案007可以沿远离衬底基板001的方向层叠设置。也即是，显示基板中的第一金属层图案003a，第一平坦层，第三金属层003b，钝化层009，第二平坦层，以及第一有机层可以沿衬底基板001的方向层叠设置。
需要说明的是，第一金属层003a和第三金属层003b均可以包括三层金属膜层，例如，该三层金属膜层的材料可以依次为：Ti，Al以及Ti。
还需要说明的是，参考图9和图18，当第一阻挡坝0041还包括：设置在第二有机图案012远离衬底基板一侧的第四有机图案016，第二阻挡坝0042还包括：设置在第三有机图案014远离衬底基板001一侧的第五有机图案017时，包括该第四有机图案016和第五有机图案017的第二有机层可以设置在第一有机层远离衬底基板001的一侧。
图19是本公开实施例提供的再一种显示基板的结构示意图。参考图5和图19可以看出，至少一条第一电源线003的第一部分0031位于阻挡结构004远离多个像素单元002的一端的侧面形成有多个齿状的凸起结构，从而可以进一步延长水汽进入的路径，避免水汽被引入至多个像素单元002中。
参考图5和图19，凸起结构在衬底基板001上的正投影，与阻挡结构004在衬底基板001上的正投影不重叠。并且，该至少一条第一电源线003的第一 部分0031位于阻挡结构004围成的区域内的另一端的侧面可以为平面，即该至少一条第一电源线003的第一部分0031位于阻挡结构004围成的区域内的另一端的侧面未形成凸起结构。
在制备该显示基板时，转接结构005是依次通过曝光，显影以及刻蚀等工艺制备得到的。在刻蚀工艺中需要采用刻蚀剂对膜层进行刻蚀，若将第一电源线003的第一部分0031位于阻挡结构004围成的区域内的另一端的侧面也设置为齿状的凸起结构，则会使得刻蚀剂残留在该第一电源线003相邻的凸起结构之间，使得第一电源线003的第一部分0031的另一端的侧壁被腐蚀。因此将第一电源线003位于该阻挡结构004围成的区域内的第一部分0031的另一端的侧面设置为平面，可以避免在制造显示基板的过程中，由于该第一电源线003的侧壁被腐蚀，刺穿位于该第一电源线003远离衬底基板001一侧的膜质较脆的钝化层009，保证该钝化层009的质量。
参考图19还可以看出，至少一条第一电源线003的第一部分0031远离多个像素单元002的一端的侧面也形成有多个齿状的凸起结构，可以延长水汽沿第一电源线003进入的路径，避免水汽被引入至多个像素单元002。并且，该至少一条第一电源线003位于阻挡结构004围成的区域内的另一端008b的侧面可以为平面。
参考图19可以看出，该显示基板还可以包括：多条第三电源线020，该多条第三电源线020可以位于衬底基板001上。该多条第三电源线020与显示基板中的像素单元002中的晶体管电连。例如，可以与像素单元002中晶体管的源极或者漏极连接。该第三电源线020可以用于为像素单元002中的晶体管提供正极电源信号，因此该第三电源线020也可以称为VDD电源线或者VDD走线。
在本公开实施例中，该多条第三电源线020可以对称设置在至少一条第一电源线003的两侧。例如，参考图19，该显示基板可以包括：四条第三电源线020，其中两条第三电源线020可以位于阻挡结构004远离多个像素单元002的一侧的中部，且该两条第三电源线020可以以衬底基板001的纵轴线X为轴对称设置在第二电源线008的两侧。其余两条第三电源线020可以均位于阻挡结构远离多个像素单元002的一侧的边缘处。每条第三电源线020可以位于第一电源线003中一个第一部分0031靠近该第二电源线008的一侧。
参考图19，该多条第三电源线020位于阻挡结构004远离多个像素单元002 的一端的侧面也可以形成有多个齿状的凸起结构，从而可以延长水汽沿该第三电源线020进入的路径，避免水汽被引入至多个像素单元002中。并且，该第三电源线0200位于阻挡结构004围成的区域内的另一端的侧面可以为平面。
参考图2，图8至图9，图15，以及图17至图18可以看出，该显示基板还可以包括：封装膜层021。该封装膜层021可以位于多个第一电源线远离衬底基板001的一侧，该封装膜层021可以覆盖阻挡结构004围成的区域。参考图10，该封装膜层021覆盖的区域00g的边界可以位于阻挡结构004远离多个像素单元002的一侧。
在本公开实施例中，封装膜层021可以包括：沿远离衬底基板001的方向层叠设置的第一膜层0211，第二膜层0212以及第三膜层0213。
可选的，该第一膜层0211和该第三膜层0213可以由无机材料制成，该第二膜层0212可以由有机材料制成。例如，该第一膜层0211和该第三膜层0213可以由SiNx、SiOx和SiOxNy等一种或多种无机氧化物制成。第二膜层0212可以由树脂材料制成。该树脂可以为热塑性树脂或热塑性树脂，热塑性树脂可以包括亚克力(PMMA)树脂，热固性树脂可以包括环氧树脂。
需要说明的是，该第二膜层0212可以位于阻挡结构004围成的区域内，第一膜层0211和第三膜层0213可以覆盖阻挡结构004围成的区域，且覆盖该阻挡结构004。即阻挡结构004在衬底基板001上的正投影，位于该封装膜层021覆盖的区域内，由此确保该封装膜层021对位于阻挡结构004围成的区域内的各个结构的有效封装。
在本公开实施例中，第二膜层0212可以采用喷墨打印(ink jet printing，IJP)的方法制作。第一膜层0211和第三膜层0213可以采用化学气相沉积(chemical vapor deposition，CVD)的方法制作。
图20是本公开实施例提供的再一种显示基板的结构示意图。参考图20可以看出，衬底基板001上可以依次设置有缓冲层022，半导体层023，栅极绝缘层024，栅极025，层间介电层026和源漏极层027，源漏极层027可以包括源极0271和漏极0272。源极0271和漏极0272彼此间隔并可分别通过过孔与半导体层023连接。沿源漏极层027远离衬底基板001的方向依次设置有钝化层009，第一平坦层028，第二平坦层029，以及发光元件。该发光元件可以包括依次层叠的阳极层030，发光层031以及阴极层006。该阳极层030可以通过过孔与漏极0272电连。其中，栅极025，源极0271和漏极0272构成一个晶体管，每个 发光元件和其所连接的晶体管可以构成一个像素单元002。
参考图20可以看出，第一电源线003包括的第一金属层003a可以与源漏极层027同层设置。转接结构005可以与像素的阳极层030同层设置。该转接结构005可以包括三层膜层，例如，该三层膜层的材料可以依次为：氧化铟锡(indium tin oxide，ITO)，银(Ag)，以及ITO。
参考图19可以看出，多条第三电源线020中的至少一条第三电源线020在衬底基板001上的正投影，可以与第一电源线003在衬底基板上的正投影相邻。图21是本公开实施例提供的再一种显示基板的结构示意图。参考图21，多条第三电源线020在衬底基板001上的正投影，可以与转接结构005在衬底基板001上的正投影存在交叠区域。且在该交叠区域内，该多条第三电源线020与转接结构005之间可以设置有钝化层009。并且，该多条第三电源线020不与转接结构005接触。
综上所述，本公开实施例提供了一种显示基板，该显示基板包括衬底基板，多个像素单元，至少一条第一电源线，阻挡结构，转接结构，阴极层，以及第一有机图案。通过将靠近至少一条第一电源线中第一部分的第一连接处，与阻挡结构之间的间距设置的较大，可以减少该第一电源线的第一部分带入的水汽，通过阻挡结构中的亲水材料引入至多个像素单元，保证了显示基板的良率，从而确保显示基板的显示效果。
图22是本公开实施例提供的一种显示基板的制造方法的流程图。该方法可以用于制造上述实施例提供的显示基板。参考图22可以看出，该方法可以包括：
步骤101、提供一衬底基板。
步骤102、在该衬底基板上形成多个像素单元，至少一条第一电源线，阻挡结构，转接结构，第一有机图案，以及阴极层。
该至少一条第一电源线003包括第一部分0031和第二部分0032，该第一部分0031可以位于阻挡结构004远离多个像素单元002的一侧，用于接收电源信息后，该第二部分0032可以通过转接结构005与阴极层006连接。
该第二部分0032可以包括与转接结构005连接的第一连接处0032a和第二连接处0032b，该第一连接处0032a与阻挡结构004之间的间距大于第二连接处0032b与阻挡结构004之间的间距。
需要说明的是，在上述步骤102中，可以先在衬底基板001上形成至少一条第一电源线003，然后在该第一电源线003远离衬底基板001的一侧形成阻挡 结构004和转接结构005。之后在该转接结构005远离衬底基板001的一侧形成第一有机图案007，最后在该第一有机图案007远离衬底基板001的一侧形成阴极层006。
其中，该至少一条第一电源线003可以与像素单元002中的薄膜晶体管的源漏极通过一次构图工艺形成，该阻挡结构004可以在平坦层，像素界定层以及支撑层的形成过程中形成。该第一有机图案005可以在该像素界定层的形成过程中形成。该转接结构005可以与像素单元002中的阳极层030通过一次构图工艺形成。
综上所述，本公开实施例提供了一种显示基板的制造方法，该方法可以包括在衬底基板上依次形成的多个像素单元，至少一条第一电源线，阻挡结构，转接结构，第一有机图案，以及阴极层。通过将靠近至少一条第一电源线中第一部分的第一连接处，与阻挡结构之间的间距设置的较大，可以减少该第一电源线的第一部分带入的水汽，通过阻挡结构中的亲水材料引入至多个像素单元，保证了显示基板的良率，从而确保显示基板的显示效果。
本公开实施例还提供了一种显示装置，该显示装置可以包括：上述实施例所述的显示基板。该显示装置可以为折叠显示装置，例如可以为：液晶面板、电子纸、有机发光二极管(organic light-emitting diode，OLED)面板、有源矩阵有机发光二极管(active-matrix organic light-emitting diode，AMOLED)面板、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
以上所述仅为本申请的可选实施例，并不用以限制本申请，凡在本申请的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本申请的保护范围之内。

Claims (29)

  1. 一种显示基板，包括：
    衬底基板；
    多个像素单元，所述多个像素单元位于所述衬底基板上；
    至少一条第一电源线，位于所述衬底基板上；
    阻挡结构，所述阻挡结构围绕所述多个像素单元；
    转接结构，包括相对的第一侧面以及第二侧面，所述第一侧面较所述第二侧面更靠近所述多个像素单元；
    阴极层，位于所述转接结构远离所述衬底基板的一侧；
    第一有机图案，位于所述转接结构远离所述衬底基板的一侧；
    其中，所述至少一条第一电源线包括第一部分和第二部分，所述第一部分位于所述阻挡结构远离所述多个像素单元的一侧，用于接收电源信号，所述第二部分通过所述转接结构与所述阴极层连接；
    所述第二部分包括与所述转接结构连接的第一连接处和第二连接处，所述第一连接处与所述阻挡结构之间的间距大于所述第二连接处与所述阻挡结构之间的间距。
  2. 根据权利要求1所述的显示基板，所述显示基板具有绑定区域，所述绑定区域位于所述阻挡结构远离所述多个像素单元的一侧；
    所述第一连接处相对于所述第二连接处更靠近所述绑定区域。
  3. 根据权利要求1或2所述的显示基板，
    所述转接结构在所述衬底基板上的正投影包括第一投影区域和第二投影区域，所述第一投影区域与所述阻挡结构在所述衬底基板上的正投影不重叠，所述第二投影区域与所述阻挡结构在所述衬底基板上的正投影包括相互重叠的第一重叠区域；
    所述第一投影区域相对于所述第二投影区域靠近所述第一部分。
  4. 根据权利要求1至3任一所述的显示基板，所述第一有机图案覆盖所述第二侧面的至少部分。
  5. 根据权利要求4所述的显示基板，所述第二侧面包括被所述第一有机图案和所述阻挡结构覆盖的部分。
  6. 根据权利要求1至5任一所述的显示基板，所述转接结构为环绕所述多个像素单元的环状结构。
  7. 根据权利要求1至6任一所述的显示基板，所述显示基板还包括：至少一条第二电源线；
    所述至少一条第二电源线的一端位于所述阻挡结构远离所述多个像素单元的一侧，用于接收电源信号，另一端位于所述阻挡结构与所述多个像素单元之间，且通过所述转接结构与所述阴极层连接；
    所述第一有机图案与所述至少一条第二电源线在所述衬底基板上的正投影包括相互重叠的第二重叠区域，所述第二重叠区域不与所述阻挡结构在所述衬底基板上的正投影重叠。
  8. 根据权利要求7所述的显示基板，
    所述至少一条第二电源线的一端位于所述阻挡结构远离所述多个像素单元的一侧的中部。
  9. 根据权利要求7或8所述的显示基板，
    所述第二重叠区域与所述阻挡结构在所述衬底基板上的正投影之间的间距大于间距阈值。
  10. 根据权利要求9所述的显示基板，
    所述间距阈值的范围为80微米至150微米。
  11. 根据权利要求8至10任一所述的显示基板，所述显示基板还具有：位于所述多个像素单元与所述阻挡结构之间的行驱动区域；
    所述至少一条第二电源线在所述衬底基板上的正投影与所述行驱动区域之间的间距，大于所述至少一条第一电源线在所述衬底基板上的正投影与所述行 驱动区域之间的间距。
  12. 根据权利要求1至11任一所述的显示基板，所述显示基板还包括：
    钝化层，覆盖所述至少一条第一电源线；
    所述钝化层中还设置有开口，所述转接结构靠近所述衬底基板的一侧通过所述开口与所述至少一条第一电源线连接，所述转接结构远离所述衬底基板的一侧与所述阴极层连接。
  13. 根据权利要求1至12任一所述的显示基板，所述阻挡结构包括：第一阻挡坝和第二阻挡坝；
    所述第一阻挡坝相对于所述第二阻挡坝远离所述多个像素单元，且所述第一阻挡坝的厚度大于所述第二阻挡坝的厚度；
    所述第一阻挡坝包括：沿远离所述衬底基板的方向设置的第一平坦层图案，第二平坦层图案，以及第二有机图案；
    所述第二阻挡坝包括：沿远离所述衬底基板的方向设置的第三平坦层图案，第三有机图案；
    其中，所述第二平坦层图案和所述第三平坦层图案包括相同材料，所述第一有机图案，所述第二有机图案和所述第三有机图案包括相同材料。
  14. 根据权利要求1至12任一所述的显示基板，所述阻挡结构包括：第一阻挡坝和第二阻挡坝；
    所述第一阻挡坝相对于所述第二阻挡坝远离所述多个像素单元，且所述第一阻挡坝的厚度大于所述第二阻挡坝的厚度；
    所述第一阻挡坝包括：沿远离所述衬底基板的方向依次层叠设置的平坦层图案，以及第二有机图案；
    所述第二阻挡坝包括：在所述衬底基板上设置的第三有机图案；
    其中，所述第一有机图案，所述第二有机图案和所述第三有机图案包括相同材料。
  15. 根据权利要求13或14所述的显示基板，第一阻挡坝还包括：设置在 所述第二有机图案远离所述衬底基板一侧的第四有机图案；
    所述第二阻挡坝还包括：设置在所述第三有机图案远离所述衬底基板一侧的第五有机图案；
    所述第四有机图案和所述第五有机图案采用包括材料。
  16. 根据权利要求1至12任一所述的显示基板，所述阻挡结构包括：第一阻挡坝和第二阻挡坝；
    所述第一阻挡坝相对于所述第二阻挡坝远离所述多个像素单元，且所述第一阻挡坝的厚度大于所述第二阻挡坝的厚度；
    所述第一有机图案包括与所述第二阻挡坝直接接触的部分。
  17. 根据权利要求16所述的显示基板，所述第一电源线包括：环绕所述多个像素单元所在区域的直边部分以及弧状部分；
    所述第一有机图案中与所述第二阻挡坝直接接触的部分在所述衬底基板上的正投影，位于所述弧状部分在所述衬底基板上的正投影内。
  18. 根据权利要求17所述的显示基板，所述第一电源线的第二部分包括：环绕所述多个像素单元所在区域的直边部分以及弧状部分。
  19. 根据权利要求13至18任一所述的显示基板，所述第一阻挡坝为第一环形，所述第二阻挡坝为第二环形；
    所述第一有机图案，与所述第三有机图案中的部分图案围成第三环形，所述第三环形在所述衬底基板上的正投影，位于所述第二环形在所述衬底基板上的正投影内，所述第二环形在所述衬底基板上的正投影，位于所述第一环形在所述衬底基板上的正投影内；
    其中，所述第三环形围绕所述多个像素单元。
  20. 根据权利要求1至13任一所述的显示基板，所述至少一条第一电源线包括：第一金属层；所述显示基板还包括：位于所述第一金属层远离所述衬底基板的一侧的辅助金属层；
    所述辅助金属层远离所述第一金属层的一侧与所述转接结构接触。
  21. 根据权利要求20所述的显示基板，
    所述显示基板中的所述第一金属层，钝化层，第一平坦层图案，所述辅助金属层，第二平坦层图案，以及所述第一有机图案沿远离所述衬底基板的方向层叠设置。
  22. 根据权利要求1至13任一所述的显示基板，所述至少一条第一电源线包括：沿远离所述衬底基板的方向设置的第一金属层和第二金属层；
    所述第二金属层远离所述第一金属层的一侧与所述转接结构接触。
  23. 根据权利要求22所述的显示基板，
    所述显示基板中的所述第一金属层，第一平坦层图案，所述第二金属层，钝化层，第二平坦层图案，以及所述第一有机图案沿远离所述衬底基板的方向层叠设置。
  24. 根据权利要求1至23任一所述的显示基板，所述至少一条第一电源线的第一部分位于所述阻挡结构远离所述多个像素单元的一端的侧面形成有多个齿状的凸起结构。
  25. 根据权利要求24所述的显示基板，所述凸起结构在所述衬底基板上的正投影，与所述阻挡结构在所述衬底基板上的正投影不重叠。
  26. 根据权利要求1至25任一所述的显示基板，所述显示基板还包括：封装膜层；
    所述封装膜层位于所述第一电源线远离所述衬底基板的一侧，所述封装膜层覆盖所述阻挡结构围成的区域。
  27. 根据权利要求1至26任一所述的显示基板，所述显示基板还包括：多条第三电源线，位于所述衬底基板上；
    所述多条第三电源线与所述像素单元中的晶体管电连。
  28. 根据权利要求27所述的显示基板，
    所述多条第三电源线中的至少一条所述第三电源线在所述衬底基板上的正投影，与所述第一电源线在衬底基板上的正投影相邻；
    所述多条第三电源线在所述衬底基板上的正投影，与所述转接结构在所述衬底基板上的正投影存在交叠区域，且在所述交叠区域内，所述多条第三电源线与所述转接结构之间设置有钝化层。
  29. 一种显示装置，所述显示装置包括：权利要求1至28任一所述的显示基板。
PCT/CN2019/098938 2019-08-01 2019-08-01 显示基板及显示装置 WO2021017011A1 (zh)

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