WO2021184273A1 - 显示基板及其制作方法、显示装置 - Google Patents

显示基板及其制作方法、显示装置 Download PDF

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Publication number
WO2021184273A1
WO2021184273A1 PCT/CN2020/080074 CN2020080074W WO2021184273A1 WO 2021184273 A1 WO2021184273 A1 WO 2021184273A1 CN 2020080074 W CN2020080074 W CN 2020080074W WO 2021184273 A1 WO2021184273 A1 WO 2021184273A1
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WIPO (PCT)
Prior art keywords
layer
area
dam
encapsulation
display
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Application number
PCT/CN2020/080074
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English (en)
French (fr)
Inventor
张鑫
周洋
和玉鹏
姜晓峰
张猛
白露
屈忆
李慧君
杨路路
于鹏飞
张昊
王梦奇
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US17/252,427 priority Critical patent/US12010876B2/en
Priority to CN202080000289.0A priority patent/CN113875036B/zh
Priority to PCT/CN2020/080074 priority patent/WO2021184273A1/zh
Priority to EP20900706.1A priority patent/EP4123740A4/en
Publication of WO2021184273A1 publication Critical patent/WO2021184273A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/84—Passivation; Containers; Encapsulations
    • H10K50/844—Encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/87—Passivation; Containers; Encapsulations
    • H10K59/873—Encapsulations
    • H10K59/8731—Encapsulations multilayered coatings having a repetitive structure, e.g. having multiple organic-inorganic bilayers

Definitions

  • the embodiments of the present disclosure relate to the field of display technology, and in particular to a display substrate, a manufacturing method thereof, and a display device.
  • organic electroluminance display devices Organic Electroluminance Display, abbreviated as: OLED
  • OLED Organic Electroluminance Display
  • the embodiments of the present disclosure provide a display substrate, a manufacturing method thereof, and a display device, which can prevent water vapor and oxygen from entering the display area from the opening of the perforated area, thereby prolonging the service life of the product and the display effect.
  • a display substrate having a display area, an opening area, and a transition area between the display area and the opening area, and the transition area surrounds the The opening area is provided; wherein, the display substrate includes:
  • a display device located in the display area, and including a first electrode and a pixel defining portion sequentially formed on the interlayer dielectric layer;
  • a first encapsulation dam is located in the transition area and arranged around the opening area, and the first encapsulation dam includes a first protection part and a first blocking part sequentially stacked on the interlayer dielectric layer;
  • the second encapsulation dam is located in the transition area and is arranged around the opening area, the second encapsulation dam is located on the side of the first encapsulation dam away from the display area, and the thickness of the second encapsulation dam is Greater than the thickness of the first encapsulation dam, the second encapsulation dam includes a second protection part and a second blocking part sequentially stacked on the interlayer dielectric layer; wherein,
  • the first blocking portion, the second blocking portion and the pixel defining portion are arranged in the same layer and are disconnected from each other;
  • the distance between the first packaging dam and the second packaging dam is smaller than the distance between the first packaging dam and the display area.
  • the thickness of the second protection part is greater than the thickness of the first protection part.
  • the first protection portion and the first electrode are provided in the same layer and are disconnected from each other.
  • the display substrate further includes a planarization portion, the planarization portion is located in the display area and formed between the interlayer dielectric layer and the first electrode;
  • the first protection part and the planarization part are provided in the same layer and are disconnected from each other.
  • the second protection part and the first protection part are provided in the same layer.
  • the display substrate further includes a planarization portion, the planarization portion is located in the display area and formed between the interlayer dielectric layer and the first electrode;
  • the second protection part and the planarization part are provided in the same layer and are disconnected from each other.
  • At least one of the first encapsulation dam and the second encapsulation dam further includes a spacer part formed on the first blocking part or The side of the second blocking portion away from the interlayer dielectric layer;
  • the display device further includes a supporting portion formed on a side of the pixel defining portion away from the base substrate, and the supporting portion and the spacer portion are provided in the same layer.
  • the display substrate further has an isolation area between the display area and the transition area, and the isolation area is arranged around the transition area;
  • the display substrate further includes isolation pillars formed on a side of the interlayer dielectric layer away from the base substrate and located in the isolation region, the isolation pillars are arranged around the first packaging dam, and the isolation pillars
  • the side wall is provided with grooves.
  • the driving circuit layer includes a thin film transistor located in the display area, and the source and drain of the thin film transistor are arranged in the same layer as the isolation pillar and are disconnected from each other. .
  • the display substrate further has an inner ring wiring area located between the isolation area and the display area, and the inner ring wiring area is arranged around the isolation area ;
  • the driving circuit layer further includes an inner ring signal line located in the inner ring wiring area, and the inner ring signal line is electrically connected with the signal wiring in the display area.
  • the isolation pillar includes a first metal layer, a second metal layer, and a third metal layer sequentially stacked on the interlayer dielectric layer, and the second metal layer is
  • the outer boundary of the orthographic projection on the interlayer dielectric layer is located inside the outer boundary of the orthographic projection of the first metal layer and the third metal layer on the interlayer dielectric layer, so as to be on the inner side of the isolation column.
  • the side wall forms the groove.
  • the first metal layer and the third metal layer are titanium layers, and the second metal layer is an aluminum layer.
  • the driving circuit layer has a first slot and a second slot located in the isolation region; the first slot is located in the isolation column close to the first slot.
  • the first slot is arranged around the first encapsulation dam; the second slot is located on the side of the isolation column close to the display area, and the second slot surrounds the The first slot setting;
  • the first slot and the second slot penetrate the driving circuit layer.
  • the display substrate further includes an encapsulation layer, and the encapsulation layer includes a first inorganic encapsulation film layer, an organic encapsulation film layer, and a second inorganic encapsulation film layer stacked in sequence;
  • the first inorganic encapsulation film layer and the second inorganic encapsulation film layer encapsulate the first encapsulation dam, the second encapsulation dam, and the display device;
  • the organic encapsulation film layer encapsulates the display device and blocks the side of the first encapsulation dam close to the display area.
  • a method for manufacturing a display substrate having a display area, an opening area, and a transition area between the display area and the opening area.
  • the transition area is arranged around the opening area; wherein, the manufacturing method includes:
  • the driving circuit layer including an interlayer dielectric layer located in the display area and the transition area;
  • a display device, a first packaging dam, and a second packaging dam are formed on the side of the interlayer dielectric layer away from the base substrate;
  • the first encapsulation dam is located in the transition area and is arranged around the opening area, and the first encapsulation dam includes layers stacked on the interlayer dielectric layer in turn The first protection part and the first blocking part;
  • the second encapsulation dam is located in the transition area and arranged around the opening area, and the second encapsulation dam is located at a distance of the first encapsulation dam away from the display area Side, and the thickness of the second encapsulation dam is greater than the thickness of the first encapsulation dam, and the second encapsulation dam includes a second protection part and a second blocking part sequentially laminated on the interlayer dielectric layer;
  • the distance between the first packaging dam and the second packaging dam is smaller than the distance between the first packaging dam and the display area.
  • the first protection part and the first electrode that are disconnected from each other are formed by using the same patterning process.
  • the first protection part and the planarization part that are disconnected from each other are formed by the same patterning process, and the planarization part is located in the display area and formed between the layers. Between the dielectric layer and the first electrode.
  • the second protection part and the first protection part which are disconnected from each other are formed by using the same patterning process.
  • the second protection part and the planarization part that are disconnected from each other are formed by the same patterning process, and the planarization part is located in the display area and formed between the layers. Between the dielectric layer and the first electrode.
  • the display substrate further has an isolation region located between the display region and the transition region, and the isolation region is arranged around the transition region; wherein, the fabrication Methods also include:
  • An isolation pillar located in the isolation region is formed on a side of the interlayer dielectric layer away from the base substrate, the isolation pillar is arranged around the transition region, and the sidewall of the isolation pillar is provided with a groove.
  • the driving circuit layer includes a thin film transistor located in the display area, and the thin film transistor includes a source electrode and a drain electrode;
  • the source electrode, the drain electrode and the isolation pillar which are disconnected from each other are formed by the same patterning process.
  • the display substrate further has an inner ring wiring area located between the isolation area and the display area, and the inner ring wiring area is arranged around the isolation area
  • the driving circuit layer also includes an inner ring signal line located in the inner ring wiring area, the inner ring signal line is electrically connected to the signal wiring of the display area.
  • the method further includes:
  • an encapsulation layer including a first inorganic encapsulation film layer, an organic encapsulation film layer, and a second inorganic encapsulation film layer stacked in sequence;
  • the first inorganic encapsulation film layer and the second inorganic encapsulation film layer encapsulate the first encapsulation dam, the second encapsulation dam, and the display device;
  • the organic encapsulation film layer encapsulates the display device and blocks the side of the first encapsulation dam close to the display area.
  • a display device which includes the display substrate described in any one of the above.
  • FIG. 1 is a schematic plan view of the display substrate according to an embodiment of the present disclosure
  • FIG. 2 is a schematic diagram of the base substrate described in an embodiment of the disclosure.
  • FIG. 3 is a cross-sectional view of the display substrate in the A-A direction according to an embodiment shown in FIG. 1;
  • FIG. 4 is a cross-sectional view of the display substrate according to another embodiment shown in FIG. 1 in the direction A-A;
  • FIG. 5 is a cross-sectional view of the display substrate in the B-B direction of the embodiment shown in FIG. 1;
  • FIG. 6 is a cross-sectional view of the display substrate in the direction B-B according to another embodiment shown in FIG. 1;
  • FIG. 7 is a cross-sectional view of the barrier wall in the display substrate shown in FIG. 6;
  • FIG. 8 is a cross-sectional view of an isolation pillar in an isolation region of a display substrate according to an embodiment of the present disclosure
  • 9A and 9B are cross-sectional views of the display substrate in the C-C direction under the different embodiments shown in FIG. 1;
  • FIG. 10 is a cross-sectional view of the display substrate in the direction B-B according to another embodiment shown in FIG. 1;
  • FIG. 11 is a schematic plan view of the display device described in an embodiment of the present disclosure.
  • FIG. 12 is a flowchart of a manufacturing method of the display substrate described in an embodiment of the disclosure.
  • FIG. 13 is an equivalent circuit diagram of a pixel circuit in a display area of a display substrate provided by at least one embodiment of the present disclosure
  • 14A-14E are layout designs of various layers of a pixel circuit in a display area of a display substrate provided by some embodiments of the present disclosure.
  • 14F is a layout design of a conductive layer of a pixel circuit in a display area of a display substrate provided by some embodiments of the present disclosure
  • 15A is another layout design of the second conductive layer of the pixel circuit in the display area of the display substrate provided by some embodiments of the present disclosure.
  • 15B is another layout design of the third conductive layer of the pixel circuit in the display area of the display substrate provided by some embodiments of the present disclosure.
  • 15C is another layout design of the fourth conductive layer of the pixel circuit in the display area of the display substrate provided by some embodiments of the present disclosure.
  • 16A is a schematic diagram of a first packaging dam and a second packaging dam in a display substrate provided by some embodiments of the present disclosure under a scanning electron microscope;
  • 16B is a schematic diagram showing the observation port at P in FIG. 16A under a scanning electron microscope
  • 16C is a schematic diagram showing the observation port at Q in FIG. 16A under a scanning electron microscope
  • FIG. 17 is a schematic top view of a part of a structure in a display substrate provided by some embodiments of the present disclosure.
  • Display substrate; 10a display area; 10b, opening area; 10c, transition area; 10d, isolation area; 10e, inner wiring area; 10f, peripheral wiring area; 10g, peripheral packaging area; 101, poly Imide layer; 102, buffer layer; 103, interlayer dielectric layer; 104, active layer; 105, first gate insulating layer; 106, gate electrode; 107, peripheral wiring; 108, second gate insulating layer; 109a, the first peripheral transfer line; 109b, the second peripheral transfer line; 110, the source electrode; 111, the drain electrode; 112, the first electrode; 113, the pixel defining part; 114, the luminescent material layer; 114a, the light emitting part; 115 116.
  • Planarization part; 116a first planarization film layer; 116b, second planarization film layer; 117, first barrier part; 118, encapsulation layer; 118a, first inorganic encapsulation film layer; 118b , Organic encapsulation film layer; 118c, second inorganic encapsulation film layer; 119, first protection part; 120, second protection part; 121, second barrier part; 122, first spacer part; 123, second spacer 124, isolation column; 124a, groove; 124b, first metal layer; 124c, second metal layer; 124d, third metal layer; 125, first slot; 126, second slot; 127, first A peripheral packaging dam; 127a, the first peripheral barrier portion; 127b, the first peripheral spacer portion; 128, the second peripheral packaging dam; 128a, the third protection portion; 128b, the second peripheral barrier portion; 128c, the first periphery Septum part; 129a, first inner ring signal line; 129b second inner
  • Passivation film layer 135. Barrier wall; 136. First film layer; 137. Second film layer; 138. Third film layer; 139. Organic insulation package part; 140. First pattern Block; 141, the second pattern block; 1a, the first package dam; 1b, the second package dam; 1c, the third package dam; 1d, the light-emitting sub-pixel;
  • on can mean that one layer is directly formed or disposed on another layer, or can mean a layer A layer is formed indirectly or arranged on another layer, that is, there are other layers between the two layers.
  • first may be used herein to describe various components, components, elements, regions, layers and/or parts, these components, components, elements, regions, and layers And/or part should not be limited by these terms. Rather, these terms are used to distinguish one component, member, element, region, layer, and/or section from another.
  • the term “same layer arrangement” used means that two layers, parts, components, elements or parts can be formed by the same patterning process, and the two layers, parts, components , Components or parts are generally formed of the same material.
  • patterning process generally includes the steps of photoresist coating, exposure, development, etching, and photoresist stripping.
  • one-time patterning process means a process of forming patterned layers, parts, components, etc., using one mask.
  • the display substrate 10 may have a display area 10a, an opening area 10b, and a transition area 10c between the display area 10a and the opening area 10b, and the transition area 10c is arranged around the opening area 10b;
  • the display substrate 10 may further include an isolation region 10d, an inner wiring region 10e, a peripheral wiring region 10f, and a peripheral packaging region 10g; this isolation region 10d is located between the display region 10a and the transition region 10c and surrounds the transition region 10c setting; this inner ring wiring area 10e is located between the isolation area 10d and the display area 10a, and is set around the isolation area 10d; this peripheral wiring area 10f can be set around the display area 10a, or set on both sides of the display area 10a ;
  • the outer packaging area 10g can be at the outermost edge of the entire base substrate, encapsulating the entire display substrate 10.
  • the display substrate may include a base substrate, a driving circuit layer, a display device, a first packaging dam, and a second packaging dam; wherein,
  • the base substrate may be a flexible substrate to improve the flexibility of the display substrate 10, so that the display substrate 10 can have properties such as bendable and bendable, so as to expand the applicable scope of the display substrate 10; but not limited to this, the base substrate It can also be set to be rigid, and the specific performance of the base substrate can be determined according to the actual requirements of the product.
  • the base substrate may have a single-layer structure or a multilayer structure.
  • the base substrate may include a polyimide layer 101 and a buffer layer 102 stacked in sequence.
  • the base substrate may include a plurality of polyimide layers stacked in sequence.
  • the amine layer 101 and the buffer layer 102; the buffer layer 102 can be made of silicon nitride, silicon oxide and other materials to achieve the effect of blocking water and oxygen and blocking alkaline ions; it should be noted that the structure of the base substrate is not Limited to this, it can be determined according to actual needs.
  • each area may be defined on the base substrate.
  • the display area 10a and the transition area may be divided on the base substrate first.
  • 10c, the opening area 10b, the isolation area 10d, the inner wiring area 10e, the outer wiring area 10f, the outer packaging area 10g, that is, the display area 10a, the transition area 10c, and the opening area 10b of the entire display substrate 10 are divided.
  • the driving circuit layer may be formed on the base substrate.
  • the driving circuit layer may be formed on the buffer layer 102.
  • the driving circuit layer may include an interlayer dielectric layer 103 located in the display area 10a and the transition area 10c.
  • the interlayer dielectric layer 103 is made of inorganic materials, such as silicon oxide, silicon nitride and other inorganic materials to achieve The effect of blocking water and oxygen and blocking alkaline ions; it should be understood that when the display substrate 10 has an isolation area 10d, an inner wiring area 10e, a peripheral wiring area 10f, and a peripheral packaging area 10g, the interlayer dielectric layer 103 It is also located in the isolation area 10d, the inner wiring area 10e, the outer wiring area 10f, and the outer packaging area 10g.
  • inorganic materials such as silicon oxide, silicon nitride and other inorganic materials to achieve The effect of blocking water and oxygen and blocking alkaline ions; it should be understood that when the display substrate 10 has an isolation area 10d, an inner wiring area 10e, a peripheral wiring area 10f, and a peripheral packaging area 10g, the interlayer dielectric layer 103 It is also located in the isolation area 10d, the inner wiring area 10e, the outer wiring area 10f, and the outer packaging area 10g.
  • the portion of the driving circuit layer located in the display area 10a may include a thin film transistor and a capacitor structure.
  • the thin film transistor may be a top gate type, and the thin film transistor may include an active layer 104, a first gate insulating layer 105, a gate 106, a second gate insulating layer 108, an interlayer dielectric layer 103, and a source electrode. 110, the drain 111.
  • the active layer 104 may be formed on the buffer layer 102, the first gate insulating layer 105 covers the buffer layer 102 and the active layer 104, and the gate 106 is formed on the side of the first gate insulating layer 105 away from the active layer 104
  • the second gate insulating layer 108 covers the gate 106 and the first gate insulating layer 105
  • the interlayer dielectric layer 103 covers the second gate insulating layer 108
  • the source 110 and the drain 111 are formed on the interlayer dielectric layer 103 away from the base substrate
  • the source electrode 110 and the drain electrode 111 can respectively contact the opposite sides of the active layer 104 through via holes (for example, metal via holes). It should be understood that this thin film transistor may also be a bottom gate type.
  • the capacitor structure may include a first electrode plate 130 and a second electrode plate 131.
  • the first electrode plate 130 and the gate electrode 106 are arranged in the same layer, and the second electrode plate 131 is located on the second gate insulating layer 108 and the layer Between the dielectric layers 103 and opposite to the first electrode plate 130, they are arranged.
  • the materials of the gate 106, the first electrode plate 130, and the second electrode plate 131 may include metal materials or alloy materials, such as molybdenum, aluminum, and titanium.
  • the source 110 and the drain 111 may include a metal material or an alloy material, such as a metal single-layer or multi-layer structure formed of molybdenum, aluminum, titanium, etc.
  • the multi-layer structure is a multi-metal laminate layer, such as titanium, aluminum, Titanium three-layer metal laminate (Al/Ti/Al), etc.
  • the aforementioned first gate insulating layer 105 and second gate insulating layer 108 are also located in the transition region 10c and the isolation region 10d.
  • the inner ring wiring area 10e, the outer wiring area 10f, and the outer packaging area 10g are also located in the transition region 10c and the isolation region 10d.
  • the display device is located in the display area.
  • the display device may include a first electrode 112 and a pixel defining portion 113 sequentially formed on the interlayer dielectric layer 103. It should be understood that the display device may further include a light emitting portion. 114a and second electrode 115.
  • a planarization layer can be fabricated before the display device is fabricated.
  • the planarization layer can be a single-layer structure or a multilayer structure; the planarization layer is usually It is made of organic materials, such as photoresist, acrylic-based polymer, silicon-based polymer, etc.; as shown in FIG. 3, the planarization layer may include a planarization portion 116 located in the display area 10a, and the planarization portion 116 is formed between the interlayer dielectric layer 103 and the first electrode 112.
  • the first electrode 112 can be electrically connected to the drain 111 through a metal via.
  • the first electrode 112 can be an anode.
  • the anode can be ITO (Indium Tin Oxide), Indium Zinc Oxide (IZO), or Zinc Oxide (ZnO). ) And other materials; the pixel defining portion 113 can cover the planarizing portion 116, the pixel defining portion 113 can be made of organic materials, such as photoresist and other organic materials, and the pixel defining portion 113 is located in the display area 10a
  • the portion of may have a pixel opening exposing the first electrode 112; the light-emitting portion 114a is located in the pixel opening and is formed on the first electrode 112, and the light-emitting portion 114a may include small molecular organic materials or polymer molecular organic materials, and may be fluorescent light-emitting
  • the material or phosphorescent light-emitting material can emit red light, green light, blue light, or white light, etc.; and, according to different actual needs, in different examples, the light-emitting portion 114a may further include an electron injection layer, an electron transport layer, Hol
  • the first electrode 112, the light-emitting portion 114a, and the second electrode 115 may constitute one light-emitting sub-pixel 1d.
  • the portion of the display device located in the display area 10a may include a plurality of light-emitting sub-pixels 1d arranged in an array.
  • the first electrode 112 of each light-emitting sub-pixel 1d is independent of each other, and the second electrode 115 of each light-emitting sub-pixel 1d is connected over the entire surface; that is, the second electrode 115 is disposed on the entire surface of the display substrate 10.
  • the structure is a common electrode for multiple display devices.
  • the side of the pixel defining portion 113 away from the interlayer dielectric layer 103 may further be provided with a supporting portion 132, which may function to support the protective film layer (not shown in the figure) The effect is to prevent the protective film layer from contacting the first electrode 112 or other traces, which may cause the first electrode 112 or other traces to be easily damaged.
  • this protective film layer mainly occurs during the transfer of semi-finished products to avoid damage to the semi-finished products during the transfer process, specifically: in the process of transferring the substrate on which the support portion 132 has been fabricated to the evaporation production line , Can be covered with a protective film layer, when the luminescent material needs to be evaporated, the protective film layer is removed.
  • the material of the support portion 132 can be the same as the material of the pixel defining portion 113, and the support portion 132 and the pixel defining portion 113 can be formed by the same patterning process, but it is not limited to this.
  • the material of the support portion 132 can also be the same as that of the pixel.
  • the material of the defining portion 113 is different, and the supporting portion 132 and the pixel defining portion 113 can also be formed by using different patterning processes.
  • the pixel defining portion 113 is also located in the peripheral wiring area 10f.
  • the first electrode 112 may also be electrically connected to the drain 111 through the transfer electrode 133.
  • the planarization portion 116 may have a double-layer structure, and specifically may include a first planarization film (PLN1) layer 116a and a second planarization film (PLN1) layer 116a and a second planarization film (PLN1) formed in sequence.
  • a passivation film (PVX) layer 134 can be formed between the first planarization film layer 116a and the interlayer dielectric layer 103.
  • the passivation film layer 134 can be made of silicon oxide, nitride
  • the passivation film layer 134 covers the source 110 and the drain 111. It should be noted that when the planarization portion 116 is a single layer, the planarization portion 116 and the interlayer dielectric layer 103 are formed A passivation film layer 134 may also be formed between; and the transfer electrode 133 is formed between the first planarization film layer 116a and the second planarization film layer 116b, and passes through the first planarization film layer 116a and the passivation film layer in sequence.
  • the via hole (such as a metal via) on 134 is electrically connected to the drain 111; and the first electrode 112 can be electrically connected to the transfer electrode 133 through a via (such as a metal via) on the second planarization film layer 116b. Connect as shown in Figure 4. However, it is not limited to this, and the via electrode 133 may also be formed between the first planarization film layer 116 a and the passivation film layer 134.
  • the first encapsulation dam 1a is formed on the side of the interlayer dielectric layer 103 away from the base substrate and is located in the transition area 10c.
  • the first encapsulation dam 1a is arranged around the opening area 10b.
  • the first encapsulation dam 1a may include a first blocking portion 117.
  • the first blocking portion 117 can restrict the flow of the organic encapsulation film layer material in the encapsulation layer 118. This prevents the organic encapsulation film layer material in the encapsulation layer 118 from flowing to the opening area 10b to cause encapsulation failure.
  • the first barrier portion 117 of the first encapsulation dam 1a can cooperate with the encapsulation layer 118 to effectively block Water and oxygen enter the display area 10a through the opening area 10b, thereby avoiding the failure of the light-emitting portion 114a of the display area 10a and causing poor display effect, and prolonging the service life of the product.
  • the encapsulation layer 118 of the display substrate 10 may include a first inorganic encapsulation film layer 118a, an organic encapsulation film layer 118b, and a second inorganic encapsulation film layer 118c stacked in sequence.
  • the first inorganic encapsulation film layer 118a encapsulates the display device and the first encapsulation dam 1a and the second encapsulation dam 1b, and the organic encapsulation film layer 118b encapsulates the display device and blocks the side of the first encapsulation dam 1a close to the display area 10a;
  • the second inorganic encapsulation film layer 118c encapsulates the display device and the first encapsulation dam 1a and the second encapsulation dam 1b.
  • the first inorganic encapsulation film layer 118a and the second inorganic encapsulation film layer 118c are used to prevent water and oxygen from entering the light-emitting portion 114a of the display area 10a from the display side of the display function and the aperture area 10b; the first inorganic encapsulation film layer 118a and the second inorganic packaging film layer 118c can be made of inorganic materials such as silicon nitride and silicon oxide.
  • the organic encapsulation film layer 118b is used to achieve planarization to facilitate the production of the second inorganic encapsulation film layer 118c.
  • the organic encapsulation film layer 118b can be made of acrylic-based polymer, silicon-based polymer, or other materials.
  • the first inorganic encapsulation film layer 118a and the second inorganic encapsulation film layer 118c can be made by a chemical vapor deposition process, but it is not limited to this, and a physical vapor deposition process can also be used; while the organic encapsulation film layer 118b is made by spraying Ink printing process, but not limited to this, spraying process etc. can also be used.
  • the flow of the organic encapsulating material can be restricted by setting the first blocking portion 117 to prevent the organic encapsulating material from flowing to the opening area 10b Problems that cause package failure.
  • the first blocking portion 117 and the pixel defining portion 113 are arranged in the same layer, that is, the first blocking portion 117 and the pixel defining portion 113 can be formed at the same time through a single patterning process, which can reduce processing steps and masks. The use of plates can reduce costs. In addition, it should be understood that the first blocking portion 117 and the pixel defining portion 113 should be disconnected from each other.
  • first barrier portion 117 and the pixel defining portion 113 are provided in the same layer, it can be seen that if the first barrier portion 117 is directly fabricated on the interlayer dielectric layer 103 of the transition region 10c, it will be located before the first barrier portion 117 is fabricated.
  • the surface of the interlayer dielectric layer 103 in the transition region 10c needs to go through other layers of patterning processes (for example: source and drain patterning process, planarization layer patterning process, first electrode 112 patterning process) etching solution For example: nitric acid solution, etc.) are cleaned for many times, so that the surface roughness of the interlayer dielectric layer 103 located in the transition zone 10c (referring to the small spacing and the unevenness of the small peaks and valleys of the processed surface) becomes smaller, that is : Becomes smoother; if the first barrier portion 117 is formed directly on the surface of the interlayer dielectric layer 103 in the transition zone 10c, the adhesion of the first barrier portion 117 on the interlayer dielectric layer 103 is reduced, and the first barrier The portion 117 cannot be stably combined with the interlayer dielectric layer 103 of the transition zone 10c; in the process of forming the first barrier portion 117 by patterning, the first barrier portion 117 is likely to fall off during the cleaning process of the developer, that
  • the first packaging dam 1a further includes a first protection portion 119 formed on the interlayer dielectric layer 103, and the first protection portion 119 is away from the interlayer dielectric layer 103.
  • the aforementioned first blocking portion 117 is provided on one side of the dielectric layer 103. That is, in the embodiment of the present disclosure, before the first encapsulation dam 1a is fabricated, the first protective portion 119 may be formed on the surface of the interlayer dielectric layer 103 located in the transition region 10c, and then the first protective portion 119 is away from the layer.
  • the first barrier portion 117 is formed on one side of the interlayer dielectric layer 103; by providing the first protection portion 119, the surface of the interlayer dielectric layer 103 located in the transition zone 10c can be protected before the first barrier portion 117 is made to reduce the The number of times the interlayer dielectric layer 103 in the transition zone 10c is cleaned by the etching solution, so as to improve the adhesion of the interlayer dielectric layer 103 in the transition zone 10c, and ensure the stability of the bonding between the first encapsulation dam 1a and the interlayer dielectric layer 103 This effectively reduces the risk of the first package dam 1a falling off during the process, thereby reducing the risk of package failure, improving the package yield, and ensuring the display effect and product service life.
  • the interlayer dielectric layer 103 covered with the first protective layer 119 is greater than the surface roughness of the non-covered first protective layer 119.
  • the ratio between the surface roughness of the interlayer dielectric layer 103 covered with the first protective part 119 and the surface roughness of the first protective layer 119 not covered may be 100:5 to 100:95, 100: 10 ⁇ 100:90, 100:20 ⁇ 100:80, 100:30 ⁇ 100:70, 100:40 ⁇ 100:60 and so on. It should be understood that the evaluation of surface roughness usually uses the three height characteristic parameters of "the average arithmetic deviation of the profile Ra, the average height of unevenness Rz and the maximum height Ry".
  • the first protection portion 119 can be arranged in the same layer as the first electrode 112, that is, it can be covered on the interlayer dielectric layer 103 and located in the display area 10a and the transition area through a single patterning process.
  • the first conductive film of 10c is patterned to form the first protection portion 119 and the first electrode 112 at the same time. Since the first conductive film covers the interlayer dielectric layer 103 in the transition region 10c, during the patterning and formation of the first electrode 112, the interlayer dielectric layer 103 in the transition region 10c will not be affected by the etching solution in the process.
  • the cleaning reduces the number of times the interlayer dielectric layer 103 in the transition zone 10c is cleaned by the etching solution, thereby improving the adhesion of the interlayer dielectric layer 103 in the transition zone 10c.
  • the first protection part 119 since the first protection part 119 is also formed in the process of forming the first electrode 112, the first protection part 119 can continue to protect the interlayer dielectric layer 103 located in the transition region 10c to avoid subsequent The etching solution of the patterning process cleans the interlayer dielectric layer 103 located in the transition region 10c.
  • first protection portion 119 and the first electrode 112 are formed by the same patterning process, the processing steps and the use of masks can be reduced, so that the cost can be reduced.
  • first protection portion 119 and the first electrode 112 should be disconnected from each other to prevent the first protection portion 119 from being energized during display.
  • the first protection portion 119 and the planarization portion 116 may be provided in the same layer, that is, the interlayer dielectric layer 103 can be covered on the interlayer dielectric layer 103 and located in the display area 10a and the transition area 10c through a single patterning process.
  • the flattening film of ⁇ is subjected to a patterning process to form the first protection portion 119 and the flattening portion 116 at the same time. Since the planarization film covers the interlayer dielectric layer 103 in the transition region 10c, during the process of patterning to form the planarization portion 116, the interlayer dielectric layer 103 in the transition region 10c will not be cleaned by the etching solution in this process.
  • the first protection part 119 can continue to protect the interlayer dielectric layer 103 located in the transition region 10c to avoid subsequent The etching solution of the patterning process cleans the interlayer dielectric layer 103 located in the transition region 10c.
  • first protection portion 119 and the planarization portion 116 are formed by the same patterning process, the processing steps and the use of masks can be reduced, so that the cost can be reduced.
  • first protection portion 119 and the flattening portion 116 should be disconnected from each other to prevent water and oxygen from being transmitted to the flattening portion 116 of the display area 10a through the first protection portion 119, thereby causing the display area 10a Circumstances where the components fail.
  • the material of the first blocking portion 117 and the pixel defining portion 113 are the same, and they are also organic materials; in this embodiment, the first protection portion 119 is combined with the pixel defining portion 113
  • the planarization portion 116 is arranged in the same layer, so that the material of the first protection portion 119 is the same as that of the planarization portion 116, and is also an organic material.
  • the material of the first protection portion 119 can be the same as the material of the first barrier portion 117.
  • the design can improve the bonding force between the first protection part 119 and the first barrier part 117, ensure the structural stability of the first packaging dam 1a, and prevent the first barrier part 117 from falling off the first protection part 119 to further Reduce the risk of package failure, improve the package yield, and ensure the display effect and product service life.
  • the display substrate 10 further includes a second encapsulation dam 1b.
  • the second encapsulation dam 1b is formed on the side of the interlayer dielectric layer 103 away from the base substrate and is located in the transition area.
  • the second encapsulation dam 1b is located on the side of the first encapsulation dam 1a away from the display area 10a and surrounds the opening area 10b, wherein the thickness of the second encapsulation dam 1b is greater than that of the first encapsulation dam 1a Thickness; to further restrict the flow of the organic encapsulation film layer material of the encapsulation layer 118, so as to prevent the organic encapsulation film layer material of the encapsulation layer 118 from flowing to the opening area 10b causing the problem of package failure.
  • the second packaging dam 1b may include a second protection portion 120 and a second barrier portion 121 formed on the side of the second protection portion 120 away from the interlayer dielectric layer 103, and the second barrier portion 121 It is arranged in the same layer as the first barrier portion 117, that is, the second barrier portion 121, the first barrier portion 117, and the pixel defining portion 113 can be formed at the same time through a single patterning process, which can reduce the processing steps and the use of masks, thereby enabling reduce costs.
  • first blocking portion 117 and the second blocking portion 121 should be disconnected from each other, so that the design can increase the blocking and packaging path, and therefore, the packaging effect can be further improved.
  • the second blocking portion 121 is arranged in the same layer as the first blocking portion 117 and the pixel defining portion 113, the surface of the interlayer dielectric layer 103 located in the transition zone 10c needs to be patterned by other layers before the second blocking portion 121 is fabricated The etching solution of the process is cleaned many times, so that the adhesion of the first barrier portion 117 on the interlayer dielectric layer 103 is reduced. If the second barrier portion 121 is directly fabricated on the interlayer dielectric layer 103 in the transition zone 10c , The second barrier portion 121 cannot be stably combined with the interlayer dielectric layer 103 of the transition region 10c, and it is easy to fall off from the interlayer dielectric layer 103 of the transition region 10c.
  • the second protection portion 120 by providing the second protection portion 120, the surface of the interlayer dielectric layer 103 located in the transition area 10c can be protected before the second barrier portion 121 is made, so as to reduce the interlayer dielectric layer 103 located in the transition area 10c.
  • the number of times of cleaning by the etching solution can improve the adhesion of the interlayer dielectric layer 103 in the transition zone 10c, and ensure the stability of the bonding between the first encapsulation dam 1a and the interlayer dielectric layer 103.
  • the interlayer dielectric layer 103 covered with the second protective layer 120 is greater than the surface roughness of the non-covered second protective layer 120.
  • the ratio of the surface roughness of the interlayer dielectric layer 103 covered with the second protective layer 120 to the surface roughness of the uncovered second protective layer 120 may be 100:5 to 100:95, 100: 10 ⁇ 100:90, 100:20 ⁇ 100:80, 100:30 ⁇ 100:70, 100:40 ⁇ 100:60 and so on.
  • the solution adopted in this embodiment is to design the thickness of the second protection portion 120 to be greater than the thickness of the first protection portion 119.
  • the thickness of the first protection part 119 and the second protection part 120 can be made equal, and then the thickness of the second blocking part 121 is made larger than the thickness of the first blocking part 117, so that the thickness of the second encapsulation dam 1b is increased.
  • the thickness is greater than the thickness of the first encapsulation dam 1a, depending on the specific circumstances.
  • the second protection part 120 may be provided in the same layer as the first protection part 119, that is, the first protection part 119 and the second protection part 120 can be formed at the same time through a single patterning process, This design can reduce the processing steps and the use of masks, thereby reducing costs.
  • the second protection portion 120 and the first protection portion 119 can be arranged in the same layer, when the first protection portion 119 and the first electrode 112 are arranged in the same layer, the second protection portion 120 is also arranged in the same layer as the first protection portion 119.
  • the electrodes 112 are arranged in the same layer, that is, the first conductive film covering the interlayer dielectric layer 103 and located in the display area 10a and the transition area 10c can be patterned by one patterning process to form the first protection portion 119 at the same time ,
  • the second protection portion 120 and the first electrode 112; the first protection portion 119 and the planarization portion 116 are provided in the same layer, and the second protection portion 120 is also provided in the same layer as the planarization portion 116, that is, through a patterning process
  • the planarization film covering the interlayer dielectric layer 103 and located in the display area 10a and the transition area 10c may be patterned to form the first protection portion 119, the second protection portion 120, and the planarization portion 116 at the same time.
  • a grayscale mask can be used to The thin film is patterned to form the first protection part 119 and the second protection part 120 with different thicknesses.
  • the planarization film can be a photoresist film, and the photoresist film can be a positive photoresist or a negative photoresist; and the first protection part 119 is formed in the gray-scale mask.
  • the light transmittance of the area corresponding to the area where the second protection portion 120 is formed is different, so that the thickness of the first protection portion 119 and the thickness of the second protection portion 120 obtained after exposure and development are different.
  • the gray-scale mask corresponds to the area where the first protection portion 119 is formed.
  • the photoresist film is a negative photoresist, in order to make the thickness of the second protection part 120 greater than the thickness of the first protection part 119, The light transmittance of the area corresponding to the first protection portion 119 in the gray-scale mask is lower than the light transmittance of the area corresponding to the second protection portion 120.
  • the second protection part 120 and the first protection part 119 are arranged in different layers, that is, the first protection part 119 and the second protection part 120 are each formed by a patterning process.
  • the second protection part 120 and the planarization part 116 may be arranged in the same layer, that is, the first protection part 119 and the first electrode 112 may be arranged in the same layer.
  • the second protection portion 120 and the planarization portion 116 are formed by a patterning process, which is designed to increase the distance between the first encapsulation dam 1a and the second encapsulation dam 1b and the interlayer dielectric layer 103 located in the transition area 10c.
  • a patterning process which is designed to increase the distance between the first encapsulation dam 1a and the second encapsulation dam 1b and the interlayer dielectric layer 103 located in the transition area 10c.
  • no additional patterning process is required, so that the processing steps and the use of masks can be reduced, so as to reduce the cost.
  • the thickness of the first electrode 112 is usually smaller than the thickness of the planarization portion 116, the thickness of the first protection portion 119 provided on the same layer as the first electrode 112 may be smaller than that of the second protection portion 119 provided on the same layer as the planarization portion 116.
  • the thickness of the protection portion 120 is designed such that the thickness of the first protection portion 119 can be made smaller than the thickness of the second protection portion 120 without the need for additional adjustment of processing parameters.
  • the bonding force between the first encapsulation dam 1a and the interlayer dielectric layer 103 located in the transition zone 10c is consistent with that of the second encapsulation dam.
  • the bonding force between 1b and the interlayer dielectric layer 103 in the transition zone 10c is different. This design can prevent the first encapsulation dam 1a and the second encapsulation dam 1b from falling off the interlayer dielectric layer 103 at the same time, so as to improve the packaging effect.
  • first protection part 119 and the second protection part 120 are not limited to the above two cases, and the second protection part 120 can also be provided when the first protection part 119 and the planarization part 116 are arranged in the same layer. It can be arranged in the same layer as the first electrode 112. This design improves the bonding stability between the first encapsulation dam 1a and the second encapsulation dam 1b and the interlayer dielectric layer 103 located in the transition zone 10c, without adding additional The patterning process can reduce the processing steps and the use of masks to reduce costs.
  • the thickness of the first barrier portion 117 may be adjusted to be smaller than the thickness of the second barrier portion 121 through a grayscale process in this embodiment.
  • a grayscale process is used to pattern the first insulating film to form the pixel defining portion 113, the first blocking portion 117, and the second blocking portion 121.
  • the first insulating film may be a photoresist film.
  • the photoresist film can be a positive photoresist or a negative photoresist; and the light transmittance of the area corresponding to the first barrier portion 117 in the gray-scale mask and the area corresponding to the second barrier portion 121 are different. , So that the thickness of the first barrier portion 117 and the thickness of the second barrier portion 121 obtained after exposure and development are different.
  • the photoresist film is a positive photoresist, in order to make the thickness of the second barrier portion 121 greater than the thickness of the first barrier portion 117, the light transmittance of the region corresponding to the first barrier portion 117 in the grayscale mask is greater than Corresponding to the light transmittance of the region where the second barrier portion 121 is formed; when the photoresist film is a negative photoresist, in order to make the thickness of the second barrier portion 121 greater than the thickness of the first barrier portion 117, the gray scale mask The light transmittance of the area corresponding to the first blocking portion 117 is lower than the light transmittance of the area corresponding to the second blocking portion 121.
  • beneficial effects of the second protection part 120 and the first electrode 112 being provided in the same layer, and the beneficial effects of the second protection part 120 and the planarization part 116 being provided in the same layer can be referred to the aforementioned first protection part 119 and the first protection part 119 and the first protection part 116 respectively.
  • the beneficial effects of an electrode 112 arranged in the same layer and the beneficial effects of the second protection portion 120 and the planarization portion 116 arranged in the same layer are not repeated here.
  • the second protection portion 120 and the first protection portion 119 can be disconnected from each other. This design can increase the barrier and packaging path, and thus can further improve the packaging effect.
  • first protection portion 119 and the second protection portion 120 and the planarization portion 116 are provided in the same layer
  • planarization portion 116 includes the first planarization film layer 116a and the second planarization film layer 116b
  • the first protection part 119 and the second protection part 120 can also be a two-layer structure. Both the first protection part 119 and the second protection part 120 include the same layer as the first planarization film layer 116a. A film layer and a film layer provided in the same layer as the second planarization film layer 116b. But it is not limited to this.
  • the second protection portion 120 may also have a two-layer structure, and the first protection portion 119 may have a single-layer structure (that is, only include the film layer provided in the same layer as the second planarization film layer 116b); Both the first protection portion 119 and the second protection portion 120 are single-layer structures that only include a film layer provided in the same layer as the second planarization film layer 116b.
  • At least one of the first encapsulation dam 1a and the second encapsulation dam 1b further includes a spacer part (Photo Spacer, PS for short), and the spacer part may be formed on the first spacer part 117 Or the side of the second blocking portion 121 away from the interlayer dielectric layer 103, which can increase the thickness of the first encapsulation dam 1a and the second encapsulation dam 1b, and the spacer portion can block the organic encapsulation film material in the encapsulation layer 118 from flowing to the opening
  • the area 10b further improves the restriction on the flow of the organic packaging film material in the packaging layer 118, and further improves the packaging reliability of the display substrate 10.
  • the aforementioned spacer portion and the support portion 132 of the display area 10a may be provided in the same layer.
  • the spacer portion formed on the first barrier portion 117 can be defined as the first spacer portion 122
  • the spacer portion formed on the second barrier portion 121 can be defined as the second spacer portion 123.
  • the material of the pad portion 122 and the first barrier portion 117 may be the same, and the first pad portion 122 and the first barrier portion 117 may be formed by the same patterning process (for example, a gray-scale mask process) to improve the first package dam
  • the material of the second spacer portion 123 and the second barrier portion 121 can be the same, and the second spacer portion 123 and the second barrier portion 121 can use the same patterning process (for example: gray-scale masking process) )
  • the material of the second spacer portion 123 and the second barrier portion 121 may also be different, and the second spacer portion 123 and the first
  • the second blocking portion 121 can be formed by using different patterning processes.
  • the thickness mentioned in the embodiment of the present disclosure refers to the dimension in the Z direction as shown in FIGS. 3 to 6 and shown in FIGS. 9A, 9B and 10.
  • FIG. 16A shows a schematic diagram of the first package dam and the second package dam under a scanning electron microscope
  • FIG. 16B is a schematic diagram showing the observation port at P in FIG. 16A under a scanning electron microscope
  • FIG. 16C is a diagram showing The schematic diagram of the observation port at Q in Figure 16A under the scanning electron microscope is shown.
  • the outer contour of the first encapsulation dam 1a is inclined with respect to the surface of the interlayer dielectric layer 103, and the inclination angle ⁇ 1 between the contour and the interlayer dielectric layer 103 can be 20° to 35°, for example : 20°, 25°, 30°, 35°, etc.; for example, the profile can be arc-shaped.
  • the thickness of the first encapsulation dam 1a may be 0.5 ⁇ m to 2 ⁇ m, for example: 0.5 ⁇ m, 1 ⁇ m, 1.5 ⁇ m, 2 ⁇ m, and so on.
  • the outer contour of the second encapsulation dam 1b is inclined with respect to the surface of the interlayer dielectric layer 103, and the inclination angle ⁇ 2 between the contour and the interlayer dielectric layer 103 can be 20° to 35°, for example: 20°, 25°, 30°, 35°, etc.; for example, the profile can be arc-shaped.
  • the thickness of the second packaging dam 1b may be 0.5 ⁇ m to 2 ⁇ m, for example: 0.5 ⁇ m, 1 ⁇ m, 1.5 ⁇ m, 2 ⁇ m, and so on.
  • the inclination angle ⁇ 2 between the second encapsulation dam 1b and the interlayer dielectric layer 103 is greater than that between the first encapsulation dam 1a and the interlayer dielectric layer 103.
  • the distance h1 between the first encapsulation dam 1a and the second encapsulation dam 1b is relatively small, so as to ensure that the first encapsulation dam 1a and the second encapsulation dam 1b can block the encapsulation layer 118.
  • the organic packaging film material flows to the opening area 10b, it can also reduce the proportion of the transition area 10c in the display substrate, thereby increasing the proportion of other areas, such as the display area 10a; and the first packaging dam 1a and The distance h2 between the display areas 10a is relatively large, in order to facilitate the design of the inner ring wiring area 10e, the isolation area 10d, etc.; and the distance h3 between the second packaging dam 1b and the opening area 10b is relatively large, so that the laser cutting In the process of the hole area, it is possible to prevent the second packaging dam 1b from being damaged or falling off due to excessively high temperature, thereby improving the packaging stability. Based on this, in some embodiments, as shown in FIG.
  • the distance h1 between the first packaging dam 1a and the second packaging dam 1b may be less than the distance h2 between the first packaging dam 1a and the display area 10a; and/or less than The distance h3 between the second encapsulation dam 1b and the opening area 10b. .
  • the transition area 10c may further include a third packaging dam 1c, a barrier wall 135, and an organic insulation packaging portion 139; wherein:
  • the third encapsulation dam 1c is arranged around the opening area 10a and is located on the side of the second encapsulation dam 1b close to the opening area 10a; the third encapsulation dam 1c and the second encapsulation dam 1b have the same structure and include the same material. Therefore, the third packaging dam 1c and the second packaging dam 1b can be formed using the same material layer and through the same patterning process.
  • the barrier wall 135 is located between the second encapsulation dam 1b and the third encapsulation dam 1c, and the barrier wall 135 is arranged around the third encapsulation dam 1c.
  • the barrier wall 135 may include a first film layer 136 provided in the same layer as the gate electrode 106 and the first electrode plate 130, a second film layer 137 provided in the same layer as the second electrode plate 131, and the source electrode 110
  • the third film layer 138 provided in the same layer as the drain electrode 111, the second gate insulating layer 108 located between the first film layer 136 and the second film layer 137, and the third film layer 138 and the second film layer 137
  • the interlayer dielectric layer 103 between.
  • the first film layer 136, the gate 106, and the first electrode plate 130 have the same structure and include the same material; the second film layer 137 and the second electrode plate 131 have the same structure and include the same Material;
  • the third film layer 138 has the same structure as the source 110 and the drain 111 and includes the same material. Therefore, the first film layer 136, the gate 106, and the first electrode plate 130 can be formed by using the same material layer and through the same patterning process; the second film layer 137 and the second electrode plate 131 can be formed by using the same material layer and through The third film layer 138 and the source electrode 110 and the drain electrode 111 can be formed using the same material layer and formed by the same patterning process.
  • the organic insulating encapsulation portion 139 is between the third encapsulation dam 1c and the second encapsulation dam 1b and covers the barrier wall 135.
  • the organic insulating encapsulation portion 139 and the organic encapsulation film layer 118b of the encapsulation layer 118 have the same material, for example, the same Formed by inkjet printing process.
  • the third encapsulation dam 1c, the barrier wall 135, and the organic insulation encapsulation portion 139 are provided to provide a further barrier effect, so that the transition area 10c can fully isolate the opening area 10b and the display area 10a, and prevent water and oxygen.
  • Other impurities enter the display region 10a from the opening region 10b, and prevent cracks that may be formed when the opening region 10b is formed from extending to the display region 10a.
  • the transition area 10c includes the third encapsulation dam 1c, the barrier wall 135 and the organic insulating encapsulation part 139
  • the aforementioned first inorganic encapsulation film layer 118a also covers the third encapsulation dam 1c and the barrier wall 135
  • the organic encapsulation film The layer 118b and the organic insulating packaging portion 139 are formed by an inkjet printing process
  • the second inorganic packaging film layer 118c also covers the third packaging dam 1c, the barrier wall 135 and the organic insulating packaging portion 139.
  • the first encapsulation dam 1a, the second encapsulation dam 1b, the third encapsulation dam 1c, and the barrier wall 135 are The orthographic projection on the base substrate can also be a circular ring; when the opening area 10b is rectangular, the first packaging dam 1a, the second packaging dam 1b, the third packaging dam 1c, and the barrier wall 135 are on the base substrate.
  • the projection can also be a rectangular ring; but it is not limited to this opening area 10b can also have other regular or irregular shapes, and the first encapsulation dam 1a, the second encapsulation dam 1b, the third encapsulation dam 1c, and the barrier wall 135 can be the same. adaptation.
  • the display substrate 10 further includes an isolation pillar 124 located in the isolation region 10d, and the isolation pillar 124 is formed on the side of the interlayer dielectric layer 103 away from the base substrate And is arranged around the first packaging dam 1a, and the side wall of the isolation column 124 is provided with a groove 124a; so that when the luminescent material or cathode material is evaporated, the luminescent material layer 114 and the cathode (ie, the second electrode 115) are here
  • the grooves 124a are discontinuous, which can block the path of water and oxygen in the opening area 10b to the display area 10a, thereby further preventing the light-emitting portion 114a of the display area 10a from being corroded, and improving the display effect and extension of the display substrate 10.
  • the service life of the product is increased.
  • isolation pillars 124 is not limited to one, but may also be multiple.
  • the isolation pillar 124 can be arranged in the same layer as the source 110 and the drain 111 of the thin film transistor, that is, the isolation pillar 124, the source 110, and the drain 111 are formed by the same patterning process. The processing steps and the use of masks can reduce costs. In addition, it should be understood that the isolation pillar 124 may be disconnected from the source 110 and the drain 111 of the thin film transistor to prevent the isolation pillar 124 from being energized during display.
  • the structure and material of the isolation pillar 124 may be the same as the structure and material of the source 110 and the drain 111
  • the isolation pillar 124 may also have a three-layer metal structure.
  • the isolation pillar 124 may include a first metal layer 124b, a second metal layer 124c, and a third metal layer 124d sequentially stacked on the interlayer dielectric layer 103, and the second metal layer 124c is located between the layers.
  • the outer boundary of the orthographic projection on the dielectric layer 103 is located inside the outer boundary of the orthographic projection of the first metal layer 124b and the third metal layer 124d on the interlayer dielectric layer 103 to form a groove 124a on the sidewall of the isolation column 124,
  • the longitudinal section of the isolation column 124 is formed into an "I-shaped" structure.
  • the first metal layer 124b and the third metal layer 124d can be titanium layers, that is, the first metal layer 124b and the third metal layer 124d can be made of titanium (Ti) material, and the second metal layer 124c can be aluminum.
  • the second metal layer 124c can be made of aluminum (Al) material, which can ensure that the first metal layer 124b and the third metal layer 124d will not be etched when the second metal layer 124c is side-etched Impact.
  • the first metal layer 124b, the second metal layer 124c, and the third metal layer 124d can also be made of other materials, such as: molybdenum, aluminum and other metal materials or alloy materials, as long as the above technical effects can be achieved.
  • this disclosure does not limit this.
  • the driving circuit layer has a first slot 125 and a second slot 126 located in the isolation region 10d; the first slot 125 is located in the isolation pillar 124 close to the first package dam On one side of 1a, the first slot 125 is arranged around the first encapsulation dam 1a; the second slot 126 is located on the side of the isolation column 124 close to the display area 10a, and the second slot 126 is arranged around the first slot 125, which is designed like this The probability that the luminescent material is disconnected at the side of the isolation pillar 124 can be increased.
  • first slot 125 and the second slot 126 can penetrate part of the driver circuit layer, and the first slot 125 and the second slot 126 are formed on the side of the driver circuit layer away from the base substrate; in addition, the first slot The slot 125 and the second slot 126 can also run through the entire driving circuit layer, that is, the slot can extend to the buffer layer 102.
  • the first slot 125 and the second slot 126 can penetrate the entire driving circuit layer to further increase the probability that the luminescent material or the cathode material is disconnected on the side of the isolation column 124; in addition, the display substrate 10 has When flexible and bent, this design can also relieve the stress on the portion of the drive circuit layer located in the display area 10a, and ensure the connection reliability of the components in the drive circuit layer.
  • the orthographic projection of the first slot 125, the second slot 126, and the spacer 124 on the base substrate may also be a circular ring.
  • the orthographic projection of the first opening 125, the second opening 126, and the spacer 124 on the base substrate can also be a rectangular ring; but not limited to this opening area 10b can also be For other regular or irregular shapes, the first slot 125, the second slot 126, and the isolation column 124 can be adapted to it.
  • the peripheral packaging area 10g may also be provided with a first peripheral packaging dam 127 and a second peripheral packaging dam 128.
  • the second peripheral packaging dam 128 is provided at the first peripheral packaging dam 127 away from the display.
  • the thickness of the second peripheral encapsulation dam 128 is greater than the thickness of the first peripheral encapsulation dam 127; wherein, the first peripheral encapsulation dam 127 may include first peripheral barriers sequentially formed on the interlayer dielectric layer 103 Portion 127a and the first peripheral spacer portion 127b; the second peripheral encapsulation dam 128 may include a third protective portion 128a, a second peripheral barrier portion 128b, and a second peripheral spacer portion 128c sequentially formed on the interlayer dielectric layer 103 .
  • the third protection portion 128a may be provided in the same layer as the planarization portion 116 of the display area 10a, and the first peripheral barrier portion 127a and the second peripheral barrier portion 128b may be provided in the same layer as the pixel defining portion 113 of the display area 10a.
  • the first peripheral spacer portion 127b and the second peripheral spacer portion 128c can be provided in the same layer as the support portion of the display area 10a.
  • first peripheral encapsulation dam 127 may also include a protection portion located between the interlayer dielectric layer 103 and the first peripheral blocking portion 127a and provided on the same layer as the planarization portion 116, depending on the specific circumstances.
  • the thickness difference between the second peripheral packaging dam 128 and the first peripheral packaging dam 127 is greater than the thickness difference between the second packaging dam 1b and the first packaging dam 1a.
  • the driving circuit layer further includes a peripheral wiring 107 and a first peripheral transfer wiring 109a located in the peripheral wiring area 10f, and the peripheral wiring 107 may be the same layer as the source 110 and the drain 111.
  • the first peripheral transfer line 109a and the first electrode 112 can be provided in the same layer.
  • one end of the peripheral wiring 107 can extend to the peripheral packaging area 10g, and the peripheral wiring 107 can be located under the first peripheral packaging dam 127 and the second peripheral packaging dam 128; one end of the first peripheral transfer line 109a can extend to The peripheral packaging area 10g is located between the third protection portion 128a and the second peripheral blocking portion 128b in the second peripheral packaging dam 128.
  • a passivation film layer 134 can also be fabricated. After the passivation film layer 134 is patterned, not only It includes a portion located in the display area 10a, as shown in FIG. 4; and may also include a portion located in the peripheral wiring area 10f and the peripheral packaging area 10g, as shown in FIG. 9A.
  • the planarization layer can also be directly fabricated without fabricating the passivation film 134; or after the passivation film 134 is patterned, the The passivation film 134 may include a portion located in the display area 10a, while the peripheral wiring area 10f and the peripheral packaging area 10g do not have a partial structure of the passivation film 134, depending on the requirements.
  • the first peripheral transfer line 109a may be electrically connected to the peripheral wiring 107 located in the peripheral wiring area 10f through a via hole.
  • the first peripheral transfer line 109a may be under the first peripheral package dam 127 It is in contact with the peripheral wiring 107 to realize electrical connection, but it is not limited to this.
  • the first peripheral transfer line 109a can also be electrically connected to the second electrode 115 located in the peripheral wiring area 10f.
  • the surrounding wiring 107 can be a VSS power line or the like, but is not limited thereto.
  • the driving circuit layer further includes a peripheral wiring 107 located in the peripheral wiring area 10f, a first peripheral transfer line 109a, and a second peripheral transfer line 109b.
  • the peripheral wiring 107 can be sourced.
  • 110 and the drain electrode 111 are arranged in the same layer, the first peripheral transfer line 109a may be arranged in the same layer as the first electrode 112; the second peripheral transfer line 109b may be arranged in the same layer as the transfer electrode 133 of the display area 10a.
  • one end of the peripheral wiring 107 can extend to the peripheral packaging area 10g, and the peripheral wiring 107 can be located under the first peripheral packaging dam 127 and the second peripheral packaging dam 128, and one end of the first peripheral transfer line 109a can extend to
  • the peripheral packaging area 10g is located between the third protection portion 128a and the second peripheral blocking portion 128b in the second peripheral packaging dam 128; one end of the second peripheral transfer line 109b can extend to the peripheral packaging area 10g, and the second peripheral transfer The wire 109b may be located below the first peripheral encapsulation dam 127 and the second peripheral encapsulation dam 128.
  • the flattening layer can be provided with two layers, namely: a first flattening layer and a second flattening layer.
  • a planarization layer is patterned to form a first planarization film layer 116a located in the display area 10a and the peripheral wiring area 10f (as shown in FIG.
  • the second pattern block 141 is located under the second peripheral encapsulation dam 128 to heighten the second peripheral encapsulation dam 128; this second planarization layer is used to fabricate the second peripheral transfer line 109b and the transfer electrode After 133, the second planarization layer can be patterned to form the second planarization film layer 116b (shown in FIG. 4) located in the display area 10a and the peripheral wiring area 10f and located in the peripheral package.
  • the first pattern block 140 and the third protection portion 128a of the area 10g (as shown in FIG. 9B), the first pattern block 140 is located below the first peripheral packaging dam 127 to heighten the first peripheral packaging dam 127.
  • a passivation film layer 134 can also be fabricated. After the passivation film layer 134 is patterned, not only It includes the part located in the display area 10a, as shown in FIG. 4; it may also include the part located in the peripheral packaging area 10g, as shown in FIG. 9B.
  • the planarization layer may be directly formed without forming the passivation film 134; or after the passivation film 134 is patterned, the passivation layer 134 may be patterned.
  • the passivation film layer 134 may include a portion located in the display area 10a, while the peripheral packaging area 10g does not have a partial structure of the passivation film layer 134, depending on specific requirements.
  • the planarization layer may also be a single-layer structure; or after the double-layer planarization layer is patterned, the planarization layer may include a first planarization film layer 116a and a second planarization film layer 116a located in the display area 10a.
  • the planarization film layer 116b, and the peripheral packaging area 10g and the peripheral wiring area 10f may only have the structure after the patterning of the first planarization layer, but not the structure of the second planarization layer, etc. , Depending on specific needs.
  • the second peripheral transfer line 109b can be electrically connected to the peripheral wiring 107 located in the peripheral wiring area 10f through a via hole.
  • the second peripheral transfer line 109b may be under the first peripheral package dam 127 It is in contact with the peripheral wiring 107 and at the side of the second peripheral encapsulation dam 128 away from the first peripheral encapsulation dam 127 to achieve electrical connection, but is not limited to this.
  • the first peripheral patch cord 109a can be electrically connected to the second peripheral patch cord 109b located in the peripheral wiring area 10f through a via hole.
  • the first peripheral patch cord 109a can be connected to the second peripheral patch cord under the first peripheral package dam 127 109b contact to achieve electrical connection, but not limited to this.
  • the first peripheral transfer line 109a can also be electrically connected to the second electrode 115 located in the peripheral wiring area 10f.
  • the surrounding wiring 107 can be a VSS power line or the like, but is not limited thereto.
  • the peripheral wiring area 10f may not only be provided with the peripheral wiring 107, the first peripheral transfer line 109a, the second peripheral transfer line 109b, but also other wiring (not shown in the figure), it should be understood
  • other traces can include not only traces provided on the same layer as the source 110 and drain 111 and the same layer as the first electrode 112, but can also include traces that are connected to the first electrode plate 130, the second electrode plate 131 or the Connect the wires arranged on the same layer as the electrode 133.
  • the driving circuit layer further includes an inner circle signal line located in the inner circle wiring area 10e, and the inner circle signal line can be electrically connected to the signal line in the display area.
  • there may be multiple inner ring signal lines including at least a first inner ring signal line 129a arranged on the same layer as the source 110/drain 111 of the thin film transistor and the gate 106 of the thin film transistor.
  • the second inner circle signal line 129b provided on the same layer as the first electrode plate 130, and the third inner circle signal line 129c provided on the same layer as the second electrode plate 131.
  • first inner ring signal lines 129a there may be multiple first inner ring signal lines 129a, second inner ring signal lines 129b, and third inner ring signal lines 129c.
  • the first inner circle signal line 129a may include a data signal line, but is not limited to this, and may also include other signal lines, as long as the signal lines of the conductive layer can be arranged as required;
  • the ring signal line 129b may include a gate signal line, but is not limited to this, and may also include other signal lines, as long as the signal lines of the conductive layer can be arranged as required;
  • the third inner ring signal line 129c may include a reset signal Lines and initialization lines, but not limited to these, can also include other signal lines, as long as the signal lines of the conductive layer can be arranged as required.
  • the first inner circle signal line 129a may include a gate signal line, but is not limited to this, and may also include other signal lines, such as reset signal lines and initialization lines, as long as the signal lines of the conductive layer can be Arrange as required;
  • the second inner circle signal line 129b can be a data signal line, but is not limited to this, and may also include other signal lines, as long as the signal lines of the conductive layer can be arranged as required;
  • third The inner circle signal line 129c may include a data signal line, but is not limited to this, and may also include other signal lines, as long as the signal lines of the conductive layer can be arranged as required.
  • the opening area 10b in the display substrate 10 of the embodiment of the present disclosure is used to assemble devices such as a camera, a sensor, a HOME key, an earpiece, or a speaker after the opening treatment. It should be noted that, for the display substrate 10 of the embodiment of the present disclosure, as shown in FIG. 5 and FIG. 6, the opening area 10b is not subjected to the opening treatment, and the opening treatment can be performed before the assembly of the camera and other devices. In addition, the display substrate 10 of the embodiment of the present disclosure may also be processed in the opening area 10b as shown in FIG. 10. In this case, the display substrate 10 can be directly used for subsequent assembly.
  • the obtained holes include but are not limited to the following forms: through holes, grooves, openings, and the like.
  • An embodiment of the present disclosure also provides a display device, which may include the display substrate 10 described in the foregoing embodiment, and the aperture area 10b of the display substrate 10 may be processed to form an aperture, as shown in FIG. 10; As shown in FIG. 11, the display device also includes a camera, a sensor, a HOME button, an earpiece or a speaker and other functional devices 20 installed in the opening.
  • the specific type of the display device is not particularly limited, and the types of display devices commonly used in the field can be used, such as OLED (Organic Light-Emitting Diode, organic light-emitting diode) display screens, mobile devices such as mobile phones, etc.
  • OLED Organic Light-Emitting Diode, organic light-emitting diode
  • mobile devices such as mobile phones, etc.
  • Wearable devices such as watches, VR devices, etc., can be selected by those skilled in the art according to the specific use of the display device, which will not be repeated here.
  • the display device in addition to the display substrate 10 and the camera, sensor, HOME button, earpiece or speaker and other devices, the display device also includes other necessary components and components. Take the display as an example, such as a housing. , The power line, the driving chip 30, etc., those skilled in the art can make corresponding supplements according to the specific use requirements of the display device, which will not be repeated here.
  • the embodiments of the present disclosure provide a manufacturing method of a display substrate.
  • the structure of the display substrate may refer to the structure of the display substrate 10 described in the foregoing embodiments, which is not described here; wherein, as shown in FIG. 12, the manufacturing method may include:
  • Step S100 providing a base substrate
  • Step S101 forming a driving circuit layer on a base substrate, the driving circuit layer including an interlayer dielectric layer located in the display area and the transition area;
  • Step S102 forming a display device, a first packaging dam, and a second packaging dam on the side of the interlayer dielectric layer away from the base substrate;
  • the display device is located in the display area and includes first electrodes and Pixel defining part;
  • the first encapsulation dam is located in the transition area and arranged around the opening area, and the first encapsulation dam includes a first protection part and a first blocking part sequentially laminated on the interlayer dielectric layer;
  • the second encapsulation dam is located in the transition area And arranged around the opening area, the second encapsulation dam is located on the side of the first encapsulation dam away from the display area, and the thickness of the second encapsulation dam is greater than that of the first encapsulation dam.
  • the second protection part and the second blocking part on the upper part; wherein,
  • the distance between the first packaging dam and the second packaging dam is smaller than the distance between the first packaging dam and the display area.
  • the above-mentioned manufacturing method provided by the embodiment of the present disclosure should have the same features and advantages as the display substrate 10 provided by the embodiment of the present disclosure. Therefore, the above-mentioned manufacturing method provided by the embodiment of the present disclosure has the characteristics and advantages. Reference can be made to the features and advantages of the display substrate 10 described above, which will not be repeated here.
  • the first protection part and the first electrode that are disconnected from each other are formed by the same patterning process.
  • the first protection part and the planarization part that are disconnected from each other are formed by the same patterning process, and the planarization part is located in the display area and formed between the interlayer dielectric layer and the first electrode.
  • the second protection part and the first protection part which are disconnected from each other are formed by the same patterning process.
  • the second protection part and the planarization part that are disconnected from each other are formed by the same patterning process, and the planarization part is located in the display area and formed between the interlayer dielectric layer and the first electrode.
  • an isolation column in the isolation region is formed on the side of the interlayer dielectric layer away from the base substrate, the isolation column is arranged around the transition region, and the sidewall of the isolation column is provided with a groove.
  • the driving circuit layer includes a thin film transistor located in the display area, and the thin film transistor includes a source electrode and a drain electrode;
  • the source electrode, the drain electrode and the isolation pillars that are disconnected from each other are formed by the same patterning process.
  • the display substrate further has an inner ring wiring area located between the isolation area and the display area, the inner ring wiring area is arranged around the isolation area;
  • the driving circuit layer further includes an inner ring signal located in the inner ring wiring area Line, the inner circle signal line is electrically connected with the signal line in the display area.
  • the method further includes:
  • the encapsulation layer includes a first inorganic encapsulation film layer, an organic encapsulation film layer, and a second inorganic encapsulation film layer stacked in sequence;
  • the first inorganic encapsulation film layer and the second inorganic encapsulation film layer encapsulate the first encapsulation dam, the second encapsulation dam and the display device;
  • the organic encapsulation film layer encapsulates the display device and blocks the side of the first encapsulation dam close to the display area.
  • the display area 10a of the display substrate 10 and the preparation method thereof will be introduced in conjunction with the pixel circuit and layout of the display area 10a of the display substrate 10.
  • FIG. 13 is an equivalent circuit diagram of a pixel circuit in a display area of a display substrate provided by at least one embodiment of the present disclosure
  • FIGS. 14A-10E are various pixel circuits in a display area of a display substrate provided by some embodiments of the present disclosure.
  • FIG. 13 is an equivalent circuit diagram of a pixel circuit in a display substrate provided by at least one embodiment of the present disclosure
  • FIGS. 14A-10E are schematic diagrams of various layers of a pixel circuit in a display substrate provided by some embodiments of the present disclosure.
  • the pixel circuit in the display area in the driving circuit layer includes a plurality of thin film transistors T1, T2, T3, T4, T5, T6, and T7, connected to a plurality of thin film transistors T1, T2. , T3, T4, T5, T6 and T7 multiple signal lines and storage capacitor Cst, multiple signal lines include gate line GL (ie scanning signal line), light-emitting control line EM, initialization line RL, data line DAT and first Power supply line VDD.
  • the gate line GL may include a first gate line GLn and a second gate line GLn-1.
  • the first gate line GLn may be used to transmit a gate scan signal
  • the second gate line GLn-1 may be used to transmit a reset signal
  • the light emission control line EM can be used to transmit light emission control signals.
  • the pixel circuit is a 7T1C pixel circuit.
  • the embodiments of the present disclosure include but are not limited to this, and the pixel circuit may also adopt other types of circuit structures, such as 7T2C structure or 9T2C structure, etc.
  • the embodiment of the present disclosure does not limit this.
  • the first gate line GLn of the pixel circuit corresponding to each row of light-emitting sub-pixels 1d in the display area 10a located on the left and right sides of the opening area 10b can be electrically connected through the inner gate signal line to transmit the gate scanning signal, thereby Realize the compensation effect of the gate scanning signal.
  • the first gate G1 of the first thin film transistor T1 is electrically connected to the third drain D3 of the third thin film transistor T3 and the fourth drain D4 of the fourth thin film transistor T4.
  • the first source S1 of the first thin film transistor T1 is electrically connected to the second drain D2 of the second thin film transistor T2 and the fifth drain D5 of the fifth thin film transistor T5.
  • the first drain electrode D1 of the first thin film transistor T1 is electrically connected to the third source electrode S3 of the third thin film transistor T3 and the sixth source electrode S6 of the sixth thin film transistor T6.
  • the second gate G2 of the second thin film transistor T2 is configured to be electrically connected to the first gate line GLn to receive a gate scan signal
  • the second source S2 of the second thin film transistor T2 is configured
  • the second drain electrode D2 of the second thin film transistor T2 is electrically connected to the first source electrode S1 of the first thin film transistor T1.
  • the third gate G3 of the third thin film transistor T3 is configured to be electrically connected to the first gate line GLn, and the third source S3 of the third thin film transistor T3 is connected to the third source S3 of the first thin film transistor T1.
  • a drain D1 is electrically connected, and the third drain D3 of the third thin film transistor T3 is electrically connected with the first gate G1 of the first thin film transistor T1.
  • the fourth gate G4 of the fourth thin film transistor T4 is configured to be electrically connected to the second gate line GLn-1 to receive a reset signal
  • the fourth source S4 of the fourth thin film transistor T4 is configured
  • the fourth drain electrode D4 of the fourth thin film transistor T4 is electrically connected to the first gate electrode G1 of the first thin film transistor T1.
  • the fifth gate G5 of the fifth thin film transistor T5 is configured to be electrically connected to the emission control line EM to receive the emission control signal
  • the fifth source S5 of the fifth thin film transistor T5 is configured to be connected to the emission control line EM.
  • the first power line VDD is electrically connected to receive the first power signal
  • the fifth drain electrode D5 of the fifth thin film transistor T5 is electrically connected to the first source electrode S1 of the first thin film transistor T1.
  • the sixth gate G6 of the sixth thin film transistor T6 is configured to be electrically connected to the emission control line EM to receive the emission control signal, and the sixth source S6 of the sixth thin film transistor T6 and the first thin film
  • the first drain D1 of the transistor T1 is electrically connected
  • the sixth drain D6 of the sixth thin film transistor T6 is electrically connected to the first display electrode (for example, the first electrode 112) of the light-emitting sub-pixel 1d.
  • the seventh gate G7 of the seventh thin film transistor T7 is configured to be electrically connected to the second gate line GLn-1 to receive a reset signal
  • the seventh source S7 of the seventh thin film transistor T7 is The first display electrode (for example, the first electrode 112) of the sub-pixel 1d is electrically connected
  • the seventh drain electrode D7 of the seventh thin film transistor T7 is configured to be electrically connected to the initialization line RL to receive the initialization signal.
  • the seventh drain electrode D7 of the seventh thin film transistor T7 may be electrically connected to the initialization line RL by being connected to the fourth source electrode S4 of the fourth thin film transistor T4.
  • the storage capacitor Cst includes a first capacitor electrode CE1 (ie, a first electrode plate 130) and a second capacitor electrode CE2 (ie, a second electrode plate 131).
  • the second capacitor electrode CE2 is electrically connected to the first power line VDD
  • the first capacitor electrode CE1 is electrically connected to the first gate G1 of the first thin film transistor T1 and the third drain D3 of the third thin film transistor T3.
  • the second display electrode (e.g., the second electrode 115) of the light-emitting sub-pixel 1d is electrically connected to the second power supply line VSS.
  • first power line VDD and the second power line VSS are a power line that provides a high voltage, and the other is a power line that provides a low voltage.
  • first power line VDD provides a constant first voltage
  • first voltage is a positive voltage
  • second power line VSS provides a constant second voltage
  • the second voltage may be a negative voltage.
  • the second voltage may be a ground voltage.
  • transistors can be divided into N-type transistors and P-type transistors.
  • the embodiments of the present disclosure take the transistors as P-type transistors (for example, P-type TFTs) as an example to illustrate in detail.
  • the first thin film transistor T1, the second thin film transistor T2, the third thin film transistor T3, the fourth thin film transistor T4, the fifth thin film transistor T5, and the sixth thin film transistor The transistor T6, the seventh thin film transistor T7, etc. may all be P-type transistors.
  • the transistors in the embodiments of the present disclosure are not limited to P-type transistors, and those skilled in the art can also use N-type transistors (for example, N-type TFTs) to implement the functions of one or more transistors in the embodiments of the present disclosure according to actual needs.
  • N-type transistors for example, N-type TFTs
  • the transistors used in the embodiments of the present disclosure may be thin film transistors or field effect transistors or other switching devices with the same characteristics.
  • the thin film transistors may include oxide semiconductor thin film transistors, amorphous silicon thin film transistors, or polysilicon thin film transistors.
  • the source and drain of the transistor can be symmetrical in structure, so the source and drain can be indistinguishable in physical structure. In the embodiments of the present disclosure, the source and drain of all or part of the transistor can be as required Are interchangeable.
  • the pixel circuit includes the above-mentioned thin film transistors T1, T2, T3, T4, T5, T6, and T7, a storage capacitor Cst, and a plurality of thin film transistors T1, T2, T3, T4. , T5, T6, and T7 of the first gate line GLn, the second gate line GLn-1, the light emission control line EM, the initialization line RL, the data line DAT, and the first power supply line VDD.
  • T5, T6, and T7 of the first gate line GLn the second gate line GLn-1
  • the light emission control line EM the initialization line RL
  • the data line DAT the data line DAT
  • VDD first power supply line
  • FIG. 14A is a schematic diagram of the stacked positional relationship of the semiconductor layer, the first conductive layer, the second conductive layer, and the third conductive layer of the pixel circuit.
  • FIG. 14B shows the semiconductor layer of the pixel circuit.
  • the semiconductor layer shown in FIG. 14B includes the active layer 104 shown in FIGS. 3 and 4, and the active layer 104 is, for example, the active layer of the sixth thin film transistor T6.
  • the semiconductor layer can be formed by a patterning process using a semiconductor material layer.
  • the semiconductor layer can be used to make the aforementioned first thin film transistor T1, second thin film transistor T2, third thin film transistor T3, fourth thin film transistor T4, fifth thin film transistor T5, sixth thin film transistor T6, and seventh thin film transistor T7.
  • the source layer, each active layer may include a source region, a drain region, and a channel region between the source region and the drain region.
  • the semiconductor layer can be made of amorphous silicon, polysilicon, oxide semiconductor materials, or the like. It should be noted that the aforementioned source region and drain region may be regions doped with n-type impurities or p-type impurities.
  • an insulating layer is formed on the above-mentioned semiconductor layer, and the insulating layer includes the first gate insulating layer 105 shown in FIGS. 3 and 4, which are not shown in FIGS. 14A-10E. out.
  • FIG. 14C shows the first conductive layer of the pixel circuit.
  • the first conductive layer of the pixel circuit is provided on the above-mentioned insulating layer so as to be insulated from the semiconductor layer shown in FIG. 14B.
  • the first conductive layer may include the first capacitor electrode CE1 (equivalent to the first electrode plate 130) of the storage capacitor Cst, the first gate line GLn, the second gate line GLn-1, the light emission control line EM, and the first thin film transistor T1 ,
  • the gates of the second thin film transistor T2, the third thin film transistor T3, the fourth thin film transistor T4, the fifth thin film transistor T5, the sixth thin film transistor T6, and the seventh thin film transistor T7 for example, the first gate G1, The second, second grid G2, third grid G3, fourth grid G4, fifth grid G5, sixth grid G6, and seventh grid G7).
  • the first gate G1 the second, second grid G2, third grid G3, fourth grid G4, fifth grid G5, sixth grid G6, and seventh grid G7.
  • the gates of the second thin film transistor T2, the fourth thin film transistor T4, the fifth thin film transistor T5, the sixth thin film transistor T6, and the seventh thin film transistor T7 are the first gate line GLn and the second gate line GLn- 1.
  • the third thin film transistor T3 may be a thin film transistor with a double gate structure, and a gate of the third thin film transistor T3 may be the overlap between the first gate line GLn and the semiconductor layer Partly, the other gate of the third thin film transistor T3 may be a protrusion protruding from the first gate line GLn; the gate of the first thin film transistor T1 may be the first capacitor electrode CE1.
  • the fourth thin film transistor T4 may be a thin film transistor with a double-gate structure, and the two gates are respectively the overlapping portions of the second gate line GLn-1 and the semiconductor layer.
  • another insulating layer is formed on the above-mentioned first conductive layer, and the insulating layer includes the second gate insulating layer 108 shown in FIG. 3 and FIG. 4, FIG. 14A- Not shown in 10E.
  • FIG. 14D shows the second conductive layer of the pixel circuit.
  • the second conductive layer of the pixel circuit includes the second capacitor electrode CE2 (ie, the second electrode plate 131) of the storage capacitor Cst and the initialization line RL.
  • the second capacitor electrode CE2 and the first capacitor electrode CE1 at least partially overlap to form a storage capacitor Cst.
  • the second capacitor electrode CE2 shown in FIG. 14D has a gap.
  • the second capacitor electrode CE2 may not have the gap.
  • the embodiment of the present disclosure does not limit the specific structure of the second capacitor electrode CE2.
  • the second conductive layer may further include a first light shielding portion 791 and a second light shielding portion 792.
  • the orthographic projection of the first light shielding portion 791 on the base substrate covers the active layer between the active layer of the second thin film transistor T2, the drain of the third thin film transistor T3, and the drain of the fourth thin film transistor T4, thereby preventing External light affects the active layers of the second thin film transistor T2, the third thin film transistor T3, and the fourth thin film transistor T4.
  • the orthographic projection of the second light shielding portion 792 on the base substrate covers the active layer between the two gates of the third thin film transistor T3, thereby preventing external light from affecting the active layer of the third thin film transistor T3.
  • the first light-shielding portion 791 may be an integral structure with the second light-shielding portion 792 of the adjacent pixel circuit, and is electrically connected to the first power line VDD through a via hole penetrating the insulating layer.
  • another insulating layer is formed on the above-mentioned second conductive layer, and the insulating layer includes the interlayer dielectric layer 103 shown in FIGS. 3 and 4, FIGS. 14A-10E Not shown in.
  • FIG. 14E shows the third conductive layer of the pixel circuit.
  • the third conductive layer of the pixel circuit includes a data line DAT and a first power supply line VDD.
  • the data line DAT passes through at least one via hole (for example, via hole VH1) in the first gate insulating layer 105, the second gate insulating layer 108, and the interlayer dielectric layer 103 and the first gate in the semiconductor layer.
  • the source regions of the two thin film transistors T2 are connected.
  • the first power line VDD is connected to the source region of the semiconductor layer corresponding to the fifth thin film transistor T5 through at least one via hole (for example, via hole VH2) in the first gate insulating layer, the second gate insulating layer and the interlayer dielectric layer.
  • the first power line VDD is connected to the second capacitor electrode CE2 in the second conductive layer through at least one via (for example, via VH3) in the interlayer dielectric layer.
  • the third conductive layer further includes a first connection portion CP1, a second connection portion CP2, and a third connection portion CP3.
  • One end of the first connecting portion CP1 passes through at least one via hole (for example, via hole VH4) in the first gate insulating layer 105, the second gate insulating layer 108, and the interlayer dielectric layer 103 with the corresponding third thin film transistor T3 in the semiconductor layer.
  • the drain region is connected, and the other end of the first connection portion CP1 is connected to the first thin film transistor T1 in the first conductive layer through at least one via hole (for example, via hole VH5) in the second gate insulating layer 108 and the interlayer dielectric layer 103
  • the gate is connected.
  • One end of the second connection portion CP2 is connected to the initialization line RL through a via hole (for example, via hole VH6) in the interlayer dielectric layer, and the other end of the second connection portion CP2 is connected through the first gate insulating layer 105 and the second gate insulating layer
  • a via hole for example, via hole VH6
  • At least one via hole for example, via hole VH7 in 108 and the interlayer dielectric layer 103 is connected to the source region of the seventh thin film transistor T7 and the source region of the fourth thin film transistor T4 in the semiconductor layer.
  • the third connection portion CP3 passes through at least one via hole (for example via hole VH8) in the first gate insulating layer 105, the second gate insulating layer 108, and the interlayer dielectric layer 103 and the drain of the sixth thin film transistor T6 in the semiconductor layer.
  • the areas are connected.
  • the pixel circuit of the display substrate may further have a fourth conductive layer.
  • FIG. 14F shows the fourth conductive layer of the pixel circuit.
  • the fourth conductive layer includes a second power line VDD2 and a third power line VDD3.
  • the second power line VDD2 extends in the vertical direction in the figure.
  • the third power line VDD3 and the second power line VDD2 intersect.
  • the second power supply line VDD2 and the third power supply line VDD3 are electrically connected to each other or have an integrated structure.
  • the second power line VDD2 and the third power line VDD3 are electrically connected to the first power line VDD through via holes, thereby forming a meshed power line structure.
  • This structure helps to reduce the resistance on the power line, thereby reducing the voltage drop of the power line, and helps to evenly transmit the power supply voltage to each sub-pixel of the display substrate.
  • the fourth conductive layer further includes a fourth connection portion CP4 insulated from the second power supply line VDD2 and the third power supply line VDD3, and the fourth connection electrode 234 is used to connect the sixth transistor T6
  • the drain D6 is electrically connected to the light-emitting sub-pixel 1d.
  • the fourth connection electrode 234 is implemented as the transfer electrode 133 in the above embodiment, and is used to electrically connect the first electrode 112 of the light-emitting sub-pixel 1d and the drain 111 of the thin film transistor.
  • a protective layer is formed on the above-mentioned fourth conductive layer, and the protective layer includes the planarization portion 116 shown in FIGS. 3 and 4, which are not shown in FIGS. 14A-10E. out.
  • the above-mentioned conductive layers may also adopt other layouts.
  • FIG. 15A shows another layout design of another second conductive layer pattern.
  • the second conductive layer includes the second capacitor electrode CE2 (ie, the second electrode plate 131) of the storage capacitor Cst, the reset signal line Init1, the second power signal line VDD2, and the light shielding portion S .
  • the second power signal line VDD2 is formed integrally with the second capacitor electrode CE2.
  • FIG. 15B shows another layout design of another third conductive layer pattern.
  • the third conductive layer includes a data line Vd, a first power signal line VDD1, and a shield line PB.
  • the above-mentioned data line Vd, the first power signal line VDD1 and the shielding line PB all extend in the same direction, such as the vertical direction in the figure.
  • the third conductive layer may further include a first connection portion CP1, a second connection portion CP2, and a third connection portion CP3 for electrically connecting different wires or electrodes.
  • FIG. 15C shows another layout design of another fourth conductive layer pattern.
  • the fourth conductive layer includes a fourth connection portion CP4 and a third power signal line VDD3 distributed across the vertical direction and the horizontal direction in the figure.
  • the third power signal line VDD3 may be connected in parallel with the first power signal line VDD1 to form a mesh power structure, which is beneficial to reduce the resistance of the power signal line.

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  • Electroluminescent Light Sources (AREA)

Abstract

一种显示基板及其制作方法、显示装置，显示基板包括：衬底基板；驱动电路层，形成在衬底基板上，且包括位于显示区（10a）和过渡区（10c）的层间介质层（103）；显示器件，位于显示区（10a），并包括依次形成在层间介质层（103）上的第一电极（112）和像素界定部（113）；第一封装坝（1a）和第二封装坝（1b），位于过渡区（10c）并环绕开孔区（10b）设置，且均包括依次层叠在层间介质层（103）上的保护部（119,120）和阻隔部（117,121）；第二封装坝（1b）位于第一封装坝（1a）远离显示区（10a）的一侧，且其厚度大于第一封装坝（1a）的厚度；第一阻隔部（117）、第二阻隔部（121）与像素界定部（113）同层设置、且相互断开；且第一封装坝（1a）与第二封装坝（1b）之间的间距小于第一封装坝（1a）与显示区（10a）的间距。可延长产品的使用寿命及显示效果。

Description

显示基板及其制作方法、显示装置 技术领域
本公开实施例涉及显示技术领域，特别涉及一种显示基板及其制作方法、显示装置。
背景技术
随着科技的进步，近年来，异形屏以及全面屏已经逐渐走入大家的视野。不论是异形屏还是全面屏目的都是为了提升显示设备的屏占比。那么，为了实现更高的屏占比，在显示屏的一些位置上需要为一些附加部件(例如摄像头、传感器等等)预留一些开口区域(例如开孔)。
随着显示器技术发展和更新换代，有机电致发光显示器件(Organic Electroluminance Display，简称为：OLED)由于具有自发光、高亮度、高对比度、低工作电压、可制作柔性显示器等特点，已经逐渐成为显示领域的主流产品。
但对于OLED显示面板而言，外界的水氧可能会由开孔位置沿发光层进入显示屏内部，对显示屏内部造成侵蚀，导致显示失效。
发明内容
本公开实施例提供一种显示基板及其制作方法、显示装置，可避免水汽和氧气从开孔区的开口进入显示区，从而可延长产品的使用寿命及显示效果。
在本公开的一种实施例中，提供了一种显示基板，所述显示基板具有显示区、开孔区及位于所述显示区与开孔区之间的过渡区，所述过渡区环绕所述开孔区设置；其中，所述显示基板包括：
衬底基板；
驱动电路层，形成在所述衬底基板上，所述驱动电路层包括位于 所述显示区和所述过渡区的层间介质层；
显示器件，位于所述显示区，并包括依次形成在所述层间介质层上的第一电极和像素界定部；
第一封装坝，位于所述过渡区并环绕所述开孔区设置，且所述第一封装坝包括依次层叠在所述层间介质层上的第一保护部和第一阻隔部；
第二封装坝，位于所述过渡区并环绕所述开孔区设置，所述第二封装坝位于所述第一封装坝远离所述显示区的一侧，且所述第二封装坝的厚度大于所述第一封装坝的厚度，所述第二封装坝包括依次层叠在所述层间介质层上的第二保护部和第二阻隔部；其中，
所述第一阻隔部、所述第二阻隔部与所述像素界定部同层设置、且相互断开；
且所述第一封装坝与所述第二封装坝之间的间距小于所述第一封装坝与所述显示区的间距。
在本公开的一种示例性实施例中，所述第二保护部的厚度大于所述第一保护部的厚度。
在本公开的一种示例性实施例中，所述第一保护部与所述第一电极同层设置、且相互断开。
在本公开的一种示例性实施例中，所述显示基板还包括平坦化部，所述平坦化部位于所述显示区并形成在所述层间介质层与所述第一电极之间；
其中，所述第一保护部与所述平坦化部同层设置、且相互断开。
在本公开的一种示例性实施例中，所述第二保护部与所述第一保护部同层设置。
在本公开的一种示例性实施例中，所述显示基板还包括平坦化部，所述平坦化部位于所述显示区并形成在所述层间介质层与所述第一电极之间；
其中，所述第二保护部与所述平坦化部同层设置、且相互断开。
在本公开的一种示例性实施例中，所述第一封装坝和所述第二封装坝中的至少一者还包括隔垫部，所述隔垫部形成在所述第一阻隔部 或所述第二阻隔部背离所述层间介质层的一侧；
所述显示器件还包括支撑部，所述支撑部形成在所述像素界定部背离所述衬底基板的一侧，所述支撑部与所述隔垫部同层设置。
在本公开的一种示例性实施例中，所述显示基板还具有位于所述显示区与所述过渡区之间的隔离区，所述隔离区环绕所述过渡区设置；
所述显示基板还包括隔离柱，形成在所述层间介质层背离所述衬底基板的一侧并位于所述隔离区，所述隔离柱环绕所述第一封装坝设置，所述隔离柱的侧壁设置有凹槽。
在本公开的一种示例性实施例中，所述驱动电路层包括位于所述显示区的薄膜晶体管，所述薄膜晶体管的源极和漏极与所述隔离柱同层设置、且相互断开。
在本公开的一种示例性实施例中，所述显示基板还具有位于所述隔离区与所述显示区之间的内圈走线区，所述内圈走线区环绕所述隔离区设置；
所述驱动电路层还包括位于所述内圈走线区的内圈信号线，所述内圈信号线与所述显示区的信号走线电连接。
在本公开的一种示例性实施例中，所述隔离柱包括依次层叠在所述层间介质层上的第一金属层、第二金属层及第三金属层，所述第二金属层在所述层间介质层上的正投影的外边界位于所述第一金属层、所述第三金属层在所述层间介质层上的正投影的外边界内侧，以在所述隔离柱的侧壁形成所述凹槽。
在本公开的一种示例性实施例中，所述第一金属层和所述第三金属层为钛层，所述第二金属层为铝层。
在本公开的一种示例性实施例中，所述驱动电路层具有位于所述隔离区的第一开槽和第二开槽；所述第一开槽位于所述隔离柱靠近所述第一封装坝的一侧，所述第一开槽环绕所述第一封装坝设置；所述第二开槽位于所述隔离柱靠近所述显示区的一侧，所述第二开槽环绕所述第一开槽设置；
其中，所述第一开槽和所述第二开槽贯穿所述驱动电路层。
在本公开的一种示例性实施例中，所述显示基板还包括封装层， 所述封装层包括依次层叠设置的第一无机封装薄膜层、有机封装薄膜层和第二无机封装薄膜层；
所述第一无机封装薄膜层和所述第二无机封装薄膜层封装所述第一封装坝、所述第二封装坝和所述显示器件；
所述有机封装薄膜层封装所述显示器件，并在所述第一封装坝靠近所述显示区的一侧阻断。
在本公开的一种实施例中，还提供了一种显示基板的制作方法，所述显示基板具有显示区、开孔区及位于所述显示区与开孔区之间的过渡区，所述过渡区环绕所述开孔区设置；其中，所述制作方法包括：
提供一衬底基板；
在所述衬底基板上形成驱动电路层，所述驱动电路层包括位于所述显示区和所述过渡区的层间介质层；
在所述层间介质层背离所述衬底基板的一侧形成显示器件、第一封装坝和第二封装坝；所述显示器件位于所述显示区，并包括依次形成在所述层间介质层上的第一电极和像素界定部；所述第一封装坝位于所述过渡区并环绕所述开孔区设置，且所述第一封装坝包括依次层叠在所述层间介质层上的第一保护部和第一阻隔部；所述第二封装坝位于所述过渡区并环绕所述开孔区设置，所述第二封装坝位于所述第一封装坝远离所述显示区的一侧，且所述第二封装坝的厚度大于所述第一封装坝的厚度，所述第二封装坝包括依次层叠在所述层间介质层上的第二保护部和第二阻隔部；其中，
利用同一次构图工艺形成相互断开的所述第一阻隔部、所述第二阻隔部与所述像素界定部；
且所述第一封装坝与所述第二封装坝之间的间距小于所述第一封装坝与所述显示区的间距。
在本公开的一种示例性实施例中，利用同一次构图工艺形成相互断开的所述第一保护部与所述第一电极。
在本公开的一种示例性实施例中，利用同一次构图工艺形成相互断开的所述第一保护部和平坦化部，所述平坦化部位于所述显示区并形成在所述层间介质层与所述第一电极之间。
在本公开的一种示例性实施例中，利用同一次构图工艺形成相互断开的所述第二保护部与所述第一保护部。
在本公开的一种示例性实施例中，利用同一次构图工艺形成相互断开的所述第二保护部和平坦化部，所述平坦化部位于所述显示区并形成在所述层间介质层与所述第一电极之间。
在本公开的一种示例性实施例中，所述显示基板还具有位于所述显示区与所述过渡区之间的隔离区，所述隔离区环绕所述过渡区设置；其中，所述制作方法还包括：
在所述层间介质层背离所述衬底基板的一侧形成位于所述隔离区的隔离柱，所述隔离柱环绕所述过渡区设置，所述隔离柱的侧壁设置有凹槽。
在本公开的一种示例性实施例中，所述驱动电路层包括位于所述显示区的薄膜晶体管，所述薄膜晶体管包括源极和漏极；
其中，利用同一次构图工艺形成相互断开的所述源极、所述漏极和所述隔离柱。
在本公开的一种示例性实施例中，所述显示基板还具有位于所述隔离区与所述显示区之间的内圈走线区，所述内圈走线区环绕所述隔离区设置；所述驱动电路层还包括位于所述内圈走线区的内圈信号线，所述内圈信号线与所述显示区的信号走线电连接。
在本公开的一种示例性实施例中，在所述层间介质层背离所述衬底基板的一侧形成显示器件、第一封装坝和第二封装坝之后，还包括：
形成封装层，所述封装层包括依次层叠设置的第一无机封装薄膜层、有机封装薄膜层和第二无机封装薄膜层；
所述第一无机封装薄膜层和所述第二无机封装薄膜层封装所述第一封装坝、所述第二封装坝和所述显示器件；
所述有机封装薄膜层封装所述显示器件，并在所述第一封装坝靠近所述显示区的一侧阻断。
在本公开的一种实施例中，又提供了一种显示装置，其中，包括上述任一项所述的显示基板。
附图说明
附图用来提供对本公开实施例的进一步理解，并且构成说明书的一部分，与本公开实施例一起用于解释本公开，并不构成对本公开的限制。通过参考附图对详细示例实施例进行描述，以上和其它特征和优点对本领域技术人员将变得更加显而易见，在附图中：
图1为本公开的一实施例中所述的显示基板的平面示意图；
图2为本公开的一实施例中所述的衬底基板的示意图；
图3为图1所示的一实施例所述的显示基板在A-A方向上的截面图；
图4为图1所示的另一实施例所述的显示基板在A-A方向上的截面图；
图5为图1所示的一实施例所述的显示基板在B-B方向上的截面图；
图6为图1所示的另一实施例所述的显示基板在B-B方向上的截面图；
图7为图6所示的显示基板中阻隔墙的截面图；
图8为本公开的一实施例中所述的显示基板的隔离区中隔离柱的截面图；
图9A和图9B为图1所示的不同实施例下所述的显示基板在C-C方向上的截面图；
图10为图1所示的又一实施例所述的显示基板在B-B方向上的截面图；
图11为本公开的一实施例中所述的显示装置的平面示意图；
图12为本公开的一实施例中所述的显示基板的制作方法的流程图；
图13为本公开至少一实施例提供的一种显示基板中显示区的像素电路的等效电路图；
图14A-14E为本公开一些实施例提供的一种显示基板中显示区的像素电路的各层的版图设计；
图14F为本公开一些实施例提供的一种显示基板中显示区的像素电路的一个导电层的版图设计；
图15A为本公开一些实施例提供的一种显示基板中显示区的的像素电路的第二导电层的另一版图设计；
图15B为本公开一些实施例提供的一种显示基板中显示区的的像素电路的第三导电层的另一版图设计；
图15C为本公开一些实施例提供的一种显示基板中显示区的的像素电路的第四导电层的另一版图设计；
图16A为本公开一些实施例提供的一种显示基板中第一封装坝和第二封装坝在扫描电子显微镜下的示意图；
图16B为示出了图16A中P处观察口在扫描电子显微镜下的示意图；
图16C为示出了图16A中Q处观察口在扫描电子显微镜下的示意图；
图17为本公开一些实施例提供的一种显示基板中部分结构的俯视示意图。
附图说明：
10、显示基板；10a、显示区；10b、开孔区；10c、过渡区；10d、隔离区；10e、内圈走线区；10f、外围走线区；10g、外围封装区；101、聚酰亚胺层；102、缓冲层；103、层间介质层；104、有源层；105、第一栅绝缘层；106、栅极；107、外围走线；108、第二栅绝缘层；109a、第一外围转接线；109b、第二外围转接线；110、源极；111、漏极；112、第一电极；113、像素界定部；114、发光材料层；114a、发光部；115、第二电极；116、平坦化部；116a、第一平坦化膜层；116b、第二平坦化膜层；117、第一阻隔部；118、封装层；118a第一无机封装薄膜层；118b、有机封装薄膜层；118c、第二无机 封装薄膜层；119、第一保护部；120、第二保护部；121、第二阻隔部；122、第一隔垫部；123、第二隔垫部；124、隔离柱；124a、凹槽；124b、第一金属层；124c、第二金属层；124d、第三金属层；125、第一开槽；126、第二开槽；127、第一外围封装坝；127a、第一外围阻隔部；127b、第一外围隔垫部；128、第二外围封装坝；128a、第三保护部；128b、第二外围阻隔部；128c、第一外围隔垫部；129a、第一内圈信号线；129b第二内圈信号线；129c、第三内圈信号线；130、第一极板；131、第二极板；132、支撑部；133、转接电极；134、钝化膜层；135、阻隔墙；136、第一膜层；137、第二膜层；138、第三膜层；139、有机绝缘封装部；140、第一图案块；141、第二图案块；1a、第一封装坝；1b、第二封装坝；1c、第三封装坝；1d、发光子像素；
20、功能器件；
30、驱动芯片。
具体实施方式
下面通过实施例，并结合附图，对本公开的技术方案作进一步具体的说明。在说明书中，相同或相似的附图标号指示相同或相似的部件。下述参照附图对本公开实施方式的说明旨在对本公开的总体发明构思进行解释，而不应当理解为对本公开的一种限制。
另外，在下面的详细描述中，为便于解释，阐述了许多具体的细节以提供对本披露实施例的全面理解。然而明显地，一个或多个实施例在没有这些具体细节的情况下也可以被实施。
需要说明的是，本文中所述的“在……上”、“在……上形成”和“设置在……上”可以表示一层直接形成或设置在另一层上，也可以表示一层间接形成或设置在另一层上，即两层之间还存在其它的层。
用语“一个”、“一”、“该”、“所述”和“至少一个”用以表示存在一个或多个要素/组成部分/等；用语“包括”和“具有”用以表示开放式的包括在内的意思并且是指除了列出的要素/组成部分/等之外还可存在另外的要素/组成部分/等。
需要说明的是，虽然术语“第一”、“第二”等可以在此用于描述各种部件、构件、元件、区域、层和/或部分，但是这些部件、构件、元件、区域、层和/或部分不应受到这些术语限制。而是，这些术语用于将一个部件、构件、元件、区域、层和/或部分与另一个相区分。
在本公开中，除非另有说明，所采用的术语“同层设置”指的是两个层、部件、构件、元件或部分可以通过同一构图工艺形成，并且，这两个层、部件、构件、元件或部分一般由相同的材料形成。
在本公开中，除非另有说明，表述“构图工艺”一般包括光刻胶的涂布、曝光、显影、刻蚀、光刻胶的剥离等步骤。表述“一次构图工艺”意指使用一块掩模板形成图案化的层、部件、构件等的工艺。
本公开的实施例提供了一种显示基板，该显示基板可为OLED显示基板。如图1所示，此显示基板10可具有显示区10a、开孔区10b及位于显示区10a与开孔区10b之间的过渡区10c，该过渡区10c环绕开孔区10b设置；需要说明的是，显示基板10还可包括隔离区10d、内圈走线区10e、外围走线区10f和外围封装区10g；此隔离区10d位于显示区10a与过渡区10c之间、并环绕过渡区10c设置；此内圈走线区10e位于隔离区10d与显示区10a之间、并环绕隔离区10d设置；此外围走线区10f可环绕显示区10a设置，或设置在显示区10a的两侧；而外围封装区10g可在整个衬底基板的最外缘，对整个显示基板10进行封装。
具体地，该显示基板可包括衬底基板、驱动电路层、显示器件、第一封装坝和第二封装坝；其中，
衬底基板可为柔性基板，以提高显示基板10的柔性，使得显示基板10能够具有可弯曲、可弯折等性能，以便于扩大显示基板10的适用范围；但不限于此，该衬底基板也可设置为刚性，具体该衬底基板的性能可根据产品的实际需求而定。
此外，该衬底基板可为单层结构，也可为多层结构。例如，如图2所示，该衬底基板可包括依次层叠设置的聚酰亚胺层101和缓冲层102，在另一些实施例中，衬底基板可包括多个依次层叠设置的聚酰 亚胺层101和缓冲层102；缓冲层102可为氮化硅、氧化硅等材料制作而成，以达到阻水氧和阻隔碱性离子的效果；需要说明的是，该衬底基板的结构不限于此，可根据实际需求而定。
需要说明的是，为了便于后续在显示基板10的各区域加工所需部件，可在衬底基板先定义出各区域，举例而言，可先在衬底基板上划分出显示区10a、过渡区10c、开孔区10b、隔离区10d、内圈走线区10e、外围走线区10f、外围封装区10g，即划分出整个显示基板10的显示区10a、过渡区10c、开孔区10b、隔离区10d、内圈走线区10e、外围走线区10f、外围封装区10g。
驱动电路层可形成在衬底基板上。举例而言，如图3至图6、图9A、图9B及图11所示，该驱动电路层可形成在缓冲层102上。其中，此驱动电路层可包括位于显示区10a和过渡区10c的层间介质层103，此层间介质层103采用无机材料制作而成，例如：氧化硅、氮化硅等无机材料，以达到阻水氧和阻隔碱性离子的效果；应当理解的是，在显示基板10具有隔离区10d、内圈走线区10e、外围走线区10f、外围封装区10g时，该层间介质层103还位于隔离区10d、内圈走线区10e、外围走线区10f、外围封装区10g。
详细说明，驱动电路层中位于显示区10a的部位可包括薄膜晶体管和电容结构。
如图3所示，薄膜晶体管可为顶栅型，此薄膜晶体管可包括有源层104、第一栅绝缘层105、栅极106、第二栅绝缘层108、层间介质层103、源极110、漏极111。具体地，有源层104可形成在缓冲层102上，第一栅绝缘层105覆盖缓冲层102及有源层104，栅极106形成在第一栅绝缘层105背离有源层104的一侧，第二栅绝缘层108覆盖栅极106和第一栅绝缘层105，层间介质层103覆盖第二栅绝缘层108，源极110和漏极111形成在层间介质层103背离衬底基板的一侧并分别位于栅极106的相对两侧，该源极110和漏极111可分别通过过孔(例如：金属过孔)与有源层104的相对两侧接触。应当理解的是，此薄膜晶体管也可为底栅型。
如图3所示，电容结构可包括第一极板130和第二极板131，此第一极板130与栅极106同层设置，第二极板131位于第二栅绝缘层108与层间介质层103之间，并与第一极板130相对设置。
举例而言，栅极106和第一极板130、第二极板131的材料可以包括金属材料或者合金材料，例如包括钼、铝及钛等。源极110和漏极111可以包括金属材料或者合金材料，例如由钼、铝及钛等形成的金属单层或多层结构，例如，该多层结构为多金属层叠层，例如钛、铝、钛三层金属叠层(Al/Ti/Al)等。
需要说明的是，如图3至图6、图9A、图9B、及图11所示，前述提到的第一栅绝缘层105、第二栅绝缘层108也位于过渡区10c、隔离区10d、内圈走线区10e、外围走线区10f、外围封装区10g。
如图3所示，显示器件位于显示区，该显示器件可包括依次形成在层间介质层103上的第一电极112和像素界定部113，应当理解的是，该显示器件还可包括发光部114a和第二电极115。
详细说明，在显示区10a的薄膜晶体管为顶栅型时，在制作显示器件之前还可制作平坦化层，此平坦化层可为单层结构，也可为多层结构；此平坦化层通常采用有机材料制作而成，例如：光刻胶、丙烯酸基聚合物、硅基聚合物等材料；如图3所示，此平坦化层可包括位于显示区10a的平坦化部116，平坦化部116形成在层间介质层103与第一电极112之间。其中，第一电极112可通过金属过孔与漏极111电性连接，该第一电极112可为阳极，此阳极可为ITO(氧化铟锡)、氧化铟锌(IZO)、氧化锌(ZnO)等材料制作而成；像素界定部113可覆盖平坦化部116，此像素界定部113可为有机材料制作而成，例如：光刻胶等有机材料，且像素界定部113中位于显示区10a的部分可具有露出第一电极112的像素开口；发光部114a位于像素开口内并形成在第一电极112上，该发光部114a可包括小分子有机材料或聚合物分子有机材料，可以为荧光发光材料或磷光发光材料，可以发红光、绿光、蓝光，或可以发白光等；并且，根据实际不同需要，在不同的示例中，发光部114a还可以进一步包括电子注入层、 电子传输层、空穴注入层、空穴传输层等功能层；第二电极115覆盖发光部114a，且该第二电极115的极性与第一电极112的极性相反；此第二电极115可为阴极，此阴极可为锂(Li)、铝(Al)、镁(Mg)、银(Ag)等金属材料制作而成。
需要说明的是，如图3所示，第一电极112、发光部114a和第二电极115可构成一个发光子像素1d。其中，此显示器件中位于显示区10a的部分可包括多个阵列排布的发光子像素1d。此外，还需说明的是，各发光子像素1d的第一电极112相互独立，各发光子像素1d的第二电极115整面连接；即第二电极115为设置在显示基板10上的整面结构，为用于多个显示器件的公共电极。
在一些实施例中，如图3所示，像素界定部113背离层间介质层103的一侧还可设置支撑部132，该支撑部132可起到支撑保护膜层(图中未示出)的作用，以避免保护膜层与第一电极112或其他走线接触而导致第一电极112或其他走线容易损坏的情况。需要说明的是，此保护膜层主要出现在半成品转移的过程中，以避免转移过程中半成品出现损坏的情况，具体地：在将制作完支撑部132的基板转移到蒸镀产线的过程中，可覆盖一层保护膜层，当需要进行发光材料的蒸镀时，而将保护膜层移除。
举例而言，支撑部132的材料可与像素界定部113的材料相同，且支撑部132与像素界定部113可采用同一次构图工艺形成，但不限于此，支撑部132的材料也可与像素界定部113的材料不同，且支撑部132与像素界定部113也可采用不同构图工艺形成。
其中，在显示基板10具有外围走线区10f时，该像素界定部113还位于外围走线区10f。
在一些实施例中，如图4所示，第一电极112还可通过转接电极133与漏极111电性连接。当第一电极112通过转接电极133与漏极111电性连接时，该平坦化部116可为双层结构，具体可包括依次形成的第一平坦化膜(PLN1)层116a及第二平坦化膜(PLN2)层116b，此外，在第一平坦化膜层116a与层间介质层103之间还可形 成钝化膜(PVX)层134，该钝化膜层134可由氧化硅、氮化硅或者氮氧化硅等材料形成；该钝化膜层134覆盖源极110、漏极111，需要说明的是，在平坦化部116为单层时，平坦化部116与层间介质层103之间也可形成钝化膜层134；而转接电极133形成在第一平坦化膜层116a与第二平坦化膜层116b之间，并依次通过第一平坦化膜层116a及钝化膜层134上的过孔(例如金属过孔)与漏极111电性连接；而第一电极112可通过第二平坦化膜层116b上的过孔(例如金属过孔)与转接电极133电性连接，如图4所示。但不限于此，转接电极133也可形成在第一平坦化膜层116a与钝化膜层134之间。
如图5所示，第一封装坝1a形成在层间介质层103背离衬底基板的一侧并位于过渡区10c，第一封装坝1a环绕开孔区10b设置，本公开的实施例中，该第一封装坝1a可包括第一阻隔部117，在通过封装层118对此显示基板10进行封装时，该第一阻隔部117能够对封装层118中的有机封装薄膜层材料的流动形成限制，避免封装层118中的有机封装薄膜层材料流动至开孔区10b引起封装失效的问题，也就是说，该第一封装坝1a的第一阻隔部117可与封装层118配合，以有效阻隔水、氧通过开孔区10b进入到显示区10a，从而可避免显示区10a的发光部114a失效而导致显示效果差的情况，延长了产品的使用寿命。
详细说明，如图3至5所示，显示基板10的封装层118可包括依次层叠设置的第一无机封装薄膜层118a、有机封装薄膜层118b和第二无机封装薄膜层118c。此第一无机封装薄膜层118a封装显示器件和第一封装坝1a和第二封装坝1b，有机封装薄膜层118b封装显示器件，并在第一封装坝1a靠近显示区10a的一侧阻断；第二无机封装薄膜层118c封装显示器件和第一封装坝1a和第二封装坝1b。第一无机封装薄膜层118a、第二无机封装薄膜层118c用于防止水、氧从显示功能的显示侧及开孔区10b进入到显示区10a的发光部114a中；该第一无机封装薄膜层118a和第二无机封装薄膜层118c可采用氮化硅、氧化硅等无机材料制作而成。有机封装薄膜层118b用于实现平坦化作用，以便于第二无机封装薄膜层118c层的制作，此有机封装 薄膜层118b可采用丙烯酸基聚合物、硅基聚合物等材料制作而成。
其中，此第一无机封装薄膜层118a和第二无机封装薄膜层118c可采用化学气相沉积工艺制作而成，但不限于此，也可采用物理气相沉积工艺等；而有机封装薄膜层118b采用喷墨打印工艺制作，但不限于此，也可采用喷涂工艺等。在制作有机封装薄膜层118b的过程中，由于有机封装材料具有一定的流动性，因此，通过设置第一阻隔部117可对有机封装材料的流动形成限制，避免有机封装材料流动至开孔区10b引起封装失效的问题。
在本公开的实施例中，第一阻隔部117与像素界定部113同层设置，即：通过一次构图工艺即可同时形成第一阻隔部117和像素界定部113，可减少加工步骤及掩膜板的使用，从而可降低成本。此外，应当理解的是，该第一阻隔部117与像素界定部113应相互断开。
由于第一阻隔部117与像素界定部113同层设置，因此可知，若将第一阻隔部117直接制作在过渡区10c的层间介质层103上，则在制作第一阻隔部117之前，位于过渡区10c的层间介质层103的表面需经其他各层图案化工艺(例如：源漏极图案化工艺、平坦化层图案化工艺、第一电极112的图案化工艺)的刻蚀液(例如：硝酸溶液等)进行多次清洗，这样使得位于过渡区10c的层间介质层103的表面粗糙度(指加工表面具有的较小间距和微小峰谷的不平度)变得较小，即：变得较光滑；若直接在过渡区10c的层间介质层103表面形成第一阻隔部117，则使得该第一阻隔部117在层间介质层103上的粘附力降低，第一阻隔部117与过渡区10c的层间介质层103不能稳定结合；在图案化形成第一阻隔部117的过程中，第一阻隔部117容易在显影液清洗的过程中发生脱落，即：第一封装坝1a容易从过渡区10c的层间介质层103上脱落，增大了封装失效的风险。
为了解决这一问题，本公开的实施例中，如图5所示，第一封装坝1a还包括形成在层间介质层103上的第一保护部119，该第一保护部119背离层间介质层103的一侧设置有前述第一阻隔部117。也就是说，本公开的实施例在制作第一封装坝1a之前，可先在位于过渡 区10c的层间介质层103的表面形成第一保护部119，然后再在第一保护部119背离层间介质层103的一侧形成第一阻隔部117；通过设置第一保护部119，可在制作第一阻隔部117之前对位于过渡区10c的层间介质层103的表面进行保护，以减少位于过渡区10c的层间介质层103被刻蚀液清洗的次数，从而可提高位于过渡区10c的层间介质层103的粘附力，保证第一封装坝1a与层间介质层103的结合稳定，有效的降低工艺过程中第一封装坝1a脱落的风险，继而可降低封装失效风险，提高封装良率，保证显示效果及产品使用寿命。
其中，在过渡区10c中，由于层间介质层中覆盖有第一保护层119的表面相比于未覆盖第一保护层119的表面，被刻蚀液清洗的次数有减少，因此，层间介质层103上覆盖有第一保护层119的表面粗糙度大于未覆盖有第一保护层119的表面粗糙度。举例而言，层间介质层103上覆盖有第一保护部119的表面粗糙度与未覆盖有第一保护层119的表面粗糙度之间的比值可为100:5～100:95、100:10～100:90、100:20～100:80、100:30～100:70、100:40～100:60等等。应当理解的是，表面粗糙度的评定常用“轮廓的平均算术偏差Ra、不平度平均高度Rz和最大高度Ry”这三个高度特征参数。
在本公开的一些实施例中，该第一保护部119可与第一电极112同层设置，即：通过一次构图工艺即可对覆盖在层间介质层103上并位于显示区10a和过渡区10c的第一导电薄膜进行图案化处理，以同时形成第一保护部119与第一电极112。由于第一导电薄膜覆盖位于过渡区10c的层间介质层103，因此，在图案化形成第一电极112过程中，位于过渡区10c的层间介质层103不会被此过程中的刻蚀液清洗，减少了过渡区10c的层间介质层103被刻蚀液清洗的次数，从而可提高位于过渡区10c的层间介质层103的粘附力。其中，由于在形成第一电极112的过程中，同时还形成有第一保护部119，因此，该第一保护部119还可继续对位于过渡区10c的层间介质层103进行保护，避免后续图案化工艺的刻蚀液清洗位于过渡区10c的层间介质层103。
此外，由于第一保护部119与第一电极112通过同一构图工艺形 成，因此，还可减少加工步骤及掩膜板的使用，从而可降低成本。此外，应当理解的是，该第一保护部119与第一电极112应相互断开，以避免第一保护部119在显示时通电的情况。
在本公开的一些实施例中，第一保护部119可与平坦化部116同层设置，即：通过一次构图工艺即可对覆盖在层间介质层103上并位于显示区10a和过渡区10c的平坦化薄膜进行图案化处理，以同时形成第一保护部119与平坦化部116。由于平坦化薄膜覆盖位于过渡区10c的层间介质层103，因此，在图案化形成平坦化部116过程中，位于过渡区10c的层间介质层103不会被此过程中的刻蚀液清洗，减少了过渡区10c的层间介质层103被刻蚀液清洗的次数，从而可提高位于过渡区10c的层间介质层103的粘附力。其中，由于在形成平坦化部116的过程中，同时还形成有第一保护部119，因此，该第一保护部119还可继续对位于过渡区10c的层间介质层103进行保护，避免后续图案化工艺的刻蚀液清洗位于过渡区10c的层间介质层103。
此外，由于第一保护部119与平坦化部116通过同一构图工艺形成，因此，还可减少加工步骤及掩膜板的使用，从而可降低成本。此外，应当理解的是，该第一保护部119与平坦化部116应相互断开，以避免水氧通过第一保护部119传递到显示区10a的平坦化部116中，从而导致显示区10a的部件失效的情况。
其中，由于第一阻隔部117与像素界定部113同层设置，因此，第一阻隔部117与像素界定部113的材料相同，也为有机材料；本实施例中，将第一保护部119与平坦化部116同层设置，使得第一保护部119的材料与平坦化部116的材料相同，也为有机材料，此第一保护部119的材料可与第一阻隔部117的材料相同，这样设计可提高第一保护部119与第一阻隔部117之间的结合力，保证第一封装坝1a的结构稳定性，避免第一阻隔部117从第一保护部119上脱落的情况，以进一步降低封装失效风险，提高封装良率，保证显示效果及产品使用寿命。
在本公的一实施例中，如图5所示，显示基板10还包括第二封 装坝1b，此第二封装坝1b形成在层间介质层103背离衬底基板的一侧并位于过渡区10c的第二封装坝1b，且第二封装坝1b位于第一封装坝1a远离显示区10a的一侧并环绕开孔区10b，其中，第二封装坝1b的厚度大于第一封装坝1a的厚度；以进一步对封装层118的有机封装薄膜层材料流动形成限制，避免封装层118的有机封装薄膜层材料流动至开孔区10b引起封装失效的问题。
具体地，如图5所示，第二封装坝1b可包括第二保护部120和形成在第二保护部120背离层间介质层103一侧的第二阻隔部121，且第二阻隔部121与第一阻隔部117同层设置，即：通过一次构图工艺即可同时形成第二阻隔部121、第一阻隔部117和像素界定部113，可减少加工步骤及掩膜板的使用，从而可降低成本。
此外，应当理解的是，该第一阻隔部117与第二阻隔部121应相互断开，这样设计可增大阻隔和封装路径，因此，可进一步提高封装效果。
由于第二阻隔部121与第一阻隔部117、像素界定部113同层设置，这样在制作第二阻隔部121之前，位于过渡区10c的层间介质层103的表面需经其他各层图案化工艺的刻蚀液进行多次清洗，从而使得第一阻隔部117在层间介质层103上的粘附力降低，若将第二阻隔部121直接制作在过渡区10c的层间介质层103上，第二阻隔部121与过渡区10c的层间介质层103不能稳定结合，容易从过渡区10c的层间介质层103上脱落。因此，本实施例通过设置第二保护部120，可在制作第二阻隔部121之前对位于过渡区10c的层间介质层103的表面进行保护，以减少位于过渡区10c的层间介质层103被刻蚀液清洗的次数，从而可提高位于过渡区10c的层间介质层103的粘附力，保证第一封装坝1a与层间介质层103的结合稳定。
其中，在过渡区10c中，由于层间介质层中覆盖有第二保护层120的表面相比于未覆盖第二保护层120的表面，被刻蚀液清洗的次数有减少，因此，层间介质层103上覆盖有第二保护层120的表面粗糙度大于未覆盖有第二保护层120的表面粗糙度。举例而言，层间介 质层103上覆盖有第二保护层120的表面粗糙度与未覆盖有第二保护层120的表面粗糙度之间的比值可为100:5～100:95、100:10～100:90、100:20～100:80、100:30～100:70、100:40～100:60等等。
由于第一阻隔部117和第二阻隔部121为同层设置，因此，制作出来的第一阻隔部117和第二阻隔部121通常一样厚，因此，为了使得第二封装坝1b的厚度大于第一封装坝1a的厚度，本实施例采用的方案为：将第二保护部120的厚度设计为大于第一保护部119的厚度。但不限于此，也可使第一保护部119和第二保护部120的厚度相等，然后通过使第二阻隔部121的厚度大于第一阻隔部117的厚度，来使第二封装坝1b的厚度大于第一封装坝1a的厚度，视具体情况而定。
在本公开的一可选实施例中，该第二保护部120可与第一保护部119同层设置，即：通过一次构图工艺即可同时形成第一保护部119和第二保护部120，这样设计可减少加工步骤及掩膜板的使用，从而可降低成本。
本实施例中，由于第二保护部120可与第一保护部119同层设置，因此，在第一保护部119与第一电极112同层设置时，该第二保护部120也与第一电极112同层设置，即：通过一次构图工艺即可对覆盖在层间介质层103上并位于显示区10a和过渡区10c的第一导电薄膜进行图案化处理，以同时形成第一保护部119、第二保护部120与第一电极112；在第一保护部119与平坦化部116同层设置，该第二保护部120也与平坦化部116同层设置，即：通过一次构图工艺即可对覆盖在层间介质层103上并位于显示区10a和过渡区10c的平坦化薄膜进行图案化处理，以同时形成第一保护部119、第二保护部120与平坦化部116。
其中，在第一保护部119、第二保护部120与平坦化部116同层设置时，为了使得第二保护部120的厚度大于第一保护部119的厚度，可利用灰阶掩膜对平坦化薄膜进行图案化处理，以形成厚度不同的第一保护部119和第二保护部120。举例而言，此平坦化薄膜可以为光刻胶薄膜，此光刻胶薄膜可为正性光刻胶、也可为负性光刻胶；而灰 阶掩膜中对应形成第一保护部119的区域与对应形成第二保护部120的区域透光率不同，以使得曝光、显影后得到第一保护部119的厚度与第二保护部120的厚度不同。
需要说明的是，在光刻胶薄膜为正性光刻胶时，为了使得第二保护部120的厚度大于第一保护部119的厚度，灰阶掩膜中对应形成第一保护部119的区域的透光率大于对应形成第二保护部120的区域的透光率；在光刻胶薄膜为负性光刻胶时，为了使得第二保护部120的厚度大于第一保护部119的厚度，灰阶掩膜中对应形成第一保护部119的区域的透光率小于对应形成第二保护部120的区域的透光率。
在本公开的另一可选实施例中，第二保护部120与第一保护部119不同层设置，即：第一保护部119和第二保护部120各通过一次构图工艺形成。举例而言，在第一保护部119与第一电极112同层设置时，该第二保护部120可与平坦化部116同层设置，也就是说，在第一保护部119与第一电极112通过一次构图工艺形成时，第二保护部120与平坦化部116通过一次构图工艺，这样设计在提高第一封装坝1a和第二封装坝1b与位于过渡区10c的层间介质层103之间的结合稳定性的同时，不需要增加额外的构图工艺，从而可减少加工步骤及掩膜板的使用，以降低成本。
其中，由于第一电极112的厚度通常比平坦化部116的厚度小，因此，与第一电极112同层设置的第一保护部119的厚度可小于与平坦化部116同层设置的第二保护部120的厚度，这样设计不需要额外调控加工参数，即可使第一保护部119的厚度小于第二保护部120的厚度。
此外，本实施例中由于第一保护部119的材料与第二保护部120的材料不同，因此，第一封装坝1a与位于过渡区10c的层间介质层103的结合力与第二封装坝1b与位于过渡区10c的层间介质层103的结合力不同，这样设计可防止第一封装坝1a和第二封装坝1b同时从层间介质层103上脱落的情况，以提高封装效果。
需要说明的是，第一保护部119和第二保护部120的形成方式不 限于上述两种情况，还可在第一保护部119与平坦化部116同层设置时，该第二保护部120可与第一电极112同层设置，这样设计在提高第一封装坝1a和第二封装坝1b与位于过渡区10c的层间介质层103之间的结合稳定性的同时，不需要增加额外的构图工艺，从而可减少加工步骤及掩膜板的使用，以降低成本。应当理解的是，为了使得第二封装坝1b的厚度大于第一封装坝1a的厚度，本实施例可通过灰阶工艺调整第一阻隔部117的厚度小于第二阻隔部121的厚度。
举例而言，采用灰阶工艺对第一绝缘薄膜进行图案化处理，以形成像素界定部113、第一阻隔部117和第二阻隔部121，此第一绝缘薄膜可以为光刻胶薄膜，此光刻胶薄膜可为正性光刻胶、也可为负性光刻胶；而灰阶掩膜中对应形成第一阻隔部117的区域与对应形成第二阻隔部121的区域透光率不同，以使得曝光、显影后得到第一阻隔部117的厚度与第二阻隔部121的厚度不同。在光刻胶薄膜为正性光刻胶时，为了使得第二阻隔部121的厚度大于第一阻隔部117的厚度，灰阶掩膜中对应形成第一阻隔部117的区域的透光率大于对应形成第二阻隔部121的区域的透光率；在光刻胶薄膜为负性光刻胶时，为了使得第二阻隔部121的厚度大于第一阻隔部117的厚度，灰阶掩膜中对应形成第一阻隔部117的区域的透光率小于对应形成第二阻隔部121的区域的透光率。
还需要说明的是，第二保护部120与第一电极112同层设置的有益效果、第二保护部120与平坦化部116同层设置的有益效果可分别参考前述第一保护部119与第一电极112同层设置的有益效果、第二保护部120与平坦化部116同层设置的有益效果，在此不再重复赘述。
在一些实施例中，第二保护部120与第一保护部119可相互断开，这样设计可增大阻隔和封装路径，因此可进一步提高封装效果。
在一些实施例中，在第一保护部119和第二保护部120与平坦化部116同层设置时，若平坦化部116为包括第一平坦化膜层116a和第二平坦化膜层116b的两层结构，那么第一保护部119、第二保护部120也可为两层结构，该第一保护部119和第二保护部120均包括与 第一平坦化膜层116a同层设置的一膜层和与第二平坦化膜层116b同层设置的膜层。但不限于此，也可第二保护部120为两层结构，第一保护部119为单层结构(即：仅包括与第二平坦化膜层116b同层设置的膜层)；还可第一保护部119和第二保护部120均为，仅包括与第二平坦化膜层116b同层设置的膜层的单层结构。
其中，如图5所示，第一封装坝1a和第二封装坝1b中的至少一者还包括隔垫部(Photo Spacer，简称：PS)，此隔垫部可形成在第一阻隔部117或第二阻隔部121背离层间介质层103的一侧，其可以增加第一封装坝1a和第二封装坝1b的厚度，该隔垫部可阻挡封装层118中有机封装薄膜材料流向开孔区10b，进一步提高了对封装层118中有机封装薄膜材料流动的限制，进一步提高了显示基板10封装的可靠性。
举例而言，前述隔垫部可与显示区10a的支撑部132同层设置。其中，形成在第一阻隔部117上的隔垫部可定义为第一隔垫部122，形成在第二阻隔部121上的隔垫部可定义为第二隔垫部123，该第一隔垫部122与第一阻隔部117的材料可相同，且第一隔垫部122与第一阻隔部117可采用同一次构图工艺(例如：灰阶掩膜工艺)形成，以提高第一封装坝1a中各层的结构稳定性；但不限于此，第一隔垫部122与第一阻隔部117的材料也可不相同，且第一隔垫部122与第一阻隔部117可采用不同构图工艺形成；同理，该第二隔垫部123与第二阻隔部121的材料可相同，且第二隔垫部123与第二阻隔部121可采用同一次构图工艺(例如：灰阶掩膜工艺)形成，以提高第一封装坝1a中各层的结构稳定性；但不限于此，第二隔垫部123与第二阻隔部121的材料也可不相同，且第二隔垫部123与第二阻隔部121可采用不同构图工艺形成。
需要说明的是，本公开的实施例中提到的厚度指的是在如图3至图6所示及图9A、图9B与图10所示的Z方向上的尺寸。
其中，图16A示出了第一封装坝和第二封装坝在扫描电子显微镜下的示意图；图16B为示出了图16A中P处观察口在扫描电子显微 镜下的示意图；图16C为示出了图16A中Q处观察口在扫描电子显微镜下的示意图。
如图16B所示，第一封装坝1a的外轮廓相对层间介质层103的表面呈倾斜设置，此外轮廓与层间介质层103之间的倾斜角度α1斜可为20°至35°，例如：20°、25°、30°、35°等等；举例而言，此外轮廓可为弧形。且第一封装坝1a的厚度可为0.5μm至2μm，例如：0.5μm、1μm、1.5μm、2μm等等。
如图16C所示，第二封装坝1b的外轮廓相对层间介质层103的表面呈倾斜设置，此外轮廓与层间介质层103之间的倾斜角度α2可为20°至35°，例如：20°、25°、30°、35°等等；举例而言，此外轮廓可为弧形。且第二封装坝1b的厚度可为0.5μm至2μm，例如：0.5μm、1μm、1.5μm、2μm等等。
由于第二封装坝1b的厚度大于第一封装坝1a的厚度，因此可知，第二封装坝1b与层间介质层103之间的倾斜角度α2大于第一封装坝1a与层间介质层103之间的倾斜角度α1。
在一些实施例中，如图5所示，第一封装坝1a与第二封装坝1b之间的间距h1较小，这样在保证第一封装坝1a和第二封装坝1b能够阻挡封装层118中有机封装薄膜材料流向开孔区10b的同时，还可减小显示基板中过渡区10c的占比，从而可提高其他区域的占比，例如：显示区10a等；而第一封装坝1a与显示区10a之间的间距h2较大，为了方便设计内圈走线区10e、隔离区10d等；且第二封装坝1b与开孔区10b之间的间距h3较大，这样在激光切割开孔区的过程中可避免温度过高而导致第二封装坝1b受损或脱落的情况，从而提高封装稳定性。基于此，在一些实施例中，如图5所示，第一封装坝1a与第二封装坝1b之间的间距h1可小于第一封装坝1a与显示区10a的间距h2；和/或小于第二封装坝1b与开孔区10b之间的间距h3。。
在一些实施例中，如图6、图7和图17所示，过渡区10c还可包括第三封装坝1c、阻隔墙135及有机绝缘封装部139；其中：
第三封装坝1c环绕开孔区10a设置并位于第二封装坝1b靠近开 孔区10a的一侧；此第三封装坝1c和第二封装坝1b具有相同的结构，并且包括相同的材料。由此第三封装坝1c和第二封装坝1b可采用相同的材料层并通过相同的构图工艺形成。
阻隔墙135位于第二封装坝1b与第三封装坝1c之间，此阻隔墙135环绕第三封装坝1c设置。举例而言，此阻隔墙135可包括与栅极106和第一极板130同层设置的第一膜层136、与第二极板131同层设置的第二膜层137、与源极110和漏极111同层设置的第三膜层138、位于第一膜层136与第二膜层137之间的第二栅绝缘层108、以及位于第三膜层138与第二膜层137之间的层间介质层103。也就是说，第一膜层136、栅极106、第一极板130具有相同的结构，并且包括相同的材料；第二膜层137、第二极板131具有相同的结构，并且包括相同的材料；第三膜层138与源极110和漏极111具有相同的结构，并且包括相同的材料。由此第一膜层136、栅极106、第一极板130可采用相同的材料层并通过相同的构图工艺形成；第二膜层137、第二极板131可采用相同的材料层并通过相同的构图工艺形成；第三膜层138与源极110和漏极111可采用相同的材料层并通过相同的构图工艺形成。
有机绝缘封装部139在第三封装坝1c与第二封装坝1b之间且覆盖阻隔墙135，有机绝缘封装部139与封装层118的有机封装薄膜层118b的材料相同，例如，可以通过相同的喷墨打印工艺形成。
本实施例中，通过设置第三封装坝1c、阻隔墙135及有机绝缘封装部139，提供了进一步的阻隔效果，使得过渡区10c可以充分隔离开开孔区10b和显示区10a，防止水氧等杂质从开孔区10b进入显示区10a，并防止形成开孔区10b时可能形成的裂纹扩展至显示区10a。
其中，在过渡区10c包括第三封装坝1c、阻隔墙135及有机绝缘封装部139时，前述提到的第一无机封装薄膜层118a还覆盖第三封装坝1c、阻隔墙135；有机封装薄膜层118b与有机绝缘封装部139通过喷墨打印工艺形成；第二无机封装薄膜层118c还覆盖第三封装坝1c、阻隔墙135及有机绝缘封装部139。
需要说明的是，本公开的实施例中，如图1所示，在开孔区10b为圆形时，第一封装坝1a、第二封装坝1b、第三封装坝1c、阻隔墙135在衬底基板上的正投影也可为圆环；在开孔区10b为矩形时，第一封装坝1a、第二封装坝1b、第三封装坝1c、阻隔墙135在衬底基板上的正投影也可为矩形环；但不限于此开孔区10b还可为其他规则或不规则形状，第一封装坝1a、第二封装坝1b、第三封装坝1c、阻隔墙135可与之相适配。
在一些实施例中，如图5、图6、图8所示，显示基板10还包括位于隔离区10d的隔离柱124，此隔离柱124形成在层间介质层103背离衬底基板的一侧并环绕第一封装坝1a设置，且隔离柱124的侧壁设置有凹槽124a；以在蒸镀发光材料或阴极材料时，使得发光材料层114和阴极(即：第二电极115)在此凹槽124a处间断，这样可阻断开孔区10b的水氧向显示区10a侵蚀的路径，从而进一步防止显示区10a的发光部114a被侵蚀的情况，提高了显示基板10的显示效果及延长了产品使用寿命。
需要说明的是，隔离柱124的数量不限于一个、也可为多个。
在一些实施例中，该隔离柱124可与薄膜晶体管的源极110、漏极111同层设置，即：隔离柱124与源极110、漏极111通过同一构图工艺形成，这样设计还可减少加工步骤及掩膜板的使用，从而可降低成本。此外，应当理解的是，该隔离柱124可与薄膜晶体管的源极110、漏极111应相互断开，以避免隔离柱124在显示时通电的情况。
由于前述提到隔离柱124可与显示区中薄膜晶体管的源极110和漏极111同层设置，因此，该隔离柱124的结构、材料可与源极110和漏极111的结构和材料相同，例如，在源极110和漏极111为三层金属结构时，该隔离柱124也可为三层金属结构。具体地，如图8所示，隔离柱124可包括依次层叠在层间介质层103上的第一金属层124b、第二金属层124c及第三金属层124d，第二金属层124c在层间介质层103上的正投影的外边界位于第一金属层124b、第三金属层124d在层间介质层103上的正投影的外边界内侧，以在隔离柱124 的侧壁形成凹槽124a，使得隔离柱124的纵截面成“工字形”结构。
其中，第一金属层124b与第三金属层124d可为钛层，即：第一金属层124b和第三金属层124d可采用钛(Ti)材料制作而成，第二金属层124c可为铝层，即：第二金属层124c可采用铝(Al)材料制作而成，这样可保证第二金属层124c在进行侧蚀时，第一金属层124b与第三金属层124d不会受到刻蚀的影响。但不限于此，第一金属层124b、第二金属层124c、第三金属层124d也可采用其它材料制作而成，例如：钼、铝等金属材料或者合金材料，只要能实现上述技术效果即可，本公开对此不做限制。
在一些实施例中，如图5和图6所示，驱动电路层具有位于隔离区10d的第一开槽125和第二开槽126；第一开槽125位于隔离柱124靠近第一封装坝1a的一侧，第一开槽125环绕第一封装坝1a设置；第二开槽126位于隔离柱124靠近显示区10a的一侧，第二开槽126环绕第一开槽125设置，这样设计可增大发光材料在隔离柱124的侧面断开的概率。
其中，第一开槽125和第二开槽126可贯穿部分驱动电路层，此第一开槽125和第二开槽126形成在驱动电路层远离衬底基板的一侧；此外，第一开槽125和第二开槽126也可贯穿整个驱动电路层，即：开槽可延伸至缓冲层102。
如图所示，第一开槽125和第二开槽126可贯穿整个驱动电路层，以进一步增大发光材料或阴极材料在隔离柱124的侧面断开的概率；此外，在显示基板10具有柔性并进行弯曲时，这样设计还可缓解驱动电路层位于显示区10a的部分所受到的应力，保证驱动电路层中各元件的连接可靠性。
需要说明的是，本公开的实施例中，在开孔区10b为圆形时，第一开槽125、第二开槽126、隔离柱124在衬底基板上的正投影也可为圆环；在开孔区10b为矩形时，第一开槽125、第二开槽126、隔离柱124在衬底基板上的正投影也可为矩形环；但不限于此开孔区10b还可为其他规则或不规则形状，第一开槽125、第二开槽126、 隔离柱124可与之相适配。
在一些实施例中，如图9A所示，外围封装区10g也可设置第一外围封装坝127和第二外围封装坝128，该第二外围封装坝128设置在第一外围封装坝127远离显示区10a的一侧，且第二外围封装坝128的厚度大于第一外围封装坝127的厚度；其中，该第一外围封装坝127可包括依次形成在层间介质层103上的第一外围阻隔部127a及第一外围隔垫部127b；第二外围封装坝128可包括依次形成在位于层间介质层103上的第三保护部128a、第二外围阻隔部128b及第二外围隔垫部128c。
在一些实施例中，第三保护部128a可与显示区10a的平坦化部116同层设置，第一外围阻隔部127a、第二外围阻隔部128b可与显示区10a的像素界定部113同层设置；第一外围隔垫部127b与第二外围隔垫部128c可与显示区10a的支撑部同层设置。
需要说明的是，第一外围封装坝127也可包括位于层间介质层103与第一外围阻隔部127a之间、并与平坦化部116同层设置的保护部，视具体情况而定。
在一些实施例中，第二外围封装坝128与第一外围封装坝127之间的厚度差大于第二封装坝1b与第一封装坝1a之间的厚度差。
在一些实施例中，如图9A所示，驱动电路层还包括位于外围走线区10f的外围走线107和第一外围转接线109a，外围走线107可源极110和漏极111同层设置，第一外围转接线109a可与第一电极112同层设置。其中，外围走线107的一端可延伸至外围封装区10g，且外围走线107可位于第一外围封装坝127和第二外围封装坝128的下方；第一外围转接线109a的一端可延伸至外围封装区10g，并位于第二外围封装坝128中第三保护部128a与第二外围阻隔部128b之间。
需要说明的是，在一些实施例中，在制作源漏极层之后及制作平坦化层之前，还可制作一层钝化膜层134，此钝化膜层134经图案化处理后，不仅可以包括位于显示区10a的部分，如图4所示；也可包括位于外围走线区10f和外围封装区10g的部分，如图9A所示。但 应当理解的是，在一些实施例中，在制作源漏极层之后，也可直接制作平坦化层，不制作钝化膜层134；或再对钝化膜层134图案化处理之后，该钝化膜层134可包括位于显示区10a的部分，而在外围走线区10f和外围封装区10g不具有钝化膜层134的部分结构，具体视需求而定。
其中，如图9A所示，第一外围转接线109a可通过过孔与位于外围走线区10f的外围走线107电连接，具体第一外围转接线109a可在第一外围封装坝127的下方与外围走线107接触，以实现电连接，但不限于此。且该第一外围转接线109a还可与位于外围走线区10f的第二电极115电连接。此外围走线107可为VSS电源线等，但不限于此。
在一些实施例中，如图9B所示，驱动电路层还包括位于外围走线区10f的外围走线107、第一外围转接线109a和第二外围转接线109b，外围走线107可源极110和漏极111同层设置，第一外围转接线109a可与第一电极112同层设置；第二外围转接线109b可与显示区10a的转接电极133同层设置。其中，外围走线107的一端可延伸至外围封装区10g，且外围走线107可位于第一外围封装坝127和第二外围封装坝128的下方，第一外围转接线109a的一端可延伸至外围封装区10g，并位于第二外围封装坝128中第三保护部128a与第二外围阻隔部128b之间；第二外围转接线109b的一端可延伸至外围封装区10g，且第二外围转接线109b可位于第一外围封装坝127和第二外围封装坝128的下方。
此外，如图9B所示，由于本公开实施例中外围走线区10f与外围封装区109g设置有与转接电极133同层设置的第二外围转接线109b，因此，本公开实施例的平坦化层可设置有两层，即：第一平坦化层和第二平坦化层，此第一平坦化层在制作第二外围转接线109b和转接电极133之前制成，其中，可对第一平坦化层进行图案化处理，可形成位于显示区10a和外围走线区10f的第一平坦化膜层116a(如图4所示)和位于外围封装区10g的第二图案块141(如图9A所示)，此第二图案块141位于第二外围封装坝128的下方，以垫高第二外围 封装坝128；此第二平坦化层在制作第二外围转接线109b和转接电极133之后制成，其中，可对第二平坦化层进行图案化处理，可形成位于显示区10a和外围走线区10f的第二平坦化膜层116b(如图4所示)和位于外围封装区10g的第一图案块140和第三保护部128a(如图9B所示)，此第一图案块140位于第一外围封装坝127的下方，以垫高第一外围封装坝127。
需要说明的是，在一些实施例中，在制作源漏极层之后及制作平坦化层之前，还可制作一层钝化膜层134，此钝化膜层134经图案化处理后，不仅可以包括位于显示区10a的部分，如图4所示；也可包括位于外围封装区10g的部分，如图9B所示。
应当理解的是，在一些实施例中，在制作源漏极层之后，也可直接制作平坦化层，不制作钝化膜层134；或再对钝化膜层134图案化处理之后，该钝化膜层134可包括位于显示区10a的部分，而在外围封装区10g不具有钝化膜层134的部分结构，具体视需求而定。在一些实施例中，平坦化层也可为单层结构；或再对双层平坦化层图案化处理之后，该平坦化层可包括位于显示区10a的第一平坦化膜层116a、第二平坦化膜层116b，而在外围封装区10g和外围走线区10f可仅具有对第一平坦化层图案化处理后的结构，而不具有对第二平坦化层图案化处理的结构等等，视具体需求而定。
其中，如图9B所示，第二外围转接线109b可通过过孔与位于外围走线区10f的外围走线107电连接，具体第二外围转接线109b可在第一外围封装坝127的下方与外围走线107接触及在第二外围封装坝128远离第一外围封装坝127的一侧接触，以实现电连接，但不限于此。第一外围转接线109a可通过过孔与位于外围走线区10f的第二外围转接线109b电连接，具体第一外围转接线109a可在第一外围封装坝127的下方与第二外围转接线109b接触，以实现电连接，但不限于此。且该第一外围转接线109a还可与位于外围走线区10f的第二电极115电连接。此外围走线107可为VSS电源线等，但不限于此。
在一些实施例中，该外围走线区10f不仅可设置外围走线107和第一外围转接线109a、第二外围转接线109b，也可设置其他走线(图中未示出)，应当理解的是，其他走线不仅可包括与源极110和漏极111同层设置、与第一电极112同层设置的走线，还可包括与第一极板130、第二极板131或转接电极133等同层设置的走线。
在一些实施例中，如图5和图6所示，驱动电路层还包括位于内圈走线区10e的内圈信号线，此内圈信号线可与显示区的信号走线电连接。举例而言，内圈信号线可设置有多条，多条中至少包括与薄膜晶体管的源极110/漏极111同层设置的第一内圈信号线129a、及与薄膜晶体管的栅极106/第一极板130同层设置的第二内圈信号线129b、及与第二极板131同层设置的第三内圈信号线129c。
应当理解的是，第一内圈信号线129a、第二内圈信号线129b及第三内圈信号线129c可设置有多条。
在一些实施例中，第一内圈信号线129a可包括数据信号线，但不限于此，也可包括其他信号线，只要该导电层的各信号线可以按要求排布即可；第二内圈信号线129b可包括栅极信号线，但不限于此，也可包括其他信号线，只要该导电层的各信号线可以按要求排布即可；第三内圈信号线129c可包括复位信号线、初始化线，但不限于此，也可包括其他信号线，只要该导电层的各信号线可以按要求排布即可。
在一些实施例中，第一内圈信号线129a可包括栅极信号线，但不限于此，也可包括其他信号线，例如：复位信号线、初始化线，只要该导电层的各信号线可以按要求排布即可；第二内圈信号线129b可为数据信号线，但不限于此，也可包括其他信号线，只要该导电层的各信号线可以按要求排布即可；第三内圈信号线129c可包括数据信号线，但不限于此，也可包括其他信号线，只要该导电层的各信号线可以按要求排布即可。
需要说明的是，本公开实施例的显示基板10中开孔区10b在开孔处理后，用于组装摄像头、传感器、HOME键、听筒或扬声器等器件。需要说明的是，对于本公开实施例的显示基板10，可以如图5 和图6所示，开孔区10b未进行开孔处理，在组装摄像头等器件前，再进行开口处理即可。此外，本公开实施例的显示基板10，也可以如图10所示，在开孔区10b已进行了开孔处理，在此情况下，该显示基板10可直接拿来进行后续组装。
此外，还需要说明的是，在对本公开的显示基板10的显示区10a进行开孔处理后，得到的开孔包括但不限于如下形式：通孔、凹槽、开口等。
本公开的一实施例中还提供了一种显示装置，可包括前述实施例中所描述的显示基板10，可对显示基板10的开孔区10b进行开孔处理，以形成开孔，如图10所示；如图11所示，显示装置还包括安装于开孔的摄像头、传感器、HOME键、听筒或扬声器等功能器件20。
根据本申请的实施例，该显示装置的具体类型不受特别的限制，本领域常用的显示装置类型均可，具体例如OLED(OrganicLight-Emitting Diode，有机发光二极管)显示屏、手机等移动装置、手表等可穿戴设备、VR装置等等，本领域技术人员可根据该显示设备的具体用途进行相应地选择，在此不再赘述。
需要说明的是，如图11所示，该显示装置除了显示基板10及摄像头、传感器、HOME键、听筒或扬声器等器件以外，还包括其他必要的部件和组成，以显示器为例，具体例如外壳、电源线，驱动芯片30等等，本领域技术人员可根据该显示装置的具体使用要求进行相应地补充，在此不再赘述。
本公开实施例提供了一种显示基板的制作方法，该显示基板的结构可参考前述实施例所描述的显示基板10的结构，在此不在描述；其中，如图12所示，该制作方法可包括：
步骤S100、提供一衬底基板；
步骤S101、在衬底基板上形成驱动电路层，驱动电路层包括位于显示区和过渡区的层间介质层；
步骤S102、在层间介质层背离衬底基板的一侧形成显示器件、第一封装坝和第二封装坝；显示器件位于显示区，并包括依次形成在 层间介质层上的第一电极和像素界定部；第一封装坝位于过渡区并环绕开孔区设置，且第一封装坝包括依次层叠在层间介质层上的第一保护部和第一阻隔部；第二封装坝位于过渡区并环绕开孔区设置，第二封装坝位于第一封装坝远离显示区的一侧，且第二封装坝的厚度大于第一封装坝的厚度，第二封装坝包括依次层叠在层间介质层上的第二保护部和第二阻隔部；其中，
利用同一次构图工艺形成相互断开的第一阻隔部、第二阻隔部与像素界定部；
且第一封装坝与第二封装坝之间的间距小于第一封装坝与显示区的间距。
应当理解的是，本公开实施例的提供的上述制作方法应该具备与本公开实施例提供的显示基板10具有相同的特点和优点，所以，本公开实施例的提供的上述制作方法的特点和优点可以参照上文描述的显示基板10的特点和优点，在此不再赘述。
在一些实施例中，利用同一次构图工艺形成相互断开的第一保护部与第一电极。
在一些实施例中，利用同一次构图工艺形成相互断开的第一保护部和平坦化部，平坦化部位于显示区并形成在层间介质层与第一电极之间。
在一些实施例中，利用同一次构图工艺形成相互断开的第二保护部与第一保护部。
在一些实施例中，利用同一次构图工艺形成相互断开的第二保护部和平坦化部，平坦化部位于显示区并形成在层间介质层与第一电极之间。
在一些实施例中，在层间介质层背离衬底基板的一侧形成位于隔离区的隔离柱，隔离柱环绕过渡区设置，隔离柱的侧壁设置有凹槽。
在一些实施例中，驱动电路层包括位于显示区的薄膜晶体管，薄膜晶体管包括源极和漏极；
其中，利用同一次构图工艺形成相互断开的源极、漏极和隔离柱。
在一些实施例中，显示基板还具有位于隔离区与显示区之间的内圈走线区，内圈走线区环绕隔离区设置；驱动电路层还包括位于内圈走线区的内圈信号线，内圈信号线与显示区的信号走线电连接。
在一些实施例中，在层间介质层背离衬底基板的一侧形成显示器件、第一封装坝和第二封装坝之后，还包括：
形成封装层，封装层包括依次层叠设置的第一无机封装薄膜层、有机封装薄膜层和第二无机封装薄膜层；
第一无机封装薄膜层和第二无机封装薄膜层封装第一封装坝、第二封装坝和显示器件；
有机封装薄膜层封装显示器件，并在第一封装坝靠近显示区的一侧阻断。
需要说明的是，显示基板10中各层的具体细节已在对应的实施例中进行了详细描述，关于本方法实施例中未描述的细节，可参照上述显示基板10实施例中的相关描述，在此不再赘述。
应当注意，尽管在附图中以特定顺序描述了本公开中方法的各个步骤，但是，这并非要求或者暗示必须按照该特定顺序来执行这些步骤，或是必须执行全部所示的步骤才能实现期望的结果。附加的或备选的，可以省略某些步骤，将多个步骤合并为一个步骤执行，以及/或者将一个步骤分解为多个步骤执行等。此外，上面的一些步骤可以并行执行或顺序执行等等，并不局限于上文描述的具体操作顺序。
下面，结合显示基板10中显示区10a的像素电路以及版图对上述显示基板10的显示区10a及其制备方法进行介绍。
图13为本公开至少一实施例提供的一种显示基板中显示区的像素电路的等效电路图，图14A-10E为本公开一些实施例提供的一种显示基板中显示区的像素电路的各层的版图设计。
图13为本公开至少一实施例提供的一种显示基板中的像素电路的等效电路图，图14A-10E为本公开一些实施例提供的一种显示基板 中的像素电路的各层的示意图。
在一些实施例中，如图13所示，驱动电路层中位于显示区的像素电路包括多个薄膜晶体管T1、T2、T3、T4、T5、T6和T7、连接到多个薄膜晶体管T1、T2、T3、T4、T5、T6和T7的多条信号线和存储电容Cst，多条信号线包括栅线GL(即扫描信号线)、发光控制线EM、初始化线RL、数据线DAT和第一电源线VDD。栅线GL可包括第一栅线GLn和第二栅线GLn-1，例如第一栅线GLn可用于传输栅极扫描信号，第二栅线GLn-1可用于传输复位信号。发光控制线EM可用于传输发光控制信号。由此，像素电路为7T1C的像素电路。
需要说明的是，本公开实施例包括但并不限于此，像素电路也可采用其他类型的电路结构，例如7T2C结构或者9T2C结构等，本公开实施例对此不作限制。
例如，可以通过内圈栅极信号线将显示区10a中位于开孔区10b左右两侧的每行发光子像素1d对应的像素电路的第一栅线GLn电连接以传输栅极扫描信号，从而实现栅极扫描信号的补偿效果。
例如，如图13所示，第一薄膜晶体管T1的第一栅极G1与第三薄膜晶体管T3的第三漏极D3和第四薄膜晶体管T4的第四漏极D4电连接。第一薄膜晶体管T1的第一源极S1与第二薄膜晶体管T2的第二漏极D2和第五薄膜晶体管T5的第五漏极D5电连接。第一薄膜晶体管T1的第一漏极D1与第三薄膜晶体管T3的第三源极S3和第六薄膜晶体管T6的第六源极S6电连接。
例如，如图13所示，第二薄膜晶体管T2的第二栅极G2被配置为与第一栅线GLn电连接以接收栅极扫描信号，第二薄膜晶体管T2的第二源极S2被配置为与数据线DAT电连接以接收数据信号，第二薄膜晶体管T2的第二漏极D2与第一薄膜晶体管T1的第一源极S1电连接。
例如，如图13所示，第三薄膜晶体管T3的第三栅极G3被配置为与第一栅线GLn电连接，第三薄膜晶体管T3的第三源极S3与第一薄膜晶体管T1的第一漏极D1电连接，第三薄膜晶体管T3的第三 漏极D3与第一薄膜晶体管T1的第一栅极G1电连接。
例如，如图13所示，第四薄膜晶体管T4的第四栅极G4被配置为与第二栅线GLn-1电连接以接收复位信号，第四薄膜晶体管T4的第四源极S4被配置为与初始化线RL电连接以接收初始化信号，第四薄膜晶体管T4的第四漏极D4与第一薄膜晶体管T1的第一栅极G1电连接。
例如，如图13所示，第五薄膜晶体管T5的第五栅极G5被配置为与发光控制线EM电连接以接收发光控制信号，第五薄膜晶体管T5的第五源极S5被配置为与第一电源线VDD电连接以接收第一电源信号，第五薄膜晶体管T5的第五漏极D5与第一薄膜晶体管T1的第一源极S1电连接。
例如，如图13所示，第六薄膜晶体管T6的第六栅极G6被配置为与发光控制线EM电连接以接收发光控制信号，第六薄膜晶体管T6的第六源极S6与第一薄膜晶体管T1的第一漏极D1电连接，第六薄膜晶体管T6的第六漏极D6与发光子像素1d的第一显示电极(例如：第一电极112)电连接。
例如，如图13所示，第七薄膜晶体管T7的第七栅极G7被配置为与第二栅线GLn-1电连接以接收复位信号，第七薄膜晶体管T7的第七源极S7与发光子像素1d的第一显示电极(例如第一电极112)电连接，第七薄膜晶体管T7的第七漏极D7被配置为与初始化线RL电连接以接收初始化信号。例如，第七薄膜晶体管T7的第七漏极D7可以通过连接到第四薄膜晶体管T4的第四源极S4以实现与初始化线RL电连接。
例如，如图13所示，存储电容Cst包括第一电容电极CE1(即：第一极板130)和第二电容电极CE2(即：第二极板131)。第二电容电极CE2与第一电源线VDD电连接，第一电容电极CE1与第一薄膜晶体管T1的第一栅极G1和第三薄膜晶体管T3的第三漏极D3电连接。
例如，如图13所示，发光子像素1d的第二显示电极(例如第二 电极115)与第二电源线VSS电连接。
需要说明的是，第一电源线VDD和第二电源线VSS之一为提供高电压的电源线，另一个为提供低电压的电源线。在如图13所示的实施例中，第一电源线VDD提供恒定的第一电压，第一电压为正电压；而第二电源线VSS提供恒定的第二电压，第二电压可以为负电压等。例如，在一些示例中，第二电压可以为接地电压。
需要说明的是，上述的复位信号和上述的初始化信号可为同一信号。
还需要说明的是，按照晶体管的特性，晶体管可以分为N型晶体管和P型晶体管，为了清楚起见，本公开的实施例以晶体管为P型晶体管(例如，P型TFT)为例详细阐述了本公开的技术方案，也就是说，在本公开的描述中，第一薄膜晶体管T1、第二薄膜晶体管T2、第三薄膜晶体管T3、第四薄膜晶体管T4、第五薄膜晶体管T5、第六薄膜晶体管T6和第七薄膜晶体管T7等均可以为P型晶体管。然而本公开的实施例的晶体管不限于P型晶体管，本领域技术人员还可以根据实际需要利用N型晶体管(例如，N型TFT)实现本公开的实施例中的一个或多个晶体管的功能。
需要说明的是，本公开的实施例中采用的晶体管可以为薄膜晶体管或场效应晶体管或其他特性相同的开关器件，薄膜晶体管可以包括氧化物半导体薄膜晶体管、非晶硅薄膜晶体管或多晶硅薄膜晶体管等。晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在物理结构上可以是没有区别的，本公开的实施例中全部或部分晶体管的源极和漏极根据需要是可以互换的。
在一些实施例中，如图14A所示，像素电路包括上述的薄膜晶体管T1、T2、T3、T4、T5、T6和T7、存储电容Cst、连接到多个薄膜晶体管T1、T2、T3、T4、T5、T6和T7的第一栅线GLn、第二栅线GLn-1、发光控制线EM、初始化线RL、数据线DAT和第一电源线VDD。下面，结合图13和图14A-10E对像素电路的结构进行说明。
例如，图14A为像素电路的半导体层、第一导电层、第二导电层 和第三导电层的层叠位置关系的示意图。
图14B示出了像素电路的半导体层。例如，图14B所示的该半导体层包括图3和图4中所示的有源层104，该有源层104例如为第六薄膜晶体管T6的有源层。如图14B所示，半导体层可采用半导体材料层通过构图工艺形成。半导体层可用于制作上述的第一薄膜晶体管T1、第二薄膜晶体管T2、第三薄膜晶体管T3、第四薄膜晶体管T4、第五薄膜晶体管T5、第六薄膜晶体管T6和第七薄膜晶体管T7的有源层，各有源层可包括源极区域、漏极区域以及源极区域和漏极区域之间的沟道区。例如，半导体层可采用非晶硅、多晶硅、氧化物半导体材料等制作。需要说明的是，上述的源极区域和漏极区域可为掺杂有n型杂质或p型杂质的区域。
在本公开一些实施例提供的显示基板中，在上述的半导体层上形成有绝缘层，该绝缘层包括图3和图4中所示的第一栅绝缘层105，图14A-10E中未示出。
图14C示出了像素电路的第一导电层。例如，如图14C所示，像素电路的第一导电层设置在上述绝缘层上，从而与图14B所示的半导体层绝缘。第一导电层可包括存储电容Cst的第一电容电极CE1(相当于第一极板130)、第一栅线GLn、第二栅线GLn-1、发光控制线EM、以及第一薄膜晶体管T1、第二薄膜晶体管T2、第三薄膜晶体管T3、第四薄膜晶体管T4、第五薄膜晶体管T5、第六薄膜晶体管T6和第七薄膜晶体管T7的栅极(例如，上述的第一栅极G1、第，二栅极G2、第三栅极G3、第四栅极G4、第五栅极G5、第六栅极G6和第七栅极G7)。如图14C所示，第二薄膜晶体管T2、第四薄膜晶体管T4、第五薄膜晶体管T5、第六薄膜晶体管T6和第七薄膜晶体管T7的栅极为第一栅线GLn、第二栅线GLn-1、发光控制线EM与半导体层交叠的部分，第三薄膜晶体管T3可为双栅结构的薄膜晶体管，第三薄膜晶体管T3的一个栅极可为第一栅线GLn与半导体层交叠的部分，第三薄膜晶体管T3的另一个栅极可为从第一栅线GLn突出的突出部；第一薄膜晶体管T1的栅极可为第一电容电极CE1。第四薄膜晶体管T4可为双栅结构的薄膜晶体管，两个栅极分别为第 二栅线GLn-1与半导体层交叠的部分。
在本公开一些实施例提供的显示基板中，在上述的第一导电层上形成有另一绝缘层，该绝缘层包括图3和图4中所示的第二栅绝缘层108，图14A-10E中未示出。
图14D示出了像素电路的第二导电层。例如，如图14D所示，像素电路的第二导电层包括存储电容Cst的第二电容电极CE2(即：第二极板131)和初始化线RL。第二电容电极CE2与第一电容电极CE1至少部分重叠以形成存储电容Cst。
例如，图14D示出的第二电容电极CE2具有缺口，在一些实施例中，第二电容电极CE2也可以不具有该缺口。本公开的实施例对第二电容电极CE2的具体结构不做限定。
在一些实施例中，第二导电层还可包括第一遮光部791和第二遮光部792。第一遮光部791在衬底基板上的正投影覆盖第二薄膜晶体管T2的有源层、第三薄膜晶体管T3的漏极和第四薄膜晶体管T4的漏极之间的有源层，从而防止外界光线对第二薄膜晶体管T2、第三薄膜晶体管T3和第四薄膜晶体管T4的有源层产生影响。第二遮光部792在衬底基板上的正投影覆盖第三薄膜晶体管T3的两个栅极之间的有源层，从而防止外界光线对第三薄膜晶体管T3的有源层产生影响。第一遮光部791可与相邻像素电路的第二遮光部792为一体结构，并通过贯穿绝缘层中的过孔与第一电源线VDD电连接。
在本公开一些实施例提供的显示基板中，在上述的第二导电层上形成有另一绝缘层，该绝缘层包括图3和图4中所示的层间介质层103，图14A-10E中未示出。
图14E示出了像素电路的第三导电层。例如，如图14E所示，像素电路的第三导电层包括数据线DAT和第一电源线VDD。结合图14A和图14E所示，数据线DAT通过第一栅绝缘层105、第二栅绝缘层108和层间介质层103中的至少一个过孔(例如过孔VH1)与半导体层中的第二薄膜晶体管T2的源极区域相连。第一电源线VDD通过第一栅绝缘层、第二栅绝缘层和层间介质层中的至少一个过孔(例如 过孔VH2)与半导体层中对应第五薄膜晶体管T5的源极区域相连。第一电源线VDD通过层间介质层中的至少一个过孔(例如过孔VH3)与第二导电层中的第二电容电极CE2相连。
例如，第三导电层还包括第一连接部CP1、第二连接部CP2和第三连接部CP3。第一连接部CP1的一端通过第一栅绝缘层105、第二栅绝缘层108和层间介质层103中的至少一个过孔(例如过孔VH4)与半导体层中对应第三薄膜晶体管T3的漏极区域相连，第一连接部CP1的另一端通过第二栅绝缘层108和层间介质层103中的至少一个过孔(例如过孔VH5)与第一导电层中的第一薄膜晶体管T1的栅极相连。第二连接部CP2的一端通过层间介质层中的一个过孔(例如过孔VH6)与初始化线RL相连，第二连接部CP2的另一端通过第一栅绝缘层105、第二栅绝缘层108和层间介质层103中的至少一个过孔(例如过孔VH7)与半导体层中的第七薄膜晶体管T7的源极区域和第四薄膜晶体管T4的源极区域相连。第三连接部CP3通过第一栅绝缘层105、第二栅绝缘层108和层间介质层103中的至少一个过孔(例如过孔VH8)与半导体层中的第六薄膜晶体管T6的漏极区域相连。
例如，在一些实施例中，显示基板的像素电路还可以具有第四导电层。例如，图14F示出了像素电路的第四导电层。如图14F所示，该第四导电层包括第二电源线VDD2和第三电源线VDD3，该第二电源线VDD2沿图中的竖直方向延伸，第三电源线VDD3与第二电源线VDD2相交。例如，第二电源线VDD2和第三电源线VDD3彼此电连接或为一体的结构。
例如，在一些实施例中，第二电源线VDD2和第三电源线VDD3分别通过过孔与第一电源线VDD电连接，由此从而形成网状的电源线结构。这种结构有助于降低电源线上的电阻从而降低电源线的压降，并有助于将电源电压均匀地输送至显示基板的各个子像素中。
例如，在一些实施例中，该第四导电层还包括与该第二电源线VDD2和第三电源线VDD3相绝缘的第四连接部CP4，该第四连接电 极234用于将第六晶体管T6的漏极D6与发光子像素1d电连接。例如，第四连接电极234即实现为上述实施例中的转接电极133，用于将发光子像素1d的第一电极112与薄膜晶体管的漏极111电连接。
在本公开一些实施例提供的显示基板中，在上述的第四导电层上形成有保护层，该保护层包括图3和图4中所示的平坦化部116，图14A-10E中未示出。
例如，在一些实施例中，上述各导电层也可以采用其他布图。例如，图15A示出了另一种第二导电层图的另一版图设计。如图15A所示，在该示例中，第二导电层包括存储电容Cst的第二电容电极CE2(即：第二极板131)、复位信号线Init1、第二电源信号线VDD2以及遮光部S。第二电源信号线VDD2与第二电容电极CE2一体形成。
例如，图15B示出了另一种第三导电层图的另一版图设计。如图15B所示，该第三导电层包括数据线Vd、第一电源信号线VDD1以及屏蔽线PB。上述数据线Vd、第一电源信号线VDD1以及屏蔽线PB均沿相同的方向延伸，例如图中的竖直方向。例如，第三导电层还可以包括第一连接部CP1、第二连接部CP2和第三连接部CP3，以用于将不同的走线或者电极电连接。
例如，图15C示出了另一种第四导电层图的另一版图设计。如图15C所示，该第四导电层包括第四连接部CP4以及沿图中的竖直方向和水平方向交叉分布的第三电源信号线VDD3。例如，在一些示例中，第三电源信号线VDD3可与第一电源信号线VDD1并联，从而形成网状的电源结构，有利于降低电源信号线的电阻。
本领域技术人员在考虑说明书及实践这里公开的内容后，将容易想到本公开的其他实施例。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由权利要求指出。

Claims (24)

  1. 一种显示基板，所述显示基板具有显示区、开孔区及位于所述显示区与开孔区之间的过渡区，所述过渡区环绕所述开孔区设置；其中，所述显示基板包括：
    衬底基板；
    驱动电路层，形成在所述衬底基板上，所述驱动电路层包括位于所述显示区和所述过渡区的层间介质层；
    显示器件，位于所述显示区，并包括依次形成在所述层间介质层上的第一电极和像素界定部；
    第一封装坝，位于所述过渡区并环绕所述开孔区设置，且所述第一封装坝包括依次层叠在所述层间介质层上的第一保护部和第一阻隔部；
    第二封装坝，位于所述过渡区并环绕所述开孔区设置，所述第二封装坝位于所述第一封装坝远离所述显示区的一侧，且所述第二封装坝的厚度大于所述第一封装坝的厚度，所述第二封装坝包括依次层叠在所述层间介质层上的第二保护部和第二阻隔部；其中，
    所述第一阻隔部、所述第二阻隔部与所述像素界定部同层设置、且相互断开；
    且所述第一封装坝与所述第二封装坝之间的间距小于所述第一封装坝与所述显示区的间距。
  2. 根据权利要求1所述的显示基板，其中，所述第二保护部的厚度大于所述第一保护部的厚度。
  3. 根据权利要求2所述的显示基板，其中，所述第一保护部与所述第一电极同层设置、且相互断开。
  4. 根据权利要求2所述的显示基板，其中，
    所述显示基板还包括平坦化部，所述平坦化部位于所述显示区并形成在所述层间介质层与所述第一电极之间；
    其中，所述第一保护部与所述平坦化部同层设置、且相互断开。
  5. 根据权利要求3或4所述的显示基板，其中，所述第二保护部与 所述第一保护部同层设置。
  6. 根据权利要求3所述的显示基板，其中，
    所述显示基板还包括平坦化部，所述平坦化部位于所述显示区并形成在所述层间介质层与所述第一电极之间；
    其中，所述第二保护部与所述平坦化部同层设置、且相互断开。
  7. 根据权利要求1所述的显示基板，其中，
    所述第一封装坝和所述第二封装坝中的至少一者还包括隔垫部，所述隔垫部形成在所述第一阻隔部或所述第二阻隔部背离所述层间介质层的一侧；
    所述显示器件还包括支撑部，所述支撑部形成在所述像素界定部背离所述衬底基板的一侧，所述支撑部与所述隔垫部同层设置。
  8. 根据权利要求1所述的显示基板，其中，
    所述显示基板还具有位于所述显示区与所述过渡区之间的隔离区，所述隔离区环绕所述过渡区设置；
    所述显示基板还包括隔离柱，形成在所述层间介质层背离所述衬底基板的一侧并位于所述隔离区，所述隔离柱环绕所述第一封装坝设置，所述隔离柱的侧壁设置有凹槽。
  9. 根据权利要求8所述的显示基板，其中，
    所述驱动电路层包括位于所述显示区的薄膜晶体管，所述薄膜晶体管的源极和漏极与所述隔离柱同层设置、且相互断开。
  10. 根据权利要求9所述的显示基板，其中，
    所述显示基板还具有位于所述隔离区与所述显示区之间的内圈走线区，所述内圈走线区环绕所述隔离区设置；
    所述驱动电路层还包括位于所述内圈走线区的内圈信号线，所述内圈信号线与所述显示区的信号走线电连接。
  11. 根据权利要求9所述的显示基板，其中，
    所述隔离柱包括依次层叠在所述层间介质层上的第一金属层、第二金属层及第三金属层，所述第二金属层在所述层间介质层上的正投影的外边界位于所述第一金属层、所述第三金属层在所述层间介质层上的正投影的外边界内侧，以在所述隔离柱的侧壁形成所述凹槽。
  12. 根据权利要求11所述的显示基板，其中，
    所述第一金属层和所述第三金属层为钛层，所述第二金属层为铝层。
  13. 根据权利要求8所述的显示基板，其中，
    所述驱动电路层具有位于所述隔离区的第一开槽和第二开槽；所述第一开槽位于所述隔离柱靠近所述第一封装坝的一侧，所述第一开槽环绕所述第一封装坝设置；所述第二开槽位于所述隔离柱靠近所述显示区的一侧，所述第二开槽环绕所述第一开槽设置；
    其中，所述第一开槽和所述第二开槽贯穿所述驱动电路层。
  14. 根据权利要求1所述的显示基板，其中，
    所述显示基板还包括封装层，所述封装层包括依次层叠设置的第一无机封装薄膜层、有机封装薄膜层和第二无机封装薄膜层；
    所述第一无机封装薄膜层和所述第二无机封装薄膜层封装所述第一封装坝、所述第二封装坝和所述显示器件；
    所述有机封装薄膜层封装所述显示器件，并在所述第一封装坝靠近所述显示区的一侧阻断。
  15. 一种显示基板的制作方法，所述显示基板具有显示区、开孔区及位于所述显示区与开孔区之间的过渡区，所述过渡区环绕所述开孔区设置；其中，所述制作方法包括：
    提供一衬底基板；
    在所述衬底基板上形成驱动电路层，所述驱动电路层包括位于所述显示区和所述过渡区的层间介质层；
    在所述层间介质层背离所述衬底基板的一侧形成显示器件、第一封装坝和第二封装坝；所述显示器件位于所述显示区，并包括依次形成在所述层间介质层上的第一电极和像素界定部；所述第一封装坝位于所述过渡区并环绕所述开孔区设置，且所述第一封装坝包括依次层叠在所述层间介质层上的第一保护部和第一阻隔部；所述第二封装坝位于所述过渡区并环绕所述开孔区设置，所述第二封装坝位于所述第一封装坝远离所述显示区的一侧，且所述第二封装坝的厚度大于所述第一封装坝的厚度，所述第二封装坝包括依次层叠在所述层间介质层上的第二保护部和第二阻隔部；其中，
    利用同一次构图工艺形成相互断开的所述第一阻隔部、所述第二阻隔部与所述像素界定部；
    且所述第一封装坝与所述第二封装坝之间的间距小于所述第一封装坝与所述显示区的间距。
  16. 根据权利要求15所述的制作方法，其中，利用同一次构图工艺形成相互断开的所述第一保护部与所述第一电极。
  17. 根据权利要求15所述的制作方法，其中，利用同一次构图工艺形成相互断开的所述第一保护部和平坦化部，所述平坦化部位于所述显示区并形成在所述层间介质层与所述第一电极之间。
  18. 根据权利要求16或17所述的制作方法，其中，利用同一次构图工艺形成相互断开的所述第二保护部与所述第一保护部。
  19. 根据权利要求16所述的制作方法，其中，
    利用同一次构图工艺形成相互断开的所述第二保护部和平坦化部，所述平坦化部位于所述显示区并形成在所述层间介质层与所述第一电极之间。
  20. 根据权利要求15所述的制作方法，其中，所述显示基板还具有位于所述显示区与所述过渡区之间的隔离区，所述隔离区环绕所述过渡区设置；其中，所述制作方法还包括：
    在所述层间介质层背离所述衬底基板的一侧形成位于所述隔离区的隔离柱，所述隔离柱环绕所述过渡区设置，所述隔离柱的侧壁设置有凹槽。
  21. 根据权利要求20所述的制作方法，其中，所述驱动电路层包括位于所述显示区的薄膜晶体管，所述薄膜晶体管包括源极和漏极；
    其中，利用同一次构图工艺形成相互断开的所述源极、所述漏极和所述隔离柱。
  22. 根据权利要求21所述的制作方法，其中，所述显示基板还具有位于所述隔离区与所述显示区之间的内圈走线区，所述内圈走线区环绕所述隔离区设置；所述驱动电路层还包括位于所述内圈走线区的内圈信号线，所述内圈信号线与所述显示区的信号走线电连接。
  23. 根据权利要求15所述的制作方法，其中，在所述层间介质层背 离所述衬底基板的一侧形成显示器件、第一封装坝和第二封装坝之后，还包括：
    形成封装层，所述封装层包括依次层叠设置的第一无机封装薄膜层、有机封装薄膜层和第二无机封装薄膜层；
    所述第一无机封装薄膜层和所述第二无机封装薄膜层封装所述第一封装坝、所述第二封装坝和所述显示器件；
    所述有机封装薄膜层封装所述显示器件，并在所述第一封装坝靠近所述显示区的一侧阻断。
  24. 一种显示装置，其中，包括权利要求1至14中任一项所述的显示基板。
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