JP7234380B2 - アレイ基板及びその製造方法 - Google Patents
アレイ基板及びその製造方法 Download PDFInfo
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- JP7234380B2 JP7234380B2 JP2021538805A JP2021538805A JP7234380B2 JP 7234380 B2 JP7234380 B2 JP 7234380B2 JP 2021538805 A JP2021538805 A JP 2021538805A JP 2021538805 A JP2021538805 A JP 2021538805A JP 7234380 B2 JP7234380 B2 JP 7234380B2
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- 239000000758 substrate Substances 0.000 title claims description 101
- 238000004519 manufacturing process Methods 0.000 title claims description 32
- 239000010410 layer Substances 0.000 claims description 355
- 239000003990 capacitor Substances 0.000 claims description 93
- 229910052751 metal Inorganic materials 0.000 claims description 48
- 239000002184 metal Substances 0.000 claims description 48
- 239000000463 material Substances 0.000 claims description 47
- 239000011229 interlayer Substances 0.000 claims description 25
- 238000000034 method Methods 0.000 claims description 24
- 239000004065 semiconductor Substances 0.000 description 11
- 230000008569 process Effects 0.000 description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 7
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 6
- 238000010586 diagram Methods 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 6
- 239000010408 film Substances 0.000 description 6
- 238000009832 plasma treatment Methods 0.000 description 6
- 229920005591 polysilicon Polymers 0.000 description 6
- 238000005530 etching Methods 0.000 description 5
- 238000009434 installation Methods 0.000 description 4
- 238000000465 moulding Methods 0.000 description 3
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 2
- 238000004891 communication Methods 0.000 description 2
- 229910052733 gallium Inorganic materials 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 229910052738 indium Inorganic materials 0.000 description 2
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 2
- 229910010272 inorganic material Inorganic materials 0.000 description 2
- 239000011147 inorganic material Substances 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000000149 penetrating effect Effects 0.000 description 2
- 239000011787 zinc oxide Substances 0.000 description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 239000007777 multifunctional material Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
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Description
ベースと、
前記ベースに設けられる第1TFTであって、前記ベースに設けられる第1アクティブ層と、前記第1アクティブ層を覆うように前記ベース及び前記第1アクティブ層に設けられる第1ゲート絶縁層と、前記第1ゲート絶縁層に設けられる第1ゲートと、を含む第1TFTと、
前記第1ゲート絶縁層に設けられる第2TFTであって、前記第1ゲート絶縁層に設けられる第2アクティブ層と、前記第2アクティブ層に設けられる第2ゲート絶縁層と、前記第2ゲート絶縁層に設けられる第2ゲートと、を含む第2TFTと、を含み、
前記第1ゲート及び前記第2アクティブ層は、材料が同じであり、かつ一体成形される成形構造であるアレイ基板が提供される。
前記多機能金属層は、前記基板に設けられる信号サブ層を含み、
前記第1ゲート絶縁層には、前記信号サブ層と並列に接続される信号線が設けられる。
前記信号線は、各前記並列ビアホールをそれぞれ貫通して前記信号サブ層と並列に接続される。
前記第1ゲート絶縁層には、前記コンデンササブ層に対応する第1コンデンサ電極が設けられ、
前記第1ゲート絶縁層、前記第1ゲート、前記第2TFT、前記信号線及び前記第1コンデンサ電極には、前記第1ゲート絶縁層、前記第1ゲート、前記第2TFT、前記信号線及び前記第1コンデンサ電極を覆う層間絶縁層が設けられ、
前記層間絶縁層には、前記第1コンデンサ電極に対応する第2コンデンサ電極が設けられる。
前記第2TFTは、前記層間絶縁層に設けられる第2ソースドレインを含み、
前記第1ソースドレイン、前記第2ソースドレイン及び前記第2コンデンサ電極は、材料が同じであり、かつ一体成形される成形構造である。
ベースを提供することと、
前記ベースに設けられる第1アクティブ層と、前記第1アクティブ層を覆うように前記ベース及び前記第1アクティブ層に設けられる第1ゲート絶縁層と、前記第1ゲート絶縁層に設けられる第1ゲートと、を含む第1TFTを前記ベースに形成することと、
前記第1ゲート絶縁層に設けられる第2アクティブ層と、前記第2アクティブ層に設けられる第2ゲート絶縁層と、前記第2ゲート絶縁層に設けられる第2ゲートと、を含む第2TFTを前記第1ゲート絶縁層に形成することと、を含み、
前記第1ゲート及び前記第2アクティブ層は、材料が同じであり、かつ一体成形される成形構造であるアレイ基板の製造方法が提供される。
基板を提供することと、
前記基板に多機能金属層を形成し、前記基板及び前記多機能金属層に前記多機能金属層を覆うバッファ層を形成することと、を含み、
前記多機能金属層は、前記基板に設けられる信号サブ層を含み、
前記第1ゲート絶縁層には、前記信号サブ層と並列に接続される信号線が設けられ、
前記信号サブ層には、前記バッファ層及び前記第1ゲート絶縁層を貫通する少なくとも二つの並列ビアホールが形成され、
前記信号線は、各前記並列ビアホールをそれぞれ貫通して前記信号サブ層と並列に接続される。
図2に示すように、アレイ基板は、ベース10と、(a)領域内に位置するように前記ベースに設けられる第1TFT101であって、前記ベースに設けられる第1アクティブ層21、前記第1アクティブ層21を覆うように前記ベース10及び前記第1アクティブ層21に設けられる第1ゲート絶縁層22、及び、前記第1ゲート絶縁層22に設けられる第1ゲート23を含む第1TFT101と、(b)領域内に位置するように前記第1ゲート絶縁層22に設けられる第2TFT102であって、前記第1ゲート絶縁層22に設けられる第2アクティブ層31、前記第2アクティブ層31に設けられる第2ゲート絶縁層32、及び、前記第2ゲート絶縁層32に設けられる第2ゲート33を含む第2TFT102と、を含む。
図3を参照して、本実施例と実施例1とは、同一であり又は類似するが、以下の点で相違する。
図5を参照して、本実施例と実施例1及び実施例2とは、同一であり又は類似するが、以下の点で相違する。
図6を参照して、本実施例と実施例1~3とは、同一であり又は類似するが、以下の点で相違する。
ベースを提供するステップS10と、
前記ベース10に設けられる第1アクティブ層21と、前記第1アクティブ層21を覆うように前記ベース10及び前記第1アクティブ層21に設けられる第1ゲート絶縁層22と、前記第1ゲート絶縁層22に設けられる第1ゲート23と、を含む第1TFT101を前記ベース10に形成するステップS20と、
前記第1ゲート絶縁層22に設けられる第2アクティブ層31と、前記第2アクティブ層31に設けられる第2ゲート絶縁層32と、前記第2ゲート絶縁層32に設けられる第2ゲート33と、を含む第2TFT102を前記第1ゲート絶縁層22に形成するステップS30と、を含み、
前記第1ゲート23及び前記第2アクティブ層31は、材料が同じであり、かつ一体成形される成形構造であるアレイ基板の製造方法が提供される。
1)ベース10を提供し、
2)ベース10に第1TFT101の第1アクティブ層21を形成し、
3)ベース10及び第1アクティブ層21に第1アクティブ層21を覆う第1ゲート絶縁層22を形成し、
4)第1ゲート絶縁層22に第1ゲート23及び第2TFT102の第2アクティブ層を形成し、第1ゲート23及び第2アクティブ層31は、材料が同じであり、かつ一体成形される成形方法により製造され、
5)第2アクティブ層31に第2ゲート絶縁層32を形成し、
6)第2ゲート絶縁層32に第2ゲート33を形成する。
前記ベース10を提供することは、
1)基板11を提供することと、
2)前記基板11に多機能金属層12を形成することと、
3)前記基板11及び前記多機能金属層12に前記多機能金属層12を覆うバッファ層13を形成することと、を含む。
Claims (14)
- ベースと、
前記ベースに設けられる第1TFTであって、前記ベースに設けられる第1アクティブ層と、前記第1アクティブ層を覆うように前記ベース及び前記第1アクティブ層に設けられる第1ゲート絶縁層と、前記第1ゲート絶縁層に設けられる第1ゲートと、を含む第1TFTと、
前記第1ゲート絶縁層に設けられる第2TFTであって、前記第1ゲート絶縁層に設けられる第2アクティブ層と、前記第2アクティブ層に設けられる第2ゲート絶縁層と、前記第2ゲート絶縁層に設けられる第2ゲートと、を含む第2TFTと、を含み、
前記第1ゲート及び前記第2アクティブ層は、材料が同じであり、かつ一体成形される成形構造であり、
前記ベースは、基板と、前記基板に設けられる多機能金属層と、前記多機能金属層を覆うように前記基板及び前記多機能金属層に設けられるバッファ層と、を含み、
前記多機能金属層は、前記基板に設けられるコンデンササブ層をさらに含み、
前記第1ゲート絶縁層には、前記コンデンササブ層に対応する第1コンデンサ電極が設けられ、
前記第1ゲート絶縁層、前記第1ゲート、前記第2TFT、及び前記第1コンデンサ電極には、前記第1ゲート絶縁層、前記第1ゲート、前記第2TFT、及び前記第1コンデンサ電極を覆う層間絶縁層が設けられ、
前記層間絶縁層には、前記第1コンデンサ電極に対応する第2コンデンサ電極が設けられ、
前記コンデンササブ層、前記第1コンデンサ電極、及び前記第2コンデンサ電極は、互いに電気的に接続されずに積層方向に対して垂直方向に重なるように設けられ、三層構造のコンデンサを形成する、
アレイ基板。 - 前記多機能金属層は、前記基板に設けられる信号サブ層を含み、
前記第1ゲート絶縁層には、前記信号サブ層と並列に接続される信号線が設けられ、
前記信号線は、前記層間絶縁層により覆われる、
請求項1に記載のアレイ基板。 - 前記信号サブ層には、前記バッファ層及び前記第1ゲート絶縁層を貫通する少なくとも二つの並列ビアホールが形成され、
前記信号線は、各前記並列ビアホールをそれぞれ貫通して前記信号サブ層と並列に接続される、
請求項2に記載のアレイ基板。 - 前記第1ゲート、前記第2アクティブ層及び前記信号線は、材料が同じであり、かつ一体成形される成形構造である、
請求項3に記載のアレイ基板。 - 前記第1コンデンサ電極及び前記第2ゲートは、材料が同じであり、かつ一体成形される成形構造である、
請求項1に記載のアレイ基板。 - 前記第1TFTは、前記層間絶縁層に設けられる第1ソースドレインを含み、
前記第2TFTは、前記層間絶縁層に設けられる第2ソースドレインを含み、
前記第1ソースドレイン、前記第2ソースドレイン及び前記第2コンデンサ電極は、材料が同じであり、かつ一体成形される成形構造である、
請求項1に記載のアレイ基板。 - 前記第2アクティブ層はIGZOである、
請求項1に記載のアレイ基板。 - ベースと、
前記ベースに設けられる第1TFTであって、前記ベースに設けられる第1アクティブ層と、前記第1アクティブ層を覆うように前記ベース及び前記第1アクティブ層に設けられる第1ゲート絶縁層と、前記第1ゲート絶縁層に設けられる第1ゲートと、を含む第1TFTと、
前記第1ゲート絶縁層に設けられる第2TFTであって、前記第1ゲート絶縁層に設けられる第2アクティブ層と、前記第2アクティブ層に設けられる第2ゲート絶縁層と、前記第2ゲート絶縁層に設けられる第2ゲートと、を含む第2TFTと、を含み、
前記第1ゲート及び前記第2アクティブ層は、材料が同じであり、かつ一体成形される
成形構造であり、
前記ベースは、基板と、前記基板に設けられる多機能金属層と、前記多機能金属層を覆
うように前記基板及び前記多機能金属層に設けられるバッファ層と、を含み、
前記多機能金属層は、前記基板に設けられる信号サブ層を含み、
前記第1ゲート絶縁層には、前記信号サブ層と並列に接続される信号線が設けられ、
前記信号サブ層には、前記バッファ層及び前記第1ゲート絶縁層を貫通する少なくとも二つの並列ビアホールが形成され、
前記信号線は、各前記並列ビアホールをそれぞれ貫通して前記信号サブ層と並列に接続され、
前記多機能金属層は、前記基板に設けられるコンデンササブ層をさらに含み、
前記第1ゲート絶縁層には、前記コンデンササブ層に対応する第1コンデンサ電極が設けられ、
前記第1ゲート絶縁層、前記第1ゲート、前記第2TFT、前記信号線及び前記第1コンデンサ電極には、前記第1ゲート絶縁層、前記第1ゲート、前記第2TFT、前記信号線及び前記第1コンデンサ電極を覆う層間絶縁層が設けられ、
前記層間絶縁層には、前記第1コンデンサ電極に対応する第2コンデンサ電極が設けられ、
前記コンデンササブ層、前記第1コンデンサ電極、及び前記第2コンデンサ電極は、互いに電気的に接続されずに積層方向に対して垂直方向に重なるように設けられ、三層構造のコンデンサを形成する、
アレイ基板。 - 前記第1ゲート、前記第2アクティブ層及び前記信号線は、材料が同じであり、かつ一体成形される成形構造である、
請求項8に記載のアレイ基板。 - 前記第1コンデンサ電極及び前記第2ゲートは、材料が同じであり、かつ一体成形される成形構造である、
請求項8に記載のアレイ基板。 - 前記第1TFTは、前記層間絶縁層に設けられる第1ソースドレインを含み、
前記第2TFTは、前記層間絶縁層に設けられる第2ソースドレインを含み、
前記第1ソースドレイン、前記第2ソースドレイン及び前記第2コンデンサ電極は、材料が同じであり、かつ一体成形される成形構造である、
請求項8に記載のアレイ基板。 - 前記第2アクティブ層はIGZOである、
請求項8に記載のアレイ基板。 - ベースを提供することと、
前記ベースに設けられる第1アクティブ層と、前記第1アクティブ層を覆うように前記ベース及び前記第1アクティブ層に設けられる第1ゲート絶縁層と、前記第1ゲート絶縁層に設けられる第1ゲートと、を含む第1TFTを前記ベースに形成することと、
前記第1ゲート絶縁層に設けられる第2アクティブ層と、前記第2アクティブ層に設けられる第2ゲート絶縁層と、前記第2ゲート絶縁層に設けられる第2ゲートと、を含む第2TFTを前記第1ゲート絶縁層に形成することと、を含み、
前記第1ゲート及び前記第2アクティブ層は、材料が同じであり、かつ一体成形される成形構造であり、
前記ベースを提供することは、基板を提供することと、前記基板に多機能金属層を形成し、前記基板及び前記多機能金属層に前記多機能金属層を覆うバッファ層を形成することと、を含み、
前記多機能金属層は、前記基板に設けられるコンデンササブ層をさらに含み、
前記第1ゲート絶縁層には、前記コンデンササブ層に対応する第1コンデンサ電極が設けられ、
前記第1ゲート絶縁層、前記第1ゲート、前記第2TFT及び前記第1コンデンサ電極には、前記第1ゲート絶縁層、前記第1ゲート、前記第2TFT及び前記第1コンデンサ電極を覆う層間絶縁層が設けられ、
前記層間絶縁層には、前記第1コンデンサ電極に対応する第2コンデンサ電極が設けられ、
前記コンデンササブ層、前記第1コンデンサ電極、及び前記第2コンデンサ電極は、互いに電気的に接続されずに積層方向に対して垂直方向に重なるように設けられ、三層構造のコンデンサを形成する、
アレイ基板の製造方法。 - 前記多機能金属層は、前記基板に設けられる信号サブ層を含み、
前記第1ゲート絶縁層には、前記信号サブ層と並列に接続される信号線が設けられ、
前記信号サブ層には、前記バッファ層及び前記第1ゲート絶縁層を貫通する少なくとも
二つの並列ビアホールが形成され、
前記信号線は、各前記並列ビアホールをそれぞれ貫通して前記信号サブ層と並列に
接続される、
請求項13に記載のアレイ基板の製造方法。
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CN107819038A (zh) | 2016-09-12 | 2018-03-20 | 三星显示有限公司 | 晶体管和具有该晶体管的显示装置 |
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CN107403804A (zh) | 2016-05-17 | 2017-11-28 | 群创光电股份有限公司 | 显示设备 |
US10629665B2 (en) | 2016-08-30 | 2020-04-21 | Samsung Display Co., Ltd. | Semiconductor device including an oxide thin film transistor |
US20180061868A1 (en) | 2016-08-31 | 2018-03-01 | Lg Display Co., Ltd. | Organic light-emitting display device comprising multiple types of thin-film transistors and method of fabricating the same |
CN107819038A (zh) | 2016-09-12 | 2018-03-20 | 三星显示有限公司 | 晶体管和具有该晶体管的显示装置 |
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