CN107819038A - 晶体管和具有该晶体管的显示装置 - Google Patents

晶体管和具有该晶体管的显示装置 Download PDF

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Publication number
CN107819038A
CN107819038A CN201710817570.3A CN201710817570A CN107819038A CN 107819038 A CN107819038 A CN 107819038A CN 201710817570 A CN201710817570 A CN 201710817570A CN 107819038 A CN107819038 A CN 107819038A
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Prior art keywords
transistor
contact site
insulating barrier
floating grid
oxide
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CN107819038B (zh
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林志勋
金宰范
朴晙皙
孙暻锡
林俊亨
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Samsung Display Co Ltd
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Samsung Display Co Ltd
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Abstract

提供了一种晶体管和一种具有该晶体管的显示装置。所述晶体管包括：半导体层，包括沟道部、第一接触部和第二接触部；栅电极，面对浮置栅极；浮置栅极，设置在半导体层和栅电极之间浮置栅极与半导体层和栅电极绝缘。浮置栅极包括氧化物半导体。

Description

晶体管和具有该晶体管的显示装置
本申请要求于2016年9月12日提交的第10-2016-0117118号韩国专利申请的优先权，该韩国专利申请的全部内容通过引用全部包含于此。
技术领域
本公开涉及一种存储器晶体管和一种具有该存储器晶体管的显示装置。更具体地，本公开涉及一种能够改善存储器效率的存储器晶体管和一种具有该存储器晶体管的显示装置。
背景技术
有机发光显示装置包括多个像素。每个像素包括有机发光二极管和控制有机发光二极管的电路。
有机发光二极管包括阳极、阴极和设置在阳极与阴极之间的有机发光层。当在阳极与阴极之间施加有大于有机发光层的阈值电压的电压时，有机发光二极管发光。
电路包括控制晶体管、驱动晶体管和存储电容器。驱动晶体管和控制晶体管是具有半导体材料作为沟道层的晶体管。驱动晶体管和控制晶体管中的每个可以包括相同的半导体材料，但是近来已经开发了使用用于驱动晶体管和控制晶体管的不同的半导体材料的结构。
此外，近来，具有低功耗结构的显示装置使用具有存储器功能的晶体管作为驱动晶体管和控制晶体管。
发明内容
本公开提供了一种具有存储器功能并且能够改善阈值电压的可控性的晶体管。
本公开提供了一种具有所述晶体管、能够减少漏电流并且使功耗最小化的显示装置。
发明构思的实施例提供了一种晶体管，所述晶体管包括：半导体层，包括沟道部、第一接触部和第二接触部；浮置栅极，面对半导体层的沟道部；栅电极，面对浮置栅极，浮置栅极设置在半导体层与栅电极之间；以及源电极和漏电极，分别与第一接触部和第二接触部接触。浮置栅极包括氧化物半导体。
发明构思的实施例提供了一种显示装置，所述显示装置包括：第一线；第二线，与第一线不同；开关晶体管，连接到第一线和第二线；以及显示元件，连接到开关晶体管。
开关晶体管包括：第一半导体层，包括沟道部、第一接触部和第二接触部；浮置栅极，面对第一半导体层的沟道部；栅电极，面对浮置栅极；以及源电极和漏电极，分别与第一接触部和第二接触部接触。浮置栅极包括氧化物半导体。
根据上述，晶体管包括由氧化物半导体形成的浮置栅极。当浮置栅极由氧化物半导体形成时，改善了通过捕获或控制来自浮置栅极的电荷来改变阈值电压的能力，从而减少了漏电流。
此外，由氧化物半导体形成的浮置栅极进一步设置在执行显示装置的存储器功能的晶体管中。因此，当以低功率驱动显示装置时，能够有效降低功耗。
附图说明
当结合附图考虑时，通过下面的详细描述，本公开的以上和其它优点将变得很明显，在附图中：
图1是示出根据本公开的示例性实施例的存储器晶体管的剖视图；
图2是示出根据施加到图1中示出的栅电极的栅极电压的阈值电压的偏移的波形图；
图3是示出根据本公开的示例性实施例的存储器晶体管的剖视图；
图4是示出根据本公开的示例性实施例的有机发光显示装置的框图；
图5是示出图4中示出的像素的电路图；
图6是图5中示出的像素的剖视图；
图7A、图7B、图7C、图7D、图7E、图7F和图7G是示出制造图6中示出的像素的工艺的剖视图。
图8是示出根据本公开的示例性实施例的像素的电路图；
图9是示出图8中示出的像素的剖视图。
具体实施方式
将理解的是，当元件或层被称为“在”另一元件或层“上”、“连接到”或“结合到”另一元件或层时，该元件或层可直接在所述另一元件或层上、直接连接到或直接结合到所述另一元件或层，或者可以存在中间元件或层。相反，当元件或层被称为“直接在”另一元件或层“上”、“直接连接到”或“直接结合到”另一元件或层时，不存在中间元件或层。同样的附图标记始终表示同样的元件。如在此使用的，术语“和/或”包括一个或更多个相关所列项的任何组合和全部组合。
将理解的是，尽管在此可以使用术语第一、第二等来描述各种元件、组件、区域、层和/或部分，但是这些元件、组件、区域、层和/或部分不应受这些术语限制。这些术语仅用来将一个元件、组件、区域、层或部分与另一元件、组件、区域、层或部分区分开。因此，在不脱离本发明构思的教导的情况下，以下讨论的第一元件、第一组件、第一区域、第一层和/或第一部分可被命名为第二元件、第二组件、第二区域、第二层和/或第二部分。
为了易于描述如图中示出的一个元件或特征相对其它元件或特征的关系，可以在此使用诸如“在……之下”、“在……下方”、“下”、“在……上方”和“上”等的空间相对术语。将理解的是，空间相对术语意图包含除了在图中描绘的方位之外的装置在使用或操作中的不同方位。例如，如果图中的装置被翻转，则被描述为“在”其它元件或特征“下方”或“之下”的元件随后被定位为“在”所述其它元件或特征“上方”。因此，示例性术语“在……下方”可以包含上方和下方两种方位。装置可以被另外定位(旋转90度或在其它方位处)，因此相应地解释在此使用的空间相对描述语。
在此使用的术语是出于描述具体实施例的目的，而不意图限制发明构思。如在此使用的，除非上下文另外明确地指出，否则单数形式“一个”、“一种”和“该(所述)”也意图包括复数形式。还将理解的是，当在该说明书中使用术语“包括”和/或“包含”时，说明存在陈述的特征、整体、步骤、操作、元件、组件和/或它们的组，但是不排除存在或附加一个或更多个其它特征、整体、步骤、操作、元件、组件和/或它们的组。
除非另外定义，否则在此使用的所有术语(包括技术术语和科学术语)具有与本发明构思所属领域的普通技术人员所通常理解的意思相同的意思。还将理解的是，除非这里明确定义，否则术语(诸如在通用的字典中定义的术语)应该被解释为具有与相关领域的上下文中它们的意思一致的意思，而将不以理想的或者过于形式化的意思来被解释。
在下文中，将参照附图详细地解释本发明构思。
图1是示出根据本公开的示例性实施例的存储器晶体管的剖视图。
参照图1，存储器晶体管MT设置在基体基底SUB上。在本公开的示例性实施例中，存储器晶体管MT包括半导体层AL、浮置栅极FGE、栅电极GE、源电极SE和漏电极DE。
半导体层AL包括沟道部CH、第一接触部OCT1和第二接触部OCT2。沟道部CH是存储器晶体管MT的沟道区。在本公开的示例性实施例中，半导体层AL可以包括多晶硅。第一接触部OCT1和第二接触部OCT2可以是包括掺杂剂的区域。第一接触部OCT1和第二接触部OCT2可以掺杂有诸如注入的n+掺杂剂或p+掺杂剂的杂质。注入到第一接触部OCT1和第二接触部OCT2中的掺杂剂可以根据存储器晶体管MT的类型而改变。在本公开的示例性实施例中，存储器晶体管MT可以是N型晶体管，但是根据本公开的存储器晶体管MT的类型不应限于此。在存储器晶体管MT是N型晶体管的情况下，第一接触部OCT1和第二接触部OCT2可以是n+掺杂区。沟道部CH形成在第一接触部OCT1与第二接触部OCT2之间。
存储器晶体管MT1还可以包括绝缘图案ILP。在与半导体层AL的沟道部CH对应的区域中设置绝缘图案ILP之后，掺杂剂可以注入到区域中，以形成半导体层AL的第一接触部OCT1和第二接触部OCT2。在本公开的示例性实施例中，绝缘图案ILP可以包括诸如氧化硅SiOx、氮化硅SiNx、氮氧化硅SiON、氟化氧化硅SiOF或氧化铝AlOx等的无机材料或者有机材料，并且包括具有上面材料中的至少一种的单层或多层。
存储器晶体管MT还可以包括覆盖半导体层AL和绝缘图案ILP的第一绝缘层IL1。第一绝缘层IL1可以包括诸如氧化硅SiOx、氮化硅SiNx、氮氧化硅SiON、氟化氧化硅SiOF或氧化铝AlOx等的无机材料或者有机材料，并且包括具有上面材料中的至少一种的单层或多层。浮置栅极FGE形成在第一绝缘层IL1上。
浮置栅极FGE形成在第一绝缘层IL1上，以面对半导体层AL的沟道部CH。浮置栅极FGE包括氧化物半导体。在本公开的示例性实施例中，氧化物半导体可以包括诸如锌Zn、铟In、镓Ga、锡Sn、钛Ti等的金属氧化物或诸如锌Zn、铟In、镓Ga、锡Sn、钛Ti等的金属氧化物的组合。更具体地，氧化物半导体可以包括氧化锌ZnO、氧化锌锡ZTO、氧化锌铟ZIO、氧化铟In2O3、氧化钛TiO2、氧化铟镓锌IGZO、氧化铟锌锡IZTO等。
为了改善的浮置栅极FGE的导电性，可以对氧化物半导体执行氢H等离子体工艺。在本公开的示例性实施例中，具有1E+17/cm3或更大的氢掺杂浓度的IGZO可以用作浮置栅极FGE。
存储器晶体管MT还可以包括覆盖浮置栅极FGE的第二绝缘层IL2，栅电极GE形成在第二绝缘层IL2上。第二绝缘层IL2可以包括氧化硅SiOx、氮化硅SiNx、氮氧化硅SiON、氟化氧化硅SiOF或氧化铝AlOx等的无机材料或者有机材料，并且包括具有上面材料中的至少一种的单层或多层。在图1中，第二绝缘层IL2具有单层结构，但是发明构思不限于此。在单层结构中，第二绝缘层IL2可以包括氮化硅SiNx。在第二绝缘层IL2具有双层结构的情况下，第二绝缘层IL2可以包括顺序地堆叠的下层和上层。在本公开的示例性实施例中，下层可以包括氧化硅SiOx，上层可以包括氮化硅SiNx。
栅电极GE设置在第二绝缘层IL2上，以面对浮置栅极FGE。栅电极GE可以包括金属材料。
第一接触孔CNT1和第二接触孔CNT2被形成为通过第一绝缘层IL1和第二绝缘层IL2，以暴露第一接触部OCT1和第二接触部OCT2。第一接触孔CNT1和第二接触孔CNT2穿过第一绝缘层IL1和第二绝缘层IL2，并且分别部分地暴露第一接触部OCT1和第二接触部OCT2。
源电极SE和漏电极DE形成在第二绝缘层IL2上，并且分别通过第一接触孔CNT1和第二接触孔CNT2与第一接触部OCT1和第二接触部OCT2接触。源电极SE和漏电极DE可以包括金属材料。源电极SE和漏电极DE可以由与栅电极GE相同的金属材料形成。在这种情况下，可以经由同一光刻工艺同时使栅电极GE、源电极SE和漏电极DE图案化，但是发明构思不限于此。栅电极GE以及源电极SE和漏电极DE可以由不同的材料形成，并且经由不同的光刻工艺被图案化。栅电极GE以及源电极SE和漏电极DE可以形成在不同的层上。
图2是示出根据施加到图1中示出的栅电极的栅极电压的阈值电压的偏移的波形图。在图2中，x轴表示施加到栅电极GE的栅极偏置电压V，y轴表示漏电流A。
参照图1和图2，当足够的电压被施加到栅电极GE时，沟道通过载流子形成在沟道部CH中，然后从存储器晶体管MT的源电极SE到存储器晶体管MT的漏电极DE的电流流过沟道。如图1中所示，在具有浮置栅极FGE的存储器晶体管MT中，第一电容器形成在沟道部CH与浮置栅极FGE之间，第二电容器形成在栅电极GE与浮置栅极FGE之间。第一电容器和第二电容器串联连接。
在浮置栅极FGE中捕获或去除的电荷改变了存储器晶体管MT的阈值电压Vth。在图2中，第一曲线G1表示电荷被捕获在浮置栅极FGE中之前的状态。如图2的第二曲线G2中所示，当施加到栅电极GE的偏置电压改变时，电荷被捕获在浮置栅极FGE中。当电荷被捕获在浮置栅极FGE中时，存储器晶体管MT的阈值电压Vth被改变。例如，如第二曲线G2中所示，当电荷被捕获在浮置栅极FGE中时，阈值电压Vth可以偏移到正电压(+)。
根据本公开，浮置栅极FGE包括具有高导电率的氧化物半导体。因为氧化物半导体具有相对宽的带隙并且可以使捕获位点(trap sites)比多晶硅更有用，所以氧化物半导体有利于载流子的充电。因此，当浮置栅极FGE包括氧化物半导体时，可以通过捕获或控制来自浮置栅极FGE的电荷来改善改变阈值电压Vth的能力。
具有图1中示出的结构的存储器晶体管MT可以作为具有存储器功能的晶体管应用于显示装置的显示元件(例如，有机发光二极管或液晶显示装置)。
图3是示出根据本公开的示例性实施例的存储器晶体管的剖视图。然而，贯穿图5和图7A至图7G，同样的附图标记表示同样的元件，并且省略了它们的详细描述。
参照图3，缓冲层BUF形成在基体基底SUB上。存储器晶体管MT'形成在缓冲层BUF上。缓冲层BUF在执行薄膜工艺之前形成，以在基体基底SUB上形成存储器晶体管MT'，从而防止湿气或杂质渗透到存储器晶体管MT'中。
半导体层AL形成在缓冲层BUF上，第一绝缘层IL1设置在半导体层AL上。第一绝缘层IL1包括氧化硅SiOx。
浮置栅极FGE形成在第一绝缘层IL1上。第一接触部OCT1和第二接触部OCT2使用浮置栅极FGE作为掩模通过掺杂工艺掺杂杂质。
因为半导体层AL的沟道部CH与设置浮置栅极FGE的区域对应，所以沟道部CH在掺杂工艺期间不被掺杂。因此，沟道部CH被定义为存储器晶体管MT'的沟道区。在本公开的示例性实施例中，半导体层AL可以包括多晶硅。
浮置栅极FGE可以包括氧化物半导体。在本公开的示例性实施例中，氧化物半导体可以包括诸如锌Zn、铟In、镓Ga、锡Sn、钛Ti等的金属氧化物或诸如锌Zn、铟In、镓Ga、锡Sn、钛Ti等的金属氧化物的组合。更具体地，氧化物半导体可以包括氧化锌ZnO、氧化锌锡ZTO、氧化锌铟ZIO、氧化铟In2O3、氧化钛TiO2、氧化铟镓锌IGZO、氧化铟锌锡IZTO等。
此外，根据本公开，浮置栅极FGE是n型氧化物半导体，例如，具有1E+17/cm3或更大的掺杂浓度的IGZO可以用作浮置栅极FGE。
存储器晶体管MT'还可以包括覆盖浮置栅极FGE的第二绝缘层IL2。第二绝缘层IL2可以包括氧化硅SiOx、氮化硅SiNx、氮氧化硅SiON、氟化氧化硅SiOF或氧化铝AlOx等的无机材料或者有机材料，并且包括具有上面材料中的至少一种的单层或多层。
栅电极GE设置在第二绝缘层IL2上，以面对浮置栅极FGE。栅电极GE可以包括金属材料。
栅电极GE被第三绝缘层IL3覆盖，第一接触孔CNT1和第二接触孔CNT2形成为通过第一绝缘层IL1、第二绝缘层IL2和第三绝缘层IL3，以暴露第一接触部OCT1和第二接触部OCT2。第三绝缘层IL3可以包括氧化硅SiOx、氮化硅SiNx、氮氧化硅SiON、氟化氧化硅SiOF或氧化铝AlOx等的无机材料或者有机材料，并且包括具有上面材料中的至少一种的单层或多层。
源电极SE和漏电极DE形成在第三绝缘层IL3上。源电极SE经由第一接触孔CNT1与第一接触部OCT1直接接触，漏电极DE经由第二接触孔CNT2与第二接触部OCT2直接接触。
图4是示出根据本公开的示例性实施例的有机发光显示装置的框图。
如图4中所示，有机发光显示装置400包括信号控制电路100、扫描驱动电路200、数据驱动电路300和有机发光显示面板DP。
信号控制电路100接收输入图像信号(未示出)，并且将输入图像信号的数据格式转换成适合于数据驱动电路(DDC)300的规格，以产生图像数据RGB。信号控制电路100输出图像数据RGB以及各种控制信号DCS和SCS。
扫描驱动电路200从信号控制电路100接收扫描控制信号SCS。扫描控制信号SCS可以包括用于开始扫描驱动电路200的操作的垂直起始信号以及用于确定信号的输出时序的时钟信号。扫描驱动电路200产生多个扫描信号，并且向后面将描述的多条扫描线SL1至SLn顺序地输出多个扫描信号。此外，扫描驱动电路200响应于扫描控制信号SCS产生多个发光控制信号，并且向后面将描述的多条发光线EL1至ELn输出多个发光控制信号。
虽然图4示出了从一个扫描驱动单元200输出的多个扫描信号和多个发光控制信号，但是发明构思不限于此。在本公开的另一示例性实施例中，扫描驱动电路200仅输出扫描信号，有机发光显示装置400还可以包括单独的发光控制电路(未示出)，以输出发光控制信号。
数据驱动电路300从信号控制电路100接收图像数据RGB和数据控制信号DCS。数据驱动电路300将图像数据RGB转换成数据信号，并且向后面将描述的多条数据线DL1至DLm输出数据信号。数据信号是与图像数据RGB的灰度值对应的模拟电压。
有机发光显示面板DP包括多条扫描线SL1至SLn、多条发光线EL1至ELn、多条数据线DL1至DLm和多个像素PX。多条扫描线SL1至SLn在第一方向DR1上延伸，并且在与第一方向DR1基本垂直的第二方向DR2上布置。多条发光线EL1至ELn中的每条可以与多条扫描线SL1至SLn中的相应的扫描线基本平行地布置。多条数据线DL1至DLm与多条扫描线SL1至SLn绝缘并且交叉。
多个像素PX中的每个连接到多条扫描线SL1至SLn中的相应的扫描线、多条发光线EL1至ELn中的相应的发光线以及多条数据线DL1至DLm中的相应的数据线。多个像素PX中的每个接收电源电压ELVDD和具有比电源电压ELVDD低的电压电平的参考电压ELVSS。多个像素PX中的每个连接到电源电压ELVDD所施加到的电源线PL，以接收电源电压ELVDD。
多个像素PX中的每个包括有机发光二极管(未示出)和控制有机发光二极管的操作的电路(未示出)。电路可以包括多个薄膜晶体管(在下文中，被称作晶体管)和电容器。多个像素PX可以包括发射红颜色的红色像素、发射绿颜色的绿色像素和发射蓝颜色的蓝色像素。红色像素的有机发光二极管、绿色像素的有机发光二极管和蓝色像素的有机发光二极管可以分别包括具有彼此不同的材料的有机发光层。
多条扫描线SL1至SLn、多条发光线EL1至ELn、多条数据线DL1至DLm、电源线PL和多个像素PX可以通过多次光刻工艺形成在基体基底SUB上(在图3中示出)。多个绝缘层可以通过多次沉积工艺和多次涂覆工艺形成在基体基底SUB上。绝缘层可以包括有机层和/或无机层。此外，还可以在基体基底SUB上形成保护多个像素PX的包封层(未示出)。
图5是图4中示出的像素的等效电路图。
在图5中，连接到多条数据线DL1至DLm之中的第k数据线DLk和连接到多条扫描线SL1至SLn之中的第i扫描线SLi的第k×i像素PXki作为示例被示出。
第k×i像素PXki包括有机发光二极管ED和控制有机发光二极管ED的电路单元。电路单元可以包括第一晶体管T1、第二晶体管T2、第三晶体管T3和电容器Cst。在下文中，包括n型薄膜晶体管的第一晶体管T1至第三晶体管T3作为示例被示出。图5中示出的电路单元作为示例被示出，并且可以修改电路单元的构造。
第一晶体管T1至第三晶体管T3之中的第一晶体管T1是用于控制施加到有机发光二极管ED的驱动电流的驱动晶体管，第二晶体管T2和第三晶体管T3是用于控制第一晶体管T1的控制晶体管。控制晶体管可以包括多个晶体管。在本公开的示例性实施例中，包括第二晶体管T2和第三晶体管T3的控制晶体管作为示例被示出，但是不限于此。控制晶体管可以包括至少两个晶体管。此外，第二晶体管T2和第三晶体管T3的连接结构不限于此。
控制晶体管可以接收多个像素控制信号。施加到第k×i像素PXki的像素控制信号可以包括第i扫描信号Si、第k数据信号Dk和第i发光控制信号Ei。
第一晶体管T1包括第一控制电极、第一输入电极和第一输出电极。第一输入电极通过第三晶体管T3接收电源电压ELVDD。第一输出电极连接到有机发光二极管ED的阳极，并且向阳极供应电源电压ELVDD。有机发光二极管ED的阴极接收参考电压ELVSS。
第一控制电极连接到第一节点N1。使第一输出电极和有机发光二极管ED的阳极连接的节点是第二节点N2。
第二晶体管T2包括第二控制电极、第二输入电极和第二输出电极。第二控制电极连接到第i条扫描线SLi并且接收第i扫描信号Si，第二输入电极连接到第k数据线DLk并且接收第k数据信号Dk，第二输出电极连接到第一节点N1。当第二晶体管T2响应于第i扫描信号Si而导通时，第k数据信号Dk被施加到第一节点N1。第一晶体管T1根据第一节点N1的电势来控制供应到有机发光二极管ED的驱动电流。
第三晶体管T3包括第三控制电极、第三输入电极和第三输出电极。第三控制电极连接到第i发光线Eli并且接收第i发光控制信号Ei，第三输入电极连接到电源线PL，以接收电源电压ELVDD，第三输出电极连接到第一晶体管T1的第一输入电极。第三晶体管T3由第i发光控制信号Ei来切换，以向第一晶体管T1供应电源电压ELVDD。
存储电容器Cst设置在第一节点N1与第二节点N2之间。当第二晶体管T2响应于第i扫描信号Si而导通时，第k数据信号Dk被存储到存储电容器Cst。因此，在存储电容器Cst中充有的电压的电平可以根据第k数据信号Dk而改变。
图5中示出的第一晶体管T1至第三晶体管T3之中的第二晶体管T2可以是能够在低电源模式下执行存储器功能的存储器晶体管。在这种情况下，与图1中示出的存储器晶体管相似，第二晶体管T2可以包括由氧化物半导体形成的浮置栅极FGE。
在下文中，参照图6、图7A至图7G，将详细地示出第一晶体管T1和第二晶体管T2的结构和制造工艺。
图6是图5中示出的像素的剖视图，图7A至图7G是示出制造图6中示出的像素的工艺的剖视图。
参照图6，第一半导体层AL1形成在基体基底SUB上。
第一半导体层AL1包括第一沟道部CH1、第一接触部OCT1和第二接触部OCT2。第一沟道部CH1是第二晶体管T2的沟道区。第一半导体层AL1可以包括低温多晶硅。第一接触部OCT1和第二接触部OCT2可以是包括掺杂剂的区域。第一接触部OCT1和第二接触部OCT2可以是通过离子注入技术掺杂有n+掺杂剂或p+掺杂剂的掺杂区。第二晶体管T2的类型可以根据注入到第一接触部OCT1和第二接触部OCT2中的掺杂剂而改变。在本公开的示例性实施例中，第二晶体管T2可以是N型晶体管，但是根据本公开的第二晶体管T2的类型不应限于此。在第二晶体管T2是N型晶体管的情况下，第一接触部OCT1和第二接触部OCT2可以是n+掺杂区。第一沟道部CH1形成在第一接触部OCT1与第二接触部OCT2之间。
参照图6和图7A，在基体基底SUB上形成第一半导体材料(未示出)之后，使第一半导体材料图案化，以形成第一半导体图案。形成第一半导体图案的步骤可以包括使第一半导体材料结晶的步骤。
在第一半导体图案上形成绝缘材料(未示出)之后，通过使绝缘材料图案化来形成第一绝缘图案ILP1。绝缘材料可以包括氧化硅。
使用第一绝缘图案ILP1作为掩模将掺杂剂注入第一半导体图案中，以形成第一半导体层AL1。具体地，第一半导体图案图案包括第一区域至第三区域，第一绝缘图案ILP1设置在第一半导体图案的作为第一沟道部CH1的第二区域上，第一半导体图案的第一区域和第三区域不被第一绝缘图案ILP1覆盖。因此，使用掺杂剂掺杂第一区域和第三区域，然后形成了第一接触部OCT1和第二接触部OCT2。掺杂剂可以包括三价元素或五价元素。当掺杂剂包括三价元素时，可以形成P型半导体，当掺杂剂包括五价元素时，可以形成N型半导体。
因为第二区域被第一绝缘图案ILP1覆盖，所以第二区域在掺杂剂注入工艺期间不被掺杂。第二区域被定义为第一半导体层AL1的第一沟道部CH1。第一绝缘图案ILP1用作掺杂剂注入工艺的掩模。因此，第一区域和第二区域之间的边界与第一绝缘图案ILP1的第一侧对齐，第二区域和第三区域之间的边界与第一绝缘图案ILP1的第二侧对齐。
在图6和图7A中，示出了具有第一绝缘图案ILP1的结构，但是如图3中所示，可以省略第一绝缘图案ILP1。
如图6和图7B中所示，通过第一绝缘层IL1来覆盖第一半导体层AL1和第一绝缘图案ILP1。在本公开的示例性实施例中，第一绝缘层IL1可以包括氧化硅SiOx、氮化硅SiNx、氮氧化硅SiON、氟化氧化硅SiOF或氧化铝AlOx等的无机材料或者有机材料，并且包括具有上面材料中的至少一种的单层或多层。
在第一绝缘层IL1上形成第一氧化物半导体图案SOP1和第二氧化物半导体图案SOP2。第一氧化物半导体图案SOP1和第二氧化物半导体图案SOP2可以包括氧化物半导体。氧化物半导体可以包括诸如锌Zn、铟In、镓Ga、锡Sn、钛Ti等的金属氧化物或诸如锌Zn、铟In、镓Ga、锡Sn、钛Ti等的金属氧化物的组合。更具体地，氧化物半导体可以包括氧化锌ZnO、氧化锌锡ZTO、氧化锌铟ZIO、氧化铟In2O3、氧化钛TiO2、氧化铟镓锌IGZO、氧化铟锌锡IZTO等。
另一方面，第一氧化物半导体图案SOP1和第二氧化物半导体图案SOP2可以包括结晶的氧化物半导体。氧化物半导体的晶体可以具有竖直的方向性。
参照图6和图7C，通过第二绝缘层IL2覆盖第一氧化物半导体图案SOP1和第二氧化物半导体图案SOP2。第二绝缘层IL2可以包括氧化硅SiOx、氮化硅SiNx、氮氧化硅SiON、氟化氧化硅SiOF或氧化铝AlOx等的无机材料或者有机材料，并且包括具有上面材料中的至少一种的单层或多层。在第二绝缘层IL2上形成第一金属层ML1。
如图6和图7D中所示，通过经由掩模工艺使第二绝缘层IL2和第一金属层ML1图案化来形成第二绝缘图案ILP2和第一电极GAT1。使用第二绝缘图案ILP2和第一电极GAT1作为掩模对第一氧化物半导体图案SOP1和第二氧化物半导体图案SOP2执行氢等离子体处理工艺。在本公开的示例性实施例中，第一氧化物半导体图案SOP1包括第一区域至第三区域，第二绝缘图案ILP2和第一电极GAT1设置在第一氧化物半导体图案SOP1的第二区域上。因此，仅对第一氧化物半导体图案SOP1的被第一电极GAT1暴露的第一区域和第三区域执行氢等离子体处理。具体地，在第一金属层ML1的蚀刻工艺期间，可以将氢(H)或氢氧化物(OH)包括进第一氧化物半导体图案SOP1的第一区域和第三区域中。因此，第一氧化物半导体图案SOP1的第一区域和第三区域可以被还原为金属，以形成第三接触部OCT3和第四接触部OCT4。
这里，第一电极GAT1可以是第一晶体管T1(在图5中示出)的第一栅电极和存储电容器Cst(在图5中示出)的下电极。
第二区域被第一电极GAT1覆盖，并且在氢等离子体处理期间未掺杂氢。第一氧化物半导体图SOP1的第二区域是第二半导体层AL2的第二沟道部CH2。
此外，通过第一金属层ML1的蚀刻工艺将第二氧化物半导体图案SOP2还原成金属以形成浮置栅极FGE。为了改善浮置栅极FGE的金属性能，氢掺杂浓可以是大约1E+17/cm3或更大。
根据本公开，浮置栅极FGE包含具有高导电率的氧化物半导体。因为氧化物半导体具有相对宽的带隙并且可以使捕获位点比多晶硅更有用，所以氧化物半导体有利于载流子的充电。因此，当浮置栅极FGE包括氧化物半导体时，可以改善改变阈值电压以捕获或控制来自浮置栅极FGE的电荷。因此，可以改善第二晶体管T2的性能，从而当低功耗驱动时，可以使OLED显示装置400的功耗最小化。
通过在形成第二半导体层AL2的工艺中同时形成浮置栅极FGE，当浮置栅极FGE由氧化物半导体形成时，可以防止发生附加的工艺。
参照图6和图7E，通过第三绝缘层IL3覆盖第一电极GAT1和浮置栅极FGE，并且在第三绝缘层IL3上形成第二电极GAT2和第二栅电极GE2。第三绝缘层IL3可以包括氧化硅SiOx、氮化硅SiNx、氮氧化硅SiON、氟化氧化硅SiOF或氧化铝AlOx等的无机材料或者有机材料，并且包括具有上面材料中的至少一种的单层或多层。
第二电极GAT2是存储电容器Cst的上电极，并且在第三绝缘层IL3上面对第一电极GAT1。第二栅电极GE2被形成为在第三绝缘层IL3上面对浮置栅极FGE。
虽然附图中未示出，在第三绝缘层IL3上还设置图4中示出的第i条扫描线SLi、第i条发光线Eli和第(i-1)条发光线ELi-1。
参照图6和图7F，通过第四绝缘层IL4覆盖第二电极GAT2和第二栅电极GE2。第四绝缘层IL4可以包括无机材料和有机材料中的一种。
将第一接触孔CNT1和第二接触孔CNT2形成为通过第一绝缘层IL1至第四绝缘层IL4，以暴露第一接触部OCT1和第二接触部OCT2。此外，将第三接触孔CNT3和第四接触孔CNT4形成为通过第二绝缘层IL2至第四绝缘层IL4，以暴露第三接触部OCT3和第四接触部OCT4。
参照图6和图7G，在第四绝缘层IL4上形成第一晶体管T1的第一源电极SE1和第一漏电极DE1，在第四绝缘层IL4上形成第二晶体管T2的第二源电极SE2和第二漏电极DE2。第二晶体管T2的第二源电极SE2通过第一接触孔CNT1与第一接触部OCT1接触，第二漏电极DE2通过第二接触孔CNT2与第二接触部OCT2接触。第一晶体管T1的第一源电极SE1通过第三接触孔CNT3与第三接触部OCT3接触，第一漏电极DE1通过第四接触孔CNT4与第四接触部OCT4接触。
虽然图中未示出，在第四绝缘层IL4上还形成有第三晶体管T3(在图5中示出)的第三源电极和第三漏电极、第k数据线DLk(在图5中示出)和电源线PL(在图5中示出)。
在图中，示出了具有第二半导体层AL2的第一晶体管T1的结构，但是第三晶体管T3也可以包括第二半导体层AL2。
再次参照图6，通过第五绝缘层IL5覆盖第一源电极SE1和第二源电极SE2、第一漏电极DE1以及第二漏电极DE2。第五绝缘层IL5可以包括无机材料和有机材料中的一种。第五绝缘层IL5可以由有机绝缘材料形成，以提供平坦的表面。
将第五接触孔CNT5形成为通过第五绝缘层IL5，并且经由第五接触孔CNT5部分地暴露第一漏电极DE1。在第五绝缘层IL5上形成有机发光二极管ED的阳极AE。
在其上形成阳极AE的第五绝缘层IL5上设置像素限定层PDL。在像素限定层PDL中限定有开口OP，以暴露阳极AE的至少一部分。在阳极AE上设置有机发光层(未示出)，以与开口OP叠置。在有机发光层上设置阴极(未示出)。
虽然附图中未示出，但是可以在阴极上设置包封层，以覆盖有机发光二极管ED。包封层可以包括彼此交替地堆叠的多个无机层和多个有机层。
在根据本公开的OLED显示装置400中，具有存储器晶体管的结构的第二晶体管T2被示出为示例，但是不限于此。根据本发明构思的存储器晶体管可以用于液晶显示装置的像素。在下文中，参照图8和图9，将详细地描述使用于液晶显示装置的像素中的存储器晶体管的结构。
图8是示出根据本公开的示例性实施例的像素的电路图，图9是示出图8中示出的像素的剖视图。
参照图8和图9，根据本公开的示例性实施例的像素PXki包括像素晶体管TR、液晶电容器Clc和存储电容器Cst。像素晶体管TR包括连接到第i条栅极线GLi的栅电极、连接到第k条数据线DLk的源电极以及连接到液晶电容器Clc的漏电极。像素晶体管TR可以是具有浮置栅极FGE的存储器晶体管。在本公开的示例性实施例中，浮置栅极FGE可以由氧化物半导体形成。
像素晶体管TR响应于施加到第i条栅极线GLi的第i栅极电压Gi而导通，施加到第k条数据线DLk的第k数据电压Dk通过导通的像素晶体管TR被充电到液晶电容器Clc
参照图9，使用在液晶显示装置中的液晶显示面板500包括第一基底510、面对第一基底510的第二基底520以及设置在第一基底510与第二基底520之间的液晶层530。
第一基底510包括第一基体基底SUB1、设置在第一基体基底SUB1上的像素晶体管TR和液晶电容器Clc的第一电极PE。
设置在第一基体基底SUB1上的像素晶体管TR具有与图5中示出的第二晶体管T2基本相同的结构，所以将省略像素晶体管TR的详细描述，然而，因为图8中示出的像素具有一个晶体管，所以仅一个绝缘层(例如，第二绝缘层IL2)设置在浮置栅极FGE与栅电极GE之间，其它结构与第二晶体管T2几乎相同。
第一基底510包括第四绝缘层IL4，第六接触孔CNT6被形成为通过第四绝缘层IL4，以暴露像素晶体管TR的漏电极DE。像素电极PE设置在第四绝缘层IL4上。像素电极PE用作液晶电容器Clc的第一电极。
第二基底520包括第二基体基底SUB2和设置在第二基体基底SUB2上的共电极CE。共电极CE面对像素电极PE并且液晶层530置于共电极CE与像素电极PE之间，以形成使用液晶层530作为介电层的液晶电容器Clc。
为了改变像素晶体管TR的阈值电压Vth，在用于显示静止图像等的低功率驱动时间段期间，可以将低功率栅极电压施加到像素晶体管TR的栅电极。低功率栅极电压可以比正常栅极电压高。
在本公开的示例性实施例中，低功率栅极电压是在低功率驱动期间被施加到液晶显示装置的栅极线的电压，正常栅极电压是在正常驱动时间段期间被施加到液晶显示装置的栅极线的电压。
在低功率驱动期间，当将低功率栅极电压被施加到栅极线时，电荷被捕获在浮置栅极FGE中，因此像素晶体管TR的阈值电压Vth被偏移到正(+)侧。根据本公开，浮置栅极FGE包括具有高导电率的氧化物半导体。因为氧化物半导体具有相对宽的带隙并且可以使捕获位点比多晶硅更有用，所以氧化物半导体有利于载流子的充电。因此，当浮置栅极FGE包括氧化物半导体时，可以改善改变阈值电压Vth以捕获或者控制来自浮置栅极FGE的电荷的能力。
因此，可以改善像素晶体管TR的性能，从而减少在低功率驱动期间像素晶体管TR中产生的漏电流。因此，可以使液晶显示装置500的功耗最小化。
在此已经公开了示例实施例，尽管采用了具体术语，但仅以一般的和描述性的含义而非限制性的目的来使用和解释这些术语。在一些情况下，如对于自提交本申请时起的本领域普通技术人员而言将明显的是，结合具体实施例描述的特征、特性和/或元件可单独使用，或者可与结合其它实施例描述的特征、特性和/或元件组合使用，除非另有明确说明。因此，本领域技术人员将理解的是，在不脱离如权利要求中阐述的本发明的精神和范围的情况下，可以进行形式和细节上的各种变化。

Claims (10)

1.一种晶体管，所述晶体管包括：
半导体层，包括沟道部、第一接触部和第二接触部；
浮置栅极，面对所述半导体层的所述沟道部；
栅电极，面对所述浮置栅极；以及
源电极和漏电极，分别与所述第一接触部和所述第二接触部接触，其中，所述浮置栅极包括氧化物半导体。
2.根据权利要求1所述的晶体管，其中，所述半导体层包括多晶硅。
3.根据权利要求1所述的晶体管，其中，所述氧化物半导体包括氧化锌、氧化锌锡、氧化锌铟、氧化铟、氧化钛、氧化铟镓锌或氧化铟锌锡。
4.根据权利要求3所述的晶体管，其中，所述氧化物半导体包括具有1E+17/cm3或更大的掺杂浓度的所述氧化铟镓锌。
5.根据权利要求1所述的晶体管，所述晶体管还包括：
第一绝缘层，覆盖所述半导体层，其中，所述浮置栅极设置在所述第一绝缘层上；以及
第二绝缘层，覆盖所述浮置栅极，其中，所述栅电极设置在所述第二绝缘层上。
6.根据权利要求5所述的晶体管，其中，所述第一绝缘层和所述第二绝缘层中的每个包括包含氧化硅SiOx、氮化硅SiNx、氮氧化硅SiON、氟化氧化硅SiOF或氧化铝AlOx的无机材料或者有机材料。
7.根据权利要求5所述的晶体管，
其中，所述源电极通过第一接触孔与所述第一接触部接触，所述漏电极通过第二接触孔与所述第二接触部接触，
所述第一接触孔和所述第二接触孔被设置为通过所述第一绝缘层和所述第二绝缘层部分地暴露所述第一接触部和所述第二接触部。
8.一种显示装置，所述显示装置包括：
第一线；
第二线，与所述第一线不同；
开关晶体管，连接到所述第一线和所述第二线；以及
显示元件，连接到所述开关晶体管，
其中，所述开关晶体管包括：
第一半导体层，包括沟道部、第一接触部和第二接触部；
浮置栅极，面对所述第一半导体层的所述沟道部；
栅电极，面对所述浮置栅极；以及
源电极和漏电极，分别与所述第一接触部和所述第二接触部接触，其中，所述浮置栅极包括氧化物半导体。
9.根据权利要求8所述的显示装置，其中，所述显示元件包括具有阳极和阴极的有机发光二极管。
10.根据权利要求9所述的显示装置，所述显示装置还包括：
驱动晶体管，连接到所述有机发光二极管的阳极；以及
控制晶体管，控制所述驱动晶体管的操作。
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