WO2022165833A1 - 显示基板及其制备方法、显示装置 - Google Patents

显示基板及其制备方法、显示装置 Download PDF

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Publication number
WO2022165833A1
WO2022165833A1 PCT/CN2021/075975 CN2021075975W WO2022165833A1 WO 2022165833 A1 WO2022165833 A1 WO 2022165833A1 CN 2021075975 W CN2021075975 W CN 2021075975W WO 2022165833 A1 WO2022165833 A1 WO 2022165833A1
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WIPO (PCT)
Prior art keywords
sub
pixels
voltage signal
signal line
substrate
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PCT/CN2021/075975
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English (en)
French (fr)
Inventor
韩龙
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京东方科技集团股份有限公司
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Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2021/075975 priority Critical patent/WO2022165833A1/zh
Priority to US17/619,292 priority patent/US20240049542A1/en
Priority to GB2217867.7A priority patent/GB2610522A/en
Priority to CN202180000211.3A priority patent/CN115250637A/zh
Publication of WO2022165833A1 publication Critical patent/WO2022165833A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H10K59/1315—Interconnections, e.g. wiring lines or terminals comprising structures specially adapted for lowering the resistance
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0297—Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing
    • G09G2320/045—Compensation of drifts in the characteristics of light emitting or modulating elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a display substrate, a preparation method thereof, and a display device.
  • the refresh rate of the display device refers to the number of times the display screen can display new images per second.
  • the display screen can display 60 times per second at a refresh rate of 60Hz. new picture.
  • the refresh rate of the display device is relatively high, for example, 75Hz, 90Hz, 120Hz or higher, it can avoid blurring and smearing of the picture when displaying high-speed moving pictures, and improve picture quality and user visual experience.
  • a display panel in one aspect, includes a substrate, and a plurality of sub-pixels, a plurality of first data lines, a plurality of second data lines and a plurality of first voltage data lines disposed on the substrate.
  • a plurality of sub-pixels are arranged in an array.
  • a first data line and a second data line are disposed between every two adjacent columns of sub-pixels.
  • Each column of sub-pixels includes a plurality of first sub-pixels and second sub-pixels, and the first sub-pixels and the second sub-pixels are alternately arranged along the second direction; along the first direction, a column of sub-pixels is associated with a first data line and a second sub-pixel The data lines are adjacent, and the first data line and the second data line are located on both sides of the column of sub-pixels, and each first sub-pixel of the column of sub-pixels is electrically connected to its adjacent first data line. Each second sub-pixel of the pixel is electrically connected to its adjacent second data line.
  • each first voltage signal line on the substrate is located between the orthographic projections of the first data line and the second data line between two adjacent columns of sub-pixels on the substrate;
  • the voltage signal line is electrically connected to at least one column of sub-pixels;
  • the first voltage signal line includes: a first sub-voltage signal line and a second sub-voltage signal line, and the second sub-voltage signal line is set at the first sub-voltage
  • the side of the signal line close to the substrate is electrically connected to the first sub-voltage signal line, and the first sub-voltage signal line is arranged on the same layer as the first data line and the second data line .
  • the first subpixels and the second subpixels are alternately arranged along the first direction.
  • the display substrate further includes a first insulating layer disposed between the first sub-voltage signal line and the second sub-voltage signal line, the first insulating layer including a plurality of first sub-voltage signal lines vias.
  • the first sub-voltage signal line and the second sub-voltage signal line are electrically connected through at least one first via hole among the plurality of first via holes.
  • the part of the first data line adjacent to the first via hole is directed away from the first via hole.
  • the direction of the hole is curved to form a first curved portion.
  • a portion of the second data line adjacent to the first via hole is bent in a direction away from the first via hole to form a second bent portion.
  • the first curved portion and the second curved portion are opposite to form a receiving area.
  • the first sub-voltage signal line includes a conductive portion passing through the first via hole, and the conductive portion is located in the accommodating area.
  • the size of the conductive portion is larger than the width of the first sub-voltage signal line; and the size of the accommodating space is larger than the first space between two adjacent columns of sub-pixels The spacing between the portion of the data line that is not the first bend and the portion of the second data line that is not the second bend.
  • the distance between the conductive portion and the first curved portion is equal to or substantially equal to the distance between the conductive portion and the second curved portion.
  • the distance between the conductive portion and the first curved portion is equal to or approximately equal to the distance between the portion of the first data line that is not the first curved portion and the first curved portion.
  • the distance between parts of the non-conductive portion of the first sub-voltage signal line; and/or, along the first direction, the distance between the conductive portion and the second bent portion is equal to or approximately equal to, A distance between a portion of the second data line that is not the second curved portion and a portion of the non-conductive portion of the first sub-voltage signal line.
  • the first curved portion and the second data line A first connection part is arranged between the bending parts, and the first connection part is arranged in the same layer as the first sub-voltage signal line.
  • the display substrate further includes an anode layer and a first light emission control transistor disposed on the substrate, and the anode layer is disposed on a side of the first connection portion away from the substrate.
  • the first light emission control transistor includes an active layer including a first conductor portion, the first connection portion is electrically connected to the first conductor portion, and the anode layer.
  • the display substrate further includes a second connection portion.
  • the second connection part is arranged between the active layer of the first light-emitting control transistor and the first connection part, and is arranged in the same layer as the second sub-voltage signal line.
  • the second connection portion is electrically connected to the first conductor portion and the first connection portion.
  • the size of the first connecting portion is greater than or equal to the lengths of the first curved portion and the second curved portion.
  • the orthographic projection of the first connection portion on the substrate and the orthographic projection of the second connection portion on the substrate have an overlapping area.
  • the first via hole is located between two adjacent rows of sub-pixels and between two adjacent columns of sub-pixels.
  • the display substrate when the display substrate further includes the first connecting portion, along the second direction, two second connecting portions of the first connecting portion located adjacent to the first connecting portion The maximum dimensions of the two parts on both sides of the connection line at the center of a via hole are approximately equal.
  • each subpixel includes a second light emission control transistor and a capacitor.
  • the second sub-voltage signal line is electrically connected to the active layer of the second light-emitting control transistor.
  • the capacitor includes a first electrode plate located on the side of the film layer where the second sub-voltage signal line is located close to the substrate, and a second electrode plate located on the side of the first electrode plate close to the substrate.
  • the second sub-voltage signal line is also electrically connected to the first electrode plate.
  • the first plates of capacitors of a plurality of sub-pixels in each row of sub-pixels are electrically connected to each other to form a plurality of auxiliary conductive strips extending along the first direction, and the plurality of auxiliary conductive strips are formed. Interlaced with the orthographic projections of the plurality of first sub-voltage signal lines on the substrate to form a grid structure.
  • a display device including the display substrate as described above.
  • a method for manufacturing a display substrate includes: providing a substrate; forming a pixel driving circuit of a plurality of sub-pixels arranged in an array on the substrate, each column of sub-pixels includes a plurality of first sub-pixels and a plurality of second sub-pixels, the first sub-pixels The pixels and the second sub-pixels are alternately arranged along the second direction; a plurality of second sub-voltage signal lines are formed on the side of the pixel driving circuit of the plurality of sub-pixels away from the substrate, and each second sub-voltage signal line
  • the orthographic projection on the substrate is located between two adjacent columns of sub-pixels; a plurality of first data lines, a plurality of first data lines, a plurality of first data lines, a plurality of first data lines, a plurality of first data lines, a plurality of Two data lines and a plurality of first sub-voltage signal lines, one first sub-volt
  • the pixel driving circuit of each first sub-pixel of the column of sub-pixels is electrically connected to the adjacent first data line, and the pixel driving circuit of each second sub-pixel of the column of sub-pixels is connected to the adjacent second sub-pixel.
  • Data lines are electrically connected.
  • FIG. 1 is an equivalent circuit diagram of a 7T1C pixel driving circuit according to some embodiments
  • FIG. 2 is a signal timing diagram of the pixel driving circuit shown in FIG. 1;
  • FIG. 3 is a schematic structural diagram of a driving architecture according to some embodiments.
  • FIG. 4 is a signal timing diagram of the driving architecture shown in FIG. 3;
  • FIG. 5 is a schematic structural diagram of another driving system according to some embodiments.
  • FIG. 6 is a signal timing diagram of the driving system shown in FIG. 5;
  • FIG. 7 is a schematic top view of a display substrate according to some embodiments.
  • FIG. 8A to 8H are schematic top views of each film layer of the display substrate shown in FIG. 7;
  • Fig. 9A is a partial enlarged schematic view of region S1 in Fig. 7;
  • 9B is a schematic cross-sectional view taken along the dotted line XX' of the display substrate in FIGS. 7 and 9A;
  • 10A is a schematic structural diagram of a sub-pixel according to some embodiments.
  • 10B is a schematic structural diagram of another sub-pixel according to some embodiments.
  • FIG. 11 is an equivalent circuit diagram of a portion in the region S2 of the display substrate shown in FIG. 7;
  • FIG. 12 is a partially enlarged schematic view of the region S3 of the display substrate shown in FIG. 7;
  • FIG. 13 is a schematic diagram of another display substrate according to some embodiments.
  • FIG. 14 is a partially enlarged schematic view of the region S4 of the display substrate shown in FIG. 13;
  • 15A to 15F are schematic diagrams illustrating steps of a method for fabricating a display substrate according to some embodiments.
  • first and second are only used for descriptive purposes, and should not be construed as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Thus, a feature defined as “first” or “second” may expressly or implicitly include one or more of that feature.
  • plural means two or more.
  • the expressions “coupled” and “connected” and their derivatives may be used.
  • the term “connected” may be used in describing some embodiments to indicate that two or more components are in direct physical or electrical contact with each other, or to indicate that two or more components are in indirect physical contact with each other connection or electrical connection.
  • At least one of A, B, and C has the same meaning as “at least one of A, B, or C”, and both include the following combinations of A, B, and C: A only, B only, C only, A and B , A and C, B and C, and A, B, and C.
  • a and/or B includes the following three combinations: A only, B only, and a combination of A and B.
  • multiple in terms such as “plurality”, “plurality”, “multiple columns” and “multiple rows” in this disclosure refers to two or more in number.
  • the display device When the display device operates at a higher refresh rate (eg, 75 Hz, 90 Hz, 120 Hz or higher), the displayed picture quality and the user's visual experience can be improved.
  • a higher refresh frequency will shorten the data writing and compensation time of each sub-pixel in the display device, which may lead to insufficient charging rate of each sub-pixel and a decrease in the compensation effect of the threshold voltage, which will reduce the display effect of the display device. reduce.
  • the display device includes a plurality of sub-pixels, each sub-pixel has a pixel driving circuit with the 7T1C structure, and the pixel driving circuit includes seven transistors (the first transistors T1 to seventh transistor T7) and a capacitor Cst.
  • the seven transistors can be P-type transistors, that is, when the gate receives a low-level signal, it is turned on, and when it receives a high-level signal, it is turned off; the seven transistors can also be N-type transistors, that is, when the gate receives a low-level signal, it is turned off; It is turned on when a high-level signal is received, and it is turned off when a low-level signal is received.
  • the electrical connection point of the second electrode of the first transistor T1, the second electrode plate B1 of the capacitor Cst, and the gate of the third transistor T3 is referred to as the first node N1, and the first node N1 , the voltages of the second plate B1 of the capacitor Cst and the gate of the third transistor T3 are equal; connect the voltage between the second pole of the fifth transistor T5, the second pole of the fourth transistor T4 and the first pole of the third transistor T3
  • the electrical connection point is referred to as the second node N2; the electrical connection node of the third transistor T3, the second transistor T2 and the sixth transistor T6 is referred to as the third node N3.
  • the channel width to length ratio of the driving transistor is usually larger than that of other switching transistors, that is, the channel width to length ratio of the third transistor T3 is usually greater than that of the first transistor T1 and the second transistor.
  • Channel width to length ratios of T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 are usually greater than that of the first transistor T1 and the second transistor.
  • the light-emitting brightness of the light-emitting device E corresponding to each sub-pixel is related to the magnitude of the driving current I flowing therethrough.
  • the driving current I is related to the source and gate voltage difference Vgs of the driving transistor and the threshold voltage Vth of the driving transistor, that is, when the voltage difference Vgs is constant, each light-emitting
  • the light-emitting brightness of the device E is mainly affected by the threshold voltage Vth of the corresponding driving transistor.
  • the threshold voltage Vth of the driving transistor in the sub-pixels of the display device is not equal, for example, with the increase of the working time, the threshold voltage Vth of the driving transistor will occur.
  • the display device may exhibit uneven display brightness.
  • the transistors included in the pixel driving circuit are P-type transistors as an example, that is, the first transistor T1 to the seventh transistor T7 are turned on when the signal received by their gates is low, and the signals received by their gates are high. Usually due.
  • the gate of the first transistor T1 is electrically connected to the reset signal terminal RESET, the first electrode is electrically connected to the initialization voltage signal terminal INIT, and the second electrode is electrically connected to the first node N1.
  • the gate of the second transistor T2 is electrically connected to the scan signal terminal GATE, the first electrode is electrically connected to the third node N3, and the second electrode is electrically connected to the first node N1.
  • the gate of the third transistor T3 is electrically connected to the first node N1, the first electrode is electrically connected to the second node N2, the second electrode is electrically connected to the third node N3, and the gate of the fourth transistor T4 is electrically connected to the scan signal terminal GATE connection, the first pole is electrically connected to the data signal terminal DATA, and the second pole is electrically connected to the second node N2.
  • the gate of the fifth transistor T5 is electrically connected to the light-emitting signal terminal EM, the first electrode is electrically connected to the first voltage signal terminal VDD, and the second electrode is electrically connected to the second node N2.
  • the gate of the sixth transistor T6 is electrically connected to the light-emitting signal terminal EM, the first electrode is electrically connected to the third node N3, and the second electrode is electrically connected to the anode of the light-emitting device E of the sub-pixel.
  • the gate of the seventh transistor T7 is electrically connected to the reset signal terminal RESET, the first electrode is electrically connected to the initialization voltage signal terminal INIT, and the second electrode is electrically connected to the anode of the light emitting device E of the sub-pixel.
  • the first plate A1 of the capacitor Cst is electrically connected to the first voltage signal terminal VDD, and the second plate B1 is electrically connected to the first node N1.
  • the anode of the light-emitting device E of the sub-pixel is electrically connected to the above-mentioned pixel driving circuit, and the cathode is electrically connected to the second voltage signal terminal VSS.
  • the working process of the pixel driving circuit of the 7T1C is introduced in conjunction with the signal timing diagram shown in FIG. 2.
  • the working process of the pixel driving circuit includes a reset phase P1, a writing and compensation phase P2, and a light-emitting phase P3 .
  • the reset signal Vre of the reset signal terminal RESET transmitted to the gate of the first transistor T1 and the gate of the seventh transistor T7 is at a low level, and the first transistor T1 and the seventh transistor T7 are turned on.
  • the first transistor T1 transmits the initialization voltage signal Vinit from the initialization voltage signal terminal INIT to the first node N1 to connect the second plate B1 of the capacitor Cst and the gate of the third transistor T3 (also referred to as the driving transistor T3 )
  • the voltage of the second plate B1 is reset, and the voltage of the second plate B1 is equal to the voltage Vi of the initialization voltage signal Vinit.
  • the seventh transistor T7 transmits the initialization voltage signal Vinit from the initialization voltage signal terminal INIT to the anode of the light emitting device E to reset the anode voltage of the light emitting device E.
  • the initialization voltage signal Vinit is at a low level in the reset phase P1, and the voltage of the first node N1 is at a low voltage, so the third transistor T3 whose gate is electrically connected to the first node N1 is turned on.
  • the initialization voltage signal Vinit may be a constant low voltage signal.
  • the reset signal Vre is at a high level, and the first transistor T1 and the seventh transistor T7 are turned off.
  • the voltage of the first node N1 is equal to the voltage of the second plate B1 of the capacitor Cst, that is, the voltage of the first node N1 is still a low voltage, and the third transistor T3 is maintained in an on state.
  • the scan signal Vgate of the scan signal terminal GATE transmitted to the gate of the fourth transistor T4 (may be referred to as the writing transistor T4) and the gate of the second transistor T2 (may be referred to as the compensation transistor T2) is at a low level, and the fourth transistor T4 and the second transistor T2 is turned on.
  • the fourth transistor T4 transmits the data signal Vdata from the data signal terminal DATA to the third transistor T3.
  • the data signal Vdata is transferred to the second transistor T2 through the turned-on third transistor T3, and then transferred to the first node N1 through the turned-on second transistor T2, so as to be written to the capacitor Cst.
  • the process in which the data signal Vdata is written to the capacitor Cst is actually the charging process of the second plate B1 of the capacitor Cst (ie, the process in which the voltage of the second plate B1 gradually increases).
  • the voltage of the first node N1 increases from In one stage (ie, the reset stage P1 ), Vi gradually increases until the voltage of the first node N1 rises to Vdata+Vth, and the third transistor T3 is turned off, where Vth is the threshold voltage value of the third transistor T3 .
  • the voltage of the second plate B1 of the capacitor Cst is equal to Vdata+Vth, so that the threshold voltage value Vth of the third transistor T3 is compensated for the data signal written in the capacitor Cst.
  • duration 1H of the active level of the scan signal Vgate (that is, the level at which the corresponding transistor is turned on) is the time required for a row of sub-pixels to complete the writing of the data signal Vdata.
  • the light-emitting signal Vem transmitted from the light-emitting signal terminal EM to the gate of the fifth transistor T5 and the gate of the sixth transistor T6 is at a low level, and the fifth transistor T5 and the sixth transistor T6 are turned on.
  • the source voltage Vs of the third transistor T3 is equal to the first voltage Vdd of the first voltage signal terminal VDD
  • the gate voltage Vg of the third transistor T3 is equal to Vdata+Vth, where the first voltage Vdd is greater than Vdata+Vth, so the third transistor T3 is turned on. In this way, a current path is formed between the first voltage signal terminal VDD and the second voltage signal terminal VSS, so that the light emitting device E can emit light.
  • the magnitude of the driving current I has nothing to do with the threshold voltage value Vth of the third transistor T3, so that the influence of the threshold voltage shift of the third transistor T3 on the driving current I can be avoided, and the luminance of each sub-pixel in the display device can be more uniform.
  • the time of each frame is shortened, resulting in a corresponding shortening of the writing and compensation stage P2 in one frame, that is, As a result, the duration of the active level of the scan signal is shortened.
  • This may cause the data writing time of the sub-pixels of the display device (that is, the charging time of the sub-pixels) and the threshold voltage compensation time to be short, so that the charging rate of the sub-pixels is insufficient, and the threshold voltage compensation effect is poor, which affects the picture of the display device. quality and user visual experience.
  • a driving method in which two data lines DL are arranged to jointly provide the data signal Vdata to a column of sub-pixels can be used to solve the problem.
  • FIGS. 3 to 6 the above-mentioned display device with a 7T1C pixel driving circuit, and the scheme of adopting this driving method will be exemplarily introduced.
  • the display device includes a plurality of sub-pixels PX, a plurality of data lines DL, and a plurality of gate lines GL (eg, GL1 to GL4 ), and the sub-pixels PX may be arranged in an array.
  • Each column of sub-pixels corresponds to two data lines DL (eg, DL1 to DL8 ), and the two data lines DL are respectively disposed on the left and right sides of the column of sub-pixels.
  • each adjacent two sub-pixels PX are respectively electrically connected to different data lines DL in the data lines DL on the left and right sides, that is, along the extension direction of the sub-pixels in the column, the sub-pixels located in the same column are electrically connected to each other.
  • the pixels PX are alternately electrically connected to the data lines DL on the left and right sides.
  • the sub-pixels located in the same row can be electrically connected to the same gate line GL, where the gate line GL can provide the scan signal Vgate to the row of sub-pixels electrically connected to it, so that the data signal Vdata from the data line DL is transmitted into the corresponding sub-pixels.
  • the writing of the data signal Vdata is realized.
  • the sub-pixels PX located in the same row may be alternately electrically connected to the data lines DL on the left and right sides thereof (as shown in FIG. 3 and FIG. 5 ), or both It is electrically connected to the data line DL on its left side or its right side.
  • the display device may further include a plurality of source driving signal lines S (eg, S1 to S4 ) and a source driver 100 , and the plurality of source driving signal lines S are electrically connected to the source driver 100 .
  • the source driver 100 is used for providing the data signal Vdata of the image to be displayed by the display device, and these data signals Vdata can be provided to each sub-pixel PX through the source driving signal line S and the data line DL.
  • Each adjacent plurality of data lines DL are electrically connected to the same source driving signal line S, in this way, the source driver 100 can pass the source driving signal line S to a plurality of data lines that are electrically connected to the source driving signal line S
  • the line DL transmits the data signal Vdata, so that the number of interfaces provided on the source driver 100 for outputting the data signal Vdata can be reduced.
  • a switch SW is disposed between each data line DL and its corresponding source driving signal line S, so that the source driving signal line S can be time-division multiplexed by controlling the opening and closing of the corresponding switch SW.
  • control electrodes of the switches SW corresponding to the same source driving signal line S and located on the left side of the sub-pixels in one column of the switches SW are all electrically connected to the same control signal line MUX (for example, MUX1 or MUX2 in FIG. 3 ).
  • the control signal line MUX can control the opening and closing of the switch SW corresponding to the data line DL, so as to control the transmission of the data signal Vdata from the source driving signal line S to the specific data line DL in a certain frame.
  • the data signal Vdata is written into the corresponding sub-pixel PX.
  • the switch SW here may comprise N-type or P-type transistors.
  • the switch SW includes an N-type transistor, the switch SW is turned on when the signal from the control signal line MUX is at a high level, and turned off when the signal is at a low level.
  • the switch SW includes a P-type transistor, the switch SW is turned on when the signal from the control signal line MUX is at a low level, and turned off when the signal is at a high level.
  • the structure of the display device shown in FIG. 2 and FIG. 4 is taken as an example below to introduce the driving process of the display device, and the pixel driving circuit in the sub-pixel in the display device can refer to FIG. 1 .
  • the second transistor T2 and the fourth transistor T4 in the pixel driving circuit, and the switch SW are P-type transistors as an example, and along the extension direction of a row of sub-pixels, the sub-pixels PX located in the same row are alternately located on the left and right sides of the sub-pixels PX in the same row.
  • the data line DL is electrically connected.
  • every two adjacent data lines DL are electrically connected to the same source driving signal line S.
  • the source driving signal line S1 is electrically connected to the data line DL1 and the data line DL2, that is to say, the source driver 100 can connect the source driving signal line S1, the data line DL1 and the data line DL2 to the first column sub-pixel PC1 through the source driving signal line S1, the data line DL1 and the data line DL2.
  • a data signal Vdata is provided.
  • the source driving signal line S2 is electrically connected to the data line DL3 and the data line DL4, and the source driver 100 can provide data signals to the second column sub-pixel PC2 through the source driving signal line S2, the data line DL3 and the data line DL4 Vdata;
  • the source drive signal line S3 is electrically connected to the data line DL5 and the data line DL6,
  • the source drive signal line S4 is electrically connected to the data line DL7 and the data line DL8, and the source driver 100 can pass the source drive signal line S4, data line The line DL7 and the data line DL8 provide the data signal Vdata to the fourth column sub-pixel PC4.
  • the gate of the thin film transistor is electrically connected to the control signal line MUX1.
  • the gates of the thin film transistors in the switches SW electrically connected to the data lines DL1, DL3, DL5 and DL7 are all electrically connected to the control signal line MUX1, and the thin film transistors in the switches SW corresponding to the data lines DL2, DL4, DL6 and DL8 The gates are all electrically connected to the control signal line MUX2.
  • the control signal Vumx1 transmitted via the control signal line MUX1 is at a low level, and the thin film transistor in the switch SW electrically connected to the control signal line MUX1 is turned on; via the control The control signal Vumx2 transmitted by the signal line MUX2 is at a high level, and the thin film transistor in the switch SW electrically connected to the control signal line MUX2 is turned off.
  • the scan signal Vgate1 transmitted via the scan signal line GL1 is at a low level, and the second transistor T2 and the fourth transistor T4 in each sub-pixel PX of the first sub-pixel row PR1 are turned on; the scan signal transmitted via the scan signal line GL2 Vgate2 is at a high level, and the second transistor T2 and the fourth transistor T4 in each sub-pixel PX in the second sub-pixel row PR2 are turned off.
  • the data signal Vdata transmitted via the source driving signal line S1 is written in the sub-pixels located in the first row sub-image PR1 and the first column sub-pixel PC1
  • the data signal Vdata transmitted via the source driving signal line S3 is written in It is located in the sub-pixels of the sub-image PR1 in the first row and the sub-pixel PC3 in the third column.
  • the control signal Vumx1 transmitted through the control signal line MUX1 is at a high level, and each switch SW electrically connected to the control signal line MUX1 is turned off; the control signal Vumx2 transmitted through the control signal line MUX2 is at a low level , each switch SW electrically connected to the control signal line MUX2 is turned on.
  • the scan signal Vgate1 transmitted through the scan signal line GL1 and the scan signal Vgate2 transmitted through the scan signal line GL2 are both low level, located in the second row of the sub-pixels PR1 and the sub-pixels PR2 in the second row of the sub-pixels PX. Both the transistor T2 and the fourth transistor T4 are turned on.
  • the data signal Vdata transmitted via the source driving signal line S1 is written into the sub-pixels located in the second row sub-image PR2 and the first column sub-image PC1 by the data line DL2, and the data signal Vdata transmitted via the source driving signal line S2
  • the sub-pixels located in the first row sub-image PR1 and the second column sub-image PC2 are written by the data line DL4, and the data signal Vdata transmitted through the source driving signal line S3 is written by the data line DL6 in the second row sub-image PR2,
  • the data signal Vdata transmitted via the source driving signal line S4 is written into the sub-pixels of the first row sub-image PR1 and the fourth column sub-image PC4 by the data line DL8.
  • the duration of the active level of the scan signal Vgate of the sub-pixel PX is 2H, that is, the duration of the active level of the scan signal Vgate of the sub-pixel PX is the same as the completion data of the two rows of sub-pixels.
  • the time required to write the signal Vdata is equal. In this way, the time of the writing and compensation phase P2 can be increased, so that the charging time of the sub-pixels PX is sufficient, and the threshold voltage compensation effect can be improved, so that the display effect of the display device at a high refresh frequency can be improved.
  • every four adjacent data lines DL are electrically connected to the same source driving signal line S.
  • the source driving signal line S1 is electrically connected to the data lines DL1 to DL4
  • the source data line S2 is electrically connected to the data lines DL5 to DL8.
  • each of the data lines DL with serial number 1 is electrically connected to the thin film transistors in the switches SW.
  • the gates are all electrically connected to the control signal line MUX1
  • the gates of the thin film transistors in each switch SW electrically connected to the data line DL with the serial number 2 are all electrically connected to the control signal line MUX2, and the data line with the serial number of 3 is electrically connected.
  • the gates of the thin film transistors in each switch SW electrically connected to DL are all electrically connected to the control signal line MUX3, and the gates of the thin film transistors in each switch SW electrically connected to the data line DL with the serial number 4 are all electrically connected to the control signal line.
  • the source driver 100 can transmit data signals to the four data lines DL electrically connected to the source driving signal line S through the same source driving signal line S Vdata, so that the corresponding four-column sub-pixels realize the writing of the data signal Vdata.
  • the control signal Vumx1 transmitted via the control signal line MUX1 is at a low level, and the thin film transistor in the switch SW electrically connected to the control signal line MUX1 is turned on; via
  • the control signals Vumx2 to Vumx4 transmitted by the control signal lines MUX2 to MUX4 are all high level, and the thin film transistors in the switches SW electrically connected to the control signal lines MUX2 to MUX4 are all turned off.
  • the scan signal Vgate1 transmitted via the scan signal line GL1 is at a low level, and the second transistor T2 and the fourth transistor T4 in each sub-pixel PX in the first sub-pixel row PR1 are turned on; the scan signal Vgate1 transmitted via the scan signal lines GL2 to GL4
  • the scan signals Vgate2 to Vgate4 are all high level, and the second transistor T2 and the fourth transistor T4 in each of the sub-pixels PX located in the second pixel row PR2 to the fourth pixel row PR4 are both turned off.
  • the data signal Vdata transmitted via the source driving signal line S1 is written in the sub-pixels located in the first row sub-image PR1 and the first column sub-pixel PC1
  • the data signal Vdata transmitted via the source driving signal line S2 is written in It is located in the sub-pixels of the sub-image PR1 in the first row and the sub-pixel PC3 in the third column.
  • the control signal Vumx2 transmitted via the control signal line MUX2 is at a low level, and the thin film transistor in the switch SW electrically connected to the control signal line MUX2 is turned on;
  • the control signals Vumx1 , Vumx3 and Vumx4 are all at a high level, and the thin film transistors in the switches SW electrically connected to the control signal lines MUX1 , MUX3 and MUX4 are all turned off.
  • the scan signals Vgate1 and Vgate2 transmitted via the scan signal lines GL1 and GL2 are at a low level, and the second transistor T2 and the fourth transistor T4 in each sub-pixel PX of the first sub-pixel row PR1 and the second sub-pixel row PR2 are turned on.
  • the scan signals Vgate3 and Vgate4 transmitted via the scan signal lines GL3 and GL4 are both high level, the second transistor T2 and the fourth transistor T4 in each sub-pixel PX of the third pixel row PR3 and the fourth pixel row PR4 all expire.
  • the data signal Vdata transmitted via the source driving signal line S1 is written into the sub-pixels located in the sub-image PR2 in the second row and the sub-pixel PC1 in the first column
  • the data signal Vdata transmitted via the source driving signal line S2 is written in It is located in the sub-pixels of the sub-image PR2 in the second row and the sub-pixel PC3 in the third column.
  • the control signal Vumx3 transmitted via the control signal line MUX3 is at a low level, and the thin film transistor in the switch SW electrically connected to the control signal line MUX3 is turned on;
  • the control signals Vumx1 , Vumx2 and Vumx4 are all at a high level, and the thin film transistors in the switches SW electrically connected to the control signal lines MUX1 , MUX2 and MUX4 are all turned off.
  • the scan signals Vgate1 to Vgate3 transmitted through the scan signal lines GL1 to GL3 are at low level, and the second transistor T2 and the fourth transistor T4 in each of the subpixels PX in the first to third subpixel rows PR1 to PR3 are turned on.
  • the scan signal Vgate4 transmitted via the scan signal line GL4 is at a high level, and both the second transistor T2 and the fourth transistor T4 in each sub-pixel PX in the fourth pixel row PR4 are turned off.
  • the data signal Vdata transmitted via the source driving signal line S1 is written into the sub-pixels located in the sub-image PR2 in the second row and the sub-pixel PC2 in the second column, and the data signal Vdata transmitted via the source driving signal line S2 is written in It is located in the sub-pixels of the sub-image PR2 in the second row and the sub-pixel PC4 in the fourth column.
  • the control signal Vumx4 transmitted via the control signal line MUX4 is at a low level, and the thin film transistor in the switch SW electrically connected to the control signal line MUX4 is turned on; the control signals transmitted via the control signal lines MUX1 to MUX3 Vumx1 to Vumx3 are all at a high level, and the thin film transistors in the switches SW electrically connected to the control signal lines MUX1 to MUX3 are all turned off.
  • the scan signals Vgate1 to Vgate4 transmitted through the scan signal lines GL1 to GL4 are all low level, and the second transistor T2 and the fourth transistor T4 in each sub-pixel PX of the first sub-pixel row PR1 to the fourth sub-pixel row PR4 are turned on.
  • the data signal Vdata transmitted via the source driving signal line S1 is written into the sub-pixels located in the first row sub-image PR2 and the second column sub-pixel PC2 and the sub-pixels located in the third row sub-image PR3 and the second column sub-pixel PC2
  • the data signal Vdata transmitted via the source driving signal line S2 is written into the sub-pixels located in the first row of sub-images PR1 and the fourth column of sub-pixels PC4 and the sub-pixels located in the third row of sub-images PR3 and the fourth column of sub-pixels PC4 middle.
  • the duration of the active level of the scanning signal Vgate of the sub-pixel PX is 2H, which can also increase the time of the writing and compensation phase P2, so that the charging time of the sub-pixel PX is sufficient, the threshold voltage compensation effect is improved, and the display can be improved.
  • the data signal Vdata is not the data signal actually required in its light-emitting phase.
  • the duration of the active level of the scan signal is 2H, before the active level of the scan signal Vgate3 corresponding to the above two sub-pixels ends, the two sub-pixels will be written into a new data signal Vdata again.
  • the incoming data signal Vdata is the data signal required for the light-emitting stage.
  • the display device adopts the above-mentioned driving method of jointly providing the data signal Vdata to a column of sub-pixels through two data lines DL
  • the number of data lines DL provided in the display device will be doubled, so that the distance between the data lines DL will be doubled. becomes smaller, which may lead to a larger parasitic capacitance between adjacent data lines DL.
  • the larger parasitic capacitance will cause crosstalk between the data signals Vdata transmitted by the adjacent data lines DL, which affects the data writing and threshold voltage compensation of the sub-pixels, thereby possibly reducing the display effect of the display device.
  • the display substrate 200 includes a substrate 10 , a plurality of first data lines 21 and a plurality of second data lines 22 disposed on the substrate 10 , and a plurality of second data lines 22 disposed on the substrate 10 . , a plurality of sub-pixels arranged in an array. A first data line 21 and a second data line 22 are disposed between every two adjacent columns of sub-pixels.
  • each column of sub-pixels includes a plurality of first sub-pixels 31 and a plurality of second sub-pixels 32 .
  • the first direction OU is defined as the direction perpendicular or substantially perpendicular to the extension direction of a column of sub-pixels, that is, the first direction OU is the row direction in which a plurality of sub-pixels are arranged in an array.
  • the direction in which the direction is parallel or substantially parallel is the second direction OV, that is, the second direction OV is the column direction in which a plurality of sub-pixels are arranged in an array.
  • first subpixels 31 and the second subpixels 32 are alternately arranged.
  • a column of sub-pixels is adjacent to a first data line 21 and a second data line 22, and the first data line 21 and the second data line 22 are respectively located on two sides of the column of sub-pixels.
  • Each first subpixel 31 of the column of subpixels is electrically connected to the first data line 21 adjacent thereto, and each second subpixel 32 of the column of subpixels is electrically connected to the second data line 22 adjacent thereto.
  • the display substrate 200 further includes a first voltage signal line 40 disposed on the substrate 10 , the orthographic projection of each first voltage signal line 40 on the substrate 10 is a first data line located between two adjacent columns of sub-pixels Between the orthographic projections of the second data lines 21 and the second data lines 22 on the substrate 10, each of the first voltage signal lines 40 is electrically connected to at least one column of sub-pixels. Exemplarily, between the orthographic projections of the first data line 21 and the second data line 22 on the substrate 10 between every two adjacent columns of sub-pixels, there is a first voltage signal line 40 on the substrate 10. Orthographic projection.
  • a film layer such as an inorganic buffer layer 11 may also be disposed between the substrate 10 and the plurality of sub-pixels.
  • the inorganic buffer layer 11 may be a single-layer structure or a multi-layer stack structure, for example, a stack structure in which inorganic film layers and organic film layers are alternately arranged.
  • FIG. 11 is an equivalent circuit diagram of the portion of the display substrate 200 shown in FIG. 7 located in the area S2, where the display substrate 200 includes two first sub-pixels 31 and two second sub-pixels 32 arranged in a matrix in the area S2 Take an example to illustrate.
  • Each of the first sub-pixels 31 and each of the second sub-pixels 32 has a pixel driving circuit of a 7T1C structure, and the pixel driving circuit includes a first transistor T1 to a seventh transistor T7 and a capacitor Cst.
  • the electrical connection relationship between the components in the pixel driving circuit and the working process of the driving circuit can be referred to the above description, which will not be repeated here.
  • the display panel 200 includes an active layer LA , a first gate metal layer L G1 , a second gate metal layer LG2 and a first source-drain metal layer L SD1 sequentially disposed on the substrate 10 .
  • the area SP in FIG. 8D is an area corresponding to a sub-pixel, that is, the structure in the area SP in FIG. 8D is a minimum repeating unit of the display substrate 200 , here and below, one sub-pixel corresponds to The structure in the area SP of . is introduced as an example.
  • the active layer LA includes the active layer 71 of the first transistor T1, the active layer 72 of the second transistor T2, the active layer 73 of the third transistor T3, and the active layer 73 of the fourth transistor T4.
  • the first gate metal layer L G1 includes the gate G1 of the first transistor T1 , the gate G2 of the second transistor T2 , the gate G3 of the third transistor T3 , and the gate of the fourth transistor T4 G4, the gate G5 of the fifth transistor T5, the gate G6 of the sixth transistor T6, and the gate G7 of the seventh transistor T7.
  • the first gate metal layer LG1 further includes the second plate B1 of the capacitor Cst, the reset signal line RL, the gate line GL and the light emitting signal line EML.
  • the reset signal line RL is configured to transmit the reset signal Vre from the reset signal terminal RESET to the corresponding sub-pixel
  • the gate line GL is configured to transmit the scan signal Vgate from the scan signal terminal GATE to the corresponding sub-pixel, and emits light
  • the signal line EML is configured to transmit the light-emitting signal Vem from the light-emitting signal terminal EM to the corresponding sub-pixel.
  • the overlapping portion of the first gate metal layer L G1 and the orthographic projection of the active layer 71 of the first transistor T1 on the substrate 10 can be used as the gate G1 of the first transistor T1, and the first gate metal layer L
  • the overlapping portion of the orthographic projection of G1 and the active layer 72 of the second transistor T2 on the substrate 10 can be used as the gate G2 of the second transistor T2, the first gate metal layer L G1 and the active layer 73 of the third transistor T3
  • the overlapping portion of the orthographic projection on the substrate 10 can be used as the gate G3 of the third transistor T3, the overlapping portion of the orthographic projection of the first gate metal layer LG1 and the active layer 74 of the fourth transistor T4 on the substrate 10 Can be used as the gate G4 of the fourth transistor T4, the overlapping part of the orthographic projection of the first gate metal layer L G1 and the active layer 75 of the fifth transistor T5 on the substrate 10 can be used as the gate G5 of the fifth transistor T5,
  • the second gate metal layer LG2 includes the first plate A1 of the capacitor Cst, the initialization voltage signal line IL, and the shielding portion 102 .
  • the initialization voltage signal line is configured to transmit the initialization voltage signal Vin from the initialization voltage signal terminal INIT to the corresponding sub-pixel.
  • the first source-drain metal layer L SD1 includes the above-mentioned first signal lines 21 and second signal lines 22 , and along the first direction OU, the first signal lines 21 and the second signal lines 22 are alternately arranged .
  • the fourth transistor T4 of the first sub-pixel 31 is electrically connected to the same first data line 21
  • the fourth transistor T4 of the second sub-pixel 32 is electrically connected to the same second data line 22 . That is, the first sub-pixel 31 receives the data signal Vdata through the first data line 21
  • the second sub-pixel 32 receives the data signal Vdata through the second data line 22 .
  • the first electrodes of the fifth transistors T5 of the sub-pixels located in the same column are electrically connected to the first voltage signal terminal VDD through the same first voltage signal line 40 .
  • the first voltage signal line 40 can be used to transmit the first voltage signal Vdd from the first voltage signal terminal VDD to the sub-pixels electrically connected thereto.
  • the first voltage signal Vdd is a constant voltage signal, such as a constant voltage signal in FIG. 11 . low voltage signal.
  • the gates of the second transistor T2 and the fourth transistor T4 of the sub-pixels located in the same row are electrically connected to the same-level scan signal terminal GATE (for example, the Nth-level scan signal terminal GATE N or the (N+1)th scan signal terminal GATE) through the same gate line GL. stage scan signal terminal GATA N+1 ).
  • the gates of the fifth transistor T5 and the sixth transistor T6 of the sub-pixels located in the same row are electrically connected to the same level light emitting signal terminal EM (for example, the Nth level light emitting signal terminal EM N or the (N+1th level) through the same light emitting signal line EML. )
  • the light-emitting signal terminal EM N+1 The light-emitting signal terminal EM N+1 ).
  • the gates of the first transistor T1 and the seventh transistor T7 of the sub-pixels located in the same row are electrically connected to the upper-stage scanning signal terminal GATE through the same reset signal line RL.
  • the scan signal Vgate output by the previous scan signal terminal GATE is used as the reset signal Vre, that is, the previous scan signal terminal GATE is used as the reset signal terminal RESET of the current sub-pixel.
  • the scan signal Vgate output from the Nth-level scan signal terminal GATE N serves as a sub-pixel electrically connected to the (N+1)th-level scan signal terminal GATA N+1 by the second transistor T2 and the fourth transistor T4 the reset signal Vre.
  • the first electrodes of the first transistors T1 and the seventh transistors T7 of the sub-pixels in the same row are electrically connected to the initialization voltage signal terminal INIT through the same initialization voltage signal line IL.
  • the initialization voltage signal Vin output by the initialization voltage signal terminal INIT may be a constant voltage signal.
  • the initialization voltage signal Vin in FIG. 11 may be a constant low voltage signal.
  • the display substrate 200 further includes a second source-drain metal layer L SD2 disposed between the first source-drain metal layer L SD1 and the second gate metal layer L G2 .
  • each first voltage signal line 40 includes a first sub-voltage signal line 41 and a second sub-voltage signal line 42 , the first sub-voltage signal line 41 and the first sub-voltage signal line 41 electrical connection.
  • the first sub-voltage signal line 41 is disposed in the first source-drain metal layer L SD1
  • the second sub-voltage signal line 42 is disposed in the second source-drain metal layer L SD2 , that is, the second sub-voltage signal line
  • the device 42 is placed on the side of the first sub-voltage signal line 41 close to the substrate 10 , and the first sub-voltage signal line 41 , the first data line 21 and the second data line 22 are arranged in the same layer.
  • the first voltage signal line 40 may transmit the first voltage signal Vdd as a constant voltage signal to the sub-pixels electrically connected thereto, that is, the voltages on the first sub-voltage signal line 41 and the second sub-voltage signal line 42 may be the same. for a stable voltage.
  • the first sub-voltage signal line 41 disposed in the same layer as the first data line 21 and the second data line 22 and located therebetween has a stable voltage
  • the data signal Vdata transmitted on the first data line 21 and the second data line 22 can be shielded.
  • the parasitic capacitance between the adjacent first data lines 21 and the second data lines 22 can be reduced by the first self-voltage signal line 41 between them, thereby reducing the The crosstalk between the small data signals Vdata improves the display effect of the display device.
  • first sub-voltage signal line 41 , the first data line 21 and the second data line 22 may be formed through the same patterning process, so that they are arranged in the same layer.
  • the first sub-pixels 31 and the second sub-pixels 32 may be alternately arranged along the first direction OU.
  • the first sub-pixels 31 and the second sub-pixels 32 are arranged along the first The OUs are alternately arranged in one direction.
  • the first sub-pixels 31 and the second sub-pixels 32 may also be arranged non-alternately, for example, a row of sub-pixels is entirely composed of the first sub-pixels 31 or all of them are composed of the second sub-pixels 32;
  • a row of sub-pixels includes both a plurality of first sub-pixels 31 and a plurality of second sub-pixels 32, and at least part of the first sub-pixels 31 and/or the second sub-pixels 32 are arranged continuously.
  • the display substrate 200 further includes a first insulating layer IS1 disposed between the first sub-voltage signal line 41 and the second sub-voltage signal line 42 , and the first insulating layer IS1 includes multiple a first via hole 501 .
  • the first sub-voltage signal line 41 and the second sub-voltage signal line 42 are electrically connected through at least one first via hole 501 among the plurality of first via holes 501 .
  • the orthographic projections of the first sub-voltage signal line 41 and the second sub-voltage signal line 42 on the substrate 10 overlap or partially overlap.
  • the first via hole 501 can be disposed in the overlapping or overlapping area of the orthographic projections of the two, so that the two can be connected through the first via hole 501 .
  • the first insulating layer IS1 may have a single-layer structure or a stacked structure including a plurality of film layers.
  • the first insulating layer IS1 includes a stacked first planar layer 502 and a passivation layer 503 .
  • the first via hole 501 is a via hole passing through the first planarization layer 502 and the passivation layer 503 .
  • the connecting line between the centers of two adjacent first via holes 501 may be parallel or substantially parallel to the first direction OU.
  • the first data line 21 (refer to the data line DL3 in FIG. 12 ) and the second data line 22 (refer to the data line 22 in FIG. Line DL2) and the first sub-voltage signal line 41
  • the portion of the first data line 21 adjacent to the first via hole 501 is bent in a direction away from the first via hole 501 to form a first curved portion 211
  • the second data A portion of the line 22 adjacent to the first via hole 501 is bent in a direction away from the first via hole 501 to form a second bent portion 221 .
  • the first curved portion 211 and the second curved portion 221 are opposite to each other to form a receiving area A.
  • the first sub-voltage signal line 41 includes a conductive portion 411 passing through the first via hole 501 , and the conductive portion 411 is located in the accommodating area A. As shown in FIG.
  • the first sub-voltage signal line 41 is electrically connected to the second sub-voltage signal line 42 through its conductive portion 411 located at the first via hole 501 .
  • the size D1 of the conductive portion 411 is larger than the width D0 of the first sub-voltage signal line 41 , so that the first via hole 501 can be
  • the direction OU has a larger size, so as to ensure good electrical contact between the first sub-voltage signal line 41 and the second sub-voltage signal line 41 .
  • the size D3 of the accommodating space A may be larger than the portion of the first data line 21 (refer to the data line DL3 ) that is not the first curved portion and the non-first curved portion of the second data line 22 (refer to the data line DL2 ) between two adjacent columns of sub-pixels.
  • the first curved portion 211 helps the first data line 21 to avoid the conductive portion 43 at the first via hole 501 .
  • the second curved portion 211 helps the second data line 22 to avoid the conductive portion 43 at the first via hole 501 .
  • the first data line 21 and the second data line 22 can be made farther from the first voltage signal line 40, that is, the first data line 21 and the second data line 22 can be prevented from being connected to the first voltage signal line 40.
  • the line 40 is short-circuited, which improves the yield of the display substrate 200 .
  • the first via hole 501 is disposed between two adjacent rows of sub-pixels and between two adjacent columns of sub-pixels.
  • the first curved portion 211 and the second curved portion 221 occupy the arrangement space of the components in the adjacent sub-pixels, so that the first curved portion 211 and the second curved portion 221 along the
  • the degree of bending of the OU in one direction can be set to be relatively large without hindering the arrangement of components in adjacent sub-pixels.
  • the size D3 of the accommodating area A formed by the first bending portion 211 and the second connecting portion 221 can be set larger, so that along the first direction OU, the size D1 of the conductive portion 411 and the size of the first via hole 501 It can also be set larger, which is beneficial to the electrical contact between the first sub-voltage signal line 41 and the second sub-voltage signal line. Based on this, exemplarily, referring to FIG.
  • the conductive portion 411 The distance D4 from the first curved portion 211 is equal to or approximately equal to the distance D5 between the conductive portion 411 and the second curved portion 221 .
  • the spacing D4 between the bent portions 211 is equal to or substantially equal to the spacing D4 ′ between the portion of the first data line 21 that is not the first bent portion and the portion of the non-conductive portion of the first sub-voltage signal line 41 .
  • the conductive portion 411 and the second The distance D5 between the curved portions 221 is equal to or approximately equal to the distance D5 ′ between the portion of the second data line 22 that is not the second curved portion and the portion of the non-conductive portion of the first sub-voltage signal line 41 .
  • the display substrate 20 further includes a first connection part 60 disposed on the first source-drain metal layer L SD2 , that is, the first sub-voltage signal line 41 is connected to The first connection portion 60 is disposed on the same layer.
  • the first connecting portion 60 is disposed between the above-mentioned first bending portion 211 and the second bending portion 221 .
  • the first connection part 60 may be configured to shield the data signals Vdata of the first and second data lines 21 and 22 described above.
  • the bending of the first bending portion 211 and the second bending portion 221 The directions are opposite, that is, the first curved portion 221 is curved in a direction away from the second curved portion 221, and the second curved portion 221 is curved in a direction away from the first curved portion 211 to avoid the The first via hole 501 .
  • the first signal line 21 (refer to the data line DL1 ) and the second signal line 22 (refer to the data line DL2 , which are electrically connected to the same column of sub-pixels, the first curved portion 211 and the second curved portion 221 are disposed opposite to each other, that is, The first curved portion 211 is curved in a direction close to the second curved portion 221 , and the second curved portion 221 is curved in a direction close to the first curved portion 211 .
  • the first connection part 60 In the case where the first connection part 60 is not provided, the above situation may cause the first signal line 21 and the second signal line 22 electrically connected to the same column of sub-pixels, between the first bending part 211 and the second bending part 221 The smaller the distance, the larger parasitic capacitance is generated between the first curved portion 211 and the second curved portion 221, which affects the data writing and threshold voltage compensation of the sub-pixels.
  • the first connection part 60 can shield the data signal Vdata of the first signal line 21 and the second signal line 22, so the crosstalk between the data signals Vdata can be reduced, Improve the display effect of the display device.
  • the dimension L1 of the first connecting portion 60 is greater than or equal to the length L2 of the first curved portion 211 and the length L3 of the second curved portion 221, which can reduce the number of The relative area of the first curved portion 211 and the second curved portion 221 can further reduce the parasitic capacitance, thereby helping the first connection portion 60 to further reduce the crosstalk between the above-mentioned data signals Vdata.
  • the two adjacent first via holes 501 of the first connecting portion 60 are The two parts on either side of the connecting line in the center have approximately equal maximum dimensions.
  • the orthographic projection of the first connection portion 60 on the substrate 10 may be a regular figure or an irregular figure. 7 and 12, in the case that the orthographic projection of the first connection part on the substrate 10 is a regular figure, the orthographic projection of the geometric center O1 of the first connection part 60 on the substrate 10 is the same as The orthographic projections of the centers O 2 of the two adjacent first via holes 501 of the first connecting portion 60 on the substrate 10 are approximately located on the same straight line.
  • the geometry of the orthographic projection of the first connecting portion 60 on the substrate 10 is a regular figure, that is, when the orthographic projection of the first connecting portion 60 has a geometric center
  • the geometry of the orthographic projection of the first connecting portion 60 The center may be approximately located on the same straight line with the geometric centers of the orthographic projections of the two adjacent first via holes 501 .
  • the relative area of the first curved portion 211 and the second curved portion 221 is reduced to 0, so that the shielding effect of the first connection portion 60 on the data signal Vdata of the first data line 21 and the second data line 22 can be further improved , reducing the crosstalk between the data signals Vdata.
  • the display substrate 200 further includes an anode layer 90 disposed in the light emitting device E of each subpixel and a sixth electrode disposed in the pixel driving circuit of each subpixel transistor T6.
  • the active layer 76 of the sixth transistor T6 includes a first conductor portion, and the first connection portion 60 is electrically connected to the first conductor portion of the active layer 76 and the anode layer 90 . That is, the first conductor portion of the active layer 76 and the anode layer 90 are electrically connected through the first connection portion 60 .
  • the active layer 76 of the sixth transistor T6 may include a first conductor portion, a channel portion, and a second conductor portion, and the first conductor portion and the second conductor portion are connected through the channel portion.
  • the first conductor portion may serve as one of the source and the drain of the sixth transistor T6, and the second conductor portion may serve as the other of the source and the drain.
  • the sixth transistor T6 is a P-type transistor
  • the first conductive portion connected to the anode layer 90 serves as the drain of the sixth transistor T6, and the second conductive portion serves as the source of the sixth transistor T6 .
  • the sixth transistor T6 and the fifth transistor T5 are configured to conduct between the first voltage signal terminal VDD and the second voltage signal terminal VSS in response to the lighting signal Vem from the lighting signal segment EM 's line.
  • the sixth transistor T6 may be referred to as the first light emission control transistor
  • the fifth transistor T5 may be referred to as the second light emission control transistor.
  • the first connection portion 60 is electrically connected to the light-emitting device E, and the light-emitting device E is electrically connected to the second voltage signal terminal VSS, so that during the process of displaying an image by the display device including the display substrate 200, the first connection portion 60 has stable
  • the voltage can shield the data signal Vdata on the first signal line 21 and the second signal line 22 between two columns of pixels, reduce the crosstalk between the data signals Vdata, and improve the display effect of the display device.
  • first connection portion 60 in the above-mentioned display substrate 200 is disposed on the same layer as the first sub-voltage signal line 41 , the first data line 21 and the second data line 22 , no additional patterning process is required. In the case of , a first connection portion 60 that can be used to reduce crosstalk between the data signals Vdata of the first data line 21 and the second data line 22 is formed.
  • the light-emitting device E of each sub-pixel is not shown in FIG. 13 .
  • the light-emitting device E is disposed on the side of the first connection portion 60 away from the substrate 10, and the light-emitting device E includes an anode layer 90, a light-emitting functional layer and a cathode layer disposed along a direction away from the substrate. At least a portion of the anode layer 90 electrically connected to the first connection portion 60 is shown in the form of a dashed outline in FIG. 9B .
  • the display substrate 200 further includes a third insulating layer IS3, a fourth insulating layer IS4 and a fifth insulating layer disposed between the active layer LA and the second source-drain metal layer L SD2 .
  • IS5 , the third insulating layer IS3 , the fourth insulating layer IS4 and the fifth insulating layer IS5 are sequentially arranged along the direction away from the substrate 10 . It should be noted that FIG.
  • FIG 8D shows a top view of the stacked structure 12 formed by the third insulating layer IS3 , the fourth insulating layer IS4 and the fifth insulating layer IS5 , and here is a clear illustration of the arrangement in the stacked structure 12 For each via position of , the stacked structure 12 is shown in a transparent form.
  • the display substrate 200 further includes a second connection portion 80 .
  • Each second connection portion 80 is disposed between the active layer 76 of the sixth transistor T6 and the corresponding first connection portion 60 , and the second connection portion 80 is disposed in the same layer as the second sub-voltage signal line 42 .
  • the second connection portion 80 is electrically connected to the active layer 76 of the sixth transistor T6 and the corresponding first connection portion 60 described above. That is, the first connection part 60 and the anode layer 90 are electrically connected through the second connection part 80 .
  • the provision of the second connection part 80 facilitates the electrical connection between the first connection part 60 and the anode layer 90 .
  • the stacked structure 12 is further provided with a sixth via hole 508 penetrating through it, and the second connection portion 80 is electrically connected to the active layer 76 of the sixth transistor T6 through the sixth via hole 508 . connect.
  • the light-emitting functional layer includes a light-emitting material layer, and may also include a transport layer (election transporting layer, abbreviated as ETL), an electron injection layer (election injection layer, abbreviated as EIL), a hole transport layer (hole transporting layer, abbreviated as HTL) or an empty layer. At least one of the hole injection layers (HIL for short).
  • the light-emitting material layer may be an organic light-emitting material layer.
  • the display device including the display substrate 200 is an OLED (Organic Light-Emitting Diode, organic light-emitting diode) display device.
  • the light-emitting material layer may also be a quantum dot light-emitting material layer, in this case, the display device including the display substrate 200 is a QLED (Quantum Dot Light-Emitting Diode, quantum dot light-emitting diode) display device.
  • QLED Quantum Dot Light-Emitting Diode, quantum dot light-emitting diode
  • the display substrate 200 further includes a second insulating layer IS2 disposed between the anode layer 90 and the first connection part 60 .
  • the second insulating layer IS2 may be, for example, a second flat layer.
  • a second via hole 504 is provided in the second insulating layer IS2.
  • the orthographic projection of the second via hole 504 on the substrate 10 is located within the orthographic projection of the first connection portion 60 on the substrate 10 .
  • the anode layer 90 of the light emitting device E is electrically connected to the first connection part 60 through the second via hole 504 .
  • the orthographic projection of the first connection portion 60 on the substrate 10 and the orthographic projection of the second connection portion 80 on the substrate 10 have an overlapping area. In this way, vias can be placed in the overlapping area, so that the two can be connected through vias.
  • the first insulating layer IS1 is further provided with third via holes 505 , and each third via hole 505 is located on the lining of the first connection portion 60 and the second connection portion 80 .
  • the first connection portion 60 and the second connection portion 80 are electrically connected through the third via hole 505 .
  • both the first subpixel 31 and the second subpixel 32 include a fifth transistor T5 (which may be referred to as a second light emission control transistor) and a capacitor Cst, as shown in FIG. 9B
  • the second sub-voltage signal line 42 is electrically connected to the active layer 75 of the fifth transistor T5.
  • the third insulating layer IS3 , the fourth insulating layer IS4 and the fifth insulating layer IS5 are provided with a fourth through hole 506 , and the active layer of the fifth transistor T5 75 is electrically connected to the second sub-voltage signal line 42 through the fourth via hole 506 .
  • the first plate A1 of the capacitor Cst is disposed between the fourth insulating layer IS4 and the fifth insulating layer IS5
  • the second plate B1 is disposed between the fourth insulating layer IS4 and the fifth insulating layer IS5 .
  • the first pole plate A1 and the second pole plate B1 are disposed opposite to each other, that is, the plate surfaces of the two are at least partially opposite.
  • the second sub-voltage signal line 42 is also electrically connected to the first plate A1 of the capacitor Cst.
  • a plurality of fifth via holes 507 are provided in the fifth insulating layer IS5 , and the second sub-voltage signal line 42 passes through the fifth via holes 507 and the first plate A1 of the capacitor Cst.
  • the second sub-voltage signal line 42 passes through a fifth through hole 507 and the first plate A1 of the capacitor Cst; or as shown in FIG. 14 , the second sub-voltage signal line 42 passes through two or more fifth through holes
  • the hole 507 is connected to the first plate A1 of the capacitor Cst to ensure good electrical contact therebetween.
  • each sub-pixel located in the same row at least two adjacent sub-pixels are electrically connected between the first plates A1 of the capacitors Cst.
  • at least part of the first sub-voltage signal lines 41 can be connected in parallel through the first plates A1 of the capacitors Cst that are electrically connected to each other, that is to say, at least part of the first voltage signal lines 40 are connected in parallel, thereby reducing these
  • the resistance of the first voltage signal lines 40 connected in parallel can further reduce the voltage division on the first voltage signal lines 40 .
  • a plurality of sub-pixels in each row of sub-pixels are electrically connected to each other on the first plate A1 of the capacitor Cst. connected to form a plurality of auxiliary conductive strips 101 extending along the first direction OU, and the orthographic projections of the plurality of auxiliary conductive strips 101 on the substrate 10 are interlaced with the orthographic projections of the plurality of first sub-voltage signal lines 41 on the substrate 10 , forming a grid structure.
  • the first voltage signal lines 40 can be connected in parallel, thereby further reducing the resistance of the first voltage signal lines 40 and further reducing the divided voltage thereon.
  • the second source-drain metal layer L SD2 further includes a third connection part 110 , a fourth connection part 120 and a fifth connection part 130 .
  • the stacked structure 12 further includes a plurality of penetrating seventh via holes 510
  • the fifth insulating layer IS5 further includes a plurality of penetrating tenth via holes 513
  • the fourth insulating layer IS4 and the fifth insulating layer IS5 A plurality of penetrating eleventh via holes 514 are included.
  • the first end of the third connection part 110 is electrically connected to the initialization voltage signal line IL through the tenth via hole 513, and the second end of the third connection part 110 is electrically connected to the first end of the third connection part 110 through the seventh via hole 510B
  • the first end of the active layer 71 of the transistor T1 is electrically connected, so that the active layer 71 of the first transistor T1 and the initialization voltage signal line IL can be electrically connected.
  • the first end of the fourth connection portion 120 is electrically connected to the second end of the active layer 71 of the first transistor T1 through the seventh via hole 510C, and the second end of the fourth connection portion 120 is electrically connected to the capacitor through the eleventh via hole 514 .
  • the second plate B1 of Cst is electrically connected, so that the active layer 71 of the first transistor T1 can be electrically connected to the second plate B1 of the capacitor Cst.
  • the second plate B1 of the capacitor Cst and the gate G3 of the third transistor T3 are integrally formed, and the second plate B1 of the capacitor Cst overlaps with the orthographic projection of the active layer 73 of the third transistor T3 part as the gate G3 of the third transistor T3. That is, the second end of the active layer 71 of the first transistor T1 is also electrically connected to the gate G3 of the third transistor T3.
  • the gate G1 of the first transistor T1 is electrically connected to the reset signal line RL.
  • the portion of the reset signal line RL overlapping the orthographic projection of the active layer 71 of the first transistor T1 may be used as the gate G1 of the first transistor T1.
  • the second end of the active layer 72 of the second transistor T2 is electrically connected to the first end of the fourth connection part 120 through the seventh via hole 510C, so as to realize electrical connection with the second plate B1 of the capacitor Cst.
  • the first end of the active layer 72 of the second transistor T2 is electrically connected to the second end of the active layer 73 of the third transistor T3.
  • the gate G2 of the second transistor T2 is electrically connected to the gate line GL.
  • the first end of the active layer 73 of the third transistor T3 is electrically connected to the second end of the active layer 74 of the fourth transistor T4 and the second end of the active layer 75 of the fifth transistor T5.
  • the second end of the active layer 73 of the third transistor T3 is also electrically connected to the first end of the active layer 76 of the sixth transistor T6.
  • the first end of the fifth connection part 130 is electrically connected to the first end of the active layer 74 of the fourth transistor T4 through the seventh via hole 510E.
  • an eighth via hole 511 is further provided in the first insulating layer IS1 .
  • the second end of the fifth connection part 130 is electrically connected to the first data line 21 or the second data line 22 through the eighth via hole 511 .
  • the gate G4 of the fourth transistor T4 is electrically connected to the gate line GL.
  • the portion of the gate line GL overlapping with the orthographic projection of the active layer 74 of the fourth transistor T4 may be used as the gate G4 of the fourth transistor T4.
  • the area S P1 is the area where the first sub-pixel 31 is located
  • the area S P2 is the area where the second sub-pixel 32 is located.
  • the plane MN is perpendicular to the plane where the substrate 10 is located, and the two regions SP1 and SP2 are approximately symmetrically distributed along the orthographic projection of the plane MN on the substrate 10 .
  • the first subpixel 31 is connected to the first signal line 21 located on the left side thereof, and the second subpixel 32 is connected to the second signal line 22 located on the right side thereof, the first subpixel 31 can be connected to the first signal line
  • the connection position of 21 and the connection position of the second sub-pixel 32 and the second signal line 22 are set to be non-identical, that is, the distribution position of the eighth via hole 511 in the first sub-pixel 31 in the area S P1 is the same as The distribution positions of the eighth via holes 511 in the second sub-pixel 32 in the region SP2 are different.
  • the eighth via hole 511 in the first sub-pixel 31 and the eighth via hole 511 in the second sub-pixel 32 are not relative to the plane MN. mirror symmetrical.
  • the fifth connection parts 130 of the first sub-pixel 31 and the second sub-pixel 32 may be configured to be non-identical structures, so as to facilitate the electrical connection of the fourth transistor T4 with the corresponding data line. In this way, when there are process deviations during fabrication, for example, when each of the eighth via holes 511 and/or the fifth connection portion 130 is offset to one side, the offset of the above structure relative to the other side can be avoided to double . This can reduce dimensional errors caused by process fluctuations.
  • the gate G5 of the fifth transistor T5 is electrically connected to the light emission signal line EML.
  • the portion where the light-emitting signal line EML and the active layer 75 of the fifth transistor T5 are orthographically overlapped may be used as the gate G5 of the fifth transistor T5.
  • the gate G6 of the sixth transistor T6 is electrically connected to the light emission signal line EML.
  • the portion where the light emitting signal line EML and the active layer 76 of the sixth transistor T6 are orthographically overlapped may be used as the gate G6 of the sixth transistor T6.
  • the first end of the active layer 77 of the seventh transistor T7 is electrically connected to the first end of the third connection part 110 through the tenth via hole 513 , so as to be connected to the initialization voltage through the third connection part 110
  • the signal line IL is electrically connected.
  • the second end of the active layer 77 of the seventh transistor T7 is electrically connected to the anode layer 90 of the light emitting device E. It should be noted that, since the anode layer 90 is not shown in the display panel 200 shown in FIG. 7 , the connection relationship between the two is not shown in the figure. It should be understood that the connection structure between the second end of the active layer 77 of the seventh transistor T7 and the anode layer 90 of the light emitting device E can be set according to actual requirements.
  • the second metal layer L G2 further includes a shielding portion 102
  • the fifth insulating layer IS5 further includes a plurality of ninth via holes 512 .
  • the shielding portion 102 is electrically connected to the second sub-voltage signal line 42 through the ninth via 512, and the orthographic projection of the shielding portion 102 on the substrate 20 is connected to the first transistor
  • the orthographic projections of the active layer 71 of T1 , the active layer 72 of the second transistor T2 , the active layer 75 of the fourth transistor T4 and the active layer 77 of the seventh transistor T7 on the substrate 10 partially overlap. In this way, when the display device including the display substrate 200 displays an image, the shielding portion 102 can play a role of shielding light, thereby reducing the leakage current of the above-mentioned transistors.
  • Some embodiments of the present disclosure provide a display device including the display substrate 200 as described above.
  • the beneficial effects of the display device are the same as those of the above-mentioned display substrate 200 , which will not be repeated here.
  • some embodiments of the present disclosure provide a method for fabricating a display substrate, which can be used to fabricate the above-described display substrate 200 .
  • the preparation method includes the following S110 to S140.
  • the substrate 10 is provided.
  • each column of subpixels includes a plurality of first subpixels 31 and second subpixels 32 , and the first subpixels 31 and the second subpixels 32 are alternately arranged along the second direction OV.
  • a plurality of second sub-voltage signal lines 42 are formed on the side of the pixel driving circuit of the plurality of sub-pixels away from the substrate 10 , and each second sub-voltage signal line 42 is on the substrate 10 .
  • the orthographic projection is located between two adjacent columns of subpixels. It should be noted that the equivalent circuit diagram of the pixel driving circuit of the sub-pixel may refer to FIG. 11 , and the structures of the first transistor T1 to the seventh transistor T7 and the storage capacitor Cst included may refer to the above related description.
  • a plurality of first data lines 21, a plurality of second data lines 22, and a plurality of first sub-voltage signal lines 42 are formed on the side of the plurality of second sub-voltage signal lines 42 away from the substrate 10 Voltage signal line 41 .
  • a first sub-voltage signal line 41 and a second sub-voltage signal line 42 constitute a first voltage signal line 40
  • each first voltage signal line 40 is electrically connected to the pixel driving circuit of at least one column of sub-pixels
  • each The orthographic projection of the first voltage signal line 40 on the substrate 10 is located between the orthographic projections of the sub-pixels in two adjacent columns on the substrate 10 .
  • the first data lines 21 and the second data lines 22 are alternately arranged in the first direction.
  • a column of sub-pixels is adjacent to a first data line 21 and a second data line 22, and the first data line 21 and the second data line 22 are located on both sides of the column of sub-pixels, respectively.
  • the pixel driving circuit of each first sub-pixel 31 of the column sub-pixels is electrically connected to the first data line 21 adjacent thereto, and the pixel driving circuit of each second sub-pixel 32 of the column sub-pixels is the same as the adjacent second data line 21 Line 22 is electrically connected.
  • the preparation method includes the following S210 to S310.
  • an active layer L A is formed on the substrate 10 .
  • the active layer LA includes the active layer 71 of the first transistor T1, the active layer 72 of the second transistor T2, the active layer 73 of the third transistor T3, the The active layer 74 of the four transistors T4, the active layer 75 of the fifth transistor T5, the active layer 76 of the sixth transistor T6, and the active layer 77 of the seventh transistor T7.
  • the method further includes forming an inorganic buffer layer 11 on the substrate 10 .
  • the inorganic buffer layer 11 may be a single-layer structure or a multi-layer stack structure, for example, a stack structure in which inorganic film layers and organic film layers are alternately arranged.
  • a third insulating layer IS3 is formed on the side of the active layer LA away from the substrate 10 .
  • a first gate metal layer L G1 is formed on the side of the third insulating layer IS3 away from the substrate 10 .
  • the first gate metal layer LG1 includes the gate G1 of the first transistor T1, the gate G2 of the second transistor T2, the gate G3 of the third transistor T3, and the gate G4 of the fourth transistor T4 , the gate G5 of the fifth transistor T5, the gate G6 of the sixth transistor T6 and the gate G7 of the seventh transistor T7, and the second plate B1 of the capacitor Cst, the reset signal line RL, the gate line GL and the light emitting signal line EML.
  • a fourth insulating layer IS4 is formed on the side of the first gate metal layer LG1 away from the substrate 10 .
  • the above-mentioned preparation method further includes S241 .
  • S241 a plurality of tenth via holes 513 are formed in the fourth insulating layer IS4.
  • a second gate metal layer LG2 is formed on the side of the fourth insulating layer IS4 away from the substrate 10, and the second gate metal layer LG2 includes the first plate A1 of the capacitor Cst , and initialize the voltage signal line IL and the shielding portion 102 .
  • a fifth insulating layer IS5 is formed on the side of the second gate metal layer LG2 away from the substrate 10 .
  • the above preparation method further includes S261 to S263 .
  • a plurality of fifth via holes 507 and a plurality of ninth via holes 512 are formed in the fifth insulating layer IS5.
  • a plurality of penetrating eleventh via holes 514 are formed in the fourth insulating layer IS4 and the fifth insulating layer IS5.
  • a plurality of penetrating fourth via holes 506, sixth via holes 508 and seventh via holes 510 are formed in the third insulating layer IS3, the fourth insulating layer IS4 and the fifth insulating layer IS5 and 510E). That is, a plurality of penetrating fourth via holes 506, sixth via holes 508 and seventh via holes 510 are formed in the stacked structure 12.
  • S261 to S263 is not limited here, and S261 to S263 may be performed in a certain order, or the three steps may be performed simultaneously.
  • a second source-drain metal layer L SD2 is formed on the side of the fifth insulating layer IS5 away from the substrate 10 .
  • the second source-drain metal layer L SD2 may include the second sub-voltage signal line 42 , the second connection part 80 , the third connection part 110 , the fourth connection part 120 and the fifth connection part 130 .
  • a first insulating layer IS1 is formed on the side of the second gate metal layer LG2 away from the substrate 10 .
  • S280 includes: forming the first planarization layer 502 on the side of the second gate metal layer LG2 away from the substrate 10 , a passivation layer 503 is formed on the side of the first flat layer 502 away from the substrate 10, thereby forming a first insulating layer IS1.
  • the preparation method further includes S281.
  • S281 a plurality of first via holes 501, third via holes 505, and eighth via holes 511 are formed in the first insulating layer IS1.
  • a first source-drain metal layer L SD1 is formed on the side of the first insulating layer IS1 away from the substrate 10 .
  • the first source-drain metal layer L SD1 includes a plurality of first connection parts 60 , a first data line 21 , a second data line 22 and a first sub-voltage signal line 41 .
  • a second insulating layer IS2 is formed on a side of the first source-drain metal layer L SD1 away from the substrate 10 .
  • the preparation method further includes S301.
  • S301 a plurality of second via holes 504 are formed in the second insulating layer IS2.
  • the above preparation method further includes S310.
  • the anode layer 90 of each light emitting device E is formed on the side of the second insulating layer IS2 away from the substrate 10 .
  • the above-mentioned film layer and via hole can be formed by a patterning process, and the patterning process can include a photolithography process. , development and other processes and the use of photoresist, mask, exposure machine and other processes to form patterns.

Abstract

一种显示基板，包括衬底，以及设置于衬底上的第一数据线、第二数据线、多个子像素和第一电压信号线。第一数据线和第二数据线沿第一方向交替排列。每列子像素包括沿第二方向交替排列的第一子像素和第二子像素。沿第一方向，一列子像素的第一子像素与位于其一侧且相邻的第一数据线电连接，第二子像素与位于其另一侧且相邻的第二数据线电连接。每条第一电压信号线的正投影位于相邻的两列子像素之间的第一数据线和第二数据线的正投影之间。第一电压信号线包括第一子电压信号线和第二子电压信号线，第二子电压信号线设置于第一子电压信号线的靠近衬底的一侧，并与第一子电压信号线电连接，第一子电压信号线与第一数据线和第二数据线同层设置。

Description

显示基板及其制备方法、显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种显示基板及其制备方法、显示装置。
背景技术
显示装置的刷新频率(也可称为垂直刷新频率或垂直扫描频率)是指显示屏每秒可以显示的新的画面的次数，例如，显示屏在60Hz的刷新频率下，每秒可以显示60次新的画面。显示装置的刷新率较高时，例如75Hz、90Hz、120Hz或更高，其在显示高速移动的画面时可以避免画面出现模糊和拖尾等现象，提高画面质量和用户视觉体验。
发明内容
一方面，提供一种显示面板。所述显示面板包括衬底，以及设置于述衬底上的多个子像素、多条第一数据线、多条第二数据线和多条第一电压数据线。多个子像素呈阵列式布置。每相邻两列子像素之间设置有一条第一数据线和一条第二数据线。每列子像素包括多个第一子像素和第二子像素，第一子像素和第二子像素沿第二方向交替排列；沿第一方向，一列子像素与一条第一数据线和一条第二数据线相邻，且该第一数据线和该第二数据线分别位于该列子像素的两侧，该列子像素的每个第一子像素同与其相邻的第一数据线电连接，该列子像素的每个第二子像素同与其相邻的第二数据线电连接。每条第一电压信号线在所述衬底上的正投影位于相邻两列子像素之间的第一数据线和第二数据线在所述衬底上的正投影之间；所述第一电压信号线与至少一列子像素电连接；所述第一电压信号线包括：第一子电压信号线和第二子电压信号线，所述第二子电压信号线设置于所述第一子电压信号线的靠近所述衬底的一侧，并与所述第一子电压信号线电连接，所述第一子电压信号线与所述第一数据线和所述第二数据线同层设置。
在一些实施例中，沿所述第一方向，所述第一子像素与所述第二子像素交替布置。
在一些实施例中，所述显示基板还包括设置于所述第一子电压信号线和所述第二子电压信号线之间的第一绝缘层，所述第一绝缘层包括多个第一过孔。所述第一子电压信号线和所述第二子电压信号线通过所述多个第一过孔中的至少一个第一过孔电连接。位于相邻两列子像素之间的第一数据线、第二数据线和第一子电压信号线中，所述第一数据线中与所述第一过孔相邻的部 分向远离所述第一过孔的方向弯曲，形成第一弯曲部。所述第二数据线中与所述第一过孔相邻的部分向远离所述第一过孔的方向弯曲，形成第二弯曲部。所述第一弯曲部和所述第二弯曲部相对，形成容纳区域。所述第一子电压信号线包括经过所述第一过孔的导电部，所述导电部位于所述容纳区域内。
在一些实施例中，沿所述第一方向，所述导电部的尺寸大于所述第一子电压信号线的宽度；且，所述容纳空间的尺寸大于相邻两列子像素之间的第一数据线的非第一弯曲部的部分和第二数据线的非第二弯曲部的部分之间的间距。
在一些实施例中，沿所述第一方向，所述导电部与所述第一弯曲部之间的间距等于或大致等于所述导电部与所述第二弯曲部之间的间距。
在一些实施例中，沿所述第一方向，所述导电部与所述第一弯曲部之间的间距，等于或大致等于，所述第一数据线的非第一弯曲部的部分与所述第一子电压信号线的非导电部的部分之间的间距；和/或，沿所述第一方向，所述导电部与所述第二弯曲部之间的间距，等于或大致等于，所述第二数据线的非第二弯曲部的部分与所述第一子电压信号线的非导电部的部分之间的间距。
在一些实施例中，与一列子像素相邻，且位于该列子像素沿所述第一方向的两侧的第一数据线和第二数据线中，所述第一弯曲部和所述第二弯曲部之间设置有第一连接部，所述第一连接部与所述第一子电压信号线同层设置。
在一些实施例中，所述显示基板还包括阳极层和设置于所述衬底上的第一发光控制晶体管，所述阳极层设置于所述第一连接部远离所述衬底一侧。所述第一发光控制晶体管包括有源层，所述有源层包括第一导体部分，所述第一连接部与所述第一导体部分，以及所述阳极层电连接。
在一些实施例中，所述显示基板还包括第二连接部。所述第二连接部设置于所述第一发光控制晶体管的有源层和所述第一连接部之间，并与所述第二子电压信号线同层设置。所述第二连接部与所述第一导体部分，以及所述第一连接部电连接。
在一些实施例中，沿所述第二方向，所述第一连接部的尺寸大于或等于所述第一弯曲部和所述第二弯曲部的长度。
在一些实施例中，所述第一连接部在所述衬底上的正投影与所述第二连接部在所述衬底上的正投影具有重叠区域。
在一些实施例中，所述第一过孔位于相邻两行子像素之间，且位于相邻两列子像素之间。
在一些实施例中，在所述显示基板还包括所述第一连接部的情况下，沿所述第二方向，所述第一连接部的位于所述第一连接部相邻的两个第一过孔的 中心的连线两侧的两个部分的最大尺寸大致相等。
在一些实施例中，每个子像素包括第二发光控制晶体管和电容器。所述第二子电压信号线与所述第二发光控制晶体管的有源层电连接。所述电容器包括位于所述第二子电压信号线所在膜层靠近所述衬底一侧的第一极板，以及位于所述第一极板靠近所述衬底一侧的第二极板。所述第二子电压信号线还与所述第一极板电连接。
在一些实施例中，每行子像素中的多个子像素的电容器的第一极板之间相互电连接，形成沿所述第一方向延伸的多条辅助导电条，所述多条辅助导电条与所述多条第一子电压信号线在所述衬底上的正投影交错，形成网格结构。
另一方面，提供一种显示装置，包括如上所的显示基板。
又一方面，提供一种显示基板的制备方法。所述制备方法包括：提供衬底；在所述衬底上形成阵列排布的多个子像素的像素驱动电路，每列子像素包括多个第一子像素和多个第二子像素，第一子像素和第二子像素沿第二方向交替排列；在所述多个子像素的像素驱动电路的远离所述衬底的一侧形成多条第二子电压信号线，每条第二子电压信号线在所述衬底上的正投影位于相邻的两列子像素之间；在所述多条第二子电压信号线的远离所述衬底的一侧形成多条第一数据线、多条第二数据线和多条第一子电压信号线，一条第一子电压信号线和所述一条第二子电压信号线构成一条第一电压信号线，每条第一电压信号线与至少一列子像素的像素驱动电路电连接，每条第一电压信号线在所述衬底上的正投影位于所述相邻两列子像素在所述衬底上的正投影之间，第一数据线和第二数据线沿第一方向交替排列，沿第一方向，一列子像素与一条第一数据线和一条第二数据线相邻，且该第一数据线和该第二数据线分别位于该列子像素的两侧，该列子像素的每个第一子像素的像素驱动电路同与其相邻的第一数据线电连接，该列子像素的每个第二子像素的像素驱动电路同与其相邻的第二数据线电连接。
附图说明
为了更清楚地说明本公开中的技术方案，下面将对本公开一些实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例的附图，对于本领域普通技术人员来讲，还可以根据这些附图获得其他的附图。此外，以下描述中的附图可以视作示意图，并非对本公开实施例所涉及的产品的实际尺寸、方法的实际流程、信号的实际时序等的限制。
图1为根据一些实施例的一种7T1C像素驱动电路的等效电路图；
图2为图1所示的像素驱动电路的信号时序图；
图3为根据一些实施例的一种驱动架构的结构示意图；
图4为图3所示的驱动架构的信号时序图；
图5根据一些实施例的另一种驱动系统的结构示意图；
图6为图5所示的驱动系统的信号时序图；
图7为根据一些实施例的一种显示基板的俯视示意图；
图8A至8H为图7所示的显示基板的各膜层的俯视示意图；
图9A为图7中区域S1的局部放大示意图；
图9B为沿图7和图9A中的显示基板沿虚线XX’剖开的剖面示意图；
图10A为根据一些实施例的一种子像素的结构示意图；
图10B为根据一些实施例的另一种子像素的结构示意图；
图11为图7所示的显示基板的区域S2内部分的等效电路图；
图12为图7所示的显示基板的区域S3的局部放大示意图；
图13为根据一些实施例的另一种显示基板的示意图；
图14为图13所示的显示基板的区域S4的局部放大示意图；
图15A至15F为根据一些实施例的一种显示基板的制备方法的各步骤的示意图。
具体实施方式
下面将结合附图，对本公开一些实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开所提供的实施例，本领域普通技术人员所获得的所有其他实施例，都属于本公开保护的范围。
除非上下文另有要求，否则，在整个说明书和权利要求书中，术语“包括(comprise)”及其其他形式例如第三人称单数形式“包括(comprises)”和现在分词形式“包括(comprising)”被解释为开放、包含的意思，即为“包含，但不限于”。在说明书的描述中，术语“一个实施例(one embodiment)”、“一些实施例(some embodiments)”、“示例性实施例(exemplary embodiments)”、“示例(example)”、“特定示例(specific example)”或“一些示例(some examples)”等旨在表明与该实施例或示例相关的特定特征、结构、材料或特性包括在本公开的至少一个实施例或示例中。上述术语的示意性表示不一定是指同一实施例或示例。此外，所述的特定特征、结构、材料或特点可以以任何适当方式包括在任何一个或多个实施例或示例中。
以下，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗 示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本公开实施例的描述中，除非另有说明，“多个”的含义是两个或两个以上。
在描述一些实施例时，可能使用了“耦接”和“连接”及其衍伸的表达。例如，描述一些实施例时可能使用了术语“连接”以表明两个或两个以上部件彼此间有直接物理接触或电接触，或者以表明两个或两个以上的部件彼此间为间接的物理连接或电连接。
需要理解的是，在本公开的描述中，术语“中心”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本发明和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本发明的限制。在本发明的描述中，除非另有说明，“多个”的含义是两个或两个以上。
“A、B和C中的至少一个”与“A、B或C中的至少一个”具有相同含义，均包括以下A、B和C的组合：仅A，仅B，仅C，A和B的组合，A和C的组合，B和C的组合，及A、B和C的组合。
“A和/或B”，包括以下三种组合：仅A，仅B，及A和B的组合。
如本文所使用的那样，“约”或“近似”包括所阐述的值以及处于特定值的可接受偏差范围内的平均值，其中所述可接受偏差范围如由本领域普通技术人员考虑到正在讨论的测量以及与特定量的测量相关的误差(即，测量系统的局限性)所确定。
此外，本公开中“多个”、“多条”、“多列”和“多行”等术语中的“多”指数量上的两个及两个以上。
显示装置在较高的刷新频率(例如75Hz、90Hz、120Hz或更高)下工作时，可以提高所显示的画面质量以及用户的视觉体验。但是较高的刷新频率会带来显示装置中各子像素的数据写入和补偿时间变短的问题，这可能会导致各子像素充电率不足和阈值电压补偿效果下降，使显示装置的显示效果降低。
如图1所示，以包括7T1C结构的像素驱动电路的显示装置为例，显示装置包括多个子像素，每个子像素具有该7T1C结构的像素驱动电路，该像素驱动电路包括七个晶体管(第一晶体管T1至第七晶体管T7)和一个电容器Cst。该七个晶体管可以为P型晶体管，即在栅极接收到低电平信号时导通、接收到高电平信号是截止；该七个晶体管也可以为N型晶体管，即在栅极接收到高电平信号时导通、接收到低电平信号是截止。
为了方便介绍该7T1C的像素驱动电路，将第一晶体管T1的第二极、电容器Cst的第二极板B1和第三晶体管T3的栅极电连接点称为第一节点N1，第一节点N1、电容器Cst的第二极板B1和第三晶体管T3栅极的电压相等；将第五晶体管T5的第二极、第四晶体管T4的第二极和第三晶体管T3的第一极之间的电连接点称为第二节点N2；将第三晶体管T3、第二晶体管T2和第六晶体管T6的电连接节点称为第三节点N3。
需要说明的是，驱动晶体管的沟道宽长比通常会大于其他作为开关晶体管的沟道宽长比，也即第三晶体管T3的沟道宽长比通常会大于第一晶体管T1、第二晶体管T2、第四晶体管T4、第五晶体管T5、第六晶体管T6和第七晶体管T7的沟道宽长比。此外，以电致发光器件为例，各子像素对应的发光器件E的发光亮度与流过其的驱动电流I的大小有关。根据公式I＝K(Vgs-Vth) 2，可知，驱动电流I与驱动晶体管的源极和栅极电压差Vgs以及驱动晶体管的阈值电压Vth有关，即在电压差Vgs一定的情况下，各发光器件E的发光亮度主要会受到相应的驱动晶体管的阈值电压Vth的影响，这样在显示装置的子像素中驱动晶体管的阈值电压Vth不相等时，例如随工作时间增加，驱动晶体管的阈值电压Vth发生漂移时，显示装置可能出现显示亮度不均匀的现象。
下面对上述7T1C的像素驱动电路的各元器件及元器件之间的连接关系进行介绍。这里以像素驱动电路所包括的晶体管为P型晶体管为例，即第一晶体管T1至第七晶体管T7在其栅极接收的信号为低电平时导通，在其栅极接收的信号为高电平时截止。
第一晶体管T1的栅极与复位信号端RESET电连接，第一极与初始化电压信号端INIT电连接，第二极与第一节点N1电连接。第二晶体管T2的栅极与扫描信号端GATE电连接，第一极与第三节点N3电连接，第二极与第一节点N1电连接。第三晶体管T3的栅极与第一节点N1电连接，第一极与第二节点N2电连接，第二极与第三节点N3电连接，第四晶体管T4的栅极与扫描信号端GATE电连接，第一极与数据信号端DATA电连接，第二极与第二节点N2电连接。第五晶体管T5的栅极与发光信号端EM电连接，第一极与第一电压信号端VDD电连接，第二极与第二节点N2电连接。第六晶体管T6的栅极与发光信号端EM电连接，第一极与第三节点N3电连接，第二极与子像素的发光器件E的阳极电连接。第七晶体管T7的栅极与复位信号端RESET电连接，第一极与初始化电压信号端INIT电连接，第二极与子像素的发光器件E的阳极电连接。电容器Cst的第一极板A1与第一电压信号端VDD电连 接，第二极板B1与第一节点N1电连接。
此外，子像素的发光器件E的阳极与上述像素驱动电路电连接，阴极与第二电压信号端VSS电连接。
下面结合图2所示的信号时序图，对上述7T1C的像素驱动电路的工作过程介绍，在一帧时间里，像素驱动电路的工作过程包括复位阶段P1、写入和补偿阶段P2和发光阶段P3。
在复位阶段P1中，复位信号端RESET的传输至第一晶体管T1的栅极和第七晶体管T7的栅极的复位信号Vre为低电平，第一晶体管T1和第七晶体管T7导通。第一晶体管T1将来自初始化电压信号端INIT的初始化电压信号Vinit传输至第一节点N1，以对电容器Cst的第二极板B1和第三晶体管T3(也可以称为驱动晶体管T3)的栅极的电压进行复位，第二极板B1的电压等于初始化电压信号Vinit的电压Vi。第七晶体管T7将来自初始化电压信号端INIT的初始化电压信号Vinit传输至发光器件E的阳极，以对发光器件E的阳极电压进行复位。
这里，初始化电压信号Vinit在复位阶段P1中为低电平，第一节点N1的电压为低电压，因此栅极与第一节点N1电连接的第三晶体管T3导通。示例性的，初始化电压信号Vinit可以为恒定的低电压信号。
在写入和补偿阶段P2，复位信号Vre为高电平，第一晶体管T1和第七晶体管T7截止。第一节点N1的电压与电容器Cst的第二极板B1的电压相等，即第一节点N1的电压仍为低电压，第三晶体管T3维持导通状态。
扫描信号端GATE的传输至第四晶体管T4(可以称为写入晶体管T4)栅极和第二晶体管T2(可以称为补偿晶体管T2)栅极的扫描信号Vgate为低电平，第四晶体管T4和第二晶体管T2导通。第四晶体管T4将来自数据信号端DATA的数据信号Vdata传输至第三晶体管T3。数据信号Vdata通过导通的第三晶体管T3传输至第二晶体管T2，继而通过导通的第二晶体管T2传输至第一节点N1，从而被写入至电容器Cst。该数据信号Vdata通被写入至电容器Cst的过程实际为电容器Cst的第二极板B1的充电过程(即第二极板B1的电压逐渐升高的过程)，第一节点N1的电压由上一阶段(即复位阶段P1)中的Vi逐渐升高，直至第一节点N1的电压上升至Vdata+Vth，第三晶体管T3截止，这里Vth为第三晶体管T3的阈值电压值。此时，电容器Cst的第二极板B1的电压等于Vdata+Vth，这样，第三晶体管T3的阈值电压值Vth被补偿至电容器Cst所写入的数据信号中。
需要说明的是，这里扫描信号Vgate的有效电平(即，使相应晶体管导通 的电平)的持续时间1H为一行子像素完成数据信号Vdata写入所需要的时间。
在发光阶段P3，发光信号端EM的传输至第五晶体管T5栅极和第六晶体管T6栅极发光信号Vem为低电平，第五晶体管T5和第六晶体管T6导通。第三晶体管T3的源极电压Vs等于第一电压信号端VDD的第一电压Vdd，第三晶体管T3的栅极电压Vg等于Vdata+Vth，这里第一电压Vdd大于Vdata+Vth，因此第三晶体管T3被导通。这样，第一电压信号端VDD和第二电压信号端VSS之间形成了电流通路，从而发光器件E可以发光。
需要说明的是，发光阶段P3中流过发光器件E的驱动电流I为I＝K(Vgs-Vth) 2＝K(Vdata+Vth-Vdd-Vth) 2＝K(Vdata-Vdd) 2。这样，驱动电流I的大小与第三晶体管T3的阈值电压值Vth无关，从而可以避免第三晶体管T3的阈值电压漂移对驱动电流I的影响，使显示装置中各子像素的发光亮度更加均匀。
在显示装置需要以较快的频率进行刷新的情况下，由于每秒内显示的新画面次数较多，每帧画面的时间缩短，导致一帧内的写入和补偿阶段P2相应缩短，也即导致扫描信号的有效电平的持续时间缩短。这可能引起显示装置的子像素的数据写入时间(即子像素的充电时间)和阈值电压补偿时间较短，从而使子像素的充电率不足，以及阈值电压补偿效果不良，影响显示装置的画面质量和用户的视觉体验效果。
针对上述问题，可以采用设置两根数据线DL共同向一列子像素提供数据信号Vdata的驱动方式解决。下面将参照图3至6，对上述具有7T1C像素驱动电路的显示装置，采用该驱动方式的方案进行示例性介绍。
如图3和5所示，显示装置包括多个子像素PX、多条数据线DL和多条栅线GL(例如GL1至GL4)，这些子像素PX可以以阵列的方式设置。每列子像素与两条数据线DL(例如DL1至DL8)对应，该两条数据线DL分别设置于该列子像素的左、右两侧。位于同一列的子像素中，每相邻的两个子像素PX分别与上述左、右两侧数据线DL中不同的数据线DL电连接，即沿该列子像素的延伸方向，位于同一列的子像素PX交替地与左、右两侧的数据线DL电连接。位于同一行的子像素可以与同一条栅线GL电连接，这里，栅线GL可以向与其电连接的一行子像素提供扫描信号Vgate，使来自数据线DL的数据信号Vdata被传输进相应的子像素PX中，实现数据信号Vdata的写入。各子像素PX的数据写入过程可参考上文中对于写入和补偿阶段P2的描述，此处不再赘述。
需要说明的是，沿每行子像素的延伸方向，位于同一行的子像素PX可以交替地与其左、右两侧的数据线DL电连接(如图3和图5所示)，也可以均与位于其左侧或位于其右侧的数据线DL电连接。
显示装置还可以包括多条源极驱动信号线S(例如S1至S4)和源极驱动器100，多条源极驱动信号线S与源极驱动器100电连接。源极驱动器100用于提供显示装置所要显示图像的数据信号Vdata，通过源极驱动信号线S和数据线DL可以将这些数据信号Vdata提供给各子像素PX。
每相邻的多条数据线DL电连接至同一源极驱动信号线S上，这样，源极驱动器100可以通过源极驱动信号线S向与该源极驱动信号线S电连接的多条数据线DL传输数据信号Vdata，从而可以减少源极驱动器100上设置的用于输出数据信号Vdata的接口数量。每条数据线DL和其对应的源极驱动信号线S之间设置有开关SW，这样通过控制相应的开关SW的开启和关闭，可以使源极驱动信号线S被分时复用。这里，与同一源极驱动信号线S对应，且位于一列子像素左侧的数据线DL对应的开关SW的控制极均与同一控制信号线MUX(例如图3中的MUX1或MUX2)电连接，通过该控制信号线MUX可以控制上述数据线DL对应的开关SW的开启和关闭，从而控制某一帧内来自该源极驱动信号线S的数据信号Vdata向特定的数据线DL传输，这样可以控制该数据信号Vdata被写入进相应的子像素PX中。
这里开关SW可以包括N型或P型晶体管。在开关SW包括N型晶体管的情况下，开关SW在来自控制信号线MUX的信号为高电平时开启，在该信号为低电平时关闭。在开关SW包括P型晶体管的情况下，开关SW在来自控制信号线MUX的信号为低电平时开启，在该信号为高电平时关闭。
下面将分别以图2和图4所示的显示装置的结构为例，对该显示装置的驱动过程进行介绍，显示装置中的子像素内的像素驱动电路可以参考图1。这里以像素驱动电路中第二晶体管T2和第四晶体管T4，以及开关SW为P型晶体管为例，且沿一行子像素的延伸方向，位于同一行的子像素PX交替地与其左、右两侧的数据线DL电连接。
在一些示例中，参见图3，每两条相邻的数据线DL与同一源极驱动信号线S电连接。例如，源极驱动信号线S1与数据线DL1和数据线DL2电连接，也就是说，源极驱动器100可以通过源极驱动信号线S1、数据线DL1和数据线DL2，向第一列子像素PC1提供数据信号Vdata。类似地，源极驱动信号线S2与数据线DL3和数据线DL4电连接，源极驱动器100可以通过源极驱动信号线S2、数据线DL3和数据线DL4，向第二列子像素PC2提供数据信号 Vdata；源极驱动信号线S3与数据线DL5和数据线DL6电连接，源极驱动信号线S4与数据线DL7和数据线DL8电连接，源极驱动器100可以通过源极驱动信号线S4、数据线DL7和数据线DL8，向第四列子像素PC4提供数据信号Vdata。
与同一源极驱动信号线S对应的两条数据线DL中，每条位于相应列子像素左侧的数据线DL所电连接的各开关SW中，薄膜晶体管的栅极均与控制信号线MUX1电连接；每条位于相应列子像素右侧的数据线DL所对应的开关SW中，薄膜晶体管的栅极均与控制信号线MUX2电连接。例如数据线DL1、DL3、DL5和DL7所电连接的各开关SW中薄膜晶体管的栅极均与控制信号线MUX1电连接，数据线DL2、DL4、DL6和DL8所对应的开关SW中的薄膜晶体管的栅极均与控制信号线MUX2电连接。
由此，通过向不同的开关SW中的薄膜晶体管传输不同电平的信号，可以选通不同的数据线DL来传输数据信号Vdata至相应的子像素PX中。这样，源极驱动器100可以通过一条源极驱动信号线S向与该源极驱动信号线S电连接的两条数据线DL传输数据信号Vdata。
在这种情况下，参见图4，第一阶段T11中，经由控制信号线MUX1传输的控制信号Vumx1为低电平，与控制信号线MUX1电连接的开关SW中的薄膜晶体管导通；经由控制信号线MUX2传输的控制信号Vumx2为高电平，与控制信号线MUX2电连接的开关SW中的薄膜晶体管截止。经由扫描信号线GL1传输的扫描信号Vgate1为低电平，位于第一子像素行PR1的各子像素PX中的第二晶体管T2和第四晶体管T4导通；经由扫描信号线GL2传输的扫描信号Vgate2为高电平，位于第二子像素行PR2的各子像素PX中的第二晶体管T2和第四晶体管T4截止。这样，经由源极驱动信号线S1传输的数据信号Vdata被写入位于第一行子像PR1、第一列子像素PC1的子像素中，经由源极驱动信号线S3传输的数据信号Vdata被写入位于第一行子像PR1、第三列子像素PC3的子像素中。
在第二阶段T12中，通过控制信号线MUX1传输的控制信号Vumx1为高电平，与控制信号线MUX1电连接的各开关SW被关闭；通过控制信号线MUX2传输的控制信号Vumx2为低电平，与控制信号线MUX2电连接的各开关SW被开启。通过扫描信号线GL1传输的扫描信号Vgate1和通过扫描信号线GL2传输的扫描信号Vgate2均为低电平，位于第一行子像素PR1和第二行子像素PR2的各子像素PX中的第二晶体管T2和第四晶体管T4均导通。这样，虽然第一行子像素PR1和第二行子像素PR2中的各子像素的第四晶体 管T4均被导通，但是由于与数据线DL1、DL3、DL5和DL7对应的开关SW均为关闭的，经由源极驱动信号线S1传输的数据信号Vdata由数据线DL2写入位于第二行子像PR2、第一列子像PC1的子像素中，经由源极驱动信号线S2传输的数据信号Vdata由数据线DL4写入位于第一行子像PR1、第二列子像PC2的子像素中，经由源极驱动信号线S3传输的数据信号Vdata由数据线DL6写入位于第二行子像PR2、第三列子像PC3的子像素中，经由源极驱动信号线S4传输的数据信号Vdata由数据线DL8写入位于第一行子像PR1、第四列子像PC4的子像素中。
需要注意的是，在上述驱动方式中，子像素PX的扫描信号Vgate的有效电平的持续时间为2H，即子像素PX的扫描信号Vgate的有效电平的持续时间与两行子像素完成数据信号Vdata写入所需要的时间相等。这样可以增加写入和补偿阶段P2的时间，使子像素PX的充电时间充足、阈值电压补偿效果提高，从而可以提高显示装置在高刷新频率下的显示效果。
在一些实施例中，参见图5，每4条相邻的数据线DL与同一源极驱动信号线S电连接。例如，源极驱动信号线S1与数据线DL1至DL4电连接，源极数据线S2与数据线DL5至DL8电连接。
沿一行子像素的延伸方向从左向右，每4条与同一源极驱动信号线S对应的数据线DL中，每个序号为1的数据线DL所电连接的各开关SW中薄膜晶体管的栅极均与控制信号线MUX1电连接，每个序号为2的数据线DL所电连接的各开关SW中薄膜晶体管的栅极均与控制信号线MUX2电连接，每个序号为3的数据线DL所电连接的各开关SW中薄膜晶体管的栅极均与控制信号线MUX3电连接，每个序号为4的数据线DL所电连接的各开关SW中薄膜晶体管的栅极均与控制信号线MUX4电连接。
同样地，通过向不同的开关SW中的薄膜晶体管传输不同电平的信号，可以选通不同的数据线DL来传输数据信号Vdata至相应的子像素PX中。这样，通过分时复用源极驱动信号线S的方式，源极驱动器100可以通过同一条源极驱动信号线S向与该源极驱动信号线S电连接的4条数据线DL传输数据信号Vdata，从而使对应的四列子像素实现数据信号Vdata的写入。
在这种情况下，参见图6，在第一阶段T21中，经由控制信号线MUX1传输的控制信号Vumx1为低电平，与控制信号线MUX1电连接的开关SW中的薄膜晶体管导通；经由控制信号线MUX2至MUX4传输的控制信号Vumx2至Vumx4均为高电平，与控制信号线MUX2至MUX4电连接的开关SW中的薄膜晶体管均截止。经由扫描信号线GL1传输的扫描信号Vgate1为低电 平，位于第一子像素行PR1的各子像素PX中的第二晶体管T2和第四晶体管T4导通；经由扫描信号线GL2至GL4传输的扫描信号Vgate2至Vgate4均为高电平，位于第二像素行PR2至第四像素行PR4的各子像素PX中的第二晶体管T2和第四晶体管T4均截止。这样，经由源极驱动信号线S1传输的数据信号Vdata被写入位于第一行子像PR1、第一列子像素PC1的子像素中，经由源极驱动信号线S2传输的数据信号Vdata被写入位于第一行子像PR1、第三列子像素PC3的子像素中。
在第二阶段T22中，经由控制信号线MUX2传输的控制信号Vumx2为低电平，与控制信号线MUX2电连接的开关SW中的薄膜晶体管导通；经由控制信号线MUX1、MUX3和MUX4传输的控制信号Vumx1、Vumx3和Vumx4均为高电平，与控制信号线MUX1、MUX3和MUX4电连接的开关SW中的薄膜晶体管均截止。经由扫描信号线GL1和GL2传输的扫描信号Vgate1和Vgate2为低电平，位于第一子像素行PR1和第二子像素行PR2的各子像素PX中的第二晶体管T2和第四晶体管T4导通；经由扫描信号线GL3和GL4传输的扫描信号Vgate3和Vgate4均为高电平，位于第三像素行PR3和第四像素行PR4的各子像素PX中的第二晶体管T2和第四晶体管T4均截止。这样，经由源极驱动信号线S1传输的数据信号Vdata被写入位于第二行子像PR2、第一列子像素PC1的子像素中，经由源极驱动信号线S2传输的数据信号Vdata被写入位于第二行子像PR2、第三列子像素PC3的子像素中。
在第三阶段T3中，经由控制信号线MUX3传输的控制信号Vumx3为低电平，与控制信号线MUX3电连接的开关SW中的薄膜晶体管导通；经由控制信号线MUX1、MUX2和MUX4传输的控制信号Vumx1、Vumx2和Vumx4均为高电平，与控制信号线MUX1、MUX2和MUX4电连接的开关SW中的薄膜晶体管均截止。经由扫描信号线GL1至GL3传输的扫描信号Vgate1至Vgate3为低电平，位于第一子像素行PR1至第三子像素行PR3的各子像素PX中的第二晶体管T2和第四晶体管T4导通；经由扫描信号线GL4传输的扫描信号Vgate4为高电平，位于第四像素行PR4的各子像素PX中的第二晶体管T2和第四晶体管T4均截止。这样，经由源极驱动信号线S1传输的数据信号Vdata被写入位于第二行子像PR2、第二列子像素PC2的子像素中，经由源极驱动信号线S2传输的数据信号Vdata被写入位于第二行子像PR2、第四列子像素PC4的子像素中。
在第四阶段T4中，经由控制信号线MUX4传输的控制信号Vumx4为低电平，与控制信号线MUX4电连接的开关SW中的薄膜晶体管导通；经由控 制信号线MUX1至MUX3传输的控制信号Vumx1至Vumx3均为高电平，与控制信号线MUX1至MUX3电连接的开关SW中的薄膜晶体管均截止。经由扫描信号线GL1至GL4传输的扫描信号Vgate1至Vgate4均为低电平，位于第一子像素行PR1至第四子像素行PR4的各子像素PX中的第二晶体管T2和第四晶体管T4均导通。这样，经由源极驱动信号线S1传输的数据信号Vdata被写入位于第一行子像PR2、第二列子像素PC2的子像素和位于第三行子像PR3、第二列子像素PC2的子像素中，经由源极驱动信号线S2传输的数据信号Vdata被写入位于第一行子像PR1、第四列子像素PC4的子像素和位于第三行子像PR3、第四列子像素PC4的子像素中。
这里，子像素PX的扫描信号Vgate的有效电平的持续时间为2H，同样可以增加写入和补偿阶段P2的时间，使子像素PX的充电时间充足、阈值电压补偿效果提高，从而可以提高显示装置在高刷新频率下的显示效果。
需要注意的是，在该第四阶段T4中，位于第三行子像PR3、第二列子像素PC2的子像素，以及位于第三行子像PR3、第四列子像素PC4的子像素所写入的数据信号Vdata并不是其发光阶段中实际所需要的数据信号。在扫描信号的有效电平的持续时间为2H，在与上述两个子像素对应的扫描信号Vgate3的有效电平结束之前，该两个子像素还会被再次写入新的数据信号Vdata，该新写入的数据信号Vdata为其发光阶段所需要的数据信号。
然而，在显示装置采用上述通过两根数据线DL共同向一列子像素提供数据信号Vdata的驱动方式时，显示装置中设置的数据线DL的数量会增加一倍，使得数据线DL之间的间距变小，从而可能导致相邻的数据线DL之间产生较大的寄生电容。较大的寄生电容会引起相邻的数据线DL传输的数据信号Vdata之间的串扰，影响子像素的数据写入及阈值电压补偿，从而可能降低显示装置的显示效果。
参见图7至14，本公开的一些实施例提供一种显示基板200。如图7、9A和9B所示，该显示基板200包括衬底10，设置于衬底10上的多条第一数据线21和多条第二数据线22，以及设置于衬底10上的、阵列式布置的多个子像素。每相邻两列子像素之间设置有一条第一数据线21和一条第二数据线22。
如图7、10A和10B所示，每列子像素包括多个第一子像素31和多个第二子像素32。这里，为便于描述，定义与一列子像素的延伸方向垂直或大致垂直的方向为第一方向OU，也即第一方向OU为多个子像素阵列式布置的行方向，定义与一列子像素的延伸方向平行或大致平行的方向为第二方向OV，也即第二方向OV为多个子像素阵列式布置的列方向。沿第二方向OV，第一 子像素31和第二子像素32交替排列。沿第一方向OU，一列子像素与一条第一数据线21和一条第二数据线22相邻，且该第一数据线21和该第二数据线22分别位于该列子像素的两侧。该列子像素的每个第一子像素31同与其相邻的第一数据线21电连接，该列子像素的每个第二子像素32同与其相邻的第二数据线22电连接。
显示基板200还包括设置于衬底10上的第一电压信号线40，每条第一电压信号线40在衬底10上的正投影，位于相邻的两列子像素之间的第一数据线21和第二数据线22在衬底10上的正投影之间，每条第一电压信号线40与至少一列子像素电连接。示例性的，每相邻的两列子像素之间的第一数据线21和第二数据线22在衬底10上的正投影之间，均有第一电压信号线40在衬底10上的正投影。
需要说明的是，衬底10与多个子像素之间还可以设置有例如无机缓冲层11的膜层。无机缓冲层11可以为单层结构，也可以为多层的层叠结构，例如为无机膜层和有机膜层的交替设置的层叠结构。
图11为图7所示显示基板200的位于区域S2内部分的等效电路图，这里以显示基板200在区域S2内包括矩阵排布的2个第一子像素31和2个第二子像素32为例进行说明。每个第一子像素31和每个第二子像素32具有7T1C结构的像素驱动电路，像素驱动电路包括第一晶体管T1至第七晶体管T7和电容器Cst。该像素驱动电路内部的元器件之间的电连接关系，以及该驱动电路的工作过程可以参照上文的描述，此处不再赘述。
下面将参照图7至9B，对显示面板200中子像素的像素驱动电路中的各元器件的结构进行示例性的介绍。沿衬底10的厚度方向，显示面板200包括依次设置于衬底10上的有源层L A、第一栅金属层L G1、第二栅金属层L G2和第一源漏金属层L SD1。需要说明的是，图8D中区域S P为一个子像素所对应的区域，即图8D中区域S P内的结构为显示基板200的一个最小重复单元，这里及下文将以一个子像素所对应的区域S P内的结构为例进行介绍。
如图8A和9B所示，有源层L A包括第一晶体管T1的有源层71、第二晶体管T2的有源层72、第三晶体管T3的有源层73、第四晶体管T4的有源层74、第五晶体管T5的有源层75、第六晶体管T6的有源层76和第七晶体管T7的有源层77。
如图8B和9B所示，第一栅金属层L G1包括第一晶体管T1的栅极G1、第二晶体管T2的栅极G2、第三晶体管T3的栅极G3、第四晶体管T4的栅极G4、第五晶体管T5的栅极G5、第六晶体管T6的栅极G6和第七晶体管T7 的栅极G7。第一栅金属层L G1还包括电容器Cst的第二极板B1、复位信号线RL、栅线GL和发光信号线EML。这里，复位信号线RL被配置为将来自复位信号端RESET的复位信号Vre传输至相应的子像素，栅线GL被配置为将来自扫描信号端GATE的扫描信号Vgate传输至相应的子像素，发光信号线EML被配置为将来自发光信号端EM的发光信号Vem传输至相应的子像素。
需要说明的是，第一栅金属层L G1与第一晶体管T1的有源层71在衬底10上的正投影的重叠部分可以作为第一晶体管T1的栅极G1，第一栅金属层L G1与第二晶体管T2的有源层72在衬底10上的正投影的重叠部分可以作为第二晶体管T2的栅极G2，第一栅金属层L G1与第三晶体管T3的有源层73在衬底10上的正投影的重叠部分可以作为第三晶体管T3的栅极G3，第一栅金属层L G1与第四晶体管T4的有源层74在衬底10上的正投影的重叠部分可以作为第四晶体管T4的栅极G4，第一栅金属层L G1与第五晶体管T5的有源层75在衬底10上的正投影的重叠部分可以作为第五晶体管T5的栅极G5，第一栅金属层L G1与第六晶体管T6的有源层76在衬底10上的正投影的重叠部分可以作为第六晶体管T6的栅极G6，第一栅金属层L G1与第七晶体管T7的有源层77在衬底10上的正投影的重叠部分可以作为第七晶体管T7的栅极G7。
如图8C和9B所示，第二栅金属层L G2包括电容器Cst的第一极板A1、初始化电压信号线IL和遮挡部102。初始化电压信号线被配置为将来自初始化电压信号端INIT的初始化电压信号Vin传输至相应的子像素。
如图8G和9B所示，第一源漏金属层L SD1包括上述第一信号线21和第二信号线22，且沿第一方向OU，第一信号线21和第二信号线22交替排列。
下面参照图11，对各子像素的像素驱动电路与显示基板中的信号线的连接关系进行说明。
同一列子像素中，第一子像素31的第四晶体管T4与同一第一数据线21电连接，第二子像素32的第四晶体管T4与同一第二数据线22电连接。也就是说，第一子像素31通过第一数据线21接收数据信号Vdata，第二子像素32通过第二数据线22接收数据信号Vdata。
位于同一列的子像素的第五晶体管T5的第一极通过同一第一电压信号线40电连接至第一电压信号端VDD。这里，第一电压信号线40可以用于传输来自第一电压信号端VDD的第一电压信号Vdd至与其电连接的子像素中，第一电压信号Vdd为恒压信号，例如图11中为恒低压信号。
位于同一行的子像素的第二晶体管T2和第四晶体管T4的栅极通过同一 栅线GL电连接至同一级扫描信号端GATE(例如第N级扫描信号端GATE N或第(N+1)级扫描信号端GATA N+1)。
位于同一行的子像素的第五晶体管T5和第六晶体管T6的栅极通过同一发光信号线EML电连接至同一级发光信号端EM(例如第N级发光信号端EM N或第(N+1)发光信号端EM N+1)。
位于同一行的子像素的第一晶体管T1和第七晶体管T7的栅极，通过同一复位信号线RL电连接至上一级扫描信号端GATE。需要说明的是，这里以上一级扫描信号端GATE输出的扫描信号Vgate作为复位信号Vre，也就是说，上一级扫描信号端GATE用作当前子像素的复位信号端RESET。例如，图11中，第N级扫描信号端GATE N输出的扫描信号Vgate，作为第二晶体管T2和第四晶体管T4与第(N+1)级扫描信号端GATA N+1电连接的子像素的复位信号Vre。
位于同一行的子像素的第一晶体管T1第七晶体管T7的第一极通过同一初始化电压信号线IL电连接至初始化电压信号端INIT。这里初始化电压信号端INIT输出的初始化电压信号Vin可以为恒压信号，例如，图11中的初始化电压信号Vin可以为恒低压信号。
在一些实施例中，参见图8G和9B，显示基板200还包括设置于第一源漏金属层L SD1和第二栅金属层L G2之间的第二源漏金属层L SD2。
如图8E、8G和9B所示，每个第一电压信号线40包括第一子电压信号线41和第二子电压信号线42，第一子电压信号线41与第一子电压信号线41电连接。这里，第一子电压信号线41设置于第一源漏金属层L SD1中，第二子电压信号线42设置于第二源漏金属层L SD2中，也就是说，第二子电压信号线设42置于第一子电压信号线41的靠近衬底10的一侧，第一子电压信号线41、第一数据线21及第二数据线22同层设置。
第一电压信号线40可以向与其电连接的子像素传输为恒定电压信号的第一电压信号Vdd，也就是说，第一子电压信号线41和第二子电压信号线42上的电压可以均为稳定的电压。在包括有上述显示基板200的显示装置显示画面时，与第一数据线21和第二数据线22同层设置的，且位于二者之间的第一子电压信号线41因具有稳定的电压，可以对第一数据线21和第二数据线22上传输的数据信号Vdata起到屏蔽作用。这样，该显示装置在显示过程中，相邻的第一数据线21和第二数据线22之间的寄生电容可以被设置与二者之间的第一自电压信号线41降低，从而可以减小数据信号Vdata之间的串扰，提高显示装置的显示效果。
需要说明的是，可以通过同一次构图工艺形成第一子电压信号线41、第一数据线21和第二数据线22，以使他们同层设置。
此外，沿第一方向OU，第一子像素31和第二子像素32可以为交替排布的，例如图7所示的显示基板200中，第一子像素31和第二子像素32沿第一方向OU交替排布。沿第一方向OU，第一子像素31和第二子像素32也可以为非交替排布的，例如，一行子像素全部由第一子像素31构成或全部由第二子像素32构成；又例如，一行子像素既包括多个第一子像素31，又包括多个第二子像素32，至少部分的第一子像素31和/或第二子像素32连续排布。
示例性的，参见图8F、9B和12，显示基板200还包括设置于第一子电压信号线41和第二子电压信号线42之间的第一绝缘层IS1，第一绝缘层IS1包括多个第一过孔501。第一子电压信号线41和第二子电压信号线42通过多个第一过孔501中的至少一个第一过孔501电连接。
示例性的，第一子电压信号线41和第二子电压信号线42在衬底10上的正投影重合或部分重叠。这样第一过孔501可以设置于二者正投影的重合或重叠区域内，便于二者通过第一过孔501连接。
这里，第一绝缘层IS1可以为单层结构，也可以为包括多个膜层的层叠结构。例如，如图9B所示，第一绝缘层IS1包括层叠的第一平坦层502和钝化层503。在这种情况下，第一过孔501为贯穿第一平坦层502和钝化层503的通孔。
示例性的，参见图8F，相邻的两个第一过孔501的中心之间的连线可以平行或大致平行于第一方向OU。
在一些实施例中，参见图7、8G和图12，位于相邻两列子像素之间的第一数据线21(参照图12中数据线DL3)、第二数据线22(参照图12中数据线DL2)和第一子电压信号线41中，第一数据线21中与第一过孔501相邻的部分向远离第一过孔501的方向弯曲，形成第一弯曲部211；第二数据线22中与第一过孔501相邻的部分向远离第一过孔501的方向弯曲，形成第二弯曲部221。第一弯曲部211和第二弯曲部221相对，形成容纳区域A。第一子电压信号线41包括经过第一过孔501的导电部411，导电部411位于容纳区域A内。
需要说明的是，第一子电压信号线41通过其位于第一过孔501处的导电部411，与第二子电压信号线42电连接。在这种情况下，示例性的，参见图12，沿第一方向OU，导电部411的尺寸D1大于第一子电压信号线41的宽度D0，这样可以使第一过孔501在沿第一方向OU上具有较大尺寸，从而保 证第一子电压信号线41和第二子电压信号线41的电接触良好。
容纳空间A的尺寸D3可以大于相邻两列子像素之间的第一数据线21(参照数据线DL3)的非第一弯曲部的部分和第二数据线22(参照数据线DL2)的非第二弯曲部的部分之间的间距D2。这里，第一弯曲部211有利于该第一数据线21避让第一过孔501处的导电部43。同样地，第二弯曲部211有利于该第二数据线22避让第一过孔501处的导电部43。从而可以使该第一数据线21和该第二数据线22距离第一电压信号线40较远，也就是说，可以防止该第一数据线21和该第二数据线22与第一电压信号线40发生短路，提高显示基板200的良率。
示例性的，参见图7和12，第一过孔501设置于相邻两行子像素之间，且位于相邻两列子像素之间。在这种情况下，可以避免上述第一弯曲部211和第二弯曲部221占用与之相邻的子像素中的元器件的设置空间，这样第一弯曲部211和第二弯曲部221沿第一方向OU的弯折程度可以设置的较大，而不会妨碍相邻的子像素中的元器件的设置。因此，上述第一弯曲部211和第二连接部221所形成的容纳区域A的尺寸D3可以设置的较大，从而沿第一方向OU，导电部411的尺寸D1和第一过孔501的尺寸也可以设置的较大，这有利于第一子电压信号线41和第二子电压信号线的电接触。基于此，示例性的，参见图12，位于相邻两列子像素之间的第一数据线21、第二数据线22和第一子电压信号线41中，沿第一方向OU，导电部411与第一弯曲部211之间的间距D4等于或大致等于该导电部411与第二弯曲部221之间的间距D5。
示例性的，参见图12，位于相邻两列子像素之间的第一数据线21、第二数据线22和第一子电压信号线41中，沿第一方向OU，导电部411与第一弯曲部211之间的间距D4，等于或大致等于第一数据线21的非第一弯曲部的部分与第一子电压信号线41的非导电部的部分之间的间距D4’。
示例性的，参见图12，位于相邻两列子像素之间的第一数据线21、第二数据线22和第一子电压信号线41中，沿第一方向OU，导电部411与第二弯曲部221之间的间距D5，等于或大致等于第二数据线22的非第二弯曲部的部分与第一子电压信号线41的非导电部的部分之间的间距D5’。
在一些实施例中，参见图7、8G、9B和12，与一列子像素相邻，且位于该列子像素沿第一方向OU的两侧(即图12中该子像素的左、右两侧)的第一数据线21(参照图12中数据线DL1)和第二数据线22(参照图12中数据线DL2)中，第一弯曲部211向该第一数据线21弯曲，第二弯曲部221向该 第二数据线22弯曲，也即二者的弯曲方向是相对的。在这种情况下，示例性的，参见图8G和9B，显示基板20还包括设置于第一源漏金属层L SD2的第一连接部60，也就是说，第一子电压信号线41与第一连接部60同层设置。第一连接部60设置于上述第一弯曲部211和第二弯曲部221之间。这里，第一连接部60可以被配置为对上述第一数据线21和第二数据线22的数据信号Vdata进行屏蔽。
需要说明的是，位于两列像素之间的第一信号线21(参照数据线DL3)和第二信号线22(参照数据线DL2)中，第一弯曲部211和第二弯曲部221的弯曲方向是相反的，即该第一弯曲部221向远离该第二弯曲部221的方向弯曲，该第二弯曲部221向远离该第一弯曲部211的方向弯曲，以避让位于二者之间的第一过孔501。因此，与同一列子像素电连接的第一信号线21(参照数据线DL1)和第二信号线22(参照数据线DL2中，第一弯曲部211与第二弯曲部221为相对设置的，即该第一弯曲部211向靠近该第二弯曲部221的方向弯曲，该第二弯曲部221向靠近该第一弯曲部211的方向弯曲。
在未设置有第一连接部60的情况下，上述情况可能导致与同一列子像素电连接的第一信号线21和第二信号线22中，第一弯曲部211和第二弯曲部221之间距离较小，引起第一弯曲部211和第二弯曲部221之间产生较大的寄生电容，影响子像素的数据写入和阈值电压补偿。而在设置有第一连接部60的情况下，第一连接部60可以对上述第一信号线21和第二信号线22的数据信号Vdata进行屏蔽，因此可以降低数据信号Vdata之间的串扰，提高显示装置的显示效果。
示例性的，参见图12，沿第二方向OV，上述第一连接部60的尺寸L1大于或等于上述第一弯曲部211的长度L2和上述第二弯曲部221的长度L3，这样可以减少第一弯曲部211和第二弯曲部221的相对面积，即可以进一步降低寄生电容，从而有利于第一连接部60进一步降低上述数据信号Vdata之间的串扰。
在一些实施例中，参见图12，在显示基板200还包括第一连接部60的情况下，沿第二方向OV，第一连接部60的位于其相邻的两个第一过孔501的中心的连线两侧的两个部分的最大尺寸大致相等。
需要说明的是，第一连接部60在衬底10上的正投影可以为规则的图形，也可以为不规则的图形。示例性的，参见图7和12，在第一连接部在衬底10上的正投影为规则图形的情况下，第一连接部60的几何中心O 1在衬底10上的正投影，与该第一连接部60相邻的两个第一过孔501的中心O 2在衬底10 上的正投影大致位于同一条直线上。这里，在第一连接部60在衬底10上的正投影为规则的图形的情况下，也即第一连接部60的正投影具有几何中心的情况下，第一连接部60正投影的几何中心可以与其相邻的两个第一过孔501正投影的几何中心大致位于同一条直线上。这样，上述第一弯曲部211和第二弯曲部221的相对面积被降低至0，从而可以进一步提高第一连接部60对第一数据线21和第二数据线22的数据信号Vdata的屏蔽效果，降低数据信号Vdata之间的串扰。
在一些实施例中，参见图8A、9B、10A、10B和11，显示基板200还包括设置于每个子像素的发光器件E中阳极层90和设置于每个子像素的像素驱动电路中的第六晶体管T6。第六晶体管T6的有源层76包括第一导体部分，第一连接部60与有源层76的第一导体部分，以及阳极层90电连接。也就是说，有源层76的第一导体部分与阳极层90通过第一连接部60电连接。
这里，第六晶体管T6的有源层76可以包括第一导体部分、沟道部分和第二导体部分，第一导体部分和第二导体部分通过沟道部分连接。第一导体部分和可以作为第六晶体管T6的源极和漏极中的一者，第二导体部分可以作为源极和漏极中的另一者。例如，参见图11，在第六晶体管T6为P型晶体管的情况下，与阳极层90连接的第一导电部分作为第六晶体管T6的漏极，第二导电部分作为第六晶体管T6的源极。
此外，参照图11及上文描述，第六晶体管T6和第五晶体管T5被配置响应于来自发光信号段EM的发光信号Vem，导通第一电压信号端VDD和第二电压信号端VSS之间的线路。这里可以称第六晶体管T6为第一发光控制晶体管，称第五晶体管T5为第二发光控制晶体管。
这样，第一连接部60与发光器件E电连接，发光器件E与第二电压信号端VSS电连接，从而在包括显示基板200的显示装置显示图像的过程中，第一连接部60因具有稳定的电压而可以屏蔽位于两列像素之间的第一信号线21和第二信号线22上的数据信号Vdata，降低数据信号Vdata之间的串扰，提高显示装置的显示效果。
还需要说明的是，由于上述显示基板200中第一连接部60与第一子电压信号线41、第一数据线21和第二数据线22同层设置，因此可以在无需增加额外的构图工艺的情况下，形成可用于降低第一数据线21和第二数据线22的数据信号Vdata之间串扰的第一连接部60。
需要说明的是，由于显示基板200所包括的膜层较多，因此图13中并未画出各子像素的发光器件E。示例性的，发光器件E设置于第一连接部60的 远离衬底10的一侧，发光器件E包括沿远离衬底方向设置的阳极层90、发光功能层和阴极层。图9B中以虚线轮廓的形式示出与第一连接部60电连接的阳极层90的至少一部分。
示例性的，参见8D和图9B，显示基板200还包括设置于有源层L A与第二源漏金属层L SD2之间的第三绝缘层IS3、第四绝缘层IS4和第五绝缘层IS5，第三绝缘层IS3、第四绝缘层IS4和第五绝缘层IS5沿远离衬底10方向依次设置。需要说明的是，图8D所示出的为第三绝缘层IS3、第四绝缘层IS4和第五绝缘层IS5所构成的叠层结构12的俯视图，这里为清晰示出叠层结构12中设置的各过孔位置，叠层结构12以透明形式示出。
基于此，在一些实施例中，显示基板200还包括第二连接部80。每个第二连接部80设置于第六晶体管T6的有源层76与相应的第一连接部60之间，且第二连接部80与第二子电压信号线42同层设置。
第二连接部80与第六晶体管T6的有源层76，及上述相应的第一连接部60电连接。也就是说，第一连接部60和阳极层90通过第二连接部80电连接。第二连接部80的设置便于第一连接部60和阳极层90的电连接。
示例性的，参见图8D、9B和14，叠层结构12中还设置有贯穿的第六过孔508，第二连接部80与第六晶体管T6的有源层76通过第六过孔508电连接。
发光功能层包括发光材料层，此外，还可以包括传输层(election transporting layer，简称ETL)、电子注入层(election injection layer，简称EIL)、空穴传输层(hole transporting layer，简称HTL)或空穴注入层(hole injection layer，简称HIL)中的至少一个。发光材料层可以为有机发光材料层，在这种情况下，包括显示基板200的显示装置为OLED(Organic Light-Emitting Diode，有机发光二极管)显示装置。发光材料层也可以是量子点发光材料层，在这种情况下，包括显示基板200的显示装置为QLED(Quantum Dot Light-Emitting Diode，量子点发光二极管)显示装置。
示例性的，参见图8H、9A和9B，显示基板200还包括设置于阳极层90和第一连接部60之间的第二绝缘层IS2。第二绝缘层IS2例如可以为第二平坦层。第二绝缘层IS2中设置有第二过孔504。第二过孔504在衬底10上的正投影位于第一连接部60在衬底10上的正投影之内。发光器件E的阳极层90与第一连接部60通过第二过孔504电连接。
在一些实施例中，参见图12，第一连接部60在衬底10上的正投影与第二连接部80在衬底10上的正投影具有重叠区域。这样，可以在重叠区域内 设置过孔，便于二者通过过孔连接。
示例性的，参见图8F、9A、9B和14，第一绝缘层IS1内还设置有第三过孔505，每个第三过孔505位于第一连接部60和第二连接部80在衬底10上的正投影的重叠部分内，第一连接部60和第二连接部80通过第三过孔505电连接。
在一些实施例中，参见图10A至11，在第一子像素31和第二子像素32均包括第五晶体管T5(可以称为第二发光控制晶体管)和电容器Cst的情况下，如图9B所示，第二子电压信号线42与第五晶体管T5的有源层75电连接。
示例性的，如图8D、9B和14所示，第三绝缘层IS3、第四绝缘层IS4和第五绝缘层IS5中设置有贯穿的第四过孔506，第五晶体管T5的有源层75通过第四过孔506与第二子电压信号线42电连接。
基于此，在一些实施例中，如图8D、9B和14所示，电容器Cst的第一极板A1设置于第四绝缘层IS4和第五绝缘层IS5之间，第二极板B1设置于第三绝缘层ISO3和第四绝缘层IS4之间。也就是说，第一极板A1位于第二子电压信号线42靠近衬底10的一侧，第二极板B1位于第一极板A1靠近衬底10的一侧。第一极板A1和第二极板B1相对设置，即二者的板面至少部分相对。第二子电压信号线42还与电容器Cst的第一极板A1电连接。示例性的，参见图9B，第五绝缘层IS5中设置有多个第五过孔507，第二子电压信号线42通过第五过孔507与电容器Cst的第一极板A1。这里，第二子电压信号线42通过一个第五过孔507与电容器Cst的第一极板A1；也可以如图14所示，第二子电压信号线42通过两个及以上的第五过孔507与电容器Cst的第一极板A1，以保证二者之间具有良好的电接触。
在一些实施例中，参见图7和8C，位于同一行的各子像素中，至少两个相邻的子像素的电容器Cst的第一极板A1之间电连接。这里，至少部分的第一子电压信号线41通过这些相互电连接的电容器Cst的第一极板A1可以实现并联连接，也就是说至少部分的第一电压信号线40并联连接，从而可以降低这些并联连接的第一电压信号线40的电阻，进而可以降低第一电压信号线40上的分压。
基于此，示例性的，如图7和8C所示，每行子像素中的多个子像素，例如每行子像素中的全部的子像素，的电容器Cst的第一极板A1之间相互电连接，形成多条沿第一方向OU延伸的辅助导电条101，多条辅助导电条101在衬底10上的正投影与多条第一子电压信号线41在衬底10上的正投影交错， 形成网格结构。这样可以使第一电压信号线40之间并联连接，从而进一步降低第一电压信号线40的电阻，进一步降低其上的分压。
下面将对显示基板200中的像素驱动电路中其他未介绍过的连接关系进行示例性的介绍。
参见图8E，第二源漏金属层L SD2还包括第三连接部110、第四连接部120和第五连接部130。参见图8D和15D，叠层结构12还包括贯穿的多个第七过孔510，第五绝缘层IS5还包括多个贯穿的第十过孔513，第四绝缘层IS4和第五绝缘层IS5包括多个贯穿的第十一过孔514。
参见图8A、15D和15E，第三连接部110的第一端通过第十过孔513与初始化电压信号线IL电连接，第三连接部110的第二端通过第七过孔510B与第一晶体管T1的有源层71的第一端电连接，这样第一晶体管T1的有源层71与初始化电压信号线IL可实现电连接。第四连接部120的第一端通过第七过孔510C与第一晶体管T1的有源层71的第二端电连接，第四连接部120的第二端通过第十一过孔514与电容器Cst的第二极板B1电连接，这样第一晶体管T1的有源层71可实现与电容器Cst的第二极板B1的电连接。需要说明的是，电容器Cst的第二极板B1与第三晶体管T3的栅极G3为一体成型的，电容器Cst的第二极板B1与第三晶体管T3的有源层73的正投影交叠部分作为第三晶体管T3的栅极G3。也就是说，第一晶体管T1的有源层71的第二端也电连接于第三晶体管T3的栅极G3。第一晶体管T1的栅极G1电连接于复位信号线RL。这里，可以将复位信号线RL与第一晶体管T1的有源层71正投影重叠的部分作为第一晶体管T1的栅极G1。
第二晶体管T2有源层72的第二端与第四连接部120的第一端通过第七过孔510C电连接，从而实现与电容器Cst的第二极板B1的电连接。第二晶体管T2有源层72的第一端与第三晶体管T3的有源层73的第二端电连接。第二晶体管T2的栅极G2与栅线GL电连接。
第三晶体管T3有源层73的第一端与第四晶体管T4的有源层74的第二端，以及第五晶体管T5的有源层75的第二端电连接。第三晶体管T3有源层73的第二端还与第六晶体管T6的有源层76的第一端电连接。
参见图8A、8E和15D至15F，第五连接部130的第一端通过第七过孔510E与第四晶体管T4的有源层74的第一端电连接。参见图8F和13，第一绝缘层IS1中还设置有第八过孔511。继续参见15D至15F，第五连接部130的第二端通过第八过孔511与第一数据线21或第二数据线22电连接。这样，第四晶体管T4的有源层74的第一端可通过第五连接部130电连接至第一数 据线21或第二数据线22上。第四晶体管T4的栅极G4电连接与栅线GL。这里，可以将栅线GL与第四晶体管T4的有源层74正投影重叠的部分作为第四晶体管T4的的栅极G4。
需要说明的是，参见图8E和8F，区域S P1为第一子像素31所在的区域，区域S P2为第二子像素32所在的区域。平面MN与衬底10所在的平面垂直，两个区域S P1和S P2大致沿平面MN在衬底10上的正投影对称分布。由于第一子像素31与位于其左侧的第一信号线21的连接，第二子像素32与位于其右侧的第二信号线22连接，可以将第一子像素31与第一信号线21的连接位置与第二子像素32与第二信号线22的连接位置设设置为非相同的，也即第一子像素31中的第八过孔511在区域S P1中的分布位置，与第二子像素32中的第八过孔511在区域S P2中的分布位置不相同。
在此基础上，示例性的，参图7、8E、10A和10B，第一子像素31中的第八过孔511与第二子像素32中的第八过孔511相对于平面MN为非镜面对称的。此外，可以将第一子像素31和第二子像素32的第五连接部130设置为非相同的结构，以便于第四晶体管T4与相应数据线的电连接。这样在制备时存在工艺偏差的情况下，例如各第八过孔511和/或第五连接部130向一侧发生偏移的情况下，可以避免上述结构相对于另一侧的偏移量加倍。这样能够减少工艺波动带来的尺寸误差。
第五晶体管T5的栅极G5电连接至发光信号线EML。这里，可以将发光信号线EML与第五晶体管T5的有源层75正投影重叠的部分作为第五晶体管T5的栅极G5。
第六晶体管T6的栅极G6电连接至发光信号线EML。这里，可以将发光信号线EML与第六晶体管T6的有源层76正投影重叠的部分作为第六晶体管T6的栅极G6。
参见图8A、15D和15E，第七晶体管T7的有源层77的第一端通过第十过孔513与第三连接部110的第一端电连接，从而通过第三连接部110与初始化电压信号线IL电连接。第七晶体管T7的有源层77的第二端与发光器件E的阳极层90电连接。需要说明的是，由于图7所示的显示面板200并未示出阳极层90，因此图中并未示出二者的连接关系。应理解的是，可以按实际需求自行设置第七晶体管T7的有源层77的第二端与发光器件E的阳极层90的连接结构。
在一些实施例中，参见图8C，第二删金属层L G2还包括遮挡部102，参见图8D、9B和15D，第五绝缘层IS5还包括多个第九过孔512。参见图15D和 15E，每个子像素所在区域S P内，遮挡部102通过第九过孔512与第二子电压信号线42电连接，遮挡部102在衬底20上的正投影与第一晶体管T1的有源层71、第二晶体管T2的有源层72、第四晶体管T4的有源层75和第七晶体管T7的有源层77在衬底10上的正投影部分重叠。这样在包括有显示基板200的显示装置显示图像时，遮挡部102可以起到遮光作用，从而降低上述晶体管的漏电流。
本公开的一些实施例提供了一种显示装置，包括如上所述的显示基板200。该显示装置的有益效果与上述显示基板200的有益效果相同，此处不再赘述。
参见图7、13和15A至15F，本公开的一些实施例提供一种显示基板的制备方法，可用于制备上述显示基板200。该制备方法包括如下S110至S140。
在S110中，参见图7，提供衬底10。
在S120中，参见图7，在衬底10上形成阵列排布的多个子像素的像素驱动电路。这里，参见图7，每列子像素包括多个第一子像素31和第二子像素32，第一子像素31和第二子像素32沿第二方向OV交替排列。
在S130中，参见图15E，在多个子像素的像素驱动电路的远离衬底10的一侧形成多条第二子电压信号线42，每条第二子电压信号线42在衬底10上的正投影位于相邻的两列子像素之间。需要说明的是，子像素的像素驱动电路等效电路图可参见图11，其所包括的第一晶体管T1至第七晶体管T7和存储电容器Cst的结构可参照上文中相关描述。
在S140中，参见图7和15F，在多条第二子电压信号线42的远离衬底10的一侧形成多条第一数据线21、多条第二数据线22和多条第一子电压信号线41。
这里，一条第一子电压信号线41和一条第二子电压信号线42构成一条第一电压信号线40，每条第一电压信号线40与至少一列子像素的像素驱动电路电连接，每条第一电压信号线40在衬底10上的正投影位于相邻两列子像素在衬底10上的正投影之间。此外，第一数据线21和第二数据线22沿第一方向交替排列。沿第一方向OU，一列子像素与一条第一数据线21和一条第二数据线22相邻，且该第一数据线21和该第二数据线22分别位于该列子像素的两侧，该列子像素的每个第一子像素31的像素驱动电路同与其相邻的第一数据线21电连接，该列子像素的每个第二子像素32的像素驱动电路同与其相邻的第二数据线22电连接。
该制备方法的有益效果和上述显示基板200的有益效果相同，此处不再赘述。
下面将对显示基板200的制备方法做整体的、示例性的介绍。在一些实施例中，该制备方法包括如下S210至S310。
在S210中，如图9B和15A所示，在衬底10上形成有源层L A。在一个子像素所对应的区域S P内，该有源层L A包括第一晶体管T1的有源层71、第二晶体管T2的有源层72、第三晶体管T3的有源层73、第四晶体管T4的有源层74、第五晶体管T5的有源层75、第六晶体管T6的有源层76和第七晶体管T7的有源层77。
示例性的，参见图9B，在S10之前，还包括在衬底10上形成无机缓冲层11。无机缓冲层11可以为单层结构，也可以为多层的层叠结构，例如为无机膜层和有机膜层的交替设置的层叠结构。
在S220中，如图9B所示，在有源层L A的远离衬底10的一侧形成第三绝缘层IS3。
在S230中，如图9B和15B所示，在第三绝缘层IS3的远离衬底10的一侧形成第一栅金属层L G1。在区域区域S P内，第一栅金属层L G1包括第一晶体管T1的栅极G1、第二晶体管T2的栅极G2、第三晶体管T3的栅极G3、第四晶体管T4的栅极G4、第五晶体管T5的栅极G5、第六晶体管T6的栅极G6和第七晶体管T7的栅极G7，以及电容器Cst的第二极板B1、复位信号线RL、栅线GL和发光信号线EML。
在S240中，如图9B所示，在第一栅金属层L G1的远离衬底10的一侧形成第四绝缘层IS4。
示例性的，参见图15D，在S240之后，上述制备方法还包括S241。在S241中，在第四绝缘层IS4中形成多个第十过孔513。
在S250中，如图9B和15C所示，在第四绝缘层IS4的远离衬底10的一侧形成第二栅金属层L G2，二栅金属层L G2包括电容器Cst的第一极板A1、初始化电压信号线IL和遮挡部102。
在S260中，如图9B所示，在第二栅金属层L G2的远离衬底10的一侧形成第五绝缘层IS5。
示例性的，如图15D所示，在S260之后，上述制备方法还包括S261至S263。在S261中，在第五绝缘层IS5中形成多个第五过孔507和多个第九过孔512。在S262中，在第四绝缘层IS4和第五绝缘层IS5中形成多个贯穿的第十一过孔514。在S263中，在第三绝缘层IS3、第四绝缘层IS4和第五绝缘层IS5中形成多个贯穿的第四过孔506、第六过孔508和第七过孔510(包括510B、510C和510E)。也就是说，在叠层结构12中形成多个贯穿的第四过 孔506、第六过孔508和第七过孔510。
需要说明的是，这里未对S261至S263的先后顺序做限定，可以按照一定的顺序进行S261至S263，也可以同时进行该三个步骤。
在S270中，参见图8E、9B和15E，在第五绝缘层IS5远离衬底10的一侧形成第二源漏金属层L SD2。第二源漏金属层L SD2可以包括第二子电压信号线42、第二连接部80、第三连接部110、第四连接部120和第五连接部130。
在S280中，如图8F和9B所示，在第二栅金属层L G2的远离衬底10的一侧形成第一绝缘层IS1。
示例性的，在第一绝缘层IS1包括第一平坦层502和钝化层503的情况下，S280包括：在第二栅金属层L G2的远离衬底10的一侧形成第一平坦层502，在第一平坦层502的远离衬底10的一侧形钝化层503，从而形成第一绝缘层IS1。
示例性的，参见图8F和13，在S280之后，该制备方法还包括S281。在S281中，在第一绝缘层IS1中形成多个第一过孔501、第三过孔505和第八过孔511。
在S290中，参见图8G和9B、15F，在第一绝缘层IS1的远离衬底10的一侧形成第一源漏金属层L SD1。第一源漏金属层L SD1包括多个第一连接部60、第一数据线21、第二数据线22和第一子电压信号线41。
在S300中，参见图8H和9B，在第一源漏金属层L SD1的远离衬底10的一侧形成第二绝缘层IS2。
示例性的，在S300后，该制备方法还包括S301。在S301中，在第二绝缘层IS2中形成多个第二过孔504。
在一些实施例中，在S300之后，上述制备方法还包括S310。
在S310中，参见图7、8H和9B，在第二绝缘层IS2的远离衬底10的一侧形成各发光器件E的阳极层90。
需要说明的是，上述过孔和膜层的结构和作用等可以参照前文的描述，由于前文已对其进行了详细描述，此处不再赘述。上述制备方法的S120中制备子像素的像素驱动电路，可参考上述S210至S250。
此外，上述膜层和过孔可以通过构图工艺形成，构图工艺可以包括光刻工艺，所述光刻工艺是指包括成膜(例如化学气相淀积成膜，Chemical Vapor Deposition，简称CVD)、曝光、显影等工艺过程且利用光刻胶、掩模板、曝光机等形成图案的工艺。
值得注意的是，在整个说明书中，所提到的“一些实施例”意味着所描述 的与该实施例相关的特定特征、结构或特性被包括在至少一个实施例中。因此，在整个说明书中，在各个地方出现的短语“在一些实施例中”不一定都指同一个实施例。此外，这些特定特征、结构或特性可以以任意合适的方式组合在一个或多个实施例中。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (17)

  1. 一种显示基板，包括：
    衬底；
    设置于所述衬底上的多条第一数据线和多条第二数据线，第一数据线和第二数据线沿第一方向交替排列；
    设置于所述衬底上的、阵列式布置的多个子像素，每相邻两列子像素之间设置有一条第一数据线和一条第二数据线；每列子像素包括多个第一子像素和第二子像素，第一子像素和第二子像素沿第二方向交替排列；沿第一方向，一列子像素与一条第一数据线和一条第二数据线相邻，且该第一数据线和该第二数据线分别位于该列子像素的两侧，该列子像素的每个第一子像素同与其相邻的第一数据线电连接，该列子像素的每个第二子像素同与其相邻的第二数据线电连接；及，
    设置于所述衬底上的多条第一电压信号线，每条第一电压信号线在所述衬底上的正投影位于相邻两列子像素之间的第一数据线和第二数据线在所述衬底上的正投影之间；所述第一电压信号线与至少一列子像素电连接；所述第一电压信号线包括：第一子电压信号线和第二子电压信号线，所述第二子电压信号线设置于所述第一子电压信号线的靠近所述衬底的一侧，并与所述第一子电压信号线电连接，所述第一子电压信号线与所述第一数据线和所述第二数据线同层设置。
  2. 根据权利要求1所述的显示基板，其中，沿所述第一方向，所述第一子像素与所述第二子像素交替布置。
  3. 根据权利要求1或2所述的显示基板，还包括设置于所述第一子电压信号线和所述第二子电压信号线之间的第一绝缘层，所述第一绝缘层包括多个第一过孔；所述第一子电压信号线和所述第二子电压信号线通过所述多个第一过孔中的至少一个第一过孔电连接；其中，位于相邻两列子像素之间的第一数据线、第二数据线和第一子电压信号线中，
    所述第一数据线中与所述第一过孔相邻的部分向远离所述第一过孔的方向弯曲，形成第一弯曲部；
    所述第二数据线中与所述第一过孔相邻的部分向远离所述第一过孔的方 向弯曲，形成第二弯曲部；
    所述第一弯曲部和所述第二弯曲部相对，形成容纳区域；
    所述第一子电压信号线包括经过所述第一过孔的导电部，所述导电部位于所述容纳区域内。
  4. 根据权利要求3所述的显示基板，其中，沿所述第一方向，所述导电部的尺寸大于所述第一子电压信号线的宽度；且，所述容纳空间的尺寸大于相邻两列子像素之间的第一数据线的非第一弯曲部的部分和第二数据线的非第二弯曲部的部分之间的间距。
  5. 根据权利要求3或4所述的显示基板，其中，沿所述第一方向，所述导电部与所述第一弯曲部之间的间距等于或大致等于所述导电部与所述第二弯曲部之间的间距。
  6. 根据权利要求3～5中任一项所述的显示基板，其中，沿所述第一方向，所述导电部与所述第一弯曲部之间的间距，等于或大致等于，所述第一数据线的非第一弯曲部的部分与所述第一子电压信号线的非导电部的部分之间的间距；和/或，
    沿所述第一方向，所述导电部与所述第二弯曲部之间的间距，等于或大致等于，所述第二数据线的非第二弯曲部的部分与所述第一子电压信号线的非导电部的部分之间的间距。
  7. 根据权利要求3～6任一项所述的显示基板，其中，与一列子像素相邻，且位于该列子像素沿所述第一方向的两侧的第一数据线和第二数据线中，所述第一弯曲部和所述第二弯曲部之间设置有第一连接部，所述第一连接部与所述第一子电压信号线同层设置。
  8. 根据权利要求7所述的显示基板，还包括：
    阳极层，设置于所述第一连接部远离所述衬底一侧；
    设置于所述衬底上的第一发光控制晶体管，所述第一发光控制晶体管包括有源层，所述有源层包括第一导体部分；所述第一连接部与所述第一导体部分，以及所述阳极层电连接。
  9. 根据权利要求8所述的显示基板，还包括：
    第二连接部，所述第二连接部设置于所述第一发光控制晶体管的有源层和所述第一连接部之间，并与所述第二子电压信号线同层设置；所述第二连接部与所述第一导体部分，以及所述第一连接部电连接。
  10. 根据权利要求8或9所述的显示基板，其中，沿所述第二方向，所述第一连接部的尺寸大于或等于所述第一弯曲部和所述第二弯曲部的长度。
  11. 根据权利要求10所述的显示基板，其中，所述第一连接部在所述衬底上的正投影与所述第二连接部在所述衬底上的正投影具有重叠区域。
  12. 根据权利要求4～11中任一项所示的显示基板，其中，所述第一过孔位于相邻两行子像素之间，且位于相邻两列子像素之间。
  13. 根据权利要求8～12中任一项所示的显示基板，其中，在所述显示基板还包括所述第一连接部的情况下，沿所述第二方向，所述第一连接部的位于所述第一连接部相邻的两个第一过孔的中心的连线两侧的两个部分的最大尺寸大致相等。
  14. 根据权利要求3所述的显示基板，其中，每个子像素包括：
    第二发光控制晶体管，所述第二子电压信号线与所述第二发光控制晶体管的有源层电连接；
    电容器，包括位于所述第二子电压信号线所在膜层靠近所述衬底一侧的第一极板，以及位于所述第一极板靠近所述衬底一侧的第二极板；所述第二子电压信号线还与所述第一极板电连接。
  15. 根据权利要求14所述的显示基板，其中，每行子像素中的多个子像素的电容器的第一极板之间相互电连接，形成沿所述第一方向延伸的多条辅助导电条，所述多条辅助导电条与所述多条第一子电压信号线在所述衬底上的正投影交错，形成网格结构。
  16. 一种显示装置，包括如权利要求1～15中任一项所述的显示基板。
  17. 一种显示基板的制备方法，包括：
    提供衬底；
    在所述衬底上形成阵列排布的多个子像素的像素驱动电路；每列子像素包括多个第一子像素和多个第二子像素，第一子像素和第二子像素沿第二方向交替排列；
    在所述多个子像素的像素驱动电路的远离所述衬底的一侧形成多条第二子电压信号线，每条第二子电压信号线在所述衬底上的正投影位于相邻的两列子像素之间；
    在所述多条第二子电压信号线的远离所述衬底的一侧形成多条第一数据线、多条第二数据线和多条第一子电压信号线；一条第一子电压信号线和所述一条第二子电压信号线构成一条第一电压信号线，每条第一电压信号线与至少一列子像素的像素驱动电路电连接；每条第一电压信号线在所述衬底上的正投影位于所述相邻两列子像素在所述衬底上的正投影之间；第一数据线和第二数据线沿第一方向交替排列；沿第一方向，一列子像素与一条第一数据线和一条第二数据线相邻，且该第一数据线和该第二数据线分别位于该列子像素的两侧，该列子像素的每个第一子像素的像素驱动电路同与其相邻的第一数据线电连接，该列子像素的每个第二子像素的像素驱动电路同与其相邻的第二数据线电连接。
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Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 14/11/2023)