WO2022165831A1 - 显示基板及显示装置 - Google Patents

显示基板及显示装置 Download PDF

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Publication number
WO2022165831A1
WO2022165831A1 PCT/CN2021/075966 CN2021075966W WO2022165831A1 WO 2022165831 A1 WO2022165831 A1 WO 2022165831A1 CN 2021075966 W CN2021075966 W CN 2021075966W WO 2022165831 A1 WO2022165831 A1 WO 2022165831A1
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WO
WIPO (PCT)
Prior art keywords
sub
pixels
electrically connected
pixel
data line
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Application number
PCT/CN2021/075966
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English (en)
French (fr)
Inventor
韩龙
董甜
王丽
Original Assignee
京东方科技集团股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to GB2217859.4A priority Critical patent/GB2611198A/en
Priority to CN202180000182.0A priority patent/CN115244701A/zh
Priority to US17/630,589 priority patent/US20230165076A1/en
Priority to PCT/CN2021/075966 priority patent/WO2022165831A1/zh
Publication of WO2022165831A1 publication Critical patent/WO2022165831A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/33—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being semiconductor devices, e.g. diodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/04—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of a single character by selection from a plurality of characters, or by composing the character by combination of individual elements, e.g. segments using a combination of such display devices for composing words, rows or the like, in a frame with fixed character positions
    • G09G3/06—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of a single character by selection from a plurality of characters, or by composing the character by combination of individual elements, e.g. segments using a combination of such display devices for composing words, rows or the like, in a frame with fixed character positions using controlled light sources
    • G09G3/12—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of a single character by selection from a plurality of characters, or by composing the character by combination of individual elements, e.g. segments using a combination of such display devices for composing words, rows or the like, in a frame with fixed character positions using controlled light sources using electroluminescent elements
    • G09G3/14—Semiconductor devices, e.g. diodes
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
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    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0202—Addressing of scan or signal lines
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0297—Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
    • G—PHYSICS
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    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/16—Calculation or use of calculated indices related to luminance levels in display data
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/126—Shielding, e.g. light-blocking means over the TFTs

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a display substrate and a display device.
  • the refresh rate of the display device refers to the number of times the display screen can display new images per second.
  • the display screen can display 60 times per second at a refresh rate of 60Hz. new picture.
  • the refresh rate of the display device is relatively high, for example, 75Hz, 90Hz, 120Hz or higher, it can avoid blurring and smearing of the picture when displaying high-speed moving pictures, and improve picture quality and user visual experience.
  • a display substrate has a plurality of sub-pixels arranged in an array, each column of sub-pixels includes a plurality of first sub-pixels and second sub-pixels, and the first sub-pixels and the second sub-pixels are alternately arranged along the second direction.
  • the display substrate includes: a substrate, a first source-drain metal layer disposed on the substrate, and a second source-drain metal layer disposed between the substrate and the first source-drain metal layer.
  • the first source-drain metal layer includes a plurality of first data lines and a plurality of second data lines, the first data lines and the second data lines are alternately arranged along the first direction, and every two adjacent columns of sub-pixels A first data line and a second data line are arranged between them; along the first direction, a column of sub-pixels corresponds to a first data line and a second data line respectively located on both sides of the column of sub-pixels.
  • Each of the first sub-pixels is electrically connected to the corresponding first data line
  • each second sub-pixel of the column of sub-pixels is electrically connected to the corresponding second data line.
  • the second source-drain metal layer includes a plurality of first connection parts and a plurality of second connection parts.
  • Each first sub-pixel is electrically connected to the corresponding first data line through a first connection portion; the first end of each first connection portion is electrically connected to the corresponding first data line, and the second end is electrically connected to the corresponding first data line
  • the pixel driving circuits of the sub-pixels are electrically connected.
  • Each second sub-pixel is electrically connected to the corresponding second data line through a second connection part; the first end of each second connection part is electrically connected to the corresponding second data line, and the second end is connected to the corresponding second data line.
  • the pixel driving circuits of the sub-pixels are electrically connected.
  • the first connection line between the second end of the first connection part and the second end of the second connection part is substantially parallel to the second direction, and the first end of the first connection part is located in the first connection part.
  • the first end of the second connecting portion is located on the second side of the first connecting line.
  • the display substrate further includes an active layer disposed between the substrate and the second source-drain metal layer.
  • Each sub-pixel further includes a writing transistor, and the writing transistor includes a fourth active pattern disposed in the active layer; along the above-mentioned first direction, the fourth portion of the writing transistor in each adjacent two sub-pixels has a fourth active pattern.
  • the distances between the source patterns are approximately equal, and along the second direction, the distances between the fourth active patterns of the writing transistors in every two adjacent sub-pixels are approximately equal.
  • the second end of the first connection portion is electrically connected to the fourth active pattern of the corresponding writing transistor; in each second subpixel, the second end of the second connection portion is electrically connected to the fourth active pattern of the corresponding write transistor;
  • the fourth active patterns of the corresponding write transistors are electrically connected.
  • each row of sub-pixels includes a plurality of first sub-pixels and a plurality of second sub-pixels, and the first sub-pixels and the second sub-pixels are alternately arranged along the first direction.
  • the second connection line between the second end of the first connection part and the second end of the second connection part is substantially parallel to the first direction; the first end of the first connection part is located in the On the side of the second connection line away from the corresponding fourth active pattern, the first end of the second connection portion is located on the side of the second connection line close to the corresponding fourth active pattern.
  • the display substrate further includes a first insulating layer disposed between the second source-drain metal layer and the active layer, and a plurality of first pass through layers are disposed in the first insulating layer. hole and a plurality of second vias.
  • the second end of the first connection portion is electrically connected to the fourth active pattern of the corresponding writing transistor through a corresponding one first via hole; in each second subpixel , the second end of the second connection portion is electrically connected to the fourth active pattern of the corresponding writing transistor through a corresponding second via hole.
  • the first insulating layer includes a first sub-insulating layer and a second sub-insulating layer
  • the second sub-insulating layer is disposed between the first sub-insulating layer and the substrate
  • the display substrate further includes a second gate metal layer disposed between the first sub-insulating layer and the second sub-insulating layer;
  • the second gate metal layer includes a plurality of first shielding parts and a plurality of second The shielding part, each sub-pixel is provided with a first shielding part and a second shielding part.
  • the orthographic projections of the first connecting portion and the second blocking portion on the substrate have an overlapping area, and the orthographic projections of the first connecting portion and the first blocking portion on the substrate
  • the projection part does not have an overlapping area
  • the second end of the first connection part and the orthographic projection of the second blocking part on the substrate do not have an overlapping area
  • the second connection The orthographic projection of the second connecting part and the first shielding part on the substrate has an overlapping area
  • the orthographic projection of the second connecting part and the second shielding part on the substrate does not have an overlapping area
  • the second connecting part does not have an overlapping area.
  • the second end of the portion and the first shielding portion do not have an overlapping area.
  • the first shielding parts and the second shielding parts are alternately arranged, and the adjacent first shielding parts and the second shielding parts located in different sub-pixels are adjacent.
  • the two shielding parts are integrally formed.
  • the largest dimension of each first connecting portion in the extending direction thereof is greater than the largest dimension of each second connecting portion in the extending direction thereof.
  • the area of the first end of each first connection portion is larger than the area of the second end thereof, and/or the area of the first end of each second connection portion is larger than the area of the second end thereof.
  • each first data line includes a first body and a plurality of fifth connection parts; the plurality of fifth connection parts are disposed on a side of the first body close to the corresponding first sub-pixel, and are arranged along the second direction; each fifth connection portion is electrically connected between the first body and the first end of the corresponding first connection portion.
  • Each second data line includes a second body and a plurality of sixth connection parts; the plurality of sixth connection parts are disposed on a side of the second body close to the corresponding second sub-pixel, and are arranged along the second The directions are arranged; each sixth connection part is electrically connected between the second body and the first end of the corresponding second connection part.
  • the display substrate further includes a second insulating layer disposed between the first source-drain metal layer and the second source-drain metal layer, wherein a plurality of A third via hole and a plurality of fourth via holes.
  • Each fifth connection part is electrically connected to the first end of the corresponding first connection part through a corresponding third via hole
  • each sixth connection part is electrically connected to the corresponding second connection part through a corresponding fourth via hole The first end is electrically connected.
  • the display substrate further includes a plurality of first voltage signal lines, and an orthographic projection of each first voltage signal line on the substrate is located at a first data line between every two adjacent columns of sub-pixels Between the orthographic projection of the second data line on the substrate, the first voltage signal line is electrically connected to at least one column of sub-pixels.
  • the first voltage signal line includes: a first sub-voltage signal line disposed in the first source-drain metal layer, and a second sub-voltage signal line disposed in the second source-drain metal layer, the The first sub-voltage signal line is electrically connected to the second sub-voltage signal line.
  • a plurality of fifth via holes are provided in the second insulating layer; the first sub-voltage signal line and the second sub-voltage The signal line is electrically connected through at least one fifth via hole in the plurality of fifth via holes; wherein the first data line, the second data line and the first sub-voltage signal line located between the sub-pixels in two adjacent columns are , the portion of the first data line adjacent to the fifth via is bent in a direction away from the fifth via to form a first curved portion, and the portion of the second data line adjacent to the fifth via is A part is bent away from the fifth via hole to form a second bent part.
  • the first curved portion and the second curved portion are opposite to form an accommodation area, the first sub-voltage signal line includes a conductive portion passing through the fifth via hole, and the conductive portion is located in the accommodation area; Along the first direction, the size of the conductive portion is larger than the width of the first sub-voltage signal line.
  • the first curved portion is connected to the second data line.
  • a seventh connection part is arranged between the bending parts, and the seventh connection part is arranged in the same layer as the first sub-voltage signal line.
  • the display substrate further includes an anode layer disposed on a side of the first source-drain metal layer away from the substrate.
  • Each sub-pixel also includes a first emission control transistor including a sixth active pattern disposed in the active layer, the sixth active pattern including a first conductor portion; the seventh connection The portion is electrically connected to the first conductor portion and the anode layer.
  • the first side of the first connection line is a side of the first connection line that is close to the first data line corresponding to the column of sub-pixels
  • the second side of the first connection line is the One side of the first connection line is close to the second data line corresponding to the column of sub-pixels.
  • a display device in another aspect, includes the display substrate according to any one of the above embodiments.
  • FIG. 1 is an equivalent circuit diagram of a 7T1C pixel driving circuit according to some embodiments
  • FIG. 2 is a signal timing diagram of the pixel driving circuit shown in FIG. 1;
  • FIG. 3 is a schematic structural diagram of a driving architecture according to some embodiments.
  • FIG. 4 is a signal timing diagram of the driving architecture shown in FIG. 3;
  • FIG. 5 is a schematic structural diagram of another driving system according to some embodiments.
  • FIG. 6 is a signal timing diagram of the driving system shown in FIG. 5;
  • FIG. 7 is a schematic top view of a display substrate according to some embodiments.
  • FIG. 8A to 8H are schematic top views of each film layer of the display substrate shown in FIG. 7;
  • 9A is a schematic structural diagram of a sub-pixel according to some embodiments.
  • FIG. 9B is a schematic cross-sectional view of the sub-pixel in FIG. 9A along the dotted line AA';
  • 10A is a schematic structural diagram of another sub-pixel according to some embodiments.
  • FIG. 10B is a schematic cross-sectional view of the sub-pixel in FIG. 10A along the dotted line BB';
  • FIG. 11 is an equivalent circuit diagram of a portion in the region S of the display substrate shown in FIG. 7;
  • Fig. 12 is a partial enlarged view of the inner portion of the region S' of the display substrate shown in Fig. 7;
  • 13A to 13F are schematic diagrams illustrating the connection relationship between layers of a display substrate according to some embodiments.
  • first and second are only used for descriptive purposes, and should not be construed as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Thus, a feature defined as “first” or “second” may expressly or implicitly include one or more of that feature.
  • plural means two or more.
  • connection and its derivatives may be used.
  • the term “connected” may be used in describing some embodiments to indicate that two or more components are in direct physical or electrical contact with each other, or that two or more components are in indirect physical or electrical contact with each other connect.
  • the embodiments disclosed herein are not necessarily limited by the content herein.
  • a and/or B includes the following three combinations: A only, B only, and a combination of A and B.
  • the display device When the display device operates at a higher refresh rate (eg, 75 Hz, 90 Hz, 120 Hz or higher), the displayed picture quality and the user's visual experience can be improved.
  • a higher refresh frequency will shorten the data writing and compensation time of each sub-pixel in the display device, which may lead to insufficient charging rate of each sub-pixel and a decrease in the compensation effect of the threshold voltage, which will reduce the display effect of the display device. reduce.
  • the display device includes a plurality of sub-pixels, each sub-pixel has a pixel driving circuit with the 7T1C structure, and the pixel driving circuit includes seven transistors (the first transistors T1 to seventh transistor T7) and a capacitor Cst.
  • the seven transistors can be P-type transistors, that is, when the gate receives a low-level signal, it is turned on, and when it receives a high-level signal, it is turned off; the seven transistors can also be N-type transistors, that is, when the gate receives a low-level signal, it is turned off; It is turned on when a high-level signal is received, and it is turned off when a low-level signal is received.
  • the electrical connection point of the second electrode of the first transistor T1, the second electrode plate B1 of the capacitor Cst, and the gate of the third transistor T3 is referred to as the first node N1, and the first node N1 , the voltages of the second plate B1 of the capacitor Cst and the gate of the third transistor T3 are equal; connect the voltage between the second pole of the fifth transistor T5, the second pole of the fourth transistor T4 and the first pole of the third transistor T3
  • the electrical connection point is called the second node N2;
  • the electrical connection node of the second pole of the third transistor T3, the first pole of the second transistor T2 and the first pole of the sixth transistor T6 is called the third node N3.
  • the third transistor T3 is used as a driving transistor in the pixel driving circuit.
  • the channel width to length ratio of the driving transistor is usually larger than that of other switching transistors, that is, the channel width to length ratio of the third transistor T3 is usually larger than that of the first transistor T1 and the second transistor.
  • the light-emitting brightness of the light-emitting device E corresponding to each sub-pixel is related to the magnitude of the driving current I flowing therethrough.
  • the driving current I is related to the gate and source voltage difference Vgs of the driving transistor and the threshold voltage Vth of the driving transistor, that is, when the voltage difference Vgs is constant, each light-emitting
  • the light-emitting brightness of the device E is mainly affected by the threshold voltage Vth of the corresponding driving transistor.
  • the threshold voltage Vth of the driving transistor in the sub-pixels of the display device is not equal, for example, with the increase of the working time, the threshold voltage Vth of the driving transistor will occur.
  • the display device may exhibit uneven display brightness.
  • the transistors included in the pixel driving circuit are P-type transistors as an example, that is, the first transistor T1 to the seventh transistor T7 are turned on when the signal received by their gates is low, and the signals received by their gates are high. Usually due.
  • the gate of the first transistor T1 (also referred to as the first reset transistor) is electrically connected to the reset signal terminal RESET, the first electrode is electrically connected to the initialization voltage signal terminal INIT, and the second electrode is electrically connected to the first node N1.
  • the gate of the second transistor T2 (also referred to as a compensation transistor) is electrically connected to the scan signal terminal GATE, the first electrode is electrically connected to the third node N3, and the second electrode is electrically connected to the first node N1.
  • the gate of the third transistor T3 (also referred to as a driving transistor) is electrically connected to the first node N1, the first electrode is electrically connected to the second node N2, the second electrode is electrically connected to the third node N3, and the fourth transistor T4 ( The gate of the transistor, which may also be referred to as a write transistor), is electrically connected to the scan signal terminal GATE, the first electrode is electrically connected to the data signal terminal DATA, and the second electrode is electrically connected to the second node N2.
  • the gate of the fifth transistor T5 (also referred to as the second light-emitting control transistor) is electrically connected to the light-emitting signal terminal EM, the first electrode is electrically connected to the first voltage signal terminal VDD, and the second electrode is electrically connected to the second node N2.
  • the gate of the sixth transistor T6 (also referred to as the first light-emitting control transistor) is electrically connected to the light-emitting signal terminal EM, the first electrode is electrically connected to the third node N3, and the second electrode is electrically connected to the anode of the light-emitting device E of the sub-pixel. connect.
  • the gate of the seventh transistor T7 (also referred to as the second reset transistor) is electrically connected to the reset signal terminal RESET, the first electrode is electrically connected to the initialization voltage signal terminal INIT, and the second electrode is electrically connected to the anode of the light-emitting device E of the sub-pixel electrical connection.
  • the first plate A1 of the capacitor Cst is electrically connected to the first voltage signal terminal VDD, and the second plate B1 is electrically connected to the first node N1.
  • the anode of the light-emitting device E of the sub-pixel is electrically connected to the above-mentioned pixel driving circuit, and the cathode is electrically connected to the second voltage signal terminal VSS.
  • the working process of the pixel driving circuit of the 7T1C is introduced in conjunction with the signal timing diagram shown in FIG. 2.
  • the working process of the pixel driving circuit includes a reset phase P1, a writing and compensation phase P2, and a light-emitting phase P3 .
  • the reset signal Vre of the reset signal terminal RESET transmitted to the gate of the first transistor T1 and the gate of the seventh transistor T7 is at a low level, and the first transistor T1 and the seventh transistor T7 are turned on.
  • the first transistor T1 transmits the initialization voltage signal Vinit from the initialization voltage signal terminal INIT to the first node N1 to connect the second plate B1 of the capacitor Cst and the gate of the third transistor T3 (also referred to as the driving transistor T3 )
  • the voltage of the second plate B1 is reset, and the voltage of the second plate B1 is equal to the voltage Vi of the initialization voltage signal Vinit.
  • the seventh transistor T7 transmits the initialization voltage signal Vinit from the initialization voltage signal terminal INIT to the anode of the light emitting device E to reset the anode voltage of the light emitting device E.
  • the initialization voltage signal Vinit is at a low level in the reset phase P1, and the voltage of the first node N1 is at a low voltage, so the third transistor T3 whose gate is electrically connected to the first node N1 is turned on.
  • the initialization voltage signal Vinit may be a constant low voltage signal.
  • the reset signal Vre is at a high level, and the first transistor T1 and the seventh transistor T7 are turned off.
  • the voltage of the first node N1 is equal to the voltage of the second plate B1 of the capacitor Cst, that is, the voltage of the first node N1 is still a low voltage, and the third transistor T3 is maintained in an on state.
  • the scan signal Vgate of the scan signal terminal GATE transmitted to the gate of the fourth transistor T4 and the gate of the second transistor T2 is at a low level, and the fourth transistor T4 and the second transistor T2 are turned on.
  • the fourth transistor T4 transmits the data signal Vdata from the data signal terminal DATA to the third transistor T3.
  • the data signal Vdata is transferred to the second transistor T2 through the turned-on third transistor T3, and then transferred to the first node N1 through the turned-on second transistor T2, so as to be written to the capacitor Cst.
  • the process in which the data signal Vdata is written to the capacitor Cst is actually the charging process of the second plate B1 of the capacitor Cst (ie, the process in which the voltage of the second plate B1 gradually increases).
  • the voltage of the first node N1 increases from In one stage (ie, the reset stage P1 ), Vi gradually increases until the voltage of the first node N1 rises to Vdata+Vth, and the third transistor T3 is turned off, where Vth is the threshold voltage value of the third transistor T3 .
  • the voltage of the second plate B1 of the capacitor Cst is equal to Vdata+Vth, so that the threshold voltage value Vth of the third transistor T3 is compensated for the data signal written in the capacitor Cst.
  • duration 1H of the active level of the scan signal Vgate is the time required for a row of sub-pixels to complete the writing of the data signal Vdata.
  • the light-emitting signal Vem transmitted from the light-emitting signal terminal EM to the gate of the fifth transistor T5 and the gate of the sixth transistor T6 is at a low level, and the fifth transistor T5 and the sixth transistor T6 are turned on.
  • the source voltage Vs of the third transistor T3 is equal to the first voltage Vdd of the first voltage signal terminal VDD
  • the gate voltage Vg of the third transistor T3 is equal to Vdata+Vth, where the first voltage Vdd is greater than Vdata+Vth, so the third transistor T3 is turned on. In this way, a current path is formed between the first voltage signal terminal VDD and the second voltage signal terminal VSS, so that the light emitting device E can emit light.
  • the magnitude of the driving current I has nothing to do with the threshold voltage value Vth of the third transistor T3, so that the influence of the threshold voltage drift of the third transistor T3 on the driving current I can be avoided, and the luminance of the display device can be more uniform.
  • the time of each frame is shortened, resulting in a corresponding shortening of the writing and compensation stage P2 in one frame, that is, As a result, the duration of the active level of the scan signal is shortened.
  • This may cause the data writing time of the sub-pixels of the display device (that is, the charging time of the sub-pixels) and the threshold voltage compensation time to be short, so that the charging rate of the sub-pixels is insufficient, and the threshold voltage compensation effect is poor, which affects the picture of the display device. quality and user visual experience.
  • a driving method in which two data lines DL are arranged to jointly provide the data signal Vdata to a column of sub-pixels can be used to solve the problem.
  • FIGS. 3 to 6 the above-mentioned display device with a 7T1C pixel driving circuit, and the scheme of adopting this driving method will be exemplarily introduced.
  • the display device includes a plurality of sub-pixels PX, a plurality of data lines DL (eg, DL1 to DL8 ) and a plurality of gate lines GL (eg, GL1 to GL4 ), and these sub-pixels PX may be arranged in an array.
  • Each column of sub-pixels corresponds to two data lines DL, and the two data lines DL are respectively disposed on the left and right sides of the column of sub-pixels.
  • each adjacent two sub-pixels PX are respectively electrically connected to different data lines DL in the data lines DL on the left and right sides, that is, along the extension direction of the sub-pixels in the column, the sub-pixels located in the same column are electrically connected to each other.
  • the pixels PX are alternately electrically connected to the data lines DL on the left and right sides.
  • the sub-pixels located in the same row can be electrically connected to the same gate line GL, where the gate line GL can provide the scan signal Vgate to the row of sub-pixels electrically connected to it, so that the data signal Vdata from the data line DL is transmitted into the corresponding sub-pixels.
  • the writing of the data signal Vdata is realized.
  • the sub-pixels PX located in the same row may be alternately electrically connected to the data lines DL on the left and right sides thereof (as shown in FIG. 3 and FIG. 5 ), or both It is electrically connected to the data line DL on its left side or its right side.
  • the display device may further include a plurality of source driving signal lines S (eg, S1 to S4 ) and a source driver 100 , and the plurality of source driving signal lines S are electrically connected to the source driver 100 .
  • the source driver 100 is used for providing the data signal Vdata of the image to be displayed by the display device, and these data signals Vdata can be provided to each sub-pixel PX through the source driving signal line S and the data line DL.
  • Each adjacent plurality of data lines DL are electrically connected to the same source driving signal line S, in this way, the source driver 100 can pass the source driving signal line S to a plurality of data lines that are electrically connected to the source driving signal line S
  • the line DL transmits the data signal Vdata, so that the number of interfaces provided on the source driver 100 for outputting the data signal Vdata can be reduced.
  • a switch SW is disposed between each data line DL and its corresponding source driving signal line S, so that the source driving signal line S can be time-division multiplexed by controlling the opening and closing of the corresponding switch SW.
  • control electrodes of the switches SW corresponding to the same source driving signal line S and located on the left side of the sub-pixels in one column of the switches SW are all electrically connected to the same control signal line MUX (for example, MUX1 or MUX2 in FIG. 3 ).
  • the control signal line MUX can control the opening and closing of the switch SW corresponding to the data line DL, so as to control the transmission of the data signal Vdata from the source driving signal line S to the specific data line DL in a certain frame.
  • the data signal Vdata is written into the corresponding sub-pixel PX.
  • the switch SW here may comprise N-type or P-type transistors.
  • the switch SW includes an N-type transistor, the switch SW is turned on when the signal from the control signal line MUX is at a high level, and turned off when the signal is at a low level.
  • the switch SW includes a P-type transistor, the switch SW is turned on when the signal from the control signal line MUX is at a low level, and turned off when the signal is at a high level.
  • the structure of the display device shown in Fig. 2 and Fig. 4 will be taken as examples below to introduce the driving process of the display device, and the pixel driving circuit in the sub-pixel in the display device may refer to Fig. 1 .
  • the second transistor T2 and the fourth transistor T4 in the pixel driving circuit, and the switch SW are P-type transistors as an example, and along the extension direction of a row of sub-pixels, the sub-pixels PX located in the same row are alternately located on the left and right sides of the sub-pixels PX in the same row.
  • the data line DL is electrically connected.
  • every two adjacent data lines DL are electrically connected to the same source driving signal line S.
  • the source driving signal line S1 is electrically connected to the data line DL1 and the data line DL2, that is to say, the source driver 100 can connect the source driving signal line S1, the data line DL1 and the data line DL2 to the first column sub-pixel PC1 through the source driving signal line S1, the data line DL1 and the data line DL2.
  • a data signal Vdata is provided.
  • the source driving signal line S2 is electrically connected to the data line DL3 and the data line DL4, and the source driver 100 can provide data signals to the second column sub-pixel PC2 through the source driving signal line S2, the data line DL3 and the data line DL4 Vdata;
  • the source driving signal line S3 is electrically connected to the data line DL5 and the data line DL6, and the source driver 100 can provide the data signal Vdata to the third column sub-pixel PC3 through the source driving signal line S3, the data line DL5 and the data line DL6
  • the source drive signal line S4 is electrically connected to the data line DL7 and the data line DL8, and the source driver 100 can provide the data signal Vdata to the fourth column sub-pixel PC4 through the source drive signal line S4, the data line DL7 and the data line DL8.
  • the gate of the thin film transistor is electrically connected to the control signal line MUX1.
  • the gates of the thin film transistors in the switches SW electrically connected to the data lines DL1, DL3, DL5 and DL7 are all electrically connected to the control signal line MUX1, and the thin film transistors in the switches SW corresponding to the data lines DL2, DL4, DL6 and DL8 The gates are all electrically connected to the control signal line MUX2.
  • the control signal Vumx1 transmitted via the control signal line MUX1 is at a low level, and the thin film transistor in the switch SW electrically connected to the control signal line MUX1 is turned on; via the control The control signal Vumx2 transmitted by the signal line MUX2 is at a high level, and the thin film transistor in the switch SW electrically connected to the control signal line MUX2 is turned off.
  • the scan signal Vgate1 transmitted via the scan signal line GL1 is at a low level, and the second transistor T2 and the fourth transistor T4 in each sub-pixel PX of the first sub-pixel row PR1 are turned on; the scan signal transmitted via the scan signal line GL2 Vgate2 is at a high level, and the second transistor T2 and the fourth transistor T4 in each sub-pixel PX in the second sub-pixel row PR2 are turned off.
  • the data signal Vdata transmitted via the source driving signal line S1 is written in the sub-pixels located in the first row sub-image PR1 and the first column sub-pixel PC1
  • the data signal Vdata transmitted via the source driving signal line S3 is written in It is located in the sub-pixels of the sub-image PR1 in the first row and the sub-pixel PC3 in the third column.
  • the control signal Vumx1 transmitted through the control signal line MUX1 is at a high level, and each switch SW electrically connected to the control signal line MUX1 is turned off; the control signal Vumx2 transmitted through the control signal line MUX2 is at a low level , each switch SW electrically connected to the control signal line MUX2 is turned on.
  • the scan signal Vgate1 transmitted through the scan signal line GL1 and the scan signal Vgate2 transmitted through the scan signal line GL2 are both low level, located in the second row of the sub-pixels PR1 and the sub-pixels PR2 in the second row of the sub-pixels PX. Both the transistor T2 and the fourth transistor T4 are turned on.
  • the data signal Vdata transmitted via the source driving signal line S1 is written into the sub-pixels located in the second row sub-image PR2 and the first column sub-image PC1 by the data line DL2, and the data signal Vdata transmitted via the source driving signal line S2
  • the sub-pixels located in the first row sub-image PR1 and the second column sub-image PC2 are written by the data line DL4, and the data signal Vdata transmitted through the source driving signal line S3 is written by the data line DL6 in the second row sub-image PR2,
  • the data signal Vdata transmitted via the source driving signal line S4 is written into the sub-pixels of the first row sub-image PR1 and the fourth column sub-image PC4 by the data line DL8.
  • the duration of the active level of the scan signal Vgate of each sub-pixel PX is 2H, that is, the duration of the active level of the scan signal Vgate of each sub-pixel PX is the same as the duration of the two rows of sub-pixels.
  • the time required to complete the writing of the data signal Vdata is equal. In this way, the time of the writing and compensation phase P2 can be increased, so that the charging time of the sub-pixels PX is sufficient, and the threshold voltage compensation effect can be improved, so that the display effect of the display device at a high refresh frequency can be improved.
  • every four adjacent data lines DL are electrically connected to the same source driving signal line S.
  • the source driving signal line S1 is electrically connected to the data lines DL1 to DL4
  • the source data line S2 is electrically connected to the data lines DL5 to DL8.
  • each of the data lines DL with serial number 1 is electrically connected to the thin film transistors in the switches SW.
  • the gates are all electrically connected to the control signal line MUX1
  • the gates of the thin film transistors in each switch SW electrically connected to the data line DL with the serial number 2 are all electrically connected to the control signal line MUX2, and the data line with the serial number of 3 is electrically connected.
  • the gates of the thin film transistors in the switches SW electrically connected to the DL are all electrically connected to the control signal line MUX3, and the gates of the thin film transistors in the switches SW electrically connected to each data line DL numbered 4 are all electrically connected to the control signal line.
  • MUX4 electrical connection.
  • the source driver 100 can transmit data signals to the four data lines DL electrically connected to the source driving signal line S through the same source driving signal line S Vdata, so that the corresponding four-column sub-pixels realize the writing of the data signal Vdata.
  • the control signal Vumx1 transmitted via the control signal line MUX1 is at a low level, and the thin film transistor in the switch SW electrically connected to the control signal line MUX1 is turned on; via
  • the control signals Vumx2 to Vumx4 transmitted by the control signal lines MUX2 to MUX4 are all high level, and the thin film transistors in the switches SW electrically connected to the control signal lines MUX2 to MUX4 are all turned off.
  • the scan signal Vgate1 transmitted via the scan signal line GL1 is at a low level, and the second transistor T2 and the fourth transistor T4 in each sub-pixel PX in the first sub-pixel row PR1 are turned on; the scan signal Vgate1 transmitted via the scan signal lines GL2 to GL4
  • the scan signals Vgate2 to Vgate4 are all high level, and the second transistor T2 and the fourth transistor T4 in each of the sub-pixels PX located in the second pixel row PR2 to the fourth pixel row PR4 are both turned off.
  • the data signal Vdata transmitted via the source driving signal line S1 is written in the sub-pixels located in the first row sub-image PR1 and the first column sub-pixel PC1
  • the data signal Vdata transmitted via the source driving signal line S2 is written in It is located in the sub-pixels of the sub-image PR1 in the first row and the sub-pixel PC3 in the third column.
  • the control signal Vumx2 transmitted via the control signal line MUX2 is at a low level, and the thin film transistor in the switch SW electrically connected to the control signal line MUX2 is turned on;
  • the control signals Vumx1 , Vumx3 and Vumx4 are all at a high level, and the thin film transistors in the switches SW electrically connected to the control signal lines MUX1 , MUX3 and MUX4 are all turned off.
  • the scan signals Vgate1 and Vgate2 transmitted via the scan signal lines GL1 and GL2 are at a low level, and the second transistor T2 and the fourth transistor T4 in each sub-pixel PX of the first sub-pixel row PR1 and the second sub-pixel row PR2 are turned on.
  • the scan signals Vgate3 and Vgate4 transmitted via the scan signal lines GL3 and GL4 are both high level, the second transistor T2 and the fourth transistor T4 in each sub-pixel PX of the third pixel row PR3 and the fourth pixel row PR4 all expire.
  • the data signal Vdata transmitted via the source driving signal line S1 is written into the sub-pixels located in the sub-image PR2 in the second row and the sub-pixel PC1 in the first column
  • the data signal Vdata transmitted via the source driving signal line S2 is written in It is located in the sub-pixels of the sub-image PR2 in the second row and the sub-pixel PC3 in the third column.
  • the control signal Vumx3 transmitted via the control signal line MUX3 is at a low level, and the thin film transistor in the switch SW electrically connected to the control signal line MUX3 is turned on;
  • the control signals Vumx1 , Vumx2 and Vumx4 are all at a high level, and the thin film transistors in the switches SW electrically connected to the control signal lines MUX1 , MUX2 and MUX4 are all turned off.
  • the scan signals Vgate1 to Vgate3 transmitted through the scan signal lines GL1 to GL3 are at low level, and the second transistor T2 and the fourth transistor T4 in each of the subpixels PX in the first to third subpixel rows PR1 to PR3 are turned on.
  • the scan signal Vgate4 transmitted via the scan signal line GL4 is at a high level, and both the second transistor T2 and the fourth transistor T4 in each sub-pixel PX in the fourth pixel row PR4 are turned off.
  • the data signal Vdata transmitted via the source driving signal line S1 is written into the sub-pixels located in the sub-image PR2 in the second row and the sub-pixel PC2 in the second column, and the data signal Vdata transmitted via the source driving signal line S2 is written in It is located in the sub-pixels of the sub-image PR2 in the second row and the sub-pixel PC4 in the fourth column.
  • the control signal Vumx4 transmitted via the control signal line MUX4 is at a low level, and the thin film transistor in the switch SW electrically connected to the control signal line MUX4 is turned on; the control signals transmitted via the control signal lines MUX1 to MUX3 Vumx1 to Vumx3 are all at a high level, and the thin film transistors in the switches SW electrically connected to the control signal lines MUX1 to MUX3 are all turned off.
  • the scan signals Vgate1 to Vgate4 transmitted through the scan signal lines GL1 to GL4 are all low level, and the second transistor T2 and the fourth transistor T4 in each sub-pixel PX of the first sub-pixel row PR1 to the fourth sub-pixel row PR4 are turned on.
  • the data signal Vdata transmitted via the source driving signal line S1 is written into the sub-pixels located in the first row sub-image PR2 and the second column sub-pixel PC2 and the sub-pixels located in the third row sub-image PR3 and the second column sub-pixel PC2
  • the data signal Vdata transmitted via the source driving signal line S2 is written into the sub-pixels located in the first row of sub-images PR1 and the fourth column of sub-pixels PC4 and the sub-pixels located in the third row of sub-images PR3 and the fourth column of sub-pixels PC4 middle.
  • the duration of the active level of the scanning signal Vgate of each sub-pixel PX is 2H, and the time of the writing and compensation phase P2 can also be increased, so that the charging time of the sub-pixel PX is sufficient and the threshold voltage compensation effect is improved.
  • the data signal Vdata is not the data signal actually required in its light-emitting phase.
  • the duration of the active level of the scan signal is 2H, before the active level of the scan signal Vgate3 corresponding to the above two sub-pixels ends, the two sub-pixels will be written into a new data signal Vdata again.
  • the incoming data signal Vdata is the data signal required for the light-emitting stage.
  • the display device adopts the above-mentioned driving method of jointly providing the data signal Vdata to a column of sub-pixels through two data lines DL
  • the number of data lines DL provided in the display device will be doubled, and the distribution density of the data lines DL will increase.
  • the distance between the sub-pixel and its corresponding two data lines that is, the two data lines adjacent to the pixel and located on both sides of the sub-pixel
  • the data line electrically connected to the sub-pixel will generate a large parasitic capacitance with the pixel driving circuit in the sub-pixel. This may affect the light emission of the sub-pixel, thereby possibly reducing the display effect of the display device.
  • the display substrate 1000 includes a substrate 10 and a plurality of sub-pixels disposed on the substrate 10 and arranged in an array.
  • the first direction OU is defined as the direction perpendicular or substantially perpendicular to the extension direction of a column of sub-pixels, that is, the first direction OU is the row direction in which a plurality of sub-pixels are arranged in an array.
  • the direction in which the direction is parallel or substantially parallel is the second direction OV, that is, the second direction OV is the column direction in which a plurality of sub-pixels are arranged in an array.
  • Each column of sub-pixels includes a plurality of first sub-pixels 31 and second sub-pixels 32, and the first sub-pixels 31 and the second sub-pixels 32 are alternately arranged along the second direction OV.
  • FIG. 11 is an equivalent circuit diagram of the portion of the display substrate 1000 shown in FIG. 7 located in the region S, where the display substrate 1000 includes two first sub-pixels 31 and two second sub-pixels 32 arranged in a matrix in the region S Take an example to illustrate.
  • Each of the first sub-pixels 31 and each of the second sub-pixels 32 has a pixel driving circuit of a 7T1C structure, and the pixel driving circuit includes a first transistor T1 to a seventh transistor T7 and a capacitor Cst.
  • the electrical connection relationship between the components in the pixel driving circuit and the working process of the driving circuit can be referred to the above description, which will not be repeated here.
  • the display panel 1000 includes an active layer LA , a first gate metal layer L G1 , a second gate metal layer LG2 and a first source-drain metal layer L SD1 sequentially disposed on the substrate 10 .
  • the area S P1 is an area where a first sub-pixel 31 is located
  • the area S P2 is an area where a second sub-pixel 32 is located.
  • the active layer LA includes an active pattern 71 of the first transistor T1, an active pattern 72 of the second transistor T2, an active pattern 73 of the third transistor T3, a fourth The active pattern 74 of the transistor T4, the active pattern 75 of the fifth transistor T5, the active pattern 76 of the sixth transistor T6, and the active pattern 77 of the seventh transistor T7.
  • the first gate metal layer L G1 includes the gate G1 of the first transistor T1 , the gate G2 of the second transistor T2 , the gate G3 of the third transistor T3 , and the fourth transistor The gate G4 of T4, the gate G5 of the fifth transistor T5, the gate G6 of the sixth transistor T6, and the gate G7 of the seventh transistor T7.
  • the first gate metal layer LG1 further includes the second plate B1 of the capacitor Cst, the reset signal line RL, the gate line GL and the light emitting signal line EML.
  • the reset signal line RL is configured to transmit the reset signal Vre from the reset signal terminal RESET to the corresponding sub-pixel
  • the gate line GL is configured to transmit the scan signal Vgate from the scan signal terminal GATE to the corresponding sub-pixel, and emits light
  • the signal line EML is configured to transmit the light-emitting signal Vem from the light-emitting signal terminal EM to the corresponding sub-pixel.
  • the overlapping portion of the first gate metal layer LG1 and the orthographic projection of the active pattern 71 of the first transistor T1 on the substrate 10 can be used as the gate G1 of the first transistor T1, and the first The overlapping portion of the gate metal layer LG1 and the orthographic projection of the active pattern 72 of the second transistor T2 on the substrate 10 can be used as the gate G2 of the second transistor T2, and the gate G2 of the first gate metal layer LG1 and the third transistor T3.
  • the overlapping portion of the orthographic projection of the active pattern 73 on the substrate 10 can be used as the gate G3 of the third transistor T3, and the positive portion of the first gate metal layer LG1 and the active pattern 74 of the fourth transistor T4 on the substrate 10.
  • the overlapping portion of the projection can be used as the gate G4 of the fourth transistor T4, and the overlapping portion of the orthographic projection of the first gate metal layer LG1 and the active pattern 75 of the fifth transistor T5 on the substrate 10 can be used as the gate G4 of the fifth transistor T5.
  • the overlapping portion of the gate G5, the first gate metal layer L G1 and the orthographic projection of the active pattern 76 of the sixth transistor T6 on the substrate 10 can be used as the gate G6 of the sixth transistor T6, the first gate metal layer L G1
  • the overlapping portion with the orthographic projection of the active pattern 77 of the seventh transistor T7 on the substrate 10 may serve as the gate G7 of the seventh transistor T7.
  • the second gate metal layer LG2 includes the first plate A1 of the capacitor Cst and the initialization voltage signal line IL.
  • the initialization voltage signal line is configured to transmit the initialization voltage signal Vin from the initialization voltage signal terminal INIT to the corresponding sub-pixel.
  • the first source-drain metal layer L SD1 includes a plurality of first data lines 21 and a plurality of second data lines 22, and the first data lines 21 and the second data lines 22 are Alternately arranged in one direction OU, a first data line 21 and a second data line 22 are disposed between every two adjacent columns of sub-pixels.
  • a column of sub-pixels corresponds to a first data line 21 and a second data line 22 respectively located on both sides thereof, and each first sub-pixel 31 of the column of sub-pixels corresponds to a corresponding first data line 21 is electrically connected, and each second sub-pixel 32 of the column of sub-pixels is electrically connected to the corresponding second data line 22 .
  • connection relationship between the pixel driving circuit of each sub-pixel and the signal line in the display substrate 1000 will be exemplarily described.
  • the fourth transistor T4 of the first sub-pixel 31 is electrically connected to the same first data line 21
  • the fourth transistor T4 of the second sub-pixel 32 is electrically connected to the same second data line 22 . That is, the first sub-pixel 31 receives the data signal Vdata through the first data line 21
  • the second sub-pixel 32 receives the data signal Vdata through the second data line 22 .
  • the gates of the second transistor T2 and the fourth transistor T4 of the sub-pixels located in the same row are electrically connected to the same-level scan signal terminal GATE (for example, the Nth-level scan signal terminal GATE N or the (N+1)th scan signal terminal GATE) through the same gate line GL. stage scan signal terminal GATA N+1 ).
  • the gates of the fifth transistor T5 and the sixth transistor T6 of the sub-pixels located in the same row are electrically connected to the same level light emitting signal terminal EM (for example, the Nth level light emitting signal terminal EM N or the (N+1th level) through the same light emitting signal line EML. ) light-emitting signal terminal EM N+1 ).
  • EM level light emitting signal terminal
  • the gates of the first transistor T1 and the seventh transistor T7 of the sub-pixels located in the same row are electrically connected to the upper-stage scanning signal terminal GATE through the same reset signal line RL.
  • the scan signal Vgate output by the previous scan signal terminal GATE is used as the reset signal Vre, that is, the previous scan signal terminal GATE is used as the reset signal terminal RESET of the current sub-pixel.
  • the scan signal Vgate output from the Nth-level scan signal terminal GATE N serves as a sub-pixel electrically connected to the (N+1)th-level scan signal terminal GATA N+1 by the second transistor T2 and the fourth transistor T4 the reset signal Vre.
  • the first electrodes of the first transistor T1 and the seventh transistor T7 of the sub-pixels in the same row are electrically connected to the initialization voltage signal terminal INIT through the same initialization voltage signal line IL.
  • the initialization voltage signal Vin output by the initialization voltage signal terminal INIT may be a constant voltage signal.
  • the initialization voltage signal Vin in FIG. 11 may be a constant low voltage signal.
  • the display substrate 1000 further includes a second source-drain metal layer L SD2 disposed between the substrate 10 and the first source-drain metal layer L SD1 , such as In the case of the second gate metal layer L G2 included in the display substrate 1000, the second source-drain metal layer L SD2 is disposed between the second gate metal layer L G2 and the first source-drain metal layer L SD1 .
  • the second source-drain metal layer L SD2 includes a plurality of first connection parts 131 and a plurality of second connection parts 132 .
  • the first connecting portion 131 is disposed in the first region S P1 where the first sub-pixel 31 is located
  • the second connecting portion 132 is disposed in the first region S P2 where the second sub-pixel 32 is located.
  • each first sub-pixel 31 is electrically connected to the corresponding first data line 21 through a first connection portion 131
  • the first end 1311 of each first connection portion 131 is electrically connected to the corresponding first data line 21 is electrically connected
  • the second end 1312 of the first connection portion 131 is electrically connected to the pixel driving circuit of the corresponding first sub-pixel 31 .
  • Each second sub-pixel 32 is electrically connected to the corresponding second data line 22 through a second connection portion 132, and the first end 1321 of each second connection portion 132 is electrically connected to the corresponding second data line 22.
  • the second ends 1322 of the two connection parts 132 are electrically connected to the pixel driving circuits of the corresponding second sub-pixels 32 .
  • the first connection line CD between the second end 1312 of the first connection portion 131 and the second end 1322 of the second connection portion 132 is substantially parallel to the second direction OV, and the first end 1311 of the first connection portion 131 Located on the first side of the first connection line CD, the first side may be, for example, the side of the first connection line CD that is close to the first data line 21 corresponding to the column of sub-pixels, and the first end 1321 of the second connection portion 132 is located at The second side of the first connection line CD, for example, the second side may be a side of the first connection line CD that is close to the second data line 22 corresponding to the column of sub-pixels.
  • the first connection portion 131 is located in the second source-drain metal layer L SD2
  • the second data line 22 adjacent to the first sub-pixel 31 is located in the first source-drain metal layer L SD1 . Therefore, the first A connecting portion 131 and the second data line 22 are located in different layers. In this way, even if the orthographic distance between the second end 1312 of the first connection part 131 and the second data line 22 on the substrate 10 is relatively close, since the first connection part 131 and the second data line 22 are located in different film layers , the parasitic capacitance generated between the two is small.
  • the first end 1311 of the first connection portion 131 is far away from the second data line 22 , so the first end 1311 of the first connection portion 131 is electrically connected to the first data line 21 adjacent to the first sub-pixel 31 .
  • the distance from the second data line 22 is relatively far, so that no large parasitic capacitance is generated between the first end 1311 of the first connection portion 131 and the electrical connection and the second data line 22 .
  • the second connection portion 32 is located in the second source-drain metal layer L SD2 , and the first data line 21 adjacent to the second sub-pixel 32 is located in the first source-drain metal layer L SD , Therefore, the second connection portion 132 and the first data line 21 are located in different layers. In this way, even if the orthographic distance between the second end 1322 of the second connection part 132 and the first data line 21 on the substrate 10 is relatively close, since the second connection part 132 and the first data line 21 are located in different film layers , the parasitic capacitance generated between the two is small.
  • the first end 1321 of the second connection portion 132 is far away from the second data line 22 , so the first end 1321 of the second connection portion 132 is electrically connected to the second data line 22 adjacent to the second sub-pixel 32 .
  • the distance from the first data line 21 is relatively far, so that no large parasitic capacitance is generated between the first end 1321 of the second connection portion 132 and the electrical connection and the first data line 21 .
  • the parasitic capacitance between the data line that is not electrically connected to the sub-pixel and the pixel driving circuit in the sub-pixel can be reduced, so that the parasitic capacitance pair can be reduced.
  • the light emission of the sub-pixels has an influence, so that the display effect of the display device can be improved.
  • the display substrate 1000 in the case where the display substrate 1000 includes an active layer LA disposed between the substrate 10 and the second source-drain metal layer L SD2 , the display substrate 1000 further includes an active layer LA disposed between the substrate 10 and the second source-drain metal layer L SD2.
  • the inorganic buffer layer 11 may be a single-layer structure or a multi-layer stack structure, for example, a stack structure in which inorganic film layers and organic film layers are alternately arranged.
  • each sub-pixel includes a fourth transistor T4 (which may be referred to as a writing transistor), along the first direction OU, every two adjacent sub-pixels
  • the spacing between the fourth active patterns 74 of the fourth transistor T4 in the pixel is approximately equal, and along the second direction OV, the spacing between the fourth active patterns 74 of the fourth transistor T4 in every two adjacent sub-pixels is approximately equal equal. That is, the positions of each fourth active pattern 74 in the region SP where the corresponding sub-pixel is located are approximately the same.
  • the second terminal 1312 of the first connection part 131 is electrically connected to the fourth active pattern 74 of the corresponding fourth transistor T4; in each second subpixel 32, the second connection The second end 1322 of the portion 132 is electrically connected to the fourth active pattern 74 of the corresponding fourth transistor T4.
  • the second source-drain metal layer L SD2 further includes a plurality of third connection parts 110 and a plurality of fourth connection parts 120 .
  • the active pattern 71 of the first transistor T1 and the active pattern 77 of the seventh transistor T7 are electrically connected to the initialization voltage signal line IL through a corresponding third connection part 110, so as to realize the first transistor T1 , and the electrical connection of the seventh transistor T7 to the initialization voltage signal line IL.
  • each row of sub-pixels includes a plurality of first sub-pixels 31 and a plurality of second sub-pixels 32 , and the first sub-pixels 31 and the second sub-pixels 32 are alternately arranged along the first direction OU .
  • the second connection line EF between the second end 1312 of the first connection part 131 and the second end 1322 of the second connection part 132 is substantially parallel to the first direction OU.
  • the first end 1311 of the first connection part 131 is located on the side of the second connection line EF away from the corresponding fourth active pattern 74
  • the first end 1321 of the second connection part 132 is located on the side of the second connection line EF close to the corresponding fourth active pattern 74 .
  • One side of the active pattern 74 is one side of the active pattern 74 .
  • the distance between the first connection portion 131 and the fourth connection portion 120 can be increased in the second sub-pixel 32 , thereby reducing the short circuit of the pixel driving circuit in the first sub-pixel 31 risks of.
  • the distance between the second connection part 132 and the third connection part 110 can be increased, so that the risk of short circuit of the pixel driving circuit in the second sub-pixel 32 can be reduced.
  • the display substrate 1000 further includes a first insulating layer IS1 disposed between the second source-drain metal layer L SD2 and the active layer LA, in the first insulating layer IS1 A plurality of first via holes 701 and a plurality of second via holes 702 are provided.
  • the second end 1312 of the first connection part 131 is electrically connected to the fourth active pattern 74 of the corresponding fourth transistor T4 through a corresponding one of the first via holes 701 .
  • the second end 1322 of the second connection part 132 is electrically connected to the fourth active pattern 74 of the corresponding fourth transistor T4 through a corresponding one of the second via holes 702 .
  • the first insulating layer IS1 includes a first sub-insulating layer IS11 and a second sub-insulating layer IS12, and the second sub-insulating layer IS12 is disposed on the first sub-insulating layer IS11 close to the substrate. 10 side.
  • the active layer LA further includes a plurality of first active connection parts 711 , a plurality of second active connection parts 712 and a plurality of third active connection parts.
  • the fourth active pattern 74 of the fourth transistor T4 is electrically connected to the second end 1312 of the first connection part 131 through a corresponding one of the first active connection parts 711;
  • the fourth active pattern 74 of the fourth transistor T4 is electrically connected to the second end 1322 of the second connection portion 132 through a corresponding one of the first active connection portions 711 .
  • the first active pattern 71 of the first transistor T1 (may be referred to as a first reset transistor) and the second active pattern 72 of the second transistor T2 (may be referred to as a compensation transistor) pass through a corresponding one of the first
  • the two active connection parts 712 are electrically connected, and a corresponding third active connection part 713 is connected between the first active pattern 71 of the first transistor T1 and the seventh active pattern 77 of the seventh transistor T7 .
  • the second gate metal layer LG2 is disposed between the first sub-insulating layer IS11 and the second sub-insulating layer IS12. 8A, 8C and 13C, the second gate metal layer LG2 further includes a plurality of first shielding parts 1021 and a plurality of second shielding parts 1022, and each sub-pixel is provided with a first shielding part 1021 and a second shielding part 1022.
  • the orthographic projection of the first shielding portion 1021 and the corresponding first active connecting portion 711 on the substrate 10 has an overlapping area
  • the second shielding portion 1022 and the corresponding third active connecting portion 713 are also underlined.
  • the orthographic projection on the base 10 has an overlapping area
  • the orthographic projection of the second blocking portion 1022 and the corresponding second active connecting portion 712 on the substrate 10 has an overlapping area.
  • the first connection part 131 can shield the corresponding first active connection part 711 and the third active connection part 713 from light, thereby reducing the first transistor T1 and the second active connection part 713
  • the leakage current of the transistor T2 and the seventh transistor T7; the second shielding portion 1022 can shield the corresponding second active connection portion 712 from light, thereby reducing the leakage current of the fourth transistor T4.
  • each first sub-pixel 31 the orthographic projections of the first connecting portion 131 and the second shielding portion 1022 on the substrate 10 have an overlapping area, and the first connecting portion 131 and the first shielding portion 1021 are on the substrate 10.
  • the orthographic portion on the substrate 10 does not have an overlapping area, and the orthographic projection of the second end 1312 of the first connecting portion 131 and the second blocking portion 1022 on the substrate 10 does not have an overlapping area.
  • the orthographic projections of the second connecting portion 132 and the first blocking portion 1021 on the substrate 10 have an overlapping area, and the second connecting portion 132 and the second blocking portion 1022 on the substrate 10 have an overlapping area.
  • the orthographic projection part does not have an overlapping area, and the second end 1322 of the second connecting part 132 and the first blocking part 1021 do not have an overlapping area.
  • the first shielding portion 1021 and the second shielding portion 1022 can avoid the first via hole 701 provided in the first insulating layer IS1, so that the first shielding portion 1021 and the second shielding portion 1021 can be avoided.
  • the part 1022 affects the electrical connection between the first connection part 131 and the corresponding fourth active pattern 74; in the second sub-pixel 32, the second shielding part 1022 can avoid the second pass through the first insulating layer IS1.
  • the holes 702 are formed, so that the first shielding part 1021 and the second shielding part 1022 can avoid the influence on the electrical connection between the second connection part 132 and the corresponding fourth active pattern 74 .
  • first shielding portion 1021 and the second shielding portion 1022 may be formed of the same material and through the same patterning process, thereby simplifying the manufacturing process.
  • the first shielding parts 1021 and the second shielding parts 1022 are alternately arranged, and the first shielding parts 1021 and the second shielding parts 1021 and 1022 that are adjacent and located in different sub-pixels respectively.
  • the two shielding parts 1022 are integrally formed.
  • the first insulating layer IS1 further includes a third sub-insulating layer IS13 disposed on a side of the second sub-insulating layer IS12 close to the substrate 10 .
  • the above-mentioned first gate metal layer LG1 is disposed between the second sub-insulating layer IS12 and the third sub-insulating layer IS13.
  • the first insulating layer IS1 is further provided with a seventh via hole 510 (for example, including 510A and 510B), the first sub-insulating layer IS11 is provided with an eighth via hole 513, and the first sub-insulating layer IS11 is provided with an eighth via hole 513.
  • a sub-insulating layer IS11 and the second sub-insulating layer IS12 are provided with a penetrating ninth via hole 514 (ie, the ninth via hole 514 penetrates the first sub-insulating layer IS11 and the second sub-insulating layer IS12).
  • One end of the third connection portion 110 is electrically connected to the active pattern 77 of the seventh transistor T7 through the seventh via hole 510A, and the other end of the third connection portion 110 is electrically connected to the initialization voltage signal line IL through the eighth via hole 513 .
  • One end of the fourth connection portion 120 is electrically connected to the active pattern 71 of the first transistor T1 and the second active pattern 72 of the second transistor T2 through the seventh via hole 510B, and the other end of the fourth connection portion 120 is electrically connected to the active pattern 71 of the first transistor T1 and the second active pattern 72 of the second transistor T2.
  • the nine via holes 514 are electrically connected to the third active pattern 73 of the third transistor T3 (which may be referred to as a driving transistor).
  • the largest dimension of each first connecting portion 131 in the extending direction thereof is larger than the largest dimension of each second connecting portion 132 in the extending direction thereof.
  • the area of the first end 1311 of each first connection portion 131 is larger than the area of the second end 1312 thereof, and/or, the area of each second connection portion 132
  • the area of the first end 1321 is larger than the area of the second end 1322. Therefore, it is favorable for the first connection portion 131 to be electrically connected to the corresponding first data line 21 , and for the second connection portion 132 to be electrically connected to the corresponding second data line 22 .
  • each of the first connection parts 131 further includes a first transition sub-part 1313, the first transition sub-part 1313 is connected between the first end 1311 and the second end 1312 of the first connection part 131, the first The size of the transition sub-portion 1313 in the direction perpendicular to the extension direction of the first connection part 131 is smaller than the size of the first end 1311 and the second end 1312 of the first connection part 131 in the direction perpendicular to the extension direction of the first connection part 131 . size.
  • each second connection part 132 further includes a second transition sub-part 1323, the second transition sub-part 1323 is connected between the first end 1321 and the second end 1322 of the second connection part 132, the second transition sub-part 1323 is The dimension of the portion 1323 in the direction perpendicular to the extending direction of the second connection portion 132 is smaller than the dimensions of the first and second ends 1321 and 1322 of the second connection portion 132 in the direction perpendicular to the extending direction of the first connection portion 132 .
  • each of the first data lines 21 includes a first body 211 and a plurality of fifth connection parts 212 .
  • a plurality of fifth connection parts 212 are disposed on a side of the first body 211 close to the corresponding first sub-pixel 31 and are arranged along the second direction OV.
  • Each fifth connection part 212 is electrically connected to the first body through 211 and the corresponding between the first ends 1311 of the first connecting parts 131 .
  • Each of the second data lines 22 includes a second body 221 and a plurality of sixth connection parts 222 .
  • a plurality of sixth connection parts 222 are disposed on a side of the second body 221 close to the corresponding second sub-pixels 32 and are arranged along the second direction OV.
  • Each sixth connection part 222 is electrically connected to the second body 221 and the corresponding second sub-pixel 32 between the first ends 1321 of the second connecting portion 132 .
  • first data line 21 is electrically connected to the corresponding first connection portion 131 through the plurality of fifth connection portions 212, which can increase the electrical contact area between the first data line 21 and the first connection portion 131, which is beneficial to the electrical connection between the two. connect.
  • second data line 22 is electrically connected to the corresponding second connection portion 132 through the plurality of sixth connection portions 222, which can increase the electrical contact area between the second data line 22 and the second connection portion 132, which is beneficial to the connection between the two. electrical connection.
  • the display substrate 1000 further includes a second insulating layer IS2 disposed between the first source-drain metal layer L SD1 and the second source-drain metal layer L SD2 , and the second insulating layer IS2 is disposed in the second insulating layer IS2 .
  • Each fifth connection portion 212 is electrically connected to the first end 1311 of the corresponding first connection portion 131 through a corresponding third via hole 801
  • each sixth connection portion 222 is electrically connected to a corresponding first connection portion 131 through a corresponding fourth via hole 802 .
  • the first end 1321 of the second connection portion 132 is electrically connected.
  • the display substrate 1000 further includes a plurality of first voltage signal lines 40 disposed on the substrate 10 , and the orthographic projection of each first voltage signal line 40 on the substrate 10 , Between the orthographic projections of the first data line 21 and the second data line 22 on the substrate 10 between every two adjacent columns of sub-pixels, each of the first voltage signal lines 40 is electrically connected to at least one column of sub-pixels.
  • the first electrodes of the fifth transistors T5 of the sub-pixels located in the same column may be electrically connected to the first voltage signal terminal VDD through the same first voltage signal line 40 .
  • the first voltage signal line 40 may be used to transmit the first voltage signal Vdd from the first voltage signal terminal VDD to the sub-pixels electrically connected thereto.
  • each first voltage signal line 40 includes a first sub-voltage signal line 41 disposed in the first source-drain metal layer L SD1 , and a first sub-voltage signal line 41 disposed in the second
  • the second sub-voltage signal line 42 and the first sub-voltage signal line 41 in the source-drain metal layer L SD2 are electrically connected to the second sub-voltage signal line 42 .
  • a plurality of fifth via holes 501 are provided in the second insulating layer IS2, and the first sub-voltage signal line 41 and the second sub-voltage signal line 42 pass through at least one fifth via hole 501 in the plurality of fifth via holes 501 electrical connection.
  • the first voltage signal line 40 can transmit the first voltage signal Vdd as a constant voltage signal to the sub-pixels electrically connected thereto, that is, the first sub-voltage signal line 41 and the second sub-voltage signal line 42
  • the voltages on both can be stable voltages.
  • the first sub-voltage signal line 41 arranged in the same layer as the first data line 21 and the second data line 22 and located between them has a stable voltage
  • the data signal Vdata transmitted on the first data line 21 and the second data line 22 can be shielded.
  • the parasitic capacitance between the adjacent first data lines 21 and the second data lines 22 can be reduced by the first self-voltage signal line 41 between them, thereby reducing the The crosstalk between the small data signals Vdata improves the display effect of the display device.
  • the first sub-voltage signal line 41 , the first data line 21 and the second data line 22 may be formed through the same patterning process, so that they are arranged in the same layer.
  • the orthographic projections of the first sub-voltage signal line 41 and the second sub-voltage signal line 42 on the substrate 10 overlap or partially overlap.
  • the first via hole 501 can be disposed in the overlapping or overlapping area of the orthographic projections of the two, so that the two can be connected through the first via hole 501 .
  • the first data is bent in a direction away from the fifth via hole 501 to form the first curved portion 213; the portion of the second data line 22 adjacent to the fifth via hole 501 is bent away from the fifth via hole 501
  • the direction of the fifth via hole 501 is bent to form the second bent portion 223 .
  • the first curved portion 213 and the second curved portion 223 are opposite to each other to form a receiving area A.
  • the first sub-voltage signal line 41 includes a conductive portion 411 passing through the fifth via hole 501 , and the conductive portion 411 is located in the accommodating area A. As shown in FIG.
  • the size D1 of the conductive portion 411 may be larger than the width D0 of the first sub-voltage signal line 41, so that the first via hole 501 has a larger size along the first direction OU, thereby ensuring the first The electrical contact between the first sub-voltage signal line 41 and the second sub-voltage signal line 41 is good.
  • the first curved portion 213 and the second curved portion 223 are set away from each other.
  • the display substrate 1000 further includes a seventh connection portion 60 disposed between the first curved portion 213 and the second curved portion 223 disposed away from each other, and the seventh connection portion 60 is disposed in the first source-drain metal layer L SD1 .
  • the seventh connection part 60 is configured to shield the data signals Vdata of the first data line 21 and the second data line 22 adjacent to the column of sub-pixels and located on both sides of the column of sub-pixels along the first direction OU.
  • the orthographic projection of the seventh connection portion 60 on the substrate 10 may be a regular figure or an irregular figure.
  • the display substrate 1000 further includes an anode layer disposed on the side of the first source-drain metal layer L SD1 away from the substrate 10 , and the anode pattern of each sub-pixel can be disposed in the anode layer.
  • the pixel driving circuit of each sub-pixel includes a sixth transistor T6 (which may be referred to as a first light-emitting transistor)
  • the sixth active pattern 76 of the sixth transistor T6 includes a first conductor portion
  • the above-mentioned seventh connection portion 60 is electrically connected to the first conductor portion of the corresponding active pattern 76 and the corresponding anode pattern.
  • the display substrate 1000 further includes a light-emitting device E disposed in each sub-pixel, the light-emitting device E further includes a cathode pattern, and a light-emitting functional layer disposed between the anode pattern and the cathode pattern.
  • the anode pattern of the light emitting device E may be electrically connected to the second voltage signal terminal VSS.
  • the anode pattern of the light emitting device E can be electrically connected to the second voltage signal terminal VSS through the second voltage signal line 50 to receive the signal from the second voltage signal terminal VSS The second voltage signal Vss.
  • the light-emitting functional layer includes a light-emitting material layer, and may also include a transport layer (election transporting layer, abbreviated as ETL), an electron injection layer (election injection layer, abbreviated as EIL), a hole transport layer (hole transporting layer, abbreviated as HTL) or an empty layer. At least one of the hole injection layers (HIL for short).
  • the light-emitting material layer may be an organic light-emitting material layer.
  • the display device including the display substrate 200 is an OLED (Organic Light-Emitting Diode, organic light-emitting diode) display device.
  • the light-emitting material layer may also be a quantum dot light-emitting material layer, in this case, the display device including the display substrate 200 is a QLED (Quantum Dot Light-Emitting Diode, quantum dot light-emitting diode) display device.
  • QLED Quantum Dot Light-Emitting Diode, quantum dot light-emitting diode
  • the sixth active pattern 76 of the sixth transistor T6 may include a first conductor part, a channel part and a second conductor part, and the first conductor part and the second conductor part are connected through the channel part.
  • the first conductor portion may serve as one of the source and the drain of the sixth transistor T6, and the second conductor portion may serve as the other of the source and the drain.
  • the sixth transistor T6 is a P-type transistor
  • the first conductive portion connected to the anode layer 90 serves as the drain of the sixth transistor T6, and the second conductive portion serves as the source of the sixth transistor T6 .
  • the seventh connection portion 60 is electrically connected to the light-emitting device E, and the light-emitting device E is electrically connected to the second voltage signal terminal VSS, so that during the process of displaying an image by the display device including the display substrate 200, the seventh connection is
  • the portion 60 can shield the data signal Vdata on the first signal line 21 and the second signal line 22 between two columns of pixels due to its stable voltage, thereby reducing crosstalk between the data signals Vdata and improving the display effect of the display device.
  • the seventh connection portion 60 in the above-mentioned display substrate 200 is arranged in the same layer as the first sub-voltage signal line 41 , the first data line 21 and the second data line 22 , no additional patterning process is required.
  • a seventh connection portion 60 that can be used to reduce crosstalk between the data signals Vdata of the first data line 21 and the second data line 22 is formed.
  • the display substrate 1000 further includes a third insulating layer IS3 disposed on the side of the first source-drain metal layer L SD1 away from the substrate 10, and the third insulating layer IS3 is provided with a third insulating layer IS3.
  • Ten via holes 504 , the seventh connection part 60 is electrically connected to the anode pattern of the light emitting device E through the tenth via hole 504 .
  • the display substrate 1000 further includes an eighth connection part 80 disposed in the second source-drain metal layer LSD2.
  • An eleventh via hole 508 is further provided in the first insulating layer IS1, and a twelfth via hole 505 is further provided in the second insulating layer IS2.
  • One end of the eighth connection portion 80 is electrically connected to the sixth active pattern 76 of the sixth transistor T6 through the eleventh via hole 508
  • the other end of the eighth connection portion 80 is electrically connected to the seventh connection portion 60 through the twelfth via hole 505 . electrical connection, so that the electrical connection between the sixth active pattern 76 of the sixth transistor T6 and the anode pattern of the light emitting device E can be realized.
  • a display device including the above-mentioned display substrate 1000 .
  • the beneficial effects of the display device are the same as those of the above-mentioned display substrate 1000 , which will not be repeated here.

Abstract

一种显示基板，具有多个子像素，每列子像素包括沿交替排列的第一子像素和第二子像素。显示基板包括依次设置的衬底、第二源漏金属层和第一源漏金属层。第一源漏金属层包括沿交替排列的第一数据线和第二数据线。第二源漏金属层包括第一连接部和第二连接部。每个第一连接部的第一端与相应的第一数据线电连接，第二端与相应的第一子像素电连接。每个第二连接部的第一端与相应的第二数据线电连接，第二端与相应的第二子像素电连接。同一列子像素中，第一连接部的第二端与第二连接部的第二端的第一连线大致平行于第二方向，第一连接部的第一端位于第一连线的第一侧，第二连接部的第一端位于第一连线的第二侧。

Description

显示基板及显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种显示基板及显示装置。
背景技术
显示装置的刷新频率(也可称为垂直刷新频率或垂直扫描频率)是指显示屏每秒可以显示的新的画面的次数，例如，显示屏在60Hz的刷新频率下，每秒可以显示60次新的画面。显示装置的刷新率较高时，例如75Hz、90Hz、120Hz或更高，其在显示高速移动的画面时可以避免画面出现模糊和拖尾等现象，提高画面质量和用户视觉体验。
发明内容
一方面，提供一种显示基板。显示基板具有阵列式布置的多个子像素，每列子像素包括多个第一子像素和第二子像素，第一子像素和第二子像素沿第二方向交替排列。所述显示基板包括：衬底、设置于所述衬底上的第一源漏金属层，以及设置于所述衬底和所述第一源漏金属层之间的第二源漏金属层。所述第一源漏金属层包括多条第一数据线和多条第二数据线，所述第一数据线和所述第二数据线沿第一方向交替排列，且每相邻两列子像素之间设置有一条第一数据线和一条第二数据线；沿第一方向，一列子像素与分别位于其两侧的一条第一数据线和一条第二数据线相对应，该列子像素的每个第一子像素与对应的第一数据线电连接，该列子像素的每个第二子像素与对应的第二数据线电连接。所述第二源漏金属层包括多个第一连接部和多个第二连接部。每个第一子像素通过一个第一连接部与对应的第一数据线电连接；每个第一连接部的第一端与相应的第一数据线电连接，第二端与相应的第一子像素的像素驱动电路电连接。每个第二子像素通过一个第二连接部与对应的第二数据线电连接；每个第二连接部的第一端与相应的第二数据线电连接，第二端与相应的第二子像素的像素驱动电路电连接。同一列子像素中，第一连接部的第二端与第二连接部的第二端的第一连线大致平行于所述第二方向，所述第一连接部的第一端位于所述第一连线的第一侧，所述第二连接部的第一端位于所述第一连线的第二侧。
在一些实施例中，所述显示基板还包括设置于所述衬底和所述第二源漏金属层之间的有源层。每个子像素还包括写入晶体管，所述写入晶体管包括设置于所述有源层中的第四有源图案；沿上述第一方向，每相邻两个子像素中写入晶体管的第四有源图案之间的间距大致相等，且沿所述第二方向，每相邻两 个子像素中写入晶体管的第四有源图案之间的间距大致相等。在每个第一子像素中，第一连接部的第二端与相应的写入晶体管的第四有源图案电连接；在每个第二子像素中，第二连接部的第二端与相应的写入晶体管的第四有源图案电连接。
在一些实施例中，每行子像素包括多个第一子像素和多个第二子像素，沿所述第一方向，第一子像素和第二子像素交替排列。同一行子像素中，第一连接部的第二端和第二连接部的第二端之间的第二连线大致平行于所述第一方向；所述第一连接部的第一端位于所述第二连线的远离相应第四有源图案的一侧，所述第二连接部的第一端位于所述第二连线的靠近相应第四有源图案的一侧。
在一些实施例中，所述显示基板还包括设置于所述第二源漏金属层和所述有源层之间的第一绝缘层，所述第一绝缘层中设置有多个第一过孔和多个第二过孔。在每个第一子像素中，所述第一连接部的第二端通过相应的一个第一过孔与相应的写入晶体管的第四有源图案电连接；在每个第二子像素中，所述第二连接部的第二端通过相应的一个第二过孔与相应的写入晶体管的第四有源图案电连接。
在一些实施例中，所述第一绝缘层包括第一子绝缘层和第二子绝缘层，所述第二子绝缘层设置于所述第一子绝缘层和所述衬底之间，所述显示基板还包括设置于所述第一子绝缘层和所述第二子绝缘层之间的第二栅金属层；所述第二栅金属层包括多个第一遮挡部和多个第二遮挡部，每个子像素设置有一个第一遮挡部和一个第二遮挡部。在每个第一子像素中，第一连接部和第二遮挡部在所述衬底上的正投影具有重叠区域，所述第一连接部和第一遮挡部在所述衬底上的正投影部分不具有重叠区域，所述第一连接部的第二端与所述第二遮挡部在所述衬底上的正投影不具有重叠区域；在每个第二子像素中，第二连接部和第一遮挡部在所述衬底上的正投影具有重叠区域，所述第二连接部和第二遮挡部在所述衬底上的正投影部分不具有重叠区域，所述第二连接部的第二端和所述第一遮挡部不具有重叠区域。
在一些实施例中，沿所述第一方向，在同一行子像素中，第一遮挡部和第二遮挡部交替排列，相邻的、且分别位于不同子像素中的第一遮挡部和第二遮挡部为一体成型。
在一些实施例中，每个第一连接部在其延伸方向上的最大尺寸，大于每个第二连接部在其延伸方向上的最大尺寸。
在一些实施例中，每个第一连接部的第一端的面积大于其第二端的面积， 和/或，每个第二连接部的第一端的面积大于其第二端的面积。
在一些实施例中，每条第一数据线包括第一本体和多个第五连接部；所述多个第五连接部设置于所述第一本体的靠近相应第一子像素的一侧，并沿所述第二方向排列；每个第五连接部电连接于所述第一本体与相应的第一连接部的第一端之间。每条第二数据线包括第二本体和多个第六连接部；所述多个第六连接部设置于所述第二本体的靠近相应第二子像素的一侧，并沿所述第二方向排列；每个第六连接部电连接于所述第二本体与相应的第二连接部的第一端之间。
在一些实施例中，所述显示基板还包括设置于所述第一源漏金属层和所述第二源漏金属层之间的第二绝缘层，所述第二绝缘层中设置有多个第三过孔和多个第四过孔。每个第五连接部通过相应的一个第三过孔与相应的第一连接部的第一端电连接，每个第六连接部通过相应的一个第四过孔与相应的第二连接部的第一端电连接。
在一些实施例中，所述显示基板还包括多条第一电压信号线，每条第一电压信号线在所述衬底上的正投影位于每相邻两列子像素之间的第一数据线和第二数据线在所述衬底上的正投影之间，所述第一电压信号线与至少一列子像素电连接。所述第一电压信号线包括：设置于所述第一源漏金属层中的第一子电压信号线，和设置于所述第二源漏金属层中的第二子电压信号线，所述第一子电压信号线与所述第二子电压信号线电连接。
在一些实施例中，所述显示基板包括第二绝缘层的情况下，所述第二绝缘层中设置有多个第五过孔；所述第一子电压信号线和所述第二子电压信号线通过所述多个第五过孔中的至少一个第五过孔电连接；其中，位于相邻两列子像素之间的第一数据线、第二数据线和第一子电压信号线中，所述第一数据线中与所述第五过孔相邻的部分向远离所述第五过孔的方向弯曲，形成第一弯曲部，所述第二数据线中与所述第五过孔相邻的部分向远离所述第五过孔的方向弯曲，形成第二弯曲部。所述第一弯曲部和所述第二弯曲部相对，形成容纳区域，所述第一子电压信号线包括经过所述第五过孔的导电部，所述导电部位于所述容纳区域内；沿所述第一方向，所述导电部的尺寸大于所述第一子电压信号线的宽度。
在一些实施例中，与一列子像素相邻，且位于该列子像素沿所述第一方向的两侧的第一数据线和第二数据线中，所述第一弯曲部与所述第二弯曲部之间设置有第七连接部，所述第七连接部与所述第一子电压信号线同层设置。
在一些实施例中，所述显示基板还包括设置于所述第一源漏金属层远离 所述衬底一侧的阳极层。每个子像素还包括第一发光控制晶体管，所述第一发光控制晶体管包括设置于有源层中的第六有源图案，所述第六有源图案包括第一导体部分；所述第七连接部与所述第一导体部分，以及所述阳极层电连接。
在一些实施例中，所述第一连线的第一侧为所述第一连线的靠近该列子像素对应的第一数据线的一侧，所述第一连线的第二侧为所述第一连线的靠近该列子像素对应的第二数据线的一侧。
另一方面，提供一种显示装置。所述显示装置包括如上述任一实施例所述的显示基板。
附图说明
为了更清楚地说明本公开中的技术方案，下面将对本公开一些实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例的附图，对于本领域普通技术人员来讲，还可以根据这些附图获得其他的附图。此外，以下描述中的附图可以视作示意图，并非对本公开实施例所涉及的产品的实际尺寸、方法的实际流程、信号的实际时序等的限制。
图1为根据一些实施例的一种7T1C像素驱动电路的等效电路图；
图2为图1所示的像素驱动电路的信号时序图；
图3为一些实施例的一种驱动架构的结构示意图；
图4为图3所示的驱动架构的信号时序图；
图5为一些实施例的另一种驱动系统的结构示意图；
图6为图5所示的驱动系统的信号时序图；
图7为根据一些实施例的一种显示基板的俯视示意图；
图8A至8H为图7所示的显示基板的各膜层的俯视示意图；
图9A为根据一些实施例的一种子像素的结构示意图；
图9B为图9A中的子像素沿虚线AA’的剖面示意图；
图10A为根据一些实施例的另一种子像素的结构示意图；
图10B为图10A中的子像素沿虚线BB’的剖面示意图；
图11为图7所示的显示基板的区域S内部分的等效电路图；
图12为图7所示的显示基板的区域S’内部分的局部放大图；
图13A至13F为根据一些实施例的一种显示基板的膜层间连接关系示意图。
具体实施方式
下面将结合附图，对本公开一些实施例中的技术方案进行清楚、完整地描 述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开所提供的实施例，本领域普通技术人员所获得的所有其他实施例，都属于本公开保护的范围。
除非上下文另有要求，否则，在整个说明书和权利要求书中，术语“包括(comprise)”及其其他形式例如第三人称单数形式“包括(comprises)”和现在分词形式“包括(comprising)”被解释为开放、包含的意思，即为“包含，但不限于”。在说明书的描述中，术语“一个实施例(one embodiment)”、“一些实施例(some embodiments)”、“示例性实施例(exemplary embodiments)”、“示例(example)”、“特定示例(specific example)”或“一些示例(some examples)”等旨在表明与该实施例或示例相关的特定特征、结构、材料或特性包括在本公开的至少一个实施例或示例中。上述术语的示意性表示不一定是指同一实施例或示例。此外，所述的特定特征、结构、材料或特点可以以任何适当方式包括在任何一个或多个实施例或示例中。
以下，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本公开实施例的描述中，除非另有说明，“多个”的含义是两个或两个以上。
在描述一些实施例时，可能使用了“连接”及其衍伸的表达。例如，描述一些实施例时可能使用了术语“连接”以表明两个或两个以上部件彼此间有直接物理接触或电接触，或者表明两个或两个以上部件彼此间有间接物理连接或电连接。这里所公开的实施例并不必然限制于本文内容。
需要理解的是，在本公开的描述中，术语“中心”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本发明和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本发明的限制。
“A和/或B”，包括以下三种组合：仅A，仅B，及A和B的组合。
如本文所使用的那样，“约”或“近似”包括所阐述的值以及处于特定值的可接受偏差范围内的平均值，其中所述可接受偏差范围如由本领域普通技术人员考虑到正在讨论的测量以及与特定量的测量相关的误差(即，测量系统的局限性)所确定。
显示装置在较高的刷新频率(例如75Hz、90Hz、120Hz或更高)下工作时，可以提高所显示的画面质量以及用户的视觉体验。但是较高的刷新频率会 带来显示装置中各子像素的数据写入和补偿时间变短的问题，这可能会导致各子像素充电率不足和阈值电压补偿效果下降，使显示装置的显示效果降低。
如图1所示，以包括7T1C结构的像素驱动电路的显示装置为例，显示装置包括多个子像素，每个子像素具有该7T1C结构的像素驱动电路，该像素驱动电路包括七个晶体管(第一晶体管T1至第七晶体管T7)和一个电容器Cst。该七个晶体管可以为P型晶体管，即在栅极接收到低电平信号时导通、接收到高电平信号是截止；该七个晶体管也可以为N型晶体管，即在栅极接收到高电平信号时导通、接收到低电平信号是截止。
为了方便介绍该7T1C的像素驱动电路，将第一晶体管T1的第二极、电容器Cst的第二极板B1和第三晶体管T3的栅极电连接点称为第一节点N1，第一节点N1、电容器Cst的第二极板B1和第三晶体管T3栅极的电压相等；将第五晶体管T5的第二极、第四晶体管T4的第二极和第三晶体管T3的第一极之间的电连接点称为第二节点N2；将第三晶体管T3的第二极、第二晶体管T2的第一极和第六晶体管T6的第一极的电连接节点称为第三节点N3。需要说明的是，这里第三晶体管T3用作该像素驱动电路中的驱动晶体管。
值得注意的是，驱动晶体管的沟道宽长比通常会大于其他作为开关晶体管的沟道宽长比，也即第三晶体管T3的沟道宽长比通常会大于第一晶体管T1、第二晶体管T2、第四晶体管T4、第五晶体管T5、第六晶体管T6和第七晶体管T7的沟道宽长比。此外，以电致发光器件为例，各子像素对应的发光器件E的发光亮度与流过其的驱动电流I的大小有关。根据公式I＝K(Vgs-Vth) 2，可知，驱动电流I与驱动晶体管的栅极和源极电压差Vgs以及驱动晶体管的阈值电压Vth有关，即在电压差Vgs一定的情况下，各发光器件E的发光亮度主要会受到相应的驱动晶体管的阈值电压Vth的影响，这样在显示装置的子像素中驱动晶体管的阈值电压Vth不相等时，例如随工作时间增加，驱动晶体管的阈值电压Vth发生漂移时，显示装置可能出现显示亮度不均匀的现象。
下面对上述7T1C的像素驱动电路的各元器件及元器件之间的连接关系进行介绍。这里以像素驱动电路所包括的晶体管为P型晶体管为例，即第一晶体管T1至第七晶体管T7在其栅极接收的信号为低电平时导通，在其栅极接收的信号为高电平时截止。
第一晶体管T1(也可以被称为第一复位晶体管)的栅极与复位信号端RESET电连接，第一极与初始化电压信号端INIT电连接，第二极与第一节点N1电连接。第二晶体管T2(也可以称为补偿晶体管)的栅极与扫描信号端 GATE电连接，第一极与第三节点N3电连接，第二极与第一节点N1电连接。第三晶体管T3(也可以称为驱动晶体管)的栅极与第一节点N1电连接，第一极与第二节点N2电连接，第二极与第三节点N3电连接，第四晶体管T4(也可以称为写入晶体管)的栅极与扫描信号端GATE电连接，第一极与数据信号端DATA电连接，第二极与第二节点N2电连接。第五晶体管T5(也可以称为第二发光控制晶体管)的栅极与发光信号端EM电连接，第一极与第一电压信号端VDD电连接，第二极与第二节点N2电连接。第六晶体管T6(也可以称为第一发光控制晶体管)的栅极与发光信号端EM电连接，第一极与第三节点N3电连接，第二极与子像素的发光器件E的阳极电连接。第七晶体管T7(也可以被称为第二复位晶体管)的栅极与复位信号端RESET电连接，第一极与初始化电压信号端INIT电连接，第二极与子像素的发光器件E的阳极电连接。电容器Cst的第一极板A1与第一电压信号端VDD电连接，第二极板B1与第一节点N1电连接。
此外，子像素的发光器件E的阳极与上述像素驱动电路电连接，阴极与第二电压信号端VSS电连接。
下面结合图2所示的信号时序图，对上述7T1C的像素驱动电路的工作过程介绍，在一帧时间里，像素驱动电路的工作过程包括复位阶段P1、写入和补偿阶段P2和发光阶段P3。
在复位阶段P1中，复位信号端RESET的传输至第一晶体管T1的栅极和第七晶体管T7的栅极的复位信号Vre为低电平，第一晶体管T1和第七晶体管T7导通。第一晶体管T1将来自初始化电压信号端INIT的初始化电压信号Vinit传输至第一节点N1，以对电容器Cst的第二极板B1和第三晶体管T3(也可以称为驱动晶体管T3)的栅极的电压进行复位，第二极板B1的电压等于初始化电压信号Vinit的电压Vi。第七晶体管T7将来自初始化电压信号端INIT的初始化电压信号Vinit传输至发光器件E的阳极，以对发光器件E的阳极电压进行复位。
这里，初始化电压信号Vinit在复位阶段P1中为低电平，第一节点N1的电压为低电压，因此栅极与第一节点N1电连接的第三晶体管T3导通。示例性的，初始化电压信号Vinit可以为恒定的低电压信号。
在写入和补偿阶段P2，复位信号Vre为高电平，第一晶体管T1和第七晶体管T7截止。第一节点N1的电压与电容器Cst的第二极板B1的电压相等，即第一节点N1的电压仍为低电压，第三晶体管T3维持导通状态。
扫描信号端GATE的传输至第四晶体管T4栅极和第二晶体管T2栅极的 扫描信号Vgate为低电平，第四晶体管T4和第二晶体管T2导通。第四晶体管T4将来自数据信号端DATA的数据信号Vdata传输至第三晶体管T3。数据信号Vdata通过导通的第三晶体管T3传输至第二晶体管T2，继而通过导通的第二晶体管T2传输至第一节点N1，从而被写入至电容器Cst。该数据信号Vdata通被写入至电容器Cst的过程实际为电容器Cst的第二极板B1的充电过程(即第二极板B1的电压逐渐升高的过程)，第一节点N1的电压由上一阶段(即复位阶段P1)中的Vi逐渐升高，直至第一节点N1的电压上升至Vdata+Vth，第三晶体管T3截止，这里Vth为第三晶体管T3的阈值电压值。此时，电容器Cst的第二极板B1的电压等于Vdata+Vth，这样，第三晶体管T3的阈值电压值Vth被补偿至电容器Cst所写入的数据信号中。
需要说明的是，这里扫描信号Vgate的有效电平(即，使相应晶体管导通的电平)的持续时间1H为一行子像素完成数据信号Vdata写入所需要的时间。
在发光阶段P3，发光信号端EM的传输至第五晶体管T5栅极和第六晶体管T6栅极发光信号Vem为低电平，第五晶体管T5和第六晶体管T6导通。第三晶体管T3的源极电压Vs等于第一电压信号端VDD的第一电压Vdd，第三晶体管T3的栅极电压Vg等于Vdata+Vth，这里第一电压Vdd大于Vdata+Vth，因此第三晶体管T3被导通。这样，第一电压信号端VDD和第二电压信号端VSS之间形成了电流通路，从而发光器件E可以发光。
需要说明的是，发光阶段P3中流过发光器件E的驱动电流I为I＝K(Vgs-Vth) 2＝K(Vdata+Vth-Vdd-Vth) 2＝K(Vdata-Vdd) 2。这样，驱动电流I的大小与第三晶体管T3的阈值电压值Vth无关，从而可以避免第三晶体管T3的阈值电压漂移对驱动电流I的影响，使显示装置的发光亮度更加均匀。
在显示装置需要以较快的频率进行刷新的情况下，由于每秒内显示的新画面次数较多，每帧画面的时间缩短，导致一帧内的写入和补偿阶段P2相应缩短，也即导致扫描信号的有效电平的持续时间缩短。这可能引起显示装置的子像素的数据写入时间(即子像素的充电时间)和阈值电压补偿时间较短，从而使子像素的充电率不足，以及阈值电压补偿效果不良，影响显示装置的画面质量和用户的视觉体验效果。
针对上述问题，可以采用设置两根数据线DL共同向一列子像素提供数据信号Vdata的驱动方式解决。下面将参照图3至6，对上述具有7T1C像素驱动电路的显示装置，采用该驱动方式的方案进行示例性介绍。
如图3和5所示，显示装置包括多个子像素PX、多条数据线DL(例如 DL1至DL8)和多条栅线GL(例如GL1至GL4)，这些子像素PX可以以阵列的方式设置。每列子像素与两条数据线DL对应，该两条数据线DL分别设置于该列子像素的左、右两侧。位于同一列的子像素中，每相邻的两个子像素PX分别与上述左、右两侧数据线DL中不同的数据线DL电连接，即沿该列子像素的延伸方向，位于同一列的子像素PX交替地与左、右两侧的数据线DL电连接。位于同一行的子像素可以与同一条栅线GL电连接，这里，栅线GL可以向与其电连接的一行子像素提供扫描信号Vgate，使来自数据线DL的数据信号Vdata被传输进相应的子像素PX中，实现数据信号Vdata的写入。各子像素PX的数据写入过程可参考上文中对于写入和补偿阶段P2的描述，此处不再赘述。
需要说明的是，沿每行子像素的延伸方向，位于同一行的子像素PX可以交替地与其左、右两侧的数据线DL电连接(如图3和图5所示)，也可以均与位于其左侧或位于其右侧的数据线DL电连接。
显示装置还可以包括多条源极驱动信号线S(例如S1至S4)和源极驱动器100，多条源极驱动信号线S与源极驱动器100电连接。源极驱动器100用于提供显示装置所要显示图像的数据信号Vdata，通过源极驱动信号线S和数据线DL可以将这些数据信号Vdata提供给各子像素PX。
每相邻的多条数据线DL电连接至同一源极驱动信号线S上，这样，源极驱动器100可以通过源极驱动信号线S向与该源极驱动信号线S电连接的多条数据线DL传输数据信号Vdata，从而可以减少源极驱动器100上设置的用于输出数据信号Vdata的接口数量。每条数据线DL和其对应的源极驱动信号线S之间设置有开关SW，这样通过控制相应的开关SW的开启和关闭，可以使源极驱动信号线S被分时复用。这里，与同一源极驱动信号线S对应，且位于一列子像素左侧的数据线DL对应的开关SW的控制极均与同一控制信号线MUX(例如图3中的MUX1或MUX2)电连接，通过该控制信号线MUX可以控制上述数据线DL对应的开关SW的开启和关闭，从而控制某一帧内来自该源极驱动信号线S的数据信号Vdata向特定的数据线DL传输，这样可以控制该数据信号Vdata被写入进相应的子像素PX中。
这里开关SW可以包括N型或P型晶体管。在开关SW包括N型晶体管的情况下，开关SW在来自控制信号线MUX的信号为高电平时开启，在该信号为低电平时关闭。在开关SW包括P型晶体管的情况下，开关SW在来自控制信号线MUX的信号为低电平时开启，在该信号为高电平时关闭。
下面将分别以图2和图4所示的显示装置的结构为例，对该显示装置的 驱动过程进行介绍，显示装置中的子像素内的像素驱动电路可以参考图1。这里以像素驱动电路中第二晶体管T2和第四晶体管T4，以及开关SW为P型晶体管为例，且沿一行子像素的延伸方向，位于同一行的子像素PX交替地与其左、右两侧的数据线DL电连接。
在一些示例中，参见图3，每两条相邻的数据线DL与同一源极驱动信号线S电连接。例如，源极驱动信号线S1与数据线DL1和数据线DL2电连接，也就是说，源极驱动器100可以通过源极驱动信号线S1、数据线DL1和数据线DL2，向第一列子像素PC1提供数据信号Vdata。类似地，源极驱动信号线S2与数据线DL3和数据线DL4电连接，源极驱动器100可以通过源极驱动信号线S2、数据线DL3和数据线DL4，向第二列子像素PC2提供数据信号Vdata；源极驱动信号线S3与数据线DL5和数据线DL6电连接，源极驱动器100可以通过源极驱动信号线S3、数据线DL5和数据线DL6，向第三列子像素PC3提供数据信号Vdata；源极驱动信号线S4与数据线DL7和数据线DL8电连接，源极驱动器100可以通过源极驱动信号线S4、数据线DL7和数据线DL8，向第四列子像素PC4提供数据信号Vdata。
与同一源极驱动信号线S对应的两条数据线DL中，每条位于相应列子像素左侧的数据线DL所电连接的各开关SW中，薄膜晶体管的栅极均与控制信号线MUX1电连接；每条位于相应列子像素右侧的数据线DL所对应的开关SW中，薄膜晶体管的栅极均与控制信号线MUX2电连接。例如数据线DL1、DL3、DL5和DL7所电连接的各开关SW中薄膜晶体管的栅极均与控制信号线MUX1电连接，数据线DL2、DL4、DL6和DL8所对应的开关SW中的薄膜晶体管的栅极均与控制信号线MUX2电连接。
由此，通过向不同的开关SW中的薄膜晶体管传输不同电平的信号，可以选通不同的数据线DL来传输数据信号Vdata至相应的子像素PX中。这样，源极驱动器100可以通过一条源极驱动信号线S向与该源极驱动信号线S电连接的两条数据线DL传输数据信号Vdata。
在这种情况下，参见图4，第一阶段T11中，经由控制信号线MUX1传输的控制信号Vumx1为低电平，与控制信号线MUX1电连接的开关SW中的薄膜晶体管导通；经由控制信号线MUX2传输的控制信号Vumx2为高电平，与控制信号线MUX2电连接的开关SW中的薄膜晶体管截止。经由扫描信号线GL1传输的扫描信号Vgate1为低电平，位于第一子像素行PR1的各子像素PX中的第二晶体管T2和第四晶体管T4导通；经由扫描信号线GL2传输的扫描信号Vgate2为高电平，位于第二子像素行PR2的各子像素PX中 的第二晶体管T2和第四晶体管T4截止。这样，经由源极驱动信号线S1传输的数据信号Vdata被写入位于第一行子像PR1、第一列子像素PC1的子像素中，经由源极驱动信号线S3传输的数据信号Vdata被写入位于第一行子像PR1、第三列子像素PC3的子像素中。
在第二阶段T12中，通过控制信号线MUX1传输的控制信号Vumx1为高电平，与控制信号线MUX1电连接的各开关SW被关闭；通过控制信号线MUX2传输的控制信号Vumx2为低电平，与控制信号线MUX2电连接的各开关SW被开启。通过扫描信号线GL1传输的扫描信号Vgate1和通过扫描信号线GL2传输的扫描信号Vgate2均为低电平，位于第一行子像素PR1和第二行子像素PR2的各子像素PX中的第二晶体管T2和第四晶体管T4均导通。这样，虽然第一行子像素PR1和第二行子像素PR2中的各子像素的第四晶体管T4均被导通，但是由于与数据线DL1、DL3、DL5和DL7对应的开关SW均为关闭的，经由源极驱动信号线S1传输的数据信号Vdata由数据线DL2写入位于第二行子像PR2、第一列子像PC1的子像素中，经由源极驱动信号线S2传输的数据信号Vdata由数据线DL4写入位于第一行子像PR1、第二列子像PC2的子像素中，经由源极驱动信号线S3传输的数据信号Vdata由数据线DL6写入位于第二行子像PR2、第三列子像PC3的子像素中，经由源极驱动信号线S4传输的数据信号Vdata由数据线DL8写入位于第一行子像PR1、第四列子像PC4的子像素中。
需要注意的是，在上述驱动方式中，每个子像素PX的扫描信号Vgate的有效电平的持续时间为2H，即每个子像素PX的扫描信号Vgate的有效电平的持续时间与两行子像素完成数据信号Vdata写入所需要的时间相等。这样可以增加写入和补偿阶段P2的时间，使子像素PX的充电时间充足、阈值电压补偿效果提高，从而可以提高显示装置在高刷新频率下的显示效果。
在一些实施例中，参见图5，每4条相邻的数据线DL与同一源极驱动信号线S电连接。例如，源极驱动信号线S1与数据线DL1至DL4电连接，源极数据线S2与数据线DL5至DL8电连接。
沿一行子像素的延伸方向从左向右，每4条与同一源极驱动信号线S对应的数据线DL中，每个序号为1的数据线DL所电连接的各开关SW中薄膜晶体管的栅极均与控制信号线MUX1电连接，每个序号为2的数据线DL所电连接的各开关SW中薄膜晶体管的栅极均与控制信号线MUX2电连接，每个序号为3的数据线DL所电连接的各开关SW中薄膜晶体管的栅极均与控制信号线MUX3电连接，每个序号为4的数据线DL所电连接的各开关SW 中薄膜晶体管的栅极均与控制信号线MUX4电连接。
同样地，通过向不同的开关SW中的薄膜晶体管传输不同电平的信号，可以选通不同的数据线DL来传输数据信号Vdata至相应的子像素PX中。这样，通过分时复用源极驱动信号线S的方式，源极驱动器100可以通过同一条源极驱动信号线S向与该源极驱动信号线S电连接的4条数据线DL传输数据信号Vdata，从而使对应的四列子像素实现数据信号Vdata的写入。
在这种情况下，参见图6，在第一阶段T21中，经由控制信号线MUX1传输的控制信号Vumx1为低电平，与控制信号线MUX1电连接的开关SW中的薄膜晶体管导通；经由控制信号线MUX2至MUX4传输的控制信号Vumx2至Vumx4均为高电平，与控制信号线MUX2至MUX4电连接的开关SW中的薄膜晶体管均截止。经由扫描信号线GL1传输的扫描信号Vgate1为低电平，位于第一子像素行PR1的各子像素PX中的第二晶体管T2和第四晶体管T4导通；经由扫描信号线GL2至GL4传输的扫描信号Vgate2至Vgate4均为高电平，位于第二像素行PR2至第四像素行PR4的各子像素PX中的第二晶体管T2和第四晶体管T4均截止。这样，经由源极驱动信号线S1传输的数据信号Vdata被写入位于第一行子像PR1、第一列子像素PC1的子像素中，经由源极驱动信号线S2传输的数据信号Vdata被写入位于第一行子像PR1、第三列子像素PC3的子像素中。
在第二阶段T22中，经由控制信号线MUX2传输的控制信号Vumx2为低电平，与控制信号线MUX2电连接的开关SW中的薄膜晶体管导通；经由控制信号线MUX1、MUX3和MUX4传输的控制信号Vumx1、Vumx3和Vumx4均为高电平，与控制信号线MUX1、MUX3和MUX4电连接的开关SW中的薄膜晶体管均截止。经由扫描信号线GL1和GL2传输的扫描信号Vgate1和Vgate2为低电平，位于第一子像素行PR1和第二子像素行PR2的各子像素PX中的第二晶体管T2和第四晶体管T4导通；经由扫描信号线GL3和GL4传输的扫描信号Vgate3和Vgate4均为高电平，位于第三像素行PR3和第四像素行PR4的各子像素PX中的第二晶体管T2和第四晶体管T4均截止。这样，经由源极驱动信号线S1传输的数据信号Vdata被写入位于第二行子像PR2、第一列子像素PC1的子像素中，经由源极驱动信号线S2传输的数据信号Vdata被写入位于第二行子像PR2、第三列子像素PC3的子像素中。
在第三阶段T3中，经由控制信号线MUX3传输的控制信号Vumx3为低电平，与控制信号线MUX3电连接的开关SW中的薄膜晶体管导通；经由控制信号线MUX1、MUX2和MUX4传输的控制信号Vumx1、Vumx2和Vumx4 均为高电平，与控制信号线MUX1、MUX2和MUX4电连接的开关SW中的薄膜晶体管均截止。经由扫描信号线GL1至GL3传输的扫描信号Vgate1至Vgate3为低电平，位于第一子像素行PR1至第三子像素行PR3的各子像素PX中的第二晶体管T2和第四晶体管T4导通；经由扫描信号线GL4传输的扫描信号Vgate4为高电平，位于第四像素行PR4的各子像素PX中的第二晶体管T2和第四晶体管T4均截止。这样，经由源极驱动信号线S1传输的数据信号Vdata被写入位于第二行子像PR2、第二列子像素PC2的子像素中，经由源极驱动信号线S2传输的数据信号Vdata被写入位于第二行子像PR2、第四列子像素PC4的子像素中。
在第四阶段T4中，经由控制信号线MUX4传输的控制信号Vumx4为低电平，与控制信号线MUX4电连接的开关SW中的薄膜晶体管导通；经由控制信号线MUX1至MUX3传输的控制信号Vumx1至Vumx3均为高电平，与控制信号线MUX1至MUX3电连接的开关SW中的薄膜晶体管均截止。经由扫描信号线GL1至GL4传输的扫描信号Vgate1至Vgate4均为低电平，位于第一子像素行PR1至第四子像素行PR4的各子像素PX中的第二晶体管T2和第四晶体管T4均导通。这样，经由源极驱动信号线S1传输的数据信号Vdata被写入位于第一行子像PR2、第二列子像素PC2的子像素和位于第三行子像PR3、第二列子像素PC2的子像素中，经由源极驱动信号线S2传输的数据信号Vdata被写入位于第一行子像PR1、第四列子像素PC4的子像素和位于第三行子像PR3、第四列子像素PC4的子像素中。
这里，每个子像素PX的扫描信号Vgate的有效电平的持续时间为2H，同样可以增加写入和补偿阶段P2的时间，使子像素PX的充电时间充足、阈值电压补偿效果提高，从而可以提高显示装置在高刷新频率下的显示效果。
需要注意的是，在该第四阶段T4中，位于第三行子像PR3、第二列子像素PC2的子像素，以及位于第三行子像PR3、第四列子像素PC4的子像素所写入的数据信号Vdata并不是其发光阶段中实际所需要的数据信号。在扫描信号的有效电平的持续时间为2H，在与上述两个子像素对应的扫描信号Vgate3的有效电平结束之前，该两个子像素还会被再次写入新的数据信号Vdata，该新写入的数据信号Vdata为其发光阶段所需要的数据信号。
然而，在显示装置采用上述通过两根数据线DL共同向一列子像素提供数据信号Vdata的驱动方式时，显示装置中设置的数据线DL的数量会增加一倍，数据线DL的分布密度增大，使得子像素同与其对应的两条数据线(即与该像素相邻、分别位于其两侧的两条数据线)之间的间距均变小，从而可能导 致对应的两条数据中，未与该子像素电连接的数据线会与该子像素中的像素驱动电路产生较大的寄生电容。这可能影响该子像素的发光，从而可能降低显示装置的显示效果。
本公开的一些实施例提供了一种显示基板，参见图7和9A至10B，该显示基板1000包括衬底10和设置在衬底10上的阵列式布置的多个子像素。这里，为便于描述，定义与一列子像素的延伸方向垂直或大致垂直的方向为第一方向OU，也即第一方向OU为多个子像素阵列式布置的行方向，定义与一列子像素的延伸方向平行或大致平行的方向为第二方向OV，也即第二方向OV为多个子像素阵列式布置的列方向。每列子像素包括多个第一子像素31和第二子像素32，第一子像素31和第二子像素32沿第二方向OV交替排列。
图11为图7所示显示基板1000的位于区域S内部分的等效电路图，这里以显示基板1000在区域S内包括矩阵排布的两个第一子像素31和两个第二子像素32为例进行说明。每个第一子像素31和每个第二子像素32具有7T1C结构的像素驱动电路，像素驱动电路包括第一晶体管T1至第七晶体管T7和电容器Cst。该像素驱动电路内部的元器件之间的电连接关系，以及该驱动电路的工作过程可以参照上文的描述，此处不再赘述。
下面将对图7所示的显示面板1000中子像素的像素驱动电路中的各元器件的结构进行示例性的介绍。沿衬底10的厚度方向，显示面板1000包括依次设置于衬底10上的有源层L A、第一栅金属层L G1、第二栅金属层L G2和第一源漏金属层L SD1。需要说明的是，图8A至8F中区域S P1为一个第一子像素31所在的区域，区域S P2为一个第二子像素32所在的区域。
如图8A、9B、10B和13A所示，有源层L A包括第一晶体管T1的有源图案71、第二晶体管T2的有源图案72、第三晶体管T3的有源图案73、第四晶体管T4的有源图案74、第五晶体管T5的有源图案75、第六晶体管T6的有源图案76和第七晶体管T7的有源图案77。
如图8B、9B、10B和13B所示，第一栅金属层L G1包括第一晶体管T1的栅极G1、第二晶体管T2的栅极G2、第三晶体管T3的栅极G3、第四晶体管T4的栅极G4、第五晶体管T5的栅极G5、第六晶体管T6的栅极G6和第七晶体管T7的栅极G7。第一栅金属层L G1还包括电容器Cst的第二极板B1、复位信号线RL、栅线GL和发光信号线EML。这里，复位信号线RL被配置为将来自复位信号端RESET的复位信号Vre传输至相应的子像素，栅线GL被配置为将来自扫描信号端GATE的扫描信号Vgate传输至相应的子像素，发光信号线EML被配置为将来自发光信号端EM的发光信号Vem传输至相 应的子像素。
需要说明的是，参见图13B，第一栅金属层L G1与第一晶体管T1的有源图案71在衬底10上的正投影的重叠部分可以作为第一晶体管T1的栅极G1，第一栅金属层L G1与第二晶体管T2的有源图案72在衬底10上的正投影的重叠部分可以作为第二晶体管T2的栅极G2，第一栅金属层L G1与第三晶体管T3的有源图案73在衬底10上的正投影的重叠部分可以作为第三晶体管T3的栅极G3，第一栅金属层L G1与第四晶体管T4的有源图案74在衬底10上的正投影的重叠部分可以作为第四晶体管T4的栅极G4，第一栅金属层L G1与第五晶体管T5的有源图案75在衬底10上的正投影的重叠部分可以作为第五晶体管T5的栅极G5，第一栅金属层L G1与第六晶体管T6的有源图案76在衬底10上的正投影的重叠部分可以作为第六晶体管T6的栅极G6，第一栅金属层L G1与第七晶体管T7的有源图案77在衬底10上的正投影的重叠部分可以作为第七晶体管T7的栅极G7。
如图8C、9B、10B和13C所示，第二栅金属层L G2包括电容器Cst的第一极板A1和初始化电压信号线IL。初始化电压信号线被配置为将来自初始化电压信号端INIT的初始化电压信号Vin传输至相应的子像素。
如图8G、9B、10B和13F所示，第一源漏金属层L SD1包括多条第一数据线21和多条第二数据线22，第一数据线21和第二数据线22沿第一方向OU交替排列，每相邻两列子像素之间设置有一条第一数据线21和一条第二数据线22。沿第一方向OU，一列子像素与分别位于其两侧的一条第一数据线21和一条第二数据线22相对应，该列子像素的每个第一子像素31与对应的第一数据线21电连接，该列子像素的每个第二子像素32与对应的第二数据线22电连接。
下面参照图11，对各子像素的像素驱动电路与显示基板1000中的信号线的连接关系进行示例性说明。
同一列子像素中，第一子像素31的第四晶体管T4与同一第一数据线21电连接，第二子像素32的第四晶体管T4与同一第二数据线22电连接。也就是说，第一子像素31通过第一数据线21接收数据信号Vdata，第二子像素32通过第二数据线22接收数据信号Vdata。
位于同一行的子像素的第二晶体管T2和第四晶体管T4的栅极通过同一栅线GL电连接至同一级扫描信号端GATE(例如第N级扫描信号端GATE N或第(N+1)级扫描信号端GATA N+1)。
位于同一行的子像素的第五晶体管T5和第六晶体管T6的栅极通过同一 发光信号线EML电连接至同一级发光信号端EM(例如第N级发光信号端EM N或第(N+1)发光信号端EM N+1)。
位于同一行的子像素的第一晶体管T1和第七晶体管T7的栅极，通过同一复位信号线RL电连接至上一级扫描信号端GATE。需要说明的是，这里以上一级扫描信号端GATE输出的扫描信号Vgate作为复位信号Vre，也就是说，上一级扫描信号端GATE用作当前子像素的复位信号端RESET。例如，图11中，第N级扫描信号端GATE N输出的扫描信号Vgate，作为第二晶体管T2和第四晶体管T4与第(N+1)级扫描信号端GATA N+1电连接的子像素的复位信号Vre。
位于同一行的子像素的第一晶体管T1和第七晶体管T7的第一极通过同一初始化电压信号线IL电连接至初始化电压信号端INIT。这里初始化电压信号端INIT输出的初始化电压信号Vin可以为恒压信号，例如，图11中的初始化电压信号Vin可以为恒低压信号。
在一些实施例中，参见7、图8E、9A至10B和13E，显示基板1000还包括设置于衬底10和第一源漏金属层L SD1之间的第二源漏金属层L SD2，例如，在显示基板1000包括的第二栅金属层L G2情况下，第二源漏金属层L SD2设置于第二栅金属层L G2和第一源漏金属层L SD1之间。
第二源漏金属层L SD2包括多个第一连接部131和多个第二连接部132。这里，第一连接部131设置于第一子像素31所在的第一区域S P1中，第二连接部132设置于第二子像素32所在的第一区域S P2中。参见图9A和9B，每个第一子像素31通过一个第一连接部131与对应的第一数据线21电连接，每个第一连接部131的第一端1311与相应的第一数据线21电连接，该第一连接部131的第二端1312与相应的第一子像素31的像素驱动电路电连接。每个第二子像素32通过一个第二连接部132与对应的第二数据线22电连接，每个第二连接部132的第一端1321与相应的第二数据线22电连接，该第二连接部132的第二端1322与相应的第二子像素32的像素驱动电路电连接。同一列子像素中，第一连接部131的第二端1312与第二连接部132的第二端1322的第一连线CD大致平行于第二方向OV，第一连接部131的第一端1311位于第一连线CD的第一侧，该第一侧例如可以为第一连线CD的靠近该列子像素对应的第一数据线21的一侧，第二连接部132的第一端1321位于第一连线CD的第二侧，该第二侧例如可以为第一连线CD的靠近该列子像素对应的第二数据线22的一侧。
对于第一子像素31而言，第一连接部131位于第二源漏金属层L SD2，邻 近该第一子像素31的第二数据线22位于第一源漏金属层L SD1，因此，第一连接部131与该第二数据线22位于不同的膜层。这样，即使第一连接部131的第二端1312与该第二数据线22在衬底10上的正投影距离较近，由于第一连接部131和该第二数据线22位于不同的膜层中，二者之间产生的寄生电容较小。第一连接部131的第一端1311距离该第二数据线22距离较远，因此第一连接部131的第一端1311与邻近该第一子像素31的第一数据线21的电连接处距离该第二数据线22较远，从而第一连接部131的第一端1311以及该电连接处与该第二数据线22之间不会产生较大的寄生电容。
类似地，对于第二子像素32而言，第二连接部32位于第二源漏金属层L SD2，邻近该第二子像素32的第一数据线21位于第一源漏金属层L SD，因此，第二连接部132与该第一数据线21位于不同的膜层。这样，即使第二连接部132的第二端1322与该第一数据线21在衬底10上的正投影距离较近，由于第二连接部132和该第一数据线21位于不同的膜层中，二者之间产生的寄生电容较小。第二连接部132的第一端1321距离该第二数据线22距离较远，因此第二连接部132的第一端1321与邻近该第二子像素32的第二数据线22的电连接处距离该第一数据线21较远，从而第二连接部132的第一端1321以及该电连接处与该第一数据线21之间不会产生较大的寄生电容。
这样，在上述显示基板1000中，对于某个子像素而言，未与该子像素电连接的数据线与该子像素中的像素驱动电路之间的寄生电容可以被降低，因此可以降低寄生电容对子像素的发光产生影响，从而可以提高显示装置的显示效果。
示例性的，参见图9B和10B，在显示基板1000包括设置于衬底10和第二源漏金属层L SD2之间的有源层L A的情况下，显示基板1000还包括设置于衬底10与有源层L A之间的有无机缓冲层11。无机缓冲层11可以为单层结构，也可以为多层的层叠结构，例如为无机膜层和有机膜层的交替设置的层叠结构。
在一些实施例中，参见图7、8A、9A至10B和11，在每个子像素包括第四晶体管T4(可以称为写入晶体管)的情况下，沿第一方向OU，每相邻两个子像素中第四晶体管T4的第四有源图案74之间的间距大致相等，且沿第二方向OV，每相邻两个子像素中第四晶体管T4的第四有源图案74之间的间距大致相等。也就是说，每个第四有源图案74在相应的子像素所在区域S P中所处的位置大致相同。在每个第一子像素31中，第一连接部131的第二端1312与相应的第四晶体管T4的第四有源图案74电连接；在每个第二子像素32中， 第二连接部132的第二端1322与相应的第四晶体管T4的第四有源图案74电连接。
示例性的，参见图9A至10B，沿第二方向OV，在每个第一子像素31中，相对于第一连接部131的第一端1311在有源层L A上的正投影，第一连接部131的第二端1312在有源层L A上的正投影更靠近相应的第四有源图案74；在每个第二子像素32中，相对于第二连接部132的第二端1322在有源层L A上的正投影，第二连接部132的第一端1321在有源层L A上的正投影更靠近相应的第四有源图案74。
在一些实施例中，参见图8A、8E、9A和10A，第二源漏金属层L SD2还包括多个第三连接部110和多个第四连接部120。每个子像素中，第一晶体管T1的有源图案71，以及第七晶体管T7的有源图案77通过相应的一个第三连接部110与始化电压信号线IL电连接，从而实现第一晶体管T1，以及第七晶体管T7与始化电压信号线IL的电连接。
在一些实施例中，参见图7，每行子像素包括多个第一子像素31和多个第二子像素32，沿第一方向OU，第一子像素31和第二子像素32交替排列。
同一行子像素中，第一连接部131的第二端1312和第二连接部132的第二端1322之间的第二连线EF大致平行于第一方向OU。第一连接部131的第一端1311位于第二连线EF的远离相应第四有源图案74的一侧，第二连接部132的第一端1321位于第二连线EF的靠近相应第四有源图案74的一侧。
这样，在第一子像素31中，可以增大第一连接部131与第四连接部120之间的距离在第二子像素32中，从而可以减少第一子像素31中的像素驱动电路短路的风险。在第二子像素32中，可以增大第二连接部132与第三连接部110之间的距离，从而可以减少第二子像素32中的像素驱动电路短路的风险。
在一些实施例中，参见图8D和9A至10B，显示基板1000还包括设置于第二源漏金属层L SD2和有源层L A之间的第一绝缘层IS1，第一绝缘层IS1中设置有多个第一过孔701和多个第二过孔702。在每个第一子像素31中，第一连接部131的第二端1312通过相应的一个第一过孔701与相应的第四晶体管T4的第四有源图案74电连接。在每个第二子像素32中，第二连接部132的第二端1322通过相应的一个第二过孔702与相应的第四晶体管T4的第四有源图案74电连接。
示例性的，参见图8A、9A至10B，第一绝缘层IS1包括第一子绝缘层IS11和第二子绝缘层IS12，第二子绝缘层IS12设置于第一子绝缘层IS11的 靠近衬底10的一侧。
有源层L A还包括多个第一有源连接部711、多个第二有源连接部712和多个第三有源连接部。在每个第一子像素31中，第四晶体管T4的第四有源图案74通过相应的一个第一有源连接部711与第一连接部131的第二端1312电连接；在每个第二子像素32中，第四晶体管T4的第四有源图案74通过相应的一个第一有源连接部711与第二连接部132的第二端1322电连接。在每个子像素中，第一晶体管T1(可以称为第一复位晶体管)的第一有源图案71和第二晶体管T2(可以称为补偿晶体管)的第二有源图案72通过相应的一个第二有源连接部712电连接，第一晶体管T1的第一有源图案71和第七晶体管T7的第七有源图案77之间连接有相应的一个第三有源连接部713。
在显示基板1000包括第二栅金属层L G2的情况下，第二栅金属层L G2设置于第一子绝缘层IS11和第二子绝缘层IS12之间。参见图8A、8C和13C，第二栅金属层L G2还包括多个第一遮挡部1021和多个第二遮挡部1022，每个子像素设置有一个第一遮挡部1021和一个第二遮挡部1022。每个子像素中，第一遮挡部1021和相应的第一有源连接部711在衬底10上的正投影具有重叠区域，第二遮挡部1022还和相应的第三有源连接部713在衬底10上的正投影具有重叠区域，第二遮挡部1022和相应的第二有源连接部712在衬底10上的正投影具有重叠区域。
这里，在包括有显示基板1000的显示装置显示图像时，第一连接部131可以为相应的第一有源连接部711和第三有源连接部713遮光，从而降低第一晶体管T1、第二晶体管T2和第七晶体管T7的漏电流；第二遮挡部1022可以为相应的第二有源连接部712遮光，从而降低第四晶体管T4的漏电流。
基于此，在每个第一子像素31中，第一连接部131和第二遮挡部1022在衬底10上的正投影具有重叠区域，第一连接部131和第一遮挡部1021在衬底10上的正投影部分不具有重叠区域，第一连接部131的第二端1312与第二遮挡部1022在衬底10上的正投影不具有重叠区域。在每个第二子像素32中，第二连接部132和第一遮挡部1021在衬底10上的正投影具有重叠区域，第二连接部132和第二遮挡部1022在衬底10上的正投影部分不具有重叠区域，第二连接部132的第二端1322和第一遮挡部1021不具有重叠区域。
这样，在第一子像素31中，第一遮挡部1021和第二遮挡部1022可以避让设置于第一绝缘层IS1中的第一过孔701，从而可以避免第一遮挡部1021和第二遮挡部1022对第一连接部131与相应的第四有源图案74的电连接造成影响；在第二子像素32中，第二遮挡部1022可以避让设置于第一绝缘层 IS1中的第二过孔702，从而可以避免第一遮挡部1021和第二遮挡部1022对第二连接部132与相应的第四有源图案74的电连接造成影响。
这里，第一遮挡部1021和第二遮挡部1022可以通过同种材料，通过同一次构图工艺形成，从而可以简化制备工艺。
示例性的，沿第一方向OU，在同一行子像素中，第一遮挡部1021和第二遮挡部1022交替排列，相邻的、且分别位于不同子像素中的第一遮挡部1021和第二遮挡部1022为一体成型的。
在一些实施例中，参见图9B和10B，第一绝缘层IS1还包括设置于第二子绝缘层IS12的靠近衬底10一侧的第三子绝缘层IS13。在这种情况下，上述第一栅金属层L G1设置于第二子绝缘层IS12和第三子绝缘层IS13之间。
示例性的，参见图8D、13D和13E，第一绝缘层IS1中还设置有第七过孔510(例如包括510A和510B)，第一子绝缘层IS11中设置有第八过孔513，第一子绝缘层IS11和第二子绝缘层IS12设置有贯穿的第九过孔514(即第九过孔514贯穿第一子绝缘层IS11和第二子绝缘层IS12)。上述第三连接部110的一端通过第七过孔510A与第七晶体管T7的有源图案77电连接，第三连接部110的另一端通过第八过孔513与始化电压信号线IL电连接。上述第四连接部120的一端通过第七过孔510B与第一晶体管T1的有源图案71，以及第二晶体管T2的第二有源图案72电连接，第四连接部120的另一端通过第九过孔514与第三晶体管T3(可以称为驱动晶体管)的第三有源图案73电连接。
在一些实施例中，参见图7和8E，每个第一连接部131在其延伸方向上的最大尺寸，大于每个第二连接部132在其延伸方向上的最大尺寸。
在一些实施例中，参见图7、8E、9A和10A，每个第一连接部131的第一端1311的面积大于其第二端1312的面积，和/或，每个第二连接部132的第一端1321的面积大于其第二端1322的面积。从而有利于第一连接部131与相应的第一数据线21电连接，以及有利于第二连接部132与相应的第二数据线22电连接。
在一些实施例中，每个第一连接部131还包括第一过渡子部1313，第一过渡子部1313连接于第一连接部131的第一端1311和第二端1312之间，第一过渡子部1313沿与第一连接部131的延伸方向垂直的方向的尺寸小于第一连接部131的第一端1311和第二端1312的沿与第一连接部131的延伸方向垂直的方向的尺寸。
示例性的，每个第二连接部132还包括第二过渡子部1323，第二过渡子 部1323连接于第二连接部132的第一端1321和第二端1322之间，第二过渡子部1323沿与第二连接部132的延伸方向垂直的方向的尺寸小于第二连接部132的第一端1321和第二端1322的沿与第一连接部132的延伸方向垂直的方向的尺寸。
在一些实施例中，参见图7、8G和9A至10B，每条第一数据线21包括第一本体211和多个第五连接部212。多个第五连接部212设置于第一本体211的靠近相应第一子像素31的一侧，并沿第二方向OV排列，每个第五连接部212电连接于第一本体通211与相应的第一连接部131的第一端1311之间。
每条第二数据线22包括第二本体221和多个第六连接部222。多个第六连接部222设置于第二本体221的靠近相应第二子像素32的一侧，并沿第二方向OV排列，每个第六连接部222电连接于第二本体221与相应的第二连接部132的第一端1321之间。
这里，第一数据线21通过多个第五连接部212与相应的第一连接部131电连接，可以增加第一数据线21与第一连接部131的电接触面积，有利于二者的电连接。同样地，第二数据线22通过多个第六连接部222与相应的第二连接部132电连接，可以增加第二数据线22与第二连接部132的电接触面积，有利于二者的电连接。
示例性的，参见图9A至10B，显示基板1000还包括设置于第一源漏金属层L SD1和第二源漏金属层L SD2之间的第二绝缘层IS2，第二绝缘层IS2中设置有多个第三过孔801和多个第四过孔802。每个第五连接部212通过相应的一个第三过孔801与相应的第一连接部131的第一端1311电连接，每个第六连接部222通过相应的一个第四过孔802与相应的第二连接部132的第一端1321电连接。
在一些实施例中，参见图7和11，显示基板1000还包括设置于衬底10上的多条第一电压信号线40，每条第一电压信号线40在衬底10上的正投影，位于每相邻的两列子像素之间的第一数据线21和第二数据线22在衬底10上的正投影之间，每条第一电压信号线40与至少一列子像素电连接。
位于同一列的子像素的第五晶体管T5的第一极通过同一第一电压信号线40可以电连接至第一电压信号端VDD。这里，第一电压信号线40可以用于传输来自第一电压信号端VDD的第一电压信号Vdd至与其电连接的子像素中。
示例性的，参见图7、8E至8F和12，每个第一电压信号线40包括设置 于第一源漏金属层L SD1中的第一子电压信号线41，以及设置于所述第二源漏金属层L SD2中的第二子电压信号线42，第一子电压信号线41与第二子电压信号线42电连接。例如，第二绝缘层IS2中设置有多个第五过孔501，第一子电压信号线41和第二子电压信号线42通过多个第五过孔501中的至少一个第五过孔501电连接。
需要说明的是，第一电压信号线40可以向与其电连接的子像素传输为恒定电压信号的第一电压信号Vdd，也就是说，第一子电压信号线41和第二子电压信号线42上的电压可以均为稳定的电压。在包括有上述显示基板1000的显示装置显示画面时，与第一数据线21和第二数据线22同层设置的，且位于二者之间的第一子电压信号线41因具有稳定的电压，可以对第一数据线21和第二数据线22上传输的数据信号Vdata起到屏蔽作用。这样，该显示装置在显示过程中，相邻的第一数据线21和第二数据线22之间的寄生电容可以被设置与二者之间的第一自电压信号线41降低，从而可以减小数据信号Vdata之间的串扰，提高显示装置的显示效果。
示例性的，可以通过同一次构图工艺形成第一子电压信号线41、第一数据线21和第二数据线22，以使他们同层设置。
示例性的，第一子电压信号线41和第二子电压信号线42在衬底10上的正投影重合或部分重叠。这样第一过孔501可以设置于二者正投影的重合或重叠区域内，便于二者通过第一过孔501连接。
基于此，在一些实施例中，参见图7、8G和12，位于相邻两列子像素之间的第一数据线21、第二数据线22和第一子电压信号线40中，第一数据线21中与第五过孔501相邻的部分向远离该第五过孔501的方向弯曲，形成第一弯曲部213；第二数据线22中与第五过孔501相邻的部分向远离该第五过孔501的方向弯曲，形成第二弯曲部223。第一弯曲部213和第二弯曲部223相对，形成容纳区域A。第一子电压信号线41包括经过第五过孔501的导电部411，导电部411位于容纳区域A内。
这里，沿第一方向OU，导电部411的尺寸D1可以大于第一子电压信号线41的宽度D0，这样可以使第一过孔501在沿第一方向OU上具有较大尺寸，从而保证第一子电压信号线41和第二子电压信号线41的电接触良好。
在一些实施例中，与一列子像素相邻，且位于该列子像素沿第一方向OU的两侧的第一数据线21和第二数据线22中，第一弯曲部213与第二弯曲部223相互背向设置。显示基板1000还包括设置于相互背向设置的第一弯曲部213和第二弯曲部223之间的第七连接部60，第七连接部60设置于第一源漏 金属层L SD1中。第七连接部60被配置为对与该列子像素相邻，且位于该列子像素沿第一方向OU的两侧的第一数据线21和第二数据线22的数据信号Vdata进行屏蔽。第七连接部60在衬底10上的正投影可以为规则的图形，也可以为不规则的图形。
示例性的，显示基板1000还包括设置于第一源漏金属层L SD1远离衬底10一侧的阳极层，各子像素的阳极图案可以设置于该阳极层中。参见图11和12，在每个子像素的像素驱动电路包括第六晶体管T6(可以称为第一发光晶体管)的情况下，该第六晶体管T6的第六有源图案76包括第一导体部分，上述第七连接部60与相应的有源图案76的第一导体部分，以及相应的阳极图案电连接。
示例性的，显示基板1000还包括设置于各子像素中的发光器件E，发光器件E还包括阴极图案，以及设置于阳极图案和阴极图案之间的发光功能层。
参见图11，发光器件E的阳极图案可以与第二电压信号端VSS电连接。例如，显示基板1000还包括第二电压信号线50的情况下，发光器件E的阳极图案可以通过第二电压信号线50电连接至第二电压信号端VSS，以接收来自第二电压信号端VSS的第二电压信号Vss。
发光功能层包括发光材料层，此外，还可以包括传输层(election transporting layer，简称ETL)、电子注入层(election injection layer，简称EIL)、空穴传输层(hole transporting layer，简称HTL)或空穴注入层(hole injection layer，简称HIL)中的至少一个。发光材料层可以为有机发光材料层，在这种情况下，包括显示基板200的显示装置为OLED(Organic Light-Emitting Diode，有机发光二极管)显示装置。发光材料层也可以是量子点发光材料层，在这种情况下，包括显示基板200的显示装置为QLED(Quantum Dot Light-Emitting Diode，量子点发光二极管)显示装置。
这里，第六晶体管T6的第六有源图案76可以包括第一导体部分、沟道部分和第二导体部分，第一导体部分和第二导体部分通过沟道部分连接。第一导体部分和可以作为第六晶体管T6的源极和漏极中的一者，第二导体部分可以作为源极和漏极中的另一者。例如，参见图11，在第六晶体管T6为P型晶体管的情况下，与阳极层90连接的第一导电部分作为第六晶体管T6的漏极，第二导电部分作为第六晶体管T6的源极。
在上述显示基板1000中，第七连接部60与发光器件E电连接，发光器件E与第二电压信号端VSS电连接，从而在包括显示基板200的显示装置显示图像的过程中，第七连接部60因具有稳定的电压而可以屏蔽位于两列像素 之间的第一信号线21和第二信号线22上的数据信号Vdata，降低数据信号Vdata之间的串扰，提高显示装置的显示效果。
还需要说明的是，由于上述显示基板200中第七连接部60与第一子电压信号线41、第一数据线21和第二数据线22同层设置，因此可以在无需增加额外的构图工艺的情况下，形成可用于降低第一数据线21和第二数据线22的数据信号Vdata之间串扰的第七连接部60。
示例性的，参见图8H、9A和10A，显示基板1000还包括设置于第一源漏金属层L SD1的远离衬底10一侧的第三绝缘层IS3，第三绝缘层IS3中设置有第十过孔504，第七连接部60通过第十过孔504与发光器件E的阳极图案电连接。
在一些实施例中，参见图8E、9A、10A和13D至13F，显示基板1000还包括设置于第二源漏金属层LSD2中的第八连接部80。第一绝缘层IS1中还设置有第十一过孔508，第二绝缘层IS2中还设置有第十二过孔505。第八连接部80的一端通过第十一过孔508与第六晶体管T6的第六有源图案76电连接，第八连接部80的另一端通过第十二过孔505与第七连接部60电连接，从而可以实现第六晶体管T6的第六有源图案76与发光器件E的阳极图案的电连接。
本公开的一些实施例中，还提供了一种显示装置，包括上述显示基板1000。该显示装置的有益效果和上述显示基板1000的有益效果相同，此处不再赘述。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (16)

  1. 一种显示基板，具有阵列式布置的多个子像素，每列子像素包括多个第一子像素和第二子像素，第一子像素和第二子像素沿第二方向交替排列；所述显示基板包括：
    衬底；
    设置于衬底上的第一源漏金属层，所述第一源漏金属层包括多条第一数据线和多条第二数据线；其中，
    所述第一数据线和所述第二数据线沿第一方向交替排列，且每相邻两列子像素之间设置有一条第一数据线和一条第二数据线；
    沿第一方向，一列子像素与分别位于其两侧的一条第一数据线和一条第二数据线相对应，该列子像素的每个第一子像素与对应的第一数据线电连接，该列子像素的每个第二子像素与对应的第二数据线电连接；
    设置于所述衬底和所述第一源漏金属层之间的第二源漏金属层，所述第二源漏金属层包括：
    多个第一连接部，每个第一子像素通过一个第一连接部与对应的第一数据线电连接；每个第一连接部的第一端与相应的第一数据线电连接，第二端与相应的第一子像素的像素驱动电路电连接；以及
    多个第二连接部，每个第二子像素通过一个第二连接部与对应的第二数据线电连接；每个第二连接部的第一端与相应的第二数据线电连接，第二端与相应的第二子像素的像素驱动电路电连接；其中，
    同一列子像素中，第一连接部的第二端与第二连接部的第二端的第一连线大致平行于所述第二方向，所述第一连接部的第一端位于所述第一连线的第一侧，所述第二连接部的第一端位于所述第一连线的第二侧。
  2. 根据权利要求1所述的显示基板，其中，所述显示基板还包括设置于所述衬底和所述第二源漏金属层之间的有源层；
    每个子像素还包括写入晶体管，所述写入晶体管包括设置于所述有源层中的第四有源图案；沿上述第一方向，每相邻两个子像素中写入晶体管的第四有源图案之间的间距大致相等，且沿所述第二方向，每相邻两个子像素中写入晶体管的第四有源图案之间的间距大致相等；
    在每个第一子像素中，第一连接部的第二端与相应的写入晶体管的第四 有源图案电连接；在每个第二子像素中，第二连接部的第二端与相应的写入晶体管的第四有源图案电连接。
  3. 根据权利要求2所述的显示基板，其中，每行子像素包括多个第一子像素和多个第二子像素，沿所述第一方向，第一子像素和第二子像素交替排列；
    同一行子像素中，第一连接部的第二端和第二连接部的第二端之间的第二连线大致平行于所述第一方向；所述第一连接部的第一端位于所述第二连线的远离相应第四有源图案的一侧，所述第二连接部的第一端位于所述第二连线的靠近相应第四有源图案的一侧。
  4. 根据权利要求2或3所述的显示基板，还包括设置于所述第二源漏金属层和所述有源层之间的第一绝缘层，所述第一绝缘层中设置有多个第一过孔和多个第二过孔；
    在每个第一子像素中，所述第一连接部的第二端通过相应的一个第一过孔与相应的写入晶体管的第四有源图案电连接；在每个第二子像素中，所述第二连接部的第二端通过相应的一个第二过孔与相应的写入晶体管的第四有源图案电连接。
  5. 根据权利要求4所述的显示基板，其中，
    所述第一绝缘层包括第一子绝缘层和第二子绝缘层，所述第二子绝缘层设置于所述第一子绝缘层和所述衬底之间，所述显示基板还包括设置于所述第一子绝缘层和所述第二子绝缘层之间的第二栅金属层；所述第二栅金属层包括多个第一遮挡部和多个第二遮挡部，每个子像素设置有一个第一遮挡部和一个第二遮挡部；
    在每个第一子像素中，第一连接部和第二遮挡部在所述衬底上的正投影具有重叠区域，所述第一连接部和第一遮挡部在所述衬底上的正投影部分不具有重叠区域，所述第一连接部的第二端与所述第二遮挡部在所述衬底上的正投影不具有重叠区域；在每个第二子像素中，第二连接部和第一遮挡部在所述衬底上的正投影具有重叠区域，所述第二连接部和第二遮挡部在所述衬底上的正投影部分不具有重叠区域，所述第二连接部的第二端和所述第一遮挡部不具有重叠区域。
  6. 根据权利要求5所述的显示基板，其中，沿所述第一方向，在同一行 子像素中，第一遮挡部和第二遮挡部交替排列，相邻的、且分别位于不同子像素中的第一遮挡部和第二遮挡部为一体成型。
  7. 根据权利要求1～6中任一项所述的显示基板，其中，每个第一连接部在其延伸方向上的最大尺寸，大于每个第二连接部在其延伸方向上的最大尺寸。
  8. 根据权利要求1～7中任一项所述的显示基板，其中，每个第一连接部的第一端的面积大于其第二端的面积，和/或，每个第二连接部的第一端的面积大于其第二端的面积。
  9. 根据权利要求1～8中任一项所述的显示基板，其中，每条第一数据线包括第一本体和多个第五连接部；所述多个第五连接部设置于所述第一本体的靠近相应第一子像素的一侧，并沿所述第二方向排列；每个第五连接部电连接于所述第一本体与相应的第一连接部的第一端之间；
    每条第二数据线包括第二本体和多个第六连接部；所述多个第六连接部设置于所述第二本体的靠近相应第二子像素的一侧，并沿所述第二方向排列；每个第六连接部电连接于所述第二本体与相应的第二连接部的第一端之间。
  10. 根据权利要求9所述的显示基板，还包括设置于所述第一源漏金属层和所述第二源漏金属层之间的第二绝缘层，所述第二绝缘层中设置有多个第三过孔和多个第四过孔；
    每个第五连接部通过相应的一个第三过孔与相应的第一连接部的第一端电连接，每个第六连接部通过相应的一个第四过孔与相应的第二连接部的第一端电连接。
  11. 根据权利要求1～10任一项所述的显示基板，还包括多条第一电压信号线，每条第一电压信号线在所述衬底上的正投影位于每相邻两列子像素之间的第一数据线和第二数据线在所述衬底上的正投影之间，所述第一电压信号线与至少一列子像素电连接；
    所述第一电压信号线包括：设置于所述第一源漏金属层中的第一子电压信号线，和设置于所述第二源漏金属层中的第二子电压信号线，所述第一子电压信号线与所述第二子电压信号线电连接。
  12. 根据权利要求11所述的显示基板，其中，所述显示基板包括第二绝缘层的情况下，所述第二绝缘层中设置有多个第五过孔；所述第一子电压信号线和所述第二子电压信号线通过所述多个第五过孔中的至少一个第五过孔电连接；其中，位于相邻两列子像素之间的第一数据线、第二数据线和第一子电压信号线中，
    所述第一数据线中与所述第五过孔相邻的部分向远离所述第五过孔的方向弯曲，形成第一弯曲部；
    所述第二数据线中与所述第五过孔相邻的部分向远离所述第五过孔的方向弯曲，形成第二弯曲部；
    所述第一弯曲部和所述第二弯曲部相对，形成容纳区域；
    所述第一子电压信号线包括经过所述第五过孔的导电部，所述导电部位于所述容纳区域内；沿所述第一方向，所述导电部的尺寸大于所述第一子电压信号线的宽度。
  13. 根据权利要求12所述的显示基板，其中，与一列子像素相邻，且位于该列子像素沿所述第一方向的两侧的第一数据线和第二数据线中，所述第一弯曲部与所述第二弯曲部之间设置有第七连接部，所述第七连接部与所述第一子电压信号线同层设置。
  14. 根据权利要求13所述的显示基板，还包括设置于所述第一源漏金属层远离所述衬底一侧的阳极层；
    每个子像素还包括第一发光控制晶体管，所述第一发光控制晶体管包括设置于有源层中的第六有源图案，所述第六有源图案包括第一导体部分；所述第七连接部与所述第一导体部分，以及所述阳极层电连接。
  15. 根据权利要求1所述的显示基板，其中，所述第一连线的第一侧为所述第一连线的靠近该列子像素对应的第一数据线的一侧，所述第一连线的第二侧为所述第一连线的靠近该列子像素对应的第二数据线的一侧。
  16. 一种显示装置，包括如权利要求1～15任一项所述的显示基板。
PCT/CN2021/075966 2021-02-08 2021-02-08 显示基板及显示装置 WO2022165831A1 (zh)

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