WO2022056825A1 - 一种显示基板、显示面板及显示装置 - Google Patents

一种显示基板、显示面板及显示装置 Download PDF

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Publication number
WO2022056825A1
WO2022056825A1 PCT/CN2020/116152 CN2020116152W WO2022056825A1 WO 2022056825 A1 WO2022056825 A1 WO 2022056825A1 CN 2020116152 W CN2020116152 W CN 2020116152W WO 2022056825 A1 WO2022056825 A1 WO 2022056825A1
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gate
layer
base substrate
substrate
film transistor
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PCT/CN2020/116152
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English (en)
French (fr)
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黄耀
承天一
黄炜赟
龙跃
王本莲
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京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Priority to PCT/CN2020/116152 priority Critical patent/WO2022056825A1/zh
Priority to US17/417,492 priority patent/US20220336676A1/en
Priority to CN202080002038.6A priority patent/CN114556566B/zh
Publication of WO2022056825A1 publication Critical patent/WO2022056825A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor
    • H01L29/78675—Polycrystalline or microcrystalline silicon transistor with normal-type structure, e.g. with top gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78645—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate
    • H01L29/78648—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate arranged on opposing sides of the channel
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/124—Insulating layers formed between TFT elements and OLED elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a display substrate, a display panel and a display device.
  • Low temperature polycrystalline oxide (English: Low temperature polycrystalline oxide; referred to as: LTPO) substrate is a new type of display substrate, which has low temperature polycrystalline silicon (English: Low Temperature Poly-silicon; referred to as: LTPS) substrate and oxide (English: The advantages of Oxide substrates are the main development direction of display substrates in the future.
  • the LTPS substrate refers to the thin film transistor (English: Thin Film Transistor; TFT for short) in the display unit which is the display substrate of the LTPS TFT
  • the oxide substrate refers to the display substrate in which the TFT in the display unit is the oxide TFT
  • LTPO substrate refers to a display substrate including LTPS TFT and oxide TFT in each display unit, and the display unit is also called sub-pixel.
  • a top-gate oxide thin film transistor located on the base substrate
  • a top-gate low-temperature polysilicon thin film transistor is located on the base substrate, and the top-gate low-temperature polysilicon thin film transistor includes a first active layer and a first gate that are stacked on the base substrate;
  • a first gate insulating layer located between the first active layer and the first gate
  • a second gate insulating layer located between the first gate insulating layer and the first gate electrode
  • the second gate is located between the first gate insulating layer and the second gate insulating layer, and the orthographic projection of the second gate on the base substrate is the same as that of the top-gate low temperature polysilicon thin film transistor
  • the orthographic projections of the second gate on the base substrate do not overlap, and the orthographic projection of the second gate on the base substrate covers the orthographic projection of the top-gate oxide thin film transistor on the base substrate projection.
  • the material of the first gate insulating layer is silicon oxide
  • the material of the second gate insulating layer is silicon oxide or silicon nitride.
  • the top-gate oxide thin film transistor includes: a second active layer and a third gate that are stacked on the base substrate, and a second active layer and a third gate that are disposed on the base substrate. a first source electrode and a first drain electrode on a side of the third gate away from the base substrate, the first source electrode and the first drain electrode are respectively electrically connected to the second active layer;
  • the orthographic projection of the second gate on the base substrate covers the orthographic projection of the second active layer on the base substrate;
  • the top-gate low temperature polysilicon thin film transistor further includes a second source electrode and a second drain electrode located on the side of the first gate electrode away from the base substrate, the second source electrode and the second drain electrode respectively electrically connected to the first active layer;
  • the first source electrode and the first drain electrode are located in the same layer as the second source electrode and the second drain electrode.
  • the above-mentioned display substrate provided in the embodiment of the present disclosure further includes: a first buffer layer located between the first gate electrode and the second active layer, and a first buffer layer located on the first buffer layer and the second buffer layer between the second active layer; the material of the first buffer layer is silicon nitride, and the material of the second buffer layer is silicon oxide.
  • the above-mentioned display substrate provided by the embodiment of the present disclosure further includes a third gate insulating layer located between the second active layer and the third gate electrode, and the third gate insulating layer has a The material is silicon oxide.
  • the above-mentioned display substrate provided by the embodiment of the present disclosure, it further includes: an interlayer insulating layer located between the third gate electrode and the first source electrode, and located away from the first source electrode. a first flat layer on the side of the base substrate, a second source-drain metal layer on the side of the first flat layer away from the base substrate, and a second source-drain metal layer on the side of the second source-drain metal layer away from the base substrate a second flat layer on one side, and an anode located on the side of the second flat layer away from the base substrate;
  • the second source-drain metal layer is electrically connected to the second drain through a via hole penetrating the first planar layer, and the anode is connected to the second source-drain via a via hole penetrating the second planar layer
  • the metal layers are electrically connected.
  • the above-mentioned display substrate provided in the embodiment of the present disclosure further includes: a pixel definition layer on the side of the anode away from the base substrate, and a spacer layer on the pixel definition layer.
  • the above-mentioned display substrate provided by the embodiment of the present disclosure further includes: a barrier layer located between the base substrate and the first active layer, and a barrier layer located between the barrier layer and the first active layer a third buffer layer between the active layers.
  • an embodiment of the present disclosure further provides a display panel, including the above-mentioned display substrate provided by an embodiment of the present disclosure.
  • an embodiment of the present disclosure further provides a display device including the above-mentioned display panel provided by an embodiment of the present disclosure.
  • FIG. 1 is a schematic partial cross-sectional structure diagram of a display substrate according to an embodiment of the present disclosure
  • FIG. 2 is a schematic partial cross-sectional structural diagram of still another display substrate according to an embodiment of the present disclosure
  • FIG. 3 is a schematic structural diagram of a display device according to an embodiment of the present disclosure.
  • the display substrate is the main component of the display device, which includes a base substrate and a display unit disposed on the base substrate, and the display unit includes a thin film transistor (Thin Film Transistor, TFT).
  • TFT Thin Film Transistor
  • the LTPS substrate refers to the display substrate in which the TFT in the display unit is an LTPS TFT
  • the oxide substrate refers to the display substrate in which the TFT in the display unit is an oxide TFT.
  • the mobility of the polysilicon active layer is large, which makes the leakage current (Ioff) of the LTPS TFT large, and the power consumption of the LTPS substrate under low-frequency driving is large, so it is difficult to maintain a static black picture well, and the picture quality is poor; and, In order to better develop the gray scale, in the LTPS substrate, the channel of the Driver Thin Film Transistor (DTFT) needs to be made very long, which makes it difficult to achieve the high resolution of the LTPS substrate.
  • Ioff leakage current
  • DTFT Driver Thin Film Transistor
  • the resolution refers to The number of pixels per inch (Pixel Per Inch, PPI); in addition, the hysteresis (Hysteresis) of the polysilicon active layer is relatively large, so the LTPS substrate is prone to the problem of image afterimage.
  • the mobility of the oxide active layer is small, so that the leakage current of the oxide TFT is small, and the power consumption of the oxide substrate under low-frequency driving is small, which can well maintain a static black picture and improve the picture quality;
  • the oxide substrate there is no need to make the channel of the DTFT very long, so that the gray scale can be better developed and high PPI can be achieved;
  • the hysteresis of the oxide active layer is small, and the oxide substrate is not prone to image afterimage problems. ; Further, the uniformity of oxide TFT is better than that of LTPS TFT.
  • the oxide process can well make up for some deficiencies of the LTPS process.
  • the LTPS process and the oxide process have their own advantages and disadvantages. Therefore, the combination of the LTPS process and the oxide process is a very competitive process solution.
  • the process of combining the LTPS process and the oxide process is the LTPO process. It is likely to be used in the development of high-end products.
  • the display substrate based on the LTPO process is an LTPO substrate.
  • each display unit includes an LTPS TFT and an oxide TFT.
  • a display substrate provided by an embodiment of the present disclosure, as shown in FIG. 1 and FIG. 2 includes:
  • the top-gate oxide thin film transistor 2 is located on the base substrate 1;
  • the top-gate low-temperature polysilicon thin film transistor 3 is located on the base substrate 1, and the top-gate low-temperature polysilicon thin film transistor 3 includes a first active layer 31 and a first gate 32 that are stacked on the base substrate 1; the present disclosure implements For example, the orthographic projection of the top gate type low temperature polysilicon thin film transistor 3 on the base substrate 1 and the orthographic projection of the top gate type oxide thin film transistor 2 on the base substrate 1 are not overlapped as an example for schematic illustration;
  • the first gate insulating layer 4 is located between the first active layer 31 and the first gate electrode 32;
  • the second gate insulating layer 5 is located between the first gate insulating layer 4 and the first gate electrode 32;
  • the second gate 6 is located between the first gate insulating layer 4 and the second gate insulating layer 5.
  • the orthographic projection of the second gate 6 on the base substrate 1 is the same as that of the top gate type low temperature polysilicon thin film transistor 3 on the base substrate.
  • the orthographic projections on 1 do not overlap, and the orthographic projection of the second gate 6 on the base substrate 1 covers the orthographic projection of the top-gate oxide thin film transistor 2 on the base substrate 1 .
  • the first gate insulating layer 4 and the second gate insulating layer 5 are disposed between the first active layer 31 and the first gate electrode 32 of the top-gate low temperature polysilicon thin film transistor 3 .
  • a gate insulating layer is formed, and the second gate 6 covering the top-gate oxide thin film transistor 2 is arranged between the first gate insulating layer 4 and the second gate insulating layer 5, so that the overall thickness of the display module is not increased.
  • the thickness of the gate insulating layer of the top-gate low-temperature polysilicon thin film transistor 3 can be increased, so that the leakage current of the top-gate low-temperature polysilicon thin film transistor 3 can be reduced, the uniformity of its characteristics can be increased, and the display picture quality can be improved;
  • the thickness of the gate insulating layer of the large top-gate low-temperature polysilicon thin film transistor 3 can reduce the inter-electrode capacitance of the top-gate low-temperature polysilicon thin film transistor 3, thereby reducing the gate load, reducing the RC delay on the gate line, and improving the gate The charging time of the cable.
  • the above-mentioned orthographic projection of the second gate 6 on the base substrate 1 covers the orthographic projection of the top-gate oxide thin film transistor 2 on the base substrate 1, which means that the second gate 6 is located on the base substrate 1.
  • the orthographic projection on the base substrate 1 can at least completely block the orthographic projection of the top gate type oxide thin film transistor 2 on the base substrate 1, that is, the orthographic projection area of the second gate 6 on the base substrate 1 is greater than or equal to the top gate
  • the orthographic projection area of the type oxide thin film transistor 2 on the base substrate 1 is greater than or equal to the top gate
  • the material of the gate insulating layer generally includes silicon oxide or silicon nitride. Silicon oxide has few defects and can improve the mobility of carriers, while silicon nitride has better insulating properties. Therefore, in the implementation of the present disclosure
  • the material of the first gate insulating layer close to the first active layer can be silicon oxide, which can improve the carrier mobility of the top-gate low temperature polysilicon thin film transistor, and the second gate insulating layer
  • the material can be silicon oxide or silicon nitride.
  • the material of the first gate insulating layer 4 is silicon oxide
  • the material of the second gate insulating layer 5 is silicon nitride
  • the material of the first gate insulating layer 4 is oxide Silicon
  • the material of the second gate insulating layer 5 is also silicon oxide.
  • the top-gate oxide thin film transistor 2 includes: a second active layer stacked on the base substrate 1 21 and the third gate 22, and the first source 23 and the first drain 24 on the side of the third gate 22 away from the base substrate 1, the first source 23 and the first drain 24 are respectively connected with the second
  • the active layer 21 is electrically connected; since the second active layer 21 of the top-gate oxide thin film transistor 2 is made of oxide material, its performance will be destroyed by the influence of external ambient light, the present disclosure places the second gate 6 on the substrate
  • the orthographic projection on the substrate 1 is set to cover the orthographic projection of the second active layer 21 on the base substrate 1 , so the second gate 6 provided in the embodiment of the present disclosure can protect the top-gate oxide thin film transistor 2 .
  • the second active layer 21 is not affected by external ambient light, thereby improving the performance of the top-gate oxide thin film transistor 2;
  • the top-gate low-temperature polysilicon thin film transistor 3 further includes a second source electrode 33 and a second drain electrode 34 located on the side of the first gate electrode 32 away from the base substrate 1, and the second source electrode 33 and the second drain electrode 34 are respectively connected with the first An active layer 31 is electrically connected; specifically, the part of the first active layer 31 that is electrically connected to the second source electrode 33 and the second drain electrode 34 is a conductive region, and ion doping can be used to form a conductive region;
  • the first source electrode 23 and the first drain electrode 24 and the second source electrode 33 and the second drain electrode 34 are located in the same layer. In this way, it is only necessary to change the original patterning pattern when forming the first source electrode 23 and the first drain electrode 24, and then the second source electrode 33 and the second drain electrode 34 and the first source electrode 23 and the first source electrode 23 and the first source electrode 23 and The pattern of the first drain electrode 24 does not need to increase the process of separately preparing the second source electrode 33 and the second drain electrode 34, which can simplify the manufacturing process flow, save the production cost, and improve the production efficiency.
  • the third gate 22 is a gate of the top-gate oxide thin film transistor 2
  • the second gate 6 can also be used as a gate of the top-gate oxide thin film transistor 2
  • the other gate so the top-gate oxide thin film transistor 2 is a thin film transistor with a double gate structure, and the double gate structure can reduce the current of the drain thin film transistor and improve the stability of the circuit structure where it is located.
  • the above-mentioned orthographic projection of the second gate 6 on the base substrate 1 covers the orthographic projection of the second active layer 21 on the base substrate 1, which means that the second gate 6 is on the substrate
  • the orthographic projection on the substrate 1 can at least completely block the orthographic projection of the second active layer 21 on the base substrate 1 , that is, the orthographic projection area of the second gate 6 on the base substrate 1 is greater than or equal to the second active layer 21 The orthographic projection area on the base substrate 1 .
  • the above-mentioned display substrate provided in the embodiment of the present disclosure further includes: a first buffer layer 7 located between the first gate electrode 32 and the second active layer 21 . , and the second buffer layer 8 between the first buffer layer 7 and the second active layer 21 ; the material of the first buffer layer 7 can be silicon nitride, and the material of the second buffer layer 8 can be silicon oxide.
  • the first buffer layer 7 and the second buffer layer 8 can play a role of flattening and improving the adhesion between the subsequent film layer and the base substrate 1 .
  • a third gate insulating layer 9 located between the second active layer 21 and the third gate electrode 22 is further included , the material of the third gate insulating layer 9 may be silicon oxide.
  • the above-mentioned display substrate provided in the embodiment of the present disclosure further includes: an interlayer insulating layer 10 located between the third gate electrode 22 and the first source electrode 23 , The first flat layer 11 on the side of the first source electrode 23 away from the base substrate 1, the second source-drain metal layer 12 on the side of the first flat layer 11 away from the base substrate 1, and the second source-drain metal layer 12 the second flat layer 13 on the side away from the base substrate 1, and the anode 14 on the side of the second flat layer 13 away from the base substrate 1;
  • the second source-drain metal layer 12 is electrically connected to the second drain 34 through vias penetrating the first planar layer 11
  • the anode 14 is electrically connected to the second source-drain metal layer 12 through vias penetrating the second planar layer 13 .
  • the above-mentioned display substrate provided by the embodiment of the present disclosure further includes: a pixel definition layer 15 located on the side of the anode 14 away from the base substrate 1 , and a pixel definition layer located on the side of the anode 14 away from the base substrate 1 .
  • Spacer layer 16 on 15 Specifically, the pixel definition layer 15 has a plurality of pixel openings, and each pixel opening exposes a part of the anode 14 , and the light-emitting layer and the cathode on the side of the anode 14 away from the base substrate 1 are subsequently fabricated, as well as other functionalities such as subsequent encapsulation layers.
  • the film layer is not described in detail here.
  • the spacer layer 16 plays a supporting role when the display substrate and the glass cover plate are subsequently assembled into a cell.
  • the anode voltage is input to the anode through the thin film transistor
  • the cathode voltage is input to the cathode, that is, under the driving of the external voltage, the electrons injected by the cathode and the holes injected by the anode recombine in the light-emitting layer to form electron holes at the bound energy level
  • exciton radiation de-excites photons, producing visible light.
  • the above-mentioned display substrate provided in the embodiment of the present disclosure further includes: a barrier layer 17 located between the base substrate 1 and the first active layer 31 , and a barrier layer 17 located between the base substrate 1 and the first active layer 31
  • the third buffer layer 18 between the barrier layer 17 and the first active layer 31 is used to block external water vapor
  • the third buffer layer 18 is used to improve the adhesion between the film layer to be produced later and the base substrate 1 .
  • the material of the barrier layer 17 may be one or a combination of silicon oxide and silicon nitride, and the material of the third buffer layer 18 may be silicon oxide.
  • the display device provided by the embodiments of the present disclosure may also include other functional film layers known to those skilled in the art, which will not be described in detail here.
  • an embodiment of the present disclosure further provides a display panel, including the above-mentioned display substrate provided by an embodiment of the present disclosure.
  • the display panel provided by the embodiment of the present disclosure is an organic light-emitting display panel.
  • an embodiment of the present disclosure further provides a display device, including the above-mentioned display panel provided by an embodiment of the present disclosure.
  • the problem-solving principle of the display device is similar to that of the aforementioned display substrate. Therefore, the implementation of the display device can refer to the aforementioned implementation of the display substrate, and repeated details will not be repeated here.
  • the above-mentioned display device provided by the embodiment of the present disclosure may be an organic light-emitting display device.
  • the above-mentioned display device provided by the embodiments of the present disclosure may be a full-screen display device, or may also be a flexible display device, etc., which is not limited herein.
  • the above-mentioned display device provided by the embodiment of the present disclosure may be a mobile phone with a full screen as shown in FIG. 3 .
  • the above-mentioned display device provided by the embodiments of the present disclosure may also be any product or component with a display function, such as a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, and a navigator.
  • a display function such as a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, and a navigator.
  • Other essential components of the display device should be understood by those of ordinary skill in the art, and will not be repeated here, nor should it be regarded as a limitation of the present disclosure.
  • a first gate insulating layer and a second gate insulating layer are provided between the first active layer and the first gate electrode of the top-gate low temperature polysilicon thin film transistor
  • Two-layer gate insulating layers, and the second gate covering the top-gate oxide thin film transistor is arranged between the first gate insulating layer and the second gate insulating layer, so that on the basis of not increasing the overall thickness of the display module,
  • the thickness of the gate insulating layer of the top-gate low-temperature polysilicon thin film transistor can be increased, thereby reducing the leakage current of the top-gate low-temperature polysilicon thin-film transistor, increasing its characteristic uniformity, and improving the display quality; in addition, increasing the top-gate low-temperature polysilicon thin film transistor
  • the thickness of the gate insulating layer of the polysilicon thin film transistor can reduce the inter-electrode capacitance of the top-gate low temperature polysilicon thin film transistor, thereby

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Abstract

本公开实施例公开了一种显示基板、显示面板及显示装置，顶栅型氧化物薄膜晶体管，顶栅型低温多晶硅薄膜晶体管，位于衬底基板上，顶栅型低温多晶硅薄膜晶体管在衬底基板上的正投影与顶栅型氧化物薄膜晶体管在衬底基板上的正投影不交叠，顶栅型低温多晶硅薄膜晶体管包括位于衬底基板上层叠设置的第一有源层和第一栅极；第一栅绝缘层，位于第一有源层和第一栅极之间；第二栅绝缘层，位于第一栅绝缘层和第一栅极之间；第二栅极，位于第一栅绝缘层和第二栅绝缘层之间，第二栅极在衬底基板上的正投影与顶栅型低温多晶硅薄膜晶体管在衬底基板上的正投影不交叠，且第二栅极在衬底基板上的正投影覆盖顶栅型氧化物薄膜晶体管在衬底基板上的正投影。

Description

一种显示基板、显示面板及显示装置 技术领域
本公开涉及显示技术领域，特别涉及一种显示基板、显示面板及显示装置。
背景技术
低温多晶氧化物(英文：Low temperature polycrystalline oxide；简称：LTPO)基板是一种新型的显示基板，其具有低温多晶硅(英文：Low Temperature Poly-silicon；简称：LTPS)基板和氧化物(英文：Oxide)基板的优点，是未来显示基板的主要发展方向。其中，LTPS基板指的是显示单元中的薄膜晶体管(英文：Thin Film Transistor；简称：TFT)为LTPS TFT的显示基板，氧化物基板指的是显示单元中的TFT为氧化物TFT的显示基板，LTPO基板指的每个显示单元中包括LTPS TFT和氧化物TFT的显示基板，显示单元也称为子像素。
发明内容
本公开实施例提供的一种显示基板，包括：
衬底基板；
顶栅型氧化物薄膜晶体管，位于所述衬底基板上；
顶栅型低温多晶硅薄膜晶体管，位于所述衬底基板上，所述顶栅型低温多晶硅薄膜晶体管包括位于所述衬底基板上层叠设置的第一有源层和第一栅极；
第一栅绝缘层，位于所述第一有源层和所述第一栅极之间；
第二栅绝缘层，位于所述第一栅绝缘层和所述第一栅极之间；
第二栅极，位于所述第一栅绝缘层和所述第二栅绝缘层之间，所述第二栅极在所述衬底基板上的正投影与所述顶栅型低温多晶硅薄膜晶体管在所述衬底基板上的正投影不交叠，且所述第二栅极在所述衬底基板上的正投影覆 盖所述顶栅型氧化物薄膜晶体管在所述衬底基板上的正投影。
可选地，在本公开实施例提供的上述显示基板中，所述第一栅绝缘层的材料为氧化硅，所述第二栅绝缘层的材料为氧化硅或氮化硅。
可选地，在本公开实施例提供的上述显示基板中，所述顶栅型氧化物薄膜晶体管包括：位于所述衬底基板上层叠设置的第二有源层和第三栅极，以及位于所述第三栅极背离所述衬底基板一侧的第一源极和第一漏极，所述第一源极和所述第一漏极分别与所述第二有源层电连接；所述第二栅极在所述衬底基板上的正投影覆盖所述第二有源层在所述衬底基板上的正投影；
所述顶栅型低温多晶硅薄膜晶体管还包括位于所述第一栅极背离所述衬底基板一侧的第二源极和第二漏极，所述第二源极和所述第二漏极分别与所述第一有源层电连接；
所述第一源极和所述第一漏极与所述第二源极和所述第二漏极位于同一层。
可选地，在本公开实施例提供的上述显示基板中，还包括：位于所述第一栅极和所述第二有源层之间的第一缓冲层，以及位于所述第一缓冲层和所述第二有源层之间的第二缓冲层；所述第一缓冲层的材料为氮化硅，所述第二缓冲层的材料为氧化硅。
可选地，在本公开实施例提供的上述显示基板中，还包括位于所述第二有源层和所述第三栅极之间的第三栅绝缘层，所述第三栅绝缘层的材料为氧化硅。
可选地，在本公开实施例提供的上述显示基板中，还包括：位于所述第三栅极和所述第一源极之间的层间绝缘层，位于所述第一源极背离所述衬底基板一侧的第一平坦层，位于所述第一平坦层背离所述衬底基板一侧的第二源漏金属层，位于所述第二源漏金属层背离所述衬底基板一侧的第二平坦层，以及位于所述第二平坦层背离所述衬底基板一侧的阳极；
所述第二源漏金属层通过贯穿所述第一平坦层的过孔与所述第二漏极电连接，所述阳极通过贯穿所述第二平坦层的过孔与所述第二源漏金属层电连 接。
可选地，在本公开实施例提供的上述显示基板中，还包括：位于所述阳极背离所述衬底基板一侧的像素定义层，以及位于所述像素定义层上的隔垫物层。
可选地，在本公开实施例提供的上述显示基板中，还包括：位于所述衬底基板和所述第一有源层之间的阻挡层，以及位于所述阻挡层和所述第一有源层之间的第三缓冲层。
相应地，本公开实施例还提供了一种显示面板，包括本公开实施例提供的上述显示基板。
相应地，本公开实施例还提供了一种显示装置，包括本公开实施例提供的上述显示面板。
附图说明
图1为本公开实施例提供的一种显示基板的局部截面结构示意图；
图2为本公开实施例提供的又一种显示基板的局部截面结构示意图；
图3为本公开实施例提供的一种显示装置的结构示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。并且在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互组合。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面 列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“内”、“外”、“上”、“下”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
需要注意的是，附图中各图形的尺寸和形状不反映真实比例，目的只是示意说明本公开内容。并且自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。
显示基板是显示装置的主要部件，其包括衬底基板以及设置在衬底基板上的显示单元，显示单元包括薄膜晶体管(Thin Film Transistor，TFT)。LTPS基板指的是显示单元中的TFT为LTPS TFT的显示基板，氧化物基板指的是显示单元中的TFT为氧化物TFT的显示基板。多晶硅有源层的迁移率较大，使得LTPS TFT的漏电流(Ioff)较大，LTPS基板在低频驱动下的功耗较大，难以很好的保持静态黑画面，画面品质较差；并且，为了更好的展开灰阶，在LTPS基板中，需要将驱动薄膜晶体管(Driver Thin Film Transistor，DTFT)的沟道制作的很长，这样就难以实现LTPS基板的高分辨率，分辨率指的是每英寸所设置的像素数目(Pixel Per Inch，PPI)；此外，多晶硅有源层的迟滞(Hysteresis)较大，因此LTPS基板容易出现画面残像的问题。氧化物有源层的迁移率较小，使得氧化物TFT的漏电流较小，氧化物基板在低频驱动下的功耗较小，能够很好的保持静态黑画面，提升画面品质；并且，在氧化物基板中，无需将DTFT的沟道制作的很长，就能更好的展开灰阶，实现高PPI；此外，氧化物有源层的迟滞较小，氧化物基板不容易出现画面残像问题；进一步地，氧化物TFT的均一性比LTPS TFT的均一性好。
根据以上描述可知，氧化物工艺能够很好的弥补LTPS工艺的一些不足。但是，LTPS工艺和氧化物工艺各有利弊，因此，将LTPS工艺和氧化物工艺结合是一种非常有竞争力的工艺方案，将LTPS工艺和氧化物工艺结合的工艺为LTPO工艺，LTPO工艺未来很有可能应用在高端产品的开发中。
基于LTPO工艺的显示基板为LTPO基板，在LTPO基板中，每个显示单元包括LTPS TFT和氧化物TFT。
本公开实施例提供的一种显示基板，如图1和图2所示，包括：
衬底基板1；
顶栅型氧化物薄膜晶体管2，位于衬底基板1上；
顶栅型低温多晶硅薄膜晶体管3，位于衬底基板1上，顶栅型低温多晶硅薄膜晶体管3包括位于衬底基板1上层叠设置的第一有源层31和第一栅极32；本公开实施例以顶栅型低温多晶硅薄膜晶体管3在衬底基板1上的正投影与顶栅型氧化物薄膜晶体管2在衬底基板1上的正投影不交叠为例进行示意说明；
第一栅绝缘层4，位于第一有源层31和第一栅极32之间；
第二栅绝缘层5，位于第一栅绝缘层4和第一栅极32之间；
第二栅极6，位于第一栅绝缘层4和第二栅绝缘层5之间，第二栅极6在衬底基板1上的正投影与顶栅型低温多晶硅薄膜晶体管3在衬底基板1上的正投影不交叠，且第二栅极6在衬底基板1上的正投影覆盖顶栅型氧化物薄膜晶体管2在衬底基板1上的正投影。
本公开实施例提供的上述显示基板，通过在顶栅型低温多晶硅薄膜晶体管3的第一有源层31和第一栅极32之间设置第一栅绝缘层4和第二栅绝缘层5两层栅绝缘层，且将覆盖顶栅型氧化物薄膜晶体管2的第二栅极6设置在第一栅绝缘层4和第二栅绝缘层5之间，这样在不增加显示模组整体厚度的基础上，可以增大顶栅型低温多晶硅薄膜晶体管3的栅绝缘层的厚度，从而可以降低顶栅型低温多晶硅薄膜晶体管3的漏电流，增加其特性均一性，提高显示画面品质；另外，增大顶栅型低温多晶硅薄膜晶体管3的栅绝缘层的厚度，可以降低顶栅型低温多晶硅薄膜晶体管3的极间电容，从而可以降低栅极负载，减小栅线上的RC delay，进而提高栅线的充电时长。
需要说明的是，上述所说的第二栅极6在衬底基板1上的正投影覆盖顶栅型氧化物薄膜晶体管2在衬底基板1上的正投影，是指第二栅极6在衬底基板1上的正投影能够至少完全遮挡顶栅型氧化物薄膜晶体管2在衬底基板1上的正 投影，即第二栅极6在衬底基板1上的正投影面积大于等于顶栅型氧化物薄膜晶体管2在衬底基板1上的正投影面积。
在具体实施时，栅绝缘层的材料一般包括氧化硅或氮化硅，氧化硅的缺陷少，可以提高载流子的迁移率，而氮化硅的绝缘性能较好，因此，在本公开实施例提供的上述显示基板中，靠近第一有源层的第一栅绝缘层的材料可以为氧化硅，这样可以提高顶栅型低温多晶硅薄膜晶体管的载流子迁移率，第二栅绝缘层的材料可以为氧化硅或氮化硅。具体地，如图1所示，第一栅绝缘层4的材料为氧化硅，第二栅绝缘层5的材料为氮化硅；如图2所示，第一栅绝缘层4的材料为氧化硅，第二栅绝缘层5的材料也为氧化硅。
在具体实施时，在本公开实施例提供的上述显示基板中，如图1和图2所示，顶栅型氧化物薄膜晶体管2包括：位于衬底基板1上层叠设置的第二有源层21和第三栅极22，以及位于第三栅极22背离衬底基板1一侧的第一源极23和第一漏极24，第一源极23和第一漏极24分别与第二有源层21电连接；由于顶栅型氧化物薄膜晶体管2的第二有源层21为氧化物材料，受到外界环境光的影响会破坏其性能，本公开将第二栅极6在衬底基板1上的正投影设置成覆盖第二有源层21在衬底基板1上的正投影，因此本公开实施例提供的第二栅极6可以起到保护顶栅型氧化物薄膜晶体管2的第二有源层21不受外界环境光的影响，从而提高顶栅型氧化物薄膜晶体管2的性能；
顶栅型低温多晶硅薄膜晶体管3还包括位于第一栅极32背离衬底基板1一侧的第二源极33和第二漏极34，第二源极33和第二漏极34分别与第一有源层31电连接；具体地，第一有源层31中与第二源极33和第二漏极34电连接的部分均为导体化区域，可以采用离子掺杂形成导体化区；
第一源极23和第一漏极24与第二源极33和第二漏极34位于同一层。这样，只需要在形成第一源极23和第一漏极24时改变原有的构图图形，即可通过一次构图工艺形成第二源极33和第二漏极34与第一源极23和第一漏极24的图形，不用增加单独制备第二源极33和第二漏极34的工艺，可以简化制备工艺流程，节省生产成本，提高生产效率。
在具体实施时，如图1和图2所示，第三栅极22是顶栅型氧化物薄膜晶体管2的一个栅极，第二栅极6也可以作为顶栅型氧化物薄膜晶体管2的另一个栅极，这样顶栅型氧化物薄膜晶体管2为具有双栅结构的薄膜晶体管，双栅结构可以降低漏薄膜晶体管的电流，提高其所在电路结构的稳定性。
需要说明的是，上述所说的第二栅极6在衬底基板1上的正投影覆盖第二有源层21在衬底基板1上的正投影，是指第二栅极6在衬底基板1上的正投影能够至少完全遮挡第二有源层21在衬底基板1上的正投影，即第二栅极6在衬底基板1上的正投影面积大于等于第二有源层21在衬底基板1上的正投影面积。
在具体实施时，在本公开实施例提供的上述显示基板中，如图1和图2所示，还包括：位于第一栅极32和第二有源层21之间的第一缓冲层7，以及位于第一缓冲层7和第二有源层21之间的第二缓冲层8；第一缓冲层7的材料可以为氮化硅，第二缓冲层8的材料可以为氧化硅。具体地，第一缓冲层7和第二缓冲层8可以起到平坦以及提高后续膜层与衬底基板1之间附着力的作用。
在具体实施时，在本公开实施例提供的上述显示基板中，如图1和图2所示，还包括位于第二有源层21和第三栅极22之间的第三栅绝缘层9，第三栅绝缘层9的材料可以为氧化硅。
在具体实施时，在本公开实施例提供的上述显示基板中，如图1和图2所示，还包括：位于第三栅极22和第一源极23之间的层间绝缘层10，位于第一源极23背离衬底基板1一侧的第一平坦层11，位于第一平坦层11背离衬底基板1一侧的第二源漏金属层12，位于第二源漏金属层12背离衬底基板1一侧的第二平坦层13，以及位于第二平坦层13背离衬底基板1一侧的阳极14；
第二源漏金属层12通过贯穿第一平坦层11的过孔与第二漏极34电连接，阳极14通过贯穿第二平坦层13的过孔与第二源漏金属层12电连接。
在具体实施时，在本公开实施例提供的上述显示基板中，如图1和图2所示，还包括：位于阳极14背离衬底基板1一侧的像素定义层15，以及位于像素定义层15上的隔垫物层16。具体地，像素定义层15具有多个像素开口，各像素开口裸露出部分阳极14，后续再制作位于阳极14背离衬底基板1一侧的发光 层以及阴极，以及后续的封装层等其它功能性膜层，在此不做详述。隔垫物层16在后续显示基板与玻璃盖板对盒时起到支撑的作用。
具体地，通过薄膜晶体管向阳极输入阳极电压，阴极输入阴极电压，即在外界电压的驱动下，由阴极注入的电子和阳极注入的空穴在发光层中复合形成处于束缚能级的电子空穴对即激子，激子辐射退激发出光子，产生可见光。
在具体实施时，在本公开实施例提供的上述显示基板中，如图1和图2所示，还包括：位于衬底基板1和第一有源层31之间的阻挡层17，以及位于阻挡层17和第一有源层31之间的第三缓冲层18。具体地，阻挡层17是为了阻隔外界水汽，第三缓冲层18是为了提高后续制作的膜层与衬底基板1之间的附着力。阻挡层17的材料可以为氧化硅、氮化硅其中之一或组合，第三缓冲层18的材料可以为氧化硅。
当然，本公开实施例提供的显示装置还可以包括本领域技术人员熟知的其他功能性膜层，在此不做详述。
基于同一发明构思，本公开实施例还提供了一种显示面板，包括本公开实施例提供的上述显示基板。
具体地，本公开实施例提供的显示面板为有机发光显示面板。
基于同一发明构思，本公开实施例还提供了一种显示装置，包括本公开实施例提供的上述显示面板。该显示装置解决问题的原理与前述显示基板相似，因此该显示装置的实施可以参见前述显示基板的实施，重复之处在此不再赘述。
在具体实施时，本公开实施例提供的上述显示装置可以为有机发光显示装置。
在具体实施时，本公开实施例提供的上述显示装置可以为全面屏显示装置，或者也可以为柔性显示装置等，在此不作限定。
在具体实施时，本公开实施例提供的上述显示装置可以为如图3所示的全面屏的手机。当然，本公开实施例提供的上述显示装置也可以为平板电脑、 电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。对于该显示装置的其它必不可少的组成部分均为本领域的普通技术人员应该理解具有的，在此不做赘述，也不应作为对本公开的限制。
本公开实施例提供的上述显示基板、显示面板及显示装置，通过在顶栅型低温多晶硅薄膜晶体管的第一有源层和第一栅极之间设置第一栅绝缘层和第二栅绝缘层两层栅绝缘层，且将覆盖顶栅型氧化物薄膜晶体管的第二栅极设置在第一栅绝缘层和第二栅绝缘层之间，这样在不增加显示模组整体厚度的基础上，可以增大顶栅型低温多晶硅薄膜晶体管的栅绝缘层的厚度，从而可以降低顶栅型低温多晶硅薄膜晶体管的漏电流，增加其特性均一性，提高显示画面品质；另外，增大顶栅型低温多晶硅薄膜晶体管的栅绝缘层的厚度，可以降低顶栅型低温多晶硅薄膜晶体管的极间电容，从而可以降低栅极负载，减小栅线上的RC delay，进而提高栅线的充电时长。
尽管已描述了本公开的优选实施例，但本领域内的技术人员一旦得知了基本创造性概念，则可对这些实施例作出另外的变更和修改。所以，所附权利要求意欲解释为包括优选实施例以及落入本公开范围的所有变更和修改。
显然，本领域的技术人员可以对本公开实施例进行各种改动和变型而不脱离本公开实施例的精神和范围。这样，倘若本公开实施例的这些修改和变型属于本公开权利要求及其等同技术的范围之内，则本公开也意图包含这些改动和变型在内。

Claims (10)

  1. 一种显示基板，其中，包括：
    衬底基板；
    顶栅型氧化物薄膜晶体管，位于所述衬底基板上；
    顶栅型低温多晶硅薄膜晶体管，位于所述衬底基板上，所述顶栅型低温多晶硅薄膜晶体管包括位于所述衬底基板上层叠设置的第一有源层和第一栅极；
    第一栅绝缘层，位于所述第一有源层和所述第一栅极之间；
    第二栅绝缘层，位于所述第一栅绝缘层和所述第一栅极之间；
    第二栅极，位于所述第一栅绝缘层和所述第二栅绝缘层之间，所述第二栅极在所述衬底基板上的正投影与所述顶栅型低温多晶硅薄膜晶体管在所述衬底基板上的正投影不交叠，且所述第二栅极在所述衬底基板上的正投影覆盖所述顶栅型氧化物薄膜晶体管在所述衬底基板上的正投影。
  2. 如权利要求1所述的显示基板，其中，所述第一栅绝缘层的材料为氧化硅，所述第二栅绝缘层的材料为氧化硅或氮化硅。
  3. 如权利要求1所述的显示基板，其中，所述顶栅型氧化物薄膜晶体管包括：位于所述衬底基板上层叠设置的第二有源层和第三栅极，以及位于所述第三栅极背离所述衬底基板一侧的第一源极和第一漏极，所述第一源极和所述第一漏极分别与所述第二有源层电连接；所述第二栅极在所述衬底基板上的正投影覆盖所述第二有源层在所述衬底基板上的正投影；
    所述顶栅型低温多晶硅薄膜晶体管还包括位于所述第一栅极背离所述衬底基板一侧的第二源极和第二漏极，所述第二源极和所述第二漏极分别与所述第一有源层电连接；
    所述第一源极和所述第一漏极与所述第二源极和所述第二漏极位于同一层。
  4. 如权利要求1所述的显示基板，其中，还包括：位于所述第一栅极和 所述第二有源层之间的第一缓冲层，以及位于所述第一缓冲层和所述第二有源层之间的第二缓冲层；所述第一缓冲层的材料为氮化硅，所述第二缓冲层的材料为氧化硅。
  5. 如权利要求1所述的显示基板，其中，还包括位于所述第二有源层和所述第三栅极之间的第三栅绝缘层，所述第三栅绝缘层的材料为氧化硅。
  6. 如权利要求3所述的显示基板，其中，还包括：位于所述第三栅极和所述第一源极之间的层间绝缘层，位于所述第一源极背离所述衬底基板一侧的第一平坦层，位于所述第一平坦层背离所述衬底基板一侧的第二源漏金属层，位于所述第二源漏金属层背离所述衬底基板一侧的第二平坦层，以及位于所述第二平坦层背离所述衬底基板一侧的阳极；
    所述第二源漏金属层通过贯穿所述第一平坦层的过孔与所述第二漏极电连接，所述阳极通过贯穿所述第二平坦层的过孔与所述第二源漏金属层电连接。
  7. 如权利要求6所述的显示基板，其中，还包括：位于所述阳极背离所述衬底基板一侧的像素定义层，以及位于所述像素定义层上的隔垫物层。
  8. 如权利要求1-7任一项所述的显示基板，其中，还包括：位于所述衬底基板和所述第一有源层之间的阻挡层，以及位于所述阻挡层和所述第一有源层之间的第三缓冲层。
  9. 一种显示面板，其中，包括如权利要求1-8任一项所述的显示基板。
  10. 一种显示装置，其中，包括如权利要求9所述的显示面板。
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