WO2022056789A1 - 一种显示面板及显示装置 - Google Patents

一种显示面板及显示装置 Download PDF

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Publication number
WO2022056789A1
WO2022056789A1 PCT/CN2020/115981 CN2020115981W WO2022056789A1 WO 2022056789 A1 WO2022056789 A1 WO 2022056789A1 CN 2020115981 W CN2020115981 W CN 2020115981W WO 2022056789 A1 WO2022056789 A1 WO 2022056789A1
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Prior art keywords
layer
source
drain metal
display panel
thickness
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PCT/CN2020/115981
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English (en)
French (fr)
Inventor
黄耀
王本莲
龙跃
黄炜赟
徐映嵩
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN202080002004.7A priority Critical patent/CN114514612A/zh
Priority to PCT/CN2020/115981 priority patent/WO2022056789A1/zh
Priority to US17/414,383 priority patent/US11844250B2/en
Publication of WO2022056789A1 publication Critical patent/WO2022056789A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/124—Insulating layers formed between TFT elements and OLED elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K2102/00—Constructional details relating to the organic devices covered by this subclass
    • H10K2102/301—Details of OLEDs
    • H10K2102/311—Flexible OLED
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/123—Connection of the pixel electrodes to the thin film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K77/00—Constructional details of devices covered by this subclass and not covered by groups H10K10/80, H10K30/80, H10K50/80 or H10K59/80
    • H10K77/10—Substrates, e.g. flexible substrates
    • H10K77/111—Flexible substrates
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/549—Organic PV cells

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a display panel and a display device.
  • Low temperature polycrystalline oxide (English: Low temperature polycrystalline oxide; Abbreviation: LTPO) substrate is a new type of display panel, which has a low temperature polycrystalline silicon (English: Low Temperature Poly-silicon; Abbreviation: LTPS) substrate and oxide (English: The advantages of Oxide substrates are the main development direction of future display panels.
  • the LTPS substrate refers to the display panel in which the thin film transistor (English: Thin Film Transistor; TFT for short) in the display unit is LTPS TFT
  • the oxide substrate refers to the display panel in which the TFT in the display unit is an oxide TFT
  • LTPO substrate refers to a display panel including LTPS TFT and oxide TFT in each display unit, and the display unit is also called sub-pixel.
  • a base substrate including a display area and a bending area on one side of the display area
  • a low temperature polysilicon semiconductor layer located in the display area of the base substrate
  • an oxide semiconductor layer located in the display area of the base substrate
  • the source-drain metal layer corresponding to the bending region is provided with a plurality of mutually insulated traces extending along the first direction and arranged along the second direction, the source-drain metal layer corresponding to the display region
  • the metal layer is provided with a plurality of mutually insulated signal lines extending along a first direction and arranged along a second direction; the second direction is the extension direction of the bending axis in the bending area, and the first direction is vertical in the horizontal direction of the second direction;
  • the signals on the traces include signals transmitted by the transistor where the low temperature polysilicon semiconductor layer is located and signals transmitted by the transistor where the oxide semiconductor layer is located;
  • an inorganic layer located between the base substrate and the source-drain metal layer, the inorganic layer is provided with a groove in the bending region, and the wiring is provided above the groove;
  • a flexible insulating material is located between the inorganic layer in the bending region and the wiring, and the flexible insulating material fills the groove.
  • the flexible insulating material fills the groove, and the thickness of the flexible insulating material is greater than the height of the groove.
  • the inorganic layer has a first thickness and a second thickness in the groove region, the first thickness is greater than the second thickness, and the first thickness is greater than the second thickness.
  • the traces are disposed above the inorganic layer of a thickness.
  • the wiring includes: a first wiring and a second wiring located at the outermost side, and a first wiring and a second wiring located on the outermost side. a plurality of third wires between wires; a side of the first wire away from the third wire has an inorganic layer of the second thickness, and the second wire is far away from the third wire
  • One side of the device has an inorganic layer of the second thickness, and an inorganic layer of the first thickness is provided between the first wiring and the second wiring.
  • an inorganic layer of the second thickness is provided between any adjacent traces.
  • the wiring includes: a first wiring and a second wiring located at the outermost side;
  • a side of the first trace away from the third trace has an inorganic layer of the second thickness
  • a side of the second trace away from the third trace has an inorganic layer of the second thickness Floor.
  • the second thickness is zero.
  • the source-drain metal layer is a first source-drain metal layer, and further comprises: being located on a side of the first source-drain metal layer away from the base substrate The first flat layer, the second source-drain metal layer on the side of the first flat layer away from the base substrate, the second source-drain metal layer on the side of the second source-drain metal layer away from the base substrate layer, and an anode located on the side of the second flat layer away from the base substrate;
  • the first flat layer and the second flat layer cover the bent region.
  • the source-drain metal layer is a second source-drain metal layer, and further comprises: a source-drain metal layer located between the second source-drain metal layer and the oxide semiconductor layer a first flat layer between the first flat layer and the oxide semiconductor layer, a first source-drain metal layer between the first flat layer and the oxide semiconductor layer, a first source-drain metal layer on the side of the second source-drain metal layer away from the base substrate two flat layers, and an anode located on the side of the second flat layer away from the base substrate;
  • the flexible insulating material is the first flat layer, and the second flat layer covers the bending region.
  • the above-mentioned display panel provided by the embodiment of the present disclosure, it further includes: a barrier layer and a first buffer layer stacked between the base substrate and the low-temperature polysilicon semiconductor layer, located in the low-temperature polysilicon A first gate insulating layer, a first gate electrode layer, a second gate insulating layer, a light shielding layer, a second buffer layer and a third buffer layer stacked between the semiconductor layer and the oxide semiconductor layer, and a second gate layer between the material semiconductor layer and the first source-drain metal layer, a third gate insulating layer between the second gate layer and the oxide semiconductor layer, and a third gate insulating layer between the second gate layer and the oxide semiconductor layer, and a third gate insulating layer between the second gate layer and the oxide semiconductor layer, and a third gate insulating layer between the second gate layer and the oxide semiconductor layer; an interlayer insulating layer between the two gate layers and the first source-drain metal layer;
  • the interlayer insulating layer constitutes the inorganic layer.
  • an embodiment of the present disclosure further provides a display device including the above-mentioned display panel provided by an embodiment of the present disclosure.
  • FIG. 1 is a schematic partial cross-sectional structure diagram of a display panel according to an embodiment of the present disclosure
  • FIG. 2 is a schematic partial cross-sectional structural diagram of still another display panel according to an embodiment of the present disclosure
  • FIG. 3 is a schematic top-view structure diagram of a display panel according to an embodiment of the present disclosure.
  • FIG. 4 is a schematic partial cross-sectional structural diagram of still another display panel according to an embodiment of the present disclosure.
  • FIG. 5 is a schematic partial cross-sectional structural diagram of still another display panel according to an embodiment of the present disclosure.
  • FIG. 6 is a schematic partial cross-sectional structural diagram of still another display panel according to an embodiment of the present disclosure.
  • FIG. 7 is a schematic partial cross-sectional structural diagram of still another display panel according to an embodiment of the present disclosure.
  • FIG. 8 is a schematic partial cross-sectional structural diagram of still another display panel according to an embodiment of the present disclosure.
  • FIG. 9 is a schematic partial cross-sectional structural diagram of still another display panel according to an embodiment of the present disclosure.
  • FIG. 10 is a schematic structural diagram of a display device according to an embodiment of the present disclosure.
  • the display panel is the main component of the display device, which includes a base substrate and a display unit disposed on the base substrate, and the display unit includes a thin film transistor (Thin Film Transistor, TFT).
  • TFT Thin Film Transistor
  • the LTPS substrate refers to a display panel in which the TFT in the display unit is an LTPS TFT
  • the oxide substrate refers to a display panel in which the TFT in the display unit is an oxide TFT.
  • the mobility of the polysilicon active layer is large, which makes the leakage current (Ioff) of the LTPS TFT large, and the power consumption of the LTPS substrate under low-frequency driving is large, so it is difficult to maintain a static black picture well, and the picture quality is poor; and, In order to better develop the gray scale, in the LTPS substrate, the channel of the Driver Thin Film Transistor (DTFT) needs to be made very long, which makes it difficult to achieve the high resolution of the LTPS substrate.
  • Ioff leakage current
  • DTFT Driver Thin Film Transistor
  • the resolution refers to The number of pixels per inch (Pixel Per Inch, PPI); in addition, the hysteresis (Hysteresis) of the polysilicon active layer is relatively large, so the LTPS substrate is prone to the problem of image afterimage.
  • the mobility of the oxide active layer is small, so that the leakage current of the oxide TFT is small, and the power consumption of the oxide substrate under low-frequency driving is small, which can well maintain a static black picture and improve the picture quality;
  • the oxide substrate there is no need to make the channel of the DTFT very long, so that the gray scale can be better developed and high PPI can be achieved;
  • the hysteresis of the oxide active layer is small, and the oxide substrate is not prone to image afterimage problems. ; Further, the uniformity of oxide TFT is better than that of LTPSTFT.
  • the oxide process can well make up for some deficiencies of the LTPS process.
  • the LTPS process and the oxide process have their own advantages and disadvantages. Therefore, the combination of the LTPS process and the oxide process is a very competitive process solution.
  • the combination of the LTPS process and the oxide process is the LTPO process, and the future of the LTPO process It is likely to be used in the development of high-end products.
  • the display panel based on the LTPO process is an LTPO substrate.
  • each display unit includes an LTPS TFT and an oxide TFT.
  • FIG. 1 to FIG. 3 are Schematic diagram of the cross-sectional structure of the film layer in the display panel
  • FIG. 3 is a schematic top view of the display panel
  • the display panel includes:
  • the base substrate 1 includes a display area AA and a bending area BA on one side of the display area AA:
  • the low temperature polysilicon semiconductor layer 2 is located in the display area AA of the base substrate 1;
  • the oxide semiconductor layer 3 is located in the display area AA of the base substrate 1.
  • the oxide semiconductor layer 3 is located on the side of the low temperature polysilicon semiconductor layer 2 away from the base substrate 1 as an example for schematic illustration;
  • the orthographic projection of the material semiconductor layer 3 on the base substrate 1 does not overlap with the orthographic projection of the low temperature polysilicon semiconductor layer 2 on the base substrate 1;
  • the source-drain metal layer 4, the source-drain metal layer 4 corresponding to the bending area BA is provided with a plurality of mutually insulated traces 41 extending along the first direction X and arranged along the second direction Y, and the source-drain metal layer 4 corresponding to the display area AA
  • the layer 4 is provided with a plurality of mutually insulated signal lines 42 extending along the first direction X and arranged along the second direction Y;
  • the second direction Y is the extension direction of the bending axis L in the bending area BA, and the first direction X is The horizontal direction perpendicular to the second direction Y;
  • the signal on the trace 41 includes the signal transmitted by the transistor where the low-temperature polysilicon semiconductor layer 2 is located and the signal transmitted by the transistor where the oxide semiconductor layer 3 is located;
  • the inorganic layer 6 is located between the base substrate 1 and the source-drain metal layer 4, and the inorganic layer 6 is provided with a groove 61 in the bending area BA, and a wiring 41 is provided above the groove 61;
  • the flexible insulating material 7 is located between the inorganic layer 6 in the bending area BA and the wiring 41 , and the flexible insulating material 7 fills the groove 61 .
  • the inorganic layer 6 of the bending area BA in the LTPO display panel is dug a groove 61, and a flexible insulating material 7 is used to fill the groove 61, so that the bending performance of the bending area BA can be improved. , to prevent the cracking of the inorganic film layer and the fracture of the metal traces when the LTPO-based display panel is bent.
  • the flexible insulating material 7 fills the groove 61 , and the thickness of the flexible insulating material 7 is greater than the height of the groove 61 , In this way, the bending performance of the LTPO-based display panel in the bending area BA can be further improved.
  • the inorganic layer 6 has a first thickness D1 and a second thickness D2 in the area of the groove 61 , and the first thickness D1 is greater than A wiring 41 is disposed above the inorganic layer 6 with the second thickness D2 and the first thickness D1.
  • the wiring is 41 includes: the outermost first trace 411 and the second trace 412, and a plurality of third traces 413 between the first trace 411 and the second trace 412 (only one third trace is shown).
  • the side of the first trace 411 away from the third trace 413 has an inorganic layer 6 with a second thickness D2
  • the side of the second trace 412 away from the third trace 413 has an inorganic layer 6 with a second thickness D2
  • the inorganic layer 6 with the second thickness D2 between adjacent traces specifically, the traces 41 include: the first traces 411 and the second traces 412 located at the outermost side, and the first traces 411 and the second traces Multiple third lines 413 between lines 412 (only one third line 43 is shown), between the first line 411 and the third line 413, the second line 412 and the adjacent third line 413 Between and between the third traces 413, there is an inorganic layer 6 with a second thickness D2, and the thickness of the inorganic layer 6 under the first traces 411, the second traces 412 and the third traces 413 is D1, that is The present disclosure can further improve the bending performance of the bending region BA by reducing the thickness of the inorganic layer 6 between the wires.
  • the wiring is 41 includes: the outermost first trace 411 and the second trace 412, and a plurality of third traces 413 between the first trace 411 and the second trace 412 (only one third trace is shown). 43);
  • the side of the first trace 411 away from the third trace 413 has an inorganic layer 6 with a second thickness D2
  • the side of the second trace 412 away from the third trace 413 has an inorganic layer with a second thickness D2 that is, the present disclosure
  • the second The thickness D2 is 0, that is, in the present disclosure, by hollowing out the inorganic layer 6 between each trace or outside the outermost trace, the thickness of the inorganic layer 6 under each trace 41 is D1, which can reduce the bending area as much as possible.
  • the thickness of the inorganic layer of BA greatly improves the bending performance of BA in the bending region.
  • the source-drain metal layer 4 is the first source-drain metal layer SD1 , that is, the path of the bending region BA.
  • the line 41 is located in the first source-drain metal layer SD1, and the display panel further includes: a first flat layer 8 located on the side of the first source-drain metal layer SD1 away from the base substrate 1, and located on the first flat layer 8 away from the base substrate 1
  • the second source-drain metal layer SD2 on one side, the second flat layer 9 on the side of the second source-drain metal layer SD2 away from the base substrate 1 , and the anode 10 on the side of the second flat layer 9 away from the base substrate 1 ;
  • the second source-drain metal layer SD2 is electrically connected to the first source-drain metal layer SD1 through the vias penetrating the first flat layer 8, and the anode 10 is electrically connected to the second source-drain metal layer SD2 through the vias penetrating the second flat layer 9 connect;
  • the first flat layer 8 and the second flat layer 9 can cover the bending area BA.
  • the source-drain metal layer 4 is the second source-drain metal layer SD2 , that is, the path of the bending region BA.
  • the line 41 is located in the second source-drain metal layer SD2, and the display panel further includes: a first planarization layer 8 located between the second source-drain metal layer SD2 and the oxide semiconductor layer 3, and located between the first planarization layer 8 and the oxide semiconductor layer 8
  • Anode 10 the second source-drain metal layer SD2 is electrically connected to the first source-drain metal layer SD1 through a via hole penetrating the first flat layer 8
  • the anode 10 is electrically connected to the second source-drain metal layer through a via hole penetrating the second flat layer 9 SD2 electrical connection;
  • the flexible insulating material 7 is the first flat layer 8, that is, when the material of the first flat layer 8 is applied, the material of the first flat layer 8 fills the groove 61,
  • the second flat layer 9 can cover the bending area BA without the need to separately fill the flexible insulating material of the groove 61 to reduce the process and cost.
  • the above-mentioned display panel provided by the embodiment of the present disclosure, as shown in FIG. 1 , FIG. 2 , FIG. 4 to FIG. 9 , it further includes: a stacking arrangement between the base substrate 1 and the low temperature polysilicon semiconductor layer 2
  • the barrier layer 11 and the first buffer layer 12, the first gate insulating layer 13, the first gate layer 14, the second gate insulating layer 15, the light shielding layer 13 are stacked between the low temperature polysilicon semiconductor layer 2 and the oxide semiconductor layer 3.
  • the barrier layer 11 , the first buffer layer 12 , the first gate insulating layer 13 , the second gate insulating layer 15 , the second buffer layer 17 , the third buffer layer 18 , the third gate insulating layer 20 and the interlayer insulating layer 21 constitute inorganic Layer 6.
  • the inorganic layer 6 of the display area AA is composed of a barrier layer 11 , a first buffer layer 12 , a first gate insulating layer 13 , a second gate insulating layer 15 , a second buffer layer 17 , a third buffer layer 18 and interlayer insulation
  • the inorganic layer 6 in the bending area BA is processed by an etching process, and only part of the inorganic layer 6 is retained to improve the bending performance of the bending area BA.
  • the thickness of the inorganic layer 6 in the bending area BA depends on the actual situation. to make a selection.
  • the orthographic projection of the light shielding layer 16 on the base substrate 1 covers the orthographic projection of the oxide semiconductor layer 3 on the base substrate 1 ;
  • the oxide semiconductor layer 3 of the thin film transistor is an oxide material, and its performance will be damaged by the influence of external ambient light. Therefore, the light shielding layer 16 provided in the embodiment of the present disclosure can protect the oxide semiconductor layer 3 of the thin film transistor from being damaged. Affected by external ambient light, the performance of the oxide thin film transistor is improved.
  • the material of the above gate insulating layer may be one or a combination of silicon oxide or silicon nitride.
  • the material of the second buffer layer 17 may be silicon nitride, and the material of the third buffer layer 18 may be silicon oxide.
  • the second buffer layer 17 and the third buffer layer 18 can play a role of flattening and improving the adhesion between the subsequent film layers and the base substrate 1 .
  • the barrier layer 11 is used to block external water vapor
  • the first buffer layer 12 is used to improve the adhesion between the film layer to be produced subsequently and the base substrate 1 .
  • the material of the barrier layer 11 may be one or a combination of silicon oxide and silicon nitride, and the material of the first buffer layer 12 may be silicon oxide.
  • the first source-drain metal layer SD1 includes a first source electrode 01 , a first source electrode 01 , a first source electrode 01 located on the side of the oxide semiconductor layer 3 away from the base substrate 1 , and a first source-drain metal layer SD1 .
  • the drain electrode 02, the second source electrode 03 and the second drain electrode 04, the first source electrode 01 and the first drain electrode 02 are respectively electrically connected to the low temperature polysilicon semiconductor layer 2, and the second source electrode 03 and the second drain electrode 04 are respectively connected to the low temperature polysilicon semiconductor layer 2.
  • the oxide semiconductor layer 3 is electrically connected; specifically, the part of the low temperature polysilicon semiconductor layer 2 that is electrically connected to the first source electrode 01 and the first drain electrode 02 is a conductive region, and ion doping can be used to form a conductive region;
  • the first source electrode 01, the first drain electrode 02, the second source electrode 03, and the second drain electrode 04 are located in the same first source-drain metal layer SD1, so that only the first source electrode 01 and the first drain electrode 02 need to be formed when the first source electrode 01 and the first drain electrode 02 are formed.
  • the pattern of the second source electrode 03 and the second drain electrode 04 and the first source electrode 01 and the first drain electrode 02 can be formed by one patterning process, without adding a separate preparation of the second source electrode 03 And the process of the second drain electrode 04 can simplify the manufacturing process flow, save the production cost, and improve the production efficiency.
  • the low temperature polysilicon semiconductor layer 2, the first gate layer 14, the first source electrode 01 and the first drain electrode 02 constitute a low temperature polysilicon thin film transistor
  • the oxide semiconductor layer 3, the second gate layer 19, the second source electrode 03 and the second drain 04 constitute an oxide thin film transistor
  • the orthographic projections of the low temperature polysilicon thin film transistor and the oxide thin film transistor on the base substrate 1 do not overlap.
  • both the low temperature polysilicon thin film transistor and the oxide thin film transistor are top-gate thin film transistors.
  • the display panel further includes: a pixel definition layer 22 located on the side of the anode 10 away from the base substrate 1 . , and the spacer layer 23 on the pixel definition layer 22 .
  • the pixel definition layer 22 has a plurality of pixel openings, and each pixel opening exposes a part of the anode 10 , and the light-emitting layer and the cathode on the side of the anode 10 away from the base substrate 1 are subsequently fabricated, as well as other functionalities such as subsequent encapsulation layers.
  • the film layer is not described in detail here.
  • the spacer layer 23 plays a supporting role when the display panel and the glass cover plate are subsequently assembled into a cell.
  • the anode voltage is input to the anode through the thin film transistor
  • the cathode voltage is input to the cathode, that is, under the driving of the external voltage, the electrons injected by the cathode and the holes injected by the anode recombine in the light-emitting layer to form electron holes at the bound energy level
  • exciton radiation de-excites photons, producing visible light.
  • the display device provided by the embodiments of the present disclosure may also include other functional film layers known to those skilled in the art, which will not be described in detail here.
  • the display panel provided by the embodiment of the present disclosure is an organic light-emitting display panel.
  • an embodiment of the present disclosure further provides a display device, including the above-mentioned display panel provided by an embodiment of the present disclosure.
  • the problem-solving principle of the display device is similar to that of the aforementioned display panel. Therefore, the implementation of the display device can refer to the aforementioned implementation of the display panel, and repeated details will not be repeated here.
  • the above-mentioned display device provided by the embodiment of the present disclosure may be an organic light-emitting display device.
  • the above-mentioned display device provided by the embodiments of the present disclosure may be a full-screen display device, or may also be a flexible display device, etc., which is not limited herein.
  • the above-mentioned display device provided by the embodiment of the present disclosure may be a mobile phone with a full screen as shown in FIG. 10 .
  • the above-mentioned display device provided by the embodiment of the present disclosure may also be any product or component with a display function, such as a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, and a navigator.
  • a display function such as a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, and a navigator.
  • Other essential components of the display device should be understood by those of ordinary skill in the art, and will not be repeated here, nor should it be regarded as a limitation of the present disclosure.
  • the above-mentioned display panels and display devices provided by the embodiments of the present disclosure, and the above-mentioned display panels provided by the embodiments of the present disclosure by digging grooves in the inorganic layer in the bending region of the LTPO display panel, and filling the grooves with flexible insulating materials, which can improve the The bending performance of the bending area can prevent the cracking of the inorganic film layer and the fracture of the metal traces caused by the bending of the LTPO-based display panel.

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Abstract

提供了一种显示面板及显示装置，该显示面板包括：衬底基板(1)，低温多晶硅半导体层(2)，氧化物半导体层(3)，源漏金属层(4)，弯折区域(BA)对应的源漏金属层(4)设置有多条沿第一方向(X)延伸且沿第二方向(Y)排列的相互绝缘的走线(41)，显示区域(AA)对应的源漏金属层(4)设置有多条沿第一方向(X)延伸且沿第二方向(Y)排列的相互绝缘的信号线(42)；走线(41)上的信号包括由低温多晶硅半导体层(2)所在晶体管传输的信号以及由氧化物半导体层(3)所在晶体管传输的信号；无机层(6)，位于衬底基板(1)和源漏金属层(4)之间，无机层(6)在弯折区域(BA)设置有凹槽(61)，凹槽(61)上方设置有走线(41)；柔性绝缘材料(7)，位于弯折区域(BA)的无机层(6)和走线(41)之间，柔性绝缘材料(7)填充凹槽(61)。

Description

一种显示面板及显示装置 技术领域
本公开涉及显示技术领域，特别涉及一种显示面板及显示装置。
背景技术
低温多晶氧化物(英文：Low temperature polycrystalline oxide；简称：LTPO)基板是一种新型的显示面板，其具有低温多晶硅(英文：Low Temperature Poly-silicon；简称：LTPS)基板和氧化物(英文：Oxide)基板的优点，是未来显示面板的主要发展方向。其中，LTPS基板指的是显示单元中的薄膜晶体管(英文：Thin Film Transistor；简称：TFT)为LTPS TFT的显示面板，氧化物基板指的是显示单元中的TFT为氧化物TFT的显示面板，LTPO基板指的每个显示单元中包括LTPS TFT和氧化物TFT的显示面板，显示单元也称为子像素。
发明内容
本公开实施例提供的一种显示面板，包括：
衬底基板，包括显示区域和位于所述显示区域一侧的弯折区域；
低温多晶硅半导体层，位于所述衬底基板的显示区域；
氧化物半导体层，位于所述衬底基板的显示区域；
源漏金属层，所述弯折区域对应的所述源漏金属层设置有多条沿第一方向延伸且沿第二方向排列的相互绝缘的走线，所述显示区域对应的所述源漏金属层设置有多条沿第一方向延伸且沿第二方向排列的相互绝缘的信号线；所述第二方向为所述弯折区域内弯折轴的延伸方向，所述第一方向为垂直于所述第二方向的水平方向；所述走线上的信号包括由所述低温多晶硅半导体层所在晶体管传输的信号以及由所述氧化物半导体层所在晶体管传输的信号；
无机层，位于所述衬底基板和所述源漏金属层之间，所述无机层在所述弯折区域设置有凹槽，所述凹槽上方设置有所述走线；
柔性绝缘材料，位于所述弯折区域的无机层和所述走线之间，所述柔性绝缘材料填充所述凹槽。
可选地，在本公开实施例提供的上述显示面板中，所述柔性绝缘材料填平所述凹槽，且所述柔性绝缘材料的厚度大于所述凹槽的高度。
可选地，在本公开实施例提供的上述显示面板中，所述无机层在所述凹槽区域具有第一厚度和第二厚度，所述第一厚度大于所述第二厚度，所述第一厚度的无机层上方设置有所述走线。
可选地，在本公开实施例提供的上述显示面板中，所述走线包括：位于最外侧的第一走线和第二走线，以及位于所述第一走线和所述第二走线之间的多条第三走线；所述第一走线远离所述第三走线的一侧具有所述第二厚度的无机层，所述第二走线远离所述第三走线的一侧具有所述第二厚度的无机层，所述第一走线和所述第二走线之间具有所述第一厚度的无机层。
可选地，在本公开实施例提供的上述显示面板中，任意相邻所述走线之间具有所述第二厚度的无机层。
可选地，在本公开实施例提供的上述显示面板中，所述走线包括：位于最外侧的第一走线和第二走线；
所述第一走线远离所述第三走线的一侧具有所述第二厚度的无机层，所述第二走线远离所述第三走线的一侧具有所述第二厚度的无机层。
可选地，在本公开实施例提供的上述显示面板中，所述第二厚度为0。
可选地，在本公开实施例提供的上述显示面板中，所述源漏金属层为第一源漏金属层，还包括：位于所述第一源漏金属层背离所述衬底基板一侧的第一平坦层，位于所述第一平坦层背离所述衬底基板一侧的第二源漏金属层，位于所述第二源漏金属层背离所述衬底基板一侧的第二平坦层，以及位于所述第二平坦层背离所述衬底基板一侧的阳极；
所述第一平坦层和所述第二平坦层覆盖所述弯折区域。
可选地，在本公开实施例提供的上述显示面板中，所述源漏金属层为第二源漏金属层，还包括：位于所述第二源漏金属层和所述氧化物半导体层之 间的第一平坦层，位于所述第一平坦层和所述氧化物半导体层之间的第一源漏金属层，位于所述第二源漏金属层背离所述衬底基板一侧的第二平坦层，以及位于所述第二平坦层背离所述衬底基板一侧的阳极；
所述柔性绝缘材料为所述第一平坦层，所述第二平坦层覆盖所述弯折区域。
可选地，在本公开实施例提供的上述显示面板中，还包括：位于所述衬底基板与所述低温多晶硅半导体层之间层叠设置的阻挡层和第一缓冲层，位于所述低温多晶硅半导体层和所述氧化物半导体层之间层叠设置的第一栅绝缘层、第一栅极层、第二栅绝缘层、遮光层、第二缓冲层和第三缓冲层，以及位于所述氧化物半导体层和所述第一源漏金属层之间的第二栅极层，位于所述第二栅极层和所述氧化物半导体层之间的第三栅绝缘层，以及位于所述第二栅极层和所述第一源漏金属层之间的层间绝缘层；
所述阻挡层、所述第一缓冲层、所述第一栅绝缘层、所述第二栅绝缘层、所述第二缓冲层、所述第三缓冲层，所述第三栅绝缘层和所述层间绝缘层构成所述无机层。
相应地，本公开实施例还提供了一种显示装置，包括本公开实施例提供的上述显示面板。
附图说明
图1为本公开实施例提供的一种显示面板的局部截面结构示意图；
图2为本公开实施例提供的又一种显示面板的局部截面结构示意图；
图3为本公开实施例提供的一种显示面板的俯视结构示意图；
图4为本公开实施例提供的又一种显示面板的局部截面结构示意图；
图5为本公开实施例提供的又一种显示面板的局部截面结构示意图；
图6为本公开实施例提供的又一种显示面板的局部截面结构示意图；
图7为本公开实施例提供的又一种显示面板的局部截面结构示意图；
图8为本公开实施例提供的又一种显示面板的局部截面结构示意图；
图9为本公开实施例提供的又一种显示面板的局部截面结构示意图；
图10为本公开实施例提供的一种显示装置的结构示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。并且在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互组合。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“内”、“外”、“上”、“下”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
需要注意的是，附图中各图形的尺寸和形状不反映真实比例，目的只是示意说明本公开内容。并且自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。
显示面板是显示装置的主要部件，其包括衬底基板以及设置在衬底基板上的显示单元，显示单元包括薄膜晶体管(Thin Film Transistor，TFT)。LTPS基板指的是显示单元中的TFT为LTPS TFT的显示面板，氧化物基板指的是显示单元中的TFT为氧化物TFT的显示面板。多晶硅有源层的迁移率较大，使得LTPS TFT的漏电流(Ioff)较大，LTPS基板在低频驱动下的功耗较大，难以很好的保持静态黑画面，画面品质较差；并且，为了更好的展开灰阶， 在LTPS基板中，需要将驱动薄膜晶体管(Driver Thin Film Transistor，DTFT)的沟道制作的很长，这样就难以实现LTPS基板的高分辨率，分辨率指的是每英寸所设置的像素数目(Pixel Per Inch，PPI)；此外，多晶硅有源层的迟滞(Hysteresis)较大，因此LTPS基板容易出现画面残像的问题。氧化物有源层的迁移率较小，使得氧化物TFT的漏电流较小，氧化物基板在低频驱动下的功耗较小，能够很好的保持静态黑画面，提升画面品质；并且，在氧化物基板中，无需将DTFT的沟道制作的很长，就能更好的展开灰阶，实现高PPI；此外，氧化物有源层的迟滞较小，氧化物基板不容易出现画面残像问题；进一步地，氧化物TFT的均一性比LTPSTFT的均一性好。
根据以上描述可知，氧化物工艺能够很好的弥补LTPS工艺的一些不足。但是，LTPS工艺和氧化物工艺各有利弊，因此，将LTPS工艺和氧化物工艺结合是一种非常有竞争力的工艺方案，将LTPS工艺和氧化物工艺结合的工艺为LTPO工艺，LTPO工艺未来很有可能应用在高端产品的开发中。
基于LTPO工艺的显示面板为LTPO基板，在LTPO基板中，每个显示单元包括LTPS TFT和氧化物TFT。
随着科技的不断发展，显示技术也一直在持续更新。显示器的未来需求也逐渐朝着更加便捷、时尚，适用环境更为广泛。采用柔性基板制成的柔性器件有望成为下一代电子器件的主流设备。柔性显示面板为了实现更小的边界和高屏占比，常会使用在绑定区域进行弯折(pad bending)。但在进行弯折时，在柔性基板上存在大量的无机层和金属线，弯折半径的减少会出现应力的大量集中，导致显示面板的无机膜层开裂以及金属走线断裂的情况，导致显示面板中的电信号无法顺利传导。
为了解决基于LTPO的显示面板在弯折时导致无机膜层开裂以及金属走线断裂的问题，本公开实施例提供了一种显示面板，如图1至图3所示，图1和图2为显示面板中膜层的截面结构示意图，图3为显示面板的俯视示意图，该显示面板包括：
衬底基板1，包括显示区域AA和位于显示区域AA一侧的弯折区域BA：
低温多晶硅半导体层2，位于衬底基板1的显示区域AA；
氧化物半导体层3，位于衬底基板1的显示区域AA，本公开实施例以氧化物半导体层3位于低温多晶硅半导体层2背离衬底基板1的一侧为例进行示意说明；具体地，氧化物半导体层3在衬底基板1上的正投影与低温多晶硅半导体层2在衬底基板1上的正投影不交叠；
源漏金属层4，弯折区域BA对应的源漏金属层4设置有多条沿第一方向X延伸且沿第二方向Y排列的相互绝缘的走线41，显示区域AA对应的源漏金属层4设置有多条沿第一方向X延伸且沿第二方向Y排列的相互绝缘的信号线42；第二方向Y为弯折区域BA内弯折轴L的延伸方向，第一方向X为垂直于第二方向Y的水平方向；走线41上的信号包括由低温多晶硅半导体层2所在晶体管传输的信号以及由氧化物半导体层3所在晶体管传输的信号；
无机层6，位于衬底基板1和源漏金属层4之间，无机层6在弯折区域BA设置有凹槽61，凹槽61上方设置有走线41；
柔性绝缘材料7，位于弯折区域BA的无机层6和走线41之间，柔性绝缘材料7填充凹槽61。
本公开实施例提供的上述显示面板，通过将LTPO显示面板中弯折区域BA的无机层6挖凹槽61，采用柔性绝缘材料7填充凹槽61，这样可以提高弯折区域BA的弯折性能，防止基于LTPO的显示面板在弯折时导致无机膜层开裂以及金属走线断裂的问题。
在具体实施时，在本公开实施例提供的上述显示面板中，如图1和图2所示，柔性绝缘材料7填平凹槽61，且柔性绝缘材料7的厚度大于凹槽61的高度，这样可以进一步提高基于LTPO的显示面板在弯折区域BA的弯折性能。
在具体实施时，在本公开实施例提供的上述显示面板中，如图4至图9所示，无机层6在凹槽61区域具有第一厚度D1和第二厚度D2，第一厚度D1大于第二厚度D2，第一厚度D1的无机层6上方设置有走线41。
在具体实施时，为了进一步提高弯折区域的弯折性能，防止无机膜层开裂以及金属走线断裂，在本公开实施例提供的上述显示面板中，如图4和图7 所示，走线41包括：位于最外侧的第一走线411和第二走线412，以及位于第一走线411和第二走线412之间的多条第三走线413(仅示意一条第三走线43)；第一走线411远离第三走线413的一侧具有第二厚度D2的无机层6，第二走线412远离第三走线413的一侧具有第二厚度D2的无机层6，第一走线411和第二走线412之间具有第一厚度D1的无机层6。通过将凹槽61区域最外侧第一走线411和第二走线412外侧的无机层6的厚度减薄，可以进一步提高弯折区域BA的弯折性能。
在具体实施时，为了进一步提高弯折区域的弯折性能，防止无机膜层开裂以及金属走线断裂，在本公开实施例提供的上述显示面板中，如图5和图8所示，任意相邻走线之间具有第二厚度D2的无机层6，具体地，走线41包括：位于最外侧的第一走线411和第二走线412，以及位于第一走线411和第二走线412之间的多条第三走线413(仅示意一条第三走线43)，第一走线411和第三走线413之间、第二走线412和相邻第三走线413之间以及第三走线413之间，均具有第二厚度D2的无机层6，第一走线411、第二走线412和第三走线413下方的无机层6的厚度为D1，即本公开通过将各走线之间的无机层6的厚度减薄，可以进一步提高弯折区域BA的弯折性能。
在具体实施时，为了进一步提高弯折区域的弯折性能，防止无机膜层开裂以及金属走线断裂，在本公开实施例提供的上述显示面板中，如图6和图9所示，走线41包括：位于最外侧的第一走线411和第二走线412，以及位于第一走线411和第二走线412之间的多条第三走线413(仅示意一条第三走线43)；
第一走线411远离第三走线413的一侧具有第二厚度D2的无机层6，第二走线412远离第三走线413的一侧具有第二厚度D2的无机层，即本公开通过将第一走线411和第三走线413之间、第二走线412和第三走线413之间、相邻第三走线413之间以及最外侧走线之外的无机层6的厚度均减薄，第一走线411、第二走线412和第三走线413下方的无机层6的厚度为D1，可以进一步提高弯折区域BA的弯折性能。
在具体实施时，为了进一步提高弯折区域的弯折性能，防止无机膜层开 裂以及金属走线断裂，在本公开实施例提供的上述显示面板中，如图4至图9所示，第二厚度D2为0，即本公开通过将各走线之间或最外侧走线之外的无机层6挖空，各走线41下方的无机层6的厚度为D1，可以尽可能的减少弯折区域BA的无机层厚度，大大的提高了弯折区域BA的弯折性能。
在具体实施时，在本公开实施例提供的上述显示面板中，如图1、图4至图6所示，源漏金属层4为第一源漏金属层SD1，即弯折区域BA的走线41位于第一源漏金属层SD1，该显示面板还包括：位于第一源漏金属层SD1背离衬底基板1一侧的第一平坦层8，位于第一平坦层8背离衬底基板1一侧的第二源漏金属层SD2，位于第二源漏金属层SD2背离衬底基板1一侧的第二平坦层9，以及位于第二平坦层9背离衬底基板1一侧的阳极10；第二源漏金属层SD2通过贯穿第一平坦层8的过孔与第一源漏金属层SD1电连接，阳极10通过贯穿第二平坦层9的过孔与第二源漏金属层SD2电连接；
由于平坦层的材料一般为柔性的有机绝缘材料，因此第一平坦层8和第二平坦层9可以覆盖弯折区域BA。
在具体实施时，在本公开实施例提供的上述显示面板中，如图2、图7至图9所示，源漏金属层4为第二源漏金属层SD2，即弯折区域BA的走线41位于第二源漏金属层SD2，该显示面板还包括：位于第二源漏金属层SD2和氧化物半导体层3之间的第一平坦层8，位于第一平坦层8和氧化物半导体层3之间的第一源漏金属层SD1，位于第二源漏金属层SD2背离衬底基板1一侧的第二平坦层9，以及位于第二平坦层9背离衬底基板1一侧的阳极10；第二源漏金属层SD2通过贯穿第一平坦层8的过孔与第一源漏金属层SD1电连接，阳极10通过贯穿第二平坦层9的过孔与第二源漏金属层SD2电连接；
由于平坦层的材料一般为柔性的有机绝缘材料，因此柔性绝缘材料7为第一平坦层8，即在涂覆第一平坦层8的材料时，第一平坦层8的材料填充凹槽61，不用单独填充凹槽61的柔性绝缘材料，降低工艺及成本，第二平坦层9可以覆盖弯折区域BA。
在具体实施时，在本公开实施例提供的上述显示面板中，如图1、图2、 图4至图9所示，还包括：位于衬底基板1与低温多晶硅半导体层2之间层叠设置的阻挡层11和第一缓冲层12，位于低温多晶硅半导体层2和氧化物半导体层3之间层叠设置的第一栅绝缘层13、第一栅极层14、第二栅绝缘层15、遮光层16、第二缓冲层17和第三缓冲层18，位于氧化物半导体层3和第一源漏金属层SD1之间的第二栅极层19，位于第二栅极层19和氧化物半导体层3之间的第三栅绝缘层20，以及位于第二栅极层19和第一源漏金属层SD1之间的层间绝缘层21；
阻挡层11、第一缓冲层12、第一栅绝缘层13、第二栅绝缘层15、第二缓冲层17、第三缓冲层18，第三栅绝缘层20和层间绝缘层21构成无机层6。具体地，显示区域AA的无机层6由阻挡层11、第一缓冲层12、第一栅绝缘层13、第二栅绝缘层15、第二缓冲层17、第三缓冲层18和层间绝缘层19构成，而弯折区域BA的无机层6通过刻蚀工艺处理，仅保留部分无机层6，以提高弯折区域BA的弯折性能，弯折区域BA的无机层6的厚度根据实际情况进行选择。
在具体实施时，如图1、图2、图4至图9所示，遮光层16在衬底基板1上的正投影覆盖氧化物半导体层3在衬底基板1上的正投影；由于氧化物薄膜晶体管的氧化物半导体层3为氧化物材料，受到外界环境光的影响会破坏其性能，因此本公开实施例提供的遮光层16可以起到保护氧化物薄膜晶体管的氧化物半导体层3不受外界环境光的影响，从而提高氧化物薄膜晶体管的性能。
在具体实施时，上述栅绝缘层的材料可以为氧化硅或氮化硅其中之一或组合。
在具体实施时，第二缓冲层17的材料可以为氮化硅，第三缓冲层18的材料可以为氧化硅。具体地，第二缓冲层17和第三缓冲层18可以起到平坦以及提高后续膜层与衬底基板1之间附着力的作用。
在具体实施时，阻挡层11是为了阻隔外界水汽，第一缓冲层12是为了提高后续制作的膜层与衬底基板1之间的附着力。阻挡层11的材料可以为氧化硅、氮化硅其中之一或组合，第一缓冲层12的材料可以为氧化硅。
在具体实施时，如图1、图2、图4至图9所示，第一源漏金属层SD1包括位 于氧化物半导体层3背离衬底基板1一侧的第一源极01、第一漏极02、第二源极03和第二漏极04，第一源极01和第一漏极02分别与低温多晶硅半导体层2电连接，第二源极03和第二漏极04分别与氧化物半导体层3电连接；具体地，低温多晶硅半导体层2中与第一源极01和第一漏极02电连接的部分均为导体化区域，可以采用离子掺杂形成导体化区；
第一源极01、第一漏极02、第二源极03和第二漏极04位于同一第一源漏金属层SD1，这样，只需要在形成第一源极01和第一漏极02时改变原有的构图图形，即可通过一次构图工艺形成第二源极03和第二漏极04与第一源极01和第一漏极02的图形，不用增加单独制备第二源极03和第二漏极04的工艺，可以简化制备工艺流程，节省生产成本，提高生产效率。
具体地，低温多晶硅半导体层2、第一栅极层14、第一源极01和第一漏极02构成低温多晶硅薄膜晶体管，氧化物半导体层3、第二栅极层19、第二源极03和第二漏极04构成氧化物薄膜晶体管，低温多晶硅薄膜晶体管和氧化物薄膜晶体管在衬底基板1上的正投影不交叠。
具体地，低温多晶硅薄膜晶体管和氧化物薄膜晶体管均为顶栅型薄膜晶体管。
在具体实施时，在本公开实施例提供的上述显示面板中，如图1、图2、图4至图9所示，还包括：位于阳极10背离衬底基板1一侧的像素定义层22，以及位于像素定义层22上的隔垫物层23。具体地，像素定义层22具有多个像素开口，各像素开口裸露出部分阳极10，后续再制作位于阳极10背离衬底基板1一侧的发光层以及阴极，以及后续的封装层等其它功能性膜层，在此不做详述。隔垫物层23在后续显示面板与玻璃盖板对盒时起到支撑的作用。
具体地，通过薄膜晶体管向阳极输入阳极电压，阴极输入阴极电压，即在外界电压的驱动下，由阴极注入的电子和阳极注入的空穴在发光层中复合形成处于束缚能级的电子空穴对即激子，激子辐射退激发出光子，产生可见光。
当然，本公开实施例提供的显示装置还可以包括本领域技术人员熟知的 其他功能性膜层，在此不做详述。
具体地，本公开实施例提供的显示面板为有机发光显示面板。
基于同一发明构思，本公开实施例还提供了一种显示装置，包括本公开实施例提供的上述显示面板。该显示装置解决问题的原理与前述显示面板相似，因此该显示装置的实施可以参见前述显示面板的实施，重复之处在此不再赘述。
在具体实施时，本公开实施例提供的上述显示装置可以为有机发光显示装置。
在具体实施时，本公开实施例提供的上述显示装置可以为全面屏显示装置，或者也可以为柔性显示装置等，在此不作限定。
在具体实施时，本公开实施例提供的上述显示装置可以为如图10所示的全面屏的手机。当然，本公开实施例提供的上述显示装置也可以为平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。对于该显示装置的其它必不可少的组成部分均为本领域的普通技术人员应该理解具有的，在此不做赘述，也不应作为对本公开的限制。
本公开实施例提供的上述显示面板及显示装置，本公开实施例提供的上述显示面板，通过将LTPO显示面板中弯折区域的无机层挖凹槽，采用柔性绝缘材料填充凹槽，这样可以提高弯折区域的弯折性能，防止基于LTPO的显示面板在弯折时导致无机膜层开裂以及金属走线断裂的问题。
尽管已描述了本公开的优选实施例，但本领域内的技术人员一旦得知了基本创造性概念，则可对这些实施例作出另外的变更和修改。所以，所附权利要求意欲解释为包括优选实施例以及落入本公开范围的所有变更和修改。
显然，本领域的技术人员可以对本公开实施例进行各种改动和变型而不脱离本公开实施例的精神和范围。这样，倘若本公开实施例的这些修改和变型属于本公开权利要求及其等同技术的范围之内，则本公开也意图包含这些改动和变型在内。

Claims (11)

  1. 一种显示面板，其中，包括：
    衬底基板，包括显示区域和位于所述显示区域一侧的弯折区域；
    低温多晶硅半导体层，位于所述衬底基板的显示区域；
    氧化物半导体层，位于所述衬底基板的显示区域；
    源漏金属层，所述弯折区域对应的所述源漏金属层设置有多条沿第一方向延伸且沿第二方向排列的相互绝缘的走线，所述显示区域对应的所述源漏金属层设置有多条沿第一方向延伸且沿第二方向排列的相互绝缘的信号线；所述第二方向为所述弯折区域内弯折轴的延伸方向，所述第一方向为垂直于所述第二方向的水平方向；所述走线上的信号包括由所述低温多晶硅半导体层所在晶体管传输的信号以及由所述氧化物半导体层所在晶体管传输的信号；
    无机层，位于所述衬底基板和所述源漏金属层之间，所述无机层在所述弯折区域设置有凹槽，所述凹槽上方设置有所述走线；
    柔性绝缘材料，位于所述弯折区域的无机层和所述走线之间，所述柔性绝缘材料填充所述凹槽。
  2. 如权利要求1所述的显示面板，其中，所述柔性绝缘材料填平所述凹槽，且所述柔性绝缘材料的厚度大于所述凹槽的高度。
  3. 如权利要求1所述的显示面板，其中，所述无机层在所述凹槽区域具有第一厚度和第二厚度，所述第一厚度大于所述第二厚度，所述第一厚度的无机层上方设置有所述走线。
  4. 如权利要求3所述的显示面板，其中，所述走线包括：位于最外侧的第一走线和第二走线，以及位于所述第一走线和所述第二走线之间的多条第三走线；所述第一走线远离所述第三走线的一侧具有所述第二厚度的无机层，所述第二走线远离所述第三走线的一侧具有所述第二厚度的无机层，所述第一走线和所述第二走线之间具有所述第一厚度的无机层。
  5. 如权利要求3所述的显示面板，其中，任意相邻所述走线之间具有所 述第二厚度的无机层。
  6. 如权利要求5所述的显示面板，其中，所述走线包括：位于最外侧的第一走线和第二走线；
    所述第一走线远离所述第三走线的一侧具有所述第二厚度的无机层，所述第二走线远离所述第三走线的一侧具有所述第二厚度的无机层。
  7. 如权利要求3所述的显示面板，其中，所述第二厚度为0。
  8. 如权利要求1所述的显示面板，其中，所述源漏金属层为第一源漏金属层，还包括：位于所述第一源漏金属层背离所述衬底基板一侧的第一平坦层，位于所述第一平坦层背离所述衬底基板一侧的第二源漏金属层，位于所述第二源漏金属层背离所述衬底基板一侧的第二平坦层，以及位于所述第二平坦层背离所述衬底基板一侧的阳极；
    所述第一平坦层和所述第二平坦层覆盖所述弯折区域。
  9. 如权利要求1所述的显示面板，其中，所述源漏金属层为第二源漏金属层，还包括：位于所述第二源漏金属层和所述氧化物半导体层之间的第一平坦层，位于所述第一平坦层和所述氧化物半导体层之间的第一源漏金属层，位于所述第二源漏金属层背离所述衬底基板一侧的第二平坦层，以及位于所述第二平坦层背离所述衬底基板一侧的阳极；
    所述柔性绝缘材料为所述第一平坦层，所述第二平坦层覆盖所述弯折区域。
  10. 如权利要求8或9所述的显示面板，其中，还包括：位于所述衬底基板与所述低温多晶硅半导体层之间层叠设置的阻挡层和第一缓冲层，位于所述低温多晶硅半导体层和所述氧化物半导体层之间层叠设置的第一栅绝缘层、第一栅极层、第二栅绝缘层、遮光层、第二缓冲层和第三缓冲层，以及位于所述氧化物半导体层和所述第一源漏金属层之间的第二栅极层，位于所述第二栅极层和所述氧化物半导体层之间的第三栅绝缘层，以及位于所述第二栅极层和所述第一源漏金属层之间的层间绝缘层；
    所述阻挡层、所述第一缓冲层、所述第一栅绝缘层、所述第二栅绝缘层、 所述第二缓冲层、所述第三缓冲层，所述第三栅绝缘层和所述层间绝缘层构成所述无机层。
  11. 一种显示装置，其中，包括如权利要求1-10任一项所述的显示面板。
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