WO2022179142A1 - 显示面板及其制作方法和显示装置 - Google Patents

显示面板及其制作方法和显示装置 Download PDF

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Publication number
WO2022179142A1
WO2022179142A1 PCT/CN2021/125822 CN2021125822W WO2022179142A1 WO 2022179142 A1 WO2022179142 A1 WO 2022179142A1 CN 2021125822 W CN2021125822 W CN 2021125822W WO 2022179142 A1 WO2022179142 A1 WO 2022179142A1
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Prior art keywords
electrode
layer
transistor
base substrate
display panel
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PCT/CN2021/125822
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English (en)
French (fr)
Inventor
刘宁
袁粲
周斌
闫梁臣
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京东方科技集团股份有限公司
合肥鑫晟光电科技有限公司
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Priority to US18/272,129 priority Critical patent/US20240114721A1/en
Publication of WO2022179142A1 publication Critical patent/WO2022179142A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/126—Shielding, e.g. light-blocking means over the TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/124—Insulating layers formed between TFT elements and OLED elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a display panel, a manufacturing method thereof, and a display device.
  • the size of the pixel gradually decreases, and the area facing the electrodes in the storage capacitor in the pixel circuit decreases, thereby reducing the capacity of the storage capacitor.
  • the capacity of the storage capacitor is small, it is difficult for the storage capacitor to maintain the stability of the gate voltage of the driving transistor, which affects the display effect.
  • Embodiments of the present application provide a display panel, a manufacturing method thereof, and a display device.
  • the display panel of the embodiment of the present application includes a base substrate, a light shielding layer, a buffer layer, an active layer, a gate insulating layer, a gate layer, a first interlayer dielectric layer, and a first conductive layer that are stacked in sequence, wherein,
  • the light shielding layer includes a first electrode
  • the active layer includes a second electrode, the second electrode is connected to the first electrode;
  • the gate layer includes a third electrode, the orthographic projection of the third electrode on the base substrate at least partially overlaps with the orthographic projection of the first electrode on the base substrate to form a first storage capacitor ;
  • the first conductive layer includes a fourth electrode, the fourth electrode is connected to the third electrode, and the orthographic projection of the fourth electrode on the base substrate is the same as that of the second electrode on the substrate.
  • the orthographic projections on the substrate overlap at least partially to form a second storage capacitor.
  • the orthographic projection of the second electrode on the base substrate at least partially overlaps the orthographic projection of the third electrode on the base substrate.
  • the orthographic projection of the second electrode on the base substrate does not overlap with the orthographic projection of the third electrode on the base substrate.
  • the display panel includes a first transistor
  • the active layer includes a source region, a drain region and a channel region of the first transistor
  • the first conductive layer includes the first transistor A source of a transistor
  • the source of the first transistor is respectively connected to the source region of the first transistor and the first electrode
  • the second electrode is connected to the source region of the first transistor.
  • the thickness of the source and drain regions of the first transistor is different from the thickness of the second electrode.
  • the gate layer includes a gate of the first transistor, the gate of the first transistor is disposed opposite to the channel region of the first transistor, and the gate of the first transistor is A pole is connected to the third electrode.
  • the display panel includes a second conductive layer and a second interlayer dielectric layer, and the second interlayer dielectric layer is located on a side of the first interlayer dielectric layer away from the base substrate , the second conductive layer is located on the side of the second interlayer dielectric layer away from the base substrate, the second conductive layer includes a fifth electrode, and the fifth electrode is connected to the second electrode, The orthographic projection of the fifth electrode on the base substrate at least partially overlaps with the orthographic projection of the fourth electrode on the base substrate to form a third storage capacitor.
  • the orthographic projection of the fifth electrode on the base substrate covers the orthographic projection of the first electrode on the base substrate.
  • the display panel includes a third interlayer dielectric layer, a first flat layer and a third conductive layer that are stacked in sequence, and the third interlayer dielectric layer is located in the second interlayer dielectric layer On the side away from the base substrate, the first flat layer is located on the side of the third interlayer dielectric layer away from the base substrate, and the third conductive layer is connected to the second conductive layer.
  • the display panel includes an anode layer connected to the third conductive layer.
  • the display panel includes a second transistor
  • the active layer includes a source region, a drain region and a channel region of the second transistor
  • the first conductive layer includes the second transistor
  • the source electrode of the second transistor is respectively connected to the source region of the second transistor and the fourth electrode.
  • the gate layer includes a gate of the second transistor, and the gate of the second transistor is disposed opposite to a channel region of the second transistor.
  • the manufacturing method of the display panel includes the following steps:
  • a base substrate is provided, a light shielding layer is formed on the base substrate, and the light shielding layer includes a first electrode;
  • the active layer includes a second electrode, and the second electrode is connected to the first electrode;
  • a gate insulating layer is formed on the active layer, and a gate layer is formed on the gate insulating layer, the gate layer includes a third electrode, and the third electrode is on the base substrate the orthographic projection at least partially overlaps the orthographic projection of the first electrode on the base substrate to form a first storage capacitor;
  • a first interlayer dielectric layer is formed on the gate layer, and a first conductive layer is formed on the first interlayer dielectric layer.
  • the first conductive layer includes a fourth electrode, and the fourth electrode is connected to the The third electrode is connected, and the orthographic projection of the fourth electrode on the base substrate at least partially overlaps the orthographic projection of the second electrode on the base substrate to form a second storage capacitor.
  • a display device includes the display panel described in any of the foregoing embodiments.
  • the first electrode is arranged in the light shielding layer
  • the second electrode is arranged in the active layer
  • the third electrode is arranged in the gate layer
  • the first conductive layer is arranged in the first conductive layer.
  • a fourth electrode is arranged in the layer, thereby forming a first storage capacitor and a second storage capacitor in the display panel, increasing the capacity of the storage capacitor, and ensuring the stability of the gate voltage of the driving transistor.
  • the increased capacity of the storage capacitor can also effectively eliminate the influence of parasitic capacitance in the circuit and improve the display effect.
  • FIG. 1 is a schematic structural diagram of a display panel according to some embodiments of the present application.
  • FIG. 2 is a schematic circuit diagram of a display panel according to some embodiments of the present application.
  • FIG. 3 is another schematic structural diagram of a display panel according to some embodiments of the present application.
  • FIG. 4 is a schematic flowchart of a manufacturing method of a display panel according to some embodiments of the present application.
  • FIG. 5 is a schematic flowchart of a manufacturing method of a display panel according to some embodiments of the present application.
  • the display panel 10 The display panel 10, the base substrate 101, the light shielding layer 102, the first electrode 1021, the buffer layer 103, the active layer 104, the second electrode 1041, the source region 1042 of the first transistor, the drain region 1043 of the first transistor, Channel region 1044 of the first transistor, source region 1045 of the second transistor, drain region 1046 of the second transistor, channel region 1047 of the second transistor, gate insulating layer 105, gate layer 106, third electrode 1061, gate 1062 of the first transistor, gate 1063 of the second transistor, first interlayer dielectric layer 107, first conductive layer 108, fourth electrode 1081, source 1082 of the first transistor, source of the second transistor electrode 1083, second interlayer dielectric layer 109, second conductive layer 110, fifth electrode 1101, third interlayer dielectric layer 111, first flat layer 112, third conductive layer 113, first passivation layer 114, first Two flat layers 115, a second passivation layer 116, an anode layer 117, a first transistor T1, a
  • the display panel 10 includes a base substrate 101 , a light shielding layer 102 , a buffer layer 103 , an active layer 104 , a gate insulating layer 105 , a gate layer 106 , and a first interlayer dielectric layer, which are stacked in sequence. 107 and the first conductive layer 108.
  • the light shielding layer 102 includes a first electrode 1021 , the active layer 104 includes a second electrode 1041 , and the second electrode 1041 is connected to the first electrode 1021 .
  • the gate layer 106 includes a third electrode 1061, the orthographic projection of the third electrode 1061 on the base substrate 101 at least partially overlaps with the orthographic projection of the first electrode 1021 on the base substrate 101 to form a first storage capacitor.
  • the first conductive layer 108 includes a fourth electrode 1081, the fourth electrode 1081 is connected to the third electrode 1061, and the orthographic projection of the fourth electrode 1081 on the base substrate 101 and the orthographic projection of the second electrode 1041 on the base substrate 101 are at least partially overlap to form a second storage capacitor.
  • FIG. 2 in a top-gate Active Matrix Organic Light-Emitting Diode (AMOLED) circuit, the 3T1C structure shown in the figure is adopted, and a conductor is arranged on the active layer 104 parts and semiconductor parts.
  • AMOLED Active Matrix Organic Light-Emitting Diode
  • the display panel 10 includes a base substrate 101 , a light shielding layer 102 , a buffer layer 103 , an active layer 104 , a gate insulating layer 105 , a gate layer 106 , and a first layer that are sequentially stacked from bottom to top.
  • the intermediate dielectric layer 107 and the first conductive layer 108 includes a first electrode 1021
  • the active layer 104 includes a second electrode 1041
  • the second electrode 1041 and the first electrode 1021 are connected through via holes provided on the buffer layer 103 .
  • the gate layer 106 includes a third electrode 1061
  • the first conductive layer 108 includes a fourth electrode 1081
  • the fourth electrode 1081 and the third electrode 1061 are connected through vias provided on the first interlayer dielectric layer 107 .
  • the orthographic projection of the third electrode 1061 on the base substrate 101 at least partially overlaps with the orthographic projection of the first electrode 1021 on the base substrate 101 , that is, the third electrode 1061 is at least partially opposite to the first electrode 1021 .
  • the portion of the third electrode 1061 opposite to the first electrode 1021 forms a first storage capacitor.
  • the orthographic projection of the fourth electrode 1081 on the base substrate 101 and the orthographic projection of the second electrode 1041 on the base substrate 101 at least partially overlap, and the fourth electrode 1081 and the second electrode 1041 are formed at the portion opposite to the second electrode 1041. Two storage capacitors.
  • the first storage capacitor and the second storage capacitor are connected in parallel. Connecting the first storage capacitor and the second storage capacitor in parallel can increase the total capacity of the storage capacitor Cst.
  • the first electrode 1021 is provided in the light shielding layer 102
  • the second electrode 1041 is provided in the active layer 104
  • the third electrode 1061 is provided in the gate layer 106
  • the first conductive layer is provided in the first conductive layer 102 .
  • a fourth electrode 1081 is arranged in the layer 108 to form a first storage capacitor and a second storage capacitor in the display panel 10, increase the capacity of the storage capacitor, and ensure the stability of the gate voltage of the driving transistor, namely the first transistor T1.
  • the increased capacity of the storage capacitor Cst can also effectively eliminate the influence of parasitic capacitance in the circuit and improve the display effect.
  • the orthographic projection of the second electrode 1041 on the base substrate 101 at least partially overlaps the orthographic projection of the third electrode 1061 on the base substrate 101 .
  • the orthographic projection of the second electrode 1041 on the base substrate 101 and the orthographic projection of the third electrode 1061 on the base substrate 101 at least partially overlap.
  • the fourth storage capacitor can be formed, thereby increasing the capacity of the storage capacitor and ensuring the stability of the gate voltage of the driving transistor, that is, the first transistor T1.
  • the increased capacity of the storage capacitor Cst can also effectively eliminate the influence of parasitic capacitance in the circuit and improve the display effect.
  • the orthographic projection of the second electrode 1041 on the base substrate 101 does not overlap with the orthographic projection of the third electrode 1061 on the base substrate 101 .
  • the orthographic projection of the second electrode 1041 on the base substrate 101 does not overlap with the orthographic projection of the third electrode 1061 on the base substrate 101, so that the crosstalk between the second electrode 1041 and the third electrode 1061 can be reduced risk and improve the stability of the display panel 10 .
  • the flatness of the gate insulating layer 105 and the gate layer 106 can also be improved.
  • the display panel 10 includes a first transistor T1
  • the active layer 104 includes a source region 1042, a drain region 1043 and a channel region 1044 of the first transistor T1
  • the first conductive layer 108 includes a first transistor
  • the source 1082 of T1 and the source 1082 of the first transistor T1 are respectively connected to the source region 1042 and the first electrode 1021 of the first transistor T1
  • the second electrode 1041 is connected to the source region 1042 of the first transistor T1.
  • the active layer 104 includes a source region 1042, a drain region 1043 and a channel region 1044 of the first transistor T1
  • the first conductive layer 108 includes a source 1082 of the first transistor T1
  • a source of the first transistor T1 1082 is connected to the source region 1042 of the first transistor T1, so that the signal communication between the source region 1042 of the first transistor T1 and the source 1082 of the first transistor T1 can be realized.
  • the source electrode 1082 of the first transistor T1 is connected to the first electrode 1021, so that the signal communication between the first electrode 1021 and the source electrode 1082 of the first transistor T1 can be realized.
  • the second electrode 1041 is connected to the source region 1042 of the first transistor T1, so that the signal communication between the second electrode and the source region 1042 of the first transistor T1 can be realized.
  • the first transistor T1 in the embodiments of the present application may be a top-gate thin film transistor. Since the overlapping area between the source-drain electrodes and the gate of the top-gate thin film transistor is small, the top-gate thin film transistor has lower parasitic capacitance, which can effectively reduce the delay in the signal transmission process. At the same time, the self-aligned preparation method is beneficial to the preparation of short-channel top-gate thin-film transistors, thereby increasing the on-state current of the top-gate thin-film transistors, improving the display effect, and reducing the power consumption of the top-gate thin-film transistors .
  • the thickness of the source region 1042 and the drain region 1043 of the first transistor T1 is different from the thickness of the second electrode 1041 .
  • the source and drain regions 1042, 1043 and the second electrode 1041 of the first transistor may be formed by different processes, so that the thickness of the source region 1042 and the drain region 1043 of the first transistor is the same as that of the first transistor.
  • the thicknesses of the second electrodes 1041 are different.
  • the thickness of the source region 1042 and the drain region 1043 of the first transistor is relatively large, and the thickness of the second electrode 1041 is relatively small. Since the capacitance is inversely proportional to the thickness of the electrode plate, when other conditions remain unchanged, reducing the thickness of the second electrode 1041 can increase the capacity of the second storage capacitor.
  • the thickness of the source region 1042 and the drain region 1043 of the first transistor T1 and the thickness of the second electrode 1041 may be the same.
  • the thicknesses of the source region 1042 and the drain region 1043 of the first transistor T1 are the same as the thickness of the second electrode 1041
  • the source region 1042, the drain region 1043 and the second electrode 1043 of the first transistor T1 may be formed by the same process. In this way, the electrode 1041 can simplify the production process and improve the production efficiency of the display panel 10 .
  • the material of the active layer may be conductor indium gallium zinc oxide (Indium Gallium Zinc Oxide, IGZO), that is, the source region 1042 and the drain region 1043 of the first transistor in the active layer
  • IGZO Indium Gallium Zinc Oxide
  • the second electrode 1041 is made of conductive IGZO as a material.
  • the source and drain regions 1042 and 1043 of the first transistor and the second electrode 1041 can also be used to form the source and drain regions 1042 and 1043 of the first transistor and the second electrode 1041 respectively.
  • the source region 1042 and the drain region 1043 of the first transistor are made of conductive IGZO
  • the material of the second electrode 1041 can be the same as the material of the gate layer 106, for example, a metal such as molybdenum is used as the material of the electrode plate. limited.
  • the gate layer 106 includes a gate 1062 of the first transistor T1, the gate 1062 of the first transistor T1 is disposed opposite to the channel region 1044 of the first transistor T1, and the gate 1062 of the first transistor T1 connected to the third electrode 1061 .
  • the gate 1062 of the first transistor T1 is disposed opposite to the channel region 1044 of the first transistor T1, and the gate 1062 of the first transistor T1 is connected to the third electrode 1061, so that the gate of the first transistor T1 can be realized 1062 communicates with the signal of the third electrode 1061 .
  • the display panel 10 includes a second interlayer dielectric layer 109 and a second conductive layer 110.
  • the second interlayer dielectric layer 109 is located on the side of the first interlayer dielectric layer 107 away from the base substrate 101.
  • the second conductive layer 110 is located on the side of the second interlayer dielectric layer 109 away from the base substrate 101 , the second conductive layer 110 includes a fifth electrode 1101 , the fifth electrode 1101 is connected to the second electrode 1041 , and the fifth electrode 1101 is on the substrate
  • the orthographic projection on the substrate 101 at least partially overlaps the orthographic projection of the fourth electrode 1081 on the base substrate 101 to form a third storage capacitor.
  • the second conductive layer 110 includes a fifth electrode 1101
  • the active layer 104 includes a second electrode 1041
  • the fifth electrode 1101 and the second electrode 1041 pass through the first interlayer dielectric layer 107 and the second interlayer dielectric layer 109 .
  • Set via connections
  • the orthographic projection of the fifth electrode 1101 on the base substrate 101 at least partially overlaps with the orthographic projection of the fourth electrode 1081 on the base substrate 101, that is, the fifth electrode 1101 is at least partially opposite to the second electrode 1041, A portion of the fifth electrode 1101 opposite to the second electrode 1041 forms a third storage capacitor.
  • the connection method is parallel. Connecting the first storage capacitor, the second storage capacitor and the third storage capacitor in parallel can increase the total capacity of the storage capacitor Cst. In this way, the stability of the gate voltage of the first transistor T1 can be ensured. At the same time, the increased capacity of the storage capacitor Cst can also effectively eliminate the influence of parasitic capacitance in the circuit and improve the display effect.
  • the orthographic projection of the fifth electrode 1101 on the base substrate 101 overlaps the orthographic projection of the first electrode 1021 on the base substrate.
  • the orthographic projection of the fifth electrode 1101 on the base substrate 101 covers the orthographic projection of the first electrode 1021 on the base substrate 101 , which can increase the size of the first electrode 1021 and the third electrode 1061 and the fifth electrode 1101 and the fifth electrode 1101 .
  • the facing area of the fourth electrode 1081 increases the capacity of the first storage capacitor and the third storage capacitor and ensures the stability of the gate voltage of the driving transistor. At the same time, the increased capacity of the storage capacitor can also effectively eliminate the influence of parasitic capacitance in the circuit and improve the display effect.
  • the orthographic projection of the fifth electrode 1101 on the base substrate 101 covers the orthographic projection of the first electrode 1021 on the base substrate 101 , which can also improve the flatness of the second conductive layer 110 .
  • the display panel 10 includes a third interlayer dielectric layer 111 , a first flat layer 112 and a third conductive layer 113 that are stacked in sequence, and the third interlayer dielectric layer 111 is located on the second interlayer dielectric layer 109 On the side away from the base substrate 101 , the first flat layer 112 is located on the side of the third interlayer dielectric layer 111 away from the base substrate 101 , and the third conductive layer 113 is connected to the second conductive layer 110 .
  • the third conductive layer 113 is connected to the second conductive layer 110 , so that the signal communication between the third conductive layer 113 and the second conductive layer 110 can be realized.
  • the third conductive layer 113 may be connected to the first data line Data, the first power supply line VDD and the second data line Sense, so as to write data into each transistor of the circuit and drive the light-emitting element to emit light and dim.
  • the display panel 10 includes an anode layer 117 connected to the third conductive layer 113 .
  • the display panel 10 includes a first passivation layer 114 , a second flat layer 115 , a second passivation layer 116 and an anode layer 117 which are stacked in sequence.
  • the first passivation layer 114 is located on the side of the third conductive layer 113 away from the base substrate 101
  • the second flat layer 115 is located at the side of the first passivation layer 114 away from the base substrate 101
  • the anode layer 117 is located on the side of the second flat layer 115 away from the base substrate 101
  • the anode layer 117 is located at the side of the second passivation layer 116 away from the base substrate 101 .
  • the display panel 10 can be planarized and the circuit structure in the display panel 10 can be protected to reduce or prevent deterioration of the circuit structure due to moisture and/or oxygen contained in the environment.
  • the anode layer 117 is connected to the third conductive layer 113 , so that the signal communication between the third conductive layer 113 and the second conductive layer 110 can be realized.
  • the display panel 10 includes a second transistor T2T2, the active layer 104 includes a source region 1045, a drain region and a channel region of the second transistor T2, and the first conductive layer 108 includes a source region 1045, a drain region and a channel region of the second transistor T2.
  • the source electrode 1083 and the source electrode 1083 of the second transistor T2 are respectively connected to the source region 1045 and the fourth electrode 1081 of the second transistor T2.
  • the active layer 104 includes a source region 1045, a drain region and a channel region of the second transistor T2
  • the first conductive layer 108 includes a source 1083 of the second transistor T2
  • the source 1083 of the second transistor T2 is connected, so that the signal communication between the source 1083 of the second transistor T2 and the source region 1045 of the second transistor T2 can be realized.
  • the source electrode 1083 of the second transistor T2 is connected to the fourth electrode 1081, so that the signal communication between the source electrode 1083 and the fourth electrode 1081 of the second transistor T2 can be realized.
  • the second transistor T2 in the embodiments of the present application may be a top-gate thin film transistor. Since the overlapping area between the source-drain electrodes and the gate of the top-gate thin film transistor is small, the top-gate thin film transistor has lower parasitic capacitance, which can effectively reduce the delay in the signal transmission process. At the same time, the self-aligned preparation method is beneficial to the preparation of short-channel top-gate thin-film transistors, thereby increasing the on-state current of the top-gate thin-film transistors, improving the display effect, and reducing the power consumption of the top-gate thin-film transistors .
  • the gate layer 106 includes a gate 1063 of the second transistor T2, and the gate 1063 of the second transistor T2 is disposed opposite to the channel region 1047 of the second transistor T2.
  • the manufacturing method of the display panel 10 includes the following steps:
  • S10 Provide a base substrate 101, and form a light shielding layer 102 on the base substrate 101, where the light shielding layer 102 includes a first electrode 1021;
  • S20 forming a buffer layer 103 on the light shielding layer 102, and forming an active layer 104 on the buffer layer, the active layer 104 includes a second electrode 1041, and the second electrode 1041 is connected to the first electrode 1021;
  • the gate layer 106 includes a third electrode 1061 , and the third electrode 1061 is formed on the base substrate 101 the orthographic projection at least partially overlaps with the orthographic projection of the first electrode 1021 on the base substrate 101 to form a first storage capacitor;
  • S40 forming a first interlayer dielectric layer 107 on the gate layer 106, and forming a first conductive layer 108 on the first interlayer dielectric layer 107, the first conductive layer 108 includes a fourth electrode 1081, the fourth electrode 1081 and the The third electrode 1061 is connected, and the orthographic projection of the fourth electrode 1081 on the base substrate 101 at least partially overlaps with the orthographic projection of the second electrode 1041 on the base substrate 101 to form a second storage capacitor.
  • the display panel 10 includes a base substrate 101 , a light shielding layer 102 , a buffer layer 103 , an active layer 104 , a gate insulating layer 105 , a gate layer 106 , and a first interlayer dielectric layer, which are sequentially stacked from bottom to top. 107 and the first conductive layer 108 .
  • the light shielding layer 102 includes a first electrode 1021
  • the active layer 104 includes a second electrode 1041
  • the second electrode 1041 and the first electrode 1021 are connected through via holes provided on the buffer layer 103 .
  • the gate layer 106 includes a third electrode 1061
  • the first conductive layer 108 includes a fourth electrode 1081
  • the fourth electrode 1081 and the third electrode 1061 are connected through vias provided on the first interlayer dielectric layer 107 .
  • the orthographic projection of the third electrode 1061 on the base substrate 101 at least partially overlaps with the orthographic projection of the first electrode 1021 on the base substrate 101 , that is, the third electrode 1061 is at least partially opposite to the first electrode 1021 .
  • the portion of the third electrode 1061 opposite to the first electrode 1021 forms a first storage capacitor.
  • the orthographic projection of the fourth electrode 1081 on the base substrate 101 and the orthographic projection of the second electrode 1041 on the base substrate 101 at least partially overlap, and the fourth electrode 1081 and the second electrode 1041 are formed at the portion opposite to the second electrode 1041. Two storage capacitors.
  • the first storage capacitor and the second storage capacitor are connected in parallel. Connecting the first storage capacitor and the second storage capacitor in parallel can increase the total capacity of the storage capacitor Cst.
  • the first electrode 1021 is provided in the light shielding layer 102
  • the second electrode 1041 is provided in the active layer 104
  • the third electrode 1061 is provided in the gate layer 106
  • the A fourth electrode 1081 is provided in the first conductive layer 108, thereby forming a first storage capacitor and a second storage capacitor in the display panel 10, increasing the capacity of the storage capacitor Cst, and ensuring the stability of the gate voltage of the driving transistor, namely the first transistor T1 .
  • the increased capacity of the storage capacitor Cst can also effectively eliminate the influence of parasitic capacitance in the circuit and improve the display effect.
  • the manufacturing method further includes the following steps:
  • the second conductive layer 110 includes a fifth electrode 1101 and a fifth electrode 1101
  • the orthographic projection of the fifth electrode 1101 on the base substrate 101 at least partially overlaps with the orthographic projection of the fourth electrode 1081 on the base substrate 101 to form a third storage capacitor.
  • the second conductive layer 110 includes a fifth electrode 1101
  • the active layer 104 includes a second electrode 1041
  • the fifth electrode 1101 and the second electrode 1041 pass through the first interlayer dielectric layer 107 and the second interlayer dielectric layer 109 .
  • Set via connections
  • the orthographic projection of the fifth electrode 1101 on the base substrate 101 at least partially overlaps with the orthographic projection of the fourth electrode 1081 on the base substrate 101, that is, the fifth electrode 1101 is at least partially opposite to the second electrode 1041, A portion of the fifth electrode 1101 opposite to the second electrode 1041 forms a third storage capacitor.
  • the connection method is parallel. Connecting the first storage capacitor, the second storage capacitor and the third storage capacitor in parallel can increase the total capacity of the storage capacitor Cst. In this way, the stability of the gate voltage of the first transistor T1 can be ensured. At the same time, the increased capacity of the storage capacitor Cst can also effectively eliminate the influence of parasitic capacitance in the circuit and improve the display effect.
  • a third interlayer dielectric layer 111 , a first flat layer 112 and a third conductive layer 113 are sequentially formed on the second conductive layer 110 , and the third interlayer dielectric layer 111 is located on the second interlayer dielectric layer 109 away from the substrate On one side of the substrate 101 , the first flat layer 112 is located on the side of the third interlayer dielectric layer 111 away from the base substrate 101 , and the third conductive layer 113 is connected to the second conductive layer 110 .
  • a first passivation layer 114 , a second flat layer 115 , a second passivation layer 116 and an anode layer 117 are sequentially formed on the first flat layer 112 .
  • the first passivation layer 114 is located on the side of the third conductive layer 113 away from the base substrate 101
  • the second flat layer 115 is located at the side of the first passivation layer 114 away from the base substrate 101
  • the anode layer 117 is located on the side of the second flat layer 115 away from the base substrate 101
  • the anode layer 117 is located at the side of the second passivation layer 116 away from the base substrate 101
  • the anode layer 117 is connected to the third conductive layer 113 .
  • the display device includes the display panel 10 described in any of the foregoing embodiments.
  • the display device may be a mobile phone, a tablet computer, an ATM, a smart wearable device, a smart home appliance, a game console, a head-mounted display device, etc., which is not specifically limited. It can be understood that the display device may also be any other device having a display function.

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Abstract

一种显示面板(10)，包括依次层叠设置的衬底基板(101)、遮光层(102)、缓冲层(103)、有源层(104)、栅极绝缘层(105)、栅极层(106)、第一层间介质层(107)和第一导电层(108)。其中，遮光层(102)包括第一电极(1021)，有源层(104)包括第二电极(1041)，第二电极(1041)与第一电极(1021)连接。栅极层(106)包括第三电极(1061)，第三电极(1061)在衬底基板(101)上的正投影与第一电极(1021)在衬底基板(101)上的正投影至少部分重叠以形成第一存储电容。第一导电层(108)包括第四电极(1081)，第四电极(1081)与第三电极(1061)连接，第四电极(1081)在衬底基板(101)上的正投影与第二电极(1041)在衬底基板(101)上的正投影至少部分重叠以形成第二存储电容。还公开了一种显示面板的制作方法和显示装置。

Description

显示面板及其制作方法和显示装置 技术领域
本公开涉及显示技术领域，特别涉及一种显示面板及其制作方法和显示装置。
背景技术
随着显示装置的分辨率越来越高，像素的尺寸逐渐减小，像素电路中的存储电容中电极的正对面积减小，进而导致存储电容容量减小。在存储电容的容量较小的情况下，存储电容难以维持驱动晶体管的栅极电压的稳定，影响显示效果。
发明内容
本申请的实施方式提供了一种显示面板及其制作方法和显示装置。
本申请实施方式的显示面板包括依次层叠设置的衬底基板、遮光层、缓冲层、有源层、栅极绝缘层、栅极层、第一层间介质层和第一导电层，其中，
所述遮光层包括第一电极；
所述有源层包括第二电极，所述第二电极与所述第一电极连接；
所述栅极层包括第三电极，所述第三电极在所述衬底基板上的正投影与所述第一电极在所述衬底基板上的正投影至少部分重叠以形成第一存储电容；
所述第一导电层包括第四电极，所述第四电极与所述第三电极连接，所述第四电极在所述衬底基板上的正投影与所述第二电极在所述衬底基板上的正投影至少部分重叠以形成第二存储电容。
在某些实施方式中，所述第二电极在所述衬底基板上的正投影与所述第三电极在所述衬底基板上的正投影至少部分重叠。
在某些实施方式中，所述第二电极在所述衬底基板上的正投影与所述第三电极在所述衬底基板上的正投影不重叠。
在某些实施方式中，所述显示面板包括第一晶体管，所述有源层包括所述第一晶体管的源极区、漏极区和沟道区，所述第一导电层包括所述第一晶体管的源极，所述第一晶体管的源极分别与所述第一晶体管的源极区和所述第一电极连接，所述第二电极与所述第一晶体管的源极区连接。
在某些实施方式中，所述第一晶体管的源极区和漏极区的厚度与所述第二电极的厚度不同。
在某些实施方式中，所述栅极层包括所述第一晶体管的栅极，所述第一晶体管的栅极 与所述第一晶体管的沟道区相对设置，所述第一晶体管的栅极与所述第三电极连接。
在某些实施方式中，所述显示面板包括第二导电层和第二层间介质层，所述第二层间介质层位于所述第一层间介质层远离所述衬底基板的一侧，所述第二导电层位于所述第二层间介质层远离所述衬底基板的一侧，所述第二导电层包括第五电极，所述第五电极与所述第二电极连接，所述第五电极在所述衬底基板上的正投影与所述第四电极在所述衬底基板上的正投影至少部分重叠以形成第三存储电容。
在某些实施方式中，所述第五电极在所述衬底基板上的正投影覆盖所述第一电极在所述衬底基板上的正投影。
在某些实施方式中，所述显示面板包括依次层叠设置的第三层间介质层、第一平坦层和第三导电层，所述第三层间介质层位于所述第二层间介质层远离所述衬底基板的一侧，所述第一平坦层位于所述第三层间介质层远离所述衬底基板的一侧，所述第三导电层与所述第二导电层连接。
在某些实施方式中，所述显示面板包括阳极层，所述阳极层与所述第三导电层连接。
在某些实施方式中，所述显示面板包括第二晶体管，所述有源层包括所述第二晶体管的源极区、漏极区和沟道区，所述第一导电层包括第二晶体管的源极，所述第二晶体管的源极分别与第二晶体管的源极区和所述第四电极连接。
在某些实施方式中，所述栅极层包括所述第二晶体管的栅极，所述第二晶体管的栅极与所述第二晶体管的沟道区相对设置。
本申请实施方式的显示面板的制作方法，所述显示面板的制作方法包括以下步骤：
提供一衬底基板，在所述衬底基板上形成遮光层，所述遮光层包括第一电极；
在所述遮光层上形成缓冲层，并在所述缓存层上形成有源层，所述有源层包括第二电极，所述第二电极和所述第一电极连接；
在所述有源层上形成栅极绝缘层，并在所述栅极绝缘层上形成栅极层，所述栅极层包括第三电极，所述第三电极在所述衬底基板上的正投影与第一电极在所述衬底基板上的正投影至少部分重叠以形成第一存储电容；
在所述栅极层上形成第一层间介质层，并在所述第一层间介质层上形成第一导电层，所述第一导电层包括第四电极，所述第四电极与所述第三电极连接，所述第四电极在所述衬底基板上的正投影与所述第二电极在所述衬底基板上的正投影至少部分重叠以形成第二存储电容。
本申请实施方式的显示装置包括上述任一实施方式所述的显示面板。
本申请实施方式的显示面板及其制作方法和显示装置中，通过在遮光层中设置第一电极、在有源层中设置第二电极、在栅极层中设置第三电极以及在第一导电层中设置第四电 极，从而在显示面板中形成第一存储电容和第二存储电容，增大存储电容的容量，确保驱动晶体管栅极电压的稳定。同时，存储电容的容量增大，还能够有效消除电路中寄生电容的影响，提升显示效果。
本申请的附加方面和优点将在下面的描述中部分给出，部分将从下面的描述中变得明显，或通过本申请的实践了解到。
附图说明
本申请的上述和/或附加的方面和优点从结合下面附图对实施方式的描述中将变得明显和容易理解，其中：
图1是本申请某些实施方式的显示面板的结构示意图。
图2是本申请某些实施方式的显示面板的电路示意图。
图3是本申请某些实施方式的显示面板的又一结构示意图。
图4是本申请某些实施方式的显示面板的制作方法的流程示意图。
图5是本申请某些实施方式的显示面板的制作方法的流程示意图。
主要元件符号说明：
显示面板10、衬底基板101、遮光层102、第一电极1021、缓冲层103、有源层104、第二电极1041、第一晶体管的源极区1042、第一晶体管的漏极区1043、第一晶体管的沟道区1044、第二晶体管的源极区1045、第二晶体管的漏极区1046、第二晶体管的沟道区1047、栅极绝缘层105、栅极层106、第三电极1061、第一晶体管的栅极1062、第二晶体管的栅极1063、第一层间介质层107、第一导电层108、第四电极1081、第一晶体管的源极1082、第二晶体管的源极1083、第二层间介质层109、第二导电层110、第五电极1101、第三层间介质层111、第一平坦层112、第三导电层113、第一钝化层114、第二平坦层115、第二钝化层116、阳极层117、第一晶体管T1、第二晶体管T2、第三晶体管T3、存储电容Cst、第一数据线Data、第二数据线Sense、第一电源线VDD、第二电源线VSS。
具体实施方式
下面详细描述本申请的实施方式，所述实施方式的示例在附图中示出，其中自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。下面通过参考附图描述的实施方式是示例性的，仅用于解释本申请，而不能理解为对本申请的限制。
在本申请的描述中，需要理解的是，术语“第一”、“第二”仅用于描述目的，而不能理 解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个所述特征。在本申请的描述中，“多个”的含义是两个或两个以上，除非另有明确具体的限定。
下文的公开提供了许多不同的实施方式或例子用来实现本申请的不同结构。为了简化本申请的公开，下文中对特定例子的部件和设置进行描述。当然，它们仅仅为示例，并且目的不在于限制本申请。此外，本申请可以在不同例子中重复参考数字和/或参考字母，这种重复是为了简化和清楚的目的，其本身不指示所讨论各种实施方式和/或设置之间的关系。此外，本申请提供了的各种特定的工艺和材料的例子，但是本领域普通技术人员可以意识到其他工艺的应用和/或其他材料的使用。
请一并参阅图1，显示面板10包括依次层叠设置的衬底基板101、遮光层102、缓冲层103、有源层104、栅极绝缘层105、栅极层106、第一层间介质层107和第一导电层108。
其中，遮光层102包括第一电极1021，有源层104包括第二电极1041，第二电极1041与第一电极1021连接。栅极层106包括第三电极1061，第三电极1061在衬底基板101上的正投影与第一电极1021在衬底基板101上的正投影至少部分重叠以形成第一存储电容。第一导电层108包括第四电极1081，第四电极1081与第三电极1061连接，第四电极1081在衬底基板101上的正投影与第二电极1041在衬底基板101上的正投影至少部分重叠以形成第二存储电容。
具体地，请参阅图2，在顶栅型有源矩阵驱动式有机电致发光(Active Matrix Organic Light-Emitting Diode，AMOLED)电路中，采用图示的3T1C结构，并在有源层104设置导体部分和半导体部分。此电路中，在存储电容Cst较大的情况下，能够使得第一晶体管T1的栅极驱动电压处于较稳定的状态，同时，存储电容Cst较大时，还能够有效消除寄生电容带来的影响，提升电路的抗干扰能力。
请再次参阅图1，显示面板10包括从下到上依次层叠设置的衬底基板101、遮光层102、缓冲层103、有源层104、栅极绝缘层105、栅极层106、第一层间介质层107以及第一导电层108。其中，遮光层102包括第一电极1021，有源层104包括第二电极1041，第二电极1041与第一电极1021通过缓冲层103上设置的过孔连接。栅极层106包括第三电极1061，第一导电层108包括第四电极1081，第四电极1081与第三电极1061通过第一层间介质层107上设置的过孔连接。
第三电极1061在衬底基板101上的正投影与第一电极1021在衬底基板101上的正投影至少部分重叠，也即是说，第三电极1061与第一电极1021至少部分相对，在第三电极1061与第一电极1021相对的部分形成第一存储电容。相类似地，第四电极1081在衬底基板101上的正投影与第二电极1041在衬底基板101上的正投影至少部分重叠，在第四电极 1081与第二电极1041相对的部分形成第二存储电容。由于第二电极1041与第一电极1021连接，第四电极1081与第三电极1061连接，因此，第一存储电容与第二存储电容的连接方式为并联。第一存储电容和第二存储电容并联，能够使得存储电容Cst的总容量增大。
本申请实施方式的显示面板10中，通过在遮光层102中设置第一电极1021、在有源层104中设置第二电极1041、在栅极层106中设置第三电极1061以及在第一导电层108中设置第四电极1081，从而在显示面板10中形成第一存储电容和第二存储电容，增大存储电容的容量，确保驱动晶体管即第一晶体管T1栅极电压的稳定。同时，存储电容Cst的容量增大，还能够有效消除电路中寄生电容的影响，提升显示效果。
在某些实施方式中，第二电极1041在衬底基板101上的正投影与第三电极1061在衬底基板101上的正投影至少部分重叠。
具体地，第二电极1041在衬底基板101上的正投影与第三电极1061在衬底基板101上的正投影至少部分重叠，如此，在第二电极1041与第三电极1061的重叠部分，能够形成第四存储电容，从而增大存储电容的容量，确保驱动晶体管即第一晶体管T1栅极电压的稳定。同时，存储电容Cst的容量增大，还能够有效消除电路中寄生电容的影响，提升显示效果。
请参阅图3，在某些实施方式中，第二电极1041在衬底基板101上的正投影与第三电极1061在衬底基板101上的正投影不重叠。
具体地，第二电极1041在衬底基板101上的正投影与第三电极1061在衬底基板101上的正投影不重叠，如此，能够降低第二电极1041与第三电极1061之间发生串扰的风险，提高显示面板10的稳定性。同时，也能够使得栅极绝缘层105和栅极层106的平坦性更佳。
在某些实施方式中，显示面板10包括第一晶体管T1，有源层104包括第一晶体管T1的源极区1042、漏极区1043和沟道区1044，第一导电层108包括第一晶体管T1的源极1082，第一晶体管T1的源极1082分别与第一晶体管T1的源极区1042和第一电极1021连接，第二电极1041与第一晶体管T1的源极区1042连接。
具体地，有源层104包括第一晶体管T1的源极区1042、漏极区1043和沟道区1044，第一导电层108包括第一晶体管T1的源极1082，第一晶体管T1的源极1082与第一晶体管T1的源极区1042连接，如此，能够实现第一晶体管T1的源极区1042与第一晶体管T1的源极1082的信号互通。第一晶体管T1的源极1082与第一电极1021连接，能够实现第一电极1021与第一晶体管T1的源极1082的信号互通。第二电极1041与第一晶体管T1的源极区1042连接，能够实现第二电极与第一晶体管T1的源极区1042的信号互通。
需要说明地，本申请实施方式中的第一晶体管T1可以是顶栅型薄膜晶体管。由于顶栅 型薄膜晶体管的源漏电极与栅极之间重叠面积较小，因此，顶栅型薄膜晶体管具有更低的寄生电容，能够有效降低信号传输过程中的延迟。同时，采用自对准的制备方法，有利于制备短沟道的顶栅型薄膜晶体管，从而提升顶栅型薄膜晶体管的开态电流，提升显示效果，并能够降低顶栅型薄膜晶体管的功耗。
在某些实施方式中，第一晶体管T1的源极区1042和漏极区1043的厚度与第二电极1041的厚度不同。
具体地，在有源层中，可以采用不同的工艺分别形成第一晶体管的源漏极区1042、1043和第二电极1041，使得第一晶体管的源极区1042和漏极区1043的厚度与第二电极1041的厚度不同。例如，第一晶体管的源极区1042和漏极区1043的厚度较大，第二电极1041的厚度较小。由于电容容量与电极极板厚度成反比，在其余条件均保持不变的情况下，减小第二电极1041的厚度，能够增大第二存储电容的容量。
需要说明地，第一晶体管T1的源极区1042和漏极区1043的厚度与第二电极1041的厚度可以相同。在第一晶体管T1的源极区1042和漏极区1043的厚度与第二电极1041的厚度相同时，可以采用相同的工艺形成第一晶体管T1的源极区1042、漏极区1043和第二电极1041，如此，能够简化生产流程，提高显示面板10的生产效率。
进一步地，有源层的材料可以是导体化铟镓锌氧化物(Indium Gallium Zinc Oxide，IGZO)，也即是说，在有源层中的第一晶体管的源极区1042和漏极区1043以及第二电极1041均采用导体化IGZO作为材料。
在另一些实施方式中，也可以采用不同的材料分别形成第一晶体管的源漏极区1042、1043和第二电极1041。例如，第一晶体管的源极区1042和漏极区1043采用导体化IGZO，第二电极1041的材料则可以与栅极层106的材料相同，例如采用钼等金属作为极板材料，具体不做限定。
在某些实施方式中，栅极层106包括第一晶体管T1的栅极1062，第一晶体管T1的栅极1062与第一晶体管T1的沟道区1044相对设置，第一晶体管T1的栅极1062与第三电极1061连接。
具体地，第一晶体管T1的栅极1062与第一晶体管T1的沟道区1044相对设置，第一晶体管T1的栅极1062与第三电极1061连接，如此，能够实现第一晶体管T1的栅极1062与第三电极1061的信号互通。
在某些实施方式中，显示面板10包括第二层间介质层109和第二导电层110，第二层间介质层109位于第一层间介质层107远离衬底基板101的一侧，第二导电层110位于第二层间介质层109远离衬底基板101的一侧，第二导电层110包括第五电极1101，第五电极1101与第二电极1041连接，第五电极1101在衬底基板101上的正投影与第四电极1081 在衬底基板101上的正投影至少部分重叠以形成第三存储电容。
具体地，第二导电层110包括第五电极1101，有源层104包括第二电极1041，第五电极1101与第二电极1041通过第一层间介质层107和第二层间介质层109上设置的过孔连接。
第五电极1101在衬底基板101上的正投影与第四电极1081在衬底基板101上的正投影至少部分重叠，也即是说，第五电极1101与第二电极1041至少部分相对，在第五电极1101与第二电极1041相对的部分形成第三存储电容。
由于第二电极1041与第一电极1021连接，第四电极1081与第三电极1061连接，第五电极1101与第二电极1041连接，因此，第一存储电容、第二存储电容和第三存储电容的连接方式为并联。第一存储电容、第二存储电容和第三存储电容并联，能够使得存储电容Cst的总容量增大。如此，能够确保第一晶体管T1栅极电压的稳定。同时，存储电容Cst的容量增大，还能够有效消除电路中寄生电容的影响，提升显示效果。
在某些实施方式中，第五电极1101在衬底基板101上的正投影覆盖第一电极1021在衬底基板上的正投影。
具体地，第五电极1101在衬底基板101上的正投影覆盖第一电极1021在衬底基板101上的正投影，能够使增大第一电极1021与第三电极1061以及第五电极1101与第四电极1081的正对面积，从而增加第一存储电容和第三存储电容的容量，确保驱动晶体管栅极电压的稳定。同时，存储电容的容量增大，还能够有效消除电路中寄生电容的影响，提升显示效果。
此外，第五电极1101在衬底基板101上的正投影覆盖第一电极1021在衬底基板101上的正投影，也能够使得第二导电层110的平坦性更佳。
在某些实施方式中，显示面板10包括依次层叠设置的第三层间介质层111、第一平坦层112和第三导电层113，第三层间介质层111位于第二层间介质层109远离衬底基板101的一侧，第一平坦层112位于第三层间介质层111远离衬底基板101的一侧，第三导电层113与第二导电层110连接。
具体地，第三导电层113与第二导电层110连接，如此，能够实现第三导电层113与第二导电层110的信号互通。
此外，第三导电层113可与第一数据线Data、第一电源线VDD和第二数据线Sense连接，从而将数据写入电路的各个晶体管中，驱动发光元件的发光和暗灭。
在某些实施方式中，显示面板10包括阳极层117，阳极层117与第三导电层113连接。
具体地，显示面板10包括依次层叠设置的第一钝化层114、第二平坦层115、第二钝化层116和阳极层117。其中，第一钝化层114位于第三导电层113远离衬底基板101的一 侧，第二平坦层115位于第一钝化层114远离衬底基板101的一侧，第二钝化层116位于第二平坦层115远离衬底基板101的一侧，阳极层117位于第二钝化层116远离衬底基板101的一侧。如此，能够对显示面板10进行平坦化处理，并对显示面板10中的电路结构进行保护，减少或防止因环境中包括的湿气和/或氧气导致的电路结构劣化。
此外，阳极层117与第三导电层113连接，能够实现第三导电层113与第二导电层110的信号互通。
在某些实施方式中，显示面板10包括第二晶体管T2T2，有源层104包括第二晶体管T2的源极区1045、漏极区和沟道区，第一导电层108包括第二晶体管T2的源极1083，第二晶体管T2的源极1083分别与第二晶体管T2的源极区1045和第四电极1081连接。
具体地，有源层104包括第二晶体管T2的源极区1045、漏极区和沟道区，第一导电层108包括第二晶体管T2的源极1083，第二晶体管T2的源极1083与第二晶体管T2的源极区1045连接，如此，能够实现第二晶体管T2的源极1083与第二晶体管T2的源极区1045的信号互通。第二晶体管T2的源极1083与第四电极1081连接，能够实现第二晶体管T2的源极1083与第四电极1081的信号互通。
需要说明地，本申请实施方式中的第二晶体管T2可以是顶栅型薄膜晶体管。由于顶栅型薄膜晶体管的源漏电极与栅极之间重叠面积较小，因此，顶栅型薄膜晶体管具有更低的寄生电容，能够有效降低信号传输过程中的延迟。同时，采用自对准的制备方法，有利于制备短沟道的顶栅型薄膜晶体管，从而提升顶栅型薄膜晶体管的开态电流，提升显示效果，并能够降低顶栅型薄膜晶体管的功耗。
在某些实施方式中，栅极层106包括第二晶体管T2的栅极1063，第二晶体管T2的栅极1063与第二晶体管T2的沟道区1047相对设置。
请参阅图1和图4，本申请实施方式的显示面板10的制作方法，制作方法包括以下步骤：
S10：提供一衬底基板101，在衬底基板101上形成遮光层102，遮光层102包括第一电极1021；
S20：在遮光层102上形成缓冲层103，并在缓存层上形成有源层104，有源层104包括第二电极1041，第二电极1041和第一电极1021连接；
S30：在有源层104上形成栅极绝缘层105，并在栅极绝缘层105上形成栅极层106，栅极层106包括第三电极1061，第三电极1061在衬底基板101上的正投影与第一电极1021在衬底基板101上的正投影至少部分重叠以形成第一存储电容；
S40：在栅极层106上形成第一层间介质层107，并在第一层间介质层107上形成第一导电层108，第一导电层108包括第四电极1081，第四电极1081与第三电极1061连接， 第四电极1081在衬底基板101上的正投影与第二电极1041在衬底基板101上的正投影至少部分重叠以形成第二存储电容。
具体地，显示面板10包括从下到上依次层叠设置的衬底基板101、遮光层102、缓冲层103、有源层104、栅极绝缘层105、栅极层106、第一层间介质层107以及第一导电层108。其中，遮光层102包括第一电极1021，有源层104包括第二电极1041，第二电极1041与第一电极1021通过缓冲层103上设置的过孔连接。栅极层106包括第三电极1061，第一导电层108包括第四电极1081，第四电极1081与第三电极1061通过第一层间介质层107上设置的过孔连接。
第三电极1061在衬底基板101上的正投影与第一电极1021在衬底基板101上的正投影至少部分重叠，也即是说，第三电极1061与第一电极1021至少部分相对，在第三电极1061与第一电极1021相对的部分形成第一存储电容。相类似地，第四电极1081在衬底基板101上的正投影与第二电极1041在衬底基板101上的正投影至少部分重叠，在第四电极1081与第二电极1041相对的部分形成第二存储电容。由于第二电极1041与第一电极1021连接，第四电极1081与第三电极1061连接，因此，第一存储电容与第二存储电容的连接方式为并联。第一存储电容和第二存储电容并联，能够使得存储电容Cst的总容量增大。
本申请实施方式的显示面板10的制作方法中，通过在遮光层102中设置第一电极1021、在有源层104中设置第二电极1041、在栅极层106中设置第三电极1061以及在第一导电层108中设置第四电极1081，从而在显示面板10中形成第一存储电容和第二存储电容，增大存储电容Cst的容量，确保驱动晶体管即第一晶体管T1栅极电压的稳定。同时，存储电容Cst的容量增大，还能够有效消除电路中寄生电容的影响，提升显示效果。
请参阅图5，在某些实施方式中，制作方法还包括以下步骤：
S50：在第一导电层108上形成第二层间介质层109，并在第二层间介质层109上形成第二导电层110，第二导电层110包括第五电极1101，第五电极1101与第二电极1041连接，第五电极1101在衬底基板101上的正投影与第四电极1081在衬底基板101上的正投影至少部分重叠以形成第三存储电容。
具体地，第二导电层110包括第五电极1101，有源层104包括第二电极1041，第五电极1101与第二电极1041通过第一层间介质层107和第二层间介质层109上设置的过孔连接。
第五电极1101在衬底基板101上的正投影与第四电极1081在衬底基板101上的正投影至少部分重叠，也即是说，第五电极1101与第二电极1041至少部分相对，在第五电极1101与第二电极1041相对的部分形成第三存储电容。
由于第二电极1041与第一电极1021连接，第四电极1081与第三电极1061连接，第 五电极1101与第二电极1041连接，因此，第一存储电容、第二存储电容和第三存储电容的连接方式为并联。第一存储电容、第二存储电容和第三存储电容并联，能够使得存储电容Cst的总容量增大。如此，能够确保第一晶体管T1栅极电压的稳定。同时，存储电容Cst的容量增大，还能够有效消除电路中寄生电容的影响，提升显示效果。
进一步地，在第二导电层110上依次形成第三层间介质层111、第一平坦层112和第三导电层113，第三层间介质层111位于第二层间介质层109远离衬底基板101的一侧，第一平坦层112位于第三层间介质层111远离衬底基板101的一侧，第三导电层113与第二导电层110连接。
在第一平坦层112上依次形成第一钝化层114、第二平坦层115、第二钝化层116和阳极层117。其中，第一钝化层114位于第三导电层113远离衬底基板101的一侧，第二平坦层115位于第一钝化层114远离衬底基板101的一侧，第二钝化层116位于第二平坦层115远离衬底基板101的一侧，阳极层117位于第二钝化层116远离衬底基板101的一侧，阳极层117与第三导电层113连接。
本申请实施方式的显示装置包括上述任一实施方式所述的显示面板10。
具体地，显示装置可以是手机、平板电脑、柜员机、智能可穿戴设备、智能家电、游戏机、头显设备等装置，具体不做限定。可以理解地，显示装置还可以是其他任意具有显示功能的装置。
在本说明书的描述中，参考术语“一个实施方式”、“一些实施方式”、“示意性实施方式”、“示例”、“具体示例”、或“一些示例”等的描述意指结合实施方式或示例描述的具体特征、结构、材料或者特点包含于本申请的至少一个实施方式或示例中。在本说明书中，对上述术语的示意性表述不一定指的是相同的实施方式或示例。而且，描述的具体特征、结构、材料或者特点可以在任何的一个或多个实施方式或示例中以合适的方式结合。
尽管已经示出和描述了本申请的实施方式，本领域的普通技术人员可以理解：在不脱离本申请的原理和宗旨的情况下可以对这些实施方式进行多种变化、修改、替换和变型，本申请的范围由权利要求及其等同物限定。

Claims (14)

  1. 一种显示面板，其特征在于，所述显示面板包括依次层叠设置的衬底基板、遮光层、缓冲层、有源层、栅极绝缘层、栅极层、第一层间介质层和第一导电层，其中，
    所述遮光层包括第一电极；
    所述有源层包括第二电极，所述第二电极与所述第一电极连接；
    所述栅极层包括第三电极，所述第三电极在所述衬底基板上的正投影与所述第一电极在所述衬底基板上的正投影至少部分重叠以形成第一存储电容；
    所述第一导电层包括第四电极，所述第四电极与所述第三电极连接，所述第四电极在所述衬底基板上的正投影与所述第二电极在所述衬底基板上的正投影至少部分重叠以形成第二存储电容。
  2. 根据权利要求1所述的显示面板，其特征在于，所述第二电极在所述衬底基板上的正投影与所述第三电极在所述衬底基板上的正投影至少部分重叠。
  3. 根据权利要求1所述的显示面板，其特征在于，所述第二电极在所述衬底基板上的正投影与所述第三电极在所述衬底基板上的正投影不重叠。
  4. 根据权利要求1所述的显示面板，其特征在于，所述显示面板包括第一晶体管，所述有源层包括所述第一晶体管的源极区、漏极区和沟道区，所述第一导电层包括所述第一晶体管的源极，所述第一晶体管的源极分别与所述第一晶体管的源极区和所述第一电极连接，所述第二电极与所述第一晶体管的源极区连接。
  5. 根据权利要求4所述的显示面板，其特征在于，所述第一晶体管的源极区和漏极区的厚度与所述第二电极的厚度不同。
  6. 根据权利要求4所述的显示面板，其特征在于，所述栅极层包括所述第一晶体管的栅极，所述第一晶体管的栅极与所述第一晶体管的沟道区相对设置，所述第一晶体管的栅极与所述第三电极连接。
  7. 根据权利要求1所述的显示面板，其特征在于，所述显示面板包括第二导电层和第二层间介质层，所述第二层间介质层位于所述第一层间介质层远离所述衬底基板的一侧，所述第二导电层位于所述第二层间介质层远离所述衬底基板的一侧，所述第二导电层包括 第五电极，所述第五电极与所述第二电极连接，所述第五电极在所述衬底基板上的正投影与所述第四电极在所述衬底基板上的正投影至少部分重叠以形成第三存储电容。
  8. 根据权利要求7所述的显示面板，其特征在于，所述第五电极在所述衬底基板上的正投影覆盖所述第一电极在所述衬底基板上的正投影。
  9. 根据权利要求7所述的显示面板，其特征在于，所述显示面板包括依次层叠设置的第三层间介质层、第一平坦层和第三导电层，所述第三层间介质层位于所述第二层间介质层远离所述衬底基板的一侧，所述第一平坦层位于所述第三层间介质层远离所述衬底基板的一侧，所述第三导电层与所述第二导电层连接。
  10. 根据权利要求9所述的显示面板，其特征在于，所述显示面板包括阳极层，所述阳极层与所述第三导电层连接。
  11. 根据权利要求1所述的显示面板，其特征在于，所述显示面板包括第二晶体管，所述有源层包括所述第二晶体管的源极区、漏极区和沟道区，所述第一导电层包括第二晶体管的源极，所述第二晶体管的源极分别与第二晶体管的源极区和所述第四电极连接。
  12. 根据权利要求11所述的显示面板，其特征在于，所述栅极层包括所述第二晶体管的栅极，所述第二晶体管的栅极与所述第二晶体管的沟道区相对设置。
  13. 一种显示基板的制造方法，其特征在于，所述制作方法包括以下步骤：
    提供一衬底基板，在所述衬底基板上形成遮光层，所述遮光层包括第一电极；
    在所述遮光层上形成缓冲层，并在所述缓存层上形成有源层，所述有源层包括第二电极，所述第二电极和所述第一电极连接；
    在所述有源层上形成栅极绝缘层，并在所述栅极绝缘层上形成栅极层，所述栅极层包括第三电极，所述第三电极在所述衬底基板上的正投影与第一电极在所述衬底基板上的正投影至少部分重叠以形成第一存储电容；
    在所述栅极层上形成第一层间介质层，并在所述第一层间介质层上形成第一导电层，所述第一导电层包括第四电极，所述第四电极与所述第三电极连接，所述第四电极在所述衬底基板上的正投影与所述第二电极在所述衬底基板上的正投影至少部分重叠以形成第二存储电容。
  14. 一种显示装置，其特征在于，所述显示装置包括如权利要求1-12中任一项所述的显示面板。
PCT/CN2021/125822 2021-02-24 2021-10-22 显示面板及其制作方法和显示装置 WO2022179142A1 (zh)

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