WO2023236770A1 - 像素驱动电路、显示面板及其制备方法、显示装置 - Google Patents

像素驱动电路、显示面板及其制备方法、显示装置 Download PDF

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Publication number
WO2023236770A1
WO2023236770A1 PCT/CN2023/095670 CN2023095670W WO2023236770A1 WO 2023236770 A1 WO2023236770 A1 WO 2023236770A1 CN 2023095670 W CN2023095670 W CN 2023095670W WO 2023236770 A1 WO2023236770 A1 WO 2023236770A1
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Prior art keywords
circuit
transistor
layer
light
gate
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PCT/CN2023/095670
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English (en)
French (fr)
Inventor
李然
田雪雁
田宏伟
孙拓
赵西玉
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京东方科技集团股份有限公司
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Publication of WO2023236770A1 publication Critical patent/WO2023236770A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits

Definitions

  • the present disclosure generally relates to the field of display technology, and in particular, to pixel driving circuits, display panels and preparation methods thereof, and display devices.
  • a small sub-threshold swing ss will cause the display panel to have poor brightness control ability when displaying low grayscale images, resulting in poor display effects.
  • the present disclosure provides a pixel driving circuit, a display panel and a preparation method thereof, and a display device.
  • the technical solutions are as follows:
  • a pixel driving circuit which includes: a light emitting control circuit and a driving circuit;
  • the light-emitting control circuit is respectively coupled to a gate signal terminal, a data signal terminal, a reset signal terminal, an initial power supply terminal and a control terminal of the drive circuit.
  • the light-emitting control circuit is used to provide light based on the gate signal terminal.
  • the gate drive signal, the data signal provided by the data signal terminal, the reset signal provided by the reset signal terminal and the initial power signal provided by the initial power supply terminal control the potential of the control terminal of the drive circuit;
  • the output end of the driving circuit is used to couple with the light-emitting element, and the driving circuit is used to transmit a light-emitting driving signal to the light-emitting element based on the potential of the control end of the driving circuit to drive the light-emitting element to emit light;
  • the driving circuit includes a first driving transistor and a second driving transistor connected in parallel. and, among the first driving transistor and the second driving transistor, the sub-threshold swing of one driving transistor is greater than the sub-threshold swing of the other driving transistor.
  • the gate of the first driving transistor is coupled to the light-emitting control circuit as a control terminal of the driving circuit, and the gate of the second driving transistor is coupled to the gate of the first driving transistor. catch;
  • the sub-threshold swing of the first driving transistor is greater than the sub-threshold swing of the second driving transistor.
  • the lighting control circuit includes: a first reset sub-circuit, a data writing sub-circuit and a compensation control sub-circuit;
  • the first reset sub-circuit is coupled to the reset signal terminal, the initial power supply terminal and the control terminal of the drive circuit respectively.
  • the first reset sub-circuit is used to control the reset signal in response to the reset signal.
  • the data writing sub-circuit is coupled to the gate signal terminal, the data signal terminal and the input terminal of the driving circuit respectively, and the data writing sub-circuit is used to respond to the gate driving signal, Control the connection between the data signal terminal and the input terminal of the driving circuit;
  • the compensation control sub-circuit is coupled to the gate signal terminal, the output terminal of the drive circuit and the control terminal of the drive circuit respectively, and the compensation control sub-circuit is used to respond to the gate drive signal, Control the connection between the output terminal of the driving circuit and the control terminal of the driving circuit.
  • the lighting control circuit also includes: a first lighting control sub-circuit, a second lighting control sub-circuit, a second reset sub-circuit and a storage sub-circuit;
  • the first lighting control sub-circuit is coupled to the lighting control terminal, the driving power terminal and the input terminal of the driving circuit respectively.
  • the first lighting control sub-circuit is used to respond to the lighting control signal provided by the lighting control terminal. , controlling the connection between the driving power terminal and the input terminal of the driving circuit;
  • the second light-emitting control sub-circuit is coupled to the light-emitting control terminal and the output terminal of the driving circuit respectively, and is used to couple with the light-emitting element.
  • the second light-emitting control sub-circuit is used to respond to the The light-emitting control signal controls the connection between the output end of the driving circuit and the light-emitting element;
  • the second reset sub-circuit is coupled to the reset signal terminal and the initial power terminal respectively. is connected and used to couple with the light-emitting element, and the second reset sub-circuit is used to control the connection between the initial power terminal and the light-emitting element in response to the reset signal;
  • the storage sub-circuit is coupled to the driving power terminal and the control terminal of the driving circuit respectively, and the storage sub-circuit is used to store the potential of the control terminal of the driving circuit based on the driving power signal.
  • the first reset sub-circuit includes: a first reset transistor; the second reset sub-circuit includes: a second reset transistor; the data writing sub-circuit includes: a data writing transistor; the compensation control The sub-circuit includes: a compensation transistor; the first light-emitting control sub-circuit includes: a first light-emitting control transistor; the second light-emitting control sub-circuit includes: a second light-emitting control transistor; the storage sub-circuit includes: a storage capacitor;
  • the gate electrode of the first reset transistor and the gate electrode of the second reset transistor are both coupled to the reset signal terminal, and the first electrode of the first reset transistor and the third electrode of the second reset transistor One pole is coupled to the initial power terminal, the second pole of the first reset transistor is coupled to the control node, and the second pole of the second reset transistor is used to couple to the light-emitting element;
  • the gate electrode of the data writing transistor and the gate electrode of the compensation transistor are both coupled to the gate signal terminal, and the first electrode of the data writing transistor is coupled to the data signal terminal.
  • the second pole of the write transistor is coupled to the input node, the first pole of the compensation transistor is coupled to the control node, and the second pole of the compensation transistor is coupled to the output node;
  • the gate of the first light-emitting control transistor and the gate of the second light-emitting control transistor are both coupled to the light-emitting control terminal, and the first electrode of the first light-emitting control transistor is coupled to the driving power terminal.
  • the second pole of the first light-emitting control transistor is coupled to the input node
  • the first pole of the second light-emitting control transistor is coupled to the output node
  • the second pole of the second light-emitting control transistor For coupling with the light-emitting element
  • One end of the storage capacitor is coupled to the driving power terminal, and the other end of the storage capacitor is coupled to the control node;
  • the gate of the first driving transistor is coupled to the control node
  • the gate of the second driving transistor is coupled to the gate of the first driving transistor
  • the first electrode of the first driving transistor is coupled to the control node.
  • the first pole of the second driving transistor is coupled to the input node
  • the second pole of the first driving transistor and the second pole of the second driving transistor are both coupled to the input node.
  • the output node is coupled.
  • each transistor included in the pixel driving circuit is a P-type transistor.
  • a display panel which includes: a substrate, and a plurality of pixels located on one side of the substrate;
  • the pixel includes: a light-emitting element, and a pixel driving circuit as described in the above aspect; the pixel driving circuit is coupled to the light-emitting element, and the pixel driving circuit is used to drive the light-emitting element to emit light.
  • a method for preparing a display panel for preparing the display panel as described in the above aspect; the method includes:
  • the active layer includes: a first active layer pattern and a second active layer pattern spaced apart from each other.
  • the first active layer pattern and the second active layer pattern are spaced apart from each other.
  • one active layer pattern belongs to the first driving transistor in the display panel, and the other active layer pattern belongs to the second driving transistor in the display panel;
  • a gate insulating layer is formed on a side of the active layer away from the substrate, the gate insulating layer covers the active layer, and the gate insulating layer covers the first active layer pattern.
  • the thickness is different from the thickness of the gate insulating layer covering the second active layer pattern.
  • the first active layer pattern belongs to the first driving transistor in the display panel, and the second active layer pattern belongs to the second driving transistor in the display panel;
  • the thickness of the gate insulating layer covering the first active layer pattern is greater than the thickness of the gate insulating layer covering the second active layer pattern.
  • performing plasma treatment on the side of the active layer away from the substrate includes:
  • Forming a gate insulating layer on a side of the active layer away from the substrate includes:
  • a first gate insulating layer is formed on a side of the first active layer pattern away from the substrate, and the first gate insulating layer is formed on a side of the first active layer pattern away from the substrate.
  • a gate insulation layer covers the first active layer pattern;
  • a second gate insulating layer is formed on a side of the second active layer pattern away from the substrate, and the second gate insulating layer covers the second active layer pattern and the first gate Extremely insulating layer.
  • the thickness of the portion of the second gate insulating layer that overlaps with the orthographic projection of the first active layer pattern on the substrate is equal to the thickness of the portion of the second gate insulating layer that overlaps with the orthographic projection of the second active layer pattern on the substrate.
  • the thickness of the orthographic overlap on the substrate is equal to the thickness of the portion of the second gate insulating layer that overlaps with the orthographic projection of the second active layer pattern on the substrate.
  • the method before forming an active layer on one side of the substrate, the method further includes:
  • Forming an active layer on one side of the substrate includes: forming an active layer on a side of the first buffer layer away from the substrate.
  • the method before forming an active layer on the side of the first buffer layer away from the substrate, the method further includes:
  • a second buffer layer is formed on a side of the first gate layer away from the first buffer layer, and the second buffer layer covers the first gate layer;
  • Forming an active layer on a side of the first buffer layer away from the substrate includes: forming an active layer on a side of the second buffer layer away from the substrate.
  • the method further includes:
  • a first interlayer dielectric layer is formed on the side of the second gate layer away from the second gate insulating layer, and the first interlayer dielectric layer covers the second gate layer;
  • a second interlayer dielectric layer is formed on the side of the third gate layer away from the first interlayer dielectric layer, and the second interlayer dielectric layer covers the third gate layer;
  • a source-drain layer is formed on a side of the second interlayer dielectric layer away from the third gate layer.
  • the source-drain layer passes through the second interlayer dielectric layer and the first interlayer dielectric layer. layer and a via hole of the gate insulating layer coupled to the active layer;
  • An anode layer is formed on a side of the flat layer away from the source and drain layer, and the anode layer is coupled to the source and drain layer through a via hole penetrating the flat layer;
  • a pixel defining layer is formed on a side of the anode layer away from the flat layer, and the pixel defining layer covers the flat layer and partially exposes the anode layer.
  • a display device which includes: a power supply component, and the display panel as described in the above aspect;
  • the power supply component is coupled to the display panel, and the power supply component is used to power the display panel.
  • Figure 1 is a schematic structural diagram of a pixel driving circuit provided by an embodiment of the present disclosure
  • Figure 2 is a schematic structural diagram of another pixel driving circuit provided by an embodiment of the present disclosure.
  • Figure 3 is a schematic diagram of IV characteristics of a driving circuit provided by an embodiment of the present disclosure.
  • Figure 4 is a schematic structural diagram of yet another pixel driving circuit provided by an embodiment of the present disclosure.
  • Figure 5 is a schematic structural diagram of a display panel provided by an embodiment of the present disclosure.
  • Figure 6 is a flow chart of a method for manufacturing a display panel provided by an embodiment of the present disclosure
  • Figure 7 is a cross-sectional view of a display panel provided by an embodiment of the present disclosure.
  • Figure 8 is a cross-sectional view of another display panel provided by an embodiment of the present disclosure.
  • Figure 9 is a top view of a display panel provided by an embodiment of the present disclosure.
  • Figure 10 is a cross-sectional view of another display panel provided by an embodiment of the present disclosure.
  • Figure 11 is a cross-sectional view of yet another display panel provided by an embodiment of the present disclosure.
  • Figure 12 is a cross-sectional view of yet another display panel provided by an embodiment of the present disclosure.
  • Figure 13 is a cross-sectional view of yet another display panel provided by an embodiment of the present disclosure.
  • Figure 14 is a cross-sectional view of yet another display panel provided by an embodiment of the present disclosure.
  • FIG. 15 is a schematic structural diagram of a display device provided by an embodiment of the present disclosure.
  • the transistors used in all embodiments of the present disclosure can be thin film transistors, field effect transistors, or other devices with the same characteristics.
  • the transistors used in the embodiments of the present disclosure are mainly switching transistors according to their functions in the circuit. Since the source and drain of the switching transistor used here are symmetrical, their source and drain are interchangeable. In the embodiment of the present disclosure, the source electrode is called the first electrode and the drain electrode is called the second electrode.
  • the middle end of the transistor is the control electrode, which can also be called the gate
  • the signal input end is the source
  • the signal output end is the drain.
  • the switching transistor used in the embodiment of the present disclosure may include any one of a P-type switching transistor and an N-type switching transistor, wherein the P-type switching transistor is turned on when the gate is at a low level, and is turned off when the gate is at a high level. (That is, for a P-type transistor, it is turned on when the potential of the signal received by the gate is low, and turned off when the potential of the signal received by the gate is high. That is, the low potential is the effective potential, and the high potential is invalid.
  • the N-type switching transistor is turned on when the gate is at a high level, and is turned off when the gate is at a low level (i.e., for an N-type transistor, it is turned on when the potential of the signal received by the gate is high, and the gate receives It is turned off when the potential of the received signal is low, that is, the high potential is the effective potential and the low potential is the invalid potential).
  • FIG. 1 is a schematic structural diagram of a pixel driving circuit provided by an embodiment of the present disclosure. As shown in Figure 1, the pixel driving circuit includes: a light emitting control circuit 01 and a driving circuit 02.
  • the light-emitting control circuit 01 is coupled to the gate signal terminal Gate, the data signal terminal V Data , the reset signal terminal Reset, the initial power supply terminal Vinit and the control terminal of the drive circuit 02 respectively.
  • the lighting control circuit 01 is used to control the drive based on the gate drive signal provided by the gate signal terminal Gate, the data signal provided by the data signal terminal V Data , the reset signal provided by the reset signal terminal Reset, and the initial power signal provided by the initial power supply terminal Vinit.
  • the output terminal of the driving circuit 02 is used to couple with the light-emitting element L1.
  • a light-emitting driving signal eg, a driving current
  • a driving current is transmitted to the light-emitting element L1 to drive the light-emitting element L1 to emit light.
  • the driving circuit 02 may be coupled to the first pole of the light-emitting element L1, and the second pole of the light-emitting element L1 may also be coupled to the pull-down power supply terminal V SS .
  • the light-emitting element L1 can emit light under the action of the voltage difference between the light-emitting driving signal received by the first pole and the pull-down power signal provided by the pull-down power terminal V SS received by the second pole.
  • the first electrode of the light-emitting element L1 may be an anode, and the second electrode may be a cathode.
  • the first electrode of the light-emitting element L1 may be a cathode, and correspondingly, the second electrode of the light-emitting element L1 may be an anode.
  • the driving circuit 02 includes a first driving transistor T3-1 and a second driving transistor T3-2 connected in parallel.
  • the performance of the two drive transistors can be neutralized, and the parallel connection of the two can improve the device sub-threshold swing ss while maintaining the device mobility.
  • the sub-threshold swing ss of one driving transistor is greater than the sub-threshold swing ss of the other driving transistor. Since the sub-threshold swing ss of the transistor is inversely proportional to the mobility, that is, the larger the sub-threshold swing ss of the transistor, the smaller the mobility; conversely, the smaller the sub-threshold swing ss of the transistor, the greater the mobility.
  • the mobility of one driving transistor can be made greater than the mobility of the other driving transistor, that is, the mobility of one driving transistor can be made mobility is smaller, the mobility of the other driver transistor is larger.
  • the sub-threshold swing ss of the two driving transistors can be further neutralized, so that the device sub-threshold swing ss can be improved while maintaining the device mobility.
  • embodiments of the present disclosure provide a pixel driving circuit, because the driving circuit includes two parallel driving transistors, and the sub-threshold swing of one driving transistor is greater than the sub-threshold swing of the other driving transistor. , so the sub-threshold swings of the two driving transistors can be neutralized, so that the device sub-threshold swing can be improved while maintaining the device mobility, ensuring that the display effect of the display panel can be better.
  • the gate of the first driving transistor T3-1 can As the control terminal of the driving circuit 02 is coupled to the light emitting control circuit 01, the gate of the second driving transistor T3-2 may be coupled with the gate of the first driving transistor T3-1.
  • the sub-threshold swing ss of the first driving transistor T3-1 may be greater than the sub-threshold swing ss of the second driving transistor T3-2. That is to say, in the embodiment of the present disclosure, among the two driving transistors connected in parallel, the driving transistor whose gate is directly coupled to the light-emitting control circuit 01 has a larger sub-threshold swing ss and a smaller mobility; while the other one has a larger sub-threshold swing ss and a smaller mobility. A drive transistor has a smaller subthreshold swing ss and a larger mobility.
  • Figure 3 shows a schematic diagram of the IV characteristic curve of a driving transistor, in which the abscissa refers to the voltage V and the ordinate refers to the current I. Moreover, FIG. 3 shows the IV characteristic curve of the first driving transistor T3-1 and the IV characteristic curve of the second driving transistor T3-2, as well as the parallel connection of the first driving transistor T3-1 and the second driving transistor T3-2. The final IV characteristic curve is labeled T3-sum. Referring to Figure 3, it can be clearly seen that after the first driving transistor T3-1 and the second driving transistor T3-2 are connected in parallel, the IV characteristics can be improved, and the first driving transistor T3-1 and the second driving transistor T3 can be neutralized. The sub-threshold swing ss of -2 reliably improves the sub-threshold swing ss of the driving circuit 02.
  • the light emission control circuit 01 recorded in the embodiment of the present disclosure may include: a first reset sub-circuit 011, a data writing sub-circuit 012 and compensation control subcircuit 013.
  • the first reset sub-circuit 011 can be coupled to the reset signal terminal Reset, the initial power terminal Vinit and the control terminal of the drive circuit 02 respectively.
  • the first reset sub-circuit 011 is used to control the initial power terminal Vinit and the drive circuit 02 in response to the reset signal.
  • the control terminal of circuit 02 is on and off.
  • the first reset sub-circuit 011 can control the initial power terminal Vinit to be connected to the control terminal of the drive circuit 02 when the potential of the reset signal is the first potential, so that the initial power terminal Vinit transmits initial power to the control terminal of the drive circuit 02 Signal. Moreover, the first reset sub-circuit 011 can control the initial power terminal Vinit to disconnect from the control terminal of the driving circuit 02 when the potential of the reset signal is the second potential.
  • the first potential may be an effective potential
  • the second potential may be an ineffective potential
  • the first potential may be a low potential relative to the second potential.
  • the first potential may also be a higher potential than the second potential.
  • the data writing sub-circuit 012 can be connected to the gate signal terminal Gate and the data signal terminal respectively.
  • V Data is coupled to the input terminal of the drive circuit 02.
  • the data writing sub-circuit 012 may be used to control the connection between the data signal terminal V Data and the input terminal of the driving circuit 02 in response to the gate driving signal.
  • the data writing sub-circuit 012 can control the data signal terminal V Data to be connected to the input terminal of the driving circuit 02 when the potential of the gate driving signal is the first potential, so that the data signal terminal V Data is connected to the input terminal of the driving circuit 02 end transmits data signals. Furthermore, the data writing sub-circuit 012 may control the data signal terminal V Data to be disconnected from the input terminal of the driving circuit 02 when the potential of the gate driving signal is the second potential.
  • the compensation control sub-circuit 013 may be coupled to the gate signal terminal Gate, the output terminal of the driving circuit 02 and the control terminal of the driving circuit 02 respectively.
  • the compensation control subcircuit 013 may be used to control the connection between the output terminal of the driving circuit 02 and the control terminal of the driving circuit 02 in response to the gate driving signal.
  • the compensation control sub-circuit 013 can control the output terminal of the driving circuit 02 to be conductive with the control terminal of the driving circuit 02 when the potential of the gate driving signal is the first potential. Furthermore, the compensation control sub-circuit 013 can control the output end of the drive circuit 02 to be disconnected from the control end of the drive circuit 02 when the potential of the gate drive signal is the second potential.
  • the lighting control circuit 01 recorded in the embodiment of the present disclosure may also include: a first lighting control sub-circuit 014, a second lighting control sub-circuit 015, a second reset sub-circuit 016 and a storage Subcircuit 017.
  • the first lighting control sub-circuit 014 may be coupled to the lighting control terminal EM, the driving power terminal V DD and the input terminal of the driving circuit 02 respectively.
  • the first lighting control sub-circuit 014 may be used to control the connection between the driving power terminal VDD and the input terminal of the driving circuit 02 in response to the lighting control signal provided by the lighting control terminal EM.
  • the first lighting control sub-circuit 014 can control the driving power terminal V DD to be connected to the input terminal of the driving circuit 02 when the potential of the lighting control signal provided by the lighting control terminal EM is the first potential, so that the driving power terminal V DD The drive power signal is transmitted to the input terminal of the drive circuit 02.
  • the first lighting control sub-circuit 014 can control the driving power terminal V DD to disconnect from the input terminal of the driving circuit 02 when the potential of the lighting control signal provided by the lighting control terminal EM is the second potential.
  • the second lighting control sub-circuit 015 can be connected to the lighting control terminal EM and the driving circuit respectively.
  • the output end of 02 is coupled and can be used to couple with the light-emitting element L1.
  • the second light-emitting control sub-circuit 015 may be used to control the connection between the output end of the driving circuit 02 and the light-emitting element L1 in response to the light-emitting control signal.
  • the second light-emitting control sub-circuit 015 can control the output end of the driving circuit 02 to conduct with the light-emitting element L1 when the potential of the light-emitting control signal is the first potential, so that the signal transmitted to the output end of the driving circuit 02 can be further transmitted to Light emitting element L1. And, the second light-emitting control sub-circuit 015 can control the output end of the driving circuit 02 to be disconnected from the light-emitting element L1 when the potential of the light-emitting control signal is the second potential.
  • the second reset sub-circuit 016 can be coupled to the reset signal terminal Reset and the initial power terminal Vinit respectively, and can be used to couple with the light-emitting element L1.
  • the second reset sub-circuit 016 may be used to control the connection between the initial power terminal Vinit and the light-emitting element L1 in response to the reset signal.
  • the second reset sub-circuit 016 can control the initial power terminal Vinit to conduct with the light-emitting element L1 when the potential of the reset signal is the first potential, so that the initial power terminal Vinit transmits the initial power signal to the light-emitting element L1. Moreover, the second reset sub-circuit 016 can control the initial power terminal Vinit to disconnect from the light-emitting element L1 when the potential of the reset signal is the second potential.
  • the storage sub-circuit 017 may be coupled to the driving power terminal V DD and the control terminal of the driving circuit 02 respectively.
  • the storage sub-circuit 017 may be used to store the potential of the control terminal of the driving circuit 02 based on the driving power signal.
  • the first reset sub-circuit 011 can be used to provide the initial power signal provided by the initial power terminal Vinit to the control terminal of the driving circuit 02 under the control of the reset signal terminal Reset, so as to control the driving circuit 02 The control end is reset.
  • the second reset sub-circuit 016 can be used to provide the initial power signal provided by the initial power terminal Vinit to the anode of the light-emitting element L1 under the control of the reset signal terminal Reset, so as to reset the anode of the light-emitting element L1.
  • the data writing sub-circuit 012 may be used to provide the data signal provided by the data signal terminal V Data to the input terminal of the driving module 02 under the control of the gate signal terminal Gate.
  • the compensation control subcircuit 013 may be used to adjust the potential of the control terminal of the driving module 02 based on the potential of the output terminal of the driving module 02 under the control of the gate signal terminal Gate.
  • the first lighting control sub-circuit 014 may be used to transmit the driving power signal provided by the driving power terminal VDD to the driving circuit 02 under the control of the lighting control terminal EM.
  • the voltage at the output terminal of the driving circuit 02 is provided to the light-emitting element L1 under the control of the light-emitting control terminal EM.
  • the driving circuit 02 can be used to drive the light-emitting element L1 to emit light under the control of a signal from the control terminal (eg, a signal transmitted by the first reset sub-circuit 011).
  • the first reset sub-circuit 011 may include: a first reset transistor T1.
  • the second reset sub-circuit 016 may include a second reset transistor T7.
  • the data writing sub-circuit 012 may include a data writing transistor T4.
  • the compensation control sub-circuit 013 may include a compensation transistor T2.
  • the first lighting control sub-circuit 014 may include: a first lighting control transistor T5.
  • the second light emission control sub-circuit 015 may include: a second light emission control transistor T6.
  • the storage sub-circuit 017 may include: a storage capacitor Cst.
  • the gate electrode of the first reset transistor T1 and the gate electrode of the second reset transistor T7 can both be coupled to the reset signal terminal Reset, and the first electrode of the first reset transistor T1 and the first electrode of the second reset transistor T7 can both be coupled.
  • the second pole of the first reset transistor T1 may be coupled with the control node N1
  • the second pole of the second reset transistor T7 may be coupled with the light emitting element L1.
  • the initial power signal can be transmitted to the control node N1 through the first reset transistor T1
  • the initial power signal can be transmitted to the anode of the light-emitting element L1 through the second reset transistor T7.
  • the gate of the data writing transistor T4 and the gate of the compensation transistor T2 may both be coupled to the gate signal terminal Gate.
  • the first electrode of the data writing transistor T4 may be coupled to the data signal terminal V Data .
  • the data writing transistor T4 The second pole of the compensation transistor T2 may be coupled to the input node N2, the first pole of the compensation transistor T2 may be coupled to the control node N1 (ie, the coupling point of the first reset sub-circuit 011 and the driving circuit 02), and the second pole of the compensation transistor T2 Pole may be coupled to output node N3.
  • the data signal can be written into the input terminal of the driving circuit 02 through the data writing transistor T4, and then the data signal can be written into the control terminal of the driving circuit 02 through the compensation transistor T2.
  • the gate of the first light-emitting control transistor T5 and the gate of the second light-emitting control transistor T6 may both be coupled to the light-emitting control terminal EM, and the first electrode of the first light-emitting control transistor T5 may be coupled to the driving power terminal V DD .
  • a second pole of a light-emitting control transistor T5 may be coupled to the input node N2, a first pole of a second light-emitting control transistor T6 may be coupled to the output node N3, and a second pole of the second light-emitting control transistor T6 may be used to communicate with the light emitting device.
  • Component L1 coupling For example, coupled to the anode of the light-emitting element L1.
  • the driving power signal provided by the driving power terminal V DD can be transmitted to the input terminal of the driving circuit 02 through the first light-emitting control transistor T5, and the signal at the output terminal of the driving circuit 02 can be transmitted through the second light-emitting control transistor T6. transmitted to the light-emitting element L1.
  • One end of the storage capacitor Cst may be coupled to the driving power terminal V DD , and the other end of the storage capacitor Cst may be coupled to the control node N1 (ie, the coupling point of the first reset sub-circuit 011 and the driving circuit 02).
  • the gate of the first driving transistor T3-1 may be coupled to the control node N1, and the gate of the second driving transistor T3-2 may be coupled to the gate of the first driving transistor T3-1.
  • the first driving transistor T3-1 The first pole of the first drive transistor T3-1 and the first pole of the second drive transistor T3-2 may both be coupled to the input node N2, and the second pole of the first drive transistor T3-1 and the second pole of the second drive transistor T3-2 may both be coupled. coupled to output node N3. It can be seen from this that the control terminal of the driving circuit 02 is the control node N1, the input terminal is the input node N2, and the output terminal is the output node N3.
  • each transistor included in the pixel driving circuit described in the embodiment of the present disclosure may be a P-type transistor.
  • the first potential (ie, effective potential) described in the above embodiments may be a low potential
  • the second potential (ie, ineffective potential) may be a high potential.
  • the light-emitting element L1 shown in FIG. 3 is an OLED.
  • the first reset sub-circuit 011 can be implemented by the first reset transistor T1; the second reset sub-circuit 016 can be implemented by the second reset transistor T7; data writing The sub-circuit 012 can be implemented by the data writing transistor T4; the compensation control sub-circuit 013 can be implemented by the compensation transistor T2; the first lighting control sub-circuit 014 can be implemented by the first lighting control transistor T5; the second lighting control sub-circuit 015 can be implemented by The second light emitting control transistor T6 is implemented; the storage sub-circuit 017 can be implemented by the storage capacitor Cst.
  • the driving circuit 02 may be implemented by a first driving transistor T3-1 and a second driving transistor T3-2 connected in parallel. And, the gate electrode of the first driving transistor T3-1 and the gate electrode of the second driving transistor T3-2 may both be coupled to the first reset sub-circuit 011. The first pole of the first driving transistor T3-1 and the first pole of the second driving transistor T3-2 may both be coupled to the first lighting control sub-circuit 014.
  • the pixel driving circuit shown in Figure 3 can be considered an 8T1C (i.e., including 8 transistors and 1 capacitor) structure.
  • the pixel driving circuit may also have other structures, such as a 6T2C structure, provided that the driving circuit 02 includes two driving transistors connected in parallel as shown in FIG. 3 .
  • embodiments of the present disclosure provide a pixel driving circuit, because the driving circuit includes two parallel driving transistors, and the sub-threshold swing of one driving transistor is greater than the sub-threshold swing of the other driving transistor. , so the sub-threshold swings of the two driving transistors can be neutralized, so that the device sub-threshold swing can be improved while maintaining the device mobility, ensuring that the display effect of the display panel can be better.
  • an embodiment of the disclosure also provides a display panel.
  • the display panel provided by the embodiment of the disclosure includes a substrate 10 and a plurality of pixels P1 located on one side of the substrate 10 .
  • Each pixel P1 includes: a light-emitting element L1, and the pixel driving circuit 00 described in the above embodiment.
  • the pixel driving circuit 00 is coupled to the light emitting element L1.
  • the pixel driving circuit 00 is used to drive the light-emitting element L1 to emit light.
  • the display panel protected by the embodiments of the present disclosure uses the above-mentioned pixel driving circuit.
  • the principle of solving the problem is similar to the pixel driving circuit mentioned above. Please refer to the previous embodiments of the pixel driving circuit and will not go into details.
  • embodiments of the present disclosure also provide a display panel preparation method for preparing the display panel as described in the above embodiments.
  • the preparation method recorded in the embodiment of the present disclosure includes the following steps:
  • Step 601 Provide a substrate.
  • FIG. 7 and FIG. 8 respectively show cross-sectional views of the two display panels at the driving circuit 02 . They each show a substrate 10 as provided.
  • the substrate 10 here may be a glass substrate.
  • the substrate 10 may also be a flexible substrate.
  • Step 602 Form an active layer on one side of the substrate, and the formed active layer includes: a first active layer pattern and a second active layer pattern spaced apart from each other.
  • the active layer 20 may be formed on one side of the substrate 10 through a sputtering process.
  • Figure 9 shows a top view of a display panel Figure, in which the active layer 20 formed on one side of the substrate 10 can also be seen.
  • the material of the active layer 20 may include: indium gallium zinc oxide (IGZO), indium zinc oxide (indium zinc oxide, IZO), indium gallium oxide (indium gallium oxide, IGO), Metal oxides such as indium tin zinc oxide (ITZO) or gallium tin oxide (zinc tin oxide, ZTO).
  • IGZO indium gallium zinc oxide
  • IZO indium zinc oxide
  • IGO indium gallium oxide
  • Metal oxides such as indium tin zinc oxide (ITZO) or gallium tin oxide (zinc tin oxide, ZTO).
  • one active layer pattern may belong to the first driving transistor in the display panel (ie, T3- shown in FIG. 3 1)
  • another active layer pattern may belong to the second driving transistor in the display panel (ie, T3-2 shown in FIG. 3). That is, the active layer 20 is formed including the active layer pattern of the first driving transistor T3-1 and the active layer pattern of the second driving transistor T3-2.
  • Step 603 Form a first gate insulating layer on a side of the first active layer pattern away from the substrate, and the formed first gate insulating layer covers the first active layer pattern.
  • the first gate insulating layer 30 may be deposited using a chemical vapor deposition method.
  • photolithography also called patterning process
  • the patterning process includes steps such as exposure, development, and etching.
  • the formed first gate insulating layer 30 can be provided to cover the first active layer pattern 201, and the gate insulating layer at the first active layer pattern 20 can be thickened to form a gate with a larger sub-threshold swing ss.
  • First drive transistor T3-1 First drive transistor T3-1.
  • the material of the first gate insulating layer 30 may include: silicon dioxide SiO 2 , aluminum oxide Al 2 O 3 , hafnium dioxide HfO 2 , zirconium dioxide ZrO 2 , titanium oxide TiOx or silicon nitride SiNx.
  • Step 604 Perform plasma treatment on the surface of the second active layer pattern away from the substrate.
  • nitrogen dioxide N 2 O or oxygen O 2 plasma treatment can be performed on the surface of the second active layer pattern 202 away from the substrate 10 , so that the threshold voltage Vth of the transistor in this area is positive. Partial.
  • Step 605 Form a second gate insulating layer on a side of the second active layer pattern away from the substrate, and the formed second gate insulating layer covers the second active layer pattern and the first gate insulating layer.
  • the chemical vapor deposition method can be used to deposit the second gate insulating layer 40 .
  • the material of the second gate insulating layer 40 can also include silicon dioxide as described in the above embodiment. SiO 2 , aluminum oxide Al 2 O 3 , hafnium dioxide HfO 2 , zirconium dioxide ZrO 2 , titanium oxide TiOx or silicon nitride SiNx, and the second gate insulating layer 40 is formed to cover the first gate insulating layer 30 and the second active layer pattern 202 is provided.
  • the thickness of the gate insulating layer 30 covering the first active layer pattern 201 can be greater than the thickness of the gate insulating layer 30 covering the second active layer pattern 202 . That is, the thickness of the gate insulating layer 30 covering the first active layer pattern 201 and the thickness of the gate insulating layer 30 covering the second active layer pattern 202 are different, and the thickness of the gate insulating layer above the two active layer patterns is different. The thickness is not the same.
  • the thinner the thickness of the gate insulating layer the larger the capacitance of the formed transistor, and the stronger the gate electric field. Therefore, two driving transistors can be formed, one with a larger sub-threshold swing ss and one with a smaller sub-threshold swing ss. That is, the sub-threshold swing ss of the first driving transistor T3-1 and the sub-threshold swing ss of the second driving transistor T3-2 shown in FIG. 2 may be made different.
  • the sub-threshold swing ss of one of the first driving transistor T3-1 and the second driving transistor T3-2 can be made larger than the sub-threshold swing ss of the other driving transistor.
  • the first gate insulating layer 30 and the second gate insulating layer 40 back and forth as described above, two driving transistors connected in parallel can be prepared.
  • a gate insulating layer needs to be set to cover the active layer 20, so that the two drive transistors prepared can not only be connected in parallel, but also have Different subthreshold swings ss.
  • Use in parallel can neutralize the performance of the two, reduce the sub-threshold swing ss of the drive transistor of the drive circuit, and improve the brightness control capability of the display panel when displaying low grayscale images without reducing mobility. It can be known from the description of the above embodiments that driving transistors with different sub-threshold swings ss can be realized through gate insulating layers of different thicknesses.
  • the first active layer pattern 201 may belong to the first driving transistor T3-1 in the display panel
  • the second active layer pattern 202 may belong to the second driving transistor T3 in the display panel. -2.
  • the sub-threshold swing ss of the first driving transistor T3-1 can be made larger than the sub-threshold swing ss of the second driving transistor T3-2. That is, the gate of the two drive transistors connected in parallel can be directly coupled to the light-emitting control circuit.
  • the driving transistor has a larger sub-threshold swing ss and a smaller mobility; while the other driving transistor has a smaller sub-threshold swing ss and has a larger mobility. Thereby better improving the sub-threshold swing.
  • the first active layer pattern 201 is formed on the substrate 10
  • the thickness of the orthographic overlap portion may be equal to the thickness of the orthographic overlap portion of the second active layer pattern 202 on the substrate 10 .
  • the thickness of the second gate insulating layer 40 located at the first active layer pattern 201 may be the same as the thickness located at the second active layer pattern 202 . In this way, the structure of two parallel driving transistors can be ensured to be reliably formed.
  • the preparation method may also include:
  • a flexible material layer 50 is formed on one side of the substrate 10 .
  • the flexible material may include polyimide (PI).
  • PI polyimide
  • the flexible material layer 50 may also be called a PI layer.
  • a first buffer layer 60 is formed on a side of the flexible material layer 50 away from the substrate 10 .
  • the material of the first buffer layer 60 may include: silicon dioxide SiO 2 , silicon nitride SiNx, or silicon oxynitride SiON.
  • forming the active layer 20 on one side of the substrate 10 may include: forming the active layer 20 on a side of the first buffer layer 60 away from the substrate 10 .
  • the preparation method may also include:
  • a first gate layer 70 is formed on a side of the first buffer layer 60 away from the substrate 10 .
  • a second buffer layer 80 is formed on a side of the first gate layer 70 away from the first buffer layer 60 , and the formed second buffer layer 80 covers the first gate layer 70 . That is, the second buffer layer 80 is provided to cover the first gate layer 70 .
  • the first gate layer 70 and the second buffer layer 80 may be sequentially deposited on the side of the first buffer layer 60 away from the substrate 10 .
  • the material of the first gate layer 70 may include: molybdenum Mo, titanium Ti, aluminum Al, Metals such as copper Cu, indium tin oxide ITO, silver Ag and their alloys can be patterned using photolithography.
  • the material of the second buffer layer 80 may include: silicon dioxide SiO 2 , aluminum oxide Al 2 O 3 , hafnium dioxide HfO 2 , zirconium dioxide ZrO 2 , titanium oxide TiOx or silicon nitride SiNx.
  • the display panel described in the embodiment of the present disclosure provides two embodiments of FIG. 7 and FIG. 8 .
  • the structure shown in Figure 8 is a double-gate transistor structure.
  • Gate layer 70 a second buffer layer 80 may be deposited on the first gate layer 70 using a chemical vapor deposition method.
  • the second buffer layer 80 may be disposed covering the first gate layer 70 and the exposed first buffer layer 60 .
  • forming the active layer 20 on a side of the first buffer layer 60 away from the substrate 10 may include: forming the active layer 20 on a side of the second buffer layer 80 away from the substrate 10 .
  • the preparation method may also include:
  • the second gate layer 90 is formed on a side of the second gate insulating layer 40 away from the substrate 10 . That is, the second gate layer 90 is provided on the second gate insulating layer 40 .
  • a first interlayer dielectric layer 100 is formed on a side of the second gate layer 90 away from the second gate insulating layer 40 , and the formed first interlayer dielectric layer 100 covers the second gate layer 90 . That is, the first interlayer dielectric layer 100 is provided on the second gate electrode layer 90 , and the first interlayer dielectric layer 100 is provided to cover the second gate electrode layer 90 .
  • the third gate layer 101 is formed on a side of the first interlayer dielectric layer 100 away from the second gate layer 90 . That is, the third gate layer 101 is provided on the first interlayer dielectric layer 100 .
  • a second interlayer dielectric layer 102 is formed on a side of the third gate layer 101 away from the first interlayer dielectric layer 100 , and the formed second interlayer dielectric layer 102 covers the third gate electrode layer 101 . That is, the second interlayer dielectric layer 102 is provided on the third gate electrode layer 101, and the second interlayer dielectric layer 102 is provided to cover the third gate electrode layer 101.
  • a source-drain layer 103 is formed on the side of the second interlayer dielectric layer 102 away from the third gate layer 101 , and the formed source-drain layer 103 passes through the second interlayer dielectric layer 102 and the first interlayer dielectric layer 100 , the via hole K1 of the second gate insulating layer 40 and the first gate insulating layer 30 has Source layer 20 is coupled. That is, the source-drain layer 103 is formed on the second interlayer dielectric layer 102, and the source-drain layer 103 is connected to the active layer 20 through the hole K1.
  • a flat layer 104 is formed on the side of the source and drain layer 103 away from the second interlayer dielectric layer 102 . That is, the source and drain layer 103 is covered with the planarization layer 104 .
  • An anode layer 105 is formed on a side of the flat layer 104 away from the source and drain layer 103 , and the formed anode layer 105 is coupled to the source and drain layer 103 through a via K2 that penetrates the flat layer 104 . That is, the anode layer 105 is deposited on the flat layer 104, and the anode layer 105 is connected to the source and drain layer 103 through the hole K2.
  • the pixel defining layer 106 is formed on one side of the flat layer 104, and the formed pixel defining layer 106 covers the flat layer 104 and partially exposes the anode layer 105.
  • the pixel defining layer 106 may be an organic film layer.
  • it may refer to forming an organic film layer that covers the flat layer 104 and partially exposes the anode layer 105 .
  • the second gate insulating layer 40 is formed, and the two driving transistors are formed, and then the second gate layer 90 is set on the second gate insulating layer 40.
  • the second gate layer 90 may refer to the first gate layer, and the material of the second gate layer may also include: molybdenum Mo, titanium Ti, aluminum Al, copper Cu, indium tin oxide ITO and silver. Metals such as Ag and their alloys are patterned using photolithography to form a structure as shown in Figure 11.
  • the first interlayer dielectric layer 100 may then be deposited using a chemical vapor deposition method.
  • the first interlayer dielectric layer 100 covers the second gate layer 90 , and the material of the first interlayer dielectric layer 100 may include: silicon dioxide. SiO 2 , aluminum oxide Al 2 O 3 , hafnium dioxide HfO 2 , zirconium dioxide ZrO 2 , titanium oxide TiOx or silicon nitride SiNx.
  • a third gate layer 101 may be formed on the first interlayer dielectric layer 100.
  • the material of the third gate layer 101 may also include: molybdenum Mo, titanium Ti, aluminum Al, copper Cu, indium tin oxide ITO and silver.
  • Metals such as Ag and their alloys are patterned using photolithography to form a structure as shown in Figure 12.
  • the second interlayer dielectric layer 102 can be deposited using a chemical vapor deposition method.
  • the material of the second interlayer dielectric layer 102 can also include: silicon dioxide SiO 2 , aluminum oxide Al 2 O 3 , hafnium dioxide HfO 2 , Zirconium oxide ZrO 2 , titanium oxide TiOx or silicon nitride SiNx.
  • the first interlayer dielectric layer 100 and the second interlayer dielectric layer 102, as well as the first gate insulating layer 30 and the second The gate insulating layer 40 is provided with via holes, through which the corresponding active layer pattern can be exposed, forming a structure as shown in FIG. 13 .
  • a source-drain layer 103 may be sputtered and deposited on the second interlayer dielectric layer 102.
  • the material of the source-drain layer 103 may also include: molybdenum Mo, titanium Ti, aluminum Al, copper Cu, indium tin oxide ITO and silver. Metals such as Ag and their alloys are patterned using photolithography.
  • the source and drain layer 103 is also connected to the corresponding active layer 20 through the above-mentioned via holes, forming a structure as shown in FIG. 14 .
  • the planarization layer 104 may then be prepared and patterned using photolithography.
  • an anode layer 105 can be sputtered and deposited on the flat layer 104.
  • the material of the anode layer 105 can also include: molybdenum Mo, titanium Ti, aluminum Al, copper Cu, indium tin oxide ITO, silver Ag and other metals and their alloys, and Using photolithography for patterning, the anode layer 105 can be connected to the above-mentioned source and drain layer 103 through via holes provided on the flat layer 104 .
  • an organic film layer ie, the pixel defining layer 106
  • the organic film layer exposes part of the anode layer.
  • the display panel provided in the above steps has two drive transistors connected in parallel, and one drive transistor has a larger sub-threshold swing ss, and the other drive transistor has a smaller sub-threshold swing ss.
  • the sub-threshold swing ss can be reduced by connecting the two structures in parallel. Swing ss for neutralization.
  • the gate insulating layers of different thicknesses are divided into two parts to prepare. After the first gate insulating layer is prepared, when the surface is treated with plasma, a part of the active layer is processed.
  • embodiments of the present disclosure provide a method for manufacturing a display panel.
  • the thickness of the gate insulating layer on one side of the active layer pattern belonging to the first driving transistor is different from that on the side of the active layer pattern belonging to the second driving transistor.
  • the gate insulating layer on one side of the active layer pattern of the driving transistor has different thicknesses.
  • the sub-threshold swing of one driving transistor can be greater than the sub-threshold swing of the other driving transistor, thereby making the sub-threshold swing of the two driving transistors
  • the swing is neutralized, and the sub-threshold swing of the device is increased while maintaining the device mobility, ensuring that the display effect of the display panel can be better.
  • the display device includes: a power supply component J1, and a display panel as shown in Figure 5 M1.
  • the power supply component J1 is coupled to the display panel M1 and used to power the display panel M1.
  • the display device may include: a monitor, a mobile phone, a television, a notebook computer and/or a navigator, etc.
  • Other essential components of the display device should be understood by those of ordinary skill in the art. Understand what you have and won’t go into details.
  • first and second are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of indicated technical features. Therefore, features defined as “first” and “second” may explicitly or implicitly include one or more of these features.
  • spatially relative terms can be used here, such as “on", “on", “on the upper surface of", “above”, etc., to describe what is shown in the figure.
  • the exemplary term “over” may include both orientations “above” and “below.”
  • the device may be otherwise oriented, rotated 90 degrees or at other orientations and the spatially relative descriptors used herein interpreted accordingly.

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Abstract

提供了一种像素驱动电路、显示面板及其制备方法、显示装置。像素驱动电路包括发光控制电路（01）和驱动电路（02），发光控制电路（01）可以在所耦接的信号端的控制下，控制驱动电路（02）的控制端的电位，驱动电路（02）可以基于其控制端的电位，驱动耦接的发光元件（L1）发光。并且，驱动电路（02）包括并联的两个驱动晶体管（T3-1，T3-2），该两个驱动晶体管（T3-1，T3-2）的亚阈值摆幅不同。如此，可以使得该两个驱动晶体管（T3-1，T3-2）的性能进行中和，进而使得在保持晶体管的迁移率的同时提升晶体管的亚阈值摆幅，确保亮度控制稳定性较好，进而确保了显示面板的显示效果可以较好。

Description

像素驱动电路、显示面板及其制备方法、显示装置
本公开要求于2022年6月9日提交的申请号为202210649930.4、发明名称为“像素驱动电路、显示面板及其制备方法、显示装置”的中国专利申请的优先权，其全部内容通过引用结合在本公开中。
技术领域
本公开一般涉及显示技术领域，尤其涉及像素驱动电路、显示面板及其制备方法、显示装置。
背景技术
氧化物晶体管在作为有机发光二极管(organic light-emitting diode，OLED)显示面板中的驱动晶体管应用时，存在亚阈值摆幅(subthreshold swing，ss)较小的问题。亚阈值摆幅ss较小会使得显示面板在显示低灰阶画面时亮度控制能力变差，造成显示效果较差。
发明内容
本公开提供了一种像素驱动电路、显示面板及其制备方法、显示装置。所述技术方案如下：
一方面，提供一种像素驱动电路，所述像素驱动电路包括：发光控制电路和驱动电路；
所述发光控制电路分别与栅极信号端、数据信号端、复位信号端、初始电源端和所述驱动电路的控制端耦接，所述发光控制电路用于基于所述栅极信号端提供的栅极驱动信号、所述数据信号端提供的数据信号、所述复位信号端提供的复位信号和所述初始电源端提供的初始电源信号，控制所述驱动电路的控制端的电位；
所述驱动电路的输出端用于与发光元件耦接，所述驱动电路用于基于所述驱动电路的控制端的电位，向所述发光元件传输发光驱动信号，以驱动所述发光元件发光；
其中，所述驱动电路包括并联的第一驱动晶体管和第二驱动晶体 管；并且，所述第一驱动晶体管和所述第二驱动晶体管中，一个驱动晶体管的亚阈值摆幅大于另一个驱动晶体管的亚阈值摆幅。
可选的，所述第一驱动晶体管的栅极作为所述驱动电路的控制端与所述发光控制电路耦接，所述第二驱动晶体管的栅极与所述第一驱动晶体管的栅极耦接；
其中，所述第一驱动晶体管的亚阈值摆幅大于所述第二驱动晶体管的亚阈值摆幅。
可选的，所述发光控制电路包括：第一复位子电路、数据写入子电路和补偿控制子电路；
所述第一复位子电路分别与所述复位信号端、所述初始电源端和所述驱动电路的控制端耦接，所述第一复位子电路用于响应于所述复位信号，控制所述初始电源端与所述驱动电路的控制端的通断；
所述数据写入子电路分别与所述栅极信号端、所述数据信号端和所述驱动电路的输入端耦接，所述数据写入子电路用于响应于所述栅极驱动信号，控制所述数据信号端与所述驱动电路的输入端的通断；
所述补偿控制子电路分别与所述栅极信号端、所述驱动电路的输出端和所述驱动电路的控制端耦接，所述补偿控制子电路用于响应于所述栅极驱动信号，控制所述驱动电路的输出端与所述驱动电路的控制端的通断。
可选的，所述发光控制电路还包括：第一发光控制子电路、第二发光控制子电路、第二复位子电路和存储子电路；
所述第一发光控制子电路分别与发光控制端、驱动电源端和所述驱动电路的输入端耦接，所述第一发光控制子电路用于响应于所述发光控制端提供的发光控制信号，控制所述驱动电源端与所述驱动电路的输入端的通断；
所述第二发光控制子电路分别与所述发光控制端和所述驱动电路的输出端耦接，且用于与所述发光元件耦接，所述第二发光控制子电路用于响应于所述发光控制信号，控制所述驱动电路的输出端与所述发光元件的通断；
所述第二复位子电路分别与所述复位信号端和所述初始电源端耦 接，且用于与所述发光元件耦接，所述第二复位子电路用于响应于所述复位信号，控制所述初始电源端与所述发光元件的通断；
所述存储子电路分别与所述驱动电源端和所述驱动电路的控制端耦接，所述存储子电路用于基于所述驱动电源信号，存储所述驱动电路的控制端的电位。
可选的，所述第一复位子电路包括：第一复位晶体管；所述第二复位子电路包括：第二复位晶体管；所述数据写入子电路包括：数据写入晶体管；所述补偿控制子电路包括：补偿晶体管；所述第一发光控制子电路包括：第一发光控制晶体管；所述第二发光控制子电路包括：第二发光控制晶体管；所述存储子电路包括：存储电容；
其中，所述第一复位晶体管的栅极和所述第二复位晶体管的栅极均与所述复位信号端耦接，所述第一复位晶体管的第一极和所述第二复位晶体管的第一极均与所述初始电源端耦接，所述第一复位晶体管的第二极与控制节点耦接，所述第二复位晶体管的第二极用于与所述发光元件耦接；
所述数据写入晶体管的栅极和所述补偿晶体管的栅极均与所述栅极信号端耦接，所述数据写入晶体管的第一极与所述数据信号端耦接，所述数据写入晶体管的第二极与输入节点耦接，所述补偿晶体管的第一极与控制节点耦接，所述补偿晶体管的第二极与所述输出节点耦接；
所述第一发光控制晶体管的栅极和所述第二发光控制晶体管的栅极均与所述发光控制端耦接，所述第一发光控制晶体管的第一极与所述驱动电源端耦接，所述第一发光控制晶体管的第二极与所述输入节点耦接，所述第二发光控制晶体管的第一极与所述输出节点耦接，所述第二发光控制晶体管的第二极用于与所述发光元件耦接；
所述存储电容的一端与所述驱动电源端耦接，所述存储电容的另一端与所述控制节点耦接；
所述第一驱动晶体管的栅极与所述控制节点耦接，所述第二驱动晶体管的栅极与所述第一驱动晶体管的栅极耦接，所述第一驱动晶体管的第一极和所述第二驱动晶体管的第一极均与所述输入节点耦接，所述第一驱动晶体管的第二极和所述第二驱动晶体管的第二极均与所 述输出节点耦接。
可选的，所述像素驱动电路包括的各个晶体管均为P型晶体管。
另一方面，提供了一种显示面板，所述显示面板包括：衬底，以及位于所述衬底一侧的多个像素；
其中，所述像素包括：发光元件，以及如上述一方面所述的像素驱动电路；所述像素驱动电路与所述发光元件耦接，所述像素驱动电路用于驱动所述发光元件发光。
又一方面，提供了一种显示面板的制备方法，用于制备如上述一方面所述的显示面板；所述方法包括：
提供衬底；
在所述衬底的一侧形成有源层，所述有源层包括：相互间隔的第一有源层图案和第二有源层图案，所述第一有源层图案和所述第二有源层图案中，一个有源层图案属于所述显示面板中的第一驱动晶体管，另一个有源层图案属于所述显示面板中的第二驱动晶体管；
对所述有源层远离所述衬底的表面进行等离子处理；
在所述有源层远离所述衬底的一侧形成栅极绝缘层，所述栅极绝缘层覆盖所述有源层，且所述栅极绝缘层覆盖所述第一有源层图案的厚度与所述栅极绝缘层覆盖所述第二有源层图案的厚度不等。
可选的，所述第一有源层图案属于所述显示面板中的第一驱动晶体管，所述第二有源层图案属于所述显示面板中的第二驱动晶体管；
并且，所述栅极绝缘层覆盖所述第一有源层图案的厚度，大于所述栅极绝缘层覆盖所述第二有源层图案的厚度。
可选的，所述对所述有源层远离所述衬底的一侧进行等离子处理，包括：
对所述第二有源层图案远离所述衬底的表面进行等离子处理；
所述在所述有源层远离所述衬底的一侧形成栅极绝缘层，包括：
在对所述第二有源层图案远离所述衬底的表面进行等离子处理之前，在所述第一有源层图案远离所述衬底的一侧形成第一栅极绝缘层，所述第一栅极绝缘层覆盖所述第一有源层图案；
在对所述第二有源层图案远离所述衬底的表面进行等离子处理之 后，在所述第二有源层图案远离所述衬底的一侧形成第二栅极绝缘层，所述第二栅极绝缘层覆盖所述第二有源层图案和所述第一栅极绝缘层。
可选的，所述第二栅极绝缘层中，与所述第一有源层图案在所述衬底上的正投影交叠部分的厚度等于与所述第二有源层图案在所述衬底上的正投影交叠部分的厚度。
可选的，所述在所述衬底的一侧形成有源层之前，所述方法还包括：
在所述衬底的一侧形成柔性材料层；
在所述柔性材料层远离所述衬底的一侧形成第一缓冲层；
所述在所述衬底的一侧形成有源层，包括：在所述第一缓冲层远离所述衬底的一侧形成有源层。
可选的，所述在所述第一缓冲层远离所述衬底的一侧形成有源层之前，所述方法还包括：
在所述第一缓冲层远离所述衬底的一侧形成第一栅极层；
在所述第一栅极层远离所述第一缓冲层的一侧形成第二缓冲层，所述第二缓冲层覆盖所述第一栅极层；
所述在所述第一缓冲层远离所述衬底的一侧形成有源层，包括：在所述第二缓冲层远离所述衬底的一侧形成有源层。
可选的，所述在所述衬底的一侧形成第二栅极绝缘层之后，所述方法还包括：
在所述第二栅极绝缘层远离所述衬底的一侧形成第二栅极层；
在所述第二栅极层远离所述第二栅极绝缘层的一侧形成第一层间介质层，所述第一层间介质层覆盖所述第二栅极层；
在所述第一层间介质层远离所述第二栅极层的一侧形成第三栅极层；
在所述第三栅极层远离所述第一层间介质层的一侧形成第二层间介质层，所述第二层间介质层覆盖所述第三栅极层；
在所述第二层间介质层远离所述第三栅极层的一侧形成源漏极层，所述源漏极层通过贯穿所述第二层间介质层、所述第一层间介质 层和所述栅极绝缘层的过孔与所述有源层耦接；
在所述源漏极层远离所述第二层间介质层的一侧形成平坦层；
在所述平坦层远离所述源漏极层的一侧形成阳极层，所述阳极层通过贯穿所述平坦层的过孔与所述源漏极层耦接；
在所述阳极层远离所述平坦层的一侧形成像素界定层，所述像素界定层覆盖所述平坦层并部分暴露所述阳极层。
再一方面，提供了一种显示装置，所述显示装置包括：供电组件，以及如上述另一方面所述的显示面板；
其中，所述供电组件与所述显示面板耦接，所述供电组件用于为所述显示面板供电。
附图说明
通过阅读参照以下附图所作的对非限制性实施例所作的详细描述，本申请的其它特征、目的和优点将会变得更明显：
图1是本公开实施例提供的一种像素驱动电路的结构示意图；
图2是本公开实施例提供的另一种像素驱动电路的结构示意图；
图3是本公开实施例提供的一种驱动电路的IV特性示意图；
图4是本公开实施例提供的又一种像素驱动电路的结构示意图；
图5是本公开实施例提供的一种显示面板的结构示意图；
图6是本公开实施例提供的一种显示面板的制备方法流程图；
图7是本公开实施例提供的一种显示面板的截面图；
图8是本公开实施例提供的另一种显示面板的截面图；
图9是本公开实施例提供的一种显示面板的俯视图；
图10是本公开实施例提供的另一种显示面板的截面图；
图11是本公开实施例提供的又一种显示面板的截面图；
图12是本公开实施例提供的再一种显示面板的截面图；
图13是本公开实施例提供的再一种显示面板的截面图；
图14是本公开实施例提供的再一种显示面板的截面图；
图15是本公开实施例提供的一种显示装置的结构示意图。
具体实施方式
下面结合附图和实施例对本申请作进一步的详细说明。可以理解的是，此处所描述的具体实施例仅仅用于解释相关发明，而非对该发明的限定。另外还需要说明的是，为了便于描述，附图中仅示出了与发明相关的部分。
需要说明的是，在不冲突的情况下，本申请中的实施例及实施例中的特征可以相互组合。下面将参考附图并结合实施例来详细说明本申请。以及，本公开所有实施例中采用的晶体管均可以为薄膜晶体管或场效应管或其他特性相同的器件，根据在电路中的作用本公开的实施例所采用的晶体管主要为开关晶体管。由于这里采用的开关晶体管的源极和漏极是对称的，所以其源极、漏极是可以互换的。在本公开实施例中，将源极称为第一极，漏极称为第二极。按附图中的形态规定晶体管的中间端为控制极，也可以称为栅极、信号输入端为源极、信号输出端为漏极。此外，本公开实施例所采用的开关晶体管可以包括P型开关晶体管和N型开关晶体管中的任一种，其中，P型开关晶体管在栅极为低电平时导通，在栅极为高电平时截止(即，对于P型晶体管而言，栅极接收到的信号的电位为低电位时开启，栅极接收到的信号的电位为高电位时关断，即低电位为有效电位，高电位为无效电位)，N型开关晶体管在栅极为高电平时导通，在栅极为低电平时截止(即，对于N型晶体管而言，栅极接收到的信号的电位为高电位时开启，栅极接收到的信号的电位为低电位时关断，即高电位为有效电位，低电位为无效电位)。
图1是本公开实施例提供的一种像素驱动电路的结构示意图。如图1所示，该像素驱动电路包括：发光控制电路01和驱动电路02。
发光控制电路01分别与栅极信号端Gate、数据信号端VData、复位信号端Reset、初始电源端Vinit和驱动电路02的控制端耦接。发光控制电路01用于基于栅极信号端Gate提供的栅极驱动信号、数据信号端VData提供的数据信号、复位信号端Reset提供的复位信号和初始电源端Vinit提供的初始电源信号，控制驱动电路02的控制端的电位。
驱动电路02的输出端用于与发光元件L1耦接。驱动电路02用 于基于驱动电路02的控制端的电位，向发光元件L1传输发光驱动信号(如，驱动电流)，以驱动发光元件L1发光。
可选的，参考图1还可以看出，驱动电路02可以是与发光元件L1的第一极耦接，发光元件L1的第二极还可以与下拉电源端VSS耦接。发光元件L1可以在第一极接收到的发光驱动信号和第二极接收到的下拉电源端VSS提供的下拉电源信号的压差作用下发光。
可选的，如图1所示，发光元件L1的第一极可以为阳极，第二极可以为阴极。当然，在一些其他实施例中，发光元件L1的第一极可以为阴极，相应的，发光元件L1的第二极可以为阳极。
其中，在本公开实施例中，结合图2示出的另一种像素驱动电路可以看出：驱动电路02包括并联的第一驱动晶体管T3-1和第二驱动晶体管T3-2。如此，能够将两个驱动晶体管的性能进行中和，两者并联能够在保持器件迁移率的同时提升器件亚阈值摆幅ss。
并且，第一驱动晶体管T3-1和第二驱动晶体管T3-2中，一个驱动晶体管的亚阈值摆幅ss大于另一个驱动晶体管的亚阈值摆幅ss。由于晶体管的亚阈值摆幅ss与迁移率成反比，即晶体管的亚阈值摆幅ss越大，则迁移率越小；反之，晶体管的亚阈值摆幅ss越小，则迁移率越大。故，通过设置其中一个驱动晶体管的亚阈值摆幅ss大于另一个驱动晶体管的亚阈值摆幅ss，可以使得一个驱动晶体管的迁移率大于另一个驱动晶体管的迁移率，即使得一个驱动晶体管的迁移率较小，另一个驱动晶体管的迁移率较大。如此，可以更进一步的使得两个驱动晶体管的亚阈值摆幅ss进行中和，使得在保持器件迁移率的同时提升器件亚阈值摆幅ss。
综上所述，本公开实施例提供了一种像素驱动电路，因其中的驱动电路包括两个并联的驱动晶体管，且其中一个驱动晶体管的亚阈值摆幅大于另一个驱动晶体管的亚阈值摆幅，故可以使得两个驱动晶体管的亚阈值摆幅进行中和，使得在保持器件迁移率的同时提升器件亚阈值摆幅，确保显示面板的显示效果可以较好。
可选的，继续参考图2可以看出，第一驱动晶体管T3-1的栅极可 以作为驱动电路02的控制端与发光控制电路01耦接，第二驱动晶体管T3-2的栅极可以与第一驱动晶体管T3-1的栅极耦接。
其中，第一驱动晶体管T3-1的亚阈值摆幅ss可以大于第二驱动晶体管T3-2的亚阈值摆幅ss。也即是，在本公开实施例中，可以设置并联的两个驱动晶体管中，栅极直接与发光控制电路01耦接的驱动晶体管的亚阈值摆幅ss较大，迁移率较小；而另一个驱动晶体管的亚阈值摆幅ss较小，迁移率较大。
在图2基础上，图3示出了一种驱动晶体管的IV特性曲线示意图，其中横坐标是指电压V，纵坐标是指电流I。且，图3中分别示出了第一驱动晶体管T3-1的IV特性曲线和第二驱动晶体管T3-2的IV特性曲线，以及并联第一驱动晶体管T3-1和第二驱动晶体管T3-2后的IV特性曲线，标识为T3-sum。参考图3可以明确看出：在将第一驱动晶体管T3-1和第二驱动晶体管T3-2并联后，可以提升IV特性，进而可以中和第一驱动晶体管T3-1和第二驱动晶体管T3-2的亚阈值摆幅ss，使得驱动电路02的亚阈值摆幅ss可靠提升。
可选的，继续参考图4示出的另一种像素驱动电路的结构示意图可以看出，本公开实施例记载的发光控制电路01可以包括：第一复位子电路011、数据写入子电路012和补偿控制子电路013。
其中，第一复位子电路011可以分别与复位信号端Reset、初始电源端Vinit和驱动电路02的控制端耦接，第一复位子电路011用于响应于复位信号，控制初始电源端Vinit与驱动电路02的控制端的通断。
例如，第一复位子电路011可以在复位信号的电位为第一电位时，控制初始电源端Vinit与驱动电路02的控制端导通，使得初始电源端Vinit向驱动电路02的控制端传输初始电源信号。以及，第一复位子电路011可以在复位信号的电位为第二电位时，控制初始电源端Vinit与驱动电路02的控制端断开耦接。
可选的，第一电位可以为有效电位，第二电位可以为无效电位，且第一电位相对于第二电位可以为低电位。当然，在一些其他实施例中，第一电位相对于第二电位也可以为高电位。
数据写入子电路012可以分别与栅极信号端Gate、数据信号端 VData和驱动电路02的输入端耦接。数据写入子电路012可以用于响应于栅极驱动信号，控制数据信号端VData与驱动电路02的输入端的通断。
例如，数据写入子电路012可以在栅极驱动信号的电位为第一电位时，控制数据信号端VData与驱动电路02的输入端导通，使得数据信号端VData向驱动电路02的输入端传输数据信号。以及，数据写入子电路012可以在栅极驱动信号的电位为第二电位时，控制数据信号端VData与驱动电路02的输入端断开耦接。
补偿控制子电路013可以分别与栅极信号端Gate、驱动电路02的输出端和驱动电路02的控制端耦接。补偿控制子电路013可以用于响应于栅极驱动信号，控制驱动电路02的输出端与驱动电路02的控制端的通断。
例如，补偿控制子电路013可以在栅极驱动信号的电位为第一电位时，控制驱动电路02的输出端与驱动电路02的控制端导通。以及，补偿控制子电路013可以在栅极驱动信号的电位为第二电位时，控制驱动电路02的输出端与驱动电路02的控制端断开耦接。
可选的，继续参考图4还看出，本公开实施例记载的发光控制电路01还可以包括：第一发光控制子电路014、第二发光控制子电路015、第二复位子电路016和存储子电路017。
第一发光控制子电路014可以分别与发光控制端EM、驱动电源端VDD和驱动电路02的输入端耦接。第一发光控制子电路014可以用于响应于发光控制端EM提供的发光控制信号，控制驱动电源端VDD与驱动电路02的输入端的通断。
例如，第一发光控制子电路014可以在发光控制端EM提供的发光控制信号的电位为第一电位时，控制驱动电源端VDD与驱动电路02的输入端导通，使得驱动电源端VDD向驱动电路02的输入端传输驱动电源信号。以及，第一发光控制子电路014可以在发光控制端EM提供的发光控制信号的电位为第二电位时，控制驱动电源端VDD与驱动电路02的输入端断开耦接。
第二发光控制子电路015可以分别与发光控制端EM和驱动电路 02的输出端耦接，且可以用于与发光元件L1耦接。第二发光控制子电路015可以用于响应于发光控制信号，控制驱动电路02的输出端与发光元件L1的通断。
例如，第二发光控制子电路015可以在发光控制信号的电位为第一电位时，控制驱动电路02的输出端与发光元件L1导通，使得传输至驱动电路02的输出端的信号可以进一步传输至发光元件L1。以及，第二发光控制子电路015可以在发光控制信号的电位为第二电位时，控制驱动电路02的输出端与发光元件L1断开耦接。
第二复位子电路016可以分别与复位信号端Reset和初始电源端Vinit耦接，且可以用于与发光元件L1耦接。第二复位子电路016可以用于响应于复位信号，控制初始电源端Vinit与发光元件L1的通断。
例如，第二复位子电路016可以在复位信号的电位为第一电位时，控制初始电源端Vinit与发光元件L1导通，使得初始电源端Vinit向发光元件L1传输初始电源信号。以及，第二复位子电路016可以在复位信号的电位为第二电位时，控制初始电源端Vinit与发光元件L1断开耦接。
存储子电路017可以分别与驱动电源端VDD和驱动电路02的控制端耦接。存储子电路017可以用于基于驱动电源信号，存储驱动电路02的控制端的电位。
即，在本公开实施例中，第一复位子电路011可以用于在复位信号端Reset的控制下将初始电源端Vinit提供的初始电源信号提供给驱动电路02的控制端，以对驱动电路02的控制端进行复位。第二复位子电路016可以用于在复位信号端Reset的控制下将初始电源端Vinit提供的初始电源信号提供给发光元件L1的阳极，以对发光元件L1的阳极进行复位。数据写入子电路012可以用于在栅极信号端Gate的控制下将数据信号端VData提供的数据信号提供给驱动模块02的输入端。补偿控制子电路013可以用于在栅极信号端Gate的控制下基于驱动模块02的输出端的电位调整驱动模块02的控制端的电位。第一发光控制子电路014可以用于在发光控制端EM的控制下将驱动电源端VDD提供的驱动电源信号传输至驱动电路02。第二发光控制子电路015用 于在发光控制端EM的控制下将驱动电路02的输出端的电压提供给发光元件L1。驱动电路02可以用于在控制端的信号(如，第一复位子电路011传输的信号)控制下驱动发光元件L1发光。
可选的，继续参考图2可以看出，在本公开实施例中，第一复位子电路011可以包括：第一复位晶体管T1。第二复位子电路016可以包括：第二复位晶体管T7。数据写入子电路012可以包括：数据写入晶体管T4。补偿控制子电路013可以包括：补偿晶体管T2。第一发光控制子电路014可以包括：第一发光控制晶体管T5。第二发光控制子电路015可以包括：第二发光控制晶体管T6。存储子电路017可以包括：存储电容Cst。
其中，第一复位晶体管T1的栅极和第二复位晶体管T7的栅极可以均与复位信号端Reset耦接，第一复位晶体管T1的第一极和第二复位晶体管T7的第一极可以均与初始电源端Vinit耦接，第一复位晶体管T1的第二极可以与控制节点N1耦接，第二复位晶体管T7的第二极可以用于与发光元件L1耦接。相应的，可以通过该第一复位晶体管T1向控制节点N1传输初始电源信号，且通过该第二复位晶体管T7向发光元件L1的阳极传输初始电源信号。
数据写入晶体管T4的栅极和补偿晶体管T2的栅极可以均与栅极信号端Gate耦接，数据写入晶体管T4的第一极可以与数据信号端VData耦接，数据写入晶体管T4的第二极可以与输入节点N2耦接，补偿晶体管T2的第一极可以与控制节点N1(即，第一复位子电路011和驱动电路02的耦接点)耦接，补偿晶体管T2的第二极可以与输出节点N3耦接。相应的，可以通过该数据写入晶体管T4将数据信号写入驱动电路02的输入端，且再通过该补偿晶体管T2将数据信号写入至驱动电路02的控制端。
第一发光控制晶体管T5的栅极和第二发光控制晶体管T6的栅极可以均与发光控制端EM耦接，第一发光控制晶体管T5的第一极可以与驱动电源端VDD耦接，第一发光控制晶体管T5的第二极可以与输入节点N2耦接，第二发光控制晶体管T6的第一极可以与输出节点N3耦接，第二发光控制晶体管T6的第二极可以用于与发光元件L1 耦接。如，与发光元件L1的阳极耦接。相应的，可以通过该第一发光控制晶体管T5将驱动电源端VDD提供的驱动电源信号传输至驱动电路02的输入端，且可以通过该第二发光控制晶体管T6将驱动电路02的输出端的信号传输至发光元件L1。
存储电容Cst的一端可以与驱动电源端VDD耦接，存储电容Cst的另一端可以与控制节点N1(即，第一复位子电路011和驱动电路02的耦接点)耦接。
第一驱动晶体管T3-1的栅极可以与控制节点N1耦接，第二驱动晶体管T3-2的栅极可以与第一驱动晶体管T3-1的栅极耦接，第一驱动晶体管T3-1的第一极和第二驱动晶体管T3-2的第一极可以均与输入节点N2耦接，第一驱动晶体管T3-1的第二极和第二驱动晶体管T3-2的第二极可以均与输出节点N3耦接。如此可知，驱动电路02的控制端即为控制节点N1，输入端即为输入节点N2，输出端即为输出节点N3。
可选的，参考图3还可以看出，本公开实施例记载的像素驱动电路包括的各个晶体管可以均为P型晶体管。相应的，上述实施例记载的第一电位(即，有效电位)可以为低电位，第二电位(即，无效电位)可以高电位。图3示出的发光元件L1为OLED。
也即是，在本公开实施例中，发光控制电路01中，第一复位子电路011可以通过第一复位晶体管T1实现；第二复位子电路016可以通过第二复位晶体管T7实现；数据写入子电路012可以通过数据写入晶体管T4实现；补偿控制子电路013可以通过补偿晶体管T2实现；第一发光控制子电路014可以通过第一发光控制晶体管T5实现；第二发光控制子电路015可以通过第二发光控制晶体管T6实现；存储子电路017可以通过存储电容Cst实现。驱动电路02可以通过并联的第一驱动晶体管T3-1和第二驱动晶体管T3-2实现。以及，第一驱动晶体管T3-1的栅极和第二驱动晶体管T3-2的栅极可以均耦接至第一复位子电路011。第一驱动晶体管T3-1的第一极和第二驱动晶体管T3-2的第一极可以均耦接至第一发光控制子电路014。
需要说明的是，图3示出的像素驱动电路可以认为是一种8T1C (即，包括8个晶体管和1个电容)结构。在一些其他实施例中，像素驱动电路也可以为其他结构，如6T2C结构，前提是驱动电路02包括如图3所示并联的两个驱动晶体管即可。
综上所述，本公开实施例提供了一种像素驱动电路，因其中的驱动电路包括两个并联的驱动晶体管，且其中一个驱动晶体管的亚阈值摆幅大于另一个驱动晶体管的亚阈值摆幅，故可以使得两个驱动晶体管的亚阈值摆幅进行中和，使得在保持器件迁移率的同时提升器件亚阈值摆幅，确保显示面板的显示效果可以较好。
基于同一发明构思，本公开实施例还提供了一种显示面板，如图5所示，本公开实施例提供的显示面板包括：衬底10，以及位于衬底10一侧的多个像素P1。其中，每个像素P1包括：发光元件L1，以及如上述实施例记载的像素驱动电路00。该像素驱动电路00与发光元件L1耦接。该像素驱动电路00用于驱动发光元件L1发光。
需要说明的是，本公开实施例保护的显示面板采用上述像素驱动电路，解决问题的原理与前面所说的像素驱动电路类似，可参考前面对像素驱动电路的实施例，不在赘述。
基于同一发明构思，本公开实施例还提供了一种显示面板制备方法，用于制备如上述实施例记载的显示面板。如图6所示，本公开实施例记载的制备方法包括如下步骤：
步骤601、提供衬底。
在显示面板的制备过程中，首先会提供一个衬底，衬底也可以称为基板。示例的，图7和图8分别示出了两种显示面板在驱动电路02处的截面图。其均示出了提供的衬底10。
可选的，这里的衬底10可以为玻璃基板。当然，在一些其他实施例中，衬底10还可以为柔性衬底。
步骤602、在衬底的一侧形成有源层，且形成的有源层包括：相互间隔的第一有源层图案和第二有源层图案。
可选的，结合图7和图8，在本公开实施例中，可以通过溅射工艺在衬底10的一侧形成有源层20。图9示出了一种显示面板的俯视 图，其中也可以看出在衬底10一侧形成的有源层20。
可选的，有源层20的材料可以包括：铟镓锌氧化物(indium gallium zinc oxide，IGZO)、铟锌氧化物(indium zinc oxide，IZO)、氧化铟镓(indium gallium oxid，IGO)、铟锡氧化锌(Indium tin zinc oxide，ITZO)或氧化镓锡(zinc tin oxid，ZTO)等金属氧化物。
并且，本公开实施例形成的第一有源层图案201和第二有源层图案202中，一个有源层图案可以属于显示面板中的第一驱动晶体管(即，图3示出的T3-1)，另一个有源层图案可以属于显示面板中的第二驱动晶体管(即，图3示出的T3-2)。即，形成的有源层20包括第一驱动晶体管T3-1的有源层图案和第二驱动晶体管T3-2的有源层图案。
步骤603、在第一有源层图案远离衬底的一侧形成第一栅极绝缘层，且形成的第一栅极绝缘层覆盖第一有源层图案。
可选的，继续结合图7和图8可以看出，在形成有源层20之后，随后可以采用化学气相淀积法沉积形成第一栅极绝缘层30。此外，还可以采用光刻法(也称为构图工艺)图形化，形成图10所示俯视图的图形，构图工艺包括：曝光、显影和刻蚀等步骤。形成的该第一栅极绝缘层30可以覆盖第一有源层图案201设置，可以对该第一有源层图案20处的栅极绝缘层进行加厚，形成亚阈值摆幅ss较大的第一驱动晶体管T3-1。
可选的，第一栅极绝缘层30的材料可以包括：二氧化硅SiO2、氧化铝Al2O3、二氧化铪HfO2、二氧化锆ZrO2、氧化钛TiOx或氮化硅SiNx。
步骤604、对第二有源层图案远离衬底的表面进行等离子处理。
可选的，结合图7至图9，可以对第二有源层图案202远离衬底10的表面进行二氧化氮N2O或氧气O2等离子处理，使得该区域的晶体管的阈值电压Vth正偏。
步骤605、在第二有源层图案远离衬底的一侧形成第二栅极绝缘层，且形成的第二栅极绝缘层覆盖第二有源层图案和第一栅极绝缘层。
可选的，继续结合图7和图8可以看出，在对第二有源层图案202 远离衬底10的表面进行等离子处理之后，可以继续采用化学气相淀积法沉积第二栅极绝缘层40，该第二栅极绝缘层40的材料也可以包括上述实施例记载的：二氧化硅SiO2、氧化铝Al2O3、二氧化铪HfO2、二氧化锆ZrO2、氧化钛TiOx或氮化硅SiNx，且形成的该第二栅极绝缘层40覆盖第一栅极绝缘层30和第二有源层图案202设置。如此，即可以使得栅极绝缘层30覆盖第一有源层图案201的厚度，大于栅极绝缘层30覆盖第二有源层图案202的厚度。即，使得栅极绝缘层30覆盖第一有源层图案201的厚度与栅极绝缘层30覆盖第二有源层图案202的厚度不等，两个有源层图案上方的栅极绝缘层的厚度不相同。
因栅极绝缘层的厚度越厚，形成的晶体管的电容越小，栅极电场越弱；反之，栅极绝缘层的厚度越薄，形成的晶体管的电容越大，栅极电场越强。故，可以使得形成一个亚阈值摆幅ss大一个亚阈值摆幅ss小的两个驱动晶体管。即，可以使得图2所示的第一驱动晶体管T3-1的亚阈值摆幅ss和第二驱动晶体管T3-2的亚阈值摆幅ss不等。即如上述实施例记载，可以使得第一驱动晶体管T3-1和第二驱动晶体管T3-2中，一个驱动晶体管的亚阈值摆幅ss大于另一个驱动晶体管的亚阈值摆幅ss。此外，通过上述前后形成第一栅极绝缘层30和第二栅极绝缘层40，可以制备得到并联的两个驱动晶体管。
换言之，在本公开实施例中，在进行相应的有源层20的设置之后，需要设置栅极绝缘层对有源层20进行覆盖，使得制备得到的两个驱动晶体管不仅可以并联，而且可以具有不同的亚阈值摆幅ss。并联使用能够将两者的性能进行中和，能够降低驱动电路的驱动晶体管的亚阈值摆幅ss，提高显示面板显示低灰阶画面时的亮度控制能力，且同时不会降低迁移率。由上述实施例记载可知，可以是通过不同厚度的栅极绝缘层实现具有不同亚阈值摆幅ss的驱动晶体管。
可选的，在本公开实施例中，第一有源层图案201可以属于显示面板中的第一驱动晶体管T3-1，第二有源层图案202可以属于显示面板中的第二驱动晶体管T3-2。如此，可以使得第一驱动晶体管T3-1的亚阈值摆幅ss大于第二驱动晶体管T3-2的亚阈值摆幅ss。也即是，可以使得并联的两个驱动晶体管中，栅极直接与发光控制电路耦接的 驱动晶体管的亚阈值摆幅ss较大，迁移率较小；而另一个驱动晶体管的亚阈值摆幅ss较小，迁移率较大。从而更好的提升亚阈值摆幅。
可选的，在上述实施例基础上，继续参考图7和图8可以看出，本公开实施例形成的第二栅极绝缘层40中，与第一有源层图案201在衬底10上的正投影交叠部分的厚度可以等于与第二有源层图案202在衬底10上的正投影交叠部分的厚度。
即，进一步的，第二栅极绝缘层40位于第一有源层图案201处的厚度，与位于第二有源层图案202处的厚度可以相同。如此，可以确保可靠形成两个并联的驱动晶体管的结构。
可选的，继续参考图7和图8示出的截面图可以看出，在衬底10的一侧形成有源层20(即，上述步骤602)之前，制备方法还可以包括：
在衬底10的一侧形成柔性材料层50。
可选的，柔性材料可以包括聚酰亚胺(polyimide，PI)，在此基础上，柔性材料层50还可以称为PI层。
随后，在柔性材料层50远离衬底10的一侧形成第一缓冲层60。
可选的，第一缓冲层60的材料可以包括：二氧化硅SiO2、氮化硅SiNx或氮氧化硅SiON。
相应的，在衬底10的一侧形成有源层20可以包括：在第一缓冲层60远离衬底10的一侧形成有源层20。
可选的，继续参考图8还可以看出，在第一缓冲层60远离衬底10的一侧形成有源层20(即，上述步骤602)之前，制备方法还可以包括：
在第一缓冲层60远离衬底10的一侧形成第一栅极层70。
在第一栅极层70远离第一缓冲层60的一侧形成第二缓冲层80，且形成的第二缓冲层80覆盖第一栅极层70。即，第二缓冲层80覆盖第一栅极层70设置。
可选的，可以在第一缓冲层60远离衬底10的一侧依次沉积第一栅极层70和第二缓冲层80。
可选的，第一栅极层70的材料可以包括：钼Mo、钛Ti、铝Al、 铜Cu、氧化铟锡ITO和银Ag等金属及其合金，并可以采用光刻法进行图案化处理。第二缓冲层80的材料可以包括：二氧化硅SiO2、氧化铝Al2O3、二氧化铪HfO2、二氧化锆ZrO2、氧化钛TiOx或氮化硅SiNx。
也即是，本公开实施例记载的显示面板提供了图7和图8两种实施例方式。其中，图8所示结构为双栅晶体管结构，在制备图8的双栅结构的时候，需要首先形成如上述实施例记载的第一缓冲层60，随后在第一缓冲层60上形成第一栅极层70。随后可以在第一栅极层70上采用化学气相淀积法沉积形成第二缓冲层80，第二缓冲层80可以覆盖第一栅极层70和露出的第一缓冲层60设置。通过在形成有源层20之前形成第一栅极层70，为后续形成双栅结构的晶体管提供条件。
相应的，在第一缓冲层60远离衬底10的一侧形成有源层20可以包括：在第二缓冲层80远离衬底10的一侧形成有源层20。
可选的，继续参考图7和图8还可以看出，在衬底10的一侧形成第二栅极绝缘层(即，上述步骤605)之后，制备方法还可以包括：
在第二栅极绝缘层40远离衬底10的一侧形成第二栅极层90。即，在第二栅极绝缘层40上设置第二栅极层90。
在第二栅极层90远离第二栅极绝缘层40的一侧形成第一层间介质层100，且形成的第一层间介质层100覆盖第二栅极层90。即，在第二栅极层90上设置第一层间介质层100，且第一层间介质层100覆盖第二栅极层90设置。
在第一层间介质层100远离第二栅极层90的一侧形成第三栅极层101。即，在第一层间介质层100上设置第三栅极层101。
在第三栅极层101远离第一层间介质层100的一侧形成第二层间介质层102，且形成的第二层间介质层102覆盖第三栅极层101。即，在第三栅极层101上设置第二层间介质层102，且第二层间介质层102覆盖第三栅极层101设置。
在第二层间介质层102远离第三栅极层101的一侧形成源漏极层103，且形成的源漏极层103通过贯穿第二层间介质层102、第一层间介质层100、第二栅极绝缘层40和第一栅极绝缘层30的过孔K1与有 源层20耦接。即，在第二层间介质层102上形成源漏极层103，该源漏极层103经过孔K1连接至有源层20。
在源漏极层103远离第二层间介质层102的一侧形成平坦层104。即，在源漏极层103上覆盖平坦层104。
在平坦层104远离源漏极层103的一侧形成阳极层105，且形成的阳极层105通过贯穿平坦层104的过孔K2与源漏极层103耦接。即，在平坦层104上沉积阳极层105，该阳极层105经过孔K2连接至源漏极层103。
在平坦层104的一侧形成像素界定层106，且形成的像素界定层106覆盖平坦层104并部分暴露阳极层105。可选的，像素界定层106可以为有机膜层，相应的，可以是指形成有机膜层，该有机膜层覆盖平坦层104并部分露出阳极层105设置。
图7和图8的结构形成好第二栅极绝缘层40，均形成好两个驱动晶体管后，随后在第二栅极绝缘层40上设置第二栅极层90，对于图7的结构来说，该第二栅极层90可以是是指第一个栅极层，该第二栅极层的材料也可以包括：钼Mo、钛Ti、铝Al、铜Cu、氧化铟锡ITO和银Ag等金属及其合金，并采用光刻法进行图案化，形成如图11所示的结构。
随后可以采用化学气相淀积法沉积第一层间介质层100，该第一层间介质层100覆盖第二栅极层90，且该第一层间介质层100的材料可以包括：二氧化硅SiO2、氧化铝Al2O3、二氧化铪HfO2、二氧化锆ZrO2、氧化钛TiOx或氮化硅SiNx。
随后可以在第一层间介质层100上形成第三栅极层101，该第三栅极层101的材料也可以包括：钼Mo、钛Ti、铝Al、铜Cu、氧化铟锡ITO和银Ag等金属及其合金，并采用光刻法进行图案化，形成如图12所示的结构。
随后可以采用化学气相淀积法沉积第二层间介质层102，第二层间介质层102的材料也可以包括：二氧化硅SiO2、氧化铝Al2O3、二氧化铪HfO2、二氧化锆ZrO2、氧化钛TiOx或氮化硅SiNx。该第一层间介质层100和第二层间介质层102，以及第一栅极绝缘层30和第二 栅极绝缘层40上均设有过孔，通过该过孔可以暴露相应的有源层图案，形成如图13所示的结构。
随后可以在第二层间介质层102上溅射沉积源漏极层103，该源漏极层103的材料也可以包括：钼Mo、钛Ti、铝Al、铜Cu、氧化铟锡ITO和银Ag等金属及其合金，并采用光刻法进行图案化，该源漏极层103还通过上述的过孔连接至相应的有源层20，形成如图14所示的结构。
随后可以进行平坦层104的制备，并采用光刻法图形化。
随后可以在平坦层104上溅射沉积阳极层105，该阳极层105的材料也可以包括：钼Mo、钛Ti、铝Al、铜Cu、氧化铟锡ITO和银Ag等金属及其合金，并采用光刻法进行图案化，该阳极层105可以通过设置在平坦层104上的过孔连接至上述的源漏极层103。
最后可以制备有机膜层(即，像素界定层106)，并采用光刻法图形化，该有机膜层暴露部分上述阳极层设置。
上述步骤中为图7和图8的结构中相同的步骤方法。
上述步骤中提供的显示面板具有并联的两个驱动晶体管，并且一个驱动晶体管的亚阈值摆幅ss较大，另一个驱动晶体管的亚阈值摆幅ss小，通过并联的两个结构可以将亚阈值摆幅ss进行中和。同时，上述步骤中将不同厚度的栅极绝缘层分为两部分制备，第一栅极绝缘层制备好后，采用等离子体处理表面时，使得一部分的有源层被处理。
综上所述，本公开实施例提供了一种显示面板的制备方法，该方法制备得到的显示面板中，属于第一驱动晶体管的有源层图案一侧的栅极绝缘层厚度与属于第二驱动晶体管的有源层图案一侧的栅极绝缘层厚度不等，如此，可以使得一个驱动晶体管的亚阈值摆幅大于另一个驱动晶体管的亚阈值摆幅，进而使得两个驱动晶体管的亚阈值摆幅进行中和，在保持器件迁移率的同时提升器件亚阈值摆幅，确保显示面板的显示效果可以较好。
基于同一发明构思，本公开实施例还提供了一种显示装置。如图15所示，该显示装置包括：供电组件J1，以及如图5所示的显示面板 M1。供电组件J1与显示面板M1耦接，并用于为显示面板M1供电。
可选的，本公开实施例提供的显示装置可以包括：显示器、手机、电视、笔记本电脑和/或导航仪等，对于显示装置的其他必不可少的组成部分均为本领域的普通技术人员应该理解具有的，不再赘述。
需要理解的是，上文如有涉及术语“中心”、“纵向”、“横向”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本公开实施例和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开实施例的限制；方位词“内、外”是指相对于各部件本身的轮廓的内外。此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。
为了便于描述，在这里可以使用空间相对术语，如“在……之上”、“在……上方”、“在……上表面”、“上面的”等，用来描述如在图中所示的一个器件或特征与其他器件或特征的空间位置关系。应当理解的是，空间相对术语旨在包含除了器件在图中所描述的方位之外的在使用或操作中的不同方位。例如，如果附图中的器件被倒置，则描述为“在其他器件或构造上方”或“在其他器件或构造之上”的器件之后将被定位为“在其他器件或构造下方”或“在其他器件或构造之下”。因而，示例性术语“在……上方”可以包括“在……上方”和“在……下方”两种方位。该器件也可以其他不同方式定位旋转90度或处于其他方位，并且对这里所使用的空间相对描述作出相应解释。
以上描述仅为本申请的较佳实施例以及对所运用技术原理的说明。本领域技术人员应当理解，本申请中所涉及的发明范围，并不限于上述技术特征的特定组合而成的技术方案，同时也应涵盖在不脱离所述发明构思的情况下，由上述技术特征或其等同特征进行任意组合而形成的其它技术方案。例如上述特征与本申请中公开的(但不限于)具有类似功能的技术特征进行互相替换而形成的技术方案。

Claims (14)

  1. 一种像素驱动电路，其特征在于，所述像素驱动电路包括：发光控制电路和驱动电路；
    所述发光控制电路分别与栅极信号端、数据信号端、复位信号端、初始电源端和所述驱动电路的控制端耦接，所述发光控制电路用于基于所述栅极信号端提供的栅极驱动信号、所述数据信号端提供的数据信号、所述复位信号端提供的复位信号和所述初始电源端提供的初始电源信号，控制所述驱动电路的控制端的电位；
    所述驱动电路的输出端用于与发光元件耦接，所述驱动电路用于基于所述驱动电路的控制端的电位，向所述发光元件传输发光驱动信号，以驱动所述发光元件发光；
    其中，所述驱动电路包括并联的第一驱动晶体管和第二驱动晶体管；并且，所述第一驱动晶体管和所述第二驱动晶体管中，一个驱动晶体管的亚阈值摆幅大于另一个驱动晶体管的亚阈值摆幅。
  2. 根据权利要求1所述的像素驱动电路，其特征在于，所述第一驱动晶体管的栅极作为所述驱动电路的控制端与所述发光控制电路耦接，所述第二驱动晶体管的栅极与所述第一驱动晶体管的栅极耦接；
    其中，所述第一驱动晶体管的亚阈值摆幅大于所述第二驱动晶体管的亚阈值摆幅。
  3. 根据权利要求1或2所述的像素驱动电路，其特征在于，所述发光控制电路包括：第一复位子电路、数据写入子电路和补偿控制子电路；
    所述第一复位子电路分别与所述复位信号端、所述初始电源端和所述驱动电路的控制端耦接，所述第一复位子电路用于响应于所述复位信号，控制所述初始电源端与所述驱动电路的控制端的通断；
    所述数据写入子电路分别与所述栅极信号端、所述数据信号端和所述驱动电路的输入端耦接，所述数据写入子电路用于响应于所述栅 极驱动信号，控制所述数据信号端与所述驱动电路的输入端的通断；
    所述补偿控制子电路分别与所述栅极信号端、所述驱动电路的输出端和所述驱动电路的控制端耦接，所述补偿控制子电路用于响应于所述栅极驱动信号，控制所述驱动电路的输出端与所述驱动电路的控制端的通断。
  4. 根据权利要求3所述的像素驱动电路，其特征在于，所述发光控制电路还包括：第一发光控制子电路、第二发光控制子电路、第二复位子电路和存储子电路；
    所述第一发光控制子电路分别与发光控制端、驱动电源端和所述驱动电路的输入端耦接，所述第一发光控制子电路用于响应于所述发光控制端提供的发光控制信号，控制所述驱动电源端与所述驱动电路的输入端的通断；
    所述第二发光控制子电路分别与所述发光控制端和所述驱动电路的输出端耦接，且用于与所述发光元件耦接，所述第二发光控制子电路用于响应于所述发光控制信号，控制所述驱动电路的输出端与所述发光元件的通断；
    所述第二复位子电路分别与所述复位信号端和所述初始电源端耦接，且用于与所述发光元件耦接，所述第二复位子电路用于响应于所述复位信号，控制所述初始电源端与所述发光元件的通断；
    所述存储子电路分别与所述驱动电源端和所述驱动电路的控制端耦接，所述存储子电路用于基于所述驱动电源信号，存储所述驱动电路的控制端的电位。
  5. 根据权利要求4所述的像素驱动电路，其特征在于，所述第一复位子电路包括：第一复位晶体管；所述第二复位子电路包括：第二复位晶体管；所述数据写入子电路包括：数据写入晶体管；所述补偿控制子电路包括：补偿晶体管；所述第一发光控制子电路包括：第一发光控制晶体管；所述第二发光控制子电路包括：第二发光控制晶体管；所述存储子电路包括：存储电容；
    其中，所述第一复位晶体管的栅极和所述第二复位晶体管的栅极均与所述复位信号端耦接，所述第一复位晶体管的第一极和所述第二复位晶体管的第一极均与所述初始电源端耦接，所述第一复位晶体管的第二极与控制节点耦接，所述第二复位晶体管的第二极用于与所述发光元件耦接；
    所述数据写入晶体管的栅极和所述补偿晶体管的栅极均与所述栅极信号端耦接，所述数据写入晶体管的第一极与所述数据信号端耦接，所述数据写入晶体管的第二极与输入节点耦接，所述补偿晶体管的第一极与控制节点耦接，所述补偿晶体管的第二极与所述输出节点耦接；
    所述第一发光控制晶体管的栅极和所述第二发光控制晶体管的栅极均与所述发光控制端耦接，所述第一发光控制晶体管的第一极与所述驱动电源端耦接，所述第一发光控制晶体管的第二极与所述输入节点耦接，所述第二发光控制晶体管的第一极与所述输出节点耦接，所述第二发光控制晶体管的第二极用于与所述发光元件耦接；
    所述存储电容的一端与所述驱动电源端耦接，所述存储电容的另一端与所述控制节点耦接；
    所述第一驱动晶体管的栅极与所述控制节点耦接，所述第二驱动晶体管的栅极与所述第一驱动晶体管的栅极耦接，所述第一驱动晶体管的第一极和所述第二驱动晶体管的第一极均与所述输入节点耦接，所述第一驱动晶体管的第二极和所述第二驱动晶体管的第二极均与所述输出节点耦接。
  6. 根据权利要求5所述的像素驱动电路，其特征在于，所述像素驱动电路包括的各个晶体管均为P型晶体管。
  7. 一种显示面板，其特征在于，所述显示面板包括：衬底，以及位于所述衬底一侧的多个像素；
    其中，所述像素包括：发光元件，以及如权利要求1至6任一所述的像素驱动电路；所述像素驱动电路与所述发光元件耦接，所述像素驱动电路用于驱动所述发光元件发光。
  8. 一种显示面板的制备方法，其特征在于，用于制备如权利要求7所述的显示面板；所述方法包括：
    提供衬底；
    在所述衬底的一侧形成有源层，所述有源层包括：相互间隔的第一有源层图案和第二有源层图案，所述第一有源层图案和所述第二有源层图案中，一个有源层图案属于所述显示面板中的第一驱动晶体管，另一个有源层图案属于所述显示面板中的第二驱动晶体管；
    在所述第一有源层图案远离所述衬底的一侧形成第一栅极绝缘层，所述第一栅极绝缘层覆盖所述第一有源层图案；
    对所述第二有源层图案远离所述衬底的表面进行等离子处理；
    在所述第二有源层图案远离所述衬底的一侧形成第二栅极绝缘层，所述第二栅极绝缘层覆盖所述第二有源层图案和所述第一栅极绝缘层。
  9. 根据权利要求8所述的方法，其特征在于，所述第一有源层图案属于所述显示面板中的第一驱动晶体管，所述第二有源层图案属于所述显示面板中的第二驱动晶体管。
  10. 根据权利要求8或9所述的方法，其特征在于，所述第二栅极绝缘层中，与所述第一有源层图案在所述衬底上的正投影交叠部分的厚度等于与所述第二有源层图案在所述衬底上的正投影交叠部分的厚度。
  11. 根据权利要求8或9所述的方法，其特征在于，所述在所述衬底的一侧形成有源层之前，所述方法还包括：
    在所述衬底的一侧形成柔性材料层；
    在所述柔性材料层远离所述衬底的一侧形成第一缓冲层；
    所述在所述衬底的一侧形成有源层，包括：在所述第一缓冲层远离所述衬底的一侧形成有源层。
  12. 根据权利要求11所述的方法，其特征在于，所述在所述第一缓冲层远离所述衬底的一侧形成有源层之前，所述方法还包括：
    在所述第一缓冲层远离所述衬底的一侧形成第一栅极层；
    在所述第一栅极层远离所述第一缓冲层的一侧形成第二缓冲层，所述第二缓冲层覆盖所述第一栅极层；
    所述在所述第一缓冲层远离所述衬底的一侧形成有源层，包括：在所述第二缓冲层远离所述衬底的一侧形成有源层。
  13. 根据权利要求8或9所述的方法，其特征在于，所述在所述衬底的一侧形成第二栅极绝缘层之后，所述方法还包括：
    在所述第二栅极绝缘层远离所述衬底的一侧形成第二栅极层；
    在所述第二栅极层远离所述第二栅极绝缘层的一侧形成第一层间介质层，所述第一层间介质层覆盖所述第二栅极层；
    在所述第一层间介质层远离所述第二栅极层的一侧形成第三栅极层；
    在所述第三栅极层远离所述第一层间介质层的一侧形成第二层间介质层，所述第二层间介质层覆盖所述第三栅极层；
    在所述第二层间介质层远离所述第三栅极层的一侧形成源漏极层，所述源漏极层通过贯穿所述第二层间介质层、所述第一层间介质层和所述栅极绝缘层的过孔与所述有源层耦接；
    在所述源漏极层远离所述第二层间介质层的一侧形成平坦层；
    在所述平坦层远离所述源漏极层的一侧形成阳极层，所述阳极层通过贯穿所述平坦层的过孔与所述源漏极层耦接；
    在所述阳极层远离所述平坦层的一侧形成像素界定层，所述像素界定层覆盖所述平坦层并部分暴露所述阳极层。
  14. 一种显示装置，其特征在于，所述显示装置包括：供电组件，以及如权利要求7所述的显示面板；
    其中，所述供电组件与所述显示面板耦接，所述供电组件用于为 所述显示面板供电。
PCT/CN2023/095670 2022-06-09 2023-05-23 像素驱动电路、显示面板及其制备方法、显示装置 WO2023236770A1 (zh)

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