WO2023029090A1 - 显示面板及显示装置 - Google Patents

显示面板及显示装置 Download PDF

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Publication number
WO2023029090A1
WO2023029090A1 PCT/CN2021/118281 CN2021118281W WO2023029090A1 WO 2023029090 A1 WO2023029090 A1 WO 2023029090A1 CN 2021118281 W CN2021118281 W CN 2021118281W WO 2023029090 A1 WO2023029090 A1 WO 2023029090A1
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WIPO (PCT)
Prior art keywords
transistor
layer
shielding
electrically connected
metal layer
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Application number
PCT/CN2021/118281
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English (en)
French (fr)
Inventor
杨国强
Original Assignee
武汉华星光电半导体显示技术有限公司
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Application filed by 武汉华星光电半导体显示技术有限公司 filed Critical 武汉华星光电半导体显示技术有限公司
Priority to US17/600,336 priority Critical patent/US12101975B2/en
Publication of WO2023029090A1 publication Critical patent/WO2023029090A1/zh

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1218—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or structure of the substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/33—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being semiconductor devices, e.g. diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/126—Shielding, e.g. light-blocking means over the TFTs

Definitions

  • the present application relates to the field of display technology, in particular to a display panel and a display device.
  • the low-temperature polycrystalline oxide backplane is used in display panels because of its advantages such as high charge mobility and good stability. However, there are some free charges in the low-temperature polycrystalline oxide backplane.
  • a back gate structure will be formed, which will affect the threshold voltage, sub-threshold swing and bias temperature stress of the transistor, thereby affecting the display effect of the display panel and causing problems such as image sticking on the display panel.
  • Embodiments of the present application provide a display panel and a display device, which can improve the influence of free charges on the electrical performance of transistors.
  • An embodiment of the present application provides a display panel, and the display panel includes a substrate, a driving array, and a shielding layer.
  • the drive array includes a first active layer on the substrate, a second active layer, a first metal layer on the first active layer, and a second metal layer on the first metal layer. layer.
  • the first active layer includes a silicon semiconductor material, and the second active layer includes an oxide semiconductor material.
  • the driving array includes a plurality of pixel driving circuits, at least one of which includes a first transistor and a second transistor. Wherein the first active layer includes an active pattern of the first transistor, the second active layer includes an active pattern of the second transistor, and the first metal layer includes an active pattern of the first transistor. grid.
  • the shielding layer includes a first shielding portion located between the active pattern of the first transistor and the substrate, the first shielding portion is electrically connected to a preset stable voltage through the second metal layer .
  • the display panel includes a substrate, a driving array, and a shielding layer, the shielding layer is located between the driving array and the substrate, and the shielding layer is electrically connected to the second metal layer in the driving array.
  • the shielding layer is located between the driving array and the substrate, and the shielding layer is electrically connected to the second metal layer in the driving array.
  • FIG. 1 is a schematic structural diagram of a display panel provided by an embodiment of the present application.
  • FIGS. 2A to 2B are schematic cross-sectional structural diagrams of a display panel provided by an embodiment of the present application.
  • FIG. 3 is a schematic structural diagram of a pixel driving circuit provided by an embodiment of the present application.
  • 4A to 4D are schematic top view structural views of the display panel using the pixel driving circuit shown in FIG. 3;
  • 5A to 5C are schematic diagrams of the manufacturing process of the display panel provided by the embodiments of the present application.
  • FIG. 1 is a schematic structural diagram of a display panel provided by an embodiment of the present application.
  • the display panel provided in the embodiment of the present application may be, but not limited to, a passive light-emitting display panel, a self-luminous display panel, a quantum dot display panel, and the like.
  • the passive light-emitting display panel includes a liquid crystal display panel
  • the self-luminous display panel includes a display panel with light-emitting devices.
  • the display panel includes a display area and a non-display area located on the periphery of the display area, the display area is used to enable the display panel to realize a display function, and the display panel has no display function in the non-display area.
  • the display panel further includes a sensing area, the sensing area is located in at least one of the non-display area, the display area, and the junction between the display area and the non-display area or; the sensing area can take into account the display function or the sensing function, or only have the sensing function.
  • the display panel includes a sensor disposed in the sensing area.
  • the sensor may include a camera, a fingerprint sensor, a distance sensor, a sound sensor, an ambient light sensor, and the like.
  • the display panel includes a plurality of sub-pixels 100, a plurality of data lines DL and a plurality of scanning lines ScanL, a plurality of sub-pixels 100 are located in the display area, each of the sub-pixels 100 and The corresponding data line DL is electrically connected to the scan line ScanL.
  • the emission colors of the plurality of sub-pixels 100 may include red, green, blue, white, yellow, etc.
  • the data line DL is arranged to cross the scan line ScanL.
  • each of the sub-pixels 100 causes the liquid crystal molecules to deflect through the electric field formed between the pixel electrode and the common electrode, and the color filter unit cooperates with the liquid crystal molecules to realize the sub-pixel 100's of display.
  • the pixel electrode is formed on the side of the array substrate
  • the common electrode is formed on the side of the color filter substrate, or the pixel electrode and the common electrode are jointly formed on the side of the array substrate;
  • the liquid crystal molecules are located between the array substrate and the Between the color filter substrates; the color filter unit can be formed on the side of the array substrate or on the side of the color filter substrate.
  • each of the sub-pixels 100 may be formed by a light-emitting device.
  • the light-emitting device includes organic light-emitting diodes, submillimeter light-emitting diodes, or micro light-emitting diodes.
  • Figure 2A to Figure 2B are schematic cross-sectional structural diagrams of the display panel provided by the embodiment of the present application
  • Figure 3 is a schematic structural diagram of the pixel driving circuit provided by the embodiment of the present application, taking the display panel as an example of a self-luminous display panel, The structure and working principle of the display panel will be described.
  • the display panel includes a substrate 1011, a driving array 102, a shielding layer 103 and a light emitting device.
  • the substrate 1011 is a flexible substrate.
  • the preparation material of the substrate 1011 includes polyimide.
  • the driving array 102 is located on the substrate 1011 , the driving array 102 includes a plurality of pixel driving circuits, and each pixel driving circuit is electrically connected to at least one corresponding sub-pixel 100 .
  • a pixel driving circuit is electrically connected to a sub-pixel 100, so that a pixel driving circuit drives a sub-pixel 100 to emit light;
  • a pixel driving circuit is electrically connected to a plurality of the sub-pixels 100 located in the sensing region, so as to drive a plurality of the sub-pixels 100 through a pixel driving circuit.
  • Pixel 100 emits light.
  • the sub-pixel 100 is formed by the light emitting device.
  • the light emitting device includes an anode 1041 , a cathode 1042 and a light emitting layer 1043 between the anode 1041 and the cathode 1042 .
  • the light emitting layer 1043 includes fluorescent material, quantum dot material or perovskite material.
  • the driving array 102 includes a first active layer 1021 on the substrate 1011 , and a first active layer 1021 on the first active layer 1021.
  • the first active layer 1021 includes a silicon semiconductor material
  • the second active layer 1024 includes an oxide semiconductor material.
  • the silicon semiconductor material includes single crystal silicon, polycrystalline silicon or amorphous silicon, etc.
  • the oxide semiconductor material includes at least one of metal oxides of zinc, indium, gallium, tin or titanium; further , the oxide semiconductor material includes zinc oxide, zinc tin oxide, zinc indium oxide, indium oxide, titanium oxide, indium gallium zinc oxide or indium zinc tin oxide and the like.
  • At least one of the pixel driving circuits includes a first transistor T1 and a second transistor T2 .
  • the first active layer 1021 includes the active pattern of the first transistor T1
  • the second active layer 1024 includes the active pattern of the second transistor T2
  • the first metal layer 1022 includes The gate of the first transistor T1
  • the second metal layer 1023 includes a metal plate above the gate of the first transistor T1.
  • the shielding layer 103 is located between the substrate 1011 and the driving array 102, so that the free charges in the substrate 1011 are shielded under the substrate 1011 by using the shielding layer 103, so that the pixel driving circuit During operation, under the action of an electric field, the fast movement and disappearance of free charges is realized through the back channel effect, so as to improve the electrical performance of free charges on the threshold voltage, sub-threshold swing, and bias temperature stress of the first transistor T1 influence, thereby improving the display effect of the display panel and reducing the probability of problems such as afterimages occurring on the display panel.
  • the preparation material of the shielding layer 103 includes a semiconductor material or a metal material. Further, the preparation material of the shielding layer 103 includes amorphous silicon or at least one of molybdenum, aluminum, gold and silver.
  • the thickness of the shielding layer 103 is greater than or equal to 15 angstroms and less than or equal to 50 angstroms, so as to avoid the shielding layer 103 being too thin during the preparation process, causing the prepared shielding layer 103 cannot be continuously formed into a film, and the uniformity of the film thickness is poor. At the same time, it can also improve the influence of the thickness of the shielding layer 103 on the parameters such as the thickness of the display panel and the overall transmittance.
  • the thickness of the shielding layer 103 can be 15 angstroms, 16 angstroms, 19 angstroms, 20 angstroms, 25 angstroms, 28 angstroms, 30 angstroms, 31 angstroms, 35 angstroms, 40 angstroms meter, 42 angstrom, 45 angstrom, 48 angstrom, or 50 angstrom.
  • the display panel further includes a barrier layer 1012, a second substrate 1013, a first buffer layer 1014, and a second substrate 1013 stacked in sequence from the substrate 1011 toward the driving array 102.
  • Second buffer layer 1015 Second buffer layer 1015.
  • the second substrate 1013 includes a flexible substrate.
  • the preparation material of the second substrate 1013 includes polyimide.
  • the second buffer layer 1015 can adopt a single-layer design, or a multi-layer stack design. Further, the second buffer layer 1015 adopts a multi-layer stack design of silicon nitride, silicon oxide and amorphous silicon.
  • the shielding layer 103 may be located between the substrate 1011 and the barrier layer 1012, so as to shield the free charges in the substrate 1011 under the shielding layer 103, thereby reducing the The influence of free charges on the electrical performance of the first transistor T1.
  • the shielding layer 103 can be located between the barrier layer 1012 and the second substrate 1013, so as to store the free charges in the substrate 1011 and the charge between the substrate 1011 and the barrier layer 1012
  • the free charges existing at the junction are shielded under the shielding layer 103, thereby reducing the impact of the free charges in the substrate 1011 and the free charges existing at the junction of the substrate 1011 and the blocking layer 1012 on the first transistor T1 influence on the electrical properties.
  • the shielding layer 103 can be located between the second substrate 1013 and the first buffer layer 1014, so that the free charges in the substrate 1011, the substrate 1011 and the barrier layer The free charges existing at the junction of 1012 and the free charges of the second substrate 1013 are shielded under the shielding layer 103, thereby reducing the free charges in the substrate 1011, the substrate 1011 and the blocking layer 1012 The influence of the free charges existing at the junction of and the free charges in the second substrate 1013 on the electrical performance of the first transistor T1.
  • the shielding layer 103 can also be located between the first buffer layer 1014 and the second buffer layer 1015, at this time, the distance between the shielding layer 103 and the driving array 102 is relatively short, It can reduce the free charges in the substrate 1011, the free charges existing at the junction of the substrate 1011 and the barrier layer 1012, and the free charges in the second substrate 1013 to the electrical resistance of the first transistor T1. At the same time, it plays a better role in homogenizing the electric field.
  • the display panel may include multiple shielding layers 103 between the driving array 102 and the substrate 1011 , or may only include a single shielding layer 103 .
  • the display panel includes a first shielding layer between the substrate 1011 and the barrier layer 1012 , a second shielding layer between the barrier layer 1012 and the second substrate 1013 shielding layer, a third shielding layer located between the second substrate 1013 and the first buffer layer 1014, a fourth shielding layer located between the first buffer layer 1014 and the second buffer layer 1015 at least one of the four.
  • the fourth shielding layer adopts a patterned design.
  • the fourth shielding layer is set corresponding to the first active layer 1021 and the second active layer 1024, so as to form conductive channel, reduce the free charges in the substrate 1011, the free charges existing at the junction of the substrate 1011 and the barrier layer 1012, and the free charges in the second substrate 1013 to the operation of each of the transistors performance impact.
  • the shielding layer 103 is electrically connected to the first metal layer 1022, or the second metal layer 1023, or the third metal layer 1025, or the anode 1041, or the cathode 1042, To make the shielding layer 103 have a stable potential, so that when the pixel driving circuit is working, the amount of free charges absorbed by the gate voltage of the first transistor T1 is further reduced, thereby improving the free charges to the The influence of the electrical performance of the first transistor T1.
  • the second metal layer 1023 includes a first signal line VI1, and the shielding layer 103 is electrically connected to the first signal line VI1, so as to make the The shielding layer 103 has different potentials according to different requirements.
  • the shielding layer 103 is electrically connected to the first metal layer 1022, or the third metal layer 1025, or the anode 1041, or the cathode 1042, the shielding layer 103 and the The design of the electrical connection of the first signal line VI1, because the first signal line VI1 can make the shielding layer 103 have different potentials according to different requirements, so in realizing the adjustment of each of the transistors in the pixel driving circuit The electrical characteristics are less difficult.
  • the gate of the first transistor T1 is electrically connected to the first signal line VI1, so that the first signal transmitted through the first signal line VI1 is connected to the gate of the first transistor T1. pole to reset.
  • the second transistor T2 is electrically connected between the gate of the first transistor T1 and the first signal line VI1, and the second transistor T2 is used to transmit the first signal to the gate of the first transistor T1. Specifically, please continue to refer to FIG. 2A to FIG. 2B and FIG.
  • the second metal layer 1023 also includes the bottom gate of the second transistor T2, and the second active layer is located on the second metal layer 1023 , the active pattern of the second transistor T2 is located above the bottom gate of the second transistor T2;
  • the third metal layer 1025 includes the top gate of the second transistor T2;
  • the fourth metal Layer 1026 includes the source and drain of the first transistor T1, the source and drain of the first transistor T1 are electrically connected to the active pattern of the first transistor T1;
  • the fourth metal layer 1026 It also includes a source and a drain of the second transistor T2, the source and the drain of the second transistor T2 are electrically connected to the active pattern of the second transistor T2.
  • One of the source and drain of the second transistor T2 is electrically connected to the first signal line VI1, and the other of the source and drain of the second transistor T2 is connected to the first transistor T1
  • the grid is electrically connected.
  • At least one of the pixel driving circuits further includes a gate electrically connected to the gate of the first transistor T1 and the source and drain of the first transistor T1
  • a third transistor T3 in between, the third transistor T3 is used to transmit the data signal having the effect of compensating the threshold voltage of the first transistor T1 to the gate of the first transistor T1.
  • the second active layer 1024 also includes the active pattern of the third transistor T3; the second metal layer 1023 also includes the bottom gate of the third transistor T3, and the third transistor T3 The active pattern is located above the bottom gate of the third transistor T3; the third metal layer 1025 also includes the top gate of the third transistor T3, and the fourth metal layer 1026 also includes the first
  • the source and drain of the third transistor T3 are electrically connected to the active pattern of the third transistor T3.
  • One of the source and drain of the third transistor T3 is electrically connected to the gate of the first transistor T1, and the other of the source and drain of the third transistor T3 is connected to the first transistor T1.
  • One of the source and the drain of the transistor T1 is electrically connected.
  • At least one of the pixel driving circuits further includes a fourth transistor T4 , a fifth transistor T5 , a sixth transistor T6 , a seventh transistor T7 and a first capacitor C1 .
  • the second metal layer 1023 also includes a second signal line VI2;
  • the third metal layer 1025 includes a third signal line Nscan(n-1) and a fourth signal line Nscan(n);
  • the fourth metal layer 1026 A fifth signal line Data and a ninth signal line ELVDD are also included.
  • the first metal layer 1022 further includes a sixth signal line Pscan(n ⁇ 1), a seventh signal line Pscan(n) and an eighth signal line EM.
  • the scanning signal line ScanL includes the third signal line Nscan(n-1), the fourth signal line Nscan(n), the sixth signal line Pscan(n-1) and the seventh signal line Signal line Pscan(n);
  • the data line DL includes the fifth signal line Data.
  • the fourth transistor T4 is electrically connected between the fifth signal line Data and one of the source and drain of the first transistor T1, and the fourth transistor T4 is used to transmit the fifth signal
  • the data signal transmitted by the line Data is transmitted to one of the source and the drain of the first transistor T1.
  • the first active layer 1021 also includes the active pattern of the fourth transistor T4
  • the first metal layer 1022 also includes the gate of the fourth transistor T4, and the fourth metal layer 1026 It also includes a source and a drain of the fourth transistor T4, the source and the drain of the fourth transistor T4 are electrically connected to the active pattern of the fourth transistor T4.
  • One of the source and drain of the fourth transistor T4 is electrically connected to the fifth signal line Data, and the other of the source and drain of the fourth transistor T4 is connected to the first transistor T1
  • One of the source and the drain of the transistor T4 is electrically connected, and the gate of the fourth transistor T4 is electrically connected to the seventh signal line Pscan(n).
  • the fifth transistor T5 is electrically connected between the ninth signal line ELVDD and one of the source and the drain of the first transistor T1, and the sixth transistor T6 is electrically connected to the first transistor T1. between the source and the drain of the transistor T1 and the light emitting device, the fifth transistor T5 and the sixth transistor T6 are used to control the light emission control signal according to the eighth signal line EM
  • the first transistor T1 generates a driving current for driving the light emitting device to emit light.
  • the first active layer 1021 also includes the active pattern of the fifth transistor T5 and the active pattern of the sixth transistor T6, and the first metal layer 1022 also includes the fifth transistor T5 and the gate of the sixth transistor T6, the fourth metal layer 1026 also includes the source and drain of the fifth transistor T5 and the source and drain of the sixth transistor T6, so The source and drain of the fifth transistor T5 are electrically connected to the active pattern of the fifth transistor T5, and the source and drain of the sixth transistor T6 are electrically connected to the active pattern of the sixth transistor T6. sexual connection.
  • One of the source and the drain of the fifth transistor T5 is electrically connected to the ninth signal line ELVDD, and the other of the source and the drain of the fifth transistor T5 is connected to the first transistor T1
  • One of the source and drain is electrically connected.
  • One of the source and drain of the sixth transistor T6 is electrically connected to the anode 1041 of the light emitting device, and the other of the source and drain of the sixth transistor T6 is connected to the source of the first transistor T1
  • the other one of the electrode and the drain is electrically connected; the gate of the fifth transistor T5 and the gate of the sixth transistor T6 are electrically connected with the eighth signal line EM.
  • the seventh transistor T7 is electrically connected between the second signal line VI2 and the anode 1041 of the light emitting device, and the seventh transistor T7 is used for transmitting the second signal transmitted by the second signal line VI2 to the anode 1041 of the light emitting device to reset the anode voltage of the light emitting device.
  • the first active layer 1021 also includes the active pattern of the seventh transistor T7
  • the first metal layer 1022 also includes the gate of the seventh transistor T7
  • the fourth metal layer 1026 It also includes a source and a drain of the seventh transistor T7, the source and the drain of the seventh transistor T7 are electrically connected to the active pattern of the seventh transistor T7.
  • One of the source and drain of the seventh transistor T7 is electrically connected to the second signal line VI2, and the other of the source and drain of the seventh transistor T7 is connected to the anode of the light emitting device 1041 is electrically connected, and the gate of the seventh transistor T7 is electrically connected to the sixth signal line Pscan(n ⁇ 1).
  • the first capacitor C1 is connected in series between the gate of the first transistor T1 and the ninth signal line ELVDD.
  • the pixel driving circuit further includes: a storage capacitor, the storage capacitor includes a first capacitor electrode and a second capacitor electrode, and the first metal layer 1022 includes all electrodes electrically connected to the gate of the first transistor T1.
  • the first capacitor electrode, the second metal layer 1023 includes the second capacitor electrode opposite to the first capacitor electrode.
  • the first capacitor C1 can be the storage capacitor, further, the gate of the first transistor T1 and the gate of the first transistor T1 in the second metal layer 1023
  • the metal plate above the pole forms the lower plate and the upper plate of the first capacitor C1 respectively, that is, the lower plate of the first capacitor C1 can be configured as the first capacitor electrode, and the first The upper plate of the capacitor C1 may be configured as the second capacitor electrode.
  • the third signal line Nscan(n ⁇ 1) is electrically connected to the gate of the second transistor T2; the fourth signal line Nscan(n) is electrically connected to the gate of the third transistor T3.
  • the second transistor T2 and the third transistor T3 are N-type transistors, and the first transistor T1 and the fourth transistor T4 to the seventh transistor T7 are P-type transistors.
  • the first transistor T1 to the seventh transistor T7 include field effect transistors; further, the second transistor T2 and the third transistor T3 are metal oxide semiconductor field effect transistors, and the first A transistor T1 and the fourth transistor T4 to the seventh transistor T7 are thin film transistors.
  • the first signal transmitted by the first signal line VI1 may be a DC signal or an AC signal
  • the second signal transmitted by the second signal line VI2 is a DC signal
  • the first signal is a positive or negative direct current signal
  • the first signal can be greater than or smaller than the second signal, and can also be equal to the second signal.
  • the first signal is an AC signal; specifically, when the second transistor T2 is turned on, the first signal is equal to the second signal; when the second transistor T2 is turned off, the The first signal is equal to the signal transmitted in the ninth signal line ELVDD.
  • each pixel driving circuit is not limited to the 7T1C structure shown in FIG. 3 , and may also be 7T2C and other forms.
  • the shielding layer 103 may be in a whole-surface design, or in a patterned design.
  • the shielding layer 103 adopts a patterned design. Specifically, please refer to FIG. 4A to FIG. 4D , taking the display panel adopting the pixel driving circuit shown in FIG. 3 as an example, the patterned design of the shielding layer 103 will be described.
  • the shielding layer 103 includes a first shielding portion 1031 located between the active pattern of the first transistor T1 and the substrate 1011, the The first shielding part 1031 is electrically connected to a preset stable voltage through the second metal layer 1023, specifically, the first shielding part 1031 is electrically connected to the second metal layer 1023 to have the preset stable voltage. Voltage.
  • the driving array further includes a first insulating layer 1051 located on the first active layer 1021 and the second buffer layer 1015, and located on the first insulating layer 1051 and the first metal layer 1022.
  • the second insulating layer 1052 on the second metal layer 1023 and the first dielectric layer 1053 on the second insulating layer 1052, the first dielectric layer 1053 and the second active layer
  • the third insulating layer 1054 on 1024, the second dielectric layer 1055 on the third insulating layer 1054 and the third metal layer 1025, the fourth metal layer 1026 and the second dielectric layer A protection layer 1056 on the protection layer 1055, and a planarization layer 1057 on the protection layer 1056.
  • the second metal layer 1023 may have a preset stable voltage
  • the first shielding part 1031 is located between the first buffer layer 1014 and the second buffer layer 1015
  • the first shielding part 1031 The first via hole 100a passing through the second buffer layer 1015, the first insulating layer 1051 and the second insulating layer 1052 is electrically connected to the second metal layer 1023, that is, the first shielding portion
  • the potential of 1031 may be the same as the potential of the second metal layer 1023, and both are equal to the preset stable voltage.
  • the orthographic projection of the first transistor T1 on the substrate 1011 is located within the orthographic projection of the first shielding portion 1031 on the substrate 1011 .
  • the orthographic projection of the gate of the first transistor T1 on the substrate 1011 is located within the orthographic projection of the first shielding portion 1031 on the substrate 1011, so as to utilize the The first shielding portion 1031 shields the free charges under the first shielding portion 1031 to reduce the influence of the free charges on the electrical performance of the first transistor T1.
  • first shielding portion 1031 is electrically connected to the first signal line VI1.
  • the first shielding portion 1031 is disposed opposite to the first capacitor electrode. It can be understood that on the basis that the first capacitor electrode and the second capacitor electrode are arranged opposite to form the storage capacitor, the first shielding part 1031 is arranged opposite to the first capacitor electrode to form a The storage capacitor is connected in parallel with the auxiliary capacitor. Similarly, when the storage capacitor is the first capacitor C1, that is, when the first capacitor electrode is the gate of the first transistor T1, since the first shielding part 1031 corresponds to the first transistor T1 The active pattern of T1, the gate of the first transistor T1 also corresponds to the active pattern of the first transistor T1, therefore, the first shielding part 1031 and the gate of the first transistor T1 can form a second The second capacitor CL is used as the auxiliary capacitor.
  • the first signal when the second transistor T2 is turned on, the first signal is equal to the second signal; when the second transistor T2 is turned off, the first signal is equal to the ninth signal line
  • the signals transmitted in ELVDD are equal, and the first shielding part 1031 is electrically connected to the first signal line VI1, then when the second transistor T2 is turned on, the second capacitor CL is blocked due to the equal potential at both ends. short circuit, the first signal resets the gate of the first transistor T1; when the second transistor T2 is cut off, the second capacitor CL is connected in parallel with the first capacitor C1, increasing the The capacitance in the pixel driving circuit is more conducive to sufficient writing of the data signal carried by the fifth signal line Data.
  • the shielding layer 103 further includes a second shielding line 1032, and the second shielding line 1032 is located between the active pattern of the second transistor T2 and the substrate 1011 , the second shielding wire 1032 is electrically connected to the first shielding portion 1031 .
  • the first signal transmitted by the first signal line VI1 may be different from the second signal transmitted by the second signal line VI2, in a top view, the first signal line VI1 and the second signal line VI2 interval setting.
  • the first signal line VI1 is close to the second shielding line 1032 in a plan view, the first shielding portion 1031 can be connected to the first signal line through the second shielding line 1032 . Electrical connection of VI1.
  • the shielding layer 103 further includes a third shielding line 1033, the third shielding line 1033 is located between the active pattern of the third transistor T3 and the substrate 1011, the third shielding line 1033 is connected to The second shielding wire 1032 and the first shielding part 1031 are electrically connected, that is, the first shielding part 1031 can be connected to the first shielding part 1031 through the third shielding wire 1033 and the second shielding wire 1032.
  • the shielding layer 103 further includes a fourth shielding line 1034 located between the active pattern of the fourth transistor T4 and the substrate 1011, as shown in FIG. 4B and FIG. 4D; the shielding layer 103 also includes a fifth shielding line 1035 located between the active pattern of the fifth transistor T5 and the substrate 1011, and between the active pattern of the sixth transistor T6 and the substrate 1011 The sixth shielding line 1036, and the seventh shielding line 1037 located between the active pattern of the seventh transistor T7 and the substrate 1011, as shown in FIG. 4D.
  • the fourth shielded wire 1034 , the fifth shielded wire 1035 , the sixth shielded wire 1036 and the seventh shielded wire 1037 are spaced apart from each other, or are in contact with each other.
  • the fourth shielding wire 1034 , the fifth shielding wire 1035 , the sixth shielding wire 1036 or the seventh shielding wire 1037 may be electrically connected to the second metal layer 1023 , or may not be connected to the second metal layer 1023 .
  • the two metal layers 1023 are electrically connected.
  • the first shielded part 1031, the second shielded wire 1032, the third shielded wire 1033, the fourth shielded wire 1034, the fifth shielded wire 1035, the sixth shielded wire 1036 and the seventh shielded wire 1037 may be arranged on the same layer, or may be located on different layers respectively.
  • the orthographic projection of the second transistor T2 on the substrate 1011 is located within the orthographic projection of the second shielding line 1032 on the substrate 1011; the third transistor T3 is in The orthographic projection on the substrate 1011 is located within the orthographic projection of the third shielding line 1033 on the substrate 1011; the orthographic projection of the fourth transistor T4 on the substrate 1011 is located in the fourth shielding line 1034 In the orthographic projection on the substrate 1011; the orthographic projection of the fifth transistor T5 on the substrate 1011 is located in the orthographic projection of the fifth shielding line 1035 on the substrate 1011; the sixth transistor The orthographic projection of T6 on the substrate 1011 is located within the orthographic projection of the sixth shielding line 1036 on the substrate 1011; the orthographic projection of the seventh transistor T7 on the substrate 1011 is located in the seventh shielding line 1036 The orthographic projection of the line 1037 on the substrate 1011 is used to reduce the impact of free charges on the electrical properties of the second transistor T2 to the seventh transistor T7.
  • the whole-surface design of the shielding layer 103 can save preparation of photomasks and production capacity, more materials will be used, and the effect of homogenizing the electric field achieved is poor, and crosstalk is likely to occur.
  • the patterned design of the shielding layer 103 will increase the manufacturing process and production capacity, the effect of homogenizing the electric field is better, and it is not conducive to the formation of parasitic capacitance, which can reduce the probability of crosstalk problems and reduce the amount of materials used.
  • the source and drain of the second transistor T2 are electrically connected to the active pattern of the second transistor T2 through the second via hole 100b passing through the third insulating layer 1054 and the second dielectric layer 1055 ;
  • the source and drain of the third transistor T3 are electrically connected to the active pattern of the third transistor T3 through the second via hole 100b.
  • the source and drain of the fourth transistor T4 pass through the first insulating layer 1051 , the second insulating layer 1052 , the first dielectric layer 1053 , the third insulating layer 1054 and the first insulating layer 1051 .
  • the third via hole 100c of the second dielectric layer 1055 is electrically connected to the active pattern of the fourth transistor T4.
  • the source and drain of the fifth transistor T5 are electrically connected to the active pattern of the fifth transistor T5 through the third via hole 100c
  • the source and drain of the sixth transistor T6 are electrically connected to the active pattern of the fifth transistor T5.
  • the drain is electrically connected to the active pattern of the sixth transistor T6 through the third via hole 100c.
  • the source and drain of the seventh transistor T7 are electrically connected to the active pattern of the seventh transistor T7 through the third via hole 100c.
  • the display panel further includes a pixel definition layer 106 and an encapsulation layer 107, the light emitting layer 1043 is located in the pixel definition area of the pixel definition layer 106, and the encapsulation layer 107 is located in the on the light emitting device. It can be understood that the display panel further includes unshown parts such as polarizers and touch electrodes.
  • FIG. 5A to FIG. 5C are schematic diagrams of the manufacturing process of the manufacturing method of the display panel provided in the embodiments of the present application.
  • Embodiments of the present application also provide a method for preparing a display panel, which is used for preparing any one of the above-mentioned display panels. Specifically, the preparation method comprises the following steps:
  • Step S10 providing the substrate 1011;
  • Step S20 preparing the shielding layer 103 on the substrate 1011, as shown in FIG. 5A;
  • Step S30 preparing the driving array 102 on the shielding layer 103 , as shown in FIG. 5B .
  • the method further includes: preparing the sub-pixels 100 and the encapsulation layer 107 on the driving array 102 , as shown in FIG. 5C .
  • an anode 1041, a pixel definition layer 106, a light-emitting layer 1043, and a cathode 1042 are sequentially prepared on the driving array 102, the packaging layer 107 is located on the cathode 1042, and the light-emitting layer 1043 is located on the pixel definition layer.
  • the step S10 further includes: sequentially preparing a barrier layer 1012 , a second substrate 1013 , and a first buffer layer 1014 on the substrate 1011 , and the shielding layer 103 is located on the first buffer layer 1014 .
  • the step S20 also includes: preparing a second buffer layer 1015 on the shielding layer 103 .
  • step S20 also includes patterning the shielding layer 103 .
  • the step S30 also includes: sequentially preparing the first active layer 1021, the first insulating layer 1051, the patterned first metal layer 1022, the second insulating layer 1052, the patterned The second metal layer 1023, the first dielectric layer 1053, the second active layer 1024, the third insulating layer 1054, the patterned third metal layer 1025, the second dielectric layer 1055, the patterned fourth metal layer 1026 , a protection layer 1056 and a flat layer 1057 .
  • the shielding layer 103 is electrically connected to the second metal layer 1023 through a first via hole penetrating through the second buffer layer 1015 , the first insulating layer 1051 and the second insulating layer 1052 .
  • An embodiment of the present application further provides a display device, including any one of the above-mentioned display panels.
  • the display device includes a fixed terminal (such as a TV, a desktop computer, etc.), a mobile terminal (such as a mobile phone, a notebook computer, etc.), and a wearable device (such as a bracelet, a virtual display device, an enhanced display device, etc.) and the like.
  • a fixed terminal such as a TV, a desktop computer, etc.
  • a mobile terminal such as a mobile phone, a notebook computer, etc.
  • a wearable device such as a bracelet, a virtual display device, an enhanced display device, etc.

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Abstract

一种显示面板及显示装置，包括基板(1011)，位于基板(1011)上的驱动阵列(102)包括第一有源层(1021)、第二有源层(1023)及堆叠于第一有源层(1021)上的第一金属层(1022)，第一晶体管(T1)的有源图案和栅极分别包含于第一有源层(1021)和第一金属层(1022)，第二晶体管(T2)的有源图案包含于第二有源层(1023)，第一晶体管(T1)的有源图案和基板(1011)之间设有具有预设稳定电压的第一屏蔽部(1031)。

Description

显示面板及显示装置 技术领域
本申请涉及显示技术领域，具体涉及显示面板及显示装置。
 背景技术
低温多晶氧化物背板相较于低温多晶硅背板因具有电荷迁移率高、稳定性好等优势被应用于显示面板中，但低温多晶氧化物背板中存在一些自由电荷，当晶体管工作时，在电场的作用下会形成背栅结构，影响晶体管的阈值电压、亚阈值摆幅及偏置温度应力等，从而影响显示面板的显示效果，导致显示面板出现残影等问题。
 技术问题
本申请实施例提供显示面板及显示装置，可以改善自由电荷对晶体管电学性能的影响。
 技术解决方案
本申请实施例提供显示面板，所述显示面板包括基板、驱动阵列以及屏蔽层。所述驱动阵列包括位于所述基板上的第一有源层、第二有源层、位于所述第一有源层上的第一金属层以及位于所述第一金属层上的第二金属层。所述第一有源层包括硅半导体材料，所述第二有源层包括氧化物半导体材料。所述驱动阵列包括多个像素驱动电路，至少一所述像素驱动电路包括第一晶体管和第二晶体管。其中所述第一有源层包括所述第一晶体管的有源图案，所述第二有源层包括所述第二晶体管的有源图案，所述第一金属层包括所述第一晶体管的栅极。所述屏蔽层包括位于所述第一晶体管的所述有源图案和所述基板之间的第一屏蔽部，所述第一屏蔽部通过所述第二金属层与预设稳定电压电性连接。
 有益效果
在本申请的实施例提供的显示面板及显示装置中，所述显示面板包括基板、驱动阵列以及屏蔽层，屏蔽层位于驱动阵列与基板之间，屏蔽层与驱动阵列中的第二金属层电性连接，以通过屏蔽层将自由电荷阻挡在屏蔽层下方。当驱动阵列中包括的晶体管工作时，在电场的作用下通过背沟道效应实现自由电荷的快速移动和消失，从而改善自由电荷对晶体管的电学性能的影响。
 附图说明
下面结合附图，通过对本申请的具体实施方式详细描述，将使本申请的技术方案及其它有益效果显而易见。
图1是本申请实施例提供的显示面板的结构示意图；
图2A至图2B是本申请实施例提供的显示面板的截面结构示意图；
图3是本申请实施例提供的像素驱动电路的结构示意图；
图4A至图4D是显示面板采用图3所示的像素驱动电路的俯视结构示意图；
图5A至图5C是本申请的实施例提供的显示面板的制备过程示意图。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。此外，应当理解的是，此处所描述的具体实施方式仅用于说明和解释本申请，并不用于限制本申请。在本申请中，在未作相反说明的情况下，使用的方位词如“上”和“下”通常是指装置实际使用或工作状态下的上和下，具体为附图中的图面方向；而“内”和“外”则是针对装置的轮廓而言的。
具体地，图1是本申请实施例提供的显示面板的结构示意图。可选地，本申请实施例提供的所述显示面板可以为但不限于被动式发光显示面板、自发光显示面板、量子点显示面板等。进一步地，被动式发光显示面板包括液晶显示面板，自发光显示面板包括具有发光器件的显示面板。
所述显示面板包括显示区和位于所述显示区外围的非显示区，所述显示区用于使所述显示面板实现显示功能，所述显示面板在所述非显示区内无显示功能。
可选地，所述显示面板还包括感应区，所述感应区位于所述非显示区内、所述显示区内、所述显示区与所述非显示区的交界处三者中的至少一者；所述感应区可兼顾显示功能或感测功能，也可仅具有感测功能。进一步地，所述显示面板包括设于所述感应区的传感器。可选地，所述传感器可以包括摄像头、指纹传感器、距离传感器、声音传感器、环境光传感器等。
请继续参阅图1，所述显示面板包括多个子像素100、多条数据线DL及多条扫描线ScanL，多个所述子像素100位于所述显示区内，每一所述子像素100与对应的所述数据线DL和所述扫描线ScanL电性连接。可选地，多个所述子像素100的发光颜色可以包括红色、绿色、蓝色、白色、黄色等，所述数据线DL与所述扫描线ScanL交叉设置。
进一步地，当所述显示面板为液晶显示面板时，每一所述子像素100通过像素电极与公共电极之间形成的电场促使液晶分子发生偏转，通过彩膜单元配合液晶分子实现所述子像素100的显示。其中，所述像素电极形成于阵列基板侧，所述公共电极形成于彩膜基板侧，或所述像素电极和所述公共电极共同形成于阵列基板侧；所述液晶分子位于所述阵列基板和所述彩膜基板之间；彩膜单元可形成于所述阵列基板侧，也可形成于所述彩膜基板侧。
进一步地，当所述显示面板为自发光显示面板时，每一所述子像素100可由发光器件形成。其中，所述发光器件包括有机发光二极管、次毫米发光二极管或微型发光二极管等。
如图2A至图2B是本申请实施例提供的显示面板的截面结构示意图，如图3是本申请实施例提供的像素驱动电路的结构示意图，以所述显示面板为自发光显示面板为例，对所述显示面板的结构及工作原理等内容进行说明。
所述显示面板包括基板1011、驱动阵列102、屏蔽层103及发光器件。
所述基板1011为柔性基板。具体地，所述基板1011的制备材料包括聚酰亚胺。
所述驱动阵列102位于所述基板1011上，所述驱动阵列102包括多个所述像素驱动电路，每一所述像素驱动电路与对应的至少一所述子像素100电性连接。可选地，在所述显示区内，一所述像素驱动电路与一所述子像素100电性连接，以使一像素驱动电路驱动一所述子像素100发光；在所述感测区可实现所述显示面板的显示功能时，一所述像素驱动电路与位于所述感测区内的多个所述子像素100电性连接，以通过一所述像素驱动电路驱动多个所述子像素100发光。其中，所述子像素100由所述发光器件形成。所述发光器件包括阳极1041、阴极1042及位于所述阳极1041和所述阴极1042之间的发光层1043。可选地，所述发光层1043包括荧光材料、量子点材料或钙钛矿材料。
请继续参阅图2A至图2B，在所述显示面板的纵截面视角下，所述驱动阵列102包括位于所述基板1011上的第一有源层1021、位于所述第一有源层1021上的第一金属层1022、位于所述第一金属层1022上的第二金属层1023、位于所述第二金属层1023上的第二有源层1024、位于所述第二有源层1024上的第三金属层1025及位于所述第三金属层1025上的第四金属层1026。
其中，所述第一有源层1021包括硅半导体材料，所述第二有源层1024包括氧化物半导体材料。可选地，所述硅半导体材料包括单晶硅、多晶硅或非晶硅等；所述氧化物半导体材料包括锌、铟、镓、锡或钛的金属的氧化物中的至少一种；进一步地，所述氧化物半导体材料包括氧化锌、氧化锌锡、氧化锌铟、氧化铟、氧化钛、氧化铟镓锌或氧化铟锌锡等。
进一步地，请继续参阅图2A至图2B、图3，至少一所述像素驱动电路包括第一晶体管T1和第二晶体管T2。其中，所述第一有源层1021包括所述第一晶体管T1的有源图案，所述第二有源层1024包括所述第二晶体管T2的有源图案，所述第一金属层1022包括所述第一晶体管T1的栅极，所述第二金属层1023包括位于所述第一晶体管T1的所述栅极的上方的金属板。
所述屏蔽层103位于所述基板1011与所述驱动阵列102之间，以利用所述屏蔽层103将所述基板1011中的自由电荷屏蔽在所述基板1011下，从而在所述像素驱动电路工作时，在电场的作用下，通过背沟道效应实现自由电荷的快速移动和消失，以改善自由电荷对所述第一晶体管T1的阈值电压、亚阈值摆幅、偏置温度应力等电学性能的影响，从而改善显示面板的显示效果，降低所述显示面板出现残影等问题的几率。
可选地，所述屏蔽层103的制备材料包括半导体材料或金属材料。进一步地，所述屏蔽层103的制备材料包括非晶硅或钼、铝、金、银中的至少一种。
可选地，所述屏蔽层103的厚度大于或等于15埃米且小于或等于50埃米，以避免在制备过程时，因所述屏蔽层103的厚度太薄，致使制备的所述屏蔽层103无法连续成膜，膜厚均一性较差的问题，同时也可改善因所述屏蔽层103的厚度太厚对所述显示面板的厚度、整体透过率等参数造成的影响。具体地，所述屏蔽层103的厚度可以为15埃米、16埃米、19埃米、20埃米、25埃米、28埃米、30埃米、31埃米、35埃米、40埃米、42埃米、45埃米、48埃米或50埃米。
进一步地，请继续参阅图2A至图2B，所述显示面板还包括自所述基板1011向所述驱动阵列102方向依次层叠的阻挡层1012、第二衬底1013、第一缓冲层1014及第二缓冲层1015。
所述第二衬底1013包括柔性衬底。可选地，所述第二衬底1013的制备材料包括聚酰亚胺。
所述第二缓冲层1015可采用单膜层设计，也可采用多膜层叠构设计。进一步地，所述第二缓冲层1015采用氮化硅、氧化硅和非晶硅的多膜层叠构设计。
可选地，所述屏蔽层103可位于所述基板1011与所述阻挡层1012之间，以将所述基板1011中具有的自由电荷屏蔽在所述屏蔽层103下，从而降低所述基板1011中自由电荷对所述第一晶体管T1的电学性能的影响。
可选地，所述屏蔽层103可位于所述阻挡层1012与所述第二衬底1013之间，以将所述基板1011中具有的自由电荷及所述基板1011与所述阻挡层1012的交界处存在的自由电荷屏蔽在所述屏蔽层103下，从而降低所述基板1011中的自由电荷及所述基板1011与所述阻挡层1012的交界处存在的自由电荷对所述第一晶体管T1的电学性能的影响。
可选地，所述屏蔽层103可位于所述第二衬底1013与所述第一缓冲层1014之间，以将所述基板1011中具有的自由电荷、所述基板1011与所述阻挡层1012的交界处存在的自由电荷及所述第二衬底1013具有的自由电荷屏蔽在所述屏蔽层103下，从而降低所述基板1011中的自由电荷、所述基板1011与所述阻挡层1012的交界处存在的自由电荷及所述第二衬底1013中的自由电荷对所述第一晶体管T1的电学性能的影响。
可选地，所述屏蔽层103还可位于所述第一缓冲层1014与所述第二缓冲层1015之间，此时所述屏蔽层103与所述驱动阵列102之间的距离较近，可在降低所述基板1011中的自由电荷、所述基板1011与所述阻挡层1012的交界处存在的自由电荷及所述第二衬底1013中的自由电荷对所述第一晶体管T1的电学性能的影响的同时，起到较好的均化电场的作用。
可选地，所述显示面板在所述驱动阵列102与所述基板1011之间可包括多个所述屏蔽层103，也可仅包括单个所述屏蔽层103。如在一些实施例中，所述显示面板包括位于所述基板1011与所述阻挡层1012之间的第一屏蔽层、位于所述阻挡层1012与所述第二衬底1013之间的第二屏蔽层、位于所述第二衬底1013与所述第一缓冲层1014之间的第三屏蔽层、位于所述第一缓冲层1014与所述第二缓冲层1015之间的第四屏蔽层四者中的至少一者。进一步地，第四屏蔽层采用图案化设计。可选地，在俯视视角下，所述第四屏蔽层对应于所述第一有源层1021和所述第二有源层1024设置，以在所述像素驱动电路包括的各晶体管分别形成导电沟道时，降低所述基板1011中的自由电荷、所述基板1011与所述阻挡层1012的交界处存在的自由电荷及所述第二衬底1013中的自由电荷对各所述晶体管的工作性能的影响。
可选地，所述屏蔽层103与所述第一金属层1022、或所述第二金属层1023或所述第三金属层1025、或所述阳极1041、或所述阴极1042电性连接，以使所述屏蔽层103具有一个稳定的电位，从而在所述像素驱动电路工作时，进一步减小所述第一晶体管T1的栅极电压对自由电荷的吸附量，进而改善自由电荷对所述第一晶体管T1的电学性能的影响。
进一步地，如图3所示，所述第二金属层1023包括第一信号线VI1，所述屏蔽层103与所述第一信号线VI1电性连接，以便通过所述第一信号线VI1使所述屏蔽层103根据不同的需求具有不同的电位。相较于所述屏蔽层103与所述第一金属层1022、或所述第三金属层1025、或所述阳极1041、或所述阴极1042电性连接的设计，所述屏蔽层103与所述第一信号线VI1电性连接的设计，因所述第一信号线VI1可使所述屏蔽层103根据不同的需求具有不同的电位，所以在实现调整所述像素驱动电路中各所述晶体管的电学特性方面的难度较低。
请继续参阅图3，所述第一晶体管T1的栅极与所述第一信号线VI1电性连接，以通过所述第一信号线VI1传输的第一信号对所述第一晶体管T1的栅极进行复位。
进一步地，所述第二晶体管T2电性连接于所述第一晶体管T1的所述栅极和所述第一信号线VI1之间，所述第二晶体管T2用于使所述第一信号传输至所述第一晶体管T1的栅极。具体地，请继续参阅图2A至图2B、图3，所述第二金属层1023还包括所述第二晶体管T2的底栅，所述第二有源层位于所述第二金属层1023上，所述第二晶体管T2的所述有源图案位于所述第二晶体管T2的所述底栅上方；所述第三金属层1025包括所述第二晶体管T2的顶栅；所述第四金属层1026包括所述第一晶体管T1的源极和漏极，所述第一晶体管T1的源极和漏极与所述第一晶体管T1的有源图案电性连接；所述第四金属层1026还包括所述第二晶体管T2的源极和漏极，所述第二晶体管T2的源极和漏极与所述第二晶体管T2的有源图案电性连接。所述第二晶体管T2的源极和漏极中的一个与所述第一信号线VI1电性连接，所述第二晶体管T2的源极和漏极中的另一个与所述第一晶体管T1的栅极电性连接。
请继续图2A至图2B、图3，至少一所述像素驱动电路还包括电性连接于所述第一晶体管T1的所述栅极与所述第一晶体管T1的源极和漏极中的一个之间的第三晶体管T3，所述第三晶体管T3用于将具有补偿所述第一晶体管T1的阈值电压作用的数据信号传输至所述第一晶体管T1的栅极。具体地，所述第二有源层1024还包括所述第三晶体管T3的有源图案；所述第二金属层1023还包括所述第三晶体管T3的底栅，所述第三晶体管T3的所述有源图案位于所述第三晶体管T3的所述底栅上方；所述第三金属层1025还包括所述第三晶体管T3的顶栅，所述第四金属层1026还包括所述第三晶体管T3的源极和漏极，所述第三晶体管T3的源极和漏极与所述第三晶体管T3的有源图案电性连接。所述第三晶体管T3的源极和漏极中的一个与所述第一晶体管T1的栅极电性连接，所述第三晶体管T3的源极和漏极中的另一个与所述第一晶体管T1的源极和漏极中的一个电性连接。
请继续图2A至图2B、图3，至少一所述像素驱动电路还包括第四晶体管T4、第五晶体管T5、第六晶体管T6、第七晶体管T7及第一电容C1。所述第二金属层1023还包括第二信号线VI2；所述第三金属层1025包括第三信号线Nscan(n-1)及第四信号线Nscan(n)；所述第四金属层1026还包括第五信号线Data和第九信号线ELVDD。所述第一金属层1022还包括第六信号线Pscan(n-1)、第七信号线Pscan(n)及第八信号线EM。其中，所述扫描信号线ScanL包括所述第三信号线Nscan(n-1)、所述第四信号线Nscan(n)、所述第六信号线Pscan(n-1)及所述第七信号线Pscan(n)；所述数据线DL包括所述第五信号线Data。
所述第四晶体管T4电性连接于所述第五信号线Data与所述第一晶体管T1的源极和漏极中的一个之间，所述第四晶体管T4用于将所述第五信号线Data传输的数据信号传输至所述第一晶体管T1的源极和漏极中的一个。具体地，所述第一有源层1021还包括所述第四晶体管T4的有源图案，所述第一金属层1022还包括所述第四晶体管T4的栅极，所述第四金属层1026还包括所述第四晶体管T4的源极和漏极，所述第四晶体管T4的源极和漏极与所述第四晶体管T4的有源图案电性连接。所述第四晶体管T4的源极和漏极中的一个与所述第五信号线Data电性连接，所述第四晶体管T4的源极和漏极中的另一个与所述第一晶体管T1的源极和漏极中的一个电性连接，所述第四晶体管T4的栅极与所述第七信号线Pscan(n)电性连接。
所述第五晶体管T5电性连接于所述第九信号线ELVDD与所述第一晶体管T1的源极和漏极中的一个之间，所述第六晶体管T6电性连接于所述第一晶体管T1的源极和漏极中的另一个与所述发光器件之间，所述第五晶体管T5和所述第六晶体管T6用于根据所述第八信号线EM载入的发光控制信号控制所述第一晶体管T1产生驱动所述发光器件发光的驱动电流。具体地，所述第一有源层1021还包括所述第五晶体管T5的有源图案和所述第六晶体管T6的有源图案，所述第一金属层1022还包括所述第五晶体管T5的栅极和所述第六晶体管T6的栅极，所述第四金属层1026还包括所述第五晶体管T5的源极和漏极以及所述第六晶体管T6的源极和漏极，所述第五晶体管T5的源极和漏极与所述第五晶体管T5的有源图案电性连接，所述第六晶体管T6的源极和漏极与所述第六晶体管T6的有源图案电性连接。所述第五晶体管T5的源极和漏极中的一个与所述第九信号线ELVDD电性连接，所述第五晶体管T5的源极和漏极中的另一个与所述第一晶体管T1的源极和漏极中的一个电性连接。所述第六晶体管T6的源极和漏极中的一个与发光器件的阳极1041电性连接，所述第六晶体管T6的源极和漏极中的另一个与所述第一晶体管T1的源极和漏极中的另一个电性连接；所述第五晶体管T5的栅极和所述第六晶体管T6的栅极与所述第八信号线EM电性连接。
所述第七晶体管T7电性连接于所述第二信号线VI2与所述发光器件的阳极1041之间，所述第七晶体管T7用于将所述第二信号线VI2传输的第二信号传输至所述发光器件的阳极1041，以对所述发光器件的阳极电压进行复位。具体地，所述第一有源层1021还包括所述第七晶体管T7的有源图案，所述第一金属层1022还包括所述第七晶体管T7的栅极，所述第四金属层1026还包括所述第七晶体管T7的源极和漏极，所述第七晶体管T7的源极和漏极与所述第七晶体管T7的有源图案电性连接。所述第七晶体管T7的源极和漏极中的一个与所述第二信号线VI2电性连接，所述第七晶体管T7的源极和漏极中的另一个与所述发光器件的阳极1041电性连接，所述第七晶体管T7的栅极与所述第六信号线Pscan(n-1)电性连接。
所述第一电容C1串联在所述第一晶体管T1的所述栅极与所述第九信号线ELVDD之间。其中，所述像素驱动电路还包括：储存电容，所述储存电容包括第一电容电极和第二电容电极，所述第一金属层1022包括与所述第一晶体管T1的栅极电连接的所述第一电容电极，所述第二金属层1023包括与所述第一电容电极相对设置的所述第二电容电极。其中，所述第一电容C1即可以为所述存储电容，进一步的，所述第一晶体管T1的所述栅极与所述第二金属层1023中位于所述第一晶体管T1的所述栅极的上方的所述金属板分别形成所述第一电容C1的下极板和上极板，即所述第一电容C1的下极板可以配置为所述第一电容电极，所述第一电容C1的上极板可以配置为所述第二电容电极。
所述第三信号线Nscan(n-1)与所述第二晶体管T2的栅极电性连接；所述第四信号线Nscan(n)与所述第三晶体管T3的栅极电性连接。
可选地，所述第二晶体管T2及所述第三晶体管T3为N型晶体管，所述第一晶体管T1及所述第四晶体管T4至所述第七晶体管T7为P型晶体管。可选地，所述第一晶体管T1至所述第七晶体管T7包括场效应管；进一步地，所述第二晶体管T2及所述第三晶体管T3为金属氧化物半导体场效应晶体管，所述第一晶体管T1及所述第四晶体管T4至所述第七晶体管T7为薄膜晶体管。
可选地，所述第一信号线VI1传输的第一信号可为直流信号或交流信号，所述第二信号线VI2传输的第二信号为直流信号。进一步地，所述第一信号为可正或可负的直流信号，所述第一信号可大于或小于所述第二信号，也可与所述第二信号相等。进一步地，所述第一信号为交流信号；具体地，在所述第二晶体管T2导通时，所述第一信号与所述第二信号相等；在所述第二晶体管T2截止时，所述第一信号与所述第九信号线ELVDD中传输的信号相等。
可以理解的，在实际应用中，每一所述像素驱动电路的结构不限于如图3所示的7T1C的结构形式，还可为7T2C等形式。
可选地，所述屏蔽层103可呈整面设计，也可采用图案化设计。
进一步地，所述屏蔽层103采用图案化设计。具体地，请参阅图4A~图4D，以所述显示面板采用图3所示的像素驱动电路为例，对所述屏蔽层103采用图案化的设计进行说明。
请继续参阅图2B、图3、图4A至图4D，所述屏蔽层103包括位于所述第一晶体管T1的所述有源图案和所述基板1011之间的第一屏蔽部1031，所述第一屏蔽部1031通过所述第二金属层1023与预设稳定电压电性连接，具体的，所述第一屏蔽部1031与所述第二金属层1023电性连接以具有所述预设稳定电压。
具体地，所述驱动阵列还包括位于所述第一有源层1021及所述第二缓冲层1015上的第一绝缘层1051，位于所述第一绝缘层1051及所述第一金属层1022上的第二绝缘层1052，位于所述第二金属层1023及所述第二绝缘层1052上的第一介电层1053，位于所述第一介电层1053及所述第二有源层1024上的第三绝缘层1054，位于所述第三绝缘层1054及所述第三金属层1025上的第二介电层1055，位于所述第四金属层1026及所述第二介电层1055上的保护层1056，以及位于所述保护层1056上的平坦层1057。具体的，所述第二金属层1023可以具有预设稳定电压，所述第一屏蔽部1031位于所述第一缓冲层1014与所述第二缓冲层1015之间，所述第一屏蔽部1031通过贯穿所述第二缓冲层1015、所述第一绝缘层1051及所述第二绝缘层1052的第一过孔100a与所述第二金属层1023电性连接，即所述第一屏蔽部1031的电位可以与所述第二金属层1023的电位相同，均等于所述预设稳定电压。
可选地，在俯视视角下，所述第一晶体管T1在所述基板1011上的正投影位于所述第一屏蔽部1031在所述基板1011上的正投影内。进一步地，在俯视视角下，所述第一晶体管T1的所述栅极在所述基板1011上的正投影位于所述第一屏蔽部1031在所述基板1011上的正投影内，以利用所述第一屏蔽部1031将自由电荷屏蔽在所述第一屏蔽部1031下，降低自由电荷对所述第一晶体管T1的电学性能的影响。
进一步地，所述第一屏蔽部1031与所述第一信号线VI1电性连接。
具体的，所述第一屏蔽部1031与所述第一电容电极相对设置。可以理解的，在所述第一电容电极和所述第二电容电极相对设置以形成所述储存电容的基础上，将所述第一屏蔽部1031与所述第一电容电极相对设置可以形成与所述储存电容并联的辅助电容。同理，当所述存储电容为所述第一电容C1时，即第一电容电极为所述第一晶体管T1的所述栅极时，由于所述第一屏蔽部1031对应所述第一晶体管T1的有源图案，所述第一晶体管T1的栅极也对应所述第一晶体管T1的有源图案，因此，所述第一屏蔽部1031与所述第一晶体管T1的栅极可形成第二电容CL作为所述辅助电容。进一步地，若在所述第二晶体管T2导通时，所述第一信号与所述第二信号相等；在所述第二晶体管T2截止时，所述第一信号与所述第九信号线ELVDD中传输的信号相等，所述第一屏蔽部1031与所述第一信号线VI1电性连接，则在所述第二晶体管T2导通时，所述第二电容CL因两端电位相等被短路，所述第一信号对所述第一晶体管T1的栅极进行复位；在所述第二晶体管T2截止时，所述第二电容CL与所述第一电容C1并联，增大了所述像素驱动电路中的电容量，更利于所述第五信号线Data载入的数据信号的充分写入。
进一步地，请继续参阅图4C至图4D，所述屏蔽层103还包括第二屏蔽线1032，所述第二屏蔽线1032位于所述第二晶体管T2的有源图案和所述基板1011之间，所述第二屏蔽线1032与所述第一屏蔽部1031电性连接。
由于所述第一信号线VI1传输的第一信号可不同于所述第二信号线VI2传输的第二信号，因此，在俯视视角下，所述第一信号线VI1和所述第二信号线VI2间隔设置。此外，由于在俯视视角下，所述第一信号线VI1靠近所述第二屏蔽线1032，因此，所述第一屏蔽部1031可通过所述第二屏蔽线1032实现与所述第一信号线VI1的电性连接。
进一步地，所述屏蔽层103还包括第三屏蔽线1033，所述第三屏蔽线1033位于所述第三晶体管T3的有源图案和所述基板1011之间，所述第三屏蔽线1033与所述第二屏蔽线1032、所述第一屏蔽部1031电性连接，即所述第一屏蔽部1031可通过所述第三屏蔽线1033、所述第二屏蔽线1032实现与所述第一信号线VI1的电性连接。
进一步地，所述屏蔽层103还包括位于所述第四晶体管T4的所述有源图案和所述基板1011之间的第四屏蔽线1034，如图4B和图4D所示；所述屏蔽层103还包括位于所述第五晶体管T5的所述有源图案和所述基板1011之间的第五屏蔽线1035，位于所述第六晶体管T6的所述有源图案和所述基板1011之间的第六屏蔽线1036，以及，位于所述第七晶体管T7的所述有源图案和所述基板1011之间的第七屏蔽线1037，如图4D所示。
可选地，所述第四屏蔽线1034、所述第五屏蔽线1035、所述第六屏蔽线1036及所述第七屏蔽线1037之间相互间隔设置，或互相接触。所述第四屏蔽线1034、所述第五屏蔽线1035、所述第六屏蔽线1036或所述第七屏蔽线1037可与所述第二金属层1023电性连接，也可不与所述第二金属层1023电性连接。
可选地，所述第一屏蔽部1031、所述第二屏蔽线1032、所述第三屏蔽线1033、所述第四屏蔽线1034、所述第五屏蔽线1035、所述第六屏蔽线1036及所述第七屏蔽线1037可同层设置，也可分别位于不同层。
可选地，在俯视视角下，所述第二晶体管T2在所述基板1011上的正投影位于所述第二屏蔽线1032在所述基板1011上的正投影内；所述第三晶体管T3在所述基板1011上的正投影位于所述第三屏蔽线1033在所述基板1011上的正投影内；所述第四晶体管T4在所述基板1011上的正投影位于所述第四屏蔽线1034在所述基板1011上的正投影内；所述第五晶体管T5在所述基板1011上的正投影位于所述第五屏蔽线1035在所述基板1011上的正投影内；所述第六晶体管T6在所述基板1011上的正投影位于所述第六屏蔽线1036在所述基板1011上的正投影内；所述第七晶体管T7在所述基板1011上的正投影位于所述第七屏蔽线1037在所述基板1011上的正投影内，以降低自由电荷对所述第二晶体管T2至所述第七晶体管T7的电学性能的影响。
所述屏蔽层103呈整面设计虽然可节省制备光罩和产能，但所用的材料会较多，所实现的均化电场的效果较差，易产生串扰。所述屏蔽层103采用图案化设计虽然会增加制程工序及产能，但均化电场的效果较好，且不利于形成寄生电容，可降低串扰问题产生的几率，还可降低材料用量。
所述第二晶体管T2的源极和漏极通过贯穿所述第三绝缘层1054及所述第二介电层1055的第二过孔100b与所述第二晶体管T2的有源图案电性连接；与之相似的，所述第三晶体管T3的源极和漏极通过所述第二过孔100b与所述第三晶体管T3的有源图案电性连接。所述第四晶体管T4的源极和漏极通过贯穿所述第一绝缘层1051、所述第二绝缘层1052、所述第一介电层1053、所述第三绝缘层1054及所述第二介电层1055的第三过孔100c与所述第四晶体管T4的有源图案电性连接。与之相似的，所述第五晶体管T5的源极和漏极通过所述第三过孔100c与所述第五晶体管T5的有源图案电性连接，所述第六晶体管T6的源极和漏极通过所述第三过孔100c与所述第六晶体管T6的有源图案电性连接。所述第七晶体管T7的源极和漏极通过所述第三过孔100c与所述第七晶体管T7的有源图案电性连接。
请继续参阅图2A至图2B，所述显示面板还包括像素定义层106及封装层107，所述发光层1043位于所述像素定义层106的像素定义区内，所述封装层107位于所述发光器件上。可以理解的，所述显示面板还包括偏光片、触控电极等未示出部分。
如图5A至图5C是本申请的实施例提供的显示面板的制备方法的制备过程示意图。本申请的实施例还提供一种显示面板的制备方法，用于制备任一上述的显示面板。具体地，所述制备方法包括以下步骤：
步骤S10：提供所述基板1011；
步骤S20：在所述基板1011上制备所述屏蔽层103，如图5A所示；
步骤S30：在所述屏蔽层103上制备所述驱动阵列102，如图5B所示。
进一步地，在步骤S30后还包括：在所述驱动阵列102上制备所述子像素100及封装层107，如图5C所示。具体地，在所述驱动阵列102上依次制备阳极1041、像素定义层106、发光层1043及阴极1042，所述封装层107位于所述阴极1042上，所述发光层1043位于所述像素定义层106的像素定义区内。
其中，在所述步骤S10中还包括：在所述基板1011上依次制备阻挡层1012、第二衬底1013、第一缓冲层1014，所述屏蔽层103位于所述第一缓冲层1014上。在所述步骤S20中还包括：在所述屏蔽层103上制备第二缓冲层1015。
进一步地，在所述步骤S20中还包括对所述屏蔽层103进行图案化处理。
在所述步骤S30中还包括：在所述第二缓冲层1015上依次制备第一有源层1021、第一绝缘层1051、图案化的第一金属层1022、第二绝缘层1052、图案化的第二金属层1023、第一介电层1053、第二有源层1024、第三绝缘层1054、图案化的第三金属层1025、第二介电层1055、图案化的第四金属层1026、保护层1056及平坦层1057。其中，所述屏蔽层103通过贯穿所述第二缓冲层1015、所述第一绝缘层1051及所述第二绝缘层1052的第一过孔与所述第二金属层1023电性连接。
本申请实施例还提供一种显示装置，包括任一上述的显示面板。
所述显示装置包括固定终端（如电视、台式电脑等），移动终端（如手机、笔记本电脑等），以及可穿戴设备（如手环、虚拟显示设备、增强显示设备等）等。
以上对本申请实施例进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的方法及其核心思想；同时，对于本领域的技术人员，依据本申请的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本申请的限制。

Claims (20)

  1. 一种显示面板，其中，包括：
    基板；
    驱动阵列，包括位于所述基板上的第一有源层和第二有源层，位于所述第一有源层上的第一金属层以及位于所述第一金属层上的第二金属层，所述第一有源层包括硅半导体材料，所述第二有源层包括氧化物半导体材料；
    所述驱动阵列包括多个像素驱动电路，至少一所述像素驱动电路包括第一晶体管和第二晶体管；其中，所述第一有源层包括所述第一晶体管的有源图案，所述第二有源层包括所述第二晶体管的有源图案，所述第一金属层包括所述第一晶体管的栅极；以及
    屏蔽层，包括位于所述第一晶体管的所述有源图案和所述基板之间的第一屏蔽部，所述第一屏蔽部通过所述第二金属层与预设稳定电压电性连接；
    其中，所述像素驱动电路还包括：
    储存电容，所述储存电容包括第一电容电极和第二电容电极，所述第一金属层包括与所述第一晶体管的栅极电连接的所述第一电容电极，所述第二金属层包括与所述第一电容电极相对设置的所述第二电容电极；
    其中，所述第二金属层还包括与所述第一晶体管的所述栅极电性连接的第一信号线，所述第一屏蔽部与所述第一信号线电性连接。
  2. 根据权利要求1所述的显示面板，其中，所述第一屏蔽部与所述第一电容电极相对设置。
  3. 根据权利要求1所述的显示面板，其中，还包括与所述第一晶体管的源极和漏极中的一个电性连接的发光器件，所述第二金属层还包括第二信号线，至少一所述像素驱动电路还包括第七晶体管，所述第二信号线通过所述第七晶体管电性连接于所述发光器件，所述第一信号线和所述第二信号线间隔设置。
  4. 根据权利要求3所述的显示面板，其中，所述第二金属层还包括所述第二晶体管的底栅，所述第二有源层位于所述第二金属层上，所述第二晶体管的有源图案位于所述第二晶体管的所述底栅上方。
  5. 根据权利要求4所述的显示面板，其中，所述第二晶体管电性连接于所述第一晶体管的所述栅极和所述第一信号线之间；所述屏蔽层还包括第二屏蔽线，所述第二屏蔽线位于所述第二晶体管的所述有源图案和所述基板之间，所述第二屏蔽线与所述第一屏蔽部电性连接。
  6. 根据权利要求5所述的显示面板，其中，至少一所述像素驱动电路还包括电性连接于所述第一晶体管的所述栅极与所述第一晶体管的源极和漏极中的一个之间的第三晶体管，所述第二有源层包括所述第三晶体管的有源图案；
    所述屏蔽层还包括第三屏蔽线，所述第三屏蔽线位于所述第三晶体管的所述有源图案和所述基板之间，且与所述第一屏蔽部和所述第二屏蔽线电性连接。
  7. 一种显示面板，其中，包括：
    基板；
    驱动阵列，包括位于所述基板上的第一有源层和第二有源层，位于所述第一有源层上的第一金属层以及位于所述第一金属层上的第二金属层，所述第一有源层包括硅半导体材料，所述第二有源层包括氧化物半导体材料；
    所述驱动阵列包括多个像素驱动电路，至少一所述像素驱动电路包括第一晶体管和第二晶体管；其中，所述第一有源层包括所述第一晶体管的有源图案，所述第二有源层包括所述第二晶体管的有源图案，所述第一金属层包括所述第一晶体管的栅极；以及
    屏蔽层，包括位于所述第一晶体管的所述有源图案和所述基板之间的第一屏蔽部，所述第一屏蔽部通过所述第二金属层与预设稳定电压电性连接。
  8. 根据权利要求7所述的显示面板，其中，所述像素驱动电路还包括：
    储存电容，所述储存电容包括第一电容电极和第二电容电极，所述第一金属层包括与所述第一晶体管的栅极电连接的所述第一电容电极，所述第二金属层包括与所述第一电容电极相对设置的所述第二电容电极。
  9. 根据权利要求8所述的显示面板，其中，所述第一屏蔽部与所述第一电容电极相对设置。
  10. 根据权利要求7所述的显示面板，其中，所述第二金属层还包括与所述第一晶体管的所述栅极电性连接的第一信号线；其中，所述第一屏蔽部与所述第一信号线电性连接。
  11. 根据权利要求10所述的显示面板，其中，还包括与所述第一晶体管的源极和漏极中的一个电性连接的发光器件，所述第二金属层还包括第二信号线，至少一所述像素驱动电路还包括第七晶体管，所述第二信号线通过所述第七晶体管电性连接于所述发光器件，所述第一信号线和所述第二信号线间隔设置。
  12. 根据权利要求11所述的显示面板，其中，所述第二金属层还包括所述第二晶体管的底栅，所述第二有源层位于所述第二金属层上，所述第二晶体管的有源图案位于所述第二晶体管的所述底栅上方。
  13. 根据权利要求12所述的显示面板，其中，所述第二晶体管电性连接于所述第一晶体管的所述栅极和所述第一信号线之间；所述屏蔽层还包括第二屏蔽线，所述第二屏蔽线位于所述第二晶体管的所述有源图案和所述基板之间，所述第二屏蔽线与所述第一屏蔽部电性连接。
  14. 根据权利要求13所述的显示面板，其中，至少一所述像素驱动电路还包括电性连接于所述第一晶体管的所述栅极与所述第一晶体管的源极和漏极中的一个之间的第三晶体管，所述第二有源层包括所述第三晶体管的有源图案；
    所述屏蔽层还包括第三屏蔽线，所述第三屏蔽线位于所述第三晶体管的所述有源图案和所述基板之间，且与所述第一屏蔽部和所述第二屏蔽线电性连接。
  15. 根据权利要求14所述的显示面板，其中，至少一所述像素驱动电路还包括：与所述第一晶体管的所述源极和所述漏极中的一个电性连接的第四晶体管及第五晶体管，以及电性连接于所述第一晶体管的所述源极和所述漏极中的另一个与所述发光器件之间的第六晶体管；
    所述第一有源层还包括所述第四晶体管的有源图案、所述第五晶体管的有源图案、所述第六晶体管的有源图案以及所述第七晶体管的有源图案；
    所述屏蔽层还包括位于所述第四晶体管的所述有源图案和所述基板之间的第四屏蔽线，位于所述第五晶体管的所述有源图案和所述基板之间的第五屏蔽线，位于所述第六晶体管的所述有源图案和所述基板之间的第六屏蔽线，以及，位于所述第七晶体管的所述有源图案和所述基板之间的第七屏蔽线。
  16. 根据权利要求15所述的显示面板，其中，所述第四屏蔽线、所述第五屏蔽线、所述第六屏蔽线及所述第七屏蔽线之间相互间隔设置，或互相接触。
  17. 根据权利要求15所述的显示面板，其中，
    所述第一金属层还包括所述第四晶体管的栅极、所述第五晶体管的栅极、所述第六晶体管的栅极以及所述第七晶体管的栅极；
    所述驱动阵列还包括第三金属层及位于所述第三金属层上的第四金属层；
    其中，所述第三金属层包括所述第二晶体管的顶栅、所述第三晶体管的顶栅、与所述第二晶体管的所述顶栅电性连接的第三信号线、以及与所述第三晶体管的所述顶栅电性连接的第四信号线，所述第二晶体管的所述顶栅位于所述第二晶体管的有源图案上方，所述第三晶体管的所述顶栅位于所述第三晶体管的所述有源图案上方；所述第四金属层包括第五信号线以及与所述第一有源层、所述第二有源层电性连接的源极和漏极，所述第五信号线通过所述第四晶体管与所述第一晶体管的所述源极和所述漏极中的一个电性连接。
  18. 根据权利要求7所述的显示面板，其中，还包括自所述基板向所述驱动阵列方向依次层叠的阻挡层、第二衬底、第一缓冲层及第二缓冲层；
    其中，所述屏蔽层位于所述基板与所述阻挡层之间；或位于所述阻挡层与所述第二衬底之间；或位于所述第二衬底与所述第一缓冲层之间，或位于所述第一缓冲层与所述第二缓冲层之间。
  19. 根据权利要求7所述的显示面板，其中，所述屏蔽层的厚度大于或等于15埃米且小于或等于50埃米。
  20. 一种显示装置，其中，包括如权利要求7所述的显示面板。
PCT/CN2021/118281 2021-09-06 2021-09-14 显示面板及显示装置 WO2023029090A1 (zh)

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