WO2019223682A1 - 薄膜晶体管及其制作方法、阵列基板、显示装置 - Google Patents

薄膜晶体管及其制作方法、阵列基板、显示装置 Download PDF

Info

Publication number
WO2019223682A1
WO2019223682A1 PCT/CN2019/087785 CN2019087785W WO2019223682A1 WO 2019223682 A1 WO2019223682 A1 WO 2019223682A1 CN 2019087785 W CN2019087785 W CN 2019087785W WO 2019223682 A1 WO2019223682 A1 WO 2019223682A1
Authority
WO
WIPO (PCT)
Prior art keywords
base substrate
layer
gate
film transistor
orthographic projection
Prior art date
Application number
PCT/CN2019/087785
Other languages
English (en)
French (fr)
Inventor
王玲
林奕呈
盖翠丽
徐攀
Original Assignee
京东方科技集团股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to EP19808048.3A priority Critical patent/EP3799132A4/en
Priority to US16/619,446 priority patent/US11133367B2/en
Priority to JP2019570058A priority patent/JP7482631B2/ja
Publication of WO2019223682A1 publication Critical patent/WO2019223682A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/126—Shielding, e.g. light-blocking means over the TFTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
    • H01L21/44—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/38 - H01L21/428
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41775—Source or drain electrodes for field effect devices characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78633—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a light shield
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78645—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate
    • H01L29/78648—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate arranged on opposing sides of the channel
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/123—Connection of the pixel electrodes to the thin film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/13—Active-matrix OLED [AMOLED] displays comprising photosensors that control luminance
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/60—OLEDs integrated with inorganic light-sensitive elements, e.g. with inorganic solar cells or inorganic photodiodes

Definitions

  • Embodiments of the present disclosure relate to the field of display technology, and in particular, to a thin film transistor and a manufacturing method thereof, an array substrate, and a display device.
  • Organic light-emitting diode (Organic Light-Emitting Diode, OLED for short) is one of the hotspots in the field of flat panel displays. Compared with liquid crystal display (Liquid Crystal Display, LCD for short), OLED display has the advantages of low energy consumption, low production cost, self-emission, wide viewing angle and fast response speed. At present, in the display field of mobile phones, tablet computers, digital cameras, etc., OLED displays have begun to replace traditional LCD displays.
  • the OLED display has a problem of brightness attenuation during operation.
  • a suitable compensation method needs to be adopted, one of which is optical compensation.
  • Optical compensation is a method of detecting the brightness of a pixel using a photosensitive element, and adjusting the data voltage in a targeted manner based on the obtained result, thereby compensating the brightness.
  • a thin film transistor including: a base substrate; a first gate located on a side of the base substrate; and a side of the first gate remote from the base substrate has A source layer; a second gate on a side of the active layer remote from the base substrate; and a source-drain electrode on a side of the second gate remote from the base substrate.
  • the orthographic projection of the source-drain electrode on the base substrate and the orthographic projection of the second gate electrode on the base substrate at least partially overlap.
  • the above thin film transistor further includes: a buffer layer located on a side of the first gate away from the base substrate; and a buffer layer located on the active layer away from the base substrate.
  • the above-mentioned thin film transistor further includes a connection electrode on a side of the interlayer dielectric layer remote from the base substrate.
  • the buffer layer includes a first via hole penetrating the buffer layer, and an orthographic projection of the first via on the base substrate and an orthographic projection of the first gate on the base substrate are at least Partial overlap.
  • the interlayer dielectric layer includes a second via hole and a third via hole penetrating the interlayer dielectric layer.
  • the orthographic projection of the second via hole on the base substrate and the active layer in the The orthographic projection on the base substrate at least partially overlaps, and the orthographic projection of the third via on the base substrate covers the orthographic projection of the first via on the base substrate.
  • the connection electrode is electrically connected to the first gate through the first via and the third via, and is electrically connected to the second gate through the third via.
  • an orthographic projection of the first gate on the base substrate covers an orthographic projection of the active layer on the base substrate.
  • the active layer includes a metal oxide semiconductor material.
  • connection electrode includes a transparent conductive material.
  • the above-mentioned thin film transistor further includes: a passivation layer located on a side of the source-drain electrode away from the base substrate; and the passivation layer located away from the base substrate A light-shielding layer on one side, the light-shielding layer is configured to absorb and / or reflect ambient light.
  • Another aspect of the present disclosure provides an array substrate including any one of the above thin film transistors; and a photosensitive element located on a side of the source and drain electrodes of the thin film transistor remote from the base substrate.
  • a first electrode of the photosensitive element is connected to a source electrode or a drain electrode of the thin film transistor.
  • the above-mentioned array substrate further includes a lead-out layer located on a side of the photosensitive element remote from the base substrate.
  • a second electrode of the photosensitive element is connected to the lead-out layer.
  • the above-mentioned array substrate further includes a conductive layer provided in the same layer as the second gate in the thin film transistor.
  • the conductive layer is connected to the lead-out layer, and the orthographic projection of the conductive layer on the base substrate and the orthographic projection of the source-drain electrode of the thin film transistor on the base substrate at least partially overlap .
  • the above-mentioned array substrate further includes a connection layer provided at the same layer as the source-drain electrodes of the thin film transistor.
  • the conductive layer is connected to the lead-out layer through the connection layer.
  • Another aspect of the present disclosure provides a display device including any one of the above-mentioned array substrates.
  • Another aspect of the present disclosure also provides a method for manufacturing a thin film transistor, including: providing a base substrate; forming a first gate on one side of the base substrate; and the first gate being far from the substrate An active layer is formed on one side of the substrate; a second gate is formed on a side of the active layer remote from the base substrate; and a source-drain electrode is formed on a side of the second gate remote from the base substrate.
  • the orthographic projection of the source-drain electrode on the base substrate and the orthographic projection of the second gate electrode on the base substrate at least partially overlap.
  • the forming an active layer on a side of the first gate far from the base substrate includes: A buffer layer is formed on the side, the buffer layer includes a first via hole penetrating the buffer layer, an orthographic projection of the first via hole on the base substrate and the first gate electrode on the base substrate Orthographic projections at least partially overlap; and an active layer is formed on a side of the buffer layer remote from the base substrate.
  • the forming a source-drain electrode on a side of the second gate far from the base substrate includes: forming an interlayer dielectric layer on a side of the second gate far from the base substrate, and the interlayer The dielectric layer includes a second via hole and a third via hole penetrating the interlayer dielectric layer.
  • the orthographic projection of the second via hole on the base substrate and the active layer on the base substrate covers the orthographic projection of the first via on the base substrate; and is farther away from the interlayer dielectric layer
  • a source-drain electrode and a connection electrode are formed on one side of the base substrate, and the connection electrode is electrically connected to the first gate through the first via and the third via, and through the third A via is electrically connected to the second gate.
  • the above method further includes: forming a passivation layer on a side of the source-drain electrode away from the base substrate; and A light shielding layer configured to absorb and / or reflect ambient light is formed on one side.
  • FIG. 1 is a schematic structural diagram of a thin film transistor according to an embodiment of the present disclosure
  • FIG. 2 is a schematic structural diagram of another thin film transistor according to an embodiment of the present disclosure.
  • FIG. 3 is a plan view of a thin film transistor provided by an embodiment of the present disclosure.
  • FIG. 4 is a schematic structural diagram of still another thin film transistor according to an embodiment of the present disclosure.
  • FIG. 5 is a flowchart of a method for manufacturing a thin film transistor according to an embodiment of the present disclosure
  • 6A is a schematic diagram of a method for manufacturing a thin film transistor according to an embodiment of the present disclosure
  • 6B is a schematic diagram of a manufacturing method of a thin film transistor provided by an embodiment of the present disclosure.
  • 6C is a schematic diagram of a method for manufacturing a thin film transistor provided by an embodiment of the present disclosure.
  • 6D is a schematic diagram of a method for manufacturing a thin film transistor according to an embodiment of the present disclosure.
  • 6E is a schematic diagram of a method for manufacturing a thin film transistor according to an embodiment of the present disclosure.
  • 6F is a schematic diagram of a method for manufacturing a thin film transistor provided by an embodiment of the present disclosure.
  • FIG. 6G is a schematic diagram of a method for manufacturing a thin film transistor according to an embodiment of the present disclosure.
  • FIG. 7 is a schematic structural diagram of an array substrate according to an embodiment of the present disclosure.
  • FIG. 8 is a schematic structural diagram of another array substrate according to an embodiment of the present disclosure.
  • FIG. 9 is a schematic structural diagram of another array substrate provided by an embodiment of the present disclosure.
  • the technical terms or scientific terms disclosed in the embodiments of the present disclosure shall have the ordinary meanings understood by those with ordinary skills in the field to which the present disclosure belongs.
  • the terms “first”, “second”, and the like used in the embodiments of the present disclosure do not indicate any order, quantity, or importance, but are only used to distinguish different components.
  • the appearance of similar terms such as “first element” in this disclosure does not necessarily mean that there is a second element, and the appearance of similar terms such as “second element” in this disclosure does not mean that there must be first elements.
  • “Include” or “including” and other similar words always include the element or mis-detection that precedes the word and covers the elements or objects listed after the word and their equivalents, without excluding other elements or objects.
  • Words such as “connected” or “connected” are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up”, “down”, “left”, “right”, etc. are only used to indicate the relative position relationship. When the absolute position of the described object changes, the relative position relationship may also change accordingly.
  • the commonly used photosensitive element is a PIN diode
  • its control device is an oxide thin film transistor (Thin Film Transistor, TFT for short).
  • TFT Thin Film Transistor
  • PIN diodes will generate more hydrogen atoms during the manufacturing process. These hydrogen atoms will erode the channel region of the active layer of the TFT, causing the threshold voltage of the TFT to drift negatively and the leakage current to increase, resulting in dark current during optical detection. Larger, the signal-to-noise ratio cannot be guaranteed, and the optical compensation cannot be accurately performed.
  • FIG. 1 is a schematic structural diagram of a thin film transistor for controlling a PIN diode as a photosensitive element according to an embodiment of the present disclosure.
  • a thin film transistor provided by an embodiment of the present disclosure includes a first gate electrode 11, an active layer 13, a second gate electrode 15, and a source-drain electrode 17 disposed on one side of a base substrate 10.
  • the active layer 13 is disposed on the side of the first gate 11 away from the substrate 10, and the second gate 15 is disposed on the side of the active layer 13 away from the substrate 10.
  • the drain electrode 17 is disposed on a side of the second gate 15 away from the base substrate 10, and the orthographic projection of the source and drain electrodes 17 on the base substrate 10 and the orthographic projection of the second gate 15 on the base substrate 10 are at least partially overlapping.
  • the active layer is disposed between the first gate and the second gate, and the orthographic projection of the source and drain electrodes on the base substrate and the second gate on the base substrate are made.
  • the orthographic projections at least partially overlap to ensure that the active layer is completely blocked by the source and drain electrodes and the second gate during subsequent fabrication processes, thereby avoiding hydrogen atoms from entering the active layer when a PIN diode is formed on the thin film transistor. , And then erode the channel region of the thin film transistor active layer. Therefore, negative threshold voltage drift of the thin film transistor can be avoided, leakage current of the thin film transistor can be reduced, dark current reduction and improved signal-to-noise ratio during optical detection can be ensured, so that the display can be accurately optically compensated.
  • the thin film transistor provided by the embodiment of the present disclosure further includes other layers, such as a buffer layer 12, a gate insulating layer 14, and an interlayer dielectric layer 16.
  • the buffer layer 12 is disposed on the side of the first gate 11 away from the base substrate 10
  • the gate insulating layer 14 is disposed on the side of the active layer 13 away from the base substrate 10
  • the interlayer dielectric layer 16 is disposed away from the buffer layer 12 One side of the base substrate 10.
  • the base substrate 10 may be a transparent insulating substrate, such as a glass substrate, a quartz substrate, or other suitable substrates, which are not limited in the embodiments of the present disclosure.
  • the first gate electrode 11 is disposed on the base substrate 10, and a material for manufacturing the first gate electrode 11 may include a copper-based metal, an aluminum-based metal, a nickel-based metal, or the like.
  • the copper-based metal includes copper, a copper-zinc alloy, a copper-nickel alloy, or a copper-zinc-nickel alloy and other stable copper-based metal alloys, which are not limited in the embodiments of the present disclosure.
  • the buffer layer 12 covers the entire base substrate 10, thereby not only preventing harmful impurities, ions, and the like in the base substrate from diffusing into the active layer, but also absorbing and reflecting light such as ambient light, ensuring that Optical stability of thin film transistors.
  • the material of the buffer layer 12 may include silicon oxide, silicon nitride, or silicon oxynitride.
  • the buffer layer may also be a single-layer structure composed of silicon nitride or silicon oxide, or a double-layer or multilayer structure composed of silicon nitride and / or silicon oxide, which is not limited in the embodiments of the present disclosure.
  • the active layer 13 is disposed on the buffer layer 12, and a material of the active layer 13 may include amorphous silicon, polysilicon, or a metal oxide semiconductor.
  • the material for the active layer provided in the embodiment of the present disclosure may be a metal oxide semiconductor, such as indium gallium zinc oxide IGZO, indium zinc oxide IZO, zinc oxide, or zinc gallium oxide GZO, etc.
  • the gate insulating layer 14 is disposed on a channel region of the active layer 13, and a material for manufacturing the gate insulating layer 14 may include silicon oxide, silicon nitride, or silicon oxynitride.
  • the gate insulating layer may also be a single-layer structure composed of silicon nitride or silicon oxide, or a double-layer or multilayer structure composed of silicon nitride and / or silicon oxide, which is not limited in the embodiments of the present disclosure. .
  • the second gate 15 is disposed on the gate insulating layer 14, and a material for the second gate 15 may be made of an alloy formed of one or more metals selected from the group consisting of molybdenum, copper, aluminum, and titanium. Formed from one or more or other suitable materials.
  • the second gate may have a single-layer or multi-layer structure, which is not limited in the embodiments of the present disclosure.
  • the interlayer dielectric layer 16 covers the base substrate 10, and a material for manufacturing the interlayer dielectric layer 16 may include silicon oxide, silicon nitride, or silicon oxynitride.
  • the interlayer dielectric layer 16 may also have a single-layer structure composed of silicon nitride or silicon oxide, or a double-layer or multilayer structure composed of silicon nitride and / or silicon oxide, which is not described in the embodiments of the present disclosure. Any restrictions.
  • the source-drain electrode 17 is disposed on the interlayer dielectric layer 16, and the material for the source-drain electrode 17 may be one of alloys formed from one or more metals selected from the group consisting of molybdenum, copper, aluminum, and titanium. One or more or other suitable materials.
  • the source-drain electrode may have a single-layer or multi-layer structure, which is not limited in the embodiments of the present disclosure.
  • FIG. 2 is a schematic structural diagram of another thin film transistor according to an embodiment of the present disclosure
  • FIG. 3 is a top view of the thin film transistor according to an embodiment of the present disclosure. It should be noted that, in order to illustrate the active layer 13 located below the source-drain electrode layer in the top view, a part of the source-drain electrode 17 is shown in the form of a dotted frame.
  • the thin film transistor further includes a connection electrode 18 disposed on a side of the interlayer dielectric layer 16 away from the base substrate 10.
  • the connecting electrode 18 may be made of a transparent conductive material, such as indium tin oxide, and the embodiment of the present disclosure does not limit this.
  • the connection electrode 18 may be formed in the same patterning process as the source-drain electrode of the thin film transistor, that is, the same material as the source-drain electrode.
  • the buffer layer 12 includes a first via hole 21 penetrating the buffer layer 12.
  • the orthographic projection of the first via hole 21 on the base substrate 10 and the orthographic projection of the first gate electrode 11 on the base substrate 10 at least partially overlap.
  • the interlayer dielectric layer 16 includes a second via hole 22 and a third via hole 23 penetrating the interlayer dielectric layer 16.
  • the orthographic projection of is at least partially overlapped, and the orthographic projection of the third via hole 23 on the base substrate 10 covers the orthographic projection of the first via hole 21 on the base substrate 10.
  • connection electrode 18 is electrically connected to the first gate electrode 11 through the first via hole 21 and the third via hole 23, and is electrically connected to the second gate electrode 15 through the third via hole 23.
  • first via hole 21 and the third via hole 23 expose a part of the first gate electrode 11, and the third via hole 23 exposes a part of the second gate electrode 15.
  • through refers to the entire thickness of the layer in a direction perpendicular to the substrate.
  • the interlayer dielectric layer 16 includes a fourth via hole exposing a first end of the active layer 13 in a direction parallel to the base substrate 10 and a third via hole exposing a second end of the active layer 13 in the direction.
  • the fourth via and the fifth via are both The via hole 22 indicates that the source-drain electrode 17 is connected to the active layer 13 below through the second via hole 22.
  • the first gate electrode 11 is disposed on one side of the base substrate 10, and the buffer layer 12, the active layer 13, the gate insulating layer 14, the first The two gate electrodes 15, the interlayer dielectric layer 16 and the source-drain electrodes are sequentially disposed on the first gate electrode 11 on a side remote from the base substrate 10.
  • the embodiments of the present disclosure are not limited to this, and may have other structures.
  • the source-drain electrodes are not shown in FIG. 2, the arrangement of the source-drain electrodes in the embodiment of FIG. 2 may be the same as that in FIG. 1, and FIG. 1 and FIG. 2 are thin film transistors at different angles. Cross section view.
  • the first gate electrode 11 and the second gate electrode 15 are respectively located on both sides of the active layer 13 and are electrically connected through the connection electrode 18 so that the first gate electrode 11 and the second gate electrode 15 can simultaneously receive the same scan signal transmitted from the gate line, thereby ensuring that the active layer has a driving effect at the same time.
  • the gate line when the gate line is applied with an open signal, under the common action of the first gate and the second gate, an induced charge is generated on the surface of the active layer, so that the thin film transistor is turned on, and the source electrode and the drain electrode pass through
  • the conductive channels in the source layer are electrically connected to each other, so that data can be transmitted between them; when the gate line is applied with an off signal, the source-drain electrodes are disconnected from each other, so data transmission cannot be performed between the two.
  • the active layer in the thin film transistor is driven by the same voltage of the first gate and the second gate, the active layer can make the source and drain electrodes more stably, thereby improving the switching ratio of the thin film transistor and ensuring The stability and driving ability of the thin film transistor are improved.
  • FIG. 4 is a schematic structural diagram of a thin film transistor according to another embodiment of the present disclosure. Compared with the embodiment shown in FIG. 1, as shown in FIG. 4, the thin film transistor provided by this embodiment further includes a passivation layer 19 and a light shielding layer 20.
  • the passivation layer 19 is disposed on a side of the source-drain electrode 17 away from the substrate 10
  • the light-shielding layer 20 is disposed on a side of the passivation layer 19 away from the substrate 10 and is configured to absorb and / or reflect the environment Light.
  • the passivation layer 19 covers the entire base substrate 10, and the material for the passivation layer 19 may include silicon oxide, silicon nitride, silicon oxynitride, and the like.
  • the passivation layer 19 may be a single-layer structure composed of silicon nitride or silicon oxide, or a double-layer or multilayer structure composed of silicon nitride and / or silicon oxide, which is not limited in the embodiments of the present disclosure. .
  • the orthographic projection of the light-shielding layer 20 on the base substrate 10 covers the entire active layer 13 on the base substrate 10 Orthographic projection.
  • the buffer layer 12 by providing both the buffer layer 12 and the light shielding layer 20, it is possible to ensure that ambient light and OLED light are absorbed and / or reflected, thereby further reducing or eliminating leakage in the channel region of the active layer.
  • the occurrence of current phenomenon improves the product yield and ensures the optical stability of the thin film transistor.
  • the orthographic projection of the first gate electrode 11 on the base substrate 10 can cover the orthographic projection of the active layer 13 on the base substrate 10.
  • FIG. 5 is a flowchart of a method of manufacturing a thin film transistor provided by an embodiment of the present disclosure.
  • the base substrate may be a transparent insulating substrate, such as a glass substrate, a quartz substrate, or another suitable substrate, which is not limited in the embodiments of the present disclosure.
  • a first gate is formed on one side of the base substrate.
  • the first gate may be made of a copper-based metal, an aluminum-based metal, a nickel-based metal, or the like.
  • the copper-based metal includes copper, a copper-zinc alloy, a copper-nickel alloy, or a copper-zinc-nickel alloy and other stable copper-based metal alloys, which are not limited in the embodiments of the present disclosure.
  • an active layer is formed on a side of the first gate away from the base substrate.
  • step 300 may specifically include: forming a buffer layer on a side of the first gate away from the base substrate; forming a first via in the buffer layer, the orthographic projection of the first via on the base substrate At least partially overlaps the orthographic projection of the first gate on the base substrate; and forms an active layer on a side of the buffer layer away from the base substrate.
  • the buffer layer can cover the entire base substrate, so that the buffer layer can not only prevent harmful impurities, ions, etc. in the base substrate from diffusing into the active layer, but also absorb and reflect light such as ambient light to ensure the film Optical stability of the transistor.
  • the material for the buffer layer may include silicon oxide, silicon nitride, silicon oxynitride, and the like.
  • the buffer layer may also be a single-layer structure composed of silicon nitride or silicon oxide, or a double-layer or multilayer structure composed of silicon nitride and / or silicon oxide, which is not limited in the embodiments of the present disclosure.
  • the material for the active layer may include amorphous silicon, polysilicon, or a metal oxide semiconductor.
  • the material of the active layer provided in the embodiments of the present disclosure may be a metal oxide semiconductor, such as indium gallium zinc oxide IGZO, indium zinc oxide IZO, zinc oxide, or gallium zinc oxide GZO. Wait.
  • a second gate is formed on a side of the active layer remote from the base substrate.
  • step 400 may specifically include: forming a gate insulating layer on a side of the active layer away from the base substrate; and forming a second gate on a side of the gate insulating layer away from the base substrate.
  • the material for the gate insulating layer may include silicon oxide, silicon nitride, silicon oxynitride, and the like.
  • the gate insulating layer may also be a single-layer structure composed of silicon nitride or silicon oxide, or a double-layer or multilayer structure composed of silicon nitride and / or silicon oxide, which is not limited in the embodiments of the present disclosure. .
  • the material for fabricating the second gate electrode may be formed of one or more materials selected from the group consisting of one or more metals selected from molybdenum, copper, aluminum, and titanium, or other suitable materials.
  • the second gate may have a single-layer or multi-layer structure, which is not limited in the embodiments of the present disclosure.
  • a source-drain electrode is formed on a side of the second gate away from the base substrate.
  • the orthographic projection of the source and drain electrodes on the base substrate at least partially overlaps with the orthographic projection of the second gate electrode on the base substrate.
  • an active layer is disposed between a first gate and a second gate, and an orthographic projection of a source-drain electrode on a base substrate and a second gate are formed.
  • the orthographic projections on the base substrate at least partially overlap, which can prevent hydrogen atoms from entering the active layer in subsequent processes, thereby eroding the channel region of the active layer of the thin film transistor, thereby avoiding negative threshold voltage drift of the thin film transistor and reducing Leakage current in thin film transistors.
  • step 500 may specifically include: forming an interlayer dielectric layer on a side of the second gate away from the substrate substrate; forming a second via and a third via in the interlayer dielectric layer;
  • the orthographic projection of the via on the base substrate at least partially overlaps with the orthographic projection of the active layer on the base substrate, and the orthographic projection of the third via on the base substrate covers the orthographic of the first via on the base substrate Projection; and forming a source-drain electrode and a connection electrode on a side of the interlayer dielectric layer remote from the substrate, the connection electrode is electrically connected to the first gate through the first via and the third via, and is electrically connected through the third via Second grid.
  • the interlayer dielectric layer covers the entire base substrate, and the material for making the interlayer dielectric layer may include silicon oxide, silicon nitride, silicon oxynitride, and the like.
  • the interlayer dielectric layer may also be a single-layer structure composed of silicon nitride or silicon oxide, or a double-layered or multi-layer structure composed of silicon nitride and / or silicon oxide, and the embodiments of the present disclosure do nothing about this. limited.
  • the material for the connection electrode may be a transparent conductive material, such as indium tin oxide, etc., which are not limited in the embodiments of the present disclosure.
  • the material for making the source-drain electrode may be formed of one or more alloys selected from one or more metals selected from the group consisting of molybdenum, copper, aluminum, and titanium, or other suitable materials.
  • the source-drain electrode may have a single-layer or multi-layer structure, which is not limited in the embodiments of the present disclosure.
  • the first gate and the second gate are respectively located on both sides of the active layer, and are electrically connected through the connection electrode, so that the first gate and the second gate can simultaneously receive the same transmitted from the gate line. Scanning signal to ensure that the active layer is driven at the same time.
  • the gate line is applied with an open signal, under the combined effect of the first gate and the second gate, an induced charge is generated on the surface of the active layer, so that the thin film transistor is turned on, and the source electrode and the drain electrode pass The conductive channels in the source layer are electrically connected to each other, so that data can be transmitted between them; when the gate line is applied with an off signal, the source-drain electrodes are disconnected from each other, so data transmission cannot be performed between the two. .
  • the active layer in the thin film transistor is driven by the same voltage of the first gate and the second gate, the active layer can make the source and drain electrodes more stably, thereby improving the switching ratio of the thin film transistor and ensuring The stability and driving ability of the thin film transistor are improved.
  • the method for manufacturing the thin film transistor may further include: forming a passivation layer on a side of the source and drain electrodes away from the base substrate; and forming a configuration on the side of the passivation layer away from the base substrate.
  • a light-shielding layer that absorbs and / or reflects ambient light.
  • the passivation layer covers the entire substrate, and the material for the passivation layer may include silicon oxide, silicon nitride, silicon oxynitride, and the like.
  • the passivation layer may also be a single-layer structure composed of silicon nitride or silicon oxide, or a double-layer or multilayer structure composed of silicon nitride and / or silicon oxide, which is not limited in the embodiments of the present disclosure. .
  • the orthographic projection of the light shielding layer on the base substrate covers the active layer on the base substrate. Orthographic projection.
  • the buffer layer and the light shielding layer at the same time, it is possible to ensure that ambient light and OLED light are absorbed and reflected, thereby further reducing or eliminating the occurrence of leakage current in the channel region of the active layer and improving the product.
  • the yield rate guarantees the optical stability of the thin film transistor.
  • the method for manufacturing a thin film transistor provided by an embodiment of the present disclosure is further described below with reference to FIGS. 6A to 6G.
  • the patterning process may be, for example, a photolithographic patterning process.
  • the process mainly includes: coating on a structure layer that needs to be patterned Photoresist, using a mask to expose the photoresist, developing the exposed photoresist to obtain a photoresist pattern, using the photoresist pattern as a mask to etch the structural layer, and then removing the photolithography gum.
  • a base substrate 10 is provided, and a first metal film is formed on the base substrate 10, and a patterning process is performed on the first metal film.
  • a first gate 11 is formed on the base substrate 10.
  • the first metal film may be deposited on the base substrate 10 by a process such as physical vapor deposition.
  • the base substrate 10 may be a transparent insulating substrate, such as a glass substrate, a quartz substrate, or other suitable substrates, which are not limited in the embodiments of the present disclosure.
  • the first metal thin film may include a copper-based metal, an aluminum-based metal, a nickel-based metal, and the like.
  • the copper-based metal includes copper, a copper-zinc alloy, a copper-nickel alloy, or a copper-zinc-nickel alloy with stable properties.
  • a buffer layer 12 is formed on the first gate electrode 11, as shown in FIG. 6B.
  • a chemical vapor deposition (Chemical Vapor Deposition, CVD for short) process may be used to deposit the buffer layer 12 on the first gate electrode 11.
  • the material for the buffer layer may include silicon oxide, silicon nitride, silicon oxynitride, and the like.
  • the buffer layer may also be a single-layer structure composed of silicon nitride or silicon oxide, or a double-layer or multilayer structure composed of silicon nitride and / or silicon oxide, which is not limited in the embodiments of the present disclosure.
  • the material for the active layer may include amorphous silicon, polysilicon, or a metal oxide semiconductor.
  • the material of the active layer may be a metal oxide semiconductor, such as indium gallium zinc oxide IGZO, indium zinc oxide IZO, zinc oxide, or gallium zinc oxide GZO.
  • a gate insulating layer 14 is formed on the active layer 13, as shown in FIG. 6D.
  • the gate insulating layer 14 may be deposited on the channel region of the active layer by using a process such as CVD.
  • the gate insulating layer may be a silicon oxide layer, a silicon nitride layer, or a composite insulating layer composed of silicon oxide and silicon nitride.
  • the embodiments of the present disclosure do not limit this.
  • the material for the gate insulating layer may include silicon oxide, silicon nitride, silicon oxynitride, and the like.
  • the gate insulating layer may also be a single-layer structure composed of silicon nitride or silicon oxide, or a double-layer or multilayer structure composed of silicon nitride and / or silicon oxide, which is not limited in the embodiments of the present disclosure. .
  • a second metal film is deposited on the gate insulating layer 14, and a patterning process is performed on the second metal film to form a second gate 15, as shown in FIG. 6E.
  • a second metal film may be deposited on the gate insulating layer 14 by a method such as physical vapor deposition.
  • the second metal film may be formed of one or more of an alloy selected from one or more metals selected from molybdenum, copper, aluminum, and titanium or any combination thereof or other suitable materials.
  • the second gate may have a single-layer or multi-layer structure, which is not limited in the embodiments of the present disclosure.
  • an insulating film is deposited on the second gate electrode 15, and a patterning process is performed on the insulating film to form an interlayer dielectric layer 16, as shown in FIG. 6F.
  • an insulating film may be deposited on the second gate by a process such as CVD, and a fourth via hole exposing one end of the active layer in a direction parallel to the substrate is formed by a patterning process, and the active layer is exposed.
  • the insulating film may include silicon oxide, silicon nitride, silicon oxynitride, and the like.
  • the interlayer dielectric layer may also be a single-layer structure composed of silicon nitride or silicon oxide, or a double-layered or multi-layer structure composed of silicon nitride and / or silicon oxide, and the embodiments of the present disclosure do nothing about this. limited.
  • a source-drain electrode 17 and a connection electrode are formed on the interlayer dielectric layer 16.
  • forming the source-drain electrode 17 may include physically depositing a third metal film on the interlayer dielectric layer 16, and performing a patterning process on the third metal film to form the source-drain electrode 17.
  • the third metal film may be formed of one or more kinds of alloys selected from one or more kinds of metals selected from molybdenum, copper, aluminum, and titanium or any combination thereof or other suitable materials.
  • the source-drain electrode may have a single-layer or multi-layer structure, which is not limited in the embodiments of the present disclosure.
  • a passivation layer 19 and a light-shielding layer 20 are formed on the source-drain electrodes 17 to form a thin film transistor as shown in FIG. 4.
  • an insulating film can be deposited on the source-drain electrodes 17 as a passivation layer by a CVD process, and a light-shielding layer 20 that can be used as a black matrix layer is formed on the passivation layer.
  • the insulating film may include silicon oxide, silicon nitride, silicon oxynitride, and the like.
  • the interlayer dielectric layer may also be a single-layer structure composed of silicon nitride or silicon oxide, or a double-layered or multi-layer structure composed of silicon nitride and / or silicon oxide, and the embodiments of the present disclosure do nothing about this. limited.
  • the method of manufacturing the array substrate includes the above steps. Further, in the manufacturing method of the array substrate, a conductive layer may be formed in the step of forming the second gate, and a connection layer may be formed in the step of forming the source-drain electrode and the connection electrode.
  • the above method may further include: setting a PIN diode on the source electrode or the drain electrode; forming a passivation layer on the PIN diode, wherein the passivation layer covers the entire substrate substrate and includes a via hole exposing the PIN diode; A transparent conductive material is deposited on the formation layer to form a lead-out layer through a patterning process; and a light-shielding layer is formed on the lead-out layer.
  • FIG. 7 is a schematic structural diagram of an array substrate provided by an embodiment of the present disclosure.
  • an array substrate provided by an embodiment of the present disclosure includes a thin film transistor 1 and a photosensitive element 2.
  • the thin film transistor 1 is a thin film transistor provided in any one of the above embodiments.
  • the photosensitive element 2 is disposed on a side of the source-drain electrode of the thin-film transistor 1 away from the substrate, and the first electrode 2 a of the photosensitive element 2 is connected to the source or drain electrode of the thin-film transistor 1.
  • the photosensitive element 2 may be a PIN diode.
  • an orthographic projection of a source electrode or a drain electrode of a thin film transistor on a base substrate in an embodiment of the present disclosure covers an orthographic projection of a photosensitive element on the base substrate.
  • an active layer is disposed between a first gate and a second gate, and an orthographic projection of a source-drain electrode on a base substrate and a second gate on a substrate
  • the orthographic projections on the substrate at least partially overlap, which can prevent hydrogen atoms from entering the active layer during the fabrication of the photosensitive element, thereby eroding the channel region of the active layer of the thin film transistor, thereby avoiding negative threshold voltage drift of the thin film transistor, and reducing the thin film transistor.
  • the leakage current in the medium can further ensure the reduction of the dark current and the acceptable signal-to-noise ratio during optical detection, so that the display can be accurately optically compensated.
  • FIG. 8 is a schematic structural diagram of an array substrate according to another embodiment of the present disclosure. As shown in FIG. 8, compared with the array substrate shown in FIG. 7, the array substrate provided by the embodiment of the present disclosure further includes a lead-out layer 3.
  • the lead-out layer 3 is disposed on the side of the photosensitive element 2 remote from the base substrate 10, and the second electrode 2 b of the photosensitive element 2 is connected to the lead-out layer 3.
  • the function of the lead-out layer 3 is equivalent to a wire.
  • the material of the conductive layer 3 may be a transparent conductive material, such as indium tin oxide, etc., which is not limited in the embodiment of the present disclosure.
  • a PIN diode is set on the side of the source or drain electrode away from the substrate, and then A side of the drain electrode and the PIN diode remote from the base substrate forms a passivation layer, the passivation layer including a via.
  • the lead-out layer 3 is connected to the PIN diode through a via in the passivation layer.
  • the array substrate provided by the embodiment of the present disclosure includes the thin film transistor provided by any of the above embodiments, its implementation principles and effects are similar, and will not be repeated here.
  • the thin film transistor 1 is turned on to drive the light-sensitive element 2 to emit light.
  • FIG. 9 is a schematic structural diagram of an array substrate according to another embodiment of the present disclosure. As shown in FIG. 9, compared with the array substrate shown in FIG. 8, the array substrate provided by the embodiment of the present disclosure further includes a conductive layer 4.
  • the conductive layer 4 is provided in the same layer as the second gate of the thin film transistor 1 and is connected to the lead-out layer 3.
  • the orthographic projection of the conductive layer 4 on the base substrate at least partially overlaps with the orthographic projection of the source-drain electrodes in the thin film transistor on the base substrate.
  • the conductive layer 4 and the source-drain electrodes form a capacitance to store or discharge electric power.
  • the lead-out layer 3 is connected to the conductive layer 4 so as to provide an electrical signal to the conductive layer 4.
  • the material for the conductive layer 4 and the material for the second gate may be the same or different.
  • the manufacturing material of the conductive layer 4 is the same as that of the second gate, the conductive layer 4 and the second gate can be simultaneously formed in the same process, thereby simplifying the manufacturing process.
  • the conductive layer 4 and the lead-out layer 3 may be connected through vias.
  • the above-mentioned array substrate further includes a connection layer 5.
  • the connection layer 5 is provided at the same layer as the source-drain electrodes in the thin film transistor, so that the conductive layer 4 is connected to the lead-out layer 3 through the connection layer 5.
  • connection layer 5 is provided to prevent disconnection of the connection due to poor electrical connection of the via when the lead-out layer 3 is connected to the conductive layer 4 through the via.
  • connection layer 5 may be made of a conductive and low-resistivity material, which is not limited in the embodiments of the present disclosure.
  • connection layer 5 and the material for the source and drain electrodes may be the same or different.
  • the manufacturing material of the connection layer 5 is the same as that of the source and drain electrodes, the connection layer 5 and the source and drain electrodes can be formed at the same time in the same process, thereby simplifying the manufacturing process.
  • an embodiment of the present disclosure further provides a display device including any of the foregoing array substrates.
  • the display device includes the array substrate provided in any of the above embodiments, its implementation principles and effects are similar, and will not be repeated here.
  • the display device may be any product or component having a display function, such as a television, a digital camera, a mobile phone, a watch, a notebook computer, a navigator, and the like.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Sustainable Development (AREA)
  • Thin Film Transistor (AREA)
  • Electroluminescent Light Sources (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

提供了一种薄膜晶体管及其制作方法、阵列基板、显示装置。该薄膜晶体管包括：衬底基板；位于衬底基板一侧的第一栅极；位于第一栅极远离衬底基板的一侧的有源层；位于有源层远离衬底基板的一侧的第二栅极；以及位于第二栅极远离衬底基板的一侧的源漏电极。源漏电极在衬底基板上的正投影与第二栅极在衬底基板上的正投影至少部分重叠。

Description

薄膜晶体管及其制作方法、阵列基板、显示装置
相关申请
本申请要求享有2018年5月21日提交的中国专利申请No.201810487978.3的优先权，其全部公开内容通过引用并入本文。
技术领域
本公开实施例涉及显示技术领域，具体涉及一种薄膜晶体管及其制作方法、阵列基板、显示装置。
背景技术
有机发光二极管(Organic Light-Emitting Diode，简称OLED)是当前平板显示器研究领域的热点之一。与液晶显示器(Liquid Crystal Display，简称LCD)相比，OLED显示器具有低能耗、生产成本低、自发光、宽视角及响应速度快等优点。目前，在手机、平板电脑、数码相机等显示领域，OLED显示器已经开始取代传统的LCD显示器。
然而，OLED显示器在工作过程中会出现亮度衰减的问题。为了保证OLED显示器均匀而持续的亮度，需要采用合适的补偿方法，其中一种就是光学补偿。光学补偿即利用光敏元件侦测像素亮度，根据得到的结果针对性地调整数据电压，进而补偿亮度的方法。目前，利用光敏元件进行补偿的设计仍有改善空间。
发明内容
根据本公开的一个方面，提供了一种薄膜晶体管，包括：衬底基板；位于衬底基板一侧的第一栅极；位于所述第一栅极远离所述衬底基板的一侧的有源层；位于所述有源层远离所述衬底基板的一侧的第二栅极；以及位于所述第二栅极远离所述衬底基板的一侧的源漏电极。所述源漏电极在所述衬底基板上的正投影与所述第二栅极在所述衬底基板上的正投影至少部分重叠。
在本公开的一些示例性实施例中，上述薄膜晶体管还包括：位于所述第一栅极远离所述衬底基板的一侧的缓冲层；位于所述有源层远离所述衬底基板的一侧的栅绝缘层；以及位于所述第二栅极远离所述衬底基板的一侧的层间介质层。
在本公开的一些示例性实施例中，上述薄膜晶体管还包括位于所述层间介质层远离所述衬底基板的一侧的连接电极。所述缓冲层包括 贯穿所述缓冲层的第一过孔，所述第一过孔在所述衬底基板上的正投影与所述第一栅极在所述衬底基板上的正投影至少部分重叠。所述层间介质层包括贯穿所述层间介质层的第二过孔和第三过孔，所述第二过孔在所述衬底基板上的正投影与所述有源层在所述衬底基板上的正投影至少部分重叠，所述第三过孔在所述衬底基板上的正投影覆盖所述第一过孔在所述衬底基板上的正投影。所述连接电极通过所述第一过孔和所述第三过孔电连接到所述第一栅极，并且通过所述第三过孔电连接到所述第二栅极。
在本公开的一些示例性实施例中，所述第一栅极在所述衬底基板上的正投影覆盖所述有源层在所述衬底基板上的正投影。
在本公开的一些示例性实施例中，所述有源层包括金属氧化物半导体材料。
在本公开的一些示例性实施例中，所述连接电极包括透明导电材料。
在本公开的一些示例性实施例中，上述薄膜晶体管还包括：位于所述源漏电极远离所述衬底基板的一侧的钝化层；以及位于所述钝化层远离所述衬底基板的一侧的遮光层，所述遮光层配置成吸收和/或反射环境光。
本公开的另一方面提供了一种阵列基板，包括上述任一种薄膜晶体管；以及位于所述薄膜晶体管的所述源漏电极远离所述衬底基板的一侧的光敏元件。所述光敏元件的第一电极与所述薄膜晶体管的源电极或漏电极连接。
在本公开的一些示例性实施例中，上述阵列基板还包括位于所述光敏元件远离所述衬底基板一侧的导出层。所述光敏元件的第二电极与所述导出层连接。
在本公开的一些示例性实施例中，上述阵列基板还包括与薄膜晶体管中的第二栅极同层设置的导电层。所述导电层与所述导出层连接，并且所述导电层在所述衬底基板上的正投影与所述薄膜晶体管的所述源漏电极在所述衬底基板上的正投影至少部分重叠。
在本公开的一些示例性实施例中，上述阵列基板还包括与所述薄膜晶体管的所述源漏电极同层设置的连接层。所述导电层通过所述连接层与所述导出层连接。
本公开另外的方面提供了一种显示装置，包括上述任一种阵列基板。
本公开另外的方面还提供了一种薄膜晶体管的制作方法，包括：提供衬底基板；在所述衬底基板的一侧形成第一栅极；在所述第一栅极远离所述衬底基板的一侧形成有源层；在所述有源层远离所述衬底基板的一侧形成第二栅极；以及在所述第二栅极远离衬底基板的一侧形成源漏电极。所述源漏电极在所述衬底基板上的正投影与所述第二栅极在所述衬底基板上的正投影至少部分重叠。
在本公开的一些示例性实施例中，所述在所述第一栅极远离所述衬底基板的一侧形成有源层包括：在所述第一栅极远离所述衬底基板的一侧形成缓冲层，所述缓冲层包括贯穿所述缓冲层的第一过孔，所述第一过孔在所述衬底基板上的正投影与所述第一栅极在所述衬底基板上的正投影至少部分重叠；以及在所述缓冲层远离所述衬底基板的一侧形成有源层。所述在所述第二栅极远离所述衬底基板的一侧形成源漏电极包括：在所述第二栅极远离所述衬底基板的一侧形成层间介质层，所述层间介质层包括贯穿所述层间介质层的第二过孔和第三过孔，所述第二过孔在所述衬底基板上的正投影与所述有源层在所述衬底基板上的正投影至少部分重叠，所述第三过孔在所述衬底基板上的正投影覆盖所述第一过孔在所述衬底基板上的正投影；以及在所述层间介质层远离所述衬底基板的一侧形成源漏电极和连接电极，所述连接电极通过所述第一过孔和所述第三过孔电连接到所述第一栅极，并且通过所述第三过孔电连接到所述第二栅极。
在本公开的一些示例性实施例中，上述方法还包括：在所述源漏电极远离所述衬底基板的一侧形成钝化层；以及在所述钝化层远离所述衬底基板的一侧形成配置成吸收和/或反射环境光的遮光层。
当然，实施本公开的任一产品或方法并不一定需要同时达到以上所述的所有优点。本公开的其它特征和优点将在随后的说明书实施例中阐述，并且，部分地从说明书实施例中变得显而易见，或者通过实施本公开而了解。本公开实施例的目的和其他优点可通过在说明书、权利要求书以及附图中所特别指出的结构来实现和获得。
附图说明
附图用来提供对本公开技术方案的进一步理解，并且构成说明书 的一部分，与本申请的实施例一起用于解释本公开的技术方案，并不构成对本公开技术方案的限制。
图1为本公开实施例提供的一种薄膜晶体管的结构示意图；
图2为本公开实施例提供的另一薄膜晶体管的结构示意图；
图3为本公开实施例提供的薄膜晶体管的平面图；
图4为本公开实施例提供的又一薄膜晶体管的结构示意图；
图5为本公开实施例提供的薄膜晶体管的制作方法的流程图；
图6A为本公开实施例提供的薄膜晶体管的制作方法示意图；
图6B为本公开实施例提供的薄膜晶体管的制作方法示意图；
图6C为本公开实施例提供的薄膜晶体管的制作方法示意图；
图6D为本公开实施例提供的薄膜晶体管的制作方法示意图；
图6E为本公开实施例提供的薄膜晶体管的制作方法示意图；
图6F为本公开实施例提供的薄膜晶体管的制作方法示意图；
图6G为本公开实施例提供的薄膜晶体管的制作方法示意图
图7为本公开实施例提供的一种阵列基板的结构示意图；
图8为本公开实施例提供的另一阵列基板的结构示意图；以及
图9为本公开实施例提供的又一阵列基板的结构示意图。
具体实施方式
为使本公开的目的、技术方案和优点更加清楚明白，下文中将结合附图对本公开的实施例进行详细说明。需要说明的是，在不冲突的情况下，本申请中的实施例及实施例中的特征可以相互任意组合。
在附图的流程图示出的步骤可以在诸如一组计算机可执行指令的计算机系统中执行。并且，虽然在流程图中示出了逻辑顺序，但是在某些情况下，可以以不同于此处的顺序执行所示出或描述的步骤。
除非另外定义，本公开实施例公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开实施例中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“第一元件”等类似术语在本公开中的出现不意味着必然存在第二元件，并且“第二元件”等类似术语在本公开中的出现也不意味着必然存在第一元件。“包括”或者“包含”等类似的词语一直出该词前面的元件或误检涵盖出现在该词后面列举的元件或者物件及其等同，而不排除 其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述的对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
目前常用的光敏元件是PIN二极管，其控制器件是氧化物薄膜晶体管(Thin Film Transistor，简称TFT)。但PIN二极管在制作过程中会产生较多的氢原子，这些氢原子会侵蚀TFT的有源层的沟道区域，导致TFT的阈值电压负向漂移，漏电流增大，造成光学检测时暗电流较大，无法保证信噪比，进而无法准确地进行光学补偿。
图1为本公开实施例提供的一种用于控制作为光敏元件的PIN二极管的薄膜晶体管的结构示意图。如图1所示，本公开实施例提供的薄膜晶体管包括设置在衬底基板10一侧的第一栅极11、有源层13、第二栅极15和源漏电极17。
具体地，如图1所示，有源层13设置在第一栅极11远离衬底基板10的一侧，第二栅极15设置在有源层13远离衬底基板10的一侧，源漏电极17设置在第二栅极15远离衬底基板10的一侧，并且源漏电极17在衬底基板10上的正投影与第二栅极15在衬底基板10上的正投影至少部分重叠。
在本公开的上述实施例中，通过将有源层设置在第一栅极和第二栅极之间，并且使得源漏电极在衬底基板上的正投影与第二栅极在衬底基板上的正投影至少部分重叠，可以保证在后续的制作工艺中，有源层被源漏电极和第二栅极完全遮挡，从而避免当在该薄膜晶体管上形成PIN二极管时氢原子进入有源层，进而侵蚀薄膜晶体管有源层的沟道区域。因此，可以避免薄膜晶体管的阈值电压负向漂移，减少薄膜晶体管的漏电流，保证在光学检测时暗电流的减小以及改进的信噪比，以便能够准确地对显示器进行光学补偿。
需要说明的是，如图1所示，本公开实施例提供的薄膜晶体管还包括其它层，诸如缓冲层12、栅绝缘层14和层间介质层16等。缓冲层12设置在第一栅极11远离衬底基板10的一侧，栅绝缘层14设置在有源层13远离衬底基板10的一侧，并且层间介质层16设置在缓冲层12远离衬底基板10的一侧。
衬底基板10可以是透明绝缘基板，比如玻璃基板、石英基板或其他合适的基板，本公开实施例对此不作任何限定。
第一栅极11设置在衬底基板10上，且第一栅极11的制作材料可以包括铜基金属、铝基金属、镍基金属等。例如，该铜基金属包括铜、铜锌合金、铜镍合金或铜锌镍合金等性能稳定的铜基金属合金，本公开实施例对此不作任何限定。
在示例性实施例中，缓冲层12覆盖整个衬底基板10，从而不仅可以防止衬底基板中的有害杂质、离子等扩散到有源层之中，还可以吸收和反射环境光等光线，保证薄膜晶体管的光学稳定性。
缓冲层12的制作材料可以包括硅氧化物、硅氮化物或硅氮氧化物等。例如，该缓冲层还可以为由氮化硅或氧化硅构成的单层结构，或者由氮化硅和/或氧化硅构成的双层或多层结构，本公开实施例对此不作任何限定。
有源层13设置在缓冲层12上，且有源层13的制作材料可以包括非晶硅、多晶硅或金属氧化物半导体等。
可选地，为了减小薄膜晶体管的漏电流，本公开实施例提供的有源层的制作材料可以采用金属氧化物半导体，例如氧化铟镓锌IGZO、氧化铟锌IZO、氧化锌或氧化镓锌GZO等。
栅绝缘层14设置在有源层13的沟道区域上，且栅绝缘层14的制作材料可以包括硅氧化物、硅氮化物或硅氮氧化物等。例如，该栅绝缘层还可以为由氮化硅或氧化硅构成的单层结构，或者由氮化硅和/或氧化硅构成的双层或多层结构，本公开实施例对此不作任何限定。
第二栅极15设置在栅绝缘层14上，且第二栅极15的制作材料可以由选自钼、铜、铝、钛中的一种或多种或以上金属任意组合形成的合金中的一种或多种或其他合适的材料形成。例如，第二栅极可为单层或多层结构，本公开实施例对此不作任何限定。
层间介质层16覆盖衬底基板10，且层间介质层16的制作材料可以包括硅氧化物、硅氮化物或硅氮氧化物等。例如，该层间介质层16还可以为由氮化硅或氧化硅构成的单层结构，或者由氮化硅和/或氧化硅构成的双层或多层结构，本公开实施例对此不作任何限定。
源漏电极17设置在层间介质层16上，且源漏电极17的制作材料可以由选自钼、铜、铝、钛中的一种或多种或以上金属任意组合形成 的合金中的一种或多种或其他合适的材料形成。例如，源漏电极可为单层或多层结构，本公开实施例对此不作任何限定。
图2为本公开实施例提供的另一薄膜晶体管的结构示意图，而图3为本公开实施例提供的该薄膜晶体管的顶视图。需要说明的是，顶视图中为了示意出位于源漏电极层下方的有源层13，将源漏电极17的一部分以虚线框的形式表示。如图2和3所示，与图1所示的实施例相比，该薄膜晶体管还包括设置在层间介质层16远离衬底基板10一侧的连接电极18。
连接电极18的制作材料可以为透明导电材料，例如氧化铟锡等，本公开实施例对此不作任何限定。例如，在示例性实施例中，连接电极18可以与薄膜晶体管的源漏电极在同一图案化工艺中形成，即与源漏电极材料相同。
进一步地，缓冲层12包括贯穿缓冲层12的第一过孔21，第一过孔21在衬底基板10上的正投影与第一栅极11在衬底基板10上的正投影至少部分重叠。层间介质层16包括贯穿层间介质层16的第二过孔22和第三过孔23，第二过孔22在衬底基板10上的正投影与有源层13在衬底基板10上的正投影至少部分重叠，并且第三过孔23在衬底基板10上的正投影覆盖第一过孔21在衬底基板10上的正投影。连接电极18通过第一过孔21和第三过孔23电连接第一栅极11，并且通过第三过孔23电连接第二栅极15。换言之，第一过孔21和第三过孔23暴露第一栅极11的一部分，并且第三过孔23暴露第二栅极15的一部分。
如本文中所使用的，“贯穿”是指在垂直于衬底基板的方向上穿过该层的整个厚度。
可选地，层间介质层16包括暴露有源层13在平行于衬底基板10的方向上的第一端的第四过孔和暴露有源层13在所述方向上的第二端的第五过孔，其中，源漏电极17分别通过第四过孔和第五过孔与有源层13连接，需要说明的是，参考图3，第四过孔和第五过孔均以第二过孔22表示，源漏电极17通过第二过孔22连接至下方的有源层13。
可选地，在示例性实施例中，如图1和2所示，第一栅极11设置在衬底基板10的一侧，并且缓冲层12、有源层13、栅绝缘层14、第二栅极15、层间介质层16和源漏电极依次设置在第一栅极11在远离 衬底基板10的一侧。当然，本公开实施例并不以此为限，还可以为其他结构。需要说明的是，尽管图2中并未示出源漏电极，但是在图2的实施例中源漏电极的布置可以与图1中的相同，并且图1和图2为薄膜晶体管在不同角度下的截面图。
在如图2所示的实施例中，第一栅极11和第二栅极15分别位于有源层13两侧，且通过连接电极18电连接，使得第一栅极11和第二栅极15能够同时接收到从栅线传输的相同的扫描信号，进而保证对有源层同时产生驱动作用。具体地，当栅线被施加开启信号时，在第一栅极和第二栅极的共同作用下，有源层表面产生感应电荷，使得该薄膜晶体管导通，并且源电极和漏电极通过有源层中的导电沟道与彼此电连接，因而可以在二者之间进行数据传输；当栅线被施加关断信号时，源漏电极彼此断开，因而不能在二者之间进行数据传输。由于该薄膜晶体管中的有源层受到第一栅极和第二栅极的相同电压驱动作用，因此使得有源层能够更加稳定地导通源漏电极，从而提高了薄膜晶体管的开关比，保证了薄膜晶体管的稳定性和驱动能力。
图4为本公开的另一实施例提供的薄膜晶体管的结构示意图。与图1所示的实施例相比，如图4所示，该实施例提供的薄膜晶体管还包括钝化层19和遮光层20。
具体地，钝化层19设置在源漏电极17远离衬底基板10的一侧，而遮光层20设置在钝化层19远离衬底基板10的一侧，并且配置成吸收和/或反射环境光。
钝化层19覆盖整个衬底基板10，且钝化层19的制作材料可以包括硅氧化物、硅氮化物、硅氮氧化物等。例如，该钝化层19可以为由氮化硅或氧化硅构成的单层结构，或者由氮化硅和/或氧化硅构成的双层或多层结构，本公开实施例对此不作任何限定。
可选地，为了充分地吸收和/或反射环境光，避免光线进入到有源层的沟道区域，遮光层20在衬底基板10上的正投影覆盖整个有源层13在衬底基板10上的正投影。
在本公开的实施例中，通过设置缓冲层12和遮光层20二者，能够保证环境光和OLED光线被吸收和/或反射，从而进一步地减少或消除有源层的沟道区域中的漏电流现象的发生，提高产品良率，保证薄膜晶体管的光学稳定性。
可选地，如图1和图4所示，为了能够保证环境光和OLED光线被更加充分地反射，从而进一步地减少或消除有源层的沟道区域中的漏电流现象的发生，提高产品良率，保证薄膜晶体管的光学稳定性，第一栅极11在衬底基板10上的正投影可以覆盖有源层13在衬底基板10上的正投影。
本公开实施例还提供了一种薄膜晶体管的制作方法，并且图5为本公开实施例提供的薄膜晶体管的制作方法的流程图。
在步骤100处，提供衬底基板。衬底基板可以是透明绝缘基板，比如玻璃基板、石英基板或其他合适的基板，本公开实施例对此不作任何限定。
在步骤200处，在衬底基板的一侧形成第一栅极。第一栅极的制作材料可以包括铜基金属、铝基金属、镍基金属等。例如，该铜基金属包括铜、铜锌合金、铜镍合金或铜锌镍合金等性能稳定的铜基金属合金，本公开实施例对此不作任何限定。
在步骤300处，在第一栅极远离衬底基板的一侧形成有源层。
在示例实施例中，步骤300可以具体包括：在第一栅极远离衬底基板的一侧形成缓冲层；在缓冲层中形成第一过孔，第一过孔在衬底基板上的正投影与第一栅极在衬底基板上的正投影至少部分重叠；以及在缓冲层远离衬底基板的一侧形成有源层。
可选地，缓冲层可以覆盖整个衬底基板，使得该缓冲层不仅可以防止衬底基板中的有害杂质、离子等扩散到有源层之中，还可以吸收和反射环境光等光线，保证薄膜晶体管的光学稳定性。
缓冲层的制作材料可以包括硅氧化物、硅氮化物、硅氮氧化物等。例如，该缓冲层还可以为由氮化硅或氧化硅构成的单层结构，或者由氮化硅和/或氧化硅构成的双层或多层结构，本公开实施例对此不作任何限定。
有源层的制作材料可以包括非晶硅、多晶硅或金属氧化物半导体等。
进一步地，为了减小薄膜晶体管的漏电流，本公开实施例提供的有源层的制作材料可以为金属氧化物半导体，例如氧化铟镓锌IGZO、氧化铟锌IZO、氧化锌或氧化镓锌GZO等。
在步骤400处，在有源层远离衬底基板的一侧形成第二栅极。
在示例实施例中，步骤400可以具体包括：在有源层远离衬底基板的一侧形成栅绝缘层；以及在栅绝缘层远离衬底基板的一侧形成第二栅极。
栅绝缘层的制作材料可以包括硅氧化物、硅氮化物、硅氮氧化物等。例如，该栅绝缘层还可以为由氮化硅或氧化硅构成的单层结构，或者由氮化硅和/或氧化硅构成的双层或多层结构，本公开实施例对此不作任何限定。
第二栅极的制作材料可以由选自钼、铜、铝、钛中的一种或多种或以上金属任意组合形成的合金中的一种或多种或其他合适的材料形成。例如，第二栅极可为单层或多层结构，本公开实施例对此不作任何限定。
在步骤500处，在第二栅极远离衬底基板的一侧形成源漏电极。源漏电极在衬底基板上的正投影与第二栅极在衬底基板上的正投影至少部分重叠。
在本公开实施例提供的薄膜晶体管的制作方法中，通过将有源层设置在第一栅极和第二栅极之间，且源漏电极在衬底基板上的正投影与第二栅极在衬底基板上的正投影至少部分重叠，能够避免在后续工艺中氢原子进入有源层，进而侵蚀薄膜晶体管有源层的沟道区域，从而避免薄膜晶体管的阈值电压负向漂移，减小薄膜晶体管中的漏电流。
在示例性实施例中，步骤500可以具体包括：在第二栅极远离衬底基板的一侧形成层间介质层；在层间介质层中形成第二过孔和第三过孔，第二过孔在衬底基板上的正投影与有源层在衬底基板上的正投影至少部分重叠，第三过孔在衬底基板上的正投影覆盖第一过孔在衬底基板上的正投影；以及在层间介质层远离衬底基板的一侧形成源漏电极和连接电极，连接电极通过第一过孔和第三过孔电连接第一栅极，并且通过第三过孔电连接第二栅极。
可选地，层间介质层覆盖整个衬底基板，且层间介质层的制作材料可以包括硅氧化物、硅氮化物、硅氮氧化物等。例如，该层间介质层还可以为由氮化硅或氧化硅构成的单层结构，或者由氮化硅和/或氧化硅构成的双层或多层结构，本公开实施例对此不作任何限定。
连接电极的制作材料可以为透明导电材料，例如氧化铟锡等，本公开实施例对此不作任何限定。
可选地，源漏电极的制作材料可以由选自钼、铜、铝、钛中的一种或多种或以上金属任意组合形成的合金中的一种或多种或其他合适的材料形成。例如，源漏电极可为单层或多层结构，本公开实施例对此不作任何限定。
在本实施例中，第一栅极和第二栅极分别位于有源层两侧，且通过连接电极电连接，使得第一栅极和第二栅极能够同时接收到从栅线传输的相同的扫描信号，进而保证对有源层同时产生驱动作用。具体地，当栅线被施加开启信号时，在第一栅极和第二栅极的共同作用下，有源层表面产生感应电荷，使得该薄膜晶体管导通，并且源电极和漏电极通过有源层中的导电沟道与彼此电连接，因而可以在二者之间进行数据传输；当栅线被施加关断信号时，源漏电极彼此断开，因而不能在二者之间进行数据传输。由于该薄膜晶体管中的有源层受到第一栅极和第二栅极的相同电压驱动作用，因此使得有源层能够更加稳定地导通源漏电极，从而提高了薄膜晶体管的开关比，保证了薄膜晶体管的稳定性和驱动能力。
可选地，在步骤500之后，上述薄膜晶体管的制作方法还可以包括：在源漏电极远离衬底基板的一侧形成钝化层；以及在钝化层远离衬底基板的一侧形成配置成吸收和/或反射环境光的遮光层。
可选地，钝化层覆盖整个衬底基板，且钝化层的制作材料可以包括硅氧化物、硅氮化物、硅氮氧化物等。例如，该钝化层还可以为由氮化硅或氧化硅构成的单层结构，或者由氮化硅和/或氧化硅构成的双层或多层结构，本公开实施例对此不作任何限定。
可选地，为了吸收和反射环境光，避免光线进入到有源层的沟道区域，在示例性实施例中，遮光层在衬底基板上的正投影覆盖有源层在衬底基板上的正投影。
在上述实施例中，通过同时设置缓冲层和遮光层，能够保证环境光和OLED光线被吸收和反射，从而进一步地减少或消除有源层的沟道区域中的漏电流现象的发生，提高产品良率，保证薄膜晶体管的光学稳定性。
下面结合图6A-图6G，进一步地描述本公开实施例提供的薄膜晶体管的制作方法，其中，构图工艺例如可以为光刻构图工艺，其流程主要包括：在需要被构图的结构层上涂覆光刻胶，使用掩膜板对光刻 胶进行曝光，对曝光的光刻胶进行显影以得到光刻胶图案，使用光刻胶图案作为掩膜板对结构层进行刻蚀，然后剥离光刻胶。
在根据本公开实施例的薄膜晶体管的制作方法中，首先，如图6A所示，提供衬底基板10，并且在衬底基板10上形成第一金属膜，对该第一金属膜执行构图工艺以形成第一栅极11。
在具体实施时，可以在衬底基板10上采用物理气相沉积等工艺沉积第一金属膜。衬底基板10可以是透明绝缘基板，比如玻璃基板、石英基板或其他合适的基板，本公开实施例对此不作任何限定。第一金属薄膜可以包括铜基金属、铝基金属、镍基金属等。例如，该铜基金属包括铜、铜锌合金、铜镍合金或铜锌镍合金等性能稳定的铜基金属合金。
接着，在第一栅极11上形成缓冲层12，如图6B所示。在具体实施时，可以采用化学气相沉积(Chemical Vapor Deposition，简称CVD)工艺在第一栅极11上沉积缓冲层12。
缓冲层的制作材料可以包括硅氧化物、硅氮化物、硅氮氧化物等。例如，该缓冲层还可以为由氮化硅或氧化硅构成的单层结构，或者由氮化硅和/或氧化硅构成的双层或多层结构，本公开实施例对此不作任何限定。
然后，在缓冲层12上形成有源层13，如图6C所示。在具体实施时，有源层的制作材料可以包括非晶硅、多晶硅或金属氧化物半导体等。
进一步地，为了减小薄膜晶体管的漏电流，有源层的制作材料可以为金属氧化物半导体，例如氧化铟镓锌IGZO、氧化铟锌IZO、氧化锌或氧化镓锌GZO等。
接着，在有源层13上形成栅绝缘层14，如图6D所示。在具体实施时，可以采用CVD等工艺在有源层的沟道区域上沉积栅绝缘层14。
栅绝缘层可以为氧化硅层、氮化硅层或由氧化硅和氮化硅所组成的复合绝缘层等，本公开实施例对此不作任何限定。
栅绝缘层的制作材料可以包括硅氧化物、硅氮化物、硅氮氧化物等。例如，该栅绝缘层还可以为由氮化硅或氧化硅构成的单层结构，或者由氮化硅和/或氧化硅构成的双层或多层结构，本公开实施例对此不作任何限定。
然后，在栅绝缘层14上沉积第二金属膜，并且对第二金属膜执行构图工艺以形成第二栅极15，如图6E所示。在具体实施时，在栅绝缘层14上可以采用物理气相沉积等方法沉积第二金属膜。
第二金属膜可以由选自钼、铜、铝、钛中的一种或多种或以上金属任意组合形成的合金中的一种或多种或其他合适的材料形成。例如，第二栅极可为单层或多层结构，本公开实施例对此不作任何限定。
然后，在第二栅极15上沉积绝缘膜，并且对该绝缘膜执行构图工艺以形成层间介质层16，如图6F所示。在具体实施时，在第二栅极上可以采用CVD等工艺沉积绝缘膜，并通过构图工艺形成暴露有源层在平行于衬底基板的方向上的一端的第四过孔、暴露有源层在所述方向上的另一端的第五过孔、暴露第二栅极的第二过孔、暴露第一栅极的第一过孔和暴露第一过孔的第三过孔。
绝缘膜可以包括硅氧化物、硅氮化物、硅氮氧化物等。例如，该层间介质层还可以为由氮化硅或氧化硅构成的单层结构，或者由氮化硅和/或氧化硅构成的双层或多层结构，本公开实施例对此不作任何限定。
接着，如图6G所示，在层间介质层16上形成源漏电极17和连接电极(图中未示出)。在具体实施时，形成源漏电极17可以包括在层间介质层16上物理沉积第三金属膜，并且对该第三金属膜执行构图工艺以形成源漏电极17。
第三金属膜可以由选自钼、铜、铝、钛中的一种或多种或以上金属任意组合形成的合金中的一种或多种或其他合适的材料形成。例如，源漏电极可为单层或多层结构，本公开实施例对此不作任何限定。
然后，在源漏电极17上形成钝化层19和遮光层20，以形成如图4所示的薄膜晶体管。在具体实施时，可以在源漏电极17上采用CVD工艺沉积绝缘膜来作为钝化层，并且在该钝化层上形成可以作为黑矩阵层的遮光层20。
上述绝缘膜可以包括硅氧化物、硅氮化物、硅氮氧化物等。例如，该层间介质层还可以为由氮化硅或氧化硅构成的单层结构，或者由氮化硅和/或氧化硅构成的双层或多层结构，本公开实施例对此不作任何限定。
需要说明的是，若通过上述方法制作的薄膜晶体管应用在阵列基 板中，那么阵列基板的制作方法包括上述各步骤。进一步地，在该阵列基板的制作方法中，可以在形成第二栅极的步骤中形成导电层，并且可以在形成源漏电极和连接电极的步骤中形成连接层。此后，上述方法还可以包括：在源电极或漏电极上设置PIN二极管；在PIN二极管上形成钝化层，其中，钝化层覆盖整个衬底基板，并且包括暴露PIN二极管的过孔；在钝化层上沉积透明导电材料，通过构图工艺形成导出层；以及在导出层上形成遮光层。
基于上述实施例的发明构思，本公开实施例还提供一种阵列基板。图7为本公开实施例提供的阵列基板的结构示意图。如图7所示，本公开实施例提供的阵列基板包括薄膜晶体管1和光敏元件2。薄膜晶体管1为上述任一实施例所提供的薄膜晶体管。光敏元件2设置在薄膜晶体管1的源漏电极远离衬底基板的一侧，并且光敏元件2的第一电极2a与薄膜晶体管1的源电极或漏电极连接。
在示例性实施例中，光敏元件2可以为PIN二极管。
在示例性实施例中，如图7所示，本公开实施例中的薄膜晶体管的源电极或漏电极在衬底基板上的正投影覆盖光敏元件在衬底基板上的正投影。
在本公开实施例提供的阵列基板中，通过将有源层设置在第一栅极和第二栅极之间，且源漏电极在衬底基板上的正投影与第二栅极在衬底基板上的正投影至少部分重叠，能够避免在制作光敏元件时氢原子进入有源层，进而侵蚀薄膜晶体管有源层的沟道区域，从而避免薄膜晶体管的阈值电压负向漂移，减小薄膜晶体管中的漏电流，进而保证在光学检测时暗电流的减小以及可接受的信噪比，从而能够准确地对显示器进行光学补偿。
图8为本公开的另一实施例提供的阵列基板的结构示意图。如图8所示，与图7所示的阵列基板相比，本公开实施例提供的阵列基板还包括导出层3。导出层3设置在光敏元件2远离衬底基板10一侧，并且光敏元件2的第二电极2b与导出层3连接。在该实施例中，导出层3的作用相当于导线。
导电层3的制作材料可以为透明导电材料，例如氧化铟锡等，本公开实施例对此不作任何限定。
需要说明的是，如图8所示，在制作阵列基板的工艺中，在制作 完成薄膜晶体管的源漏电极之后，在源电极或漏电极远离衬底基板的一侧设置PIN二极管，然后在源漏电极和PIN二极管远离衬底基板的一侧形成钝化层，该钝化层包括过孔。导出层3通过钝化层中的过孔与PIN二极管连接。
由于本公开实施例提供的阵列基板包括上述任一实施例所提供的薄膜晶体管，因此其实现原理和实现效果类似，在此不再赘述。
在本公开实施例提供的阵列基板中，当第一栅极和第二栅极同时接收到导通信号时，薄膜晶体管1导通从而驱动光敏元件2发光。
图9为本公开的另一实施例提供的阵列基板的结构示意图。如图9所示，与图8所示的阵列基板相比，本公开实施例提供的阵列基板还包括导电层4。
导电层4与薄膜晶体管1的第二栅极同层设置，且与导出层3连接。特别地，导电层4在衬底基板上的正投影与薄膜晶体管中的源漏电极在衬底基板上的正投影至少部分重叠。
在上述的布置中，导电层4和源漏电极形成电容，以存储或者释放电量。导出层3与导电层4连接，以便向导电层4提供电信号。
导电层4的制作材料与第二栅极的制作材料可以相同也可以不同。当导电层4的制作材料与第二栅极的制作材料相同时，可以在同一个工艺过程中同时形成导电层4和第二栅极，从而简化制作工艺。
导电层4和导出层3可以通过过孔连接。可替换地，如图9所示，上述阵列基板还包括连接层5。连接层5与薄膜晶体管中的源漏电极同层设置，使得导电层4通过连接层5与导出层3连接。
在本实施例中，连接层5的设置能够避免在导出层3通过过孔与导电层4连接时，该连接由于过孔电性连接不好而发生断路。
连接层5可以采用导电且电阻率较低的材料制成，本公开实施例对此不作任何限定。
连接层5的制作材料与源漏电极的制作材料可以相同也可以不同。当连接层5的制作材料与源漏电极的制作材料相同时，可以在同一个工艺过程中同时形成连接层5和源漏电极，从而简化制作工艺。
基于上述实施例的发明构思，本公开实施例还提供一种显示装置，包括上述任一种阵列基板。
由于该显示装置包括上述任一实施例中所提供的阵列基板，因此 其实现原理和实现效果类似，在此不再赘述。
显示装置可以为电视、数码相机、手机、手表、笔记本电脑、导航仪等任何具有显示功能的产品或者部件。
本公开实施例附图只涉及本公开实施例涉及到的结构，其他结构可参考通常设计。
为了清晰起见，在用于描述本公开的实施例的附图中，层或微结构的厚度和尺寸被放大。可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”，或者可以存在中间元件。
在不冲突的情况下，本公开的实施例即实施例中的特征可以相互组合以得到新的实施例。
虽然本公开所揭露的实施方式如上，但所述的内容仅为便于理解本公开而采用的实施方式，并非用以限定本公开。任何本公开所属领域内的技术人员，在不脱离本公开所揭露的精神和范围的前提下，可以在实施的形式及细节上进行任何的修改与变化，但本公开的专利保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (15)

  1. 一种薄膜晶体管，包括：
    衬底基板；
    位于衬底基板一侧的第一栅极；
    位于所述第一栅极远离所述衬底基板的一侧的有源层；
    位于所述有源层远离所述衬底基板的一侧的第二栅极；以及
    位于所述第二栅极远离所述衬底基板的一侧的源漏电极，
    其中，所述源漏电极在所述衬底基板上的正投影与所述第二栅极在所述衬底基板上的正投影至少部分重叠。
  2. 根据权利要求1所述的薄膜晶体管，还包括：
    位于所述第一栅极远离所述衬底基板的一侧的缓冲层；
    位于所述有源层远离所述衬底基板的一侧的栅绝缘层；以及
    位于所述第二栅极远离所述衬底基板的一侧的层间介质层。
  3. 根据权利要求2所述的薄膜晶体管，还包括位于所述层间介质层远离所述衬底基板的一侧的连接电极，其中
    所述缓冲层包括贯穿所述缓冲层的第一过孔，所述第一过孔在所述衬底基板上的正投影与所述第一栅极在所述衬底基板上的正投影至少部分重叠，
    所述层间介质层包括贯穿所述层间介质层的第二过孔和第三过孔，所述第二过孔在所述衬底基板上的正投影与所述有源层在所述衬底基板上的正投影至少部分重叠，所述第三过孔在所述衬底基板上的正投影覆盖所述第一过孔在所述衬底基板上的正投影，且与所述第二栅极在所述衬底基板上的正投影至少部分重叠；
    所述连接电极通过所述第一过孔和所述第三过孔电连接到所述第一栅极，并且通过所述第三过孔电连接到所述第二栅极。
  4. 根据权利要求1所述的薄膜晶体管，其中，所述第一栅极在所述衬底基板上的正投影覆盖所述有源层在所述衬底基板上的正投影。
  5. 根据权利要求1所述的薄膜晶体管，其中，所述有源层包括金属氧化物半导体材料。
  6. 根据权利要求3所述的薄膜晶体管，其中，所述连接电极包括透明导电材料。
  7. 根据权利要求3所述的薄膜晶体管，还包括：
    位于所述源漏电极远离所述衬底基板的一侧的钝化层；以及
    位于所述钝化层远离所述衬底基板的一侧的遮光层，所述遮光层配置成吸收和/或反射环境光。
  8. 一种阵列基板，包括：
    如权利要求1～7任一项所述的薄膜晶体管；以及
    位于所述薄膜晶体管的所述源漏电极远离所述衬底基板的一侧的光敏元件，其中
    所述光敏元件的第一电极与所述薄膜晶体管的源电极或漏电极连接。
  9. 根据权利要求8所述的阵列基板，还包括位于所述光敏元件远离所述衬底基板一侧的导出层，其中
    所述光敏元件的第二电极与所述导出层连接。
  10. 根据权利要求9所述的阵列基板，还包括与薄膜晶体管中的第二栅极同层设置的导电层，其中
    所述导电层与所述导出层连接，并且
    所述导电层在所述衬底基板上的正投影与所述薄膜晶体管的所述源漏电极在所述衬底基板上的正投影至少部分重叠。
  11. 根据权利要求10所述的阵列基板，还包括与所述薄膜晶体管的所述源漏电极同层设置的连接层，其中
    所述导电层通过所述连接层与所述导出层连接。
  12. 一种显示装置，包括：如权利要求8～11任一项所述的阵列基板。
  13. 一种薄膜晶体管的制作方法，包括：
    提供衬底基板；
    在所述衬底基板的一侧形成第一栅极；
    在所述第一栅极远离所述衬底基板的一侧形成有源层；
    在所述有源层远离所述衬底基板的一侧形成第二栅极；以及
    在所述第二栅极远离衬底基板的一侧形成源漏电极，
    其中，所述源漏电极在所述衬底基板上的正投影与所述第二栅极在所述衬底基板上的正投影至少部分重叠。
  14. 根据权利要求13所述的方法，其中，所述在所述第一栅极远 离所述衬底基板的一侧形成有源层包括：
    在所述第一栅极远离所述衬底基板的一侧形成缓冲层，所述缓冲层包括贯穿所述缓冲层的第一过孔，所述第一过孔在所述衬底基板上的正投影与所述第一栅极在所述衬底基板上的正投影至少部分重叠；以及
    在所述缓冲层远离所述衬底基板的一侧形成有源层，并且其中
    所述在所述第二栅极远离所述衬底基板的一侧形成源漏电极包括：
    在所述第二栅极远离所述衬底基板的一侧形成层间介质层，所述层间介质层包括贯穿所述层间介质层的第二过孔和第三过孔，所述第二过孔在所述衬底基板上的正投影与所述有源层在所述衬底基板上的正投影至少部分重叠，所述第三过孔在所述衬底基板上的正投影覆盖所述第一过孔在所述衬底基板上的正投影；以及
    在所述层间介质层远离所述衬底基板的一侧形成源漏电极和连接电极，所述连接电极通过所述第一过孔和所述第三过孔电连接到所述第一栅极，并且通过所述第三过孔电连接到所述第二栅极。
  15. 根据权利要求14所述的方法，还包括：
    在所述源漏电极远离所述衬底基板的一侧形成钝化层；以及
    在所述钝化层远离所述衬底基板的一侧形成配置成吸收和/或反射环境光的遮光层。
PCT/CN2019/087785 2018-05-21 2019-05-21 薄膜晶体管及其制作方法、阵列基板、显示装置 WO2019223682A1 (zh)

Priority Applications (3)

Application Number Priority Date Filing Date Title
EP19808048.3A EP3799132A4 (en) 2018-05-21 2019-05-21 THIN FILM TRANSISTOR AND METHOD OF MANUFACTURE THEREOF, ARRAY SUBSTRATE AND DISPLAY DEVICE
US16/619,446 US11133367B2 (en) 2018-05-21 2019-05-21 Thin film transistor and fabricating method thereof, array substrate and display device
JP2019570058A JP7482631B2 (ja) 2018-05-21 2019-05-21 薄膜トランジスタ及びその製造方法、アレイ基板、表示装置

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201810487978.3A CN108767016B (zh) 2018-05-21 2018-05-21 一种薄膜晶体管及其制作方法、阵列基板、显示装置
CN201810487978.3 2018-05-21

Publications (1)

Publication Number Publication Date
WO2019223682A1 true WO2019223682A1 (zh) 2019-11-28

Family

ID=64007308

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2019/087785 WO2019223682A1 (zh) 2018-05-21 2019-05-21 薄膜晶体管及其制作方法、阵列基板、显示装置

Country Status (5)

Country Link
US (1) US11133367B2 (zh)
EP (1) EP3799132A4 (zh)
JP (1) JP7482631B2 (zh)
CN (1) CN108767016B (zh)
WO (1) WO2019223682A1 (zh)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108767016B (zh) * 2018-05-21 2021-09-21 京东方科技集团股份有限公司 一种薄膜晶体管及其制作方法、阵列基板、显示装置
US11289548B2 (en) * 2018-11-20 2022-03-29 Boe Technology Group Co., Ltd. Display substrate, display apparatus, and method of fabricating display substrate
CN109560141B (zh) * 2018-12-13 2020-09-25 合肥鑫晟光电科技有限公司 薄膜晶体管、发光装置及其制造方法
CN109728060B (zh) 2019-01-04 2021-02-02 京东方科技集团股份有限公司 一种阵列基板、电致发光面板及显示装置
CN109742126B (zh) * 2019-01-11 2022-02-11 京东方科技集团股份有限公司 显示基板及其制备方法、显示面板、显示装置
CN109887965B (zh) * 2019-02-20 2022-01-21 京东方科技集团股份有限公司 显示模组及其制造方法、显示装置
US11637152B2 (en) 2019-06-11 2023-04-25 Boe Technology Group Co., Ltd. Array substrate and method for manufacturing the same, and display device having photosensitive element, light emitting device and sensing transistor
CN110634929B (zh) * 2019-09-26 2022-02-08 京东方科技集团股份有限公司 显示基板及其制备方法、亮度补偿方法、显示装置
JP2023504952A (ja) * 2019-10-14 2023-02-08 京東方科技集團股▲ふん▼有限公司 検出基板、その製造方法及び平板検出装置
CN110648629B (zh) * 2019-10-31 2023-09-22 厦门天马微电子有限公司 显示面板及其制作方法、显示装置
CN110993616B (zh) * 2019-11-28 2022-08-09 京东方科技集团股份有限公司 显示背板及其制备方法和显示装置
CN113785350B (zh) * 2020-04-10 2023-06-16 京东方科技集团股份有限公司 显示基板及其制作方法、显示装置
KR20210156372A (ko) * 2020-06-17 2021-12-27 삼성디스플레이 주식회사 지문 센서, 그의 제조 방법, 및 그를 포함한 표시 장치
CN112242413B (zh) * 2020-10-10 2022-10-04 武汉华星光电技术有限公司 灯板及显示装置
CN112331141A (zh) * 2020-11-03 2021-02-05 Tcl华星光电技术有限公司 Oled显示面板和显示装置
CN115398523A (zh) 2021-01-27 2022-11-25 京东方科技集团股份有限公司 像素驱动电路及其驱动方法、显示基板、显示装置
CN112965310B (zh) * 2021-02-26 2023-01-10 京东方科技集团股份有限公司 一种阵列基板及其制作方法、显示面板
CN116097924A (zh) 2021-03-11 2023-05-09 京东方科技集团股份有限公司 阵列基板及其显示面板和显示装置
CN113363329A (zh) * 2021-06-04 2021-09-07 华南理工大学 一种薄膜晶体管以及薄膜晶体管的制备方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1934605A (zh) * 2004-03-17 2007-03-21 皇家飞利浦电子股份有限公司 电致发光显示器件
CN103280181A (zh) * 2013-05-29 2013-09-04 上海中科高等研究院 Amoled像素亮度的补偿方法及补偿系统
US20140340608A1 (en) * 2013-05-16 2014-11-20 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
CN104821339A (zh) * 2015-05-11 2015-08-05 京东方科技集团股份有限公司 Tft及制作方法、阵列基板及制作驱动方法、显示装置
CN108767016A (zh) * 2018-05-21 2018-11-06 京东方科技集团股份有限公司 一种薄膜晶体管及其制作方法、阵列基板、显示装置

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3980167B2 (ja) * 1998-04-07 2007-09-26 株式会社日立製作所 Ｔｆｔ電極基板
TW478014B (en) * 1999-08-31 2002-03-01 Semiconductor Energy Lab Semiconductor device and method of manufacturing thereof
JP2002072963A (ja) 2000-06-12 2002-03-12 Semiconductor Energy Lab Co Ltd 発光モジュールおよびその駆動方法並びに光センサ
US6774578B2 (en) * 2000-09-19 2004-08-10 Semiconductor Energy Laboratory Co., Ltd. Self light emitting device and method of driving thereof
US6509616B2 (en) * 2000-09-29 2003-01-21 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and its manufacturing method
JP4312420B2 (ja) 2001-05-18 2009-08-12 株式会社半導体エネルギー研究所 半導体装置およびその作製方法
JP2003338628A (ja) 2002-05-20 2003-11-28 Seiko Epson Corp 薄膜半導体装置、電気光学装置、電子機器、薄膜半導体装置の製造方法、電気光学装置の製造方法
JP2007188936A (ja) * 2006-01-11 2007-07-26 Epson Imaging Devices Corp 表示装置
JP4459990B2 (ja) 2007-08-06 2010-04-28 株式会社半導体エネルギー研究所 半導体装置
JP5740132B2 (ja) * 2009-10-26 2015-06-24 株式会社半導体エネルギー研究所 表示装置及び半導体装置
US8637802B2 (en) 2010-06-18 2014-01-28 Semiconductor Energy Laboratory Co., Ltd. Photosensor, semiconductor device including photosensor, and light measurement method using photosensor
CN102956649A (zh) * 2012-11-26 2013-03-06 京东方科技集团股份有限公司 阵列基板、阵列基板制作方法及显示装置
CN103137641B (zh) * 2013-01-25 2015-10-21 北京京东方光电科技有限公司 一种阵列基板及其制作方法、x射线平板探测器
CN203133439U (zh) * 2013-02-28 2013-08-14 信利半导体有限公司 一种液晶显示器
CN103489826B (zh) 2013-09-26 2015-08-05 京东方科技集团股份有限公司 阵列基板、制备方法以及显示装置
CN103560135B (zh) * 2013-11-14 2015-12-02 北京京东方光电科技有限公司 一种x射线传感器的阵列基板及其制造方法
CN104977764A (zh) * 2015-06-18 2015-10-14 深圳市华星光电技术有限公司 一种阵列基板及其制作方法、液晶显示器
CN105720012A (zh) * 2016-02-18 2016-06-29 深圳市华星光电技术有限公司 双栅极tft阵列基板及制作方法
CN107946196B (zh) * 2017-11-28 2021-12-28 合肥鑫晟光电科技有限公司 氧化物薄膜晶体管及其制备方法、阵列基板和显示装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1934605A (zh) * 2004-03-17 2007-03-21 皇家飞利浦电子股份有限公司 电致发光显示器件
US20140340608A1 (en) * 2013-05-16 2014-11-20 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
CN103280181A (zh) * 2013-05-29 2013-09-04 上海中科高等研究院 Amoled像素亮度的补偿方法及补偿系统
CN104821339A (zh) * 2015-05-11 2015-08-05 京东方科技集团股份有限公司 Tft及制作方法、阵列基板及制作驱动方法、显示装置
CN108767016A (zh) * 2018-05-21 2018-11-06 京东方科技集团股份有限公司 一种薄膜晶体管及其制作方法、阵列基板、显示装置

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP3799132A4 *

Also Published As

Publication number Publication date
JP2021524148A (ja) 2021-09-09
CN108767016A (zh) 2018-11-06
EP3799132A1 (en) 2021-03-31
EP3799132A4 (en) 2022-03-23
US20200161402A1 (en) 2020-05-21
US11133367B2 (en) 2021-09-28
JP7482631B2 (ja) 2024-05-14
CN108767016B (zh) 2021-09-21

Similar Documents

Publication Publication Date Title
WO2019223682A1 (zh) 薄膜晶体管及其制作方法、阵列基板、显示装置
CN106684155B (zh) 双栅薄膜晶体管及其制备方法、阵列基板及显示装置
US11417716B2 (en) Organic light emitting display substrate and panel with photodetector for light compensation of subpixel
US11222908B2 (en) Array substrate and preparation method thereof, touch display panel
US10622427B2 (en) Array substrate, manufacturing method thereof, and display apparatus
US11665940B2 (en) Display substrate for avoiding breaks and preparation method thereof, bonding method of display panel and display apparatus
WO2016065852A1 (zh) 一种coa基板及其制作方法和显示装置
US9613986B2 (en) Array substrate and its manufacturing method, display device
TWI606283B (zh) 顯示裝置
US20160268320A1 (en) Array Substrate, Manufacturing Method Thereof and Display Apparatus
US8179506B2 (en) Method for fabricating a pixel structure and the pixel structure
US20160043116A1 (en) Thin film transistor and manufacturing method thereof, array substrate and manufacturing method thereof and display device
WO2021036840A1 (zh) 显示基板及其制造方法、显示装置
WO2016029612A1 (zh) 薄膜晶体管及其制备方法、显示基板及显示装置
KR102067669B1 (ko) 박막 트랜지스터 표시판 및 그 제조 방법
WO2019242600A1 (zh) 有机电致发光显示面板、其制作方法及显示装置
US9281324B2 (en) Array substrate, fabrication method thereof and display device
WO2016192446A1 (zh) 薄膜晶体管及其制作方法、阵列基板及其制作方法
WO2014153958A1 (zh) 阵列基板、阵列基板的制造方法以及显示装置
WO2021083226A9 (zh) 一种显示基板及其制作方法、显示装置
WO2016173012A1 (zh) 薄膜晶体管阵列基板及其制作方法
US10629834B2 (en) Thin film transistor, method for preparing the same, and display device
WO2014161349A1 (zh) 阵列基板及其制备方法、显示装置
WO2019080254A1 (zh) 背沟道蚀刻型氧化物半导体tft基板及其制作方法
WO2013174105A1 (zh) 阵列基板、其制造方法、显示面板及显示装置

Legal Events

Date Code Title Description
ENP Entry into the national phase

Ref document number: 2019570058

Country of ref document: JP

Kind code of ref document: A

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 19808048

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

ENP Entry into the national phase

Ref document number: 2019808048

Country of ref document: EP

Effective date: 20201221