CN107946196B - 氧化物薄膜晶体管及其制备方法、阵列基板和显示装置 - Google Patents

氧化物薄膜晶体管及其制备方法、阵列基板和显示装置 Download PDF

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CN107946196B
CN107946196B CN201711215165.0A CN201711215165A CN107946196B CN 107946196 B CN107946196 B CN 107946196B CN 201711215165 A CN201711215165 A CN 201711215165A CN 107946196 B CN107946196 B CN 107946196B
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程磊磊
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Hefei Xinsheng Optoelectronics Technology Co Ltd
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Abstract

本发明提供了一种氧化物薄膜晶体管及其制备方法、阵列基板和显示装置。在本发明提供的氧化物薄膜晶体管制备方法中，通过在半导体层上依次形成第二绝缘层、栅极和第三绝缘层后，去除半导体层中待导体化区域上覆盖的第二绝缘层和第三绝缘层，再通过导体化工艺处理待导体化区域，形成导体化区域。从而使得待导体化区域在第二绝缘层的遮盖下，有效避免在形成第三绝缘层时对该待导体化区域过导体化。进而有效避免短沟道效应的产生，有效提升了顶栅结构氧化物薄膜晶体管的电学性能。

Description

氧化物薄膜晶体管及其制备方法、阵列基板和显示装置
技术领域
本发明涉及显示技术领域，特别是涉及一种氧化物薄膜晶体管及其制备方法、阵列基板和显示装置。
背景技术
顶栅结构氧化物薄膜晶体管(Oxide Thin Film Transistor，Oxide TFT)是一种栅极在沟道区上方的TFT结构，因一般使用栅极对沟道区域进行光照保护，因此顶栅结构TFT电学性能通常优于底栅结构TFT。
然而，现有顶栅结构中氧化物半导体层在导体化处理后，会因后续工艺的高温以及等离子体轰击，导致该半导体层中已导体化的区域进一步导体化，使得沟道被缩短，产生短沟道效应。该短沟道效应会使得阈值电压负向漂移严重，影响TFT的稳定性，进而影响显示品质。
发明内容
本发明要解决的技术问题是提供一种氧化物薄膜晶体管及其制备方法、阵列基板和显示装置，解决顶栅结构TFT制成工艺中存在的短沟道效应问题。
一方面，提供了一种氧化物薄膜晶体管制备方法，包括：
提供基板；
在所述基板上依次形成遮光层、第一绝缘层和半导体层；
在所述半导体层上依次形成第二绝缘层、栅极和第三绝缘层，其中，第二绝缘层在所述基板上的投影覆盖所述半导体层在所述基板上的投影；
去除所述半导体层中待导体化区域上覆盖的第二绝缘层和第三绝缘层；
通过导体化工艺处理所述待导体化区域，形成导体化区域；
在所述导体化区域上形成第一电极和第二电极。
进一步地，在形成所述第三绝缘层前，通过构图工艺形成的第二绝缘层覆盖在所述半导体层上，以遮盖所述待导体化区域。
进一步地，覆盖在所述待导体化区域上的第二绝缘层的厚度大于预设厚度阈值。
进一步地，在所述导体化区域上形成第一电极和第二电极之前，还包括：去除所述遮光层设定区域上覆盖的第一绝缘层和第三绝缘层，形成电压平衡连接孔；其中，所述电压平衡连接孔用于在形成第一电极和第二电极后，实现遮光层与第一电极的连接。
进一步地，所述去除所述遮光层设定区域上覆盖的第一绝缘层和第三绝缘层，形成电压平衡连接孔的步骤，包括：去除所述遮光层设定区域上覆盖的第三绝缘层；在去除所述待导体化区域上覆盖的第三绝缘层和第二绝缘层的同时，去除所述遮光层设定区域上覆盖的第一绝缘层。
进一步地，所述去除所述遮光层设定区域上覆盖的第一绝缘层和第三绝缘层，形成电压平衡连接孔的步骤，包括：在去除所述待导体化区域上覆盖的第三绝缘层的同时，去除所述遮光层设定区域上覆盖的第三绝缘层；在去除所述待导体化区域上覆盖的第二绝缘层的同时，去除所述遮光层设定区域上覆盖的第一绝缘层。
进一步地，所述通过导体化工艺处理所述待导体化区域的步骤，包括：通过等离子体对所述待导体化区域进行导体化处理，以降低所述待导体化区域处半导体的氧含量。
进一步地，在所述导体化区域上形成第一电极和第二电极之后，还包括：在所述第一电极、所述第二电极以及所述第三绝缘层上形成第四绝缘层，作为钝化层。
另一方面，还提供了一种氧化物薄膜晶体管，采用上述任一种氧化物薄膜晶体管制备方法制备。
又一方面，还提供了一种阵列基板，包括如上所述的氧化物薄膜晶体管。
再一方面，还提供了一种显示装置，包括如上所述的阵列基板。
与现有技术相比，本发明包括以下优点：
本发明提供了一种氧化物薄膜晶体管及其制备方法、阵列基板和显示装置，在本发明提供的氧化物薄膜晶体管制备方法中，通过在半导体层上依次形成第二绝缘层、栅极和第三绝缘层后，去除半导体层中待导体化区域上覆盖的第二绝缘层和第三绝缘层，再通过导体化工艺处理待导体化区域，形成导体化区域。从而使得待导体化区域在第二绝缘层的遮盖下，有效避免在形成第三绝缘层时对该待导体化区域过导体化。进而有效避免短沟道效应的产生，有效提升了顶栅结构氧化物薄膜晶体管的电学性能。
附图说明
图1是本发明实施例提供的一种氧化物薄膜晶体管制备方法的流程图；
图2是本发明实施例提供的另一种氧化物薄膜晶体管制备方法的流程图；
图3是本发明实施例提供的一种制备氧化物薄膜晶体管的工艺流程示意图之一；
图4是本发明实施例提供的一种制备氧化物薄膜晶体管的工艺流程示意图之二；
图5是本发明实施例提供的一种制备氧化物薄膜晶体管的工艺流程示意图之三；
图6是本发明实施例提供的一种制备氧化物薄膜晶体管的工艺流程示意图之四；
图7是本发明实施例提供的一种制备氧化物薄膜晶体管的工艺流程示意图之五；
图8是本发明实施例提供的一种制备氧化物薄膜晶体管的工艺流程示意图之六；
图9是本发明实施例提供的一种制备氧化物薄膜晶体管的工艺流程示意图之七；
图10是本发明实施例提供的一种制备氧化物薄膜晶体管的工艺流程示意图之八；
图11是本发明实施例提供的另一种绝缘层刻蚀状态示意图；
图12是本发明实施例提供的一种阵列基板的剖面结构示意图。
具体实施方式
为使本发明的上述目的、特征和优点能够更加明显易懂，下面结合附图和具体实施方式对本发明作进一步详细的说明。
在本发明的描述中，除非另有说明，“多个”的含义是两个或两个以上；术语“上”、“下”、“左”、“右”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本发明和简化描述，而不是指示或暗示所指的机或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本发明的限制。
在本发明的描述中，需要说明的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接；可以是直接相连，也可以通过中间媒介间接相连。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本发明中的具体含义。本发明实施例中，为区分晶体管的除栅极之外的两极，将其中的源、漏极称为第一电极、第二电极。
下面结合附图和实施例对本发明的具体实施方式作进一步详细描述。以下实施例用于说明本发明，但不用来限制本发明的范围。
现有技术中，为了形成顶栅结构氧化物薄膜晶体管(Oxide Thin FilmTransistor，Oxide TFT)，在通过构图工艺形成半导体层与栅极之间的第二绝缘层时，通常会完全刻蚀掉半导体层中待导体化区域上覆盖的第二绝缘层，将该待导体化区域显露出来，并通过导体化工艺处理该显露出来待导体化区域。在完成对该待导体化区域的导体化工艺处理后，再形成第三绝缘层。
然而，一方面，在形成该第三绝缘层时，该第三绝缘层将形成在导体化区域的表面，与导体化区域相接触。而且形成该第三绝缘层的过程存在高温、等离子轰击等工艺，例如，在通过化学气相沉积(Plasma Enhanced Chemical Vapor Deposition，PECVD)形成该第三绝缘层时，沉积的温度约为300℃，且PECVD设备腔室内含有大量等离子体。这些工艺将夺走半导体层中氧离子，导致原本已经导体化的半导体层进一步导体化，进而导致TFT的沟道缩短，产生短沟道效应。其中，该短沟道效应是指随着TFT沟道缩短，阈值电压Vth负向漂移严重，影响TFT的稳定性。
另一方面，在将导体化区域上覆盖的第三绝缘层刻蚀掉后，由于第二绝缘层和第三绝缘层的厚度较大。因此，该连接孔的深度将较深，容易堆积硬化光刻胶、有机聚合物等刻蚀过程中产生的杂质，且由于连接孔较深，使得硬化光刻胶、有机聚合物等杂质难以被剥离药液清除干净，从而成为孔内残留物。这些孔内残留物覆盖在导体化区域表面，会导致第一电极、第二电极与导体化区域的接触电阻增加，进而影响显示面板的显示品质。
针对上述缺陷，本发明实施例提供了一种氧化物薄膜晶体管制备方法。
参照图1，示出了本发明实施例提供的一种氧化物薄膜晶体管制备方法的流程图。参照图3-10，示出了本发明实施例提供的一种制备氧化物薄膜晶体管的工艺流程示意图。
步骤101，提供基板。
具体的，该基板301可以为刚性基板或者柔性基板。
步骤102，在基板上依次形成遮光层、第一绝缘层和半导体层。
如图3所示，可以在该基板301上通过不透光的材料形成遮光层302。例如，可以形成黑矩阵(Black Matrix，BM)层作为遮光层302，或者利用金属层作为遮光层302。其中，该BM层为通过构图工艺制作的黑色光刻胶层。
在形成遮光层302后，在遮光层302上形成绝缘薄膜，作为第一绝缘层303。在第一绝缘层303上形成金属氧化物半导体薄膜，并通过构图工艺形成半导体层304。其中，构图工艺包括光刻、刻蚀和剥离等步骤。
步骤103，在半导体层上依次形成第二绝缘层、栅极和第三绝缘层。
其中，第二绝缘层305在基板301上的投影覆盖半导体层304在基板301上的投影。
具体的，如图4所示，可以先形成第二绝缘层305和栅极306，并通过构图工艺依次使栅极306和第二绝缘层305图案化。其中，在通过构图工艺形成图案化的第二绝缘层305时，可以保留待导体化区域3041上覆盖的第二绝缘层305，使得在待导体化区域3041上覆盖的第二绝缘层305可以对待导体化区域3041起到保护作用，避免在形成第三绝缘层307时对该待导体化区域3041产生导体化影响。
如图5所示，在半导体层304上依次形成图案化的栅极306和第二绝缘层305后，继续形成第三绝缘层307。在形成第三绝缘层307时，半导体层304中的待导体化区域3041在第二绝缘层305的遮盖下，可以避免受到制备过程中高温、等离子轰击等因素的影响，从而避免半导体材料中的氧离子被夺走，使得该区域半导体层304的性质不会发生变化。
步骤104，去除半导体层中待导体化区域上覆盖的第二绝缘层和第三绝缘层。
在栅极306上形成第三绝缘层307后，便消除了第三绝缘层307的制备过程对待导体化区域3041的影响。对保持半导体特性的待导体化区域3041进行导体化处理，可以准确控制对该待导体化区域3041的导体化程度，避免过导体化。为了对待导体化区域3041进行导体化处理，需要去除半导体层304中待导体化区域3041上覆盖的第二绝缘层305和第三绝缘层307，以显露出该待导体化区域3041。
具体的，如图6、图7所示，在去除半导体层304中待导体化区域3041上覆盖的第二绝缘层305和第三绝缘层307时，由于第二绝缘层305和第三绝缘层307的厚度较大，可以通过分步刻蚀形成该连接孔。例如，可以先通过高速刻蚀去除待导体化区域3041上覆盖的一部分绝缘薄膜，再通过低速刻蚀去除剩余部分绝缘薄膜，以显露出该待导体化区域3041。从而使该连接孔具有较缓和的坡度角。
步骤105，通过导体化工艺处理待导体化区域，形成导体化区域。
具体的，如图8所示，在去除半导体层304中待导体化区域3041上覆盖的第二绝缘层305和第三绝缘层307后，可以通过导体化工艺处理待导体化区域3041，形成导体化区域3042。其中，导体化处理的方式不作限定，可根据具体的半导体材料选择相对应的导体化方式。
在实际应用中，导体化处理时使用的等离子体，在作用于待导体化区域3041表面时，可以去除刻蚀第三绝缘层307和第二绝缘时残留在待导体化区域3041表面的硬化光刻胶、有机聚合物等杂质。从而可以有效清洁待导体化区域3041表面，避免这些杂质增加第一电极308、第二电极309各自与导体化区域3042的接触电阻。
步骤106，在导体化区域上形成第一电极和第二电极。
具体的，如图9所示，在将待导体化区域3041通过导体化处理，形成导体化区域3042后，可以在该导体化区域3042上形成TFT的第一电极308和第二电极309。第一电极308和第二电极309覆盖在该导体化区域3042上，从而与该导体化区域3042连接。
综上所述，在本发明实施例中，通过在半导体层304上依次形成第二绝缘层305、栅极306和第三绝缘层307后，在第三绝缘层307上通过构图工艺，去除半导体层304中待导体化区域3041上覆盖的第二绝缘层305和第三绝缘层307，再通过导体化工艺处理待导体化区域3041，形成导体化区域3042。从而使得待导体化区域3041在第二绝缘层305的遮盖下，有效避免在形成第三绝缘层307时对该待导体化区域3041过导体化。进而有效避免短沟道效应的产生，有效提升了顶栅结构氧化物薄膜晶体管的电学性能。而且还能够通过导体化工艺清除待导体化区域3041表面堆积的杂质，从而降低了第一电极308、第二电极309各自与导体化区域3042的接触电阻，提升了显示面板的显示品质。
参照图2，示出了本发明实施例提供的另一种氧化物薄膜晶体管制备方法的流程图。
步骤201，提供基板。
具体的，该基板301可以为柔性基板或者刚性基板，可以由用于形成元件的具有优良机械强度或尺寸稳定性的的材料形成。例如，基板301的材料可以是玻璃、金属、陶瓷、塑料等。其中，用于制备基板301的塑料可以为聚碳酸酯树脂、丙烯酸树脂、氯乙烯树脂、聚对苯二甲酸乙二醇酯树脂、聚酰亚胺树脂、聚酯树脂、环氧树脂、硅树脂、含氟树脂等。
步骤202，在基板上依次形成遮光层、第一绝缘层和半导体层。
具体的，可以通过无机绝缘薄膜形成第一绝缘层303，制备该无机绝缘薄膜的材料可以为：硅的氧化物(SiOx)、硅的氮化物(SiNx)、铪的氧化物(HfOx)、硅的氮氧化物(SiON)、铝的氧化物(AlOx)或有机材料中的一种或几种的组合。在实际应用中，也可以通过该无机绝缘薄膜形成第二绝缘层305、第三绝缘层307和第四绝缘层310。可根据不同绝缘层所起的作用不同选择相对应的材料制备绝缘薄膜。
该半导体层304可以由氧化物半导体材料制备，该氧化物半导体材料可以为包含铟(In)、镓(Ga)、锌(Zn)、氧(O)、锡(Sn)等元素中一种或多种的氧化物半导体。优选的，该氧化物半导体材料可以为氧化铟镓锌(IGZO)、氧化铟锌(IZO)、氧化铟锡(InSnO)、氧化铟镓锡(InGaSnO)中的一种。优选的，该半导体层304的厚度可以在30-100nm之间。
步骤203，通过构图工艺形成第二绝缘层和栅极。
如图4所示，在基板301上依次形成遮光层302、第一绝缘层303和半导体层304后，可以先通过构图工艺形成栅极306，再通过构图工艺形成第二绝缘层305。
具体的，在通过构图工艺形成第二绝缘层305时，可以对未覆盖半导体层304的第二绝缘层305和覆盖在待导体化区域3041上的第二绝缘层305进行不同程度的刻蚀。例如，可以将未覆盖半导体层304的第二绝缘层305全部刻蚀掉，但不将覆盖在待导体化区域3041上的第二绝缘层305全部刻蚀掉，并使得覆盖在待导体化区域3041上的第二绝缘层305的厚度大于预设厚度阈值，以使该待导体化区域3041上的第二绝缘层305，能够有效保护该待导体化区域3041，避免在形成第三绝缘层307时对该待导体化区域3041产生导体化影响。而且将待导体化区域3041上覆盖的第二绝缘层305刻蚀掉一部分，也有利于在形成第三绝缘层307后对这两层绝缘层刻蚀时，减少刻蚀对象的厚度，从而节省刻蚀液用量，并且可以降低该工艺所需时间。
在实际应用中，制备栅极306、第一电极308、第二电极309的材料可以为钼(Mo)、钼铌合金(MoNb)、铝(Al)、铝钕合金(AlNd)、钛(Ti)和铜(Cu)中的一种或它们中多种材料形成的单层或多层复合叠层。
步骤204，在栅极上形成第三绝缘层，并通过构图工艺将第三绝缘层、第二绝缘层和第一绝缘层图案化。
在通过构图工艺将第三绝缘层307、第二绝缘层305和第一绝缘层303图案化时，可以通过构图工艺，去除半导体层304中待导体化区域3041上覆盖的第二绝缘层305和第三绝缘层307，以显露出待导体化区域3041。也可以通过构图工艺，去除遮光层302设定区域上覆盖的第一绝缘层303和第三绝缘层307，形成电压平衡连接孔。其中，该电压平衡连接孔用于在形成第一电极308和第二电极309后，实现遮光层与第一电极308的连接。从而使第一电极308能够及时导走遮光层302上堆积的电荷，提高阈值电压均一性。
具体的，可以先去除遮光层302设定区域上覆盖的第三绝缘层307。然后在去除待导体化区域3041上覆盖的第三绝缘层307和第二绝缘层305的同时，去除遮光层302设定区域上覆盖的第一绝缘层303，以形成该电压平衡连接孔。也可以在去除待导体化区域3041上覆盖的第三绝缘层307的同时，去除遮光层302设定区域上覆盖的第三绝缘层307。并在去除待导体化区域3041上覆盖的第二绝缘层305的同时，去除遮光层302设定区域上覆盖的第一绝缘层303。
在实际应用中，通过构图工艺将第三绝缘层307、第二绝缘层305和第一绝缘层303图案化的过程，可以如图6所示，先刻蚀电压平衡连接孔处的第三绝缘层307，再如图7所示，刻蚀待导体化区域3041上覆盖的第三绝缘层307、第二绝缘层305，以及电压平衡连接孔处的第一绝缘层303。参照图11，示出了本发明实施例提供的另一种绝缘层刻蚀状态示意图。如图11所示，可以先同时刻蚀电压平衡连接孔处的第三绝缘层307，以及待导体化区域3041上覆盖的第三绝缘层307。再刻蚀待导体化区域3041上覆盖的第二绝缘层305，以及电压平衡连接孔处的第一绝缘层303。具体的，可以根据各绝缘层的厚度，确定对各位置绝缘层的刻蚀顺序和刻蚀速度，不限于上述两种方法。
步骤205，通过导体化工艺处理待导体化区域，形成导体化区域。
具体的，如图8所示，可以通过等离子体对待导体化区域3041进行导体化处理，以降低该待导体化区域3041处半导体的氧含量。例如，可以通过氦气等离子体(He plasma)、氨气等离子体(NH3plasma)、氢气等离子体(H2plasma)等对待导体化区域3041进行导体化处理。
步骤206，在导体化区域上形成第一电极和第二电极。
具体的，如图9所示，在将待导体化区域3041通过导体化处理，形成导体化区域3042后，可以在该导体化区域3042上形成TFT的第一电极308和第二电极309。第一电极308和第二电极309覆盖在该导体化区域3042上，从而与该导体化区域3042连接。在实际应用中，如图10所示，在导体化区域上形成第一电极308和第二电极309后，还可以形成第四绝缘层310作为钝化层保护该氧化物薄膜晶体管。
综上所述，在本发明实施例中，通过在形成第三绝缘层307前，对待导体化区域3041上覆盖的第二绝缘层305进行部分刻蚀，既能够起到保护待导体化区域3041免受过导体化，又能够减轻形成第三绝缘层307后，对这两层绝缘层刻蚀的负担，从而节省刻蚀液用量，并且可以降低该工艺所需时间。而且，通过电压平衡连接孔使遮光层302与第一电极308或者第二电极309相连，使得第一电极308或者第二电极309能够及时导走遮光层302上堆积的电荷，提高阈值电压均一性。
在上述实施例基础上，参照图12，本发明实施例还提供了一种阵列基板，该阵列基板包括以上所述的氧化物薄膜晶体管。本领域技术人员可以知道的是，阵列基板还包括位于第四绝缘层310上的像素电极311。其中，该像素电极311的材质可以为氧化铟锡(IndiumTin Oxide，ITO)或者氧化铟锌(Indium Zinc Oxide，IZO)等透明导电物，但不限于上述几种。
此外，本发明实施例还提供了一种显示装置，该显示装置包括以上所述的阵列基板。具体地，该显示装置可以为：液晶显示面板、OLED显示面板、电子纸、有机发光显示面板、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
本说明书中的各个实施例均采用递进的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似的部分互相参见即可。
以上对本发明所提供的一种氧化物薄膜晶体管及其制备方法、阵列基板和显示装置进行了详细介绍，本文中应用了具体个例对本发明的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本发明的方法及其核心思想；同时，对于本领域的一般技术人员，依据本发明的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本发明的限制。

Claims (9)

1.一种氧化物薄膜晶体管制备方法，包括：
提供基板；
在所述基板上依次形成遮光层、第一绝缘层和半导体层；
在所述半导体层上依次形成第二绝缘层、栅极和第三绝缘层，其中，所述第二绝缘层在所述基板上的正投影与所述半导体层在所述基板上的正投影重叠；且覆盖在待导体化区域上的所述第二绝缘层的厚度大于预设厚度阈值；
去除所述半导体层中所述待导体化区域上覆盖的所述第二绝缘层和所述第三绝缘层；
通过导体化工艺处理所述待导体化区域，形成导体化区域；
在所述导体化区域上形成第一电极和第二电极；
其中，对所述第二绝缘层和所述第三绝缘层先采用高速刻蚀，再采用低速刻蚀以形成连接孔；
所述第二绝缘层被配置为保护所述半导体层，以避免在形成所述第三绝缘层时对所述待导体化区域的过导体化；
其中，制备得到的所述氧化物薄膜晶体管的所述第二绝缘层包括第一区域和围绕所述第一区域的第二区域，所述第二绝缘层位于所述第一区域的部分沿垂直于所述基板方向的厚度大于所述第二绝缘层位于所述第二区域的部分沿垂直于所述基板方向的厚度；
所述栅极与所述第二绝缘层位于所述第一区域的部分直接接触；
所述第三绝缘层包括平坦部和围绕所述平坦部的凸出部，所述平坦部覆盖所述栅极远离所述基板的表面，所述凸出部包裹所述栅极的侧面、包裹所述第二绝缘层位于所述第一区域的部分的侧面、并延伸至所述第二绝缘层位于所述第二区域的部分处，所述凸出部与所述第二绝缘层位于所述第二区域的部分相连；
导体化工艺包括采用氦气等离子体、氨气等离子体、氢气等离子体对所述待导体化区域进行处理。
2.根据权利要求1所述的制备方法，其特征在于，在所述导体化区域上形成第一电极和第二电极之前，还包括：
去除所述遮光层设定区域上覆盖的第一绝缘层和第三绝缘层，形成电压平衡连接孔；
其中，所述电压平衡连接孔用于在形成第一电极和第二电极后，实现遮光层与第一电极的连接。
3.根据权利要求2所述的制备方法，其特征在于，所述去除所述遮光层设定区域上覆盖的第一绝缘层和第三绝缘层，形成电压平衡连接孔的步骤，包括：
去除所述遮光层设定区域上覆盖的第三绝缘层；
在去除所述待导体化区域上覆盖的第三绝缘层和第二绝缘层的同时，去除所述遮光层设定区域上覆盖的第一绝缘层。
4.根据权利要求2所述的制备方法，其特征在于，所述去除所述遮光层设定区域上覆盖的第一绝缘层和第三绝缘层，形成电压平衡连接孔的步骤，包括：
在去除所述待导体化区域上覆盖的第三绝缘层的同时，去除所述遮光层设定区域上覆盖的第三绝缘层；
在去除所述待导体化区域上覆盖的第二绝缘层的同时，去除所述遮光层设定区域上覆盖的第一绝缘层。
5.根据权利要求1所述的制备方法，其特征在于，所述通过导体化工艺处理所述待导体化区域的步骤，包括：
通过等离子体对所述待导体化区域进行导体化处理，以降低所述待导体化区域处半导体的氧含量。
6.根据权利要求1所述的制备方法，其特征在于，在所述导体化区域上形成第一电极和第二电极之后，还包括：
在所述第一电极、所述第二电极以及所述第三绝缘层上形成第四绝缘层，作为钝化层。
7.一种氧化物薄膜晶体管，其特征在于，采用如权利要求1至6中任一项所述的氧化物薄膜晶体管制备方法制备。
8.一种阵列基板，其特征在于，包括如权利要求7所述的氧化物薄膜晶体管。
9.一种显示装置，其特征在于，包括如权利要求8所述的阵列基板。
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