WO2016045241A1 - 阵列基板及其制作方法、显示装置 - Google Patents

阵列基板及其制作方法、显示装置 Download PDF

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Publication number
WO2016045241A1
WO2016045241A1 PCT/CN2015/070047 CN2015070047W WO2016045241A1 WO 2016045241 A1 WO2016045241 A1 WO 2016045241A1 CN 2015070047 W CN2015070047 W CN 2015070047W WO 2016045241 A1 WO2016045241 A1 WO 2016045241A1
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Prior art keywords
layer
pixel electrode
array substrate
region
active layer
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PCT/CN2015/070047
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English (en)
French (fr)
Inventor
王盛
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京东方科技集团股份有限公司
合肥京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 合肥京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to EP15804664.9A priority Critical patent/EP3200231B1/en
Priority to US14/769,221 priority patent/US9786696B2/en
Publication of WO2016045241A1 publication Critical patent/WO2016045241A1/zh

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    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2202/00—Materials and properties
    • G02F2202/10—Materials and properties semiconductor

Definitions

  • Embodiments of the present invention relate to an array substrate, a method of fabricating the same, and a display device.
  • the metallizing treatment comprises treating the metal oxide semiconductor in the pixel electrode pre-structure in a reducing atmosphere of 100-300 ° C for 30-120 min.
  • a photoresist complete retention region, a photoresist partial retention region, and a photoresist complete removal region are formed by a patterning process, and the photoresist complete retention region corresponds to the active layer Where the channel region is located, the photoresist portion retention region corresponds to a region where the ohmic contact region in the active layer is located and a region where the pixel electrode is located, and the photoresist complete removal region corresponds to other regions; Etching the etch stop layer and the metal oxide semiconductor layer without the photoresist overlying region; removing the photoresist partial retention region by an ashing process while the photoresist is completely The thickness of the reserved region is thinned; the etch stop layer exposed after removing the remaining portion of the photoresist portion is removed; and the photoresist is stripped to form the active layer, the pixel electrode a pattern of a pre-structure and the etch stop structure, the etch stop structure being located on a channel region in the active layer
  • the method for fabricating the array substrate further includes: forming a passivation layer on the pattern of the data line, the source, and the drain; on the passivation layer, A pattern including a transparent electrode is formed over the data line and the common electrode.
  • FIG. 4 is a schematic diagram of a process of fabricating an array substrate according to an embodiment of the present invention.
  • FIG. 7 is a specific flowchart of forming a pattern including an active layer and a pixel electrode disposed in the same layer on a substrate on which a gate insulating layer is formed in an embodiment of the present invention.
  • the drain 62 covers one end of the active layer 40 close to the pixel electrode 50 and one end of the pixel electrode 50 close to the active layer 40, and is filled in the active layer 40.
  • the connection between the drain electrode 62 and the pixel electrode 50 is achieved between the pixel electrode 50 and the pixel electrode 50.
  • the active layer 40 in the embodiment of the present invention includes a metal oxide semiconductor.
  • the pixel electrode 50 in the embodiment of the present invention is a structure in which a metal oxide semiconductor is metallized, and a metal oxide semiconductor for forming the pixel electrode 50 and a metal as the active layer 40 are used.
  • the materials of the oxide semiconductor are the same.
  • the above metal oxide semiconductor may be one or more of InGaZnO, InGaO, ITZO, and AlZnO.
  • the embodiment of the present invention further provides a display device, which includes the array substrate according to any of the above embodiments.
  • the array substrate and the opposite substrate are opposed to each other to form a liquid crystal cell, and the liquid crystal cell is filled with a liquid crystal material.
  • the opposite substrate is, for example, a color filter substrate.
  • the pixel electrode of each pixel unit of the array substrate is used to apply an electric field to control the degree of rotation of the liquid crystal material to perform a display operation.
  • the liquid crystal display device further includes a backlight that provides backlighting for the array substrate.
  • Step S503 forming an active layer on the base substrate 10 on which the gate insulating layer 30 is formed 40 and the pattern of the pixel electrode 50, the pixel electrode 50 and the active layer 40 are disposed in the same layer.
  • Step S707 removing the etch stop layer 32 exposed after removing the photoresist portion retention region 332.
  • the method of fabricating the array substrate further includes forming a passivation layer 70 on the base substrate 10 on which the pattern including the data line 60, the source 61, and the drain 62 is formed, and the substrate on which the passivation layer 70 is formed.
  • a pattern including the transparent electrode 90 is formed on the substrate 10.
  • the transparent electrode 90 is positioned above the data line and the common electrode 21, thereby shielding the electric field between the data line 60 and the pixel electrode 50, and can effectively reduce crosstalk between the data line 60 and the pixel electrode 50.
  • the transparent electrode 90 can also be connected to other wire layers through via holes to transmit external signals to the respective wire layers.

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Abstract

一种阵列基板及其制作方法、显示装置。阵列基板包括衬底基板（10）和依次位于衬底基板（10）上的同层设置的栅线（20）和公共电极（21）、栅极绝缘层（30）、有源层（40）、同层设置的源极（61）和漏极（62），以及像素电极（50），像素电极（50）和有源层（40）同层设置。

Description

阵列基板及其制作方法、显示装置 技术领域
本发明的实施例涉及一种阵列基板及其制作方法、显示装置。
背景技术
液晶显示器是一种常用的显示装置，其具有轻薄和低功耗等优点，被广泛应用于显示、通信、多媒体等多个技术领域。液晶显示器包括阵列基板等构造。
发明内容
本发明实施例提供了一种阵列基板，该阵列基板包括：衬底基板和依次位于所述衬底基板上的同层设置的栅线和公共电极、栅极绝缘层、有源层、同层设置的数据线、源极和漏极、以及像素电极，所述像素电极和所述有源层同层设置。
在一个示例中，所述漏极覆盖所述有源层靠近所述像素电极的一端以及所述像素电极靠近所述有源层的一端，并填充在所述有源层和所述像素电极之间。
在一个示例中，所述有源层包括金属氧化物半导体，并且所述像素电极通过金属氧化物半导体经金属化处理形成。
在一个示例中，用于形成所述像素电极的金属氧化物半导体与所述有源层包括的金属氧化物半导体的材料相同。
在一个示例中，所述有源层包括欧姆接触区和位于所述欧姆接触区之间的沟道区。
在一个示例中，所述阵列基板还包括位于所述沟道区上的刻蚀阻挡结构。
在一个示例中，所述有源层包括两个所述欧姆接触区，所述源极覆盖一个所述欧姆接触区，所述漏极覆盖另一个所述欧姆接触区以及所述像素电极靠近所述有源层的一端，并填充在所述有源层和所述像素电极之间。
在一个示例中，所述像素电极与靠近所述像素电极一侧的欧姆接触层之 间间隔设置，且所述漏极填充在所述间隔之间。
在一个示例中，所述公共电极包括与所述数据线平行的部分和与所述数据线垂直的部分。
在一个示例中，所述阵列基板还包括位于同层设置的所述数据线、所述源极和所述漏极上的钝化层以及位于所述钝化层上的透明电极，所述透明电极位于所述数据线和所述公共电极的上方。
在一个示例中，所述透明电极包括三个相互独立的透明导电部分，其中第一个透明导电部分通过过孔连接所述栅线，第二个透明导电部分通过过孔连接所述公共电极，第三个透明导电部分通过过孔连接所述数据线。
本发明实施例还提供了一种显示装置，该显示装置包括以上任一种实施方式所述的阵列基板。
本发明实施例还提供了一种阵列基板的制作方法，包括：在衬底基板上形成包括栅线和公共电极的图形；在所述栅线和所述公共电极的图形上，形成栅极绝缘层；在所述栅极绝缘层上，形成包括有源层和像素电极的图形，所述像素电极和所述有源层同层设置；以及形成包括数据线、源极和漏极的图形。
在该方法的一个示例中，在所述栅极绝缘层上，沉积一层金属氧化物半导体层，经过构图工艺形成包括所述有源层和像素电极预结构的图形；以及对所述像素电极预结构进行金属化处理，形成所述像素电极。
在该方法的一个示例中，所述金属化处理包括在100-300℃还原性气氛中对所述像素电极预结构中的金属氧化物半导体处理30-120min。
在该方法的一个示例中，所述还原性气氛使用的气体包括氢气或者含氢等离子体。
在该方法的一个示例中，还包括：在所述金属氧化物半导体层上，形成一层刻蚀阻挡层；以及在所述刻蚀阻挡层上，涂覆一层光刻胶。
在该方法的一个示例中，通过构图工艺，形成光刻胶完全保留区、光刻胶部分保留区和光刻胶完全去除区，所述光刻胶完全保留区对应于所述有源层中沟道区所在区域，所述光刻胶部分保留区对应于所述有源层中的欧姆接触区所在区域和所述像素电极所在区域，所述光刻胶完全去除区对应于其它区域；刻蚀去除无所述光刻胶覆盖区域的所述刻蚀阻挡层和所述金属氧化物半导体层；通过灰化工艺去除所述光刻胶部分保留区，同时所述光刻胶完全 保留区的厚度进行减薄；将去除所述光刻胶部分保留区后暴露的所述刻蚀阻挡层去除；以及，剥离所述光刻胶，形成包括所述有源层、所述像素电极预结构和所述刻蚀阻挡结构的图形，所述刻蚀阻挡结构位于所述有源层中的沟道区上。
在该方法的一个示例中，所述对所述像素电极预结构进行金属化处理，形成所述像素电极的同时，对所述有源层中用于形成所述欧姆接触区的区域进行金属化处理，形成所述欧姆接触区，以形成包括所述欧姆接触区和所述沟道区的所述有源层。
在该方法的一个示例中，所述阵列基板的制作方法还包括：在所述数据线、所述源极和所述漏极的图形上，形成钝化层；在所述钝化层上，形成包括透明电极的图形，所述透明电极位于所述数据线和所述公共电极上方。
附图说明
以下将结合附图对本发明的实施例进行更详细的说明，以使本领域普通技术人员更加清楚地理解本发明，其中：
图1为阵列基板的截面示意图；
图2为本发明实施例中的阵列基板的平面示意图；
图3为本发明实施例中图2沿A-A’方向的截面示意图；
图4为本发明实施例中的阵列基板的制作过程示意图；
图5为本发明实施例中的阵列基板的制作流程图；
图6为本发明实施例中在形成了栅极绝缘层的衬底基板上，形成包括同层设置的有源层和像素电极的图形的制作过程示意图；
图7为本发明实施例中在形成了栅极绝缘层的衬底基板上，形成包括同层设置的有源层和像素电极的图形的具体流程图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其它实施例，都属于本发明保护的范围。
除非另作定义，本文使用的技术术语或者科学术语应当为本发明所属领 域内具有一般技能的人士所理解的通常意义。本发明专利申请说明书以及权利要求书中使用的“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其它元件或者物件。“上”、“下”、等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
液晶显示器包括阵列基板、对置基板和二者之间的液晶层。一种阵列基板的结构如图1所示，该阵列基板包括衬底基板1’以及依次设置于衬底基板1’上的同层设置的栅极2’和公共电极3’，栅极绝缘层4’，有源层5’，同层设置的源极6’、漏极7’和数据线8’，钝化层9’和像素电极10’。像素电极10’、钝化层9’、栅极绝缘层4’和公共电极3’构成存储电容，存储电容的作用在于维持液晶显示器的显示画面的稳定。发明人发现，该技术中阵列基板上的存储电容较小，不利于显示画面的稳定。
下面将对本发明的示例性实施例进行说明。
实施例一
如图2和图3所示，本发明实施例的阵列基板包括衬底基板10和依次位于衬底基板10上的同层设置的栅线20和公共电极21、栅极绝缘层30(图2中无法看到栅极绝缘层30)、有源层40、同层设置的数据线60、源极61和漏极62，该阵列基板还包括像素电极50，像素电极50和有源层40同层设置。此时，存储电容为像素电极50、栅极绝缘层30和公共电极21形成的电容；而图1中存储电容为像素电极、钝化层、栅极绝缘层和公共电极形成的电容，因此与其相比，本发明实施例中的存储电容中的绝缘层仅为栅极绝缘层30，从而使得像素电极50、栅极绝缘层30和公共电极21形成的存储电容较大，从而能够有效改善显示装置的显示效果。
此外，由于像素电极50和有源层40同层设置，因此，漏极62覆盖有源层40靠近像素电极50的一端以及像素电极50靠近有源层40的一端，并填充在有源层40和像素电极50之间，以实现漏极62与像素电极50的连接。
如图2所示，本发明实施例中的公共电极21包括与数据线60平行的部分和与数据线60垂直的部分，此种设计能够有效减小公共电极21的电阻，改善阵列基板的性能。
需要说明的是，本发明实施例中的阵列基板上未单独设置有栅极，而是 使有源层40位于栅线20上方，栅线20上的信号即可实现对有源层40的控制，进而控制源极和漏极之间是否导通，本领域技术人员也可以在阵列基板上单独设置栅极，本发明实施例对此不进行限定。
例如，由于金属氧化物半导体具有较高的迁移率，因此，本发明实施例中的有源层40包括金属氧化物半导体。为了简化阵列基板的制作方法，本发明实施例中的像素电极50为金属氧化物半导体经金属化处理形成的结构，且用于形成像素电极50的金属氧化物半导体与作为有源层40的金属氧化物半导体的材料相同。示例性地，上述金属氧化物半导体可以为InGaZnO、InGaO、ITZO、AlZnO中的一种或者多种。
例如，如图3所示，有源层40包括欧姆接触区41和位于欧姆接触区41之间的用于作为沟道的沟道区42。欧姆接触区41可通过对有源层40中用于作为欧姆接触区41的区域进行金属化处理形成。阵列基板还可以包括位于沟道区42上的刻蚀阻挡结构80。刻蚀阻挡结构80在金属化处理过程中可以保护沟道区42的金属氧化物半导体不被金属化处理。
示例性地，有源层40包括两个欧姆接触区41时，源极61覆盖一个欧姆接触区41，漏极62覆盖另一个欧姆接触区41并且像素电极50靠近有源层40的一端，漏极62位于有源层40和像素电极50之间，以实现漏极62和像素电极50的连接。
此外，如图2和图3所示，本发明实施例中的阵列基板还可以包括位于同层设置的数据线60、源极61和漏极62上的钝化层70以及位于钝化层70上的透明电极90。透明电极90位于数据线60和公共电极21上方。一方面，能够减小数据线60和像素电极50之间形成的耦合电容，从而减小数据线60和像素电极50之间的串扰。例如，透明电极90包括多个相互独立的透明导电部分，每个透明导电部分通过过孔连接下方的导线。示例性地，透明电极90包括三个相互独立的透明导电部分，其中第一个透明导电部分通过过孔连接栅线20，将栅极驱动信号提供给栅线，第二个透明导电部分通过过孔连接公共电极21，将公共电极信号提供给公共电极21，第三个透明导电部分通过过孔连接数据线60，从而将数据信号提供给数据线60。
另一方面，由于像素电极50上覆盖有钝化层70和透明电极90，所以当液晶盒内部存在金属性异物时，金属性异物不会使得像素电极50和彩膜基板上的公共电极直接导通，不会影响显示装置的显示效果。
本发明实施例提供了一种阵列基板，该阵列基板包括衬底基板和依次位于衬底基板上的同层设置的栅线和公共电极、栅极绝缘层、有源层、同层设置的数据线、源极和漏极。阵列基板还包括像素电极，像素电极和有源层同层设置。如图1所示的阵列基板上的存储电容为像素电极、钝化层、栅极绝缘层和公共电极形成的电容，而本发明实施例中像素电极和公共电极之间仅设置有栅极绝缘层，因此存储电容为像素电极、栅极绝缘层和公共电极形成的电容，从而能够有效地提高存储电容，改善显示装置的显示效果。
此外，本发明实施例还提供了一种显示装置，该显示装置包括以上任一种实施方式所述的阵列基板。例如，该阵列基板与对置基板彼此对置以形成液晶盒，在液晶盒中填充有液晶材料。该对置基板例如为彩膜基板。阵列基板的每个像素单元的像素电极用于施加电场对液晶材料的旋转的程度进行控制从而进行显示操作。在一些示例中，该液晶显示装置还包括为阵列基板提供背光的背光源。
该显示装置可以为：液晶面板、电子纸、有机发光显示面板、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪、手表等任何具有显示功能的产品或部件。
实施例二
本发明实施例提供了一种阵列基板的制作方法，该阵列基板的制作方法用于制作实施例一中所述的阵列基板。阵列基板的制作过程如图4所示，包括图5所示的各个步骤。
步骤S501、在衬底基板10上形成栅线20和公共电极21的图形。
首先，在衬底基板10上沉积一层栅极金属层；其次，经过构图工艺形成包括栅线20和公共电极21的图形。需要说明的是，如无特别强调，本申请中的构图工艺可以包括：涂覆光刻胶、使用具有相应图案的掩膜板遮盖、曝光、显影、刻蚀和剥离光刻胶。
需要说明的是，本发明实施例中未在阵列基板上还形成独立的栅极，本领域技术人员也可以在形成栅线20的同时另外形成栅极，本发明实施例对此不进行限定。
步骤S502、在形成了包括栅线20和公共电极21的图形的衬底基板10上，形成栅极绝缘层30。
步骤S503、在形成了栅极绝缘层30的衬底基板10上，形成包括有源层 40和像素电极50的图形，像素电极50和有源层40同层设置。
首先，在形成了栅极绝缘层30的衬底基板10上，沉积一层金属氧化物半导体层，经过构图工艺形成包括有源层40和像素电极预结构的图形。
其次，对像素电极预结构进行金属化处理，形成像素电极50。例如，金属化处理包括在100-300℃还原性气氛中对像素电极预结构中的金属氧化物半导体处理30-120min，还原性气氛包括氢气或者含氢等离子体。在金属化处理过程中，将氢元素掺杂入金属氧化物半导体中，从而使得金属氧化物半导体转化为导体。
步骤S504、在形成了包括像素电极50的图形的衬底基板10上，形成包括数据线60、源极61和漏极62的图形。
首先，在形成了包括像素电极50的图形的衬底基板10上沉积一层数据线金属层；其次，经过构图工艺形成包括数据线60、源极61和漏极62的图形。
例如，步骤S503中在形成了栅极绝缘层30的衬底基板10上，沉积一层金属氧化物半导体层，经过构图工艺形成包括有源层40和像素电极预结构的图形的制作过程如图6所示，例如，包括如图7所示的步骤。
步骤S701、在形成了栅极绝缘层30的衬底基板10上，沉积一层金属氧化物半导体层31。
步骤S702、在形成了金属氧化物半导体层31的衬底基板10上，形成一层刻蚀阻挡层32。
步骤S703、在形成了刻蚀阻挡层32的衬底基板10上，涂覆一层光刻胶33。
步骤S704、通过构图工艺，形成光刻胶完全保留区331、光刻胶部分保留区332和光刻胶完全去除区333。
光刻胶完全保留区331对应于有源层中用于作为沟道的沟道区所在区域，光刻胶部分保留区332对应于有源层中的欧姆接触区所在区域和像素电极所在区域，光刻胶完全去除区333对应于其它区域。
在构图工艺中优选使用灰阶掩膜板，该灰阶掩膜板包括完全不透光区、半透光区和完全透光区。完全不透光区对应于有源层中用于作为沟道的沟道区所在区域，显影后光刻胶33完全保留，形成光刻胶完全保留区331；半透光区对应于有源层中的欧姆接触区和像素电极所在区域，显影后光刻胶33 部分保留，形成光刻胶部分保留区332；完全透光区对应于其它区域，显影后光刻胶33完全去除，形成光刻胶完全去除区333。
步骤S705、刻蚀去除光刻胶完全去除区333的刻蚀阻挡层32和金属氧化物半导体层31。
步骤S706、通过灰化工艺去除部分光刻胶形成部分保留区332，同时对光刻胶完全保留区331的厚度进行减薄。
步骤S707、将去除光刻胶部分保留区332后暴露的刻蚀阻挡层32去除。
步骤S708、剥离光刻胶33，形成包括有源层、像素电极预结构和刻蚀阻挡结构的图形。刻蚀阻挡结构位于有源层中用于作为沟道的沟道区上。
对像素电极预结构进行金属化处理，形成像素电极的同时，对有源层中欧姆接触区所在区域进行金属化处理，形成欧姆接触区。沟道区上覆盖有刻蚀阻挡结构，使得沟道区未被金属化处理，以形成包括欧姆接触区和沟道区的有源层。
此外，阵列基板的制作方法还包括在形成了包括数据线60、源极61和漏极62的图形的衬底基板10上，形成钝化层70，以及在形成了钝化层70的衬底基板10上，形成包括透明电极90的图形。透明电极90位于数据线和公共电极21上方，从而对数据线60和像素电极50之间的电场起到屏蔽作用，能够有效减小数据线60和像素电极50之间的串扰。例如，透明电极90还可以通过过孔与其它导线层相连，从而将外部信号传输至各导线层。
此外，在阵列基板上形成各个膜层之前还可以包括清洗的步骤，以提高阵列基板的质量。
本发明实施例提供了一种阵列基板的制作方法，该阵列基板的制作方法包括：在衬底基板上形成包括栅线和公共电极的图形，形成栅极绝缘层，形成包括有源层的图形，形成包括像素电极的图形，像素电极和有源层同层设置，形成包括数据线、源极和漏极的图形。如图1所示的阵列基板上的存储电容为像素电极、钝化层、栅极绝缘层和公共电极形成的电容，而采用本发明实施例的制作方法制作的阵列基板上的像素电极和公共电极之间仅设置有栅极绝缘层，即存储电容为像素电极、栅极绝缘层和公共电极形成的电容，因此，能够有效提高存储电容，改善显示装置的显示效果。
以上所述仅是本发明的示范性实施方式，而非用于限制本发明的保护范围，本发明的保护范围由所附的权利要求确定。
本申请要求于2014年09月25日提交的名称为“一种阵列基板及其制作方法、显示装置”的中国专利申请No.201410498785.X的优先权，其全文以引用方式合并于本文。

Claims (20)

  1. 一种阵列基板，包括衬底基板和依次位于所述衬底基板上的同层设置的栅线和公共电极、栅极绝缘层、有源层、同层设置的数据线、源极和漏极，以及
    像素电极，其中，所述像素电极和所述有源层同层设置。
  2. 根据权利要求1所述的阵列基板，其中，所述漏极覆盖所述有源层靠近所述像素电极的一端以及所述像素电极靠近所述有源层的一端，并填充在所述有源层和所述像素电极之间。
  3. 根据权利要求1所述的阵列基板，其中，所述有源层包括金属氧化物半导体，并且所述像素电极通过金属氧化物半导体经金属化处理形成。
  4. 根据权利要求1-3任一项所述的阵列基板，其中，用于形成所述像素电极的金属氧化物半导体与所述有源层包括的金属氧化物半导体的材料相同。
  5. 根据权利要求1-4任一项所述的阵列基板，其中，所述有源层包括欧姆接触区和位于所述欧姆接触区之间的沟道区。
  6. 根据权利要求5所述的阵列基板，还包括位于所述沟道区上的刻蚀阻挡结构。
  7. 根据权利要求5或6所述的阵列基板，其中，所述有源层包括两个所述欧姆接触区，所述源极覆盖一个所述欧姆接触区，所述漏极覆盖另一个所述欧姆接触区以及所述像素电极靠近所述有源层的一端，并填充在所述有源层和所述像素电极之间。
  8. 根据权利要求4-7任一项所述的阵列基板，其中，所述像素电极与靠近所述像素电极一侧的欧姆接触层之间间隔设置，且所述漏极填充在所述间隔之间。
  9. 根据权利要求1-8任一项所述的阵列基板，其中，所述公共电极包括与所述数据线平行的部分和与所述数据线垂直的部分。
  10. 根据权利要求1-9任一项所述的阵列基板，还包括：
    位于同层设置的所述数据线、所述源极和所述漏极上的钝化层；以及
    位于所述钝化层上的透明电极，其中，所述透明电极位于所述数据线和所述公共电极之上方。
  11. 根据权利要求10所述的阵列基板，其中，所述透明电极包括三个相互独立的透明导电部分，
    其中，第一个透明导电部分通过过孔连接所述栅线，第二个透明导电部分通过过孔连接所述公共电极，第三个透明导电部分通过过孔连接所述数据线。
  12. 一种显示装置，包括如权利要求1-11任一项所述的阵列基板。
  13. 一种阵列基板的制作方法，包括：
    在衬底基板上形成包括栅线和公共电极的图形；
    在所述栅线和所述公共电极的图形上形成栅极绝缘层；
    在所述栅极绝缘层上形成包括有源层和像素电极的图形，所述像素电极和所述有源层同层设置；以及
    形成包括数据线、源极和漏极的图形。
  14. 根据权利要求13所述的阵列基板的制作方法，其中，在所述栅极绝缘层上，沉积一层金属氧化物半导体层，并且经过构图工艺形成包括所述有源层和像素电极预结构的图形；以及
    对所述像素电极预结构进行金属化处理，形成所述像素电极。
  15. 根据权利要求14所述的阵列基板的制作方法，其中，所述金属化处理包括在100-300℃还原性气氛中对所述像素电极预结构中的金属氧化物半导体处理30-120min。
  16. 根据权利要求15所述的阵列基板的制作方法，其中，所述还原性气氛使用的气体包括氢气或者含氢等离子体。
  17. 根据权利要求13-16任一项所述的阵列基板的制作方法，还包括：
    在所述金属氧化物半导体层上，形成一层刻蚀阻挡层；以及
    在所述刻蚀阻挡层上，涂覆一层光刻胶。
  18. 根据权利要求17所述的阵列基板的制作方法，还包括：
    通过构图工艺，形成光刻胶完全保留区、光刻胶部分保留区和光刻胶完全去除区，所述光刻胶完全保留区对应于所述有源层中沟道区所在区域，所述光刻胶部分保留区对应于所述有源层中的欧姆接触区所在区域和所述像素电极所在区域，所述光刻胶完全去除区对应于其它区域；
    去除无所述光刻胶覆盖的区域的所述刻蚀阻挡层和所述金属氧化物半导体层；
    去除所述光刻胶部分保留区，同时对所述光刻胶完全保留区的厚度进行减薄；
    将去除所述光刻胶部分保留区后暴露的所述刻蚀阻挡层去除；
    剥离所述光刻胶，形成包括所述有源层、所述像素电极预结构和所述刻蚀阻挡结构的图形，所述刻蚀阻挡结构位于所述有源层中的沟道区上。
  19. 根据权利要求18所述的阵列基板的制作方法，其中，对所述像素电极预结构进行金属化处理，形成所述像素电极的同时，对所述有源层中用于形成所述欧姆接触区的区域进行金属化处理，形成所述欧姆接触区，所述沟道区未被金属化处理，以形成包括所述欧姆接触区和所述沟道区的所述有源层。
  20. 根据权利要求13-19任一项所述的阵列基板的制作方法，还包括：
    在所述数据线、所述源极和所述漏极上，形成钝化层；
    在所述钝化层上，形成包括透明电极，所述透明电极位于所述数据线和所述公共电极上方。
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