CN104934448B - 阵列基板及其制作方法、显示装置 - Google Patents

阵列基板及其制作方法、显示装置 Download PDF

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CN104934448B
CN104934448B CN201510405418.5A CN201510405418A CN104934448B CN 104934448 B CN104934448 B CN 104934448B CN 201510405418 A CN201510405418 A CN 201510405418A CN 104934448 B CN104934448 B CN 104934448B
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CN104934448A (zh
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张贺攀
艾青南
李跃
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BOE Technology Group Co Ltd
Beijing BOE Optoelectronics Technology Co Ltd
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Beijing BOE Optoelectronics Technology Co Ltd
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Abstract

本发明提供一种阵列基板的制作方法，包括：形成包括像素电极的图形；所述制作方法还包括在形成包括像素电极的图形的步骤之后进行的：形成包括有源层的图形。相应地，本发明还提供一种阵列基板和一种显示装置。本发明的阵列基板制作过程中，有源层上不会残留导电物，从而减少漏电流的产生，进而提高阵列基板的质量，改善显示装置的显示效果。

Description

阵列基板及其制作方法、显示装置
技术领域
本发明涉及显示技术领域，具体涉及一种阵列基板及其制作方法、一种显示装置。
背景技术
随着显示产品更新换代速度加快，工艺指标要求的不断提高，在提高产品良率及高品质化的同时使得阵列基板制作工艺越来越复杂化和精细化，这就产生了目前现有的多掩膜的阵列基板的制作工艺。目前，制作阵列基板时，首先在基板上形成栅金属层，通过第一次构图工艺形成包括栅电极的图形；然后形成栅绝缘层和半导体材料层，通过第二次构图工艺形成有源层；再形成第一导电层，通过第三次构图工艺形成包括像素电极的图形；之后再分别形成源漏电极、钝化层、公共电极等结构。
但是，这种方法在刻蚀完第一导电层以形成像素电极后，会有少量的导电物残留在沟道区域，造成薄膜晶体管漏电流增大，像素区域电压异常，从而导致显示污染、串扰等不良问题。
发明内容
本发明的目的在于提供一种阵列基板、一种阵列基板的制作方法和一种显示装置，以减少有源层的沟道区域上残留的导电物，从而改善显示效果。
为了实现上述目的，本发明提供一种阵列基板的制作方法，包括：
形成包括像素电极的图形；
所述制作方法还包括在形成包括像素电极的图形的步骤之后进行的：
形成包括有源层的图形。
优选地，所述制作方法还包括在形成包括像素电极的图形的步骤之前进行的：
形成包括栅极的图形和栅绝缘层；
所述制作方法还包括在形成包括像素电极的图形的步骤和形成包括有源层的图形的步骤之间进行的：
形成缓冲绝缘层。
优选地，所述制作方法还包括在形成有源层的步骤之后进行的：
在所述缓冲绝缘层的对应于像素电极的位置形成过孔；
形成包括源极、漏极的图形，并且所述漏极通过所述过孔与所述像素电极相连。
优选地，所述制作方法还包括：
在所述源极和所述有源层之间形成源极欧姆接触层，在所述漏极和所述有源层之间形成漏极欧姆接触层。
优选地，形成源极欧姆接触层和漏极欧姆接触层的步骤包括：
形成掺杂半导体材料层；
对所述掺杂半导体材料层进行初次构图工艺，以形成覆盖整个有源层的源漏欧姆接触层；
对所述源漏欧姆接触层进行再次构图工艺，以形成间隔的源极欧姆接触层和漏极欧姆接触层。
优选地，形成覆盖整个有源层的源漏欧姆接触层的步骤和形成包括有源层的图形的步骤通过同一次构图工艺形成；
形成间隔的源极欧姆接触层和漏极欧姆接触层的步骤与形成包括源极、漏极的图形的步骤通过同一次构图工艺形成。
优选地，所述制作方法还包括在形成包括源极、漏极的图形的步骤之后进行的：
形成钝化层。
优选地，通过气相沉积的方法形成所述钝化层和所述缓冲绝缘层，所述钝化层和所述缓冲绝缘层的材料均包括硅的氮化物，形成所述钝化层时的腔室气压在1400mT～1600mT之间，形成所述缓冲绝缘层时的腔室气压在1100mT～1300mT之间。
优选地，所述制作方法还包括在形成钝化层的步骤之后进行的：
形成包括公共电极的图形，所述公共电极包括多个公共电极条。
相应地，本发明还提供一种阵列基板，包括薄膜晶体管和像素电极，其中，所述像素电极位于所述薄膜晶体管的有源层所在层的下方，且与所述有源层绝缘间隔，所述像素电极与所述薄膜晶体管的漏极电连接。
优选地，所述薄膜晶体管的有源层和所述像素电极之间设置有缓冲绝缘层。
优选地，所述缓冲绝缘层的对应于所述像素电极的位置设置有过孔，所述薄膜晶体管的漏极通过所述过孔与所述像素电极相连。
优选地，所述薄膜晶体管的源极和所述有源层之间设置有源极欧姆接触层，所述薄膜晶体管的漏极和所述有源层之间设置有漏极欧姆接触层。
优选地，所述阵列基板还包括钝化层和设置在所述钝化层上的公共电极，所述公共电极包括多个公共电极条，所述钝化层覆盖所述薄膜晶体管的源极、漏极和所述缓冲绝缘层。
优选地，所述缓冲绝缘层和钝化层的材料均包括硅的氮化物。
相应地，本发明还提供一种显示装置，包括本发明提供的上述阵列基板。
由于本发明中在阵列基板的制作方法中，形成包括像素电极的图形的步骤在前，形成包括有源层的图形的步骤在后，即像素电极制作完成后才开始形成用于制作有源层的半导体材料层，因此，有源层上不会残留导电物，从而减少漏电流的产生，进而提高阵列基板的质量，改善显示装置的显示效果。
附图说明
附图是用来提供对本发明的进一步理解，并且构成说明书的一部分，与下面的具体实施方式一起用于解释本发明，但并不构成对本发明的限制。在附图中：
图1是本发明提供的制作方法中形成栅极的示意图；
图2是形成栅绝缘层的示意图；
图3是形成像素电极的示意图；
图4是形成缓冲绝缘层、半导体材料层和掺杂半导体层的示意图；
图5是形成半导体层和源漏欧姆接触层的示意图；
图6是在缓冲绝缘层上形成过孔的示意图；
图7是形成源漏金属层的示意图；
图8是形成源极、漏极、源极欧姆接触层和漏极欧姆接触层的示意图；
图9是形成钝化层的结构示意图；
图10是形成公共电极的示意图。
其中，附图标记为：1、栅极；2、栅绝缘层；3、像素电极；4、缓冲绝缘层；5、有源层；51、半导体材料层；6、掺杂半导体层；61、源漏欧姆接触层；62、源极欧姆接触层；63、漏极欧姆接触层；7、过孔；8、源漏金属层；81、源极；82、漏极；9、钝化层；10、公共电极条。
具体实施方式
以下结合附图对本发明的具体实施方式进行详细说明。应当理解的是，此处所描述的具体实施方式仅用于说明和解释本发明，并不用于限制本发明。
作为本发明的一方面，提供一种阵列基板的制作方法，包括：
形成包括像素电极的图形；所述制作方法还包括在形成包括像素电极的图形的步骤之后进行的：
形成包括有源层的图形。
具体地，形成像素电极时首先形成透明导电材料层(如，氧化铟锡)，然后通过构图工艺对所述透明导电材料层进行刻蚀，以形成包括像素电极的图形，即：在透明导电材料层上形成光刻胶层；对光刻胶层进行曝光并显影，以保留对应于像素电极区域的光刻胶，去除其他部分的光刻胶；再对所述透明导电材料层进行刻蚀，将没有光刻胶覆盖的透明导电材料刻蚀掉，最后去掉残留的光刻胶。形成有源层时可以首先形成半导体材料层，然后采用同样的构图工艺对所述半导体材料层进行刻蚀，具体过程这里不再重复。可以理解的是，所述像素电极和有源层的位置关系为：所述像素电极在基板上的投影位于所述有源层在基板上投影的一侧。
形成包括有源层的图形的步骤在形成包括像素电极的图形的步骤之后进行，即，像素电极制作完成后，才开始形成所述半导体材料层。
本发明尤其适用于高级超维场转换技术(Advanced Super Dimension Switch，简称ADS)模式的阵列基板，即在阵列基板上设置像素电极和公共电极，且将像素电极形成在栅绝缘层上，以提高开口率。由于本发明中在阵列基板的制作方法中，形成包括像素电极的图形的步骤在前，形成包括有源层的图形的步骤在后，即像素电极制作完成后才开始形成用于制作有源层的半导体材料层，因此，有源层上不会残留导电物，从而减少漏电流的产生，进而提高阵列基板的质量，改善显示装置的显示效果。
作为本发明的一种具体实施方式，所述制作方法还包括在形成包括像素电极的图形之前进行的：
形成包括栅极1的图形和栅绝缘层2(如图1和图2所示)；所述制作方法还包括在所述形成包括像素电极的图形的步骤和所述形成包括有源层的图形的步骤之间进行的：
形成缓冲绝缘层4(如图4所示)。
具体地，缓冲绝缘层4和栅绝缘层2的材料均可以包括硅的氮化物，其中，缓冲绝缘层4和栅绝缘层2可以采用气相沉积的方法形成，并且，缓冲绝缘层4的沉积速率可以小于栅绝缘层2的沉积速率，以减少缓冲绝缘层4中的缺陷，从而更好地和有源层进行接触，并对像素电极起到保护作用，防止后续形成膜层时的工艺气体对像素电极产生影响。
进一步地，所述制作方法还包括在形成有源层的步骤之后进行的：
在所述缓冲绝缘层的对应于像素电极的位置形成过孔7(如图6所示)；
形成包括源极81、漏极82的图形，并且漏极82通过过孔7与像素电极3相连，如图8所示。
在现有技术中，栅绝缘层和有源层连续进行，即，连续形成栅绝缘层和用于制作有源层的半导体材料层，而在连续形成的过程中会在栅绝缘层上造成异物残留，导致源极、漏极形成后，与形成在栅绝缘层上的像素电极之间容易发生短路。而本发明中，形成像素电极3和形成有源层5之间还形成有缓冲绝缘层4，通过缓冲绝缘层4将像素电极3与源极81、漏极82绝缘间隔开，从而减少了像素电极3与源极81、漏极82之间发生短路的现象。
进一步地，所述制作方法还包括：
在源极81和有源层5之间形成源极欧姆接触层62，在漏极82和有源层5之间形成漏极欧姆接触层63(如图8所示)，从而减小源极81、漏极82与有源层5之间的接触电阻。
具体地，形成源极欧姆接触层62和漏极欧姆接触层63的步骤包括：
形成掺杂半导体材料层6(如图4所示)；
对掺杂半导体材料层6进行初次构图工艺，以形成覆盖整个有源层5的源漏欧姆接触层61(如图5所示)；
对源漏欧姆接触层61进行再次构图工艺，以形成间隔的源极欧姆接触层62和漏极欧姆接触层63(如图8所示)。
优选地，形成源漏欧姆接触层61的步骤和形成包括有源层5的图形的步骤通过同一次构图工艺形成，以简化制作工艺；
形成间隔的源极欧姆接触层62和漏极欧姆接触层63的步骤与形成包括源极81、漏极82的图形的步骤通过同一次构图工艺形成，以简化制作工艺。
所述通过同一次构图工艺形成是指，使用同一张掩膜板进行构图。形成包括有源层5的图形的步骤包括：首先形成半导体材料层，然后对所述半导体材料层进行构图工艺。形成包括源极、漏极的图形的步骤包括：首先形成源漏金属层，然后对所述源漏金属层进行构图工艺。
形成源漏欧姆接触层61的步骤和形成包括有源层5的图形的步骤通过同一次构图工艺进行是指，对所述半导体材料层进行的构图工艺和对掺杂半导体材料层6进行的构图工艺是同一次构图工艺。形成间隔的源极欧姆接触层62和漏极欧姆接触层63的步骤与形成包括源极81、漏极82的图形的步骤通过同一次构图工艺形成是指，对源漏欧姆接触层61进行的构图工艺和对所述源漏金属层进行的构图工艺是同一次构图工艺。
进一步地，所述制作方法还包括在形成包括源极、漏极的图形的步骤之后还包括：
形成钝化层9，如图9所示，钝化层9覆盖源极、漏极和缓冲绝缘层4。钝化层9对有源层5的沟道区域起到保护作用，钝化层9和缓冲绝缘层4相接触的部分可以整体看做为钝化结构。
具体地，在本发明中，通过气相沉积的方法形成钝化层9和缓冲绝缘层4。
现有技术中在制作阵列基板时，会依次形成第一钝化层和位于该第一钝化层上方的第二钝化层，其中第一钝化层和像素电极直接接触，所述第一钝化层和所述第二钝化层形成为钝化结构。第一钝化层和第二钝化层采用化学气相沉积的方法形成，在沉积第一钝化层时，采用高真空低气压的工艺条件，从而导致工艺设备的电极之间容易异常放电，给设备和工艺效果造成隐患。本发明在形成缓冲绝缘层(材料可以与所述第一钝化层的材料相同)时，可以适当增大腔室气压，以减少工艺设备的电极之间的异常放电现象。
更具体地，钝化层9和缓冲绝缘层4的材料均包括硅的氮化物，形成钝化层9时的腔室气压在1400mT～1600mT之间，形成缓冲绝缘层4时的腔室气压在1100mT～1300mT之间。
进一步地，所述制作方法还包括在形成钝化层的步骤之后进行的：
形成包括公共电极的图形，如图10所示，所述公共电极包括多个公共电极条10。
下面结合图1至图10对阵列基板的制作方法进行说明。
S1、在基板上形成栅极金属层，对栅极金属层进行构图工艺，以形成包括栅极1的图形，如图1所示；
S2、如图2所示，在形成栅极1的基板上形成栅绝缘层2；
S3、在栅绝缘层2上形成导电材料层，对栅绝缘层2进行构图工艺，以形成包括像素电极3的图形，如图3所示；
S4、分别形成缓冲绝缘层4、半导体材料层51和掺杂半导体材料层6(如图4所示)，并对半导体材料层51和掺杂半导体材料层6进行构图工艺，形成有源层5和源漏欧姆接触层61(如图5所示)；
S5、在缓冲绝缘层4上对应于像素电极3的位置形成过孔7，如图6所示；
S6、形成源漏金属层8(如图7所示)，并对源漏金属层8进行构图工艺，形成源极81、漏极82，同时将源漏欧姆接触层61的对应于沟道区域的部分刻蚀掉，形成源极欧姆接触层62和漏极欧姆接触层63，如图8所示；
S7、在形成源极81、漏极82的基板上形成钝化层9，如图9所示；
S8、形成包括公共电极的图形，所述公共电极包括多个公共电极条10，如图10所示。
作为本发明的第二个方面，提供一种阵列基板，该阵列基板由本发明提供的上述制作方法制成。具体的，所述阵列基板可以包括薄膜晶体管和像素电极3，如图10所示，像素电极3位于所述薄膜晶体管的有源层5所在层的下方，且与有源层5绝缘间隔，像素电极3与所述薄膜晶体管的漏极82电连接。
进一步地，如图10所示，所述薄膜晶体管的有源层5和像素电极3之间设置有缓冲绝缘层4，有源层5设置在缓冲绝缘层4上。因此，位于有源层5下方层中的像素电极3不会在有源层上形成残留，并且，缓冲绝缘层4可以对像素电极起到一定的保护作用，较少钝化层的沉积过程中较大的气流对像素电极的影响，从而提高阵列基板的良率。
具体地，缓冲绝缘层4的对应于像素电极3的位置设置有过孔，所述薄膜晶体管的漏极82通过所述过孔与像素电极3相连。
进一步地，所述薄膜晶体管的源极82和有源层5之间设置有源极欧姆接触层62，所述薄膜晶体管的漏极82和有源层5之间设置有漏极欧姆接触层63，以减小源极81、漏极82与有源层5之间的接触电阻。
进一步地，如图10所示，所述阵列基板还包括钝化层9和设置在钝化层9上的公共电极，所述公共电极包括多个公共电极条10，钝化层9覆盖所述薄膜晶体管的源极81、漏极82和缓冲绝缘层4。
具体地，缓冲绝缘层4和钝化层9的材料均包括硅的氮化物。
作为本发明的第三个方面，提供一种显示装置，该显示装置包括本发明所提供的上述阵列基板。由于本发明的阵列基板的良率提高，从而使得包括阵列基板的显示装置的良率提高。
可以理解的是，以上实施方式仅仅是为了说明本发明的原理而采用的示例性实施方式，然而本发明并不局限于此。对于本领域内的普通技术人员而言，在不脱离本发明的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本发明的保护范围。

Claims (8)

1.一种阵列基板的制作方法，其特征在于，包括：
形成包括像素电极的图形；
所述制作方法还包括在形成包括像素电极的图形的步骤之后进行的：形成包括有源层的图形；
所述制作方法还包括在形成包括像素电极的图形的步骤之前进行的：
形成包括栅极的图形和栅绝缘层；
所述制作方法还包括在形成包括像素电极的图形的步骤和形成包括有源层的图形的步骤之间进行的：
形成缓冲绝缘层；
其中，所述缓冲绝缘层和所述栅绝缘层均采用气相沉积的方法形成，并且，所述缓冲绝缘层的沉积速率小于所述栅绝缘层的沉积速率，所述缓冲绝缘层和所述栅绝缘层的材料均包括硅的氮化物，形成所述缓冲绝缘层时的腔室气压在1100mT～1300mT之间。
2.根据权利要求1所述的制作方法，其特征在于，所述制作方法还包括在形成有源层的步骤之后进行的：
在所述缓冲绝缘层的对应于像素电极的位置形成过孔；
形成包括源极、漏极的图形，并且所述漏极通过所述过孔与所述像素电极相连。
3.根据权利要求2所述的制作方法，其特征在于，所述制作方法还包括：
在所述源极和所述有源层之间形成源极欧姆接触层，在所述漏极和所述有源层之间形成漏极欧姆接触层。
4.根据权利要求3所述的制作方法，其特征在于，形成源极欧姆接触层和漏极欧姆接触层的步骤包括：
形成掺杂半导体材料层；
对所述掺杂半导体材料层进行初次构图工艺，以形成覆盖整个有源层的源漏欧姆接触层；
对所述源漏欧姆接触层进行再次构图工艺，以形成间隔的源极欧姆接触层和漏极欧姆接触层。
5.根据权利要求4所述的制作方法，其特征在于，形成覆盖整个有源层的源漏欧姆接触层的步骤和形成包括有源层的图形的步骤通过同一次构图工艺形成；
形成间隔的源极欧姆接触层和漏极欧姆接触层的步骤与形成包括源极、漏极的图形的步骤通过同一次构图工艺形成。
6.根据权利要求2所述的制作方法，其特征在于，所述制作方法还包括在形成包括源极、漏极的图形的步骤之后进行的：
形成钝化层。
7.根据权利要求6所述的制作方法，其特征在于，通过气相沉积的方法形成所述钝化层，所述钝化层的材料均包括硅的氮化物，形成所述钝化层时的腔室气压在1400mT～1600mT之间。
8.根据权利要求6所述的制作方法，其特征在于，所述制作方法还包括在形成钝化层的步骤之后进行的：
形成包括公共电极的图形，所述公共电极包括多个公共电极条。
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