WO2020207119A1 - 显示基板及其制作方法、显示装置 - Google Patents

显示基板及其制作方法、显示装置 Download PDF

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WO2020207119A1
WO2020207119A1 PCT/CN2020/075727 CN2020075727W WO2020207119A1 WO 2020207119 A1 WO2020207119 A1 WO 2020207119A1 CN 2020075727 W CN2020075727 W CN 2020075727W WO 2020207119 A1 WO2020207119 A1 WO 2020207119A1
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oxide semiconductor
semiconductor layer
layer
thin film
film transistor
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PCT/CN2020/075727
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English (en)
French (fr)
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张文林
杨维
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京东方科技集团股份有限公司
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Priority to US16/956,983 priority Critical patent/US11283039B2/en
Publication of WO2020207119A1 publication Critical patent/WO2020207119A1/zh

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    • H—ELECTRICITY
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1251—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs comprising TFTs having a different architecture, e.g. top- and bottom gate TFTs
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    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
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    • H10K50/10—OLEDs or polymer light-emitting diodes [PLED]
    • H10K50/14—Carrier transporting layers
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1233—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with different thicknesses of the active layer in different devices
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78633—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a light shield
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H—ELECTRICITY
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    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K2102/00—Constructional details relating to the organic devices covered by this subclass
    • H10K2102/10—Transparent electrodes, e.g. using graphene
    • H10K2102/101—Transparent electrodes, e.g. using graphene comprising transparent conductive oxides [TCO]
    • H10K2102/102—Transparent electrodes, e.g. using graphene comprising transparent conductive oxides [TCO] comprising tin oxides, e.g. fluorine-doped SnO2
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    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K2102/00—Constructional details relating to the organic devices covered by this subclass
    • H10K2102/10—Transparent electrodes, e.g. using graphene
    • H10K2102/101—Transparent electrodes, e.g. using graphene comprising transparent conductive oxides [TCO]
    • H10K2102/103—Transparent electrodes, e.g. using graphene comprising transparent conductive oxides [TCO] comprising indium oxides, e.g. ITO
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    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs

Definitions

  • the present disclosure relates to the field of display technology, in particular to a display substrate, a manufacturing method thereof, and a display device.
  • Display technology is moving towards higher resolution and narrower frame. Realizing the narrow frame of OLED display products is an important direction in the development of OLED display products.
  • an embodiment of the present disclosure provides a display substrate including a display area and a GOA area, wherein the active layer of the thin film transistor in the GOA area includes at least a second oxide semiconductor layer and The first oxide semiconductor layer, the first oxide semiconductor layer is located between the second oxide semiconductor layer and the base substrate of the display substrate, and the mobility of the first oxide semiconductor layer is less than that of the Mobility of the second oxide semiconductor layer.
  • only the first oxide semiconductor layer is used for the active layer of the thin film transistor in the display area.
  • the mobility of the second oxide semiconductor layer is above 30 cm 2 /(V ⁇ S).
  • the second oxide semiconductor layer uses IGZYO or IGTO, where Y is a Sn element.
  • the In content is 6 times the Ga content, and the O content is 10%-35%.
  • the ratio of the content of each element in IGZYO satisfies the following equation:
  • the first oxide semiconductor uses IGZO.
  • the thickness of the first oxide semiconductor is
  • the thin film transistor is a top-gate thin film transistor.
  • the thickness of the second oxide semiconductor is
  • the mobility of the thin film transistor region reaches the GOA 20.5cm 2 / (V ⁇ S) to a range between 30.2cm 2 / (V ⁇ S) .
  • an embodiment of the present disclosure provides a display device including the display substrate as described in the first aspect.
  • the display device is an OLED display device.
  • embodiments of the present disclosure provide a method for manufacturing a display substrate, the display substrate including a display area and a GOA area, wherein the manufacturing method includes:
  • a first oxide semiconductor layer and a second oxide semiconductor layer are sequentially formed in the GOA region, and the second oxide semiconductor layer and the first oxide semiconductor layer are patterned to form an active layer of a thin film transistor.
  • the mobility of the oxide semiconductor layer is less than the mobility of the second oxide semiconductor layer.
  • the manufacturing method further includes:
  • the first oxide semiconductor layer is used to form an active layer of a thin film transistor in the display area.
  • FIG. 1 is a schematic diagram of an embodiment of the disclosure after a light shielding layer is formed
  • FIG. 2 is a schematic diagram of the embodiment of the disclosure after forming a buffer layer
  • FIG. 3 is a schematic diagram after forming a first oxide semiconductor layer according to an embodiment of the disclosure.
  • FIG. 4 is a schematic diagram after forming a second oxide semiconductor layer according to an embodiment of the disclosure.
  • FIG. 5 is a schematic diagram after forming a gate insulating layer and a gate metal layer according to an embodiment of the disclosure
  • FIG. 6 is a schematic diagram after patterns of the gate insulating layer and the gate metal layer are formed in the embodiment of the disclosure.
  • FIG. 7 is a schematic diagram of an embodiment of the disclosure after forming an interlayer insulating layer
  • FIG. 8 is a schematic diagram of an embodiment of the disclosure after forming a source and drain metal layer.
  • FIG. 9 is a schematic diagram of an embodiment of the disclosure after forming a passivation layer.
  • the active layer of the thin film transistor in the GOA area uses double-layer IGZO, by adjusting the bottom IGZO (that is, the IGZO located between the top IGZO and the base substrate)
  • the oxygen content in the GOA region can improve the mobility of thin film transistors in the GOA region.
  • this will affect the stability of the performance of the thin film transistor, and on the other hand, the improvement of the mobility is limited. It can only increase the mobility of the thin film transistor from about 10cm 2 /(V ⁇ S) to 11-12cm 2 / (V ⁇ S).
  • the embodiments of the present disclosure provide a display substrate, a manufacturing method thereof, and a display device, which can realize a narrow frame of a display product.
  • An embodiment of the present disclosure provides a display substrate, which includes a display area and a GOA area.
  • the active layer of a thin film transistor in the GOA area includes at least a second oxide semiconductor layer and a first oxide semiconductor layer that are stacked.
  • the first oxide semiconductor layer is located between the second oxide semiconductor layer and the base substrate of the display substrate, and the mobility of the first oxide semiconductor layer is less than the mobility of the second oxide semiconductor layer .
  • the active layer of the thin film transistor in the GOA region uses the second oxide semiconductor layer and the first oxide semiconductor layer that are stacked, and the mobility of the first oxide semiconductor layer is lower than that of the second oxide semiconductor layer.
  • the second oxide semiconductor layer can be an oxide semiconductor with high mobility, such as IGZYO or IGTO.
  • the thin film transistor may be a top-gate thin film transistor or a bottom-gate thin film transistor.
  • the display substrate includes a display area and a GOA area, the display area is used for display, and the GOA area is located at the periphery of the display area.
  • the active layer of the thin film transistor in the GOA region may include two or more oxide semiconductor layers, or may include only two oxide semiconductor layers.
  • the active layer of the thin film transistor in the GOA region can optionally be composed of two stacked oxide semiconductor layers.
  • the active layer of the thin film transistor in the display area adopts the first oxide semiconductor layer. Since the width of the thin film transistor in the display area does not need to be reduced, the active layer of the thin film transistor in the display area can still use a first oxide semiconductor layer with better stability, such as IGZO.
  • the mobility of the second oxide semiconductor layer is above 30 cm 2 /(V ⁇ S), so that the thin film transistor in the GOA region can have a higher mobility.
  • the second oxide semiconductor layer may be IGZYO or IGTO, where Y is a Sn element.
  • the second oxide semiconductor layer is characterized by a relatively high In content ratio. Generally speaking, the In content is 6 times the Ga content, which can make the mobility of the second oxide semiconductor layer 30 cm 2 /(V ⁇ S ) Above;
  • the content of O in the second oxide semiconductor layer is preferably 10%-35%, for example, it can be 10%, 15%, 20%, 25%, but should be less than 30% %, because the greater the O content, the lower the mobility of the second oxide semiconductor layer.
  • the first oxide semiconductor may be IGZO, which has good stability, and the thickness of the first oxide semiconductor may be Therefore, the mobility of the thin film transistor in the GOA region can be improved, and the stability of the performance of the thin film transistor in the GOA region can be ensured.
  • the active layer of the thin film transistor in the GOA area adopts stacked IGTO and IGZO.
  • the threshold voltage Vth of the thin film transistor in the GOA area can reach 1.28V, and the subthreshold swing
  • the active layer of the thin film transistor in the GOA area uses laminated IGZYO and IGZO.
  • the threshold voltage Vth of the thin film transistor in the GOA area can reach 1.1V
  • the SS can reach 0.31
  • I on 1.1 mA
  • I off 6.3*E -12
  • Ion/Ioff 7.1*E 8
  • saturated mobility calculation it can be obtained that the mobility of the thin film transistor in the GOA region reaches 20.5cm 2 /(V ⁇ S), and compared with the use of double-layer IGZO as the active layer, the leakage current of the thin film transistor is significantly reduced, the on-off current ratio is significantly reduced, and the stability is better.
  • the embodiment of the present disclosure also provides a display device, including the display substrate as described above.
  • the display device may be: liquid crystal display panel, OLED display panel, TV, display, digital photo frame, mobile phone, tablet computer, etc., any product or component with display function, wherein the display device also includes a flexible circuit board, a printed circuit Plate and back plate.
  • the embodiments of the present disclosure also provide a manufacturing method of a display substrate, the display substrate including a display area and a GOA area, and the manufacturing method includes:
  • a first oxide semiconductor layer and a second oxide semiconductor layer are sequentially formed in the GOA region, and the second oxide semiconductor layer and the first oxide semiconductor layer are patterned to form an active layer of a thin film transistor.
  • the mobility of the oxide semiconductor layer is less than the mobility of the second oxide semiconductor layer.
  • the active layer of the thin film transistor in the GOA region uses the second oxide semiconductor layer and the first oxide semiconductor layer that are stacked, and the mobility of the first oxide semiconductor layer is lower than that of the second oxide semiconductor layer.
  • the second oxide semiconductor layer can be an oxide semiconductor with high mobility, such as IGZYO or IGTO.
  • the display substrate includes a display area and a GOA area, the display area is used for display, and the GOA area is located at the periphery of the display area.
  • the active layer of the thin film transistor in the GOA region may include two or more oxide semiconductor layers, or may include only two oxide semiconductor layers.
  • the active layer of the thin film transistor in the GOA region can optionally be composed of two stacked oxide semiconductor layers.
  • the manufacturing method further includes:
  • the first oxide semiconductor layer is used to form an active layer of a thin film transistor in the display area. Since the width of the thin film transistor in the display area does not need to be reduced, the active layer of the thin film transistor in the display area can still use a first oxide semiconductor layer with better stability, such as IGZO.
  • the manufacturing method of the display substrate of this embodiment includes the following steps:
  • Step 1 As shown in Fig. 1, a base substrate 1 is provided, and a light shielding layer 2 is formed on the base substrate 1;
  • the base substrate 1 may be a flexible base substrate or a rigid base substrate, the flexible base substrate may be a polyimide (PI) substrate, and the rigid base substrate may be a glass substrate or a quartz substrate.
  • PI polyimide
  • a metal film can be formed on the base substrate 1 by sputtering or thermal evaporation, and the metal film can be patterned to form the pattern of the light shielding layer 2.
  • the metal film can be Cu, Al, Ag, Mo, Cr , Nd, Ni, Mn, Ti, Ta, W and other metals and alloys of these metals, the metal film can be a single-layer structure or a multilayer structure, such as Cu ⁇ Mo, Ti ⁇ Cu ⁇ Ti, Mo ⁇ Al ⁇ Mo et al.
  • the light shielding layer 2 can shield the active layer of the thin film transistor to prevent external light from irradiating the active layer to affect the performance of the thin film transistor.
  • Step 2 As shown in Figure 2, a buffer layer 3 is formed;
  • the buffer layer 3 can prevent the ions in the glass substrate or the quartz substrate from moving into the thin film transistor and affect the performance of the thin film transistor.
  • the buffer layer can be made of oxides, nitrides, or oxygen-nitrogen compounds, such as SiNx, or SiO 2 or a combination of SiNx and SiO 2 , and the thickness is controlled at
  • Step 3 As shown in FIG. 3, a first oxide semiconductor layer 4 is formed on the buffer layer 3 in the GOA area and the display area;
  • the first oxide semiconductor layer 4 may be indium gallium zinc oxide (IGZO), and the thickness is controlled at The existing deposition power and pressure can be used for IGZO deposition, but the oxygen content of IGZO needs to be controlled between 10%-30% and less than 30% as much as possible, so as not to increase the mobility of the thin film transistor too much. low.
  • IGZO indium gallium zinc oxide
  • a layer of the first oxide semiconductor layer material is deposited on the buffer layer 3, and the first oxide semiconductor layer material is patterned to form the pattern of the first oxide semiconductor layer 4.
  • Step 4 As shown in FIG. 4, a second oxide semiconductor layer 5 is formed in the GOA region;
  • a layer of material of the second oxide semiconductor layer is deposited, and the material of the second oxide semiconductor layer is patterned to form the pattern of the second oxide semiconductor layer 5.
  • the thickness of the second oxide semiconductor layer 5 is controlled to be the same as or similar to the thickness of the first oxide semiconductor layer 4, for example, In the range.
  • the oxygen content needs to be controlled at 10%-35%. For example, IGZYO and IGZO can choose oxygen content of 10%, 15%, 20%, or 25%, and try to be less than 30%. Will not reduce the mobility of the TFT.
  • the second oxide semiconductor layer 5 and the first oxide semiconductor layer 4 are stacked (as in the Y direction shown in FIG. 4) to form the active layer of the thin film transistor in the GOA area.
  • the first The oxide semiconductor layer 4 serves as an active layer of a thin film transistor in the display area.
  • the display area is located on the right side of the GOA area in the X direction.
  • Step 5 As shown in FIG. 5, a gate insulating layer 6 and a gate metal layer 7 are formed;
  • the temperature is controlled to be between 210-290°C, and SiO 2 is selected for the gate insulating layer 6, and the oxygen content of the SiO 2 film should be increased as much as possible to ensure a high-mobility oxide device Characteristic, because oxygen can absorb hydrogen in the active layer, the thickness of the gate insulating layer 6 is between.
  • the gate metal layer 7 may be Cu, Al, Ag, Mo, Cr, Nd, Ni, Mn, Ti, Ta, W and other metals and alloys of these metals.
  • the gate metal layer 7 may be a single-layer structure or a multi-layer structure. Layer structure such as Cu ⁇ Mo, Ti ⁇ Cu ⁇ Ti, Mo ⁇ Al ⁇ Mo, etc., the thickness of the gate metal layer 7 is controlled within
  • Step 6 As shown in FIG. 6, the gate insulating layer 6 and the gate metal layer 7 are patterned to form patterns of the gate insulating layer 6 and the gate metal layer 7.
  • photoresist can be coated on the gate metal layer 7, and after exposure and development of the photoresist, a photoresist retention area and a photoresist removal area are formed.
  • a wet etching process is used to remove the photoresist in the photoresist removal area.
  • the gate metal layer 7 is etched, and then the gate insulating layer 6 in the photoresist removal area is etched by a dry etching process, and then the remaining photoresist is stripped to form patterns of the gate insulating layer 6 and the gate metal layer 7.
  • the orthographic projection of the insulating layer 6 on the base substrate coincides with the orthographic projection of the gate metal layer 7 on the base substrate, wherein the pattern of the gate metal layer 7 includes gates and gate lines.
  • Step 7 As shown in FIG. 7, an interlayer insulating layer 8 is formed;
  • the interlayer insulating layer 8 can be made of oxides, nitrides or oxynitride compounds. Specifically, a combined film layer of SiO 2 , SiON and SiNx can be used, and the thickness is controlled at The interlayer insulating layer 8 is patterned to form a first via 9 exposing the active layer and a second via 10 exposing the light shielding layer.
  • Step 8 As shown in FIG. 8, a source and drain metal layer 11 is formed
  • the source and drain metal layer 11 may be Cu, Al, Ag, Mo, Cr, Nd, Ni, Mn, Ti, Ta, W and other metals and alloys of these metals.
  • the source and drain metal layer 11 may be a single-layer structure or a multilayer structure , Multilayer structure such as Cu ⁇ Mo, Ti ⁇ Cu ⁇ Ti, Mo ⁇ Al ⁇ Mo, etc., the thickness of the source and drain metal layer 11 is controlled within between.
  • the source-drain metal layer 11 is patterned to form a pattern of the source-drain metal layer 11, and the pattern of the source-drain metal layer 11 includes a source electrode, a drain electrode, and a data line.
  • the pattern of the source/drain metal layer 11 is connected to the active layer through the first via hole 9 and is connected to the light shielding layer 3 through the second via hole 10, and the source/drain metal layer can be reduced by connecting the pattern of the light shielding layer 3 and the source/drain metal layer 11 in parallel.
  • Step 9 As shown in FIG. 9, a passivation layer 12 is formed.
  • the passivation layer 12 can be made of oxides, nitrides or oxygen-nitrogen compounds, specifically SiO 2 or SiON, with a thickness of
  • the backplane of the top-gate display substrate can be fabricated.
  • the second oxide semiconductor layer 5 and the first oxide semiconductor layer 4 are stacked The active layer of the thin film transistor constituting the GOA area is provided.
  • the first oxide semiconductor layer 4 serves as an active layer of the thin film transistor in the display area.
  • the second oxide semiconductor layer uses an oxide semiconductor with high mobility, such as IGZYO or IGTO, and the first oxide semiconductor layer uses a stable oxide semiconductor, such as IGZO, so that the mobility of the thin film transistor in the GOA region can be achieved.
  • the improvement can ensure the stability of the performance of the thin film transistor in the GOA area.
  • the width of the thin film transistors in the GOA area can be reduced, thereby making the frame of the display substrate narrower and realizing a narrow frame of the display substrate.

Abstract

一种显示基板及其制作方法、显示装置，属于显示技术领域。其中，显示基板包括显示区域和GOA区域，GOA区域的薄膜晶体管的有源层至少包括层叠设置的第二氧化物半导体层（5）和第一氧化物半导体层（4），第一氧化物半导体层（4）位于第二氧化物半导体层（5）和OLED显示基板的衬底基板（1）之间，第一氧化物半导体层（4）的迁移率小于第二氧化物半导体层（5）的迁移率。

Description

显示基板及其制作方法、显示装置
相关申请的交叉引用
本申请主张在2019年4月11日在中国提交的中国专利申请号No.201910289224.1的优先权，其全部内容通过引用包含于此。
技术领域
本公开涉及显示技术领域，特别是指一种显示基板及其制作方法、显示装置。
背景技术
显示技术正朝着更高分辨率和更窄边框发展，实现OLED显示产品的窄边框，是目前OLED显示产品开发中的重要方向。
发明内容
在第一个方面中，本公开实施例提供了一种显示基板，包括显示区域和GOA区域，其中，所述GOA区域的薄膜晶体管的有源层至少包括层叠设置的第二氧化物半导体层和第一氧化物半导体层，所述第一氧化物半导体层位于所述第二氧化物半导体层和所述显示基板的衬底基板之间，所述第一氧化物半导体层的迁移率小于所述第二氧化物半导体层的迁移率。
根据本公开的一些可行实施例，所述显示区域的薄膜晶体管的有源层仅仅采用所述第一氧化物半导体层。
根据本公开的一些可行实施例，所述第二氧化物半导体层迁移率在30cm 2/(V·S)以上。
根据本公开的一些可行实施例，所述第二氧化物半导体层采用IGZYO或IGTO，其中，Y是Sn元素。
根据本公开的一些可行实施例，所述第二氧化物半导体层中，In含量是Ga含量的6倍，O含量为10％-35％。
根据本公开的一些可行实施例，关于IGZYO中各元素的含量之比满足如 下等式：
In：Ga：Zn：Sn＝6：1：4：1。
根据本公开的一些可行实施例，所述第一氧化物半导体采用IGZO。
根据本公开的一些可行实施例，所述第一氧化物半导体的厚度为
Figure PCTCN2020075727-appb-000001
Figure PCTCN2020075727-appb-000002
根据本公开的一些可行实施例，所述薄膜晶体管为顶栅型薄膜晶体管。
根据本公开的一些可行实施例，所述第二氧化物半导体的厚度为
Figure PCTCN2020075727-appb-000003
Figure PCTCN2020075727-appb-000004
根据本公开的一些可行实施例，所述GOA区域的薄膜晶体管的迁移率达到20.5cm 2/(V■S)至30.2cm 2/(V■S)之间的范围。
在第二个方面中，本公开实施例提供了一种显示装置，包括如第一个方面中所述的显示基板。
根据本公开的一些可行实施例，所述显示装置是OLED显示装置。
在第三个方面中，本公开实施例提供了一种显示基板的制作方法，所述显示基板包括显示区域和GOA区域，其中，所述制作方法包括：
在所述GOA区域依次形成第一氧化物半导体层和第二氧化物半导体层，对所述第二氧化物半导体层和第一氧化物半导体层进行构图形成薄膜晶体管的有源层，所述第一氧化物半导体层的迁移率小于所述第二氧化物半导体层的迁移率。
根据本公开的一些可行实施例，所述制作方法还包括：
在所述显示区域利用所述第一氧化物半导体层形成薄膜晶体管的有源层。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对本公开实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1为本公开实施例形成遮光层后的示意图；
图2为本公开实施例形成缓冲层后的示意图；
图3为本公开实施例形成第一氧化物半导体层后的示意图；
图4为本公开实施例形成第二氧化物半导体层后的示意图；
图5为本公开实施例形成栅绝缘层和栅金属层后的示意图；
图6为本公开实施例形成栅绝缘层和栅金属层的图形后的示意图；
图7为本公开实施例形成层间绝缘层后的示意图；
图8为本公开实施例形成源漏金属层后的示意图；以及
图9为本公开实施例形成钝化层后的示意图。
附图标记列表
1 衬底基板
2 遮光层
3 缓冲层
4 第一氧化物半导体层
5 第二氧化物半导体层
6 栅绝缘层
7 栅金属层
8 钝化层
9 第一过孔
10 第二过孔
11 源漏金属层
12 钝化层
具体实施方式
为使本公开的实施例要解决的技术问题、技术方案和优点更加清楚，下面将结合附图及具体实施例进行详细描述。
相关技术中，为了提升GOA区域的薄膜晶体管(TFT)的迁移率，GOA区域的薄膜晶体管的有源层采用双层IGZO，通过调整底层IGZO(即位于顶层IGZO和衬底基板之间的IGZO)中的氧含量来提升GOA区域的薄膜晶体管的迁移率。但是，这样一方面会影响薄膜晶体管的性能的稳定性，另一方面对迁移率的提升有限，仅能将薄膜晶体管的迁移率从10cm 2/(V·S)左右提 升到11-12cm 2/(V·S)。
为了解决上述问题，本公开的实施例提供一种显示基板及其制作方法、显示装置，能够实现显示产品的窄边框。
本公开的实施例提供一种显示基板，包括显示区域和GOA区域，所述GOA区域的薄膜晶体管的有源层至少包括层叠设置的第二氧化物半导体层和第一氧化物半导体层，所述第一氧化物半导体层位于所述第二氧化物半导体层和所述显示基板的衬底基板之间，所述第一氧化物半导体层的迁移率小于所述第二氧化物半导体层的迁移率。
本实施例中，GOA区域的薄膜晶体管的有源层采用层叠设置的第二氧化物半导体层和第一氧化物半导体层，第一氧化物半导体层的迁移率小于第二氧化物半导体层的迁移率，这样第二氧化物半导体层可以采用迁移率高的氧化物半导体，比如IGZYO或IGTO，在GOA区域的薄膜晶体管的迁移率得到提升后，能够减少GOA区域的薄膜晶体管的宽度，从而将显示基板的边框做到更窄，实现显示基板的窄边框。
本实施例的显示基板中，薄膜晶体管可以为顶栅型薄膜晶体管，也可以为底栅型薄膜晶体管。
本实施例中，显示基板包括显示区域和GOA区域，显示区域用以进行显示，GOA区域位于显示区域的周边。
GOA区域的薄膜晶体管的有源层可以包括两层以上的氧化物半导体层，也可以仅包括两层氧化物半导体层。为了简化薄膜晶体管的有源层的结构，简化薄膜晶体管的制程，进而降低显示基板的制作成本，GOA区域的薄膜晶体管的有源层可选地采用两层氧化物半导体层层叠组成。
进一步地，所述显示区域的薄膜晶体管的有源层采用所述第一氧化物半导体层。由于显示区域不需要缩小薄膜晶体管的宽度，因此，显示区域薄膜晶体管的有源层仍可以采用稳定性较好的第一氧化物半导体层，比如IGZO。
可选地，所述第二氧化物半导体层迁移率在30cm 2/(V·S)以上，这样可以使得GOA区域的薄膜晶体管拥有较高的迁移率。
具体地，所述第二氧化物半导体层可以采用IGZYO或IGTO，其中，Y是Sn元素。所述第二氧化物半导体层中，特点是In含量比例较高，一般而言， In含量是Ga含量的6倍，可以使得第二氧化物半导体层的迁移率在30cm 2/(V·S)以上；另外，为了保证迁移率，所述第二氧化物半导体层中，O含量优选为10％-35％，比如可以为10％，15％，20％，25％，但应尽量小于30％，因为O含量越大，第二氧化物半导体层的迁移率越低。
具体地，所述第一氧化物半导体可以采用IGZO，IGZO具有良好的稳定性，所述第一氧化物半导体的厚度可以为
Figure PCTCN2020075727-appb-000005
从而既可以实现GOA区域的薄膜晶体管的迁移率的提升，又能保证GOA区域的薄膜晶体管性能的稳定性。
一具体示例中，GOA区域的薄膜晶体管的有源层采用层叠设置的IGTO和IGZO，通过对IGTO和IGZO的厚度进行设计，可以使得GOA区域的薄膜晶体管的阈值电压Vth达到1.28V，亚阈值摆幅SS达到0.29，I on＝5.6mA，I off＝2.8*E -12，I on/I off＝2*E 9，采用饱和迁移率计算，可以得到GOA区域的薄膜晶体管的迁移率达到了30.2cm 2/(V■S)，并且相比采用双层IGZO作为有源层，薄膜晶体管的漏电流明显降低，开关态电流比明显降低，稳定性更好。
另一具体示例中，GOA区域的薄膜晶体管的有源层采用层叠设置的IGZYO和IGZO，通过对IGZYO和IGZO的厚度进行设计，可以使得GOA区域的薄膜晶体管的阈值电压Vth达到1.1V，SS达到0.31，I on＝1.1mA，I off＝6.3*E -12，Ion/Ioff＝7.1*E 8，采用饱和迁移率计算，可以得到GOA区域的薄膜晶体管的迁移率达到了20.5cm 2/(V■S)，并且相比采用双层IGZO作为有源层，薄膜晶体管的漏电流明显降低，开关态电流比明显降低，稳定性更好，在70℃的温度下工作一小时，PBTS 4.0V(0.4V-4.4V)，即正向偏压力下Vth偏移4.0V；或者接受5000nit的光照两小时，70℃NBTIS-2.6V(-0.4V--3.0V)，即负向偏压力和光照下Vth偏移-2.6V。
本公开实施例还提供了一种显示装置，包括如上所述的显示基板。所述显示装置可以为：液晶显示面板、OLED显示面板、电视、显示器、数码相框、手机、平板电脑等任何具有显示功能的产品或部件，其中，所述显示装置还包括柔性电路板、印刷电路板和背板。
本公开实施例还提供了一种显示基板的制作方法，所述显示基板包括显示区域和GOA区域，所述制作方法包括：
在所述GOA区域依次形成第一氧化物半导体层和第二氧化物半导体层，对所述第二氧化物半导体层和第一氧化物半导体层进行构图形成薄膜晶体管的有源层，所述第一氧化物半导体层的迁移率小于所述第二氧化物半导体层的迁移率。
本实施例中，GOA区域的薄膜晶体管的有源层采用层叠设置的第二氧化物半导体层和第一氧化物半导体层，第一氧化物半导体层的迁移率小于第二氧化物半导体层的迁移率，这样第二氧化物半导体层可以采用迁移率高的氧化物半导体，比如IGZYO或IGTO，在GOA区域的薄膜晶体管的迁移率得到提升后，能够减少GOA区域的薄膜晶体管的宽度，从而将显示基板的边框做到更窄，实现显示基板的窄边框。
本实施例中，显示基板包括显示区域和GOA区域，显示区域用以进行显示，GOA区域位于显示区域的周边。
GOA区域的薄膜晶体管的有源层可以包括两层以上的氧化物半导体层，也可以仅包括两层氧化物半导体层。为了简化薄膜晶体管的有源层的结构，简化薄膜晶体管的制程，进而降低显示基板的制作成本，GOA区域的薄膜晶体管的有源层可选地采用两层氧化物半导体层层叠组成。
进一步地，所述制作方法还包括：
在所述显示区域利用所述第一氧化物半导体层形成薄膜晶体管的有源层。由于显示区域不需要缩小薄膜晶体管的宽度，因此，显示区域薄膜晶体管的有源层仍可以采用稳定性较好的第一氧化物半导体层，比如IGZO。
下面以薄膜晶体管为顶栅型薄膜晶体管为例，结合附图以及具体的实施例对本公开的技术方案进行进一步介绍，本实施例的显示基板的制作方法包括以下步骤：
步骤1、如图1所示，提供一衬底基板1，在衬底基板1上形成遮光层2；
其中，衬底基板1可以为柔性衬底基板或刚性衬底基板，柔性衬底基板可以为聚酰亚胺(PI)基板，刚性衬底基板可以为玻璃基板或石英基板。
具体地，在衬底基板1上可以采用溅射或热蒸发的方法形成一层金属薄膜，对金属薄膜进行构图，形成遮光层2的图形，金属薄膜可以是Cu，Al，Ag，Mo，Cr，Nd，Ni，Mn，Ti，Ta，W等金属以及这些金属的合金，金属 薄膜可以为单层结构或者多层结构，多层结构比如Cu\Mo,Ti\Cu\Ti，Mo\Al\Mo等。遮光层2能够对薄膜晶体管的有源层进行遮挡，避免外界光照射到有源层上影响薄膜晶体管的性能。
步骤2、如图2所示，形成缓冲层3；
缓冲层3可以避免玻璃基板或石英基板中的离子移动到薄膜晶体管中，影响薄膜晶体管的性能。具体地，缓冲层可以采用氧化物、氮化物或者氧氮化合物，比如SiNx、或SiO 2或SiNx和SiO 2的组合，厚度控制在
Figure PCTCN2020075727-appb-000006
步骤3、如图3所示，在GOA区域和显示区域的缓冲层3上形成第一氧化物半导体层4；
第一氧化物半导体层4可以采用铟镓锌氧化物(IGZO)，厚度控制在
Figure PCTCN2020075727-appb-000007
采用现有的沉积功率和压力进行IGZO的沉积即可，但需要控制IGZO的氧含量，控制在10％-30％之间，尽量小于30％，这样不至于使得薄膜晶体管的迁移率提升的太低。
具体地，在缓冲层3上沉积一层第一氧化物半导体层材料，对第一氧化物半导体层材料进行构图，形成第一氧化物半导体层4的图形。
步骤4、如图4所示，在GOA区域形成第二氧化物半导体层5；
具体地，沉积一层第二氧化物半导体层材料，对第二氧化物半导体层材料进行构图，形成第二氧化物半导体层5的图形。
第二氧化物半导体层5为高迁移率的氧化物半导体，比如IGZYO，IGTO等，其中，Y是Sn元素。要求In：Ga：Zn：Sn＝6：1：4：1，一般而言，In是Ga的六倍左右，可以保证形成的有源层的迁移率在30cm 2/(V·S)以上。另外，如图4所示，第二氧化物半导体层5的厚度控制为与第一氧化物半导体层4的厚度相同或相似，例如控制在
Figure PCTCN2020075727-appb-000008
的范围内。另外，为了保证有源层的迁移率，氧含量需控制在10％-35％，比如IGZYO和IGZO可以选择含氧量为10％，15％，20％，或25％，尽量小于30％，不至于使得TFT的迁移率降低。
在GOA区域，第二氧化物半导体层5和第一氧化物半导体层4层叠设置(如在图4所示的Y方向上)组成GOA区域的薄膜晶体管的有源层，在显示区域，第一氧化物半导体层4作为显示区域的薄膜晶体管的有源层。其中， 如图4所示，所述显示区域在X方向上位于所述GOA区域的右侧。
步骤5、如图5所示，形成栅绝缘层6和栅金属层7；
具体地，在沉积形成栅绝缘层6时，温度控制在210-290℃之间，栅绝缘层6选择SiO 2，应尽可能提高SiO 2膜层的氧含量，确保高迁移率氧化物的器件特性，因为氧可以吸收有源层中的氢，栅绝缘层6的厚度在
Figure PCTCN2020075727-appb-000009
之间。
栅金属层7可以是Cu，Al，Ag，Mo，Cr，Nd，Ni，Mn，Ti，Ta，W等金属以及这些金属的合金，栅金属层7可以为单层结构或者多层结构，多层结构比如Cu\Mo,Ti\Cu\Ti，Mo\Al\Mo等，栅金属层7的厚度控制在
Figure PCTCN2020075727-appb-000010
步骤6、如图6所示，对栅绝缘层6和栅金属层7进行构图，形成栅绝缘层6和栅金属层7的图形。
具体地，可以在栅金属层7上涂覆光刻胶，对光刻胶进行曝光显影后，形成光刻胶保留区域和光刻胶去除区域，首先利用湿刻工艺对光刻胶去除区域的栅金属层7进行刻蚀，然后利用干刻工艺对光刻胶去除区域的栅绝缘层6进行刻蚀，之后剥离剩余的光刻胶，形成栅绝缘层6和栅金属层7的图形，栅绝缘层6在衬底基板上的正投影与栅金属层7在衬底基板上的正投影重合，其中，栅金属层7的图形包括栅极和栅线。
步骤7、如图7所示，形成层间绝缘层8；
层间绝缘层8可以采用氧化物、氮化物或者氧氮化合物，具体可以采用SiO 2、SiON和SiNx的组合膜层，厚度控制在
Figure PCTCN2020075727-appb-000011
对层间绝缘层8进行构图，形成暴露出有源层的第一过孔9和暴露出遮光层的第二过孔10。
步骤8、如图8所示，形成源漏金属层11；
源漏金属层11可以是Cu，Al，Ag，Mo，Cr，Nd，Ni，Mn，Ti，Ta，W等金属以及这些金属的合金，源漏金属层11可以为单层结构或者多层结构，多层结构比如Cu\Mo,Ti\Cu\Ti，Mo\Al\Mo等，源漏金属层11的厚度控制在
Figure PCTCN2020075727-appb-000012
之间。对源漏金属层11进行构图，形成源漏金属层11的图形，源漏金属层11的图形包括源电极、漏电极和数据线。
源漏金属层11的图形通过第一过孔9与有源层连接，通过第二过孔10 与遮光层3连接，通过遮光层3与源漏金属层11的图形并联可以降低源漏金属层11的图形的电阻。
步骤9、如图9所示，形成钝化层12。
钝化层12可以采用氧化物、氮化物或者氧氮化合物，具体可以采用SiO 2或SiON，厚度在
Figure PCTCN2020075727-appb-000013
经过上述步骤1-9即可完成顶栅型显示基板的背板制作，如图9的左侧B区域所示，在GOA区域，第二氧化物半导体层5和第一氧化物半导体层4层叠设置组成GOA区域的薄膜晶体管的有源层。另外，如图9的右侧A区域所示，在显示区域，第一氧化物半导体层4作为显示区域的薄膜晶体管的有源层。第二氧化物半导体层采用迁移率高的氧化物半导体，比如IGZYO或IGTO，第一氧化物半导体层采用稳定性好的氧化物半导体，比如IGZO，从而既可以实现GOA区域的薄膜晶体管的迁移率的提升，又能保证GOA区域的薄膜晶体管性能的稳定性。另外，在GOA区域的薄膜晶体管的迁移率得到提升后，能够减少GOA区域的薄膜晶体管的宽度，从而将显示基板的边框做到更窄，实现显示基板的窄边框。
在本公开各方法实施例中，所述各步骤的序号并不能用于限定各步骤的先后顺序，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，对各步骤的先后变化也在本公开的保护范围之内。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”，或者可以存在中间 元件。
以上所述是本公开的一些实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本公开所述原理的前提下，还可以作出若干改进和润饰，这些改进和润饰也应视为本公开的保护范围。

Claims (15)

  1. 一种显示基板，包括显示区域和GOA区域，其中，所述GOA区域的薄膜晶体管的有源层至少包括层叠设置的第二氧化物半导体层和第一氧化物半导体层，所述第一氧化物半导体层位于所述第二氧化物半导体层和所述显示基板的衬底基板之间，所述第一氧化物半导体层的迁移率小于所述第二氧化物半导体层的迁移率。
  2. 根据权利要求1所述的显示基板，其中，所述显示区域的薄膜晶体管的有源层仅仅采用所述第一氧化物半导体层。
  3. 根据权利要求1或2所述的显示基板，其中，所述第二氧化物半导体层迁移率在30cm 2/(V·S)以上。
  4. 根据权利要求1至3中任一项所述的显示基板，其中，所述第二氧化物半导体层采用IGZYO或IGTO，其中，Y是Sn元素。
  5. 根据权利要求4所述的显示基板，其中，所述第二氧化物半导体层中，In含量是Ga含量的6倍，O含量为10％-35％。
  6. 根据权利要求5所述的显示基板，其中，关于IGZYO中各元素的含量之比满足如下等式：
    In：Ga：Zn：Sn＝6：1：4：1。
  7. 根据权利要求1至6中任一项所述的显示基板，其中，所述第一氧化物半导体采用IGZO。
  8. 根据权利要求1至7中任一项所述的显示基板，其中，所述第一氧化物半导体的厚度为
    Figure PCTCN2020075727-appb-100001
  9. 根据权利要求1至8中任一项所述的显示基板，其中，所述薄膜晶体管为顶栅型薄膜晶体管。
  10. 根据权利要求1至9中任一项所述的显示基板，其中，所述第二氧化物半导体的厚度为
    Figure PCTCN2020075727-appb-100002
  11. 根据权利要求1至10中任一项所述的显示基板，其中，所述GOA区域的薄膜晶体管的迁移率达到20.5cm 2/(V·S)至30.2cm 2/(V·S)之间的范围。
  12. 一种显示装置，包括如权利要求1至11中任一项所述的显示基板。
  13. 根据权利要求12所述的显示装置，其中，所述显示装置是OLED显示装置。
  14. 一种显示基板的制作方法，所述显示基板包括显示区域和GOA区域，其中，所述制作方法包括：
    在所述GOA区域依次形成第一氧化物半导体层和第二氧化物半导体层，对所述第二氧化物半导体层和第一氧化物半导体层进行构图形成薄膜晶体管的有源层，所述第一氧化物半导体层的迁移率小于所述第二氧化物半导体层的迁移率。
  15. 根据权利要求14所述的显示基板的制作方法，其中，所述制作方法还包括：
    在所述显示区域利用所述第一氧化物半导体层形成薄膜晶体管的有源层。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2022125249A1 (en) * 2020-12-07 2022-06-16 Apple Inc. Display circuitry with semiconducting oxide transistors

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110010626B (zh) 2019-04-11 2022-04-29 京东方科技集团股份有限公司 显示基板及其制作方法、显示装置
CN112002733B (zh) 2020-08-06 2023-12-01 武汉华星光电半导体显示技术有限公司 Oled显示装置及制备方法
CN113889040A (zh) * 2021-11-22 2022-01-04 京东方科技集团股份有限公司 一种栅极驱动电路和显示装置
WO2023092562A1 (zh) * 2021-11-29 2023-06-01 京东方科技集团股份有限公司 金属氧化物薄膜晶体管、阵列基板及其制备方法
WO2023230843A1 (zh) * 2022-05-31 2023-12-07 京东方科技集团股份有限公司 驱动背板及其制作方法、显示面板

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201533912A (zh) * 2014-02-07 2015-09-01 Semiconductor Energy Lab 半導體裝置
CN106057826A (zh) * 2016-08-08 2016-10-26 京东方科技集团股份有限公司 一种阵列基板及其制备方法、显示装置
US10002970B2 (en) * 2015-04-30 2018-06-19 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device, manufacturing method of the same, or display device including the same
CN110010626A (zh) * 2019-04-11 2019-07-12 京东方科技集团股份有限公司 显示基板及其制作方法、显示装置

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102160102B (zh) * 2008-09-19 2013-11-06 株式会社半导体能源研究所 显示装置
KR101034686B1 (ko) * 2009-01-12 2011-05-16 삼성모바일디스플레이주식회사 유기전계발광 표시 장치 및 그의 제조 방법
JP6002088B2 (ja) 2012-06-06 2016-10-05 株式会社神戸製鋼所 薄膜トランジスタ
CN104584229B (zh) * 2012-08-10 2018-05-15 株式会社半导体能源研究所 半导体装置及其制造方法
KR102211596B1 (ko) * 2012-12-28 2021-02-03 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치
CN103412450A (zh) * 2013-07-26 2013-11-27 京东方科技集团股份有限公司 阵列基板及其制作方法和显示装置
US9640556B2 (en) * 2014-01-15 2017-05-02 Kobe Steel, Ltd. Thin film transistor
JPWO2016056204A1 (ja) * 2014-10-10 2017-07-13 株式会社Ｊｏｌｅｄ 薄膜トランジスタ基板、薄膜トランジスタ基板の製造方法、及び、表示パネル
CN114185216A (zh) * 2015-02-12 2022-03-15 株式会社半导体能源研究所 显示装置
CN104898342A (zh) * 2015-06-16 2015-09-09 京东方科技集团股份有限公司 阵列基板母板及其制作方法
CN105742240B (zh) * 2016-04-05 2019-09-13 武汉华星光电技术有限公司 一种ltps阵列基板的制造方法
WO2018168639A1 (ja) * 2017-03-14 2018-09-20 シャープ株式会社 半導体装置およびその製造方法
US10866475B2 (en) * 2017-03-17 2020-12-15 Sharp Kabushiki Kaisha Active matrix substrate and display device
CN114975635A (zh) * 2017-05-31 2022-08-30 乐金显示有限公司 薄膜晶体管、包括其的栅极驱动器、以及包括该栅极驱动器的显示装置
CN107863354A (zh) * 2017-10-20 2018-03-30 武汉华星光电技术有限公司 阵列基板及其制作方法
JP2019114751A (ja) * 2017-12-26 2019-07-11 シャープ株式会社 薄膜トランジスタ基板及びそれを備えた液晶表示装置並びに薄膜トランジスタ基板の製造方法
KR20200076343A (ko) * 2018-12-19 2020-06-29 엘지디스플레이 주식회사 박막 트랜지스터 및 이를 포함하는 표시장치
US10923548B2 (en) * 2019-02-25 2021-02-16 Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd. Display panel and method for manufacturing same
US20200287054A1 (en) * 2019-03-08 2020-09-10 Sharp Kabushiki Kaisha Semiconductor device and method for producing the same
KR20210051551A (ko) * 2019-10-30 2021-05-10 엘지디스플레이 주식회사 박막 트랜지스터, 그를 포함한 게이트 구동부, 및 그를 포함한 표시장치

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201533912A (zh) * 2014-02-07 2015-09-01 Semiconductor Energy Lab 半導體裝置
US10002970B2 (en) * 2015-04-30 2018-06-19 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device, manufacturing method of the same, or display device including the same
CN106057826A (zh) * 2016-08-08 2016-10-26 京东方科技集团股份有限公司 一种阵列基板及其制备方法、显示装置
CN110010626A (zh) * 2019-04-11 2019-07-12 京东方科技集团股份有限公司 显示基板及其制作方法、显示装置

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2022125249A1 (en) * 2020-12-07 2022-06-16 Apple Inc. Display circuitry with semiconducting oxide transistors

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