WO2017049862A1 - Tft及其制作方法、阵列基板及显示装置 - Google Patents

Tft及其制作方法、阵列基板及显示装置 Download PDF

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WO2017049862A1
WO2017049862A1 PCT/CN2016/074429 CN2016074429W WO2017049862A1 WO 2017049862 A1 WO2017049862 A1 WO 2017049862A1 CN 2016074429 W CN2016074429 W CN 2016074429W WO 2017049862 A1 WO2017049862 A1 WO 2017049862A1
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active layer
layer
tft
drain
source
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PCT/CN2016/074429
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English (en)
French (fr)
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朴求铉
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京东方科技集团股份有限公司
合肥京东方光电科技有限公司
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Priority to US15/317,251 priority Critical patent/US10115832B2/en
Publication of WO2017049862A1 publication Critical patent/WO2017049862A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/26—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, elements provided for in two or more of the groups H01L29/16, H01L29/18, H01L29/20, H01L29/22, H01L29/24, e.g. alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to a TFT, a method for fabricating the same, an array substrate, and a display device.
  • TFT-LCD Thin Film Transistor-Liquid Crystal Display
  • the performance of the TFT determines the display quality of the display.
  • the active layer of the TFT in the prior art can be composed of amorphous silicon and an oxide semiconductor material. Compared with amorphous silicon, the oxide semiconductor material can pass visible light, thereby increasing the pixel aperture ratio and being less expensive.
  • the oxide semiconductor material when the oxide semiconductor material is exposed to an external environment (for example, a moisture or an oxygen atmosphere), its characteristics are deteriorated, so that the mobility is lowered, thereby affecting the performance of the TFT.
  • an external environment for example, a moisture or an oxygen atmosphere
  • Embodiments of the present disclosure provide a TFT, a method of fabricating the same, an array substrate, and a display device capable of avoiding deterioration of TFT performance due to exposure of an oxide semiconductor material to an external environment.
  • a thin film transistor TFT including an active layer including a first active layer and a second active layer. a material constituting the second active layer The material is an oxide semiconductor material, and the conductivity of the first active layer is greater than the conductivity of the second active layer.
  • the active layer includes a layer of the first active layer and a layer of the second active layer.
  • the thin film transistor further includes a source and a drain.
  • the first active layer is adjacent to the source and the drain with respect to the second active layer.
  • the thin film transistor further includes a source and a drain.
  • the second active layer is adjacent to the source and the drain with respect to the first active layer, and an etch barrier layer is formed on a surface of the second active layer.
  • the thin film transistor further includes a source and a drain.
  • the active layer includes a layer of the first active layer and two layers of the second active layer.
  • the first active layer is located between the two second active layers, and an etch barrier layer is formed on a surface of the second active layer adjacent to the source and the drain.
  • the position of the first active layer corresponds to a position of a TFT channel.
  • the material constituting the first active layer includes at least one of indium tin oxide, indium zinc oxide, tin dioxide, indium trioxide, zinc oxide, and carbon nanotubes.
  • the material constituting the second active layer includes at least one of indium gallium zinc oxide, cadmium oxide, and aluminum oxide.
  • the first active layer has a thickness of 100 angstroms to 4000 angstroms.
  • a method of fabricating a TFT comprising forming an active layer on a base substrate.
  • the step of forming an active layer on the base substrate includes forming a first active layer and a second active layer on the base substrate.
  • the material constituting the second active layer is an oxide semiconductor material, and the conductivity of the first active layer is greater than the conductivity of the second active layer.
  • the step of forming the first active layer and the second active layer on the base substrate comprises: forming a layer of the first active layer and a layer on the base substrate The second active layer is described.
  • the manufacturing method of the TFT further includes forming a source and a drain on the base substrate.
  • the first active layer is adjacent to the source and the drain with respect to the second active layer.
  • the manufacturing method of the TFT further includes forming a source and a drain on the base substrate.
  • the second active layer is adjacent to the source and the drain with respect to the first active layer.
  • the step of forming a source and a drain on the base substrate includes: on a surface of the second active layer An etch stop layer is formed.
  • the manufacturing method of the TFT further includes forming a source and a drain on the base substrate.
  • the step of forming a first active layer and a second active layer on the base substrate includes: forming a layer of the first active layer and two layers of the second layer on the base substrate Source layer.
  • the first active layer is located between the two second active layers.
  • An etch stop layer is formed on a surface of the second active layer adjacent to the source and the drain.
  • the material constituting the first active layer includes at least one of indium tin oxide, indium zinc oxide, tin dioxide, indium trioxide, zinc oxide, and carbon nanotubes.
  • the material constituting the second active layer includes at least one of indium gallium zinc oxide, cadmium oxide, and aluminum oxide.
  • an array substrate including any of the TFTs described above.
  • a display device including the above array substrate.
  • Embodiments of the present disclosure provide a TFT, a method of fabricating the same, an array substrate, and a display device.
  • the TFT includes an active layer.
  • the active layer includes a first active layer and a second active layer.
  • the material constituting the second active layer is an oxide semiconductor material, and the conductivity of the first active layer is greater than the conductivity of the second active layer.
  • the second active layer composed of the oxide semiconductor material is affected by external environmental factors, the mobility thereof is lowered, and the first active layer having a large conductivity increases the electron transfer rate, thereby The mobility of the entire active layer is compensated. Therefore, the performance of the TFT is prevented from being affected.
  • FIG. 1a is a schematic structural diagram of a bottom gate TFT according to an embodiment of the present disclosure
  • FIG. 1b is a schematic structural diagram of a top gate TFT according to an embodiment of the present disclosure
  • FIG. 2a is a schematic structural view of the TFT shown in FIG. 1a when the active layer includes a first active layer and a second active layer;
  • FIG. 2b is another schematic structural view of the TFT shown in FIG. 1a when the active layer includes a first active layer and a second active layer;
  • FIG. 3 is a schematic structural view showing an active layer including a first active layer and two second active layers in the TFT shown in FIG. 1a;
  • 4a to 4c are schematic structural views corresponding to respective steps in the fabrication process of the TFT shown in FIG. 2a;
  • FIG. 5 is a schematic structural view of an array substrate using the TFT shown in FIG.
  • Embodiments of the present disclosure provide a TFT including an active layer.
  • the active layer includes a first active layer and a second active layer.
  • the material constituting the second active layer is an oxide semiconductor material, and the conductivity of the first active layer is greater than the conductivity of the second active layer.
  • a TFT provided by an embodiment of the present disclosure includes an active layer.
  • the active layer includes a first active layer and a second active layer.
  • the material constituting the second active layer is an oxide semiconductor material, and the conductivity of the first active layer is greater than the conductivity of the second active layer.
  • the present disclosure does not limit the type of TFT.
  • the TFT may be a bottom gate type TFT as shown in FIG. 1a.
  • the gate electrode 10 is closer to the base substrate 01 with respect to the gate insulating layer 11.
  • An active layer 12 is formed on the surface of the gate insulating layer 11, and a source electrode 13 and a drain electrode 14 are formed on the surface of the active layer.
  • the gate electrode 10 is further away from the base substrate 01 with respect to the gate insulating layer 11. Further, the active layer 12 is formed on the surface of the base substrate 01. The surface of the active layer forms a source electrode 13 and a drain electrode 14.
  • the oxide semiconductor material constituting the second active layer in the embodiment of the present disclosure may include any of cadmium oxide (CdO), aluminum oxide (Al 2 O 3 ), and indium gallium zinc oxide (IGZO).
  • CdO cadmium oxide
  • Al 2 O 3 aluminum oxide
  • IGZO indium gallium zinc oxide
  • the present disclosure does not limit the number of the first active layer 121 and the second active layer 122 (shown in FIG. 2a, FIG. 2b, or FIG. 3) included in the active layer 12.
  • a first active layer 121 and a second active layer 122 may be included as shown in FIG. 2a.
  • a first active layer 121 and two second active layers 122, 122' are included.
  • the structure in which the active layer 12 of the TFT has a different number of the first active layer 121 and the second active layer 122 will be exemplified in detail by way of a specific embodiment.
  • the active layer 12 provided in this embodiment includes a first active layer 121 and a second active layer 122. As shown in FIG. 2a, the first active layer 121 is closer to the source 13 and the drain 14 with respect to the second active layer 122.
  • the first active layer 121 is closer to the source 13 and the drain 14 with respect to the second active layer 122.
  • the second active layer 122 whose mobility is easily affected by the external environment can be protected. It is avoided that moisture or oxygen or the like in the external environment is directly in contact with the second active layer 122 during the process of fabricating the source 13 and the drain 14, thereby reducing the mobility of the second active layer 122.
  • the oxygen atom and other metal atoms are at The state of weak union.
  • the materials constituting the first active layer 121 are indium tin oxide (InSnO), indium zinc oxide (InZnO), tin dioxide (SnO 2 ), indium trioxide (In 2 O 3 ), and zinc oxide (ZnO).
  • carbon nanotubes (English name: Carbon Nano Tube, CNT for short), since the material constituting the first active layer 121 can induce oxygen atoms in the second active layer 122 Other atoms in the source layer 12, such as metal atom indium In, tin Sn, etc., are strongly bonded. Thereby, the number of defects in the active layer 12 can be reduced, so that the ability of the defect to capture electrons is lowered, so that the moving speed of the electrons can be increased, thereby making the mobility of the active layer 12 effectively improved.
  • CNT Carbon Nano Tube
  • the pattern of the first active layer 121 and the second active layer 122 described above may be formed by a one-time mask exposure process. Specifically, a surface composed of at least one of cadmium oxide (CdO), aluminum oxide (Al 2 O 3 ), and indium gallium zinc oxide (IGZO) may be coated on the surface of the gate insulating layer 11.
  • CdO cadmium oxide
  • Al 2 O 3 aluminum oxide
  • IGZO indium gallium zinc oxide
  • a thin film layer composed of at least one of zinc (ZnO) and carbon nanotubes.
  • a photoresist is coated on the surface of the first thin film layer, and then a pattern of the first active layer 121 and the second active layer 122 is formed at a time by a mask exposing process.
  • the active layer 12 provided in this embodiment includes a first active layer 121 and a second active layer 122. Different from the first embodiment, as shown in FIG. 2b, the second active layer 122 is closer to the source 13 and the drain 14 with respect to the first active layer 121.
  • etch stop layer 15 may be disposed on the surface of the second active layer 122 to protect the second active layer 122 from the original mobility. Further, since the first active layer 121 located under the second active layer 122 has a higher mobility, the mobility of the entire active layer 12 can be further improved.
  • the material constituting the first active layer 121 is the same as that of the first embodiment, and may be indium tin oxide (InSnO), indium zinc oxide (InZnO), tin dioxide (SnO 2 ), or indium trioxide (In 2 O). 3 ) at least one of zinc oxide (ZnO) and carbon nanotubes. The same as the beneficial effects of the first embodiment, and details are not described herein again.
  • the first active layer 121 and the second active layer 122 having the same pattern can be prepared by one mask exposure process.
  • the surface of the second active layer 122 in the second embodiment is provided with the etch barrier layer 15, so that the influence of external factors on the mobility of the second active layer 122 can be reduced. . Therefore, the mobility of the active layer 12 is higher in the solution provided in the second embodiment.
  • the second active layer 122 is in contact with the source 13 and the drain 14 , and since the conductivity of the second active layer 122 is lower than that of the first active layer 121 , Therefore, the leakage current of the TFT provided in the second embodiment is smaller than the leakage current of the TFT provided in the first embodiment. Therefore, the TFT provided in the second embodiment has a higher mobility and a smaller leakage current, so that the performance is better.
  • the etch barrier layer 15 is provided, an increase in the process of preparing the TFT is required.
  • the step of etching the barrier layer 15 is such that the fabrication process is more complicated than in the first embodiment.
  • the active layer 12, as shown in FIG. 3, may include a first active layer 121 and two second active layers 122, 122'.
  • the first active layer 121 is located between the two second active layers 122 and 122', and the surface of the second active layer 122' adjacent to the source 13 and the drain 14 is formed with an etch stop layer 15. In this way, the second active layer 122' in contact with the source 13 and the drain 14 can be protected by the etch barrier layer 15 to avoid the outside of the process of fabricating the source 13 and the drain 14.
  • the environment reduces the performance of the second active layer 122' to enable it to maintain the original mobility. Further, since the first active layer 121 located between the two second active layers 122, 122' has a higher mobility, the mobility of the entire active layer 12 can be further improved.
  • the present implementation in contact with the source 13 and the drain 14 is the second active layer 122 ′, since the conductivity of the second active layer 122 ′ is lower than that of the first active layer 121 , the present implementation In the example, the leakage current of the TFT is small. Therefore, in the TFT provided in the third embodiment, the TFT has a higher mobility and a smaller leakage current than the TFT provided in the first embodiment, so that the performance is better.
  • the etch barrier layer 15 is provided, the step of fabricating the etch barrier layer 15 is required in the process of fabricating the TFT, and thus the fabrication process is more complicated than the first embodiment.
  • the pattern of the first active layer 121 located between the two second active layers 122, 122' may be consistent with the two second active layers 122, 122', so that The pattern of the two second active layers 122, 122' and the first active layer 121 may be formed by one mask exposure process.
  • the first active layer 121 may be formed at a position corresponding to the channel of the TFT.
  • the first active layer 121 located at the position of the TFT channel can increase the moving speed of electrons at the position of the TFT channel when the TFT is turned on, so that the TFT has a higher mobility.
  • the material for fabricating the first active layer 121 can be saved while increasing the mobility of the TFT.
  • the material constituting the first active layer 121 is the same as that of the first embodiment, and may be indium tin oxide (InSnO), indium zinc oxide (InZnO), tin dioxide (SnO 2 ), or indium trioxide (In 2 ). At least one of O 3 ), zinc oxide (ZnO), and carbon nanotubes. The same as the beneficial effects of the first embodiment, and details are not described herein again.
  • the first active layer 121 may have a thickness of 100 angstroms to 4000 angstroms.
  • the thickness of the first active layer 121 is less than 100 angstroms, the material constituting the first active layer 121 induces oxygen atoms in the second active layer 122 and other atoms in the active layer 12 because the thickness is too small. The ability to combine strongly is also weak, thereby impairing the effect of compensating or enhancing the mobility of the entire active layer 12.
  • the thickness is more than 4000 angstroms, although the mobility of the active layer 12 can be effectively compensated or improved.
  • the thickness of the second active layer 122 is thick, when the above TFT is applied to a display device, it is disadvantageous for the design of the ultrathin display device.
  • the embodiment of the present disclosure further provides a method for fabricating a TFT, including: forming an active layer 12 on a substrate substrate 01, wherein the method of specifically forming the active layer 12 may include:
  • a first active layer 121 and a second active layer 122 are formed on the base substrate 01.
  • the material constituting the second active layer 12 is an oxide semiconductor material, and the conductivity of the first active layer 121 is greater than the conductivity of the second active layer 122.
  • the oxide semiconductor material constituting the second active layer may include any one of cadmium oxide (CdO), aluminum oxide (Al 2 O 3 ), and indium gallium zinc oxide (IGZO).
  • Materials constituting the first active layer 121 include indium tin oxide (InSnO), indium zinc oxide (InZnO), tin dioxide (SnO 2 ), indium trioxide (In 2 O 3 ), zinc oxide (ZnO), and carbon. At least one of the nanotubes. The same as the beneficial effects of the first embodiment, and details are not described herein again.
  • the patterning process may be referred to as including a photolithography process, or may include a photolithography process and an etching step, and may also include other processes for forming a predetermined pattern, such as printing, inkjet, and the like.
  • the photolithography process refers to a process of forming a pattern by using a photoresist, a mask, an exposure machine, or the like including a process of film formation, exposure, development, and the like.
  • the corresponding patterning process can be selected in accordance with the structure formed in the present disclosure.
  • the one-time patterning process in the embodiment of the present disclosure is to pass a mask exposure work
  • the art forms different exposure areas, and then multiple etching, ashing, and the like removal processes are performed on different exposure areas, and finally the expected pattern is taken as an example.
  • the present disclosure does not limit the number of the first active layer 121 and the second active layer 122 (shown in FIG. 2a, FIG. 2b or FIG. 3) included in the active layer 12, and by way of specific embodiments, When the active layer 12 of the TFT has a different number of the first active layer 121 and the second active layer 122, the fabrication process of the TFT is exemplified in detail.
  • the active layer 12 in this embodiment includes a first active layer 121 and a second active layer 122.
  • a gate metal layer is formed on the base substrate 01, and then a photoresist layer is coated on the surface of the gate metal layer, and then exposed through a mask.
  • the process forms a pattern of gates 10.
  • a gate insulating layer 11 is formed on the base substrate 01. Specifically, as shown in FIG. 4b, a gate insulating layer 11 is coated on the surface of the gate 10.
  • a layer of the first active layer 121 and a second active layer 122 are formed on the base substrate 01.
  • a second film made of at least one of cadmium oxide (CdO), aluminum oxide (Al 2 O 3 ), and indium gallium zinc oxide (IGZO) may be coated on the surface of the gate insulating layer 11.
  • a photoresist is coated on the surface of the first thin film layer, and then a pattern of the first active layer 121 and the second active layer 122 is formed at a time by a mask exposing process.
  • a surface of the first active layer 121 is coated with a source/drain metal layer, and then a photoresist layer is formed on the surface of the source/drain metal layer.
  • a pattern of the source 13 and the drain 14 as shown in FIG. 2a may be formed by a mask exposure process, and the first active layer 121 is closer to the source 13 and the second active layer 122. Drain 14.
  • the first active layer 121 is located on the surface of the second active layer 122, the second active layer 122 whose mobility is easily affected by the external environment can be protected. It is avoided that moisture or oxygen or the like in the external environment directly contacts the second active layer 122 during the process of fabricating the source 13 and the drain 14, resulting in lowering the mobility of the second active layer 122.
  • a layer of the first active layer 121 and a second active layer are formed on the base substrate 01.
  • the method of 122 may further include forming the first thin film layer on the surface of the gate insulating layer 11, forming the second thin film layer, and then forming the second active layer 122 and the first active layer at a time by a mask exposing process. 121 pattern.
  • a pattern of the etch barrier layer 15 may be formed on the surface of the second active layer 122 by one patterning process. In this way, the second active layer in contact with the source 13 and the drain 14 can be protected by the etch stop layer 15 to prevent the external environment from being lowered during the process of fabricating the source 13 and the drain 14.
  • the performance of the second active layer 122 enables it to maintain the original mobility.
  • a surface of the substrate on which the etch barrier layer 15 is formed is coated with a source/drain metal layer, and then a photoresist layer is formed on the surface of the source/drain metal layer, and then formed by a mask exposure process as shown in FIG. 2b.
  • the pattern of the source 13 and the drain 14 is closer to the source 13 and the drain 14 with respect to the first active layer 121.
  • the etch stop layer 15 is disposed on the surface of the second active layer 122, and the second active layer 122 can be protected to maintain the original mobility.
  • the first active layer 121 under the second active layer 122 has a higher mobility, the mobility of the entire active layer 12 can be further improved.
  • the active layer 12 in this embodiment may include a first active layer 121 and two second active layers 122, 122'.
  • the gate electrode 10 and the gate insulating layer 11 are sequentially formed on the surface of the base substrate 01 by a patterning process.
  • a first active layer 121 and two second active layers 122, 122' are then formed on the surface of the gate insulating layer 11.
  • the first active layer 121 is located between the two second active layers 122, 122'.
  • a surface of the gate insulating layer 11 is coated with a second thin film layer composed of at least one of cadmium oxide (CdO), aluminum oxide (Al 2 O 3 ), and indium gallium zinc oxide (IGZO).
  • IGZO indium gallium zinc oxide
  • the second thin film layer with indium tin oxide (InSnO), indium zinc oxide (InZnO), tin dioxide (SnO 2 ), indium trioxide (In 2 O 3 ), zinc oxide (ZnO), and A first film layer composed of at least one of carbon nanotubes.
  • the second thin film layer is coated again on the first thin film layer, and then a patterned first active layer 121 and two second active layers 122, 122' are formed by one patterning process. .
  • a method of forming a first active layer 121 and two second active layers 122, 122' on the surface of the gate insulating layer 11 may be to form the second thin film layer on the surface of the gate insulating layer 11. , Then, the pattern of the second active layer 122 is formed by one patterning process, and then the first thin film layer is coated on the surface of the second active layer 122, and then formed at the position corresponding to the TFT channel by one patterning process. The pattern of the source layer 121. Next, the second thin film layer is coated on the surface of the substrate on which the first active layer 121 and the second active layer 122 are formed, and the pattern of the second active layer 122' is formed by one patterning process.
  • the first active layer 121 is described above, so that the material for fabricating the first active layer 121 can be saved while increasing the mobility of the TFT.
  • a pattern of the etch barrier layer 15 is formed by a patterning process to protect the second active layer 122' of the uppermost layer (near the source 13 and the drain 14) To avoid the impact of the external environment on its mobility.
  • a pattern of the source 13 and the drain 14 is formed by a patterning process on the surface of the substrate on which the pattern of the etch barrier layer 15 is formed.
  • Embodiments of the present disclosure provide an array substrate including any of the TFTs described above.
  • the array substrate further includes a passivation layer 16 on the surface of the source 13 and the drain 14, and a pixel electrode 17 on the surface of the passivation layer 16.
  • the pixel electrode 17 is connected to the drain 14 of the TFT through a via hole on the passivation layer 16, so that the signal of the TFT source 13 can be transmitted to the pixel electrode through the drain 14 of the TFT when the TFT is turned on. 17, thereby charging the pixel electrode 17, and displaying different gray scales according to the size of the charging.
  • the TFT in the above array substrate has the same structure and beneficial effects as the TFT provided in the foregoing embodiment.
  • the structure and the beneficial effects of the TFT are described in detail in the foregoing embodiments, and details are not described herein again.
  • Embodiments of the present disclosure provide a display device including the array substrate as described above, and the display device may specifically include a liquid crystal display device.
  • the display device may be any product or component having a display function such as a liquid crystal display, a liquid crystal television, a digital photo frame, a mobile phone, or a tablet computer.
  • the detailed structure of the array substrate has been described in detail in the foregoing embodiments, and details are not described herein again.

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Abstract

提供一种TFT及其制作方法、阵列基板及显示装置。涉及显示技术领域，能够避免由于氧化物半导体材料暴露于外部环境而造成TFT性能的劣化。TFT包括有源层（12），有源层包括第一有源层（121）和第二有源层（122），构成第二有源层的材料为氧化物半导体材料，且第一有源层的导电率大于第二有源层的导电率。

Description

TFT及其制作方法、阵列基板及显示装置
相关申请的交叉参考
本申请主张在2015年9月23日在中国提交的中国专利申请号No.201510613453.6的优先权，其全部内容通过引用包含于此。
技术领域
本公开文本涉及显示技术领域，尤其涉及一种TFT及其制作方法、阵列基板及显示装置。
背景技术
随着科技的不断进步，用户对液晶显示设备的需求日益增加。目前，TFT-LCD(Thin Film Transistor-Liquid Crystal Display，薄膜场效应晶体管液晶显示器)成为了手机、平板电脑等产品中使用的主流显示器。
TFT的性能决定了显示器的显示品质。现有技术中TFT的有源层可以采用非晶硅以及氧化物半导体材料构成。相对于非晶硅而言，氧化物半导体材料能够使得可视光线通过，从而可以提高像素开口率，并且成本更低廉。
然而，在制备有源层的过程中，当氧化物半导体材料暴露于外部环境(例如湿气、氧气环境)时其特性会劣化，使得迁移率降低，从而会对TFT的性能造成影响。
发明内容
(一)要解决的技术问题
本公开文本的实施例提供一种TFT及其制作方法、阵列基板及显示装置，能够避免由于氧化物半导体材料暴露于外部环境而造成TFT性能的劣化。
(二)技术方案
为达到上述目的，本公开文本的实施例采用如下技术方案：
根据本公开文本实施例的一方面，提供了一种薄膜晶体管TFT，包括有源层，所述有源层包括第一有源层和第二有源层。构成所述第二有源层的材 料为氧化物半导体材料，且所述第一有源层的导电率大于所述第二有源层的导电率。
可选的，所述有源层包括一层所述第一有源层和一层所述第二有源层。
可选的，所述薄膜晶体管还包括源极、漏极。所述第一有源层相对于所述第二有源层，靠近所述源极和所述漏极。
可选的，所述薄膜晶体管还包括源极、漏极。所述第二有源层相对于所述第一有源层，靠近所述源极和所述漏极，且所述第二有源层的表面形成有刻蚀阻挡层。
可选的，所述薄膜晶体管还包括源极、漏极。所述有源层包括一层所述第一有源层和两层所述第二有源层。所述第一有源层位于所述两层第二有源层之间，且靠近所述源极、漏极的第二有源层的表面形成有刻蚀阻挡层。
可选的，所述第一有源层的位置与TFT沟道的位置相对应。
可选的，构成所述第一有源层的材料包括氧化铟锡、氧化铟锌、二氧化锡、三氧化二铟、氧化锌以及碳纳米管中的至少一种。
可选的，构成所述第二有源层的材料包括铟镓锌氧化物、氧化镉以及三氧化二铝中的至少一种。
可选的，所述第一有源层的厚度为100埃～4000埃。
根据本公开文本实施例的另一方面，提供了一种TFT的制作方法，包括在衬底基板上形成有源层。所述在衬底基板上形成有源层的步骤包括：在所述衬底基板上形成第一有源层和第二有源层。其中，构成所述第二有源层的材料为氧化物半导体材料，且所述第一有源层的导电率大于所述第二有源层的导电率。
可选的，所述在所述衬底基板上形成第一有源层和第二有源层的步骤包括：在所述衬底基板上形成一层所述第一有源层和一层所述第二有源层。
可选的，所述TFT的制作方法还包括在衬底基板上形成源极、漏极。其中，所述第一有源层相对于所述第二有源层，靠近所述源极和所述漏极。
可选的，所述TFT的制作方法还包括在衬底基板上形成源极、漏极。其中，所述第二有源层相对于所述第一有源层，靠近所述源极和所述漏极。所述在衬底基板上形成源极、漏极的步骤之前包括：在所述第二有源层的表面 形成有刻蚀阻挡层。
可选的，所述TFT的制作方法还包括在衬底基板上形成源极、漏极。所述在所述衬底基板上形成第一有源层和第二有源层的步骤包括：在所述衬底基板上形成一层所述第一有源层和两层所述第二有源层。所述第一有源层位于所述两层第二有源层之间。在靠近所述源极、漏极的第二有源层的表面形成有刻蚀阻挡层。
可选的，构成所述第一有源层的材料包括氧化铟锡、氧化铟锌、二氧化锡、三氧化二铟、氧化锌以及碳纳米管中的至少一种。
可选的，构成所述第二有源层的材料包括铟镓锌氧化物、氧化镉以及三氧化二铝中的至少一种。
根据本公开文本实施例的另一方面，提供了一种阵列基板，包括如上所述的任意一种TFT。
根据本公开文本实施例的又一方面，提供了一种显示装置，包括上述阵列基板。
(三)有益效果
本公开文本实施例至少具有如下有益效果：
本公开文本实施例提供一种TFT及其制作方法、阵列基板及显示装置。所述TFT包括有源层。该有源层包括第一有源层和第二有源层。其中，构成第二有源层的材料为氧化物半导体材料，且第一有源层的导电率大于第二有源层的导电率。这样一来，即使由氧化物半导体材料构成的第二有源层在外界环境因素的影响下，使得其迁移率降低，而导电率较大的第一有源层会增加电子的传输速率，从而对整个有源层的迁移率进行补偿。因此避免了TFT的性能受到影响。
附图说明
为了更清楚地说明本公开文本实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开文本的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附 图。
图1a为本公开文本实施例提供的一种底栅型TFT的结构示意图；
图1b为本公开文本实施例提供的一种顶栅型TFT的结构示意图；
图2a为图1a所示的TFT中当有源层包括一层第一有源层和一层第二有源层的一种结构示意图；
图2b为图1a所示的TFT中当有源层包括一层第一有源层和一层第二有源层的另一种结构示意图；
图3为图1a所示的TFT中当有源层包括一层第一有源层和两层第二有源层的一种结构示意图；
图4a～图4c为图2a所示的TFT的制作过程中各个步骤对应的结构示意图；以及
图5为采用图3所示的TFT的阵列基板的结构示意图。
附图标记说明：
01-衬底基板；10-栅极；11-栅极绝缘层；12-有源层；121-第一有源层；122、122’-第二有源层；13-源极；14-漏极；15-刻蚀阻挡层；16-钝化层；17-像素电极。
具体实施方式
下面结合附图和实施例，对本公开文本的具体实施方式做进一步描述。以下实施例仅用于说明本公开文本，但不用来限制本公开文本的范围。
为使本公开文本实施例的目的、技术方案和优点更加清楚，下面将结合本公开文本实施例的附图，对本公开文本实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开文本的一部分实施例，而不是全部的实施例。基于所描述的本公开文本的实施例，本领域普通技术人员所获得的所有其他实施例，都属于本公开文本保护的范围。
除非另作定义，此处使用的技术术语或者科学术语应当为本公开文本所属领域内具有一般技能的人士所理解的通常意义。本公开文本专利申请说明书以及权利要求书中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”或 者“一”等类似词语也不表示数量限制，而是表示存在至少一个。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也相应地改变。
下面将结合本公开文本实施例中的附图，对本公开文本实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本公开文本的一部分实施例，而不是全部的实施例。基于本公开文本中所公开的各个实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开文本保护的范围。
本公开文本实施例提供了一种TFT，其包括有源层。该有源层包括第一有源层和第二有源层。其中，构成第二有源层的材料为氧化物半导体材料，且第一有源层的导电率大于第二有源层的导电率。
本公开文本实施例所提供的一种TFT包括有源层。该有源层包括第一有源层和第二有源层。其中，构成第二有源层的材料为氧化物半导体材料，且第一有源层的导电率大于第二有源层的导电率。这样一来，即使由氧化物半导体材料构成的第二有源层在外界环境因素的影响下，使得其迁移率降低，而导电率较大的第一有源层会增加电子的传输速率，从而对整个有源层的迁移率进行补偿。因此避免了TFT的性能受到影响。
在描述本公开文本的各个实施例之前，需要做出如下的说明。
第一、本公开文本对TFT的类型不做限定。例如，TFT可以是如图1a所示的底栅型TFT。具体的，对于底栅型TFT而言，栅极10相对于栅极绝缘层11更靠近衬底基板01。在栅极绝缘层11的表面形成有源层12，在有源层的表面形成有源极13和漏极14。
或者，也可以是如图1b所示的顶栅型TFT。具体的，对于顶栅型TFT而言，栅极10相对于栅极绝缘层11更远离衬底基板01。此外，有源层12形成于衬底基板01的表面。所述有源层的表面形成有源极13和漏极14。
其中，为了方便举例说明，本公开文本以下实施例均是以底栅型TFT为例进行的说明。
第二、本公开文本实施例中构成第二有源层的氧化物半导体材料可以包括氧化镉(CdO)、三氧化二铝(Al2O3)以及铟镓锌氧化物(IGZO)中的任意一种。
第三、本公开文本对有源层12中包括的第一有源层121和第二有源层122(如图2a、图2b或图3所示)的数量不做限定。例如，可以如图2a所示包括一层第一有源层121和一层第二有源层122。或者，如图3所示包括一层第一有源层121和两层第二有源层122、122’。
以下将通过具体的实施例，对TFT的有源层12具有不同数量的第一有源层121和第二有源层122的结构进行详细的举例说明。
实施例一
本实施例所提供的有源层12包括一层第一有源层121和一层第二有源层122。如图2a所示，第一有源层121相对于第二有源层122而言，更靠近源极13和漏极14。
具体的，如图2a所示，第一有源层121相对于第二有源层122而言，更靠近源极13和漏极14。这样一来，由于第一有源层121位于第二有源层122的表面，从而可以对其迁移率容易受到外界环境影响的第二有源层122进行保护。避免在制作源极13和漏极14的过程中，外界环境中的湿气或氧气等直接与第二有源层122相接触，从而降低了第二有源层122的迁移率。
其中，对于构成第二有源层122的材料，例如氧化镉(CdO)、三氧化二铝(Al2O3)或者铟镓锌氧化物(IGZO)而言，其氧原子和其它金属原子处于弱结合的状态。而当构成上述第一有源层121的材料为氧化铟锡(InSnO)、氧化铟锌(InZnO)、二氧化锡(SnO2)、三氧化二铟(In2O3)、氧化锌(ZnO)以及碳纳米管(英文全称：Carbon Nano Tube，英文简称：CNT)中的至少一种时，由于上述构成第一有源层121的材料能够诱发第二有源层122中的氧原子与有源层12中的其它原子，例如金属原子铟In、锡Sn等进行强结合。从而可以减少有源层12中的缺陷数量，使得缺陷捕获电子的能力下降，从而可以提高电子的移动速度，由此使得有源层12的迁移率得到有效的提升。
此外，当第一有源层121和第二有源层122的图案一致时，可以采用一次掩膜曝光工艺形成上述第一有源层121和第二有源层122的图案。具体的， 可以在栅极绝缘层11的表面涂覆由氧化镉(CdO)、三氧化二铝(Al2O3)以及者铟镓锌氧化物(IGZO)中的至少一种构成的第二薄膜层，然后在所述第二薄膜层的表面涂覆由氧化铟锡(InSnO)、氧化铟锌(InZnO)、二氧化锡(SnO2)、三氧化二铟(In2O3)、氧化锌(ZnO)以及碳纳米管中的至少一种构成的第一薄膜层。接下来在上述第一薄膜层的表面涂覆光刻胶，然后通过掩膜曝光工艺一次形成第一有源层121和第二有源层122的图案。
实施例二
本实施例所提供的有源层12包括一层第一有源层121和一层第二有源层122。与实施例一不同的是，如图2b所示，第二有源层122相对于第一有源层121而言，更靠近源极13和漏极14。
在此基础上，为了避免制作源极13和漏极14的过程中，外界的湿气或者氧气对第二有源层122的性能造成影响。可以在第二有源层122的表面设置刻蚀阻挡层15，以对第二有源层122进行保护，使其能够保持原有的迁移率。此外位于第二有源层122下方的第一有源层121由于具有较高的迁移率，所以可以进一步提高整个有源层12的迁移率。
此外，构成第一有源层121的材料同实施例一相同，也可以为氧化铟锡(InSnO)、氧化铟锌(InZnO)、二氧化锡(SnO2)、三氧化二铟(In2O3)、氧化锌(ZnO)以及碳纳米管中的至少一种。且与实施例一的有益效果相同，此处不再赘述。
并且，为了节省制作工艺，可以采用一次掩膜曝光工艺制备图案一致的第一有源层121和第二有源层122。
综上所述，相对于实施例一而言，实施例二中第二有源层122的表面设置有刻蚀阻挡层15，因此可以减小外界因素对第二有源层122迁移率的影响。所以实施例二提供的方案中有源层12的迁移率更高。此外，实施例二中，与源极13和漏极14相接触的为第二有源层122，由于第二有源层122的导电率相对于第一有源层121的导电率较低，所以实施例二提供的TFT的漏电流与实施例一提供的TFT的漏电流相比较小。因此实施例二提供的TFT的迁移率较高，且漏电流较小，所以性能较佳。
然而，由于设置了刻蚀阻挡层15，所以在制备TFT的过程中需要增加制 作刻蚀阻挡层15的步骤，因此制作过程相对于实施例一而言较复杂。
实施例三
本实施例中有源层12，如图3所示，可以包括一层第一有源层121和两层第二有源层122、122’。
其中，第一有源层121位于两层第二有源层122和122’之间，并且靠近源极13、漏极14的第二有源层122’的表面形成有刻蚀阻挡层15。这样一来，通过上述刻蚀阻挡层15，可以对与源极13、漏极14相接触的第二有源层122’进行保护，避免在制作源极13、漏极14的过程中，外界环境降低第二有源层122’的性能，使其能够保持原有的迁移率。此外位于两层第二有源层122、122’中间的第一有源层121，由于具有较高的迁移率，所以可以进一步提高整个有源层12的迁移率。
此外，与源极13和漏极14相接触的是第二有源层122’，由于第二有源层122’的导电率相对于第一有源层121的导电率较低，所以本实施例中TFT的漏电流较小。因此实施例三提供的TFT，相对于实施例一提供的TFT而言，TFT的迁移率较高，且漏电流较小，所以性能较佳。
然而，由于设置了刻蚀阻挡层15，所以在制备TFT的过程中需要增加制作刻蚀阻挡层15的步骤，因此制作过程相对于实施例一而言较复杂。
此外，还需要做出如下的说明。
第一、本实施例中，位于两层第二有源层122、122’中间的第一有源层121的图案可以与两层第二有源层122、122’相一致，这样一来，可以通过一次掩膜曝光工艺形成两层第二有源层122、122’以及第一有源层121的图案。
或者，还可以如图3所示，在对应TFT沟道的位置形成上述第一有源层121。这样一来，位于TFT沟道的位置的第一有源层121可以在TFT导通时，提高TFT沟道的位置处电子的移动速度，使得TFT具有较高的迁移率。并且由于只在对应TFT沟道的位置处制作了上述第一有源层121，因此可以在提高TFT迁移率的同时，节省制作第一有源层121的材料。
第二、构成第一有源层121的材料同实施例一相同，也可以为氧化铟锡(InSnO)、氧化铟锌(InZnO)、二氧化锡(SnO2)、三氧化二铟(In2O3)、氧化锌(ZnO)以及碳纳米管中的至少一种。且与实施例一的有益效果相同， 此处不再赘述。
此外，对于上述任意一种实施例，所述第一有源层121的厚度可以为100埃～4000埃。当第一有源层121的厚度小于100埃时，由于厚度太小，因此构成第一有源层121的材料诱发第二有源层122中的氧原子与有源层12中的其它原子进行强结合的能力也较弱，从而削弱了对整个有源层12迁移率进行补偿或提升的效果。此外，当厚度大于4000埃时，虽然可以有效的对有源层12的迁移率进行补偿或提升。但是由于第二有源层122的厚度较厚，因此当上述TFT应用于显示装置时，不利于超薄化显示装置的设计。
此外，本公开文本实施例还提供了一种TFT的制作方法，包括：在衬底基板01上形成有源层12，其中具体形成该有源层12的方法可以包括：
在衬底基板01上形成第一有源层121和第二有源层122。
其中，构成第二有源层12的材料为氧化物半导体材料，且第一有源层121的导电率大于第二有源层122的导电率。
这样一来，即使由氧化物半导体材料构成的第二有源层在外界环境因素的影响下，使得其迁移率降低，而导电率较大的第一有源层会增加电子的传输速率，从而对整个有源层的迁移率进行补偿。因此避免了TFT的性能受到影响。
此外，还需要做出如下的说明。
第一、构成第二有源层的氧化物半导体材料可以包括氧化镉(CdO)、三氧化二铝(Al2O3)以及铟镓锌氧化物(IGZO)中的任意一种。构成第一有源层121的材料包括氧化铟锡(InSnO)、氧化铟锌(InZnO)、二氧化锡(SnO2)、三氧化二铟(In2O3)、氧化锌(ZnO)以及碳纳米管中的至少一种。且与实施例一的有益效果相同，此处不再赘述。
第二、本公开文本实施例中，构图工艺可指包括光刻工艺，或者包括光刻工艺以及刻蚀步骤，同时还可以包括打印、喷墨等其他用于形成预定图形的工艺。光刻工艺是指包括成膜、曝光、显影等工艺过程的利用光刻胶、掩模板、曝光机等形成图形的工艺。可根据本公开文本中所形成的结构选择相应的构图工艺。
其中，本公开文本实施例中的一次构图工艺，是以通过一次掩膜曝光工 艺形成不同的曝光区域，然后对不同的曝光区域进行多次刻蚀、灰化等去除工艺最终得到预期图案为例进行的说明。
本公开文本对有源层12中包括的第一有源层121和第二有源层122(如图2a、图2b或图3所示)的数量不做限定，以下通过具体的实施例，对TFT的有源层12具有不同数量的第一有源层121和第二有源层122时，TFT的制作过程进行详细的举例说明。
实施例四
本实施例中有源层12包括一层第一有源层121和一层第二有源层122。
具体的，首先，如图4a所示，在衬底基板01上，形成一层栅极金属层，然后在所述栅极金属层的表面涂覆一层光刻胶层，然后通过掩膜曝光工艺形成栅极10的图案。
接下来，在衬底基板01上形成栅极绝缘层11。具体的，如图4b所示，在栅极10的表面涂覆一层栅极绝缘层11。
然后，如图4c所示，在衬底基板01上形成一层所述第一有源层121和一层第二有源层122。具体的，可以在栅极绝缘层11的表面涂覆由氧化镉(CdO)、三氧化二铝(Al2O3)以及铟镓锌氧化物(IGZO)中的至少一种构成的第二薄膜层，然后在所述第二薄膜层的表面涂覆由氧化铟锡(InSnO)、氧化铟锌(InZnO)、二氧化锡(SnO2)、三氧化二铟(In2O3)、氧化锌(ZnO)以及碳纳米管中的至少一种构成的第一薄膜层。接下来在上述第一薄膜层的表面涂覆光刻胶，然后通过掩膜曝光工艺一次形成第一有源层121和第二有源层122的图案。
最后，在第一有源层121的表面涂覆一层源漏金属层，然后在该源漏金属层的表面形成光刻胶层。接下来，通过掩膜曝光工艺可以形成如图2a所示的源极13和漏极14的图案，且第一有源层121相对于第二有源层122而言，更靠近源极13和漏极14。这样一来，由于第一有源层121位于第二有源层122的表面，从而可以对其迁移率容易受到外界环境影响的第二有源层122进行保护。避免在制作源极13和漏极14的过程中，外界环境中的湿气或氧气等直接与第二有源层122相接触而导致降低第二有源层122的迁移率。
或者，在衬底基板01上形成一层所述第一有源层121和一层第二有源层 122的方法还可以包括在栅极绝缘层11的表面先形成上述第一薄膜层，再形成上述第二薄膜层，然后通过掩膜曝光工艺一次形成第二有源层122和第一有源层121的图案。接下来，可以在第二有源层122的表面通过一次构图工艺形成刻蚀阻挡层15的图案。这样一来，通过上述刻蚀阻挡层15，可以对与源极13、漏极14相接触的第二有源层进行保护，避免在制作源极13、漏极14的过程中，外界环境降低第二有源层122的性能，使其能够保持原有的迁移率。最后，在形成有刻蚀阻挡层15的基板表面涂覆一层源漏金属层，然后在该源漏金属层的表面形成光刻胶层，再通过掩膜曝光工艺形成如图2b所示的源极13和漏极14的图案，且第二有源层122相对于第一有源层121而言，更靠近源极13和漏极14。这样一来，在第二有源层122的表面设置刻蚀阻挡层15，可以对第二有源层122进行保护，使其能够保持原有的迁移率。此外，位于第二有源层122下方的第一有源层121由于具有较高的迁移率，所以可以进一步提高整个有源层12的迁移率。
实施例五
本实施例中的有源层12可以包括一层第一有源层121和两层第二有源层122，122’。
具体的，如图3所示，首先通过构图工艺，依次在衬底基板01的表面形成栅极10和栅极绝缘层11。
然后在栅极绝缘层11的表面形成一层第一有源层121和两层第二有源层122、122’。第一有源层121位于两层第二有源层122、122’之间。具体的，在栅极绝缘层11的表面涂覆由氧化镉(CdO)、三氧化二铝(Al2O3)以及铟镓锌氧化物(IGZO)中的至少一种构成的第二薄膜层。然后在上述第二薄膜层上涂覆由氧化铟锡(InSnO)、氧化铟锌(InZnO)、二氧化锡(SnO2)、三氧化二铟(In2O3)、氧化锌(ZnO)以及碳纳米管中的至少一种构成的第一薄膜层。接下来，在所述第一薄膜层上再次涂覆所述第二薄膜层，然后通过一次构图工艺形成图案一致的一层第一有源层121和两层第二有源层122、122’。
或者，在栅极绝缘层11的表面形成一层第一有源层121和两层第二有源层122、122’的方法可以是，在栅极绝缘层11的表面形成上述第二薄膜层， 然后通过一次构图工艺形成第二有源层122的图案，接下来在第二有源层122的表面涂覆上述第一薄膜层，然后通过一次构图工艺在对应TFT沟道的位置形成第一有源层121的图案。接下来，在形成有第一有源层121和第二有源层122的基板表面涂覆上述第二薄膜层，通过一次构图工艺形成第二有源层122’的图案。相对于第一有源层121与两层第二有源层122、122’的图案一致的方案而言，图3所示的方案制作过程相对复杂，但是由于只在对应TFT沟道的位置制作了上述第一有源层121，因此可以在提高TFT迁移率的同时，节省制作第一有源层121的材料。
接下来，在形成有有源层12的基板上，通过构图工艺形成刻蚀阻挡层15的图案，以对最上层(靠近源极13、漏极14)的第二有源层122’进行保护，避免外界环境对其迁移率的影响。
最后，在形成有刻蚀阻挡层15图案的基板表面，通过构图工艺形成源极13和漏极14的图案。
本公开文本实施例提供一种阵列基板，包括如上所述的任意一种TFT。如图5所示，所述阵列基板还包括位于源极13和漏极14表面的钝化层16，以及位于钝化层16表面的像素电极17。所述像素电极17通过位于钝化层16上的过孔与TFT的漏极14相连接，从而可以在TFT导通时，将TFT源极13的信号通过TFT的漏极14，传输至像素电极17，从而对像素电极17进行充电，根据充电的大小实现不同灰阶的显示。
需要说明的是，上述阵列基板中的TFT具有与前述实施例提供的TFT相同的结构和有益效果，由于前述实施例对TFT的结构和有益效果进行了详细的描述，此处不再赘述。
本公开文本实施例提供一种显示装置，包括如上所述的阵列基板，该显示装置具体可以包括液晶显示装置。例如，该显示装置可以为液晶显示器、液晶电视、数码相框、手机或平板电脑等任何具有显示功能的产品或者部件。其中，阵列基板的详细结构已在前述实施例中做了详细的描述，此处不再赘述。
以上所述，仅为本公开文本的具体实施方式，但本公开文本的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开文本揭露的技术范 围内，可轻易想到变化或替换，都应涵盖在本公开文本的保护范围之内。因此，本公开文本的保护范围应以所述权利要求的保护范围为准。

Claims (16)

  1. 一种薄膜晶体管TFT，包括有源层，所述有源层包括第一有源层和第二有源层；
    其中，构成所述第二有源层的材料为氧化物半导体材料，且所述第一有源层的导电率大于所述第二有源层的导电率。
  2. 根据权利要求1所述的TFT，其中，所述有源层包括一层所述第一有源层和一层所述第二有源层。
  3. 根据权利要求2所述的TFT，还包括源极、漏极；
    其中，所述第一有源层相对于所述第二有源层，靠近所述源极和所述漏极。
  4. 根据权利要求2所述的TFT，还包括源极、漏极；
    其中，所述第二有源层相对于所述第一有源层，靠近所述源极和所述漏极，且所述第二有源层的表面形成有刻蚀阻挡层。
  5. 根据权利要求1所述的TFT，还包括源极、漏极；
    其中，所述有源层包括一层所述第一有源层和两层所述第二有源层，所述第一有源层位于所述两层第二有源层之间，且靠近所述源极、漏极的第二有源层的表面形成有刻蚀阻挡层。
  6. 根据权利要求1所述的TFT，其中，所述第一有源层的位置与TFT沟道的位置相对应。
  7. 根据权利要求1所述的TFT，其中，构成所述第一有源层的材料包括氧化铟锡、氧化铟锌、二氧化锡、三氧化二铟、氧化锌以及碳纳米管中的至少一种；并且
    构成所述第二有源层的材料包括铟镓锌氧化物、氧化镉以及三氧化二铝中的至少一种。
  8. 根据权利要求1-7任一项所述的TFT，其中，所述第一有源层的厚度为100埃～4000埃。
  9. 一种薄膜晶体管TFT的制作方法，包括：在衬底基板上形成有源层；所述在衬底基板上形成有源层的步骤包括：
    在所述衬底基板上形成第一有源层和第二有源层；
    其中，构成所述第二有源层的材料为氧化物半导体材料，且所述第一有源层的导电率大于所述第二有源层的导电率。
  10. 根据权利要求9所述的TFT的制作方法，其中，
    所述在所述衬底基板上形成第一有源层和第二有源层的步骤包括：
    在所述衬底基板上形成一层所述第一有源层和一层所述第二有源层。
  11. 根据权利要求10所述的TFT的制作方法，还包括：在衬底基板上形成源极、漏极；
    其中，所述第一有源层相对于所述第二有源层，靠近所述源极和所述漏极。
  12. 根据权利要求10所述的TFT的制作方法，还包括：在衬底基板上形成源极、漏极；
    其中，所述第二有源层相对于所述第一有源层，靠近所述源极和所述漏极；并且
    在所述在衬底基板上形成源极、漏极的步骤之前包括：在所述第二有源层的表面形成有刻蚀阻挡层。
  13. 根据权利要求9所述的TFT的制作方法，还包括：在衬底基板上形成源极、漏极；
    其中，所述在所述衬底基板上形成第一有源层和第二有源层的步骤包括：
    在所述衬底基板上形成一层所述第一有源层和两层所述第二有源层；所述第一有源层位于所述两层第二有源层之间；并且
    在靠近所述源极、漏极的第二有源层的表面形成有刻蚀阻挡层。
  14. 根据权利要求9所述的TFT的制作方法，其中，构成所述第一有源层的材料包括氧化铟锡、氧化铟锌、二氧化锡、三氧化二铟、氧化锌以及碳纳米管中的至少一种；并且
    构成所述第二有源层的材料包括铟镓锌氧化物、氧化镉以及三氧化二铝中的至少一种。
  15. 一种阵列基板，包括如权利要求1-8任一项所述的薄膜晶体管TFT。
  16. 一种显示装置，包括如权利要求15所述的阵列基板。
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