CN103715269A - 薄膜晶体管、阵列基板及显示装置 - Google Patents
薄膜晶体管、阵列基板及显示装置 Download PDFInfo
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Abstract
本发明提供了一种薄膜晶体管、阵列基板及显示装置,所述薄膜晶体管包括:栅电极、栅绝缘层、有源层、源电极及漏电极;其中,所述有源层包括至少两层半导体薄膜,所述至少两层半导体薄膜包括至少一层单晶半导体薄膜。通过本发明的方案,可以提高薄膜晶体管的载流子迁移率。
Description
技术领域
本发明涉及显示技术领域,尤其涉及一种薄膜晶体管、阵列基板及显示装置。
背景技术
铟镓锌氧化物(IGZO)因其迁移率高、均匀性好和可在室温下制备而被广泛地研究,以期能替代单晶硅及低温多晶硅技术(LTPS)用作背板薄膜晶体管(TFT)的沟道材料,而实现诸如有源矩阵有机发光二极管面板(AMOLED)等大尺寸面板的产业化。
然而,目前IGZO半导体用作TFT的沟道材料时,相比于单晶硅及LTPS而言,其载流子迁移率仍偏低(约10~20cm2V-1s-1)。TFT器件的载流子迁移率降低,会造成其等效电阻大,充放电时间加长,成为制备大尺寸面板的严重瓶颈。
发明内容
有鉴于此,本发明提供一种薄膜晶体管、阵列基板及显示装置,以解决现有氧化物TFT器件的载流子迁移率偏低的问题。
为解决上述问题,本发明提供了一种薄膜晶体管,栅电极、栅绝缘层、有源层、源电极及漏电极;所述有源层包括至少两层半导体薄膜,所述至少两层半导体薄膜包括至少一层单晶半导体薄膜。
优选地,所述至少两层半导体薄膜为同一种半导体材料。
优选地,所述至少两层半导体薄膜为不同种半导体材料。
优选地,所述半导体材料为金属氧化物半导体、单质元素半导体或非氧化物的化合物半导体。
优选地,所述至少两层半导体薄膜全部为单晶半导体薄膜、或者同时包含单晶半导体薄膜和非晶半导体薄膜。
优选地,所述至少两层半导体薄膜包括依次设置的非晶铟镓锌氧化物薄膜、单晶铟镓锌氧化物薄膜和非晶铟镓锌氧化物薄膜。
优选地,所述至少两层半导体薄膜包括依次设置的单晶铟镓锌氧化物薄膜、单晶氧化亚铜薄膜和单晶铟镓锌氧化物薄膜。
优选地,所述至少两层半导体薄膜包括依次设置的非晶铟镓锌氧化物薄膜和单晶氧化亚铜薄膜。
本发明还提供一种阵列基板,包括上述薄膜晶体管。
本发明还提供一种显示装置,包括上述阵列基板。
本发明的上述技术方案的有益效果如下:
由于薄膜晶体管的有源层为至少两层半导体薄膜结构,其中,部分半导体薄膜可作为载流子产生区域,另一部分半导体薄膜可作为载流子传输区域,从而使得载流子产生区域和载流子传输区域分开,以避免载流子在传输过程中因为载流子被过多的电离杂质所散射而导致传输速度变慢,提高了TFT器件的载流子迁移率。
附图说明
图1为本发明实施例一的薄膜晶体管的结构示意图;
图2为本发明实施例二的薄膜晶体管的结构示意图;
图3为本发明实施例一的薄膜晶体管的制备方法流程示意图;
图4为本发明实施例的薄膜晶体管的一有源层的能带示意图;
图5为本发明实施例的薄膜晶体管的另一有源层的能带示意图;
图6为本发明实施例三的薄膜晶体管的结构示意图;
图7为本发明实施例四的薄膜晶体管的结构示意图。
具体实施方式
在针对氧化物TFT的迁移率进行研究的过程中,本发明的发明人发现:现有的以IGZO半导体为沟道材料的TFT器件的沟道(即有源层)是单层结构的,即其整体上由一层非晶氧化物构成,这种单层结构导致载流子产生区域和载流子传输区域叠合,从而在传输过程中因为载流子被过多的电离杂质所散射而导致载流子的传输速度变慢,反映为TFT器件的载流子迁移率降低。
针对这一问题,本发明实施例提供了一种薄膜晶体管、阵列基板及显示装置。为使本发明要解决的技术问题、技术方案和优点更加清楚,下面将结合附图及具体实施例进行详细描述。
为解决单层有源层结构的TFT器件的载流子迁移率偏低的问题,本发明实施例提供一种薄膜晶体管,包括:制作在衬底上的栅电极、栅绝缘层、有源层、源电极及漏电极;其中,所述有源层包括至少两层半导体薄膜,所述至少两层半导体薄膜包括至少一层单晶半导体薄膜。
其中:
所述衬底可采用玻璃或石英等透明材料制成,或者采用陶瓷、金属等非透明材料制成。
所述栅电极、源电极和漏电极可采用钼(Mo)、金(Au)、铝(Al)、铬(Cr)、钛(Ti)等金属材质、合金材料或其他复合导电材料制成。
所述栅绝缘层可采用氧化硅(SiO2)、氮化硅(SiNx)等绝缘材质制成。
所述有源层的至少两层半导体薄膜可以为同一种半导体材料,也可以为不同种半导体材料。所述半导体材料可以为金属氧化物半导体、单质元素半导体(如Si)或非氧化物的化合物半导体(如II-VI族半导体)。也就是说,所述至少两层半导体薄膜可以全部为同一种金属氧化物半导体,也可以全部为同一种单质元素半导体,或者,全部为同一种非氧化物的化合物半导体,又或者,为不同种半导体材料,例如,一层为金属氧化物半导体,一层为单质元素半导体。
另外,所述至少两层半导体薄膜可以全部为单晶半导体薄膜或者同时包含单晶半导体薄膜和非晶半导体薄膜,即,所述至少两层半导体薄膜包括至少一层单晶半导体薄膜。
优选地,所述至少两层半导体薄膜可以包括依次设置的非晶铟镓锌氧化物薄膜、单晶铟镓锌氧化物薄膜和非晶铟镓锌氧化物薄膜。
优选地,所述至少两层半导体薄膜可以包括依次设置的单晶铟镓锌氧化物薄膜、单晶氧化亚铜薄膜和单晶铟镓锌氧化物薄膜。
优选地,所述至少两层半导体薄膜可以包括依次设置的非晶铟镓锌氧化物薄膜和单晶氧化亚铜薄膜。
通过上述实施例提供的薄膜晶体管,由于薄膜晶体管的有源层为至少两层半导体薄膜结构,其中,部分半导体薄膜可作为载流子产生区域,另一部分半导体薄膜可作为载流子传输区域,从而使得载流子产生区域和载流子传输区域分开,以避免载流子在传输过程中因为载流子被过多的电离杂质所散射而导致传输速度变慢,提高了TFT器件的载流子迁移率。
下面通过具体实施例对本发明实施例的薄膜晶体管的结构进行详细说明。
实施例一
请参考图1,图1为本发明实施例一的薄膜晶体管的结构示意图,所述薄膜晶体管包括制作在衬底101上的栅电极102、栅绝缘层103、有源层104、刻蚀阻挡层105、源/漏电极106及钝化层107。其中,所述有源层104包括三层半导体薄膜,其中至少一层半导体薄膜为非晶半导体薄膜。
所述刻蚀阻挡层105是用于防止因源/漏电极106的湿法刻蚀造成对有源层104的损伤。
所述钝化层107是用于保护所述薄膜晶体管的其他各层,所述钝化层107可以采用氧化硅、氮化硅或有机材料等绝缘材料制成。
实施例二
请参考图2,图2为本发明实施例二的薄膜晶体管的结构示意图,本实施例中的薄膜晶体管与实施例一的薄膜晶体管相比,在衬底101与栅电极102之间增加了一个缓冲层108,所述缓冲层108可以采用二氧化硅等绝缘材料制成。
上述实施例一和二中的有源层104的三层半导体薄膜可以全部为三层单晶半导体薄膜、或者部分为单晶半导体薄膜部分为非晶半导体薄膜。该种结构的薄膜晶体管也称为超晶格结构的薄膜晶体管。
下面分别以有源层104的三层半导体薄膜全部为单晶半导体薄膜及部分为单晶半导体薄膜、部分为非晶半导体薄膜为例,对实施例一的薄膜晶体管的制备方法进行说明。
(1)有源层包含三层单晶半导体薄膜的薄膜晶体管的制备方法
如图3所示,所述制备方法包括以下步骤:
步骤S11:提供一衬底101,并采用标准方法清洗;
可选地,可以在衬底101上沉积缓冲层108,具体地,可以采用化学气相沉积(CVD)方法在衬底101上沉积200纳米(nm)厚的SiO2薄膜作为缓冲层108;本实施例中,未沉积缓冲层108;
步骤S12:采用溅射方法在衬底101上沉积200nm厚的栅极金属Mo,并光刻、刻蚀出所需的栅电极102的图形;
步骤S13:在370摄氏度下采用CVD方法在栅电极102上沉积150nm厚的SiO2作为栅绝缘层103;
步骤S14:
采用金属有机化学气相沉积(MOCVD)方法在栅绝缘层103上沉积约10nm后的IGZO薄膜,沉积过程中气体氛围的氧含量可以为10%~80%;
采用分子束外延生长(MBE)方法在IGZO薄膜上沉积约20nm厚的氧化亚铜(Cu2O)薄膜,沉积过程中气体氛围的氧含量可以为10%~80%;
采用MOCVD方法在Cu2O薄膜上沉积约10nm厚的IGZO薄膜,沉积过程中气体氛围的氧含量可以为10%~80%;
进行光刻、刻蚀出所需的有源层104(即TFT的沟道区)图形;
步骤S15:在有源层104上沉积约50nm厚的SiO2,并光刻、刻蚀出刻蚀阻挡层105;
步骤S16:采用溅射方法沉积约200nm厚的源、漏电极金属Mo/Al,并光刻、刻蚀出所需的源/漏电极106图形;
步骤S17:采用CVD方法沉积约100~500nm厚的SiO2,形成钝化层107。另外,还需要在所述钝化层107上进行光刻、刻蚀出连接孔,用于后续显示面板工艺的进行。
通过以上步骤,有源层包含三层单晶半导体薄膜的薄膜晶体管的制备完成。
上述薄膜晶体管的有源层104包含的三层结构均为单晶半导体薄膜(IGZO/Cu2O/IGZO)。请参考图4,该种结构下,上下两层的单晶半导体薄膜的能带与中间层单晶半导体薄膜的能带形成量子阱,因Cu2O为p型半导体,上下IGZO层向其提供空穴载流子,通过精确控制量子阱的宽度(即Cu2O层的厚度),可将空穴载流子束缚在该量子阱中,又因Cu2O层为单晶态,空穴载流子不会被过多的电离杂质所散射,因而迁移率能够得到提升,这样就得到了迁移率较高的p型TFT器件。
TFT器件制备结束后,可在其上溅射沉积ITO电极,并光刻、刻蚀出阵列基板的像素区或亚像素区图形,最终形成显示面板的阵列基板。如果是制作OLED显示设备,则继续旋涂沉积亚克力系材料并光刻、固化出约1.5um厚的像素界定层,最终形成OLED显示设备的背板。
(2)有源层包含非晶/单晶/非晶半导体薄膜的薄膜晶体管的制备方法
所述制备方法包括以下步骤:
步骤S21:提供一衬底101,并采用标准方法清洗;
可选地,可以在衬底101上沉积缓冲层108,具体地,可以采用化学气相沉积(CVD)方法在衬底101上沉积200纳米(nm)厚的SiO2薄膜作为缓冲层108;本实施例中,未沉积缓冲层108;
步骤S22:采用溅射方法在衬底101上沉积200nm厚的栅极金属Mo,并光刻、刻蚀出所需的栅电极102的图形;
步骤S23:在370摄氏度下采用CVD方法在栅电极102上沉积150nm厚的SiO2作为栅绝缘层103;
步骤S24:
采用溅射方法在栅绝缘层103上沉积约10nm后的IGZO非晶薄膜,沉积过程中气体氛围的氧含量可以为10%~80%;
采用MOCVD方法在IGZO非晶薄膜上沉积约20nm厚的IGZO单晶薄膜,沉积过程中气体氛围的氧含量可以为10%~80%;
采用溅射方法在IGZO单晶薄膜上沉积约10nm厚的IGZO非晶薄膜,沉积过程中气体氛围的氧含量可以为10%~80%;
进行光刻、刻蚀出所需的有源层104(即TFT的沟道区)图形;
步骤S25:在有源层104上沉积约50nm厚的SiO2,并光刻、刻蚀出刻蚀阻挡层105;
步骤S26:采用溅射方法沉积约200nm厚的源、漏电极金属Mo/Al,并光刻、刻蚀出所需的源/漏电极106图形;
步骤S27:采用CVD方法沉积约100~500nm厚的SiO2,形成钝化层107。另外,还需要在所述钝化层107上进行光刻、刻蚀出连接孔,用于后续显示面板工艺的进行。
通过以上步骤,有源层包含非晶/单晶/非晶半导体薄膜的薄膜晶体管的制备完成。
上述薄膜晶体管的有源层104包含的三层结构中中间的半导体薄膜为单晶态上下两层为非晶态(a-IGZO/c-IGZO/a-IGZO)。请参考图5,该种结构下,上下两层的非晶半导体薄膜的能带与中间层单晶半导体薄膜的能带形成量子阱,因c-IGZO为n型半导体,上下a-IGZO层向其提供载流子,通过精确控制量子阱的宽度(即c-IGZO层的厚度),可将载流子束缚在该量子阱中,又因c-IGZO层为单晶态,载流子在传输过程中受到较小的阻碍,因而迁移率能够得到提升,这样就得到了迁移率较高的n型TFT器件。该中结构的TFT器件的载流子迁移率理论上可从10cm2V-1s-1提升至50cm2V-1s-1。
TFT器件制备结束后,可在其上溅射沉积ITO电极,并光刻、刻蚀出像素区或亚像素区图形,最终形成显示面板的阵列基板。如果是制作OLED显示设备,则继续旋涂沉积亚克力系材料并光刻、固化出约1.5um厚的像素界定层,最终形成OLED显示器件的背板。
实施例三
请参考图6,图6为本发明实施例三的薄膜晶体管的结构示意图,实施例中的薄膜晶体管与实施例一的薄膜晶体管相比不同之处在于:所述有源层104包括两层半导体薄膜。
实施例三的有源层104的两层半导体薄膜可以全部为单晶半导体薄膜、或者一层为单晶半导体薄膜一层为非晶半导体薄膜。
下面以有源层104的两层半导体薄膜为非晶/单晶半导体薄膜为例,对实施例三的薄膜晶体管的制备方法进行说明。
(3)有源层包含非晶/单晶半导体薄膜的薄膜晶体管的制备方法
所述制备方法包括以下步骤:
步骤S31:提供一衬底101,并采用标准方法清洗;
可选地,可以在衬底101上沉积缓冲层108,具体地,可以采用化学气相沉积(CVD)方法在衬底101上沉积200纳米(nm)厚的SiO2薄膜作为缓冲层108;本实施例中,未沉积缓冲层108;
步骤S32:采用溅射方法在衬底101上沉积200nm厚的栅极金属Mo,并光刻、刻蚀出所需的栅电极102的图形;
步骤S33:在370摄氏度下采用CVD方法在栅电极102上沉积150nm厚的SiO2作为栅绝缘层103;
步骤S34:
采用溅射方法在栅绝缘层103上沉积约10nm后的IGZO非晶薄膜,沉积过程中气体氛围的氧含量可以为10%~80%;
采用MBE方法在IGZO非晶薄膜上沉积约20nm厚的Cu2O单晶薄膜,沉积过程中气体氛围的氧含量可以为10%~80%;
进行光刻、刻蚀出所需的有源层104(即TFT的沟道区)图形;
步骤S35:在有源层104上沉积约50nm厚的SiO2,并光刻、刻蚀出刻蚀阻挡层105;
步骤S36:采用溅射方法沉积约200nm厚的源、漏电极金属Mo/Al,并光刻、刻蚀出所需的源/漏电极106图形;
步骤S37:采用CVD方法沉积约100~500nm厚的SiO2,形成钝化层107。另外,还需要在所述钝化层107上进行光刻、刻蚀出用于连接孔,用于后续显示面板工艺的进行。
通过以上步骤,有源层包含非晶/单晶半导体薄膜的薄膜晶体管的制备完成。
上述薄膜晶体管的有源层104包含的两层结构中一层为非晶态、一层为单晶态(a-IGZO/c-Cu2O)。该TFT器件原理上可实现双型沟道导电。
TFT器件制备结束后,可在其上溅射沉积ITO电极,并光刻、刻蚀出像素区或亚像素区图形,最终形成显示面板。
实施例四
请参考图7,图7为本发明实施例四的薄膜晶体管的结构示意图,实施例中的薄膜晶体管与实施例一的薄膜晶体管相比不同之处在于:所述有源层104包括五层半导体薄膜。
实施例四中的有源层104的五层半导体薄膜可以全部为单晶半导体薄膜、或者部分为单晶半导体薄膜部分为非晶半导体薄膜。该种具有厚度周期性结构的薄膜晶体管也称为超晶格结构的薄膜晶体管。
下面以有源层104的五层半导体薄膜全部为单晶半导体薄膜为例,对实施例四的薄膜晶体管的制备方法进行说明。
(4)有源层包含五层单晶半导体薄膜的薄膜晶体管的制备方法
所述制备方法包括以下步骤:
步骤S41:提供一衬底101,并采用标准方法清洗;
可选地,可以在衬底101上沉积缓冲层108,具体地,可以采用化学气相沉积(CVD)方法在衬底101上沉积200纳米(nm)厚的SiO2薄膜作为缓冲层108;本实施例中,未沉积缓冲层108;
步骤S42:采用溅射方法在衬底101上沉积200nm厚的栅极金属Mo,并光刻、刻蚀出所需的栅电极102的图形;
步骤S43:在370摄氏度下采用CVD方法在栅电极102上沉积150nm厚的SiO2作为栅绝缘层103;
步骤S44:
采用金属有机化学气相沉积(MOCVD)方法在栅绝缘层103上沉积约10nm后的IGZO薄膜,沉积过程中气体氛围的氧含量可以为10%~80%;
采用分子束外延生长(MBE)方法在IGZO薄膜上沉积约10nm厚的氧化亚铜(Cu2O)薄膜,沉积过程中气体氛围的氧含量可以为10%~80%;
如此交叠沉积形成如下五层半导体薄膜结构:IGZO10nm/Cu2O10nm/IGZO10nm/Cu2O10nm/IGZO10nm;
进行光刻、刻蚀出所需的有源层104(即TFT的沟道区)图形;
步骤S45:在有源层104上沉积约50nm厚的SiO2,并光刻、刻蚀出刻蚀阻挡层105;
步骤S46:采用溅射方法沉积约200nm厚的源、漏电极金属Mo/Al,并光刻、刻蚀出所需的源/漏电极106图形;
步骤S47:采用CVD方法沉积约100~500nm厚的SiO2,形成钝化层107。另外,还需要在所述钝化层107上进行光刻、刻蚀出连接孔,用于后续显示面板工艺的进行。
通过以上步骤,有源层包含五层单晶半导体薄膜的薄膜晶体管的制备完成。
TFT器件制备结束后,可在其上溅射沉积ITO电极,并光刻、刻蚀出像素区或亚像素区图形;最后旋涂沉积亚克力系材料并光刻、固化出约1.5um厚的像素界定层,最终形成显示面板。
通过上述实施例可见,本发明实施例的薄膜晶体管中有源层的半导体薄膜的层数可为:
1)双层结构,包括同质结构和异质结构;
2)三层结构;
3)三层以上结构。
各半导体薄膜的厚度需要通过量子计算来确定,以实现载流子的约束。通常情况下,位于中间层的半导体薄膜的厚度需要精确控制。
其中,有源层的各层半导体薄膜的材料可为:
1)多层结构全部为同一种材料的金属氧化物半导体;
2)多层结构全部为同一种材料的单质元素半导体,如Si等;
3)多层结构全部为同一种材料的非氧化物的化合物半导体,如II-VI族半导体等;
4)多层结构分别为不同材料的半导体。
此外,有源层的各层半导体薄膜可以为单晶态,也可以为非晶态:
1)多层结构全部为单晶半导体薄膜;
2)多层结构全部为非晶半导体薄膜;
3)多层结构同时包含单晶半导体薄膜和非晶半导体薄膜。
上述实施例中,均以底栅结构(即栅电极在有源层的下方)的TFT为例进行说明,可以理解的是,在本发明的其他实施例中,TFT也可为其他结构,具体可以包括:
1)底栅结构;
2)顶栅结构(栅极在有源层的上方);
3)交叠型或反交叠型结构(栅极和源漏电极分别在有源层的两侧);
4)共面型或反共面型结构(栅极和源漏电极在有源层的同侧)。
本发明实施例的TFT可以为n型导电的TFT,p型导电的TFT,或者双型导电的TFT。
另外,上述薄膜晶体管的制备方法中有源层的沉积工艺并不限定,具体的,可以采用:
1)MOCVD或MBE沉积单晶半导体薄膜;
2)PECVD方法或Sputter工艺沉积中间有源层。
3)其他工艺方法沉积,如溶液淀积法等。
本发明实施例还提供一种阵列基板,包括上述薄膜晶体管。
本发明实施例还提供一种显示装置,包括上述阵列基板。具体地,所述显示装置可以为显示面板、液晶电视、手机、液晶显示器等。
以上所述是本发明的优选实施方式,应当指出,对于本技术领域的普通技术人员来说,在不脱离本发明所述原理的前提下,还可以作出若干改进和润饰,这些改进和润饰也应视为本发明的保护范围。
Claims (10)
1.一种薄膜晶体管,包括:栅电极、栅绝缘层、有源层、源电极及漏电极;其特征在于,所述有源层包括至少两层半导体薄膜,所述至少两层半导体薄膜包括至少一层单晶半导体薄膜。
2.如权利要求1所述的薄膜晶体管,其特征在于,所述至少两层半导体薄膜为同一种半导体材料。
3.如权利要求1所述的薄膜晶体管,其特征在于,所述至少两层半导体薄膜为不同种半导体材料。
4.如权利要求2或3所述的薄膜晶体管,其特征在于,所述半导体材料为金属氧化物半导体、单质元素半导体或非氧化物的化合物半导体。
5.如权利要求1所述的薄膜晶体管,其特征在于,所述至少两层半导体薄膜全部为单晶半导体薄膜、或者同时包含单晶半导体薄膜和非晶半导体薄膜。
6.如权利要求5所述的薄膜晶体管,其特征在于,所述至少两层半导体薄膜包括依次设置的非晶铟镓锌氧化物薄膜、单晶铟镓锌氧化物薄膜和非晶铟镓锌氧化物薄膜。
7.如权利要求5所述的薄膜晶体管,其特征在于,所述至少两层半导体薄膜包括依次设置的单晶铟镓锌氧化物薄膜、单晶氧化亚铜薄膜和单晶铟镓锌氧化物薄膜。
8.如权利要求5所述的薄膜晶体管,其特征在于,所述至少两层半导体薄膜包括依次设置的非晶铟镓锌氧化物薄膜和单晶氧化亚铜薄膜。
9.一种阵列基板,其特征在于,包括权利要求1-8任一项所述的薄膜晶体管。
10.一种显示装置,其特征在于,包括权利要求9所述的阵列基板。
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WO2017049862A1 (zh) * | 2015-09-23 | 2017-03-30 | 京东方科技集团股份有限公司 | Tft及其制作方法、阵列基板及显示装置 |
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