WO2015003466A1 - 一种阵列基板、显示装置及阵列基板的制备方法 - Google Patents

一种阵列基板、显示装置及阵列基板的制备方法 Download PDF

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Publication number
WO2015003466A1
WO2015003466A1 PCT/CN2013/089787 CN2013089787W WO2015003466A1 WO 2015003466 A1 WO2015003466 A1 WO 2015003466A1 CN 2013089787 W CN2013089787 W CN 2013089787W WO 2015003466 A1 WO2015003466 A1 WO 2015003466A1
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Prior art keywords
electrode
layer
forming
array substrate
data line
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PCT/CN2013/089787
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English (en)
French (fr)
Inventor
孙建
李成
安星俊
柳奉烈
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京东方科技集团股份有限公司
鄂尔多斯市源盛光电有限责任公司
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Priority to US14/360,541 priority Critical patent/US9559125B2/en
Publication of WO2015003466A1 publication Critical patent/WO2015003466A1/zh
Priority to US15/372,228 priority patent/US9735182B2/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78633—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a light shield
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor
    • H01L29/78675—Polycrystalline or microcrystalline silicon transistor with normal-type structure, e.g. with top gate

Definitions

  • Embodiments of the present invention relate to the field of display technologies, and in particular, to an array substrate, a display device, and a method for preparing an array substrate. Background technique
  • LCD Liquid Crystal Display
  • a more common liquid crystal display device is a liquid crystal display device of a twisted nematic (TN) display type.
  • TN twisted nematic
  • ADS advanced Super-dimensional field conversion
  • a relatively mature technology is a thin film transistor liquid crystal display device (TFT-LCD), and the liquid crystal display device includes an array substrate and a color filter substrate, wherein the thin film transistor is formed in On the array substrate, the thin film transistor includes a gate electrode, a source electrode and a drain electrode, and the thin film transistor is usually formed of an amorphous silicon (a-Si) material.
  • a-Si amorphous silicon
  • a source region is formed by using a polysilicon (P-Si) material, and then the active region is crystallized and ion-implanted to form a source electrode and a drain electrode of the thin film transistor.
  • P-Si polysilicon
  • Polycrystalline silicon includes high-temperature polysilicon and low-temperature polysilicon.
  • thin film transistors formed by low-temperature polysilicon have high electron mobility and can reduce the size of thin film transistors, so they are widely used in array substrates, achieving high aperture ratio and enabling
  • the corresponding display device has the advantages of high brightness and low power consumption.
  • a thin film transistor formed using a low-temperature polysilicon material has a relatively large leakage current when operating, and therefore, in order to reduce leakage Current, as shown in a schematic structural diagram of the array substrate in FIG. 1, a light shielding metal layer 3 is disposed under the active region 4 of the array substrate 1 corresponding to the thin film transistor, and the light shielding metal layer 3 will be irradiated to the drain electrode 7 and the source. A part of the light between the electrodes 6 is shielded to reduce the leakage current; or, in the process of forming the drain electrode 7 and the source electrode 6, an ion implantation method (also referred to as an ion doping method) is employed in the active region 4.
  • the lightly doped drain 8 is provided; or, the thin film transistor is set to a double gate structure (having two gate electrodes 5 in FIG. 1), etc., to reduce the leakage current to some extent.
  • an array substrate using a thin film transistor formed of a polysilicon material requires a greater number of patterning processes during preparation, as in the preparation of the array substrate in FIGS. 2a to 2j.
  • steps P1 - P10 in order to form the light-shielding metal layer 3 for reducing the leakage current of the thin film transistor, it is necessary to increase the patterning process of the light-shielding metal layer 3 (such as step P1) during the preparation of the array substrate. Process, plus the original patterning process of other layers in the preparation process of the array substrate, such as the patterning process for preparing the data line 2
  • step P6 a patterning process for preparing the common electrode 12 (step P8), a patterning process for preparing the pixel electrode 14 (step P10), and preparing for forming a data line in the gate insulating layer 10 and the intermediate dielectric layer 11.
  • step P5, P7, and P9 wherein Since the data line 2 and the common electrode 12 must be insulated from each other, and the two overlap or intersect in the forward projection direction, the flat layer 20 which is insulated between the two is indispensable, correspondingly, the patterning process of the fifth via 19 in which the electrical connection between the pixel electrode 14 and the drain electrode 7 is formed in the flat layer 20 is also indispensable), resulting in the number of patterning processes for preparing the array substrate using the polysilicon material. More, so that the respective array substrate preparation step variety, prepared low efficiency.
  • Step P2 the patterning process for preparing the gate insulating layer 10 and the gate electrode 5 shown in Fig. 2c (step P3), the preparation of the source electrode 6, the drain electrode 7, and the light doping shown in Fig. 2d
  • step P4 of the hetero-drain 8 and the like are the same as the corresponding patterning process described in detail below; and the same reference numerals always represent the same components. Summary of the invention
  • the embodiments of the present invention provide an array substrate, a display device, and a method for preparing an array substrate according to the above technical problems existing in the prior art.
  • the array substrate is formed on the substrate by the same layer in the same step, thereby reducing the number of patterning processes of the array substrate and improving the preparation efficiency of the array substrate.
  • the array substrate includes a substrate and a data line and a scan line disposed on the substrate.
  • the data line and the scan line enclose a plurality of pixel regions, and each of the pixel regions is provided with a thin film transistor including a gate electrode, a source electrode, and a leakage current.
  • a gate electrode is disposed above the active region, and the source electrode and the drain electrode are disposed on opposite sides of the active region, and each of the pixel regions is further provided with a light shielding metal layer, the light shielding metal layer and the data line are the same
  • the layer is disposed on the substrate, the light shielding metal layer is disposed under the active region and at least partially overlaps the active region in the projection direction, the data line is adjacent to the source electrode and does not at least partially overlap the active region in the projection direction.
  • the light-shielding metal layer and the data line are formed using the same conductive material.
  • the active region is formed using a low temperature polysilicon material, and the source and drain electrodes are formed on opposite sides of the active region by ion implantation.
  • the light shielding metal layer is disposed between the regions corresponding to the source and drain electrodes and at least partially overlaps the gate electrode in the projection direction.
  • a lightly doped drain is disposed in the active region, and a lightly doped drain is disposed between the source electrode and the drain electrode, and is disposed on both sides of the corresponding region of the gate electrode.
  • the array substrate further includes a buffer layer disposed under the active region and above the substrate, and the light shielding metal layer and the data line are covered by the buffer layer.
  • the position of the light-shielding metal layer is set corresponding to the position of the gate electrode.
  • the array substrate further includes a gate insulating layer disposed above the active region and below the gate electrode, and the active region and the buffer layer are covered by the gate insulating layer.
  • the array substrate further includes an intermediate dielectric layer, a first electrode, a passivation layer, and a second electrode disposed sequentially above the gate electrode, the second electrode and the first electrode at least partially overlapping in a projection direction, and the first electrode is a plate Shape or slit shape, the second electrode is slit-shaped;
  • the buffer layer, the gate insulating layer and the intermediate dielectric layer are provided with a first via hole at a position corresponding to the data line, and the gate insulating layer and the intermediate dielectric layer are provided with a second via hole corresponding to the source electrode, the data line and The source electrode is electrically connected through the first via and the second via.
  • the first electrode is a pixel electrode
  • the second electrode is a common electrode
  • the gate insulating layer and the intermediate dielectric layer are provided with a third via hole at a position corresponding to the drain electrode, and the pixel electrode and the drain electrode are electrically connected through the third via hole.
  • the first electrode is a common electrode
  • the second electrode is a pixel electrode
  • the gate insulating layer and the intermediate dielectric layer are provided with a third via hole at a position corresponding to the drain electrode, and the passivation layer is opened at a position corresponding to the drain electrode.
  • the fourth via, the pixel electrode and the drain electrode are electrically connected through the third via and the fourth via.
  • the array substrate further includes a pixel electrode, the pixel electrode is disposed above the gate insulating layer, and the gate insulating layer is provided with a third via hole at a position corresponding to the drain electrode, and the pixel electrode and the drain electrode are electrically connected through the third via hole;
  • the gate insulating layer and the buffer layer are provided with a first via hole at a position corresponding to the data line, and the gate insulating layer is provided with a second via hole at a position corresponding to the source electrode, and the data line and the source electrode pass through the first via hole and the second pass The holes are electrically connected.
  • Embodiments of the present invention also provide a display device including the above array substrate.
  • the embodiment of the invention further provides a method for preparing an array substrate, comprising the steps of forming a data line, a scan line, a light shielding metal layer on the substrate, and forming a thin film transistor, comprising forming a gate electrode, a source electrode, and a drain electrode.
  • a step of forming an active region in which the thin film transistor and the light shielding metal layer are both formed in a plurality of pixel regions surrounded by the scan line and the data line, the light shielding metal layer and the data line being The same layer is formed on the substrate in the same step, the light shielding metal layer is formed under the active region, and at least partially in the projection direction and the active region Overlap, the data line is adjacent to the source electrode and does not at least partially overlap the active region in a projection direction.
  • the step of forming a data line, a scan line, and a light shielding metal layer on the substrate includes:
  • the step of forming a thin film transistor includes:
  • a buffer layer and a pattern including the active region on the substrate Forming a buffer layer and a pattern including the active region on the substrate forming a pattern of a data line and a light-shielding metal layer; the buffer layer covering the light-shielding metal layer and the data line, the active region a pattern formed on the buffer layer, and a pattern of the active region at least partially overlapping the light-shielding metal layer in a projection direction; forming a gate insulating layer and a pattern including the gate electrode on the substrate, a pattern of the gate electrode is formed above a position corresponding to a position of the gate insulating layer and the light shielding metal layer;
  • the source electrode and the drain electrode are formed on the substrate, and the source electrode and the drain electrode are formed on opposite sides of the active region by ion implantation.
  • the preparation method further includes the step of forming a pattern including a first electrode and a second electrode, the first electrode is a pixel electrode, the second electrode is a common electrode, and the forming includes a first electrode and a second
  • the step of patterning the electrode includes: forming an intermediate dielectric layer on the substrate and a pattern including the first via, the second via, and the third via, wherein: the first via is formed corresponding to a position of the data line extending through the buffer layer, the gate insulating layer, and the intermediate dielectric layer, the second via being formed at a position corresponding to the source electrode and penetrating the gate insulating layer and the An intermediate dielectric layer, the third via hole is formed at a position corresponding to the drain electrode and penetrates the gate insulating layer and the intermediate dielectric layer;
  • the passivation layer and a pattern including the common electrode are formed on the substrate, the passivation layer completely covering the pixel electrode, and a pattern of the common electrode is formed over the passivation layer.
  • the preparation method further includes the step of forming a pattern including the first electrode and the second electrode, the first electrode being a common electrode, the second electrode being a pixel electrode, the forming including the first electrode and the second
  • the step of patterning the electrode includes: forming an intermediate dielectric layer on the substrate and a pattern including the first via, the second via, and the third via, wherein: the first via is formed corresponding to a position of the data line extending through the buffer layer, the gate insulating layer, and the intermediate dielectric layer, the second via being formed at a position corresponding to the source electrode and penetrating the gate insulating layer and the An intermediate dielectric layer, the third via hole is formed at a position corresponding to the drain electrode and penetrates the gate insulating layer and the intermediate dielectric layer;
  • the manufacturing method further includes the step of forming a pixel electrode: forming a pattern including a first via, a second via, and a third via on the substrate, wherein: the first via is formed in correspondence Positioning the data line through the buffer layer and the gate insulating layer, the second via hole is formed at a position corresponding to the source electrode and penetrates the gate insulating layer, and the third via hole is formed At a position corresponding to the drain electrode and penetrating the gate insulating layer;
  • the step of forming the source electrode and the drain electrode in the preparation method further includes: forming a lightly doped drain in the active region by ion implantation, and forming the lightly doped drain at the source
  • the electrode and the drain electrode are disposed on opposite sides of a region corresponding to the gate electrode.
  • the positions of the light shielding metal layers are respectively set corresponding to the positions of the gate electrodes.
  • the light shielding metal layer and the data line are formed in the same layer of the array substrate; and in the method for preparing the corresponding array substrate
  • the light-shielding metal layer and the data line are formed by the same patterning process, which reduces the separate patterning process for the data lines compared to the existing method of fabricating the array substrate, and does not necessarily include forming the prior art.
  • the planarization layer included and the process of forming via holes in the planarization layer reduce the total number of patterning processes in the array substrate fabrication method, and improve the fabrication efficiency of the array substrate and the display device.
  • FIG. 1 is a schematic structural view of an array substrate in the prior art
  • FIGS. 2a to 2j are schematic cross-sectional views showing various steps of preparing an array substrate provided by the prior art
  • FIG. 3 is a schematic structural view of an array substrate according to Embodiment 1 of the present invention
  • FIGS. 4a to 4h are schematic cross-sectional views showing steps of preparing the array substrate shown in FIG. 3;
  • FIG. 5 is a schematic structural view of an array substrate in Embodiment 3 of the present invention.
  • FIGS. 6a to 6f are cross-sectional schematic views showing respective steps of preparing the array substrate shown in FIG. 5.
  • the embodiment provides an array substrate.
  • the array substrate includes a substrate 1 and data lines 2 and scan lines (not shown in FIG. 3) disposed on the substrate 1, the data lines 2 and
  • the scan line encloses a plurality of pixel regions, each of which is provided with a thin film transistor including a gate electrode 5, a source electrode 6, a drain electrode 7 and an active region 4, and the gate electrode 5 is disposed in the active region 4
  • the source electrode 6 and the drain electrode 7 are disposed on opposite sides of the active region 4, and each of the pixel regions is further provided with a light shielding metal layer 3, and the light shielding metal layer 3 and the data line 2 are disposed on the substrate 1 in the same layer.
  • the light-shielding metal layer 3 is disposed under the active region 4 and in the forward projection direction (of course, the orthographic projection direction here is a typical embodiment, and may also be a projection manner of other angles, and is not limited to the embodiment.
  • the upper portion is at least partially overlapped with the active region 4, and the data line 2 is close to the source electrode 6 and does not at least partially overlap the active region 4 in the forward projection direction.
  • the light shielding metal layer 3 is disposed between the regions corresponding to the source electrode 6 and the drain electrode 7, and at least partially overlaps the gate electrode 5 in the projection direction.
  • the active region 4 is formed of a low temperature polysilicon material, and the source electrode 6 and the drain electrode 7 are formed on the opposite sides of the active region 4 by ion implantation (e.g., ion implantation of a boron-containing or phosphorus-containing material).
  • the light-shielding metal layer 3 partially overlaps the active region 4, that is, the light-shielding metal layer 3 is disposed between the source electrode 6 and the region corresponding to the drain electrode 7, in order to make the light-shielding metal layer 3 at least partially covered. a portion of the source region 4 such that light illuminating the active region 4 can be partially blocked, thereby reducing leakage of the active region 4.
  • the light-shielding metal layer 3 can also completely overlap the active region 4, so that the light-shielding metal layer 3 completely covers the active region 4, so that the light irradiated to the active region 4 is completely covered, and The leakage current of the active region 4 is further reduced.
  • the light-shielding metal layer 3 and the data line 2 are formed of the same conductive material, so that the light-shielding metal layer 3 and the data line 2 disposed in the same layer can be simultaneously formed by one patterning process; and since the conductive material is opaque, The light-shielding metal layer 3 simultaneously serves to block part of the light that is irradiated to the active region 4, thereby reducing the leakage current of the thin film transistor.
  • the light-doped drain 8 is disposed in the active region 4, and the lightly doped drain 8 is disposed between the source electrode 6 and the drain electrode 7, and is respectively disposed on the gate electrode 5. On both sides of the area.
  • the lightly doped drain 8 can simultaneously function to reduce the leakage current of the thin film transistor.
  • the gate electrode is at least one, and the light shielding metal layer 3 is at least one piece.
  • the gate electrode 5 is provided in such a manner that it can simultaneously reduce the leakage current of the thin film transistor.
  • embodiments of the present invention are not limited thereto, and the number of gate electrodes and light-shielding metal layers may be set as needed.
  • the array substrate further includes a buffer layer 9, and the buffer layer 9 is disposed under the active region 4 and above the substrate 1, and the light shielding metal layer 3 and the data line 2 are completely covered by the buffer layer 9.
  • the buffer layer 9 serves to block impurities contained in the substrate 1 from diffusing into the active region 4 of the thin film transistor, preventing threshold voltage of the thin film transistor and The characteristics such as leakage current have an influence.
  • the buffer layer 9 can be further prevented from causing diffusion of impurities in the substrate 1 by excimer laser annealing, and improving low-temperature polysilicon. The quality of the formed thin film transistor.
  • the array substrate further includes a gate insulating layer 10 and an intermediate dielectric layer 11, a first electrode, a passivation layer 13, and a second electrode disposed above the gate electrode 5; wherein the gate insulating layer 10 is disposed at Above the active region 4 and the gate Below the electrode 5, the active region 4 and the buffer layer 9 are covered by the gate insulating layer 10; the second electrode and the first electrode at least partially overlap in the front projection direction, the first electrode is plate-shaped, and the second electrode is slit-like .
  • the buffer layer 9, the gate insulating layer 10 and the intermediate dielectric layer 11 are provided with a first via 15 at a position corresponding to the data line 2, and the gate insulating layer 10 and the intermediate dielectric layer 11 are at positions corresponding to the source electrode 6.
  • a second via 16 is opened, and the data line 2 and the source electrode 6 are electrically connected through the first via 15 and the second via 16.
  • the first electrode is the common electrode 12
  • the second electrode is the pixel electrode 14
  • the gate insulating layer 10 and the intermediate dielectric layer 11 are provided with a third via 17 at a position corresponding to the drain electrode 7, which is passivated.
  • the layer 13 is provided with a fourth via 18 at a position corresponding to the drain electrode 7, and the pixel electrode 14 and the drain electrode 7 are electrically connected through the third via 17 and the fourth via 18.
  • a flat layer may be disposed between the intermediate dielectric layer 11 and the first electrode, and the flat layer can keep the intermediate dielectric layer flat; of course, the intermediate dielectric layer 11 and the first electrode may not be
  • the flat layer is provided, and this embodiment does not include a flat layer, which enables the thickness of the array substrate to be relatively thin.
  • the first electrode is in the form of a plate, and it is understood that the first electrode may also be in the shape of a slit.
  • the present embodiment further provides a method for fabricating the array substrate, comprising: a step of forming a data line, a scan line, a light shielding metal layer on the substrate, and a step of forming a thin film transistor, wherein forming the thin film transistor comprises a step of forming a gate electrode, a source electrode, a drain electrode, and an active region, wherein the thin film transistor and the light shielding metal layer are both formed in a plurality of pixel regions surrounded by the data line and the scan line, and a light shielding metal
  • the layer and the data line are formed on the substrate in the same step, the light shielding metal layer is formed under the active region and at least partially overlaps the active region in the right projection direction, the data line is close to the source electrode and is in the orthographic projection direction
  • the active areas do not at least partially overlap.
  • the manufacturing method specifically includes: forming a data line, a scan line, and a light-shielding metal layer on the substrate, comprising: Step S1: Referring to FIG. 4a, using the substrate 1 once The patterning process simultaneously forms a pattern including data lines (not shown) and the light-shielding metal layer 3, data The line and the light-shielding metal layer 3 are arranged apart from each other.
  • the patterning process may include only a photolithography process, or may include a photolithography process and an etching step, and may also include other processes for forming a predetermined pattern, such as printing, inkjet, etc.; A process of forming a pattern by using a photoresist, a mask, an exposure machine, or the like in a process of film formation, exposure, development, and the like.
  • the patterning process includes: first, forming (such as sputtering or coating, etc.) a conductive material for forming the data line and the light shielding metal layer 3 on the substrate 1; then, on the conductive material Coating a layer of photoresist; then, exposing the photoresist with a mask provided with a pattern including a data line and a light-shielding metal layer; finally, developing and etching to form a pattern including the data line and the light-shielding metal layer 3. .
  • the preparation process of the film layer formed by the patterning process is the same as that of the above, and will not be described in detail.
  • a step of forming a thin film transistor comprising:
  • Step S2 Referring to FIG. 4b, a buffer layer 9 and a pattern including the active region 4 are formed on the substrate 1 on which the step S1 is completed; the buffer layer 9 completely covers the light-shielding metal layer 3 and the data lines, and the pattern of the active region 4 is formed. On the buffer layer 9, and the pattern of the active region 4 at least partially overlaps the light-shielding metal layer 3 in the projection direction.
  • Step S3 Referring to FIG. 4c, a gate insulating layer 10 and a pattern including the gate electrode 5 are formed on the substrate 1 on which the step S2 is completed, and patterns of the gate electrode 5 are formed on the gate insulating layer 10 and the light shielding metal layer 3, respectively.
  • the position corresponds to the position above.
  • Step S4 Referring to FIG. 4d, source electrode 6 and drain electrode 7 are formed on substrate 1 which is completed in step S3, and source electrode 6 and drain electrode 7 are formed on opposite sides of active region 4 by ion implantation.
  • the preparation method further includes the step of forming a pattern including the first electrode and the second electrode, wherein the first electrode is a common electrode and the second electrode is a pixel electrode, and the forming includes a pattern of the first electrode and the second electrode
  • the steps include:
  • Step S5 ′ Referring to FIG. 4 e , an intermediate dielectric layer 11 and a pattern including the first via 15, the second via 16 and the third via 17 are formed on the substrate 1 completing the step S4, wherein:
  • the via hole 15 is formed at a position corresponding to the data line 2 and penetrates through the buffer layer 9, the gate insulating layer 10, and the intermediate dielectric layer 11, and the second via hole 16
  • a gate hole insulating layer 10 and an intermediate dielectric layer 11 are formed at a position corresponding to the source electrode 6, and a third via hole 17 is formed at a position corresponding to the drain electrode 7 and penetrates the gate insulating layer 10 and the intermediate dielectric layer 11.
  • Step S6' Referring to FIG. 4f, a pattern including the common electrode 12 is formed on the substrate 1 on which the step S5' is completed, and the data line 2 and the source electrode 6 are electrically connected through the first via 15 and the second via 16, The three via holes 17 are simultaneously filled with a conductive material for forming the common electrode 12. In this step, the electrical connection of the data line 2 to the source electrode 6 is realized while forming the pattern of the common electrode 12.
  • Step S7' Referring to FIG. 4g, a passivation layer 13 is formed on the substrate 1 on which the step S6' is completed, and a pattern including the fourth via hole 18 is formed in the passivation layer 13, and the fourth via hole 18 is formed in correspondence The position of the drain electrode 7 is located, and the position of the fourth via hole 18 corresponds to the position of the third via hole 17.
  • Step S8' Referring to Fig. 4h, a pattern including the pixel electrode 14 is formed on the substrate 1 on which the step S7' is completed, and the pixel electrode 14 and the drain electrode 7 are electrically connected through the third via hole 17 and the fourth via hole 18.
  • the step S4 of the preparation method may further include: forming a lightly doped drain 8 in the active region 4 by ion implantation, and forming a lightly doped drain 8 between the source electrode 6 and the drain electrode 7, and They are respectively disposed on both sides of a region corresponding to the gate electrode 5.
  • the light-shielding metal layer 3 formed in the step S1 is two sheets
  • the gate electrodes 5 formed in the step S3 are two
  • the positions of the light-shielding metal layers 3 are respectively provided corresponding to the positions of the gate electrodes 5.
  • the patterning process of the vias can be the same as the patterning process for forming the third vias 17, and no additional process is added (ie, step P7 of the prior art array substrate preparation method is not added (see FIG. 2g). Corresponding composition process).
  • Example 2 The array substrate provided in this embodiment differs from the first embodiment in that the first electrode is a plate-shaped pixel electrode, and the second electrode is a slit-shaped common electrode; correspondingly, in the array substrate, the gate insulating layer
  • the intermediate dielectric layer is provided with a third via hole at a position corresponding to the drain electrode, and the pixel electrode and the drain electrode are electrically connected through the third via hole.
  • the fourth via hole is not required to be formed in the array substrate of the present embodiment.
  • the other structures and materials of the array substrate are the same as those in the first embodiment, and are not described herein again.
  • the present embodiment provides a method for fabricating the array substrate, which is different from the method for fabricating the array substrate in the first embodiment, corresponding to the structure of the array substrate, in the embodiment.
  • the array substrate has no step of opening a fourth via, and the common electrode is formed over the pixel electrode.
  • the step of forming a pattern including the first electrode and the second electrode in the preparation method includes:
  • Step S5 forming an intermediate dielectric layer and a pattern including a first via, a second via, and a third via on the substrate completing step S4, wherein: the first via is formed at a position corresponding to the data line and runs through a buffer layer, a gate insulating layer and an intermediate dielectric layer, the second via hole is formed at a position corresponding to the source electrode and penetrates the gate insulating layer and the intermediate dielectric layer, and the third via hole is formed at a position corresponding to the drain electrode and penetrates the gate Insulation layer and intermediate dielectric layer.
  • Step S6 forming a pattern including the pixel electrode on the substrate of the step S5, the data line and the source electrode are electrically connected through the first via hole and the second via hole, and the pixel electrode and the drain electrode are electrically connected through the third via hole.
  • Step S7 forming a passivation layer and a pattern including a common electrode on the substrate on which the step S6 is completed, the passivation layer completely covering the pixel electrode, and the pattern of the common electrode is formed over the passivation layer.
  • the preparation method of the present embodiment does not include the step corresponding to the step S8'.
  • the other steps of the method for preparing the array substrate provided in the embodiment are the same as those of the embodiment 1, and are not described herein again.
  • the embodiment provides an array substrate.
  • the array substrate includes a substrate 1 and data lines 2 and scan lines (not shown in FIG. 5) disposed on the substrate 1, the data lines 2 and
  • the scan line encloses a plurality of pixel regions, each of which is provided with a thin film transistor including a gate electrode 5, a source electrode 6, a drain electrode 7, and an active region 4, the gate electrode 5 being disposed on the active Above the region 4, the source electrode 6 and the drain electrode 7 are respectively disposed on opposite sides of the active region 4, and each of the pixel regions is further provided with a light shielding metal layer 3, and the light shielding metal layer 3 and the data line 2 are disposed on the substrate 1 in the same layer.
  • the light-shielding metal layer 3 is disposed under the active region 4 and at least partially overlaps the active region 4 in the orthogonal projection direction, the data line 2 is close to the source electrode 6 and is at least partially not in the orthogonal projection direction with the active region 4. overlapping.
  • the array substrate further includes: a lightly doped drain 8, a buffer layer 9, and a gate insulating layer 10.
  • the structure and material of the above array substrate are the same as those of Embodiment 1 or Embodiment 2, and will not be described herein.
  • the array substrate in the embodiment further includes a pixel electrode 14 disposed above the gate insulating layer 10, and the gate insulating layer 10 is opened at a position corresponding to the drain electrode 7.
  • the third via 17 is provided, and the pixel electrode 14 and the drain electrode 7 are electrically connected through the third via 17; the gate insulating layer 10 and the buffer layer 9 are provided with a first via 15 at a position corresponding to the data line 2, and the gate insulating layer 10
  • a second via 16 is opened at a position corresponding to the source electrode 6, and the data line 2 and the source electrode 6 are electrically connected through the first via 15 and the second via 16.
  • the embodiment provides a method for preparing the array substrate, wherein the first four steps of the preparation method (ie, steps S1, S2, S3, and S4, refer to FIG. 6a to FIG. 6d).
  • the method is the same as the first four steps of the method for fabricating the array substrate in the first embodiment or the second embodiment.
  • the method for fabricating the array substrate further includes the step of forming a pixel electrode, as shown in FIGS. 6e to 6f.
  • the steps of forming the pixel electrode include: Step S5": Referring to FIG.
  • a pattern including the first via 15, the second via 16, and the third via 17 is formed on the substrate 1 on which the step S4 is completed, wherein: the first via 15 is formed in correspondence
  • the position of the data line 2 is penetrated through the buffer layer 9 and the gate insulating layer 10.
  • the second via hole 16 is formed at a position corresponding to the source electrode 6 and penetrates the gate insulating layer 10, and the third via hole 17 is formed at the drain electrode 7 corresponding thereto. The position passes through the gate insulating layer 10.
  • Step S6" Referring to FIG. 6f, a pattern including the pixel electrode 14 is formed on the substrate 1 on which the step S5" is completed, and the data line 2 is electrically connected to the source electrode 6 through the first via 15 and the second via 16; The electrode 14 and the drain electrode 7 are electrically connected through the third via hole 17.
  • Embodiment 1 and Embodiment 2 specifically describe an embodiment of the present invention by using an array substrate having an advanced super-dimensional field conversion display mode (ie, ADS display mode) as an example
  • Embodiment 3 is An embodiment of the present invention is specifically described by using an array substrate having a twisted nematic display mode (ie, a TN display mode) as an example.
  • the above embodiments are only several embodiments of the present invention, and the practical application of the present invention. The scope is not limited to this.
  • the ADS (ADvanced Super Dimension Switch) mode is a planar electric field wide viewing angle core technology, and its core technical characteristics are described as: the electric field generated by the edge of the slit electrode in the same plane and the slit electrode layer and the plate
  • the electric field generated between the electrode layers forms a multi-dimensional electric field, so that all the aligned liquid crystal molecules between the slit electrodes in the liquid crystal cell and directly above the electrodes can be rotated, thereby improving the liquid crystal working efficiency and increasing the light transmission efficiency.
  • ADS mode switching technology can improve the picture quality of TFT-LCD products, with high resolution, high transmittance, low power consumption, wide viewing angle, high aperture ratio, low chromatic aberration, and no squeeze water ripple (push Mura).
  • the improved technology of the ADS technology has high transmittance I-ADS technology, high aperture ratio H-ADS and high-resolution S-ADS technology, etc. for different applications.
  • Advantageous Effects of Embodiments of the Invention Provided by Embodiments of the Present Invention In the array substrate, a light shielding metal layer and a data line are formed in the same layer of the array substrate; and in the method for preparing the corresponding array substrate, the light shielding metal layer and the data line are passed The same patterning process (including the exposure process) is formed; in the existing array substrate, the light-shielding metal layer and the data line are not formed in the same patterning process, and the two are not disposed in the same layer of the array substrate, and the reduction is reduced.
  • a separate patterning process for the data lines ie, reducing the patterning process corresponding to the step P6 shown in FIG. 2f of the prior art array substrate fabrication method, thereby reducing the number of patterning processes of the array substrate, and improving the array substrate and The preparation efficiency of the display device.
  • Example 4
  • the embodiment provides a display device comprising the array substrate provided by any of the above embodiments.
  • the display device employs the array substrate described in the above embodiments, the number of patterning processes of the array substrate is reduced, thereby improving the preparation efficiency of the display device.
  • the display device may be: a liquid crystal panel, an electronic paper, an OLED panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigation device, and the like, or any display product or component. It is to be understood that the above embodiments are merely exemplary embodiments employed to explain the principles of the invention, but the embodiments of the invention are not limited thereto. Various modifications and improvements can be made by those skilled in the art without departing from the spirit and scope of the invention, and such modifications and improvements are also considered to be within the scope of the invention.

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Abstract

一种阵列基板、显示装置及阵列基板的制备方法。该阵列基板包括基板（1）以及设置在基板（1）上的数据线（2）和扫描线，数据线（2）和扫描线围成多个像素区域，每个像素区域内设置有薄膜晶体管，薄膜晶体管包括栅电极（5）、源电极（6）、漏电极（7）和有源区（4），栅电极（5）设置在有源区（4）的上方，源电极（6）与漏电极（7）分设在有源区（4）的相对两侧，每个像素区域内还设置有遮光金属层（3），遮光金属层（3）和数据线（2）同层设置在基板（1）上，遮光金属层（3）设置在有源区（4）下方，且在投影方向上与有源区（4）至少部分重叠，数据线（2）靠近源电极（6）且在投影方向上与有源区（4）至少部分不重叠。通过将遮光金属层（3）和数据线（2）在同一步骤中形成在同一层中，减少了阵列基板的构图工艺次数，提高了阵列基板及显示装置的制备效率。

Description

一种阵列基板、 显示装置及阵列基板的制备方法 技术领域
本发明实施例涉及显示技术领域，具体地，涉及一种阵列基 板、 显示装置及阵列基板的制备方法。 背景技术
液晶显示装置 ( Liquid Crystal Display, 简称 LCD) 因其 体积小、功耗低、无辐射等特点已成为目前平板显示装置中的主 流产品。
目前， 较常见的液晶显示装置是扭曲向列型 （Twi sted Nemat ic简称 TN)显示方式的液晶显示装置。 随着显示技术的发 展， 还出现了高级超维场转换 （即 ADvanced Super Dimens ion Switch, 简称 ADS) 显示方式的液晶显示装置。 目前， 在技术上 比较成熟的是薄膜晶体管液晶显示装置 （ Thin Fi lm Trans i stor-Liquid Crystal Di splay , 简称 TFT-LCD) ， 液晶 显示装置包括阵列基板和彩膜基板，其中，薄膜晶体管形成在阵 列基板上， 薄膜晶体管包括栅电极、源电极与漏电极， 薄膜晶体 管通常采用非晶硅 （a-Si ) 材料形成。
随着显示技术的发展， 出现了采用多晶硅（P-Si )材料形成 薄膜晶体管的方式。 具体的， 先采用多晶硅（P-Si )材料形成有 源区，然后对有源区进行晶化以及离子注入， 从而形成薄膜晶体 管的源电极与漏电极。 研究显示， 采用多晶硅（P-Si )材料形成 的薄膜晶体管的性能比采用非晶硅材料形成的薄膜晶体管的性 能高 100多倍。 多晶硅包括高温多晶硅和低温多晶硅， 其中， 采 用低温多晶硅形成的薄膜晶体管具有较高的电子迁移率，还能缩 小薄膜晶体管的尺寸， 因此广泛应用于阵列基板中， 既实现了高 开口率， 又使得相应的显示装置具有高亮度、 低耗电的优点。
与采用非晶硅材料形成的薄膜晶体管相比，采用低温多晶硅 材料形成的薄膜晶体管工作时漏电流比较大， 因此， 为了降低漏 电流， 如图 1中阵列基板的一种结构示意图所示， 在阵列基板 1 对应着薄膜晶体管的有源区 4的下方设置了遮光金属层 3， 遮光 金属层 3将照射到漏电极 7和源电极 6之间的区域的一部分光线 遮住， 从而使漏电流降低； 或者， 在形成漏电极 7 和源电极 6 的过程中采用离子注入法（也称离子掺杂法）在有源区 4中设置 轻掺杂漏极 8; 或者， 将薄膜晶体管设置为双栅极结构 （如图 1 中具有两个栅电极 5 ) 等， 都能从一定程度上降低漏电流。
与采用包括非晶硅材料形成的薄膜晶体管的阵列基板相比， 采用包括多晶硅材料形成的薄膜晶体管的阵列基板在制备时需 要更多次数的构图工艺，如图 2a至图 2j中阵列基板的制备步骤 图 （如步骤 P1-P10) 所示， 为了形成用于降低薄膜晶体管漏电 流的遮光金属层 3， 在阵列基板制备时需增加遮光金属层 3所包 括的曝光工艺 （如步骤 P1 ) 的构图工艺， 加上阵列基板制备过 程中其它膜层原有的构图工艺， 例如制备数据线 2 的构图工艺
(如步骤 P6) 、 制备公共电极 12的构图工艺（如步骤 P8) 、 制 备像素电极 14的构图工艺（如步骤 P10) 以及在栅绝缘层 10和 中间介电层 11中制备用于形成数据线 2和源电极 6之间的电连 接的第一过孔 15的构图工艺 （如步骤 P5 ) 、 在栅绝缘层 10和 中间介电层 11中制备像素电极 14与漏电极 7之间的电连接的第 三过孔 17的构图工艺、 在钝化层 13中制备第四过孔 18的构图 工艺以及在平坦层 20中制备第五过孔 19的构图工艺 （如步骤 P5、 P7和 P9， 其中， 由于数据线 2与公共电极 12之间必须互相 绝缘，而二者在正投影方向上有重叠或说交叉， 因此在二者之间 起绝缘作用的平坦层 20必不可少，相应的，在平坦层 20中形成 像素电极 14与漏电极 7之间的电连接的第五过孔 19的构图工艺 也是必不可少的），导致采用多晶硅材料制备阵列基板的制备方 法构图工艺数量增多，使得相应的阵列基板的制备工序繁多，制 备效率低。 而图 2b所示的制备缓冲层 9和有源区 4的构图工艺
(步骤 P2 ) ， 图 2c所示的制备栅绝缘层 10和栅电极 5的构图 工艺 （步骤 P3 ) ， 图 2d所示的制备源电极 6、 漏电极 7和轻掺 杂漏极 8的构图工艺 （步骤 P4) 等与下文详细描述的对应构图 工艺相同； 并且相同的附图标记始终代表相同的部件。 发明内容
本发明实施例针对现有技术中存在的上述技术问题，提供了 一种阵列基板、显示装置及阵列基板的制备方法。所述阵列基板 通过将遮光金属层和数据线在同一步骤中同层形成在所述基板 上，从而减少了阵列基板的构图工艺次数，提高了阵列基板的制 备效率。
所述阵列基板包括基板以及设置在基板上的数据线和扫描 线，数据线和扫描线围成多个像素区域，每个像素区域内设置有 薄膜晶体管，薄膜晶体管包括栅电极、源电极、漏电极和有源区， 栅电极设置在有源区的上方，源电极和漏电极分设在有源区的相 对两侧，每个像素区域内还设置有遮光金属层，遮光金属层和数 据线同层设置在基板上，遮光金属层设置在有源区下方且在投影 方向上与有源区至少部分重叠，数据线靠近源电极且在投影方向 上与有源区至少部分不重叠。
例如， 遮光金属层和数据线采用相同的导电材料形成。 例如，有源区采用低温多晶硅材料形成，源电极和漏电极采 用离子注入的方式形成在有源区的相对两侧。
例如， 遮光金属层设置在源电极和漏电极对应的区域之间， 且在投影方向上与栅电极至少部分重叠。
例如，有源区中还设置有轻掺杂漏极，轻掺杂漏极设置在源 电极和漏电极之间， 且分别设置在栅电极对应的区域的两侧。
例如， 阵列基板还包括缓冲层，缓冲层设置在有源区的下方 以及基板的上方， 遮光金属层和数据线被缓冲层覆盖。
例如， 遮光金属层的位置与栅电极的位置对应设置。
例如， 阵列基板还包括栅绝缘层，栅绝缘层设置在所述有源 区的上方以及栅电极的下方， 有源区以及缓冲层被栅绝缘层覆 。 例如， 阵列基板还包括依次设置在栅电极上方的中间介电 层、第一电极、钝化层以及第二电极， 第二电极与第一电极在投 影方向上至少部分重叠，第一电极为板状或狭缝状，第二电极为 狭缝状；
缓冲层、栅绝缘层和中间介电层在对应着数据线的位置开设 有第一过孔，栅绝缘层和中间介电层在对应着源电极的位置开设 有第二过孔， 数据线和源电极通过第一过孔以及第二过孔电连 接。
例如， 第一电极为像素电极， 第二电极为公共电极， 栅绝缘 层、中间介电层在对应着漏电极的位置开设有第三过孔，像素电 极和漏电极通过第三过孔电连接；
或者， 第一电极为公共电极， 第二电极为像素电极， 栅绝缘 层、中间介电层在对应着漏电极的位置开设有第三过孔，钝化层 在对应着漏电极的位置开设有第四过孔，像素电极和漏电极通过 第三过孔以及第四过孔电连接。
例如， 阵列基板还包括像素电极，像素电极设置在栅绝缘层 的上方，栅绝缘层在对应着漏电极的位置开设有第三过孔，像素 电极与漏电极通过第三过孔电连接；
栅绝缘层和缓冲层在对应数据线的位置开设有第一过孔，栅 绝缘层在对应着源电极的位置开设有第二过孔，数据线和源电极 通过第一过孔和第二过孔电连接。
本发明实施例还提供一种显示装置，该显示装置包括上述阵 列基板。
本发明实施例还提供一种阵列基板的制备方法，包括在基板 上形成数据线、扫描线、遮光金属层的步骤和形成薄膜晶体管的 步骤， 形成薄膜晶体管包括形成栅电极、源电极、漏电极和有源 区的步骤，所述薄膜晶体管和所述遮光金属层均形成在由所述扫 描线和所述数据线围成的多个像素区域内，所述遮光金属层和所 述数据线在同一步骤中同层形成在所述基板上，所述遮光金属层 形成在所述有源区下方，且在投影方向上与所述有源区至少部分 重叠，所述数据线靠近所述源电极且在投影方向上与所述有源区 至少部分不重叠。
例如， 所述在基板上形成数据线、扫描线、遮光金属层的步 骤包括：
在所述基板上采用一次构图工艺同时形成包括所述数据线 和所述遮光金属层的图形，所述数据线和所述遮光金属层相隔设 置；
所述形成薄膜晶体管的步骤包括：
在形成数据线和遮光金属层的图形的所述基板上形成缓冲 层和包括所述有源区的图形；所述缓冲层覆盖所述遮光金属层和 所述数据线，所述有源区的图形形成在所述缓冲层上，且所述有 源区的图形在投影方向上与所述遮光金属层至少部分重叠； 在所述基板上形成栅绝缘层和包括所述栅电极的图形，所述 栅电极的图形形成在所述栅绝缘层与所述遮光金属层位置对应 的位置的上方；
在所述基板上形成所述源电极和所述漏电极，所述源电极和 所述漏电极采用离子注入方式形成在所述有源区的相对两侧。
例如，所述制备方法还包括形成包括第一电极以及第二电极 的图形的步骤，所述第一电极为像素电极，所述第二电极为公共 电极， 所述形成包括第一电极以及第二电极的图形的步骤包括： 在所述基板上形成中间介电层以及包括第一过孔、第二过孔 以及第三过孔的图形，其中：所述第一过孔形成在对应着所述数 据线的位置并贯穿所述缓冲层、 所述栅绝缘层和所述中间介电 层，所述第二过孔形成在对应着所述源电极的位置并贯穿所述栅 绝缘层和所述中间介电层，所述第三过孔形成在对应着所述漏电 极的位置并贯穿所述栅绝缘层和所述中间介电层；
在所述基板上形成包括所述像素电极的图形，所述像素电极 的图形形成在所述中间介电层的上方，所述数据线与所述源电极 通过所述第一过孔以及所述第二过孔电连接，所述像素电极与所 述漏电极通过所述第三过孔电连接； 在所述基板上形成所述钝化层以及包括所述公共电极的图 形，所述钝化层完全覆盖所述像素电极，所述公共电极的图形形 成在所述钝化层的上方。
例如，所述制备方法还包括形成包括第一电极以及第二电极 的图形的步骤，所述第一电极为公共电极，所述第二电极为像素 电极， 所述形成包括第一电极以及第二电极的图形的步骤包括： 在所述基板上形成中间介电层以及包括第一过孔、第二过孔 以及第三过孔的图形，其中：所述第一过孔形成在对应着所述数 据线的位置并贯穿所述缓冲层、 所述栅绝缘层和所述中间介电 层，所述第二过孔形成在对应着所述源电极的位置并贯穿所述栅 绝缘层和所述中间介电层，所述第三过孔形成在对应着所述漏电 极的位置并贯穿所述栅绝缘层和所述中间介电层；
在所述基板上形成包括所述公共电极的图形，所述公共电极 的图形形成在所述中间介电层的上方，所述数据线与所述源电极 通过所述第一过孔和所述第二过孔电连接，所述第三过孔中同时 填充有用于形成所述公共电极的导电材料；
在所述基板上形成所述钝化层以及在所述钝化层中形成包 括第四过孔的图形，所述第四过孔形成在对应着所述漏电极的位 置， 且所述第四过孔的位置与所述第三过孔的位置相对应； 在所述基板上形成包括像素电极的图形并使所述像素电极 与所述漏电极通过所述第三过孔和所述第四过孔电连接。
例如， 所述制备方法还包括形成像素电极的步骤： 在所述基板上形成包括第一过孔、第二过孔以及第三过孔的 图形，其中：所述第一过孔形成在对应着所述数据线的位置并贯 穿所述缓冲层和所述栅绝缘层，所述第二过孔形成在对应着所述 源电极的位置并贯穿所述栅绝缘层，所述第三过孔形成在对应着 所述漏电极的位置并贯穿所述栅绝缘层；
在所述基板上形成包括所述像素电极的图形，所述像素电极 的图形形成在所述栅绝缘层上，所述数据线通过所述第一过孔和 所述第二过孔与所述源电极电连接；所述像素电极与所述漏电极 通过所述第三过孔电连接。
例如，该制备方法的所述形成源电极和漏电极的步骤中还包 括：采用离子注入方式在所述有源区中形成轻掺杂漏极，所述轻 掺杂漏极形成在所述源电极和所述漏电极之间，且分别设置在所 述栅电极对应的区域的两侧。
例如，所述遮光金属层的位置分别与所述栅电极的位置对应 设置。
本发明实施例的有益效果：本发明实施例所提供的阵列基板 中，所述遮光金属层和所述数据线形成在所述阵列基板的同一层 中；且在相应的阵列基板的制备方法中，所述遮光金属层和所述 数据线通过同一构图工艺形成，与现有的阵列基板的制备方法相 比，减少了对数据线的单独构图工艺， 同时也不必包括形成现有 技术中所必须包括的平坦层以及在平坦层中开设过孔的工艺，从 而减少了阵列基板制备方法中的构图工艺总次数，提高了阵列基 板以及显示装置的制备效率。 附图说明
图 1为现有技术中阵列基板的结构示意图；
图 2a至图 2j为现有技术提供的制备阵列基板的各步骤的剖 视示意图；
图 3为本发明实施例 1中阵列基板的结构示意图； 图 4a至图 4h为制备图 3所示阵列基板的各步骤的剖视示意 图；
图 5为本发明实施例 3中阵列基板的结构示意图； 图 6a至图 6f为制备图 5所示阵列基板的各步骤的剖视示意 图。
其中的附图标记说明：
1.基板； 2.数据线； 3.遮光金属层； 4.有源区； 5.栅电极； 6.源电极； 7.漏电极； 8.轻掺杂漏极； 9.缓冲层； 10.栅绝缘层； 11.中间介电层； 12.公共电极； 13.钝化层； 14.像素电极； 15. 第一过孔； 16.第二过孔； 17.第三过孔； 18.第四过孔； 19.第五 过孔； 20.平坦层。 具体实施方式
为使本领域的技术人员更好地理解本发明实施例的技术方 案，下面结合附图和具体实施方式对本发明的阵列基板、显示装 置及阵列基板的制备方法作进一步详细描述。 实施例 1 :
本实施例提供一种阵列基板，如图 3所示，所述阵列基板包 括基板 1以及设置在基板 1上的数据线 2和扫描线（图 3中未示 出）， 所述数据线 2和所述扫描线围成多个像素区域， 每个像素 区域内设置有薄膜晶体管，薄膜晶体管包括栅电极 5、源电极 6、 漏电极 7和有源区 4， 栅电极 5设置在有源区 4的上方， 源电极 6与漏电极 7分设在有源区 4的相对两侧， 每个像素区域内还设 置有遮光金属层 3， 遮光金属层 3和数据线 2同层设置在基板 1 上，遮光金属层 3设置在有源区 4下方，且在正投影方向（当然， 此处的正投影方向是一种典型的实施方式，也可以是其他角度的 投影方式， 并不限于本实施例所述方式）上与有源区 4至少部分 重叠，数据线 2靠近源电极 6且在正投影方向上与有源区 4至少 部分不重叠。
其中，遮光金属层 3设置在源电极 6与漏电极 7对应的区域 之间，且在投影方向上分别与所述栅电极 5至少部分重叠。有源 区 4采用低温多晶硅材料形成，源电极 6与漏电极 7采用离子注 入的方式（如离子注入含硼或含磷材料）形成在有源区 4的相对 两侧。
本实施例中，遮光金属层 3与有源区 4部分重叠， 即遮光金 属层 3设置在源电极 6与漏电极 7对应的区域之间，目的是为了 使遮光金属层 3至少要遮住有源区 4的一部分区域，从而使照射 到有源区 4的光线能够被遮住一部分，进而降低有源区 4的漏电 流； 当然， 遮光金属层 3也可以与有源区 4完全重叠， 这样， 遮 光金属层 3就将有源区 4完全遮住，从而使照射到有源区 4的光 线被全部遮住， 能够更进一步地降低有源区 4的漏电流。
其中， 遮光金属层 3和数据线 2采用相同的导电材料形成， 使得设置在同一层中的遮光金属层 3和数据线 2可以通过一次构 图工艺同时形成； 且由于该导电材料不透光， 所以遮光金属层 3 同时起到遮住照射到有源区 4的部分光线，从而降低薄膜晶体管 的漏电流的作用。
例如， 在本实施例中， 有源区 4中还设置有轻掺杂漏极 8， 轻掺杂漏极 8设置在源电极 6与漏电极 7之间，且分别设置在栅 电极 5对应的区域的两侧。在本实施例中，轻掺杂漏极 8能够同 时起到降低薄膜晶体管的漏电流的作用。
其中， 栅电极为至少一个， 遮光金属层 3为至少一片。在本 实施例中， 栅电极 5为两个， 遮光金属层 3为两片， 遮光金属层 3的位置分别与栅电极 5的位置对应设置。 在本实施例中， 栅电 极 5设置为两个可以同时起到减小薄膜晶体管的漏电流的作用。 但是，本发明实施例不限于此，可以根据需要设置栅电极和遮光 金属层的数量。
在本实施例中， 阵列基板还包括缓冲层 9， 缓冲层 9设置在 有源区 4的下方以及基板 1 的上方， 遮光金属层 3和数据线 2 被缓冲层 9完全覆盖。由于本实施例中有源区 4采用低温多晶硅 材料形成，因此所述缓冲层 9用于阻挡基板 1中所含的杂质扩散 进入薄膜晶体管的有源区 4中，防止对薄膜晶体管的阈值电压和 漏电流等特性产生影响； 同时， 由于低温多晶硅通常是用准分子 激光退火的方法形成在基板 1上，因此设置缓冲层 9能进一步防 止准分子激光退火造成基板 1中的杂质扩散，提高低温多晶硅形 成的薄膜晶体管的质量。
在本实施例中， 阵列基板还包括栅绝缘层 10以及依次设置 在栅电极 5上方的中间介电层 11、 第一电极、 钝化层 13以及第 二电极； 其中， 栅绝缘层 10设置在所述有源区 4的上方以及栅 电极 5的下方， 有源区 4以及缓冲层 9被栅绝缘层 10覆盖； 第 二电极与第一电极在正投影方向上至少部分重叠，第一电极为板 状， 第二电极为狭缝状。 此外， 缓冲层 9、 栅绝缘层 10和中间 介电层 11在对应着数据线 2的位置开设有第一过孔 15， 栅绝缘 层 10和中间介电层 11在对应着源电极 6的位置开设有第二过孔 16，数据线 2和源电极 6通过第一过孔 15以及第二过孔 16电连 接。
在本实施例中， 第一电极为公共电极 12， 第二电极为像素 电极 14，栅绝缘层 10、中间介电层 11在对应着漏电极 7的位置 开设有第三过孔 17， 钝化层 13在对应着漏电极 7的位置开设有 第四过孔 18， 像素电极 14与漏电极 7通过第三过孔 17以及第 四过孔 18电连接。
需要说明的是， 在中间介电层 11以及第一电极之间还可以 设置平坦层， 平坦层能使得中间介电层保持平坦； 当然， 中间介 电层 11以及第一电极之间也可以不设置平坦层， 本实施例不包 括平坦层， 这能使阵列基板的厚度相对较薄。在本实施例中， 第 一电极为板状， 可以理解的是， 第一电极还可以为狭缝状。
对于上述阵列基板，本实施例还提供了一种该阵列基板的制 备方法， 包括： 在基板上形成数据线、 扫描线、 遮光金属层的步 骤和形成薄膜晶体管的步骤，形成所述薄膜晶体管包括形成栅电 极、源电极、漏电极和有源区的步骤， 所述薄膜晶体管和所述遮 光金属层均形成在由所述数据线和所述扫描线围成的多个像素 区域内， 遮光金属层和数据线在同一步骤中同层形成在基板上， 遮光金属层形成在有源区下方且在正投影方向上与有源区至少 部分重叠，数据线靠近源电极且在正投影方向上与有源区至少部 分不重叠。
如图 4a至图 4h所示， 所述制备方法具体包括： 在基板上形成数据线、扫描线、遮光金属层的步骤，其包括： 步骤 S1 : 参照图 4a所示， 在基板 1上采用一次构图工艺同 时形成包括数据线（图中未示出）和遮光金属层 3的图形， 数据 线和遮光金属层 3相隔设置。
其中， 所述构图工艺， 可只包括光刻工艺， 或， 包括光刻工 艺以及刻蚀步骤， 同时还可以包括打印、喷墨等其他用于形成预 定图形的工艺； 光刻工艺， 是指包括成膜、 曝光、 显影等工艺过 程的利用光刻胶、 掩模板、 曝光机等形成图形的工艺。
在本实施例中， 所述构图工艺包括： 首先， 在基板 1上形成 (如溅射或涂覆等）一层用于形成数据线和遮光金属层 3的导电 材料； 接着， 在导电材料上涂覆一层光刻胶； 然后， 用设置有包 括数据线和遮光金属层的图形的掩模板对光刻胶进行曝光；最后 经显影、刻蚀后形成包括数据线和遮光金属层 3的图形。本实施 例阵列基板的制备方法中，涉及到通过构图工艺形成的膜层的制 备工艺与此相同， 不再详细赘述。
形成薄膜晶体管的步骤， 其包括：
步骤 S2 : 参照图 4b所示， 在完成步骤 S1的基板 1上形成 缓冲层 9和包括有源区 4的图形；缓冲层 9完全覆盖遮光金属层 3和数据线， 有源区 4的图形形成在缓冲层 9上， 且有源区 4的 图形在投影方向上与遮光金属层 3至少部分重叠。
步骤 S3 : 参照图 4c所示， 在完成步骤 S2的基板 1上形成 栅绝缘层 10和包括栅电极 5的图形， 栅电极 5的图形分别形成 在栅绝缘层 10的与所述遮光金属层 3位置对应的位置的上方。
步骤 S4: 参照图 4d所示， 在完成步骤 S3的基板 1上形成 源电极 6与漏电极 7， 源电极 6与漏电极 7采用离子注入方式形 成在有源区 4的相对两侧。
所述制备方法还包括形成包括第一电极以及第二电极的图 形的步骤， 其中， 第一电极为公共电极， 第二电极为像素电极， 所述形成包括第一电极以及第二电极的图形的步骤包括：
步骤 S5 ' ： 参照图 4e所示， 在完成步骤 S4的基板 1上形 成中间介电层 11以及包括第一过孔 15、 第二过孔 16以及第三 过孔 17的图形，其中：第一过孔 15形成在对应着数据线 2的位 置并贯穿缓冲层 9、 栅绝缘层 10和中间介电层 11， 第二过孔 16 形成在对应着源电极 6的位置并贯穿栅绝缘层 10和中间介电层 11， 第三过孔 17形成在对应着漏电极 7的位置并贯穿栅绝缘层 10和中间介电层 11。
步骤 S6 ' ：参照图 4f所示， 在完成步骤 S5 ' 的基板 1上形 成包括公共电极 12的图形， 数据线 2与源电极 6通过第一过孔 15以及第二过孔 16电连接， 第三过孔 17中同时填充有用于形 成公共电极 12 的导电材料。 在该步骤中， 在形成公共电极 12 的图形的同时， 实现了数据线 2与源电极 6的电连接。
步骤 S7 ' ：参照图 4g所示，在完成步骤 S6' 的基板 1上形 成钝化层 13以及在钝化层 13中形成包括第四过孔 18的图形， 第四过孔 18形成在对应着漏电极 7的位置，且第四过孔 18的位 置与第三过孔 17的位置相对应。
步骤 S8 ' ：参照图 4h所示，在完成步骤 S7' 的基板 1上形 成包括像素电极 14的图形，像素电极 14与漏电极 7通过第三过 孔 17以及第四过孔 18电连接。
例如， 该制备方法的步骤 S4还可以进一步包括： 采用离子 注入方式在有源区 4中形成轻掺杂漏极 8， 轻掺杂漏极 8形成在 源电极 6与漏电极 7之间，且分别设置在栅电极 5对应的区域的 两侧。
例如， 在步骤 S1中形成的遮光金属层 3为两片， 在步骤 S3 中形成的栅电极 5为两个， 遮光金属层 3的位置分别与栅电极 5 的位置对应设置。
作为与阵列基板的一种优选结构对应的制备方法，当在中间 介电层 11以及第一电极之间形成平坦层时， 在平坦层中形成像 素电极 14与漏电极 7之间的电连接的过孔的构图工艺可以与形 成第三过孔 17的构图工艺为同一个， 并不会增加额外的工艺过 程 （即不会增加与现有技术的阵列基板制备方法的步骤 P7 (参 见图 2g) 相对应的构图工艺） 。 实施例 2 : 本实施例所提供的阵列基板，与实施例 1不同的是：第一电 极为板状的像素电极， 第二电极为狭缝状的公共电极； 相应的， 在该阵列基板中，栅绝缘层、中间介电层在对应着漏电极的位置 开设有第三过孔，像素电极与漏电极通过第三过孔电连接。基于 上述阵列基板结构的不同，在本实施例阵列基板中不需要开设第 四过孔， 阵列基板的其它结构及材质均与实施例 1相同，在此不 再赘述。
相应地，对于上述阵列基板，本实施例提供一种该阵列基板 的制备方法， 与实施例 1中阵列基板的制备方法不同的是：与上 述阵列基板的结构相对应地，本实施例中的阵列基板没有开设第 四过孔的步骤， 且公共电极形成在像素电极之上。
在本实施例中，所述制备方法中形成包括第一电极以及第二 电极的图形的步骤包括：
步骤 S5 :在完成步骤 S4的基板上形成中间介电层以及包括 第一过孔、第二过孔以及第三过孔的图形， 其中： 第一过孔形成 在对应着数据线的位置并贯穿缓冲层、 栅绝缘层和中间介电层， 第二过孔形成在对应着源电极的位置并贯穿栅绝缘层和中间介 电层，第三过孔形成在对应着漏电极的位置并贯穿栅绝缘层和中 间介电层。
步骤 S6:在完成步骤 S5的基板上形成包括像素电极的图形， 数据线与源电极通过第一过孔以及第二过孔电连接，像素电极与 漏电极通过第三过孔电连接。
步骤 S7 :在完成步骤 S6的基板上形成钝化层以及包括公共 电极的图形，钝化层完全覆盖像素电极， 公共电极的图形形成在 钝化层的上方。
本实施例的制备方法不包括与步骤 S8 ' 对应的步骤， 本实 施例中所提供的阵列基板的制备方法的其它步骤与实施例 1 相 同， 这里不再赘述。
在本实施例所提供的阵列基板和该阵列基板的制备方法中， 由于没有设置第四过孔， 因此进一步减少了构图工艺总次数，提 高了阵列基板的制备效率。 实施例 3 :
本实施例提供一种阵列基板，如图 5所示，所述阵列基板包 括基板 1以及设置在基板 1上的数据线 2和扫描线（图 5中未示 出）， 所述数据线 2和所述扫描线围成多个像素区域， 每个像素 区域内设置有薄膜晶体管，薄膜晶体管包括栅电极 5、源电极 6、 漏电极 7和有源区 4， 所述栅电极 5设置在有源区 4的上方， 源 电极 6与漏电极 7分设在有源区 4的相对两侧，每个像素区域内 还设置有遮光金属层 3， 遮光金属层 3和数据线 2同层设置在基 板 1上，遮光金属层 3设置在有源区 4下方，且在正投影方向上 与有源区 4至少部分重叠，数据线 2靠近源电极 6且在正投影方 向上与有源区 4至少部分不重叠。
其中， 所述阵列基板还包括： 轻掺杂漏极 8、 缓冲层 9以及 栅绝缘层 10。
上述阵列基板中的结构以及材质与实施例 1或实施例 2相 同， 这里不再赘述。
与实施例 1和实施例 2不同的是：本实施例中的阵列基板还 包括像素电极 14， 像素电极 14设置在栅绝缘层 10的上方， 栅 绝缘层 10在对应着漏电极 7的位置开设有第三过孔 17， 像素电 极 14与漏电极 7通过第三过孔 17电连接； 栅绝缘层 10和缓冲 层 9在对应数据线 2的位置开设有第一过孔 15， 栅绝缘层 10在 对应着源电极 6的位置开设有第二过孔 16，数据线 2和源电极 6 通过第一过孔 15以及第二过孔 16电连接。
相应地，对于上述阵列基板的结构，本实施例提供一种该阵 列基板的制备方法， 其中， 该制备方法的前四个步骤 （即步骤 Sl、 S2、 S3、 S4， 参照图 6a至图 6d所示）与实施例 1或实施例 2中阵列基板制备方法的前四个步骤相同， 另外， 该阵列基板的 制备方法还包括形成像素电极的步骤，如图 6e至图 6f所示，所 述形成像素电极的步骤包括： 步骤 S5 " ： 参照图 6e所示， 在完成步骤 S4的基板 1上形 成包括第一过孔 15、 第二过孔 16以及第三过孔 17的图形， 其 中： 第一过孔 15形成在对应着数据线 2的位置并贯穿缓冲层 9 和栅绝缘层 10， 第二过孔 16形成在对应着源电极 6的位置并贯 穿栅绝缘层 10， 第三过孔 17形成在对应着漏电极 7的位置并贯 穿栅绝缘层 10。
步骤 S6" : 参照图 6f所示， 在完成步骤 S5 "的基板 1上形 成包括像素电极 14的图形，数据线 2通过第一过孔 15以及第二 过孔 16与源电极 6电连接；像素电极 14与漏电极 7通过第三过 孔 17电连接。
需要说明的是，实施例 1和实施例 2是以具有高级超维场转 换显示方式（即 ADS显示方式）的阵列基板作为示例对本发明实 施例的实施方式进行具体说明的，实施例 3是以具有扭曲向列型 显示方式 （即 TN显示方式） 的阵列基板作为示例对本发明实施 例的实施方式进行具体说明的，但以上实施例仅是本发明的几种 实施方式， 而本发明的实际应用范围并不局限于此。
其中， ADS (ADvanced Super Dimension Switch, 高级超维 场转换）模式是平面电场宽视角核心技术，其核心技术特性描述 为：通过同一平面内狭缝电极边缘所产生的电场以及狭缝电极层 与板状电极层间产生的电场形成多维电场，使液晶盒内狭缝电极 间、电极正上方所有取向液晶分子都能够产生旋转， 从而提高了 液晶工作效率并增大了透光效率。 ADS模式的开关技术可以提高 TFT-LCD产品的画面品质， 具有高分辨率、 高透过率、 低功耗、 宽视角、 高开口率、 低色差、 无挤压水波紋 （push Mura 等优 点。针对不同应用， ADS技术的改进技术有高透过率 I-ADS技术、 高开口率 H-ADS和高分辨率 S-ADS技术等。 本发明实施例的有益效果：本发明实施例所提供的阵列基板 中，遮光金属层和数据线形成在所述阵列基板的同一层中；且在 相应的阵列基板的制备方法中，所述遮光金属层和数据线是通过 同一构图工艺（其中包括曝光工艺）形成；与现有的阵列基板中， 遮光金属层和数据线不在同一构图工艺中形成，且二者也不设置 在阵列基板的同一层中相比， 减少了对数据线的单独构图工艺 (即减少了与现有技术的阵列基板制备方法的如图 2f 所示的步 骤 P6相对应的构图工艺） 从而使得阵列基板的构图工艺数量减 少， 提高了阵列基板以及显示装置的制备效率。 实施例 4:
本实施例提供一种显示装置，包括上述任意一个实施例所提 供的阵列基板。
所述显示装置由于采用了上述实施例中所述的阵列基板，因 此减少了阵列基板的构图工艺的数量，从而提高了显示装置的制 备效率。
所述显示装置可以为： 液晶面板、 电子纸、 0LED 面板、 手 机、 平板电脑、 电视机、 显示器、 笔记本电脑、 数码相框、 导航 仪等任何具有显示功能的产品或部件。 应当理解的是，以上实施方式仅仅是为了说明本发明的原理 而采用的示例性实施方式，然而本发明实施例并不局限于此。对 于本领域内的普通技术人员而言，在不脱离本发明的精神和实质 的情况下，可以做出各种变型和改进，这些变型和改进也视为本 发明的保护范围。

Claims

权利要求书
1. 一种阵列基板， 包括基板以及设置在所述基板上的数据 线和扫描线，所述数据线和所述扫描线围成多个像素区域，每个 像素区域内设置有薄膜晶体管，所述薄膜晶体管包括栅电极、源 电极、 漏电极和有源区， 所述栅电极设置在所述有源区的上方， 所述源电极和所述漏电极分设在所述有源区的相对两侧，每个像 素区域内还设置有遮光金属层，其特征在于，所述遮光金属层和 所述数据线同层设置在所述基板上，所述遮光金属层设置在所述 有源区下方，且在投影方向上与所述有源区至少部分重叠，所述 数据线靠近所述源电极且在投影方向上与所述有源区至少部分 不重叠。
2. 根据权利要求 1所述的阵列基板， 其特征在于， 所述遮 光金属层和所述数据线采用相同的导电材料形成。
3. 根据权利要求 2所述的阵列基板， 其特征在于， 所述有 源区采用低温多晶硅材料形成，所述源电极和所述漏电极采用离 子注入的方式形成在所述有源区的相对两侧。
4. 根据权利要求 3所述的阵列基板， 其特征在于， 所述遮 光金属层设置在所述源电极和所述漏电极对应的区域之间，且在 投影方向上与所述栅电极至少部分重叠。
5. 根据权利要求 4所述的阵列基板， 其特征在于， 所述有 源区中还设置有轻掺杂漏极，所述轻掺杂漏极设置在所述源电极 和所述漏电极之间， 且分别设置在所述栅电极对应的区域的两 侧。
6. 根据权利要求 5所述的阵列基板， 其特征在于， 所述阵 列基板还包括缓冲层，所述缓冲层设置在所述有源区的下方以及 所述基板的上方，所述遮光金属层和所述数据线被所述缓冲层覆 ϊτπ。
7. 根据权利要求 6所述的阵列基板， 其特征在于， 所述遮 光金属层的位置与所述栅电极的位置对应设置。
8. 根据权利要求 7所述的阵列基板， 其特征在于， 所述阵 列基板还包括栅绝缘层，所述栅绝缘层设置在所述有源区的上方 以及所述栅电极的下方，所述有源区以及所述缓冲层被所述栅绝 缘层覆盖。
9. 根据权利要求 8所述的阵列基板， 其特征在于， 所述阵 列基板还包括依次设置在所述栅电极上方的中间介电层、第一电 极、钝化层以及第二电极，所述第二电极与所述第一电极在投影 方向上至少部分重叠，所述第一电极为板状或狭缝状，所述第二 电极为狭缝状；
所述缓冲层、所述栅绝缘层和所述中间介电层在对应着所述 数据线的位置开设有第一过孔，所述栅绝缘层和所述中间介电层 在对应着所述源电极的位置开设有第二过孔，所述数据线和所述 源电极通过所述第一过孔以及所述第二过孔电连接。
10. 根据权利要求 9 所述的阵列基板， 其特征在于， 所述 第一电极为像素电极，所述第二电极为公共电极，所述栅绝缘层、 所述中间介电层在对应着所述漏电极的位置开设有第三过孔，所 述像素电极和所述漏电极通过所述第三过孔电连接；
或者，所述第一电极为公共电极，所述第二电极为像素电极， 所述栅绝缘层、所述中间介电层在对应着所述漏电极的位置开设 有第三过孔，所述钝化层在对应着所述漏电极的位置开设有第四 过孔，所述像素电极和所述漏电极通过所述第三过孔以及所述第 四过孔电连接。
11. 根据权利要求 8 所述的阵列基板， 其特征在于， 所述 阵列基板还包括像素电极，所述像素电极设置在所述栅绝缘层的 上方， 所述栅绝缘层在对应着所述漏电极的位置开设有第三过 孔， 所述像素电极与所述漏电极通过所述第三过孔电连接； 所述栅绝缘层和所述缓冲层在对应所述数据线的位置开设 有第一过孔，所述栅绝缘层在对应着所述源电极的位置开设有第 二过孔，所述数据线和所述源电极通过所述第一过孔和所述第二 过孔电连接。
12. —种显示装置， 其特征在于， 包括权利要求 1-11中任 意一项所述的阵列基板。
13. 一种阵列基板的制备方法， 包括在基板上形成数据线、 扫描线、遮光金属层的步骤和形成薄膜晶体管的步骤，形成所述 薄膜晶体管包括形成栅电极、 源电极、 漏电极和有源区的步骤， 所述薄膜晶体管和所述遮光金属层均形成在由所述扫描线和所 述数据线围成的多个像素区域内，其特征在于，所述遮光金属层 和所述数据线在同一步骤中同层形成在所述基板上，所述遮光金 属层形成在所述有源区下方，且在投影方向上与所述有源区至少 部分重叠，所述数据线靠近所述源电极且在投影方向上与所述有 源区至少部分不重叠。
14. 根据权利要求 13所述的阵列基板的制备方法， 其特征 在于- 所述在基板上形成数据线、扫描线、遮光金属层的步骤包括： 在所述基板上采用一次构图工艺同时形成包括所述数据线 和所述遮光金属层的图形，所述数据线和所述遮光金属层相隔设 置； 所述形成薄膜晶体管的步骤包括：
在形成数据线和遮光金属层的图形的所述基板上形成缓冲 层和包括所述有源区的图形；所述缓冲层覆盖所述遮光金属层和 所述数据线，所述有源区的图形形成在所述缓冲层上，且所述有 源区的图形在投影方向上与所述遮光金属层至少部分重叠； 在所述基板上形成栅绝缘层和包括所述栅电极的图形，所述 栅电极的图形形成在所述栅绝缘层与所述遮光金属层位置对应 的位置的上方；
在所述基板上形成所述源电极和所述漏电极，所述源电极和 所述漏电极采用离子注入方式形成在所述有源区的相对两侧。
15. 根据权利要求 14所述的阵列基板的制备方法， 其特征 在于，所述制备方法还包括形成包括第一电极以及第二电极的图 形的步骤，所述第一电极为像素电极，所述第二电极为公共电极， 所述形成包括第一电极以及第二电极的图形的步骤包括：
在所述基板上形成中间介电层以及包括第一过孔、第二过孔 以及第三过孔的图形，其中：所述第一过孔形成在对应着所述数 据线的位置并贯穿所述缓冲层、 所述栅绝缘层和所述中间介电 层，所述第二过孔形成在对应着所述源电极的位置并贯穿所述栅 绝缘层和所述中间介电层，所述第三过孔形成在对应着所述漏电 极的位置并贯穿所述栅绝缘层和所述中间介电层；
在所述基板上形成包括所述像素电极的图形，所述数据线与 所述源电极通过所述第一过孔以及所述第二过孔电连接，所述像 素电极与所述漏电极通过所述第三过孔电连接；
在所述基板上形成所述钝化层以及包括所述公共电极的图 形，所述钝化层完全覆盖所述像素电极，所述公共电极的图形形 成在所述钝化层的上方。
16. 根据权利要求 14所述的阵列基板的制备方法， 其特征 在于，所述制备方法还包括形成包括第一电极以及第二电极的图 形的步骤，所述第一电极为公共电极，所述第二电极为像素电极， 所述形成包括第一电极以及第二电极的图形的步骤包括：
在所述基板上形成中间介电层以及包括第一过孔、第二过孔 以及第三过孔的图形，其中：所述第一过孔形成在对应着所述数 据线的位置并贯穿所述缓冲层、 所述栅绝缘层和所述中间介电 层，所述第二过孔形成在对应着所述源电极的位置并贯穿所述栅 绝缘层和所述中间介电层，所述第三过孔形成在对应着所述漏电 极的位置并贯穿所述栅绝缘层和所述中间介电层；
在所述基板上形成包括所述公共电极的图形，所述数据线与 所述源电极通过所述第一过孔和所述第二过孔电连接，所述第三 过孔中同时填充有用于形成所述公共电极的导电材料；
在所述基板上形成所述钝化层以及在所述钝化层中形成包 括第四过孔的图形，所述第四过孔形成在对应着所述漏电极的位 置， 且所述第四过孔的位置与所述第三过孔的位置相对应； 在所述基板上形成包括像素电极的图形，所述像素电极与所 述漏电极通过所述第三过孔和所述第四过孔电连接。
17. 根据权利要求 14所述的阵列基板的制备方法， 其特征 在于， 所述制备方法还包括形成像素电极的步骤：
在所述基板上形成包括第一过孔、第二过孔以及第三过孔的 图形，其中：所述第一过孔形成在对应着所述数据线的位置并贯 穿所述缓冲层和所述栅绝缘层，所述第二过孔形成在对应着所述 源电极的位置并贯穿所述栅绝缘层，所述第三过孔形成在对应着 所述漏电极的位置并贯穿所述栅绝缘层；
在所述基板上形成包括所述像素电极的图形，所述数据线通 过所述第一过孔和所述第二过孔与所述源电极电连接；所述像素 电极与所述漏电极通过所述第三过孔电连接。
18. 根据权利要求 14-17 中任意一项所述的阵列基板的制 备方法，其特征在于，所述形成源电极和漏电极的步骤中还包括： 采用离子注入方式在所述有源区中形成轻掺杂漏极，所述轻掺杂 漏极形成在所述源电极和所述漏电极之间，且分别设置在所述栅 电极对应的区域的两侧。
19. 根据权利要求 18所述的阵列基板的制备方法， 其特征 在于， 所述遮光金属层的位置分别与所述栅电极的位置对应设 置。
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Families Citing this family (51)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103383946B (zh) 2013-07-12 2016-05-25 京东方科技集团股份有限公司 一种阵列基板、显示装置及阵列基板的制备方法
CN103676281A (zh) * 2013-12-23 2014-03-26 京东方科技集团股份有限公司 阵列基板及其制备方法、显示装置
CN103928472A (zh) 2014-03-26 2014-07-16 京东方科技集团股份有限公司 一种阵列基板及其制作方法和显示装置
CN104022126B (zh) * 2014-05-28 2017-04-12 京东方科技集团股份有限公司 一种阵列基板、其制作方法及显示装置
KR102241442B1 (ko) * 2014-09-05 2021-04-16 엘지디스플레이 주식회사 박막트랜지스터 기판 및 그 제조 방법
KR101679252B1 (ko) * 2014-09-30 2016-12-07 엘지디스플레이 주식회사 박막 트랜지스터 기판과 그 제조방법 및 그를 이용한 디스플레이 장치
CN104393000B (zh) * 2014-10-20 2018-06-19 上海天马微电子有限公司 一种阵列基板及其制作方法、显示装置
CN104536603B (zh) * 2014-12-18 2018-01-09 深圳市华星光电技术有限公司 显示器及具有触控功能的面板
CN104503172A (zh) * 2014-12-19 2015-04-08 深圳市华星光电技术有限公司 阵列基板及显示装置
CN104460157B (zh) * 2014-12-19 2019-09-10 深圳市华星光电技术有限公司 阵列基板及显示装置
CN104538458A (zh) * 2014-12-22 2015-04-22 京东方科技集团股份有限公司 一种显示装置、阵列基板、薄膜晶体管及其制作方法
CN204314580U (zh) * 2015-01-08 2015-05-06 京东方科技集团股份有限公司 一种像素结构、阵列基板、显示面板和显示装置
CN104637955B (zh) * 2015-01-30 2017-10-24 京东方科技集团股份有限公司 一种阵列基板及其制作方法、显示装置
CN104965365A (zh) 2015-07-14 2015-10-07 深圳市华星光电技术有限公司 液晶显示面板及其阵列基板
TWI578509B (zh) * 2015-07-23 2017-04-11 友達光電股份有限公司 畫素結構
KR102402605B1 (ko) * 2015-07-28 2022-05-27 삼성디스플레이 주식회사 유기 발광 표시 장치
CN105047610B (zh) * 2015-09-07 2018-10-12 京东方科技集团股份有限公司 一种阵列基板及其制作方法、显示装置
CN105185742B (zh) * 2015-09-22 2018-02-16 武汉华星光电技术有限公司 一种阵列基板的制作方法及阵列基板
CN105097675B (zh) * 2015-09-22 2018-01-30 深圳市华星光电技术有限公司 阵列基板及其制备方法
CN105702684A (zh) * 2016-02-02 2016-06-22 武汉华星光电技术有限公司 阵列基板及阵列基板的制备方法
CN105552024B (zh) * 2016-03-14 2018-07-06 京东方科技集团股份有限公司 阵列基板及其制作方法、显示装置
CN105742364A (zh) * 2016-04-12 2016-07-06 中山大学 一种抑制有源沟道区光致漏电流产生的mos管及应用
CN105977262B (zh) * 2016-05-27 2019-09-20 深圳市华星光电技术有限公司 一种显示装置、阵列基板及其制造方法
CN106168865B (zh) * 2016-06-28 2019-11-26 京东方科技集团股份有限公司 内嵌式触摸屏及其制作方法、显示装置
CN105932068A (zh) * 2016-06-30 2016-09-07 上海中航光电子有限公司 薄膜晶体管、显示面板及显示装置
CN106200170A (zh) * 2016-07-08 2016-12-07 深圳市华星光电技术有限公司 Tft液晶显示器件及其制作方法
US9806197B1 (en) * 2016-07-13 2017-10-31 Innolux Corporation Display device having back gate electrodes
KR102618961B1 (ko) * 2016-09-30 2024-01-02 삼성디스플레이 주식회사 트랜지스터 기판, 표시 장치, 및 트랜지스터 기판 제조 방법
CN106856210B (zh) * 2017-02-16 2019-08-02 北京京东方光电科技有限公司 薄膜晶体管及其制作方法、显示基板及显示装置
CN107425074B (zh) * 2017-05-15 2021-10-29 京东方科技集团股份有限公司 一种薄膜晶体管及其制作方法、阵列基板、显示面板
CN107204375B (zh) * 2017-05-19 2019-11-26 深圳市华星光电技术有限公司 薄膜晶体管及其制作方法
CN109037232B (zh) * 2017-06-08 2019-11-01 京东方科技集团股份有限公司 阵列基板及其制造方法、显示面板以及显示装置
CN107797344B (zh) * 2017-11-14 2021-01-15 京东方科技集团股份有限公司 阵列基板、显示面板及其制造方法
CN107797353A (zh) * 2017-11-22 2018-03-13 武汉华星光电技术有限公司 一种液晶显示面板以及液晶显示装置
CN108110010B (zh) 2017-12-15 2021-10-01 京东方科技集团股份有限公司 阵列基板及其制备方法、触控显示面板
KR102574096B1 (ko) * 2017-12-29 2023-09-01 엘지디스플레이 주식회사 유기발광표시패널 및 그 제조 방법과 이를 이용한 유기발광표시장치
CN108899325A (zh) * 2018-06-27 2018-11-27 武汉华星光电技术有限公司 一种ltps-tft阵列基板及其制造方法和显示面板
CN109300917B (zh) * 2018-09-30 2021-01-26 京东方科技集团股份有限公司 一种阵列基板及其制备方法、显示面板
US10852609B2 (en) 2019-02-27 2020-12-01 Au Optronics Corporation Pixel array substrate and driving method thereof
KR20200110573A (ko) * 2019-03-15 2020-09-24 삼성디스플레이 주식회사 표시 장치
CN110085762B (zh) * 2019-04-15 2021-08-03 昆山工研院新型平板显示技术中心有限公司 Oled显示面板及显示装置
CN110190069B (zh) * 2019-05-22 2021-08-03 武汉华星光电技术有限公司 阵列基板及其制备方法
CN110600426A (zh) * 2019-08-22 2019-12-20 武汉华星光电技术有限公司 阵列基板的制备方法及阵列基板
CN110797349B (zh) * 2019-10-15 2022-04-05 深圳市华星光电半导体显示技术有限公司 一种薄膜晶体管基板及其制备方法
US11768551B2 (en) * 2020-01-20 2023-09-26 Chengdu Boe Optoelectronics Technology Co., Ltd. Array substrate and display device
CN111969008A (zh) * 2020-06-03 2020-11-20 京东方科技集团股份有限公司 有机发光显示基板及其制备方法、显示装置
CN114002887B (zh) * 2021-11-01 2022-10-04 武汉华星光电技术有限公司 阵列基板和显示面板
CN114660862B (zh) * 2022-01-06 2023-08-29 昆山龙腾光电股份有限公司 阵列基板及制作方法、显示面板
CN114594639A (zh) * 2022-03-09 2022-06-07 昆山龙腾光电股份有限公司 阵列基板及制作方法
TWI805346B (zh) * 2022-05-03 2023-06-11 友達光電股份有限公司 陣列基板與其製造方法
CN114967258A (zh) * 2022-05-18 2022-08-30 武汉华星光电技术有限公司 显示面板及显示装置

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101083261A (zh) * 2006-06-02 2007-12-05 三星Sdi株式会社 有机发光显示器以及制造方法
CN101097381A (zh) * 2006-06-30 2008-01-02 Lg.菲利浦Lcd株式会社 液晶显示器件的制造方法
CN101123257A (zh) * 2007-09-12 2008-02-13 上海广电光电子有限公司 薄膜晶体管阵列基板及其制造方法
CN101441372A (zh) * 2007-11-23 2009-05-27 上海广电Nec液晶显示器有限公司 液晶显示器的静电放电保护装置及其制造方法
CN103383946A (zh) * 2013-07-12 2013-11-06 京东方科技集团股份有限公司 一种阵列基板、显示装置及阵列基板的制备方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3107075B2 (ja) * 1998-12-14 2000-11-06 日本電気株式会社 液晶表示装置
KR100669270B1 (ko) * 2003-08-25 2007-01-16 도시바 마쯔시따 디스플레이 테크놀로지 컴퍼니, 리미티드 표시 장치 및 광전 변환 소자
KR101219035B1 (ko) * 2005-05-03 2013-01-07 삼성디스플레이 주식회사 유기 박막 트랜지스터 표시판 및 그 제조 방법
US8242503B2 (en) * 2010-05-21 2012-08-14 Chimei Innolux Corporation Multi-gate thin film transistor device
TW201200948A (en) * 2010-06-22 2012-01-01 Au Optronics Corp Pixel structure and method for manufacturing the same
CN203422543U (zh) * 2013-07-12 2014-02-05 京东方科技集团股份有限公司 一种阵列基板和显示装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101083261A (zh) * 2006-06-02 2007-12-05 三星Sdi株式会社 有机发光显示器以及制造方法
CN101097381A (zh) * 2006-06-30 2008-01-02 Lg.菲利浦Lcd株式会社 液晶显示器件的制造方法
CN101123257A (zh) * 2007-09-12 2008-02-13 上海广电光电子有限公司 薄膜晶体管阵列基板及其制造方法
CN101441372A (zh) * 2007-11-23 2009-05-27 上海广电Nec液晶显示器有限公司 液晶显示器的静电放电保护装置及其制造方法
CN103383946A (zh) * 2013-07-12 2013-11-06 京东方科技集团股份有限公司 一种阵列基板、显示装置及阵列基板的制备方法

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