WO2020047957A1 - 一种阵列基板的制造方法、阵列基板及显示面板 - Google Patents

一种阵列基板的制造方法、阵列基板及显示面板 Download PDF

Info

Publication number
WO2020047957A1
WO2020047957A1 PCT/CN2018/111344 CN2018111344W WO2020047957A1 WO 2020047957 A1 WO2020047957 A1 WO 2020047957A1 CN 2018111344 W CN2018111344 W CN 2018111344W WO 2020047957 A1 WO2020047957 A1 WO 2020047957A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
metal layer
semiconductor active
passivation
gate
Prior art date
Application number
PCT/CN2018/111344
Other languages
English (en)
French (fr)
Inventor
杨凤云
卓恩宗
Original Assignee
重庆惠科金渝光电科技有限公司
惠科股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 重庆惠科金渝光电科技有限公司, 惠科股份有限公司 filed Critical 重庆惠科金渝光电科技有限公司
Priority to US16/311,179 priority Critical patent/US11152403B2/en
Publication of WO2020047957A1 publication Critical patent/WO2020047957A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78663—Amorphous silicon transistors
    • H01L29/78669—Amorphous silicon transistors with inverted-type structure, e.g. with bottom gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel

Definitions

  • the present application relates to the field of display panel manufacturing, and more specifically, to a method for manufacturing an array substrate, an array substrate, and a display panel.
  • Thin film transistor liquid crystal display (TFT-LCD) display uses a high-performance thin film process (TFT device).
  • TFT-LCD thin film process
  • Exemplary amorphous silicon thin film transistor (A-Si) TFT processes usually use a back channel protective layer etching BCE (Back Channel Etching) structure, which has a lower cost and simpler process than an Etching stop (ESt) structure.
  • BCE Back Channel Etching
  • Et Etching stop
  • the 4-mask technology is to combine the gate insulation layer GIN and the second metal layer M2 in the 5-mask into a mask process, as shown in Figures 4a to 4e.
  • the second metal layer is a protective layer, and the semiconductor active layer and the gate insulating layer are etched, so that the width of the semiconductor active layer is equal to or larger than the second metal layer M2, which is a source metal layer and a drain metal layer formed later.
  • the width of the semiconductor active layer is too large, even exceeding the area of the gate metal layer. It is easy to produce large doped silicon tails, and it is more likely to cause display panel image residue. sticking (IS) issue).
  • the purpose of the present application is to provide an array substrate manufacturing method, an array substrate, and a display panel which can improve the tailing phenomenon of the silicon-doped layer and the influence of the afterimage in view of the defects mentioned above.
  • a method for manufacturing an array substrate includes the following steps:
  • a half-tone mask photomask is used for one exposure above the semiconductor active base layer to form a gate metal layer, a gate insulating layer, and a semiconductor active layer above the semiconductor active base layer.
  • the The width of the semiconductor active layer is smaller than the width of the gate metal layer;
  • a first passivation layer is formed over the first passivation base layer through a first photomask, and the first passivation layer is formed with exposed semiconductor active layers at positions corresponding to the source metal layer and the drain metal layer, respectively.
  • the first passivation base layer between the two vias is a channel protection layer; the channel protection layer covers the semiconductor active layer and is not covered by the source metal between the two vias A portion blocked by the layer and the drain metal layer;
  • a photoresist material layer is coated on the second passivation base layer, and the photoresist material is patterned through a second photomask.
  • the second passivation is etched by using the coated photoresist material layer as a protective layer.
  • Layer pattern, and using the pattern of the second passivation layer as a protective layer, the second metal base layer is etched off by a wet etching to form the source metal layer and the drain metal layer, and then, Clear photoresist material layer; the source metal layer and drain metal layer communicate with the semiconductor active layer through vias; the second passivation layer forms a contact hole above the corresponding drain metal layer to expose the drain Metal layer
  • a transparent electrode base layer is deposited on the second passivation layer, and a pixel electrode layer is formed through a third photomask; the pixel electrode layer is in communication with the drain metal layer through a contact hole.
  • a method for manufacturing an array substrate includes:
  • a gate metal layer, a gate insulating layer, and a semiconductor active layer are formed over the semiconductor active base layer through a photomask process. In a direction parallel to the substrate, the width of the semiconductor active layer is smaller than that of the gate metal. Layer width
  • a first passivation layer is formed over the gate metal layer, the gate insulating layer, and the semiconductor active layer through a photomask process, and a source metal layer and a drain are formed on the first passivation layer.
  • a pixel electrode layer is formed in conduction with the drain metal layer.
  • a half-tone mask photomask is used for one exposure to form the semiconductor active base layer.
  • a first passivation layer is formed over the gate metal layer, the gate insulating layer, and the semiconductor active layer through a photomask process, and a source metal layer and a drain metal are formed on the first passivation layer.
  • the step of forming a layer further includes the step of forming a channel protection layer on a portion of the semiconductor active layer that is not blocked by the source metal layer and the drain metal layer.
  • a channel protection layer is formed on a portion of the semiconductor active layer that is not shielded by the source metal layer and the drain metal layer, so that the channel region of the TFT is protected by the source metal layer, the drain metal layer, and the channel. The layer is shielded in all directions, so that the light in the panel will not irradiate the semiconductor active layer in the channel region of the TFT, reducing the generation of photocurrent.
  • a first passivation layer is formed over the gate metal layer, the gate insulating layer, and the semiconductor active layer through a photomask process, and a source metal layer and a drain metal are formed on the first passivation layer.
  • the steps of the layer include the following steps:
  • a first passivation layer is formed over the first passivation base layer through a first photomask, and the first passivation layer is formed with exposed semiconductor active layers at positions corresponding to the source metal layer and the drain metal layer, respectively.
  • the first passivation base layer between the two vias is a channel protection layer; the channel protection layer covers the semiconductor active layer and is not covered by the source metal between the two vias A portion blocked by the layer and the drain metal layer;
  • a source metal layer, a drain metal layer, and a second passivation layer are formed on the second passivation base layer through a second photomask, and the source metal layer and the drain metal layer are connected to the semiconductor Layer communication; the second passivation layer forms a contact hole above the corresponding drain metal layer to expose the drain metal layer;
  • the step of forming a pixel electrode layer in electrical communication with the drain metal layer includes: depositing a transparent electrode base layer on the second passivation layer, and forming a pixel electrode layer through a third photomask; the pixel electrode layer is contacted by A hole is in communication with the drain metal layer.
  • the step of forming a source metal layer, a drain metal layer, and a second passivation layer over the second passivation base layer through a second photomask includes: coating a photoresist material layer on the second passivation base layer, The second photomask performs a patterning process on the photoresist material. The pattern of the second passivation layer is etched by using the coated photoresist material layer as a protection layer, and then the pattern of the formed second passivation layer is used as protection. Layer, the second metal base layer is etched and disconnected by one wet etching to form the source metal layer and the drain metal layer, and then the photoresist material layer is removed.
  • An array substrate includes:
  • a gate metal layer disposed on the substrate
  • a gate insulating layer disposed on the gate metal layer
  • a semiconductor active layer which is disposed on the gate insulating layer
  • a source metal layer and a drain metal layer are disposed on the semiconductor active layer
  • a width of the semiconductor active layer is smaller than a width of the gate metal layer.
  • the array substrate includes:
  • the source metal layer covers and is disposed on one side of the first passivation layer, and one end of the source metal layer is disposed in a via to contact the semiconductor active layer;
  • the drain metal layer covers and is disposed on the other side of the first passivation layer, and one end of the drain metal layer is disposed in another via hole to be in contact with the semiconductor active layer;
  • a channel protection layer is provided between the two vias; the channel protection layer covers the two vias on the semiconductor active layer and is not blocked by the source metal layer and the drain metal layer. part.
  • the array substrate includes:
  • a second passivation layer is disposed to cover the source metal layer and the drain metal layer, respectively; the second passivation layer forms a contact hole above the corresponding drain metal layer to expose the drain metal layer ;
  • a pixel electrode layer covers the second passivation layer located above the drain metal layer, and the pixel electrode layer is in communication with the drain metal layer through a contact hole.
  • the width of the gate insulating layer is smaller than the width of the gate metal layer, and the width of the semiconductor active layer is smaller than the width of the gate insulating layer.
  • the passivation layer sufficiently covers the gate metal layer, the gate insulating layer, and the semiconductor active layer, and because the width of the semiconductor active layer is small, the source metal layer and the drain The metal layer covers both ends of the semiconductor active layer.
  • a display panel includes the above-mentioned array substrate and a second substrate opposite to the array substrate.
  • the array substrate of the display panel of the present application uses a photomask process to form a gate metal layer, a gate insulation layer, and a semiconductor active layer
  • a first photomask process is formed on the semiconductor active layer to form a first passivation layer
  • a source metal layer and a drain metal layer are formed on the first passivation layer.
  • the pattern of the semiconductor active layer is directly formed based on the mask pattern, and does not depend on the patterns of other layers. This makes it possible to use a 4mask process to make TFTs in a direction parallel to the substrate.
  • the width of the semiconductor active layer is smaller than the width of the gate metal layer, which reduces the width of the semiconductor active layer and significantly improves the silicon doped layer drag. Tail phenomenon, thereby improving the afterimage effect and enhancing the reliability of the panel.
  • FIG. 1a to 1f are schematic sectional views of a manufacturing process according to an embodiment of the present application.
  • FIG. 3 is a flowchart of a method according to another embodiment of the present application.
  • 4a-4e are schematic cross-sectional views of a manufacturing process of a 4mask process.
  • the application provides a method for manufacturing an array substrate, an array substrate and a display panel.
  • the present application provides a method for manufacturing an array substrate, including steps:
  • a gate metal layer 111, a gate insulating layer 121, and a semiconductor active layer 131 are formed over the semiconductor active base layer 13 through a photomask process. In a direction parallel to the substrate, the semiconductor active layer 131 The width is smaller than the width of the gate metal layer 111;
  • a first passivation layer 141 is formed over the gate metal layer 111, the gate insulating layer 121, and the semiconductor active layer 131 through a photomask process, and is formed on the first passivation layer 141.
  • a pixel electrode layer 19 that is in electrical communication with the drain metal layer 162 is formed.
  • the array substrate of the display panel described in the present application is formed by using a single photomask process to form the gate metal layer 111, the gate insulating layer 121, and the semiconductor active layer 131, and is formed on the semiconductor active layer 131 after a single photomask process.
  • the first passivation layer 141, and a source metal layer 161 and a drain metal layer 162 are formed on the first passivation layer 141.
  • the pattern of the semiconductor active layer 131 is directly based on the mask. The pattern is formed and does not depend on the pattern of other layers, so that the 4mask process can also be used to make a TFT in a direction parallel to the substrate.
  • the width of the semiconductor active layer 131 is smaller than the width of the gate metal layer 111.
  • the width of the semiconductor active layer 131 is significantly improved, and the tailing phenomenon of the silicon doped layer is significantly improved, thereby improving the afterimage effect and enhancing the reliability of the panel.
  • the method is specifically:
  • a first metal base layer 11, an insulating base layer 12, and a semiconductor active base layer 13 are sequentially deposited on a substrate 10; the first metal base layer 11 covers the substrate 10, and the insulating base layer 12 covers Above the first metal base layer 11, the semiconductor active base layer 13 covers the insulating base layer 12, so that the substrate 10, the first metal base layer 11, the insulating base layer 12, and the first metal base layer 11 forms the entire plate structure.
  • the width of the semiconductor active layer 131 is smaller than the width of the gate metal layer 111; the width of the gate insulating layer 121 is also smaller than the width of the gate metal layer 111; Specifically, a photoresist material layer is coated on the semiconductor active base layer 13, and the photoresist material layer is patterned by using a half-tone mask mask to obtain the semiconductor active layer 131 pattern and the gate insulation layer.
  • the semiconductor active layer 131 is etched first, then the gate insulating layer 121 is etched, and finally the gate metal layer 111 is etched;
  • a first passivation base layer (not shown in the figure) is deposited over the substrate, the gate metal layer 111, the gate insulating layer 121, and the semiconductor active layer 131;
  • a first passivation layer 141 is formed above the first passivation base layer through a first photomask, and the first passivation layer 141 is formed at positions corresponding to the source metal layer 161 and the drain metal layer 162, respectively.
  • a residual photoresist material layer is applied to obtain the first passivation layer 141 pattern.
  • a photoresist material layer is coated on the second passivation base layer 17, and the photoresist material is patterned through a second photomask.
  • the coated photoresist material layer is used as a protective layer for etching.
  • the pattern of the second passivation layer 171 is obtained, and the pattern of the second passivation layer 171 is used as a protective layer.
  • the second metal base layer 16 is etched and disconnected by a wet etching to form the source electrode.
  • the metal layer 161 and the drain metal layer 162 are then cleared of a photoresist material layer; the source metal layer 161 and the drain metal layer 162 communicate with the semiconductor active layer 131 through vias 142, respectively; the second passivation The layer 171 forms a contact hole 172 above the corresponding drain metal layer 162 to expose the drain metal layer 162; such a design makes the second passivation layer 171, the source metal layer 161, and the drain metal layer through only one exposure development. 162, saving process time;
  • a transparent electrode base layer (ITO) is deposited on the second passivation layer 171, and a pixel electrode layer (ITO) is formed through a third photomask; the pixel electrode layer 19 communicates with The drain metal layer 162 is communicated to form a TFT switch.
  • the present application further provides a display panel.
  • the display panel includes an array substrate and a second substrate opposite to the array substrate.
  • the array substrate 10 includes:
  • the source metal layer 161 and the drain metal layer 162 are disposed on the semiconductor active layer 131;
  • a width of the semiconductor active layer 131 is smaller than a width of the gate metal layer 111.
  • the array substrate 10 includes:
  • a semiconductor active layer 131 which is disposed on the gate insulating layer 121; in a direction parallel to the substrate, a width of the semiconductor active layer 131 is smaller than that of the gate metal layer 111 The width of
  • a first passivation layer 141 is disposed to cover the gate metal layer 111, the gate insulating layer 121, and the semiconductor active layer 131.
  • the first passivation layer 141 is formed on the semiconductor.
  • Two via holes 142 are formed above the source layer 131 to expose the semiconductor active layer 131;
  • the source metal layer 161 and the drain metal layer 162 are disposed on the semiconductor active layer 131;
  • the source metal layer 161 covers and is disposed on one side of the first passivation layer 141, and one end of the source metal layer 161 is disposed in a via hole 142 to be in contact with the semiconductor active layer 131;
  • the drain metal layer 162 covers the other side of the first passivation layer 141, and one end of the drain metal layer 162 is disposed in another via hole 142 to be in contact with the semiconductor active layer 131;
  • a second passivation layer 171 is disposed to cover the source metal layer 161 and the drain metal layer 162, respectively; the second passivation layer 171 forms a contact hole 172 above the corresponding drain metal layer 162 to expose The drain metal layer 162;
  • the pixel electrode layer 19 covers the second passivation layer 171 disposed above the drain metal layer 162, and the pixel electrode layer 19 communicates with the drain metal layer 162 through a contact hole 172.
  • the width of the gate insulating layer 121 is smaller than the width of the gate metal layer 111, and the width of the semiconductor active layer 131 is smaller than the width of the gate insulating layer 121.
  • the passivation layer sufficiently covers the gate metal layer 111, the gate insulating layer 121, and the semiconductor active layer 131, and because the width of the semiconductor active layer 131 is small, the source metal layer 161 The drain metal layer 162 covers both ends of the semiconductor active layer 131.
  • the width of the gate insulating layer 121 is also smaller than the width of the gate metal layer 111, and the width of the gate insulating layer 121 is consistent with the width of the semiconductor active layer 131, which is the same as that of the semiconductor.
  • the sides of the active layer 131 are smoothly transitioned to form a trapezoidal mesa structure.
  • the width of the semiconductor active layer 131 is smaller than the width of the gate metal layer 111.
  • the width of the semiconductor active layer 131 is significantly improved, and the tailing phenomenon of the silicon doped layer is significantly improved, thereby improving the afterimage effect and enhancing the reliability of the panel.
  • a channel protection layer 18 is formed on a portion of the semiconductor active layer 131 that is not blocked by the source metal layer and the drain metal layer 162, so that the channel region of the TFT is covered by the source metal layer and the drain metal layer 162. It is shielded from the channel protection layer 18 in all directions, so that the light in the panel will not irradiate the semiconductor active layer 131 in the channel region of the TFT, reducing the generation of photocurrent.
  • the design of the process allows the surface of the channel region to be covered and protected by the first passivation base layer during subsequent processes, and the channel protection layer 18 formed by the first passivation base layer to block the subsequent processes. In order to avoid the influence of other materials on the channel region, no back channel etching is performed, and the interface state of the channel region will not be deteriorated by subsequent etching, thereby reducing the leakage of the TFT.
  • the gate insulating layer 121 is a silicon oxide film or a silicon nitride film.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Thin Film Transistor (AREA)
  • Liquid Crystal (AREA)

Abstract

一种阵列基板的制造方法、阵列基板及显示面板。一次光罩制程形成栅极金属层（111）、栅极绝缘层（121）、半导体有源层（131），一次光罩制程形成第一钝化层（141），第一钝化层上形成源极金属层（161）、漏极金属层（162）和像素电极层（19）。

Description

一种阵列基板的制造方法、阵列基板及显示面板
本申请要求于2018年09月03日提交中国专利局，申请号为CN201811021331.8、发明名称为“一种阵列基板的制造方法、阵列基板及显示面板”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及显示面板制造领域，更具体的说，是涉及一种阵列基板的制造方法、阵列基板及显示面板。
背景技术
这里的陈述仅提供与本申请有关的背景信息，而不必然地构成现有技术。薄膜晶体管液晶显示屏(Thin film transistor-liquid crystal display,TFT-LCD)显示使用高性能的薄膜工艺(TFT Device)。示例性非晶硅薄膜晶体管(A-Si TFT)制程通常采用背沟道保护层蚀刻BCE(Back Channel Etching)型结构，该结构成本相比蚀刻终止ES(Etching stop)型结构要低且工艺简单；但是由于BCE型结构的背沟道保护层Back Channel界面状态较差，TFT漏电较大。
4掩膜(4-mask)技术是将5掩膜(5-mask)中的栅极绝缘层GIN与第二层金属层M2合并为一道mask掩膜制程,如图4a-图4e，其以第二金属层为保护层蚀刻半导体有源层、栅极绝缘层，使得半导体有源层的宽度等于甚至大于第二次金属层M2也就是后来形成的源极金属层、漏极金属层在一起的宽度，导致半导体有源层的宽度过大，甚至超出了栅极金属层的面积，容易产生较大的掺杂硅拖尾(AS tail),而更易造成显示屏图像残留(display panel RA image sticking(IS)issue)。
技术解决方案
本申请的目的是针对上述存在的缺陷，提供一种改善掺硅层拖尾现象，改善残像影响的阵列基板的制造方法、阵列基板及显示面板。
本申请的目的是通过以下方案来实现的：
提供一种阵列基板的制造方法，所述方法包括以下步骤：
在基板上依次沉积第一金属基层、绝缘基层和半导体有源基层；
在半导体有源基层上方通过半色调掩膜光罩进行一次曝光，在半导体有源基层上方形成栅极金属层、栅极绝缘层和半导体有源层，在平行于基板的方向上，所述的半导体有源层的宽度小于所述栅极金属层的宽度；
在所述基板、所述栅极金属层、所述栅极绝缘层以及所述半导体有源层上方沉积第一钝化基层；
在所述第一钝化基层上方通过第一光罩形成第一钝化层，所述第一钝化层在对应源极金属层、漏极金属层的位置处分别形成有暴露半导体有源层的过孔；所述两个过孔之间的第一钝化基层为沟道保护层；所述沟道保护层覆盖所述半导体有源层上两个过孔间没有被所述源极金属层与所述漏极金属层遮挡的部分；
在所述第一钝化层上依次沉积第二金属基层及第二钝化基层；
在所述第二钝化基层上涂布光阻材料层，通过第二光罩对光阻材料进行图案化处理，先以涂布的光阻材料层为保护层蚀刻出所述第二钝化层的图案，再以形成的第二钝化层的图案为保护层，通过一次湿法蚀刻将所述第二金属基层蚀刻断开，形成所述源极金属层及漏极金属层，之后，清除光阻材料层；所述源极金属层、漏极金属层分别通过过孔与半导体有源层连通；所述第二钝化层在对应漏极金属层的上方形成接触孔以暴露漏极金属层；
在所述第二钝化层上沉积透明电极基层，并通过第三光罩形成像素电极层；所述像素电极层通过接触孔与所述漏极金属层连通。
一种阵列基板的制造方法，所述方法包括：
在基板上依次沉积第一金属基层、绝缘基层、半导体有源基层；
在半导体有源基层上方通过一次光罩制程形成栅极金属层、栅极绝缘层、半导体有源层，在平行于基板的方向上，所述的半导体有源层的宽度小于所述栅极金属层的宽度；
在所述栅极金属层、所述栅极绝缘层以及所述半导体有源层上方经过一次光罩制程形成第一钝化层，并在第一钝化层上形成源极金属层、漏极金属层；
形成与漏极金属层导通的像素电极层。
所述在半导体有源基层上方通过一次光罩制程形成栅极金属层、 栅极绝缘层、半导体有源层的步骤中，通过半色调掩膜光罩进行一次曝光，在半导体有源基层上方形成栅极金属层、栅极绝缘层、半导体有源层，在平行于基板的方向上，所述的半导体有源层的宽度小于所述栅极金属层的宽度；所述栅极绝缘层的宽度也小于所述栅极金属层的宽度。
所述栅极金属层、所述栅极绝缘层以及所述半导体有源层上方经过一次光罩制程形成第一钝化层，并在第一钝化层上形成源极金属层、漏极金属层的步骤中，还包括在所述的半导体有源层上未被所述源极金属层与所述漏极金属层遮挡的部分形成沟道保护层的步骤。在半导体有源层上未被所述源极金属层与所述漏极金属层遮挡的部分形成沟道保护层，使得TFT的沟道区域被源极金属层、漏极金属层和沟道保护层全方位遮挡，使得面板中的光线不会照射到TFT的沟道区域的半导体有源层，减小光电流的产生。
所述栅极金属层、所述栅极绝缘层以及所述半导体有源层上方经过一次光罩制程形成第一钝化层，并在第一钝化层上形成源极金属层、漏极金属层的步骤中，还包括以下步骤：
在所述基板、所述栅极金属层、所述栅极绝缘层以及所述半导体有源层上方沉积第一钝化基层；
在所述第一钝化基层上方通过第一光罩形成第一钝化层，所述第一钝化层在对应源极金属层、漏极金属层的位置处分别形成有暴露半导体有源层的过孔；所述两个过孔之间的第一钝化基层为沟道保护层；所述沟道保护层覆盖所述半导体有源层上两个过孔间没有被所述源极金属层与所述漏极金属层遮挡的部分；
在所述第一钝化层上依次沉积第二金属基层及第二钝化基层；
在所述第二钝化基层上方通过第二光罩形成源极金属层、漏极金属层以及第二钝化层，所述源极金属层、漏极金属层分别通过过孔与半导体有源层连通；所述第二钝化层在对应漏极金属层的上方形成接触孔以暴露漏极金属层；
所述形成与漏极金属层导通的像素电极层的步骤包括：在所述第二钝化层上沉积透明电极基层，并通过第三光罩形成像素电极层；所述像素电极层通过接触孔与所述漏极金属层连通。
所述第二钝化基层上方通过第二光罩形成源极金属层、漏极金属层以及第二钝化层的步骤包括：在所述第二钝化基层上涂布光阻材料层， 通过第二光罩对光阻材料进行图案化处理，先以涂布的光阻材料层为保护层蚀刻出所述第二钝化层的图案，再以形成的第二钝化层的图案为保护层，通过一次湿法蚀刻将所述第二金属基层蚀刻断开，形成所述源极金属层及漏极金属层，之后，清除光阻材料层。一种阵列基板，包括：
基板；
栅极金属层，所述栅极金属层设置于所述基板上；
栅极绝缘层，所述栅极绝缘层设置于所述栅极金属层上；
半导体有源层，所述半导体有源层设置于所述栅极绝缘层上；
源极金属层和漏极金属层，设置在所述半导体有源层上，
其中，在平行于基板的方向上，所述的半导体有源层的宽度小于所述栅极金属层的宽度。
所述的阵列基板包括：
第一钝化层，所述第一钝化层覆盖所述栅极金属层、栅极绝缘层及半导体有源层设置，所述第一钝化层在所述半导体有源层的上方形成有两个过孔，露出所述半导体有源层；
所述的源极金属层覆盖设置于所述第一钝化层一侧，所述源极金属层一端设置在一过孔内与半导体有源层相接触；
所述的漏极金属层覆盖设置于所述第一钝化层的另一侧，所述漏极金属层一端设置在另一过孔内与半导体有源层相接触；
所述两个过孔之间设有沟道保护层；所述沟道保护层覆盖所述半导体有源层上两个过孔间没有被所述源极金属层与所述漏极金属层遮挡的部分。
所述的阵列基板包括：
第二钝化层，分别覆盖所述源极金属层与所述漏极金属层进行设置；所述第二钝化层在对应漏极金属层的上方形成接触孔以暴露所述漏极金属层；
像素电极层，覆盖设置于位于所述漏极金属层上方的所述第二钝化层上，所述像素电极层通过接触孔与所述漏极金属层连通。
优选的，所述栅极绝缘层宽度小于所述栅极金属层宽度，所述半导体有源层宽度小于所述栅极绝缘层宽度。这样，使所述钝化层充分覆盖住所述栅极金属层、栅极绝缘层以及半导体有源层，而且因为所述半导体有源层宽度较小，所述源极金属层与所述漏极金属层遮挡住所述半 导体有源层的两端。
一种显示面板，包括上述的阵列基板，及与所述阵列基板对置的第二基板。
本申请显示面板的阵列基板由于使用一次光罩制程形成栅极金属层、栅极绝缘层、半导体有源层，而在半导体有源层之上经过一次光罩制程形成第一钝化层，并在第一钝化层上形成源极金属层、漏极金属层，相对于4光罩制程来说，半导体有源层的图案是直接根据光罩图案形成的，不依赖于其他层的图案，使得使用4mask工艺也能做出在平行于基板的方向上，半导体有源层的宽度小于所述栅极金属层的宽度的TFT，减小了半导体有源层的宽度，显著改善掺硅层拖尾现象，从而改善残像影响，增强面板的信耐性。
附图说明
图1a至图1f为本申请实施例的制造过程的剖面示意图；
图2为本申请一实施例的方法流程图；
图3为本申请另一实施例的方法流程图；
图4a-4e为4mask工艺制造过程的剖面示意图。
本申请的实施方式
下面描述本申请的优选实施方式，本领域普通技术人员将根据下文所述用本领域的相关技术加以实现，并能更加明白本申请的创新之处和带来的益处。
本申请提供了一种阵列基板的制造方法、阵列基板及显示面板。
本申请的目的是通过以下技术方案来实现的：
如图1a-图1f、图2所示，本申请提供一种阵列基板的制造方法，包括步骤：
S1：在基板10上依次沉积第一金属基层11、绝缘基层12、半导体有源基层13；
S2：在半导体有源基层13上方通过一次光罩制程形成栅极金属层111、栅极绝缘层121、半导体有源层131，在平行于基板的方向上，所述的半导体有源层131的宽度小于所述栅极金属层111的宽度；
S3：在所述栅极金属层111、所述栅极绝缘层121以及所述半导 体有源层131上方经过一次光罩制程形成第一钝化层141，并在第一钝化层141上形成源极金属层161、漏极金属层162；
S4：形成与漏极金属层162导通的像素电极层19。
本申请所述的显示面板的阵列基板由于使用一次光罩制程形成栅极金属层111、栅极绝缘层121、半导体有源层131，而在半导体有源层131之上经过一次光罩制程形成第一钝化层141，并在第一钝化层141上形成源极金属层161、漏极金属层162，相对于4光罩制程来说，半导体有源层131的图案是直接根据光罩图案形成的，不依赖于其他层的图案，使得使用4mask工艺也能做出在平行于基板的方向上，半导体有源层131的宽度小于所述栅极金属层111的宽度的TFT，减小了半导体有源层131的宽度，显著改善掺硅层拖尾现象，从而改善残像影响，增强面板的信耐性。
如图3所示，做为一种可能的方法实施例，所述方法具体为：
S1、参考图1a，在基板10上依次沉积第一金属基层11、绝缘基层12、半导体有源基层13；所述第一金属基层11覆盖于所述基板10的上方，所述绝缘基层12覆盖于所述第一金属基层11的上方，所述半导体有源基层13覆盖于所述绝缘基层12的上方，从而所述基板10、第一金属基层11、绝缘基层12与所述第一金属基层11形成整板结构。
S2、参考图1b，在半导体有源基层13上方通过半色调掩膜光罩进行一次曝光，在半导体有源基层13上方形成栅极金属层111、栅极绝缘层121、半导体有源层131，在平行于基板的方向上，所述的半导体有源层131的宽度小于所述栅极金属层111的宽度；所述栅极绝缘层121的宽度也小于所述栅极金属层111的宽度；具体的，在所述半导体有源基层13上涂布光阻材料层，采用半色调掩膜光罩对光阻材料层进行图案化处理，得到所述半导体有源层131图案、栅极绝缘层121图案以及栅极金属层111图案，然后对所述第一金属基层11、绝缘基层12以及半导体有源基层13进行蚀刻，依次获得所述栅极金属层111、栅极绝缘层121以及半导体有源层131，清除残留的光阻材料层。更具体的，首先蚀刻出半导体有源层131，然后蚀刻出栅极绝缘层121，最后蚀刻出栅极金属层111；
S31：参考图1c，在所述基板、所述栅极金属层111、所述栅极 绝缘层121以及所述半导体有源层131上方沉积第一钝化基层(图中未示出)；
S32：在所述第一钝化基层上方通过第一光罩形成第一钝化层141，所述第一钝化层141在对应源极金属层161、漏极金属层162的位置处分别形成有暴露半导体有源层131的过孔142；所述两个过孔142之间的第一钝化基层为沟道保护层18；所述沟道保护层18覆盖所述半导体有源层131上两个过孔142间没有被所述源极金属层161与所述漏极金属层162遮挡的部分；具体的，在所述第一钝化基层上涂布光阻材料层，通过第一光罩对光阻材料层进行图案化处理，得到所述第一钝化层141图案，然后采用干法蚀刻对所述第一钝化层141进行蚀刻，获得所述第一钝化层141，清除残留的光阻材料层；
S33：参考图1d，在所述第一钝化层141上依次沉积第二金属基层16及第二钝化基层17；
S34：参考图1e，在所述第二钝化基层17上涂布光阻材料层，通过第二光罩对光阻材料进行图案化处理，先以涂布的光阻材料层为保护层蚀刻出所述第二钝化层171的图案，再以形成的第二钝化层171的图案为保护层，通过一次湿法蚀刻将所述第二金属基层16蚀刻断开，形成所述源极金属层161及漏极金属层162，之后，清除光阻材料层；所述源极金属层161、漏极金属层162分别通过过孔142与半导体有源层131连通；所述第二钝化层171在对应漏极金属层162的上方形成接触孔172以暴露漏极金属层162；这样的设计只通过一次曝光显影制成第二钝化层171和源极金属层161及漏极金属层162，节省了制程时间；
S35：参考图1f，在所述第二钝化层171上沉积透明电极基层(ITO)，并通过第三光罩形成像素电极层(ITO)；所述像素电极层19通过接触孔172与所述漏极金属层162连通，以形成TFT开关。
参考图1f，本申请还提供一种显示面板，所述的显示面板包括阵列基板和与所述阵列基板对置的第二基板；所述的阵列基板10，包括：
基板；
栅极金属层111，所述栅极金属层111设置于所述基板上；
栅极绝缘层121，所述栅极绝缘层121设置于所述栅极金属层111上；
半导体有源层131，所述半导体有源层131设置于所述栅极绝缘层121上；
源极金属层161和漏极金属层162，设置在所述半导体有源层131上；
其中，在平行于基板的方向上，所述的半导体有源层131的宽度小于所述栅极金属层111的宽度。
具体来说，所述的阵列基板10，包括：
基板；
栅极金属层111，所述栅极金属层111设置于所述基板上；
栅极绝缘层121，所述栅极绝缘层121设置于所述栅极金属层111上；
半导体有源层131，所述半导体有源层131设置于所述栅极绝缘层121上；在平行于基板的方向上，所述的半导体有源层131的宽度小于所述栅极金属层111的宽度；
第一钝化层141，所述第一钝化层141覆盖所述栅极金属层111、栅极绝缘层121及半导体有源层131设置，所述第一钝化层141在所述半导体有源层131的上方形成有两个过孔142，露出所述半导体有源层131；
源极金属层161和漏极金属层162，设置在所述半导体有源层131上；
所述的源极金属层161覆盖设置于所述第一钝化层141一侧，所述源极金属层161一端设置在一过孔142内与半导体有源层131相接触；
所述的漏极金属层162覆盖设置于所述第一钝化层141的另一侧，所述漏极金属层162一端设置在另一过孔142内与半导体有源层131相接触；
所述两个过孔142之间设有沟道保护层18；所述沟道保护层18覆盖所述半导体有源层131上两个过孔142间没有被所述源极金属层161与所述漏极金属层162遮挡的部分；
第二钝化层171，分别覆盖所述源极金属层161与所述漏极金属层162进行设置；所述第二钝化层171在对应漏极金属层162的上方形成接触孔172以暴露所述漏极金属层162；
像素电极层19，覆盖设置于位于所述漏极金属层162上方的所述第二钝化层171上，所述像素电极层19通过接触孔172与所述漏极金属层162连通。
可选的，所述栅极绝缘层121宽度小于所述栅极金属层111宽度，所述半导体有源层131宽度小于所述栅极绝缘层121宽度。这样，使所述钝化层充分覆盖住所述栅极金属层111、栅极绝缘层121以及半导体有源层131，而且因为所述半导体有源层131宽度较小，所述源极金属层161与所述漏极金属层162遮挡住所述半导体有源层131的两端。
具体的，所述栅极绝缘层121的宽度也小于所述栅极金属层111的宽度，所述栅极绝缘层121的宽度和所述的半导体有源层131的宽度一致，与所述半导体有源层131的侧边为平滑过渡，形成一梯形台的结构。
本申请所述的显示面板的阵列基板由于使用一次光罩制程形成栅极金属层111、栅极绝缘层121、半导体有源层131，而在半导体有源层131之上经过一次光罩制程形成第一钝化层141，并在第一钝化层141上形成源极金属层161、漏极金属层162，相对于4光罩制程来说，半导体有源层131的图案是直接根据光罩图案形成的，不依赖于其他层的图案，使得使用4mask工艺也能做出在平行于基板的方向上，半导体有源层131的宽度小于所述栅极金属层111的宽度的TFT，减小了半导体有源层131的宽度，显著改善掺硅层拖尾现象，从而改善残像影响，增强面板的信耐性。
在半导体有源层131上未被所述源极金属层与所述漏极金属层162遮挡的部分形成沟道保护层18，使得TFT的沟道区域被源极金属层、漏极金属层162和沟道保护层18全方位遮挡，使得面板中的光线不会照射到TFT的沟道区域的半导体有源层131，减小光电流的产生。而其制程的设计使得沟道区域的表面在进行后续制程时先由第一钝化基层对其表面进行覆盖保护，在进行后续的制程时由第一钝化基层形成的沟道保护层18阻隔了其他材料对沟道区域的影响，不进行背沟道蚀刻，沟道区域的界面状态不会因为后续蚀刻而变差，进而降低TFT的漏电。
其中，所述栅极绝缘层121是氧化硅薄膜或者是氮化硅薄膜。
本申请的面板是TN面板(全称为Twisted Nematic，即扭曲向 列型面板)、IPS面板(In-Plane Switching，平面转换)、VA面板(Multi-domain Vertica Aignment，多象限垂直配向技术)，当然，或者是其他类型的面板，适用即可。
以上内容是结合具体的实施方式对本申请所作的详细说明，不能认定本申请的具体实施方式只局限于这些说明。对于本申请所属技术领域的普通技术人员来说，在不脱离本申请构思的前提下，做出若干简单推演或替换，都应当视为属于本申请的保护范围。

Claims (20)

  1. 一种阵列基板的制造方法，所述方法包括以下步骤：
    在基板上依次沉积第一金属基层、绝缘基层、半导体有源基层；
    在半导体有源基层上方通过一次光罩制程形成栅极金属层、栅极绝缘层和半导体有源层，在平行于基板的方向上，所述的半导体有源层的宽度小于所述栅极金属层的宽度；
    在所述栅极金属层、所述栅极绝缘层以及所述半导体有源层上方经过一次光罩制程形成第一钝化层，并在第一钝化层上形成源极金属层、漏极金属层；
    形成与漏极金属层导通的像素电极层。
  2. 如权利要求1所述的一种阵列基板的制造方法，其中，所述的在半导体有源基层上方通过一次光罩制程形成栅极金属层、栅极绝缘层、半导体有源层的步骤中，通过半色调掩膜光罩进行一次曝光，使得在半导体有源基层上方形成栅极金属层、栅极绝缘层、半导体有源层，在平行于基板的方向上，所述的半导体有源层的宽度小于所述栅极金属层的宽度。
  3. 如权利要求2所述的一种阵列基板的制造方法，其中，所述通过半色调掩膜光罩进行一次曝光的步骤中，所述的半色调掩膜光罩对应所述栅极金属层未被半导体有源层覆盖的区域为半色调区域。
  4. 如权利要求2所述的一种阵列基板的制造方法，其中，所述的在半导体有源基层上方通过一次光罩制程形成栅极金属层、栅极绝缘层、半导体有源层的步骤中：
    在所述半导体有源基层上涂布光阻材料层，采用半色调掩膜光罩对光阻材料层进行图案化处理，得到所述半导体有源层图案、栅极绝缘层图案以及栅极金属层图案；
    对所述第一金属基层、绝缘基层以及半导体有源基层进行蚀刻，依次获得所述栅极金属层、栅极绝缘层以及半导体有源层；
    清除残留的光阻材料层。
  5. 如权利要求1所述的一种阵列基板的制造方法，其中，所述 栅极金属层、所述栅极绝缘层以及所述半导体有源层上方经过一次光罩制程形成第一钝化层，并在第一钝化层上形成源极金属层、漏极金属层的步骤中，还包括在所述的半导体有源层上未被所述源极金属层与所述漏极金属层遮挡的部分形成沟道保护层的步骤。
  6. 如权利要求1所述的一种阵列基板的制造方法，其中，所述栅极金属层、所述栅极绝缘层以及所述半导体有源层上方经过一次光罩制程形成第一钝化层，并在第一钝化层上形成源极金属层、漏极金属层的步骤中，包括以下步骤：
    在所述基板、所述栅极金属层、所述栅极绝缘层以及所述半导体有源层上方沉积第一钝化基层；
    在所述第一钝化基层上方通过第一光罩形成第一钝化层，所述第一钝化层在对应源极金属层、漏极金属层的位置处分别形成有暴露半导体有源层的过孔；所述两个过孔之间的第一钝化基层为沟道保护层；所述沟道保护层覆盖所述半导体有源层上两个过孔间没有被所述源极金属层与所述漏极金属层遮挡的部分；
    在所述第一钝化层上依次沉积第二金属基层及第二钝化基层；
    在所述第二钝化基层上方通过第二光罩形成源极金属层、漏极金属层以及第二钝化层，所述源极金属层、漏极金属层分别通过过孔与半导体有源层连通；所述第二钝化层在对应漏极金属层的上方形成接触孔以暴露漏极金属层；
    所述形成与漏极金属层导通的像素电极层的步骤包括：在所述第二钝化层上沉积透明电极基层，并通过第三光罩形成像素电极层；所述像素电极层通过接触孔与所述漏极金属层连通。
  7. 如权利要求6所述的一种阵列基板的制造方法，其中，所述第一钝化基层上方通过第一光罩形成第一钝化层的步骤包括：
    在所述第一钝化基层上涂布光阻材料层，通过第一光罩对光阻材料层进行图案化处理，得到所述第一钝化层图案，然后采用干法蚀刻对所述第一钝化层进行蚀刻，获得所述第一钝化层，清除残留的光阻材料层。
  8. 如权利要求6所述的一种阵列基板的制造方法，其中，所述第二钝化基层上方通过第二光罩形成源极金属层、漏极金属层以及第二钝化层的步骤包括：在所述第二钝化基层上涂布光阻材料层，通过第二光罩对光阻材料进行图案化处理，先以涂布的光阻材料层为保护层蚀刻出所述第二钝化层的图案，再以形成的第二钝化层的图案为保护层，通过一次湿法蚀刻将所述第二金属基层蚀刻断开，形成所述源极金属层及漏极金属层，之后清除光阻材料层。
  9. 一种阵列基板，包括：
    基板；
    栅极金属层，所述栅极金属层设置于所述基板上；
    栅极绝缘层，所述栅极绝缘层设置于所述栅极金属层上；
    半导体有源层，所述半导体有源层设置于所述栅极绝缘层上；
    源极金属层和漏极金属层，设置在所述半导体有源层上，
    其中，在平行于基板的方向上，所述的半导体有源层的宽度小于所述栅极金属层的宽度。
  10. 如权利要求9所述的一种阵列基板，其中，所述的阵列基板包括：
    第一钝化层，所述第一钝化层覆盖所述栅极金属层、栅极绝缘层及半导体有源层设置，所述第一钝化层在所述半导体有源层的上方形成有两个过孔，露出所述半导体有源层；
    所述的源极金属层覆盖设置于所述第一钝化层一侧，所述源极金属层一端设置在一过孔内与半导体有源层相接触；
    所述的漏极金属层覆盖设置于所述第一钝化层的另一侧，所述漏极金属层一端设置在另一过孔内与半导体有源层相接触；
    所述两个过孔之间设有沟道保护层；所述沟道保护层覆盖所述半导体有源层上两个过孔间没有被所述源极金属层与所述漏极金属层遮挡的部分。
  11. 如权利要求9所述的一种阵列基板，其中，所述的阵列基板包括：
    第二钝化层，分别覆盖所述源极金属层与所述漏极金属层进行设置；所述第二钝化层在对应漏极金属层的上方形成接触孔以暴露所述漏极金属层；
    像素电极层，覆盖设置于位于所述漏极金属层上方的所述第二钝化层上，所述像素电极层通过接触孔与所述漏极金属层连通。
  12. 如权利要求9所述的一种阵列基板，其中，所述源极金属层与所述漏极金属层遮挡住所述半导体有源层的两端。
  13. 如权利要求9所述的一种阵列基板，其中，所述栅极绝缘层的宽度小于所述栅极金属层的宽度，所述栅极绝缘层的宽度和所述的半导体有源层的宽度一致，与所述半导体有源层的侧边为平滑过渡，形成一梯形台的结构。
  14. 如权利要求9所述的一种阵列基板，其中，所述栅极绝缘层为氧化硅薄膜或氮化硅薄膜。
  15. 一种显示面板，包括阵列基板，及与所述阵列基板对置的第二基板，所述的阵列基板包括：
    基板；
    栅极金属层，所述栅极金属层设置于所述基板上；
    栅极绝缘层，所述栅极绝缘层设置于所述栅极金属层上；
    半导体有源层，所述半导体有源层设置于所述栅极绝缘层上；
    源极金属层和漏极金属层，设置在所述半导体有源层上；
    其中，在平行于基板的方向上，所述的半导体有源层的宽度小于所述栅极金属层的宽度。
  16. 如权利要求15所述的一种显示面板，其中，所述的阵列基板包括：
    第一钝化层，所述第一钝化层覆盖所述栅极金属层、栅极绝缘层及半导体有源层设置，所述第一钝化层在所述半导体有源层的上方形成有两个过孔，露出所述半导体有源层；
    所述的源极金属层覆盖设置于所述第一钝化层一侧，所述源极金属层一端设置在一过孔内与半导体有源层相接触；
    所述的漏极金属层覆盖设置于所述第一钝化层的另一侧，所述漏极金属层一端设置在另一过孔内与半导体有源层相接触；
    所述两个过孔之间设有沟道保护层；所述沟道保护层覆盖所述半导体有源层上两个过孔间没有被所述源极金属层与所述漏极金属层遮挡的部分。
  17. 如权利要求15所述的一种显示面板，其中，所述的阵列基板包括：
    第二钝化层，分别覆盖所述源极金属层与所述漏极金属层进行设置；所述第二钝化层在对应漏极金属层的上方形成接触孔以暴露所述漏极金属层；
    像素电极层，覆盖设置于位于所述漏极金属层上方的所述第二钝化层上，所述像素电极层通过接触孔与所述漏极金属层连通。
  18. 如权利要求15所述的一种显示面板，其中，所述源极金属层与所述漏极金属层遮挡住所述半导体有源层的两端。
  19. 如权利要求15所述的一种显示面板，其中，所述栅极绝缘层的宽度小于所述栅极金属层的宽度，所述栅极绝缘层的宽度和所述的半导体有源层的宽度一致，与所述半导体有源层的侧边为平滑过渡，形成一梯形台的结构。
  20. 如权利要求15所述的一种显示面板，其中，所述栅极绝缘层为氧化硅薄膜或氮化硅薄膜。
PCT/CN2018/111344 2018-09-03 2018-10-23 一种阵列基板的制造方法、阵列基板及显示面板 WO2020047957A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US16/311,179 US11152403B2 (en) 2018-09-03 2018-10-23 Method for manufacturing array substrate, array substrate and display panel

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201811021331.8 2018-09-03
CN201811021331.8A CN109524356B (zh) 2018-09-03 2018-09-03 一种阵列基板的制造方法、阵列基板及显示面板

Publications (1)

Publication Number Publication Date
WO2020047957A1 true WO2020047957A1 (zh) 2020-03-12

Family

ID=65771157

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2018/111344 WO2020047957A1 (zh) 2018-09-03 2018-10-23 一种阵列基板的制造方法、阵列基板及显示面板

Country Status (3)

Country Link
US (1) US11152403B2 (zh)
CN (1) CN109524356B (zh)
WO (1) WO2020047957A1 (zh)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111129037B (zh) 2019-12-25 2022-09-09 Tcl华星光电技术有限公司 Tft阵列基板及其制作方法
CN112635574B (zh) * 2020-12-31 2023-06-09 北海惠科光电技术有限公司 一种液晶显示面板、薄膜晶体管及其制备方法
CN113871346B (zh) * 2021-09-24 2023-05-30 深圳市华星光电半导体显示技术有限公司 阵列基板及其制备方法和显示面板

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102890378A (zh) * 2012-09-17 2013-01-23 京东方科技集团股份有限公司 一种阵列基板及其制造方法
CN104051472A (zh) * 2014-06-19 2014-09-17 京东方科技集团股份有限公司 一种显示装置、阵列基板及其制作方法
CN105448934A (zh) * 2012-08-23 2016-03-30 株式会社日本显示器 显示装置及其制造方法
CN105589276A (zh) * 2016-03-14 2016-05-18 深圳市华星光电技术有限公司 阵列基板、液晶显示面板及液晶显示装置
CN107658267A (zh) * 2017-09-15 2018-02-02 惠科股份有限公司 阵列基板的制造方法

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7952099B2 (en) * 2006-04-21 2011-05-31 Beijing Boe Optoelectronics Technology Co., Ltd. Thin film transistor liquid crystal display array substrate
US8329523B2 (en) * 2009-05-15 2012-12-11 Lg Display Co., Ltd. Array substrate for dislay device and method of fabricating the same
KR101725993B1 (ko) * 2009-12-22 2017-04-11 엘지디스플레이 주식회사 액정표시장치 제조방법
US9019440B2 (en) * 2011-01-21 2015-04-28 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing the same
US20190097063A1 (en) * 2017-09-28 2019-03-28 Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd. Esl tft substrate and fabrication method thereof

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105448934A (zh) * 2012-08-23 2016-03-30 株式会社日本显示器 显示装置及其制造方法
CN102890378A (zh) * 2012-09-17 2013-01-23 京东方科技集团股份有限公司 一种阵列基板及其制造方法
CN104051472A (zh) * 2014-06-19 2014-09-17 京东方科技集团股份有限公司 一种显示装置、阵列基板及其制作方法
CN105589276A (zh) * 2016-03-14 2016-05-18 深圳市华星光电技术有限公司 阵列基板、液晶显示面板及液晶显示装置
CN107658267A (zh) * 2017-09-15 2018-02-02 惠科股份有限公司 阵列基板的制造方法

Also Published As

Publication number Publication date
CN109524356B (zh) 2021-08-31
US11152403B2 (en) 2021-10-19
CN109524356A (zh) 2019-03-26
US20210225904A1 (en) 2021-07-22

Similar Documents

Publication Publication Date Title
WO2017166341A1 (zh) Tft基板的制作方法及制得的tft基板
WO2018210186A1 (zh) 薄膜晶体管及其制作方法、阵列基板和显示面板
US9190429B2 (en) Manufacturing method of array substrate
US11094799B2 (en) Thin film transistor and manufacturing method thereof, array substrate and display device
WO2019205440A1 (zh) Tft基板的制作方法及tft基板
WO2013189160A1 (zh) 阵列基板及其制作方法、显示装置
KR101775726B1 (ko) 액정표시장치 제조방법
WO2018090482A1 (zh) 阵列基板及其制备方法、显示装置
WO2020047957A1 (zh) 一种阵列基板的制造方法、阵列基板及显示面板
JP5917015B2 (ja) 薄膜トランジスタ表示板の製造方法
WO2019109473A1 (zh) Ffs模式阵列基板及其制造方法
WO2014117443A1 (zh) 氧化物薄膜晶体管阵列基板及其制作方法、显示面板
WO2018032670A1 (zh) Tft基板的制作方法
WO2017140058A1 (zh) 阵列基板及其制作方法、显示面板及显示装置
US20140206139A1 (en) Methods for fabricating a thin film transistor and an array substrate
WO2013143321A1 (zh) 阵列基板及其制造方法和显示装置
WO2020062426A1 (zh) 阵列基板及其制备方法和显示器件
US20190267493A1 (en) Thin film transistor, method of fabricating thin film transistor and array substrate
WO2013181915A1 (zh) Tft阵列基板及其制造方法和显示装置
WO2016026177A1 (zh) Tft基板的制作方法及其结构
US11894386B2 (en) Array substrate, manufacturing method thereof, and display panel
KR102224457B1 (ko) 표시장치와 그 제조 방법
WO2016201778A1 (zh) 阵列基板及其制造方法
WO2016161700A1 (zh) 一种薄膜晶体管阵列基板及其制造方法
KR20130066247A (ko) 박막 트랜지스터 표시판 및 그 제조 방법

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 18932711

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 18932711

Country of ref document: EP

Kind code of ref document: A1