CN107658267A - 阵列基板的制造方法 - Google Patents

阵列基板的制造方法 Download PDF

Info

Publication number
CN107658267A
CN107658267A CN201710833667.3A CN201710833667A CN107658267A CN 107658267 A CN107658267 A CN 107658267A CN 201710833667 A CN201710833667 A CN 201710833667A CN 107658267 A CN107658267 A CN 107658267A
Authority
CN
China
Prior art keywords
layer
amorphous silicon
silicon layer
groove
manufacture method
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201710833667.3A
Other languages
English (en)
Other versions
CN107658267B (zh
Inventor
何怀亮
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
HKC Co Ltd
Original Assignee
HKC Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by HKC Co Ltd filed Critical HKC Co Ltd
Priority to CN201710833667.3A priority Critical patent/CN107658267B/zh
Priority to US16/068,423 priority patent/US10453963B2/en
Priority to PCT/CN2018/073601 priority patent/WO2019052108A1/zh
Publication of CN107658267A publication Critical patent/CN107658267A/zh
Application granted granted Critical
Publication of CN107658267B publication Critical patent/CN107658267B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78609—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device for preventing leakage current
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78663—Amorphous silicon transistors
    • H01L29/78669—Amorphous silicon transistors with inverted-type structure, e.g. with bottom gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32131—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by physical means only
    • H01L21/32132—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by physical means only of silicon-containing layers

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Plasma & Fusion (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Thin Film Transistor (AREA)

Abstract

本发明一种阵列基板的制造方法，阵列基板的制造方法包括：提供一第一基底；将一栅极层形成于所述第一基底上；将一栅极绝缘层形成于所述第一基底上，并覆盖所述栅极层；将一非晶硅层形成于所述栅极绝缘层上；将一金属层形成于所述非晶硅层上；将一感光性光阻层形成于所述金属层上；将所述非晶硅层透过惰性气体或氮离子体进行蚀刻而形成一凹槽；进而形成一源极层和一漏极层；剥离所述感光性光阻层；以及将一钝化层形成于所述源极层上；其中在所述感光性光阻层进行一烘烤制程，使感光性光阻层发生一定程度的流淌，产生一保护层，以便覆盖非主动开关沟道区域的金属层。

Description

阵列基板的制造方法
技术领域
本发明涉及一种制造方式，特别是涉及一种阵列基板的制造方法。
背景技术
随着科技进步，具有省电、无幅射、体积小、低耗电量、平面直角、高分辨率、画 质稳定等多项优势的液晶显示器，尤其是现今各式信息产品如：手机、笔记本电脑、数字相机、PDA、液晶屏幕等产品越来越普及，亦使得显示器的需求量大大提升。因此如何满足日益要求高分辨率的画素设计，且具有高画质、空间利用效率佳、低消耗功率、无辐射等优越特性的开关阵列液晶显示器(Thin Film Transistor Liquid Crystal Display，TFT-LCD)已逐渐成 为市场的主流。其中，阵列基板为组立显示器的重要构件之一。
而非晶硅(a-Si:H)薄膜晶体管(TFT)被应用在显示面板的驱动背板中，其工艺技术相对 稳定，技术较为成熟，低廉的价格使其广泛应用在目前LCD显示行业。近几年发展起来的 四道光罩(4PEP)技术进一步提高了非晶硅(a-Si:H)薄膜晶体管(TFT)背板的时间与成本优势， 各大面板厂商逐渐开始大规模量产。然而相对于稳定成熟的五道光罩(5PEP)制程与四道光罩 (4PEP)制程还存在一些待优化克服的问题。在四道光罩(4PEP)两次湿刻和两次干蚀刻中，由 于非晶硅(a-Si:H)与源极层(M2)之间的线宽(CD Bias)差异(源极层线宽损耗较大，非晶硅线 宽损耗较小)会引起非晶硅层在源极层下面有凸出来的尾端，这个尾端对薄膜晶体管(TFT) 本身的漏电流影响较大，从而影响显示面板的质量。
发明内容
为了解决上述技术问题，本发明的目的在于，提供一种阵列基板的制造方法，将可以减小由于源极层的湿蚀刻与非晶硅层干蚀刻的线宽差异所产生的非晶硅层尾端，能有效防 止由于尾端引起的薄膜晶体管(TFT)光漏电流，保证面板显示质量。
本发明的目的及解决其技术问题是采用以下技术方案来实现的。依据本发明提出的 一种阵列基板的制造方法，包括：提供一第一基底；将一栅极层形成于所述第一基底上；将 一栅极绝缘层形成于所述第一基底上，并覆盖所述栅极层；将一非晶硅层形成于所述栅极绝 缘层上；将一金属层形成于所述非晶硅层上；将一感光性光阻层形成于所述金属层上；将所 述非晶硅层透过惰性气体或氮离子体进行蚀刻而形成一凹槽；进而形成一源极层和一漏极 层；剥离所述感光性光阻层；以及将一钝化层形成于所述源极层上；其中在所述感光性光阻 层进行一烘烤制程，使感光性光阻层发生一定程度的流淌，产生一保护层，以便覆盖非主动 开关沟道区域的金属层。
本发明的另一目的一种阵列基板的制造方法，包括：提供一第一基底；将一栅极层形成于所述第一基底上；将一栅极绝缘层形成于所述第一基底上，并覆盖所述栅极层；将一非晶硅层形成于所述栅极绝缘层上；将一金属层形成于所述非晶硅层上；将一感光性光阻层 形成于所述金属层上；将所述非晶硅层透过惰性气体或氮离子体进行蚀刻而形成一凹槽，并 形成源极层和漏极层；剥离所述感光性光阻层；以及将一钝化层形成于所述源极层上；其中 所述将所述非晶硅层透过惰性气体或氮离子体进行蚀刻而形成一凹槽的步骤包括进行第一次 湿蚀刻、第一次干蚀刻、第二次干蚀刻、第二次湿蚀刻及第三次干蚀刻；其中所述光罩为灰 阶光罩或半色调光罩。
本发明解决其技术问题还可采用以下技术措施进一步实现。
在本发明的一实施例中，所述制造方法，所述将一感光性光阻层形成于该些源极层 上的步骤包括：涂布所述感光性光阻层，使其膜厚≥2.5μm；通过光罩进行曝光处理，同时 减小主动开关沟道处对应的所述感光性光阻层的膜厚，并在所述主动开关的沟道处形成一个 凹槽，使得所述凹槽的膜厚≤0.5μm。
在本发明的一实施例中，所述制造方法，所述将所述非晶硅层透过惰性气体或氮离 子体与蚀刻而形成一凹槽的步骤包括：进行第一次湿蚀刻包括：对所述金属层进行第一次湿 蚀刻，并蚀刻掉未被所述感光性光阻层所涵盖的所述金属层。
在本发明的一实施例中，所述制造方法，所述将所述非晶硅层透过惰性气体或氮离 子体与蚀刻而形成一凹槽的步骤包括：进行第一次干蚀刻包括：对所述非晶硅层进行蚀刻， 蚀刻掉未被所述感光性光阻层所涵盖的所述非晶硅层；其中对所述感光性光阻层进行一烘烤 制程，用来包住所述金属层；以及进行第二次干蚀刻包括：对所述感光性光阻层的主动开关 沟道处进行灰化，并蚀刻掉所述感光性光阻层的所述凹槽，暴露出部分所述金属层。
在本发明的一实施例中，所述制造方法，所述将所述非晶硅层透过惰性气体或氮离子 体与蚀刻而形成一凹槽的步骤包括：进行第二次湿蚀刻包括：对主动开关沟道处的暴露出的 部分所述金属层进行蚀刻，形成所述源极层和所述漏极层，并暴露出部分所述非晶硅层。
在本发明的一实施例中，所述制造方法，所述将所述非晶硅层透过惰性气体或氮离 子体与蚀刻而形成一凹槽的步骤包括：进行第三次干蚀刻包括：透过惰性气体或氮离子体， 蚀刻暴露出的部分所述非晶硅层，使所述非晶硅层形成一凹槽。
在本发明的一实施例中，所述制造方法，所述惰性气体可为氦气、氖气、氩气、氪气、氙气或氡气。
在本发明的一实施例中，所述制造方法，所述氮离子体中的氮元素可为氮族元素及 其化合物所提供。
在本发明的一实施例中，所述制造方法，所述栅绝缘层的材料为氮化硅，氧化硅，氮氧化硅，氧化铝，或氧化铪。
本发明可以减小由于源极层湿蚀刻的线宽差异较大与非晶硅层线宽差异较小差异引 起的非晶硅层边缘尾端突出部分，较小的边缘尾端突出部分对抑制主动开关组件漏电流有明 显效果；其中并对所述感光性光阻层进行一烘烤制程，将使部分所述感光性光阻层转变成具 有液体型态，而部分所述具有液体型态的感光性光阻用来包住所述金属层及所述非晶硅层。
附图说明
图1是范例性的在非晶硅层中具有多出的尾端在阵列基板中横截面示意图。
图2a至图2i是本发明一实施例的显示面板制造方法的横截面示意图。
图3是本发明一实施例一种阵列基板的制造方法流程图。
图3a是本发明一实施例一种非晶硅层在阵列基板的制造方法流程图。
具体实施方式
以下各实施例的说明是参考附加的图式，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如「上」、「下」、「前」、「后」、「左」、「右」、「内」、「外」、 「侧面」等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明， 而非用以限制本发明。
附图和说明被认为在本质上是示出性的，而不是限制性的。在图中，结构相似的单元是以相同标号表示。另外，为了理解和便于描述，附图中示出的每个组件的尺寸和厚度是任意示出的，但是本发明不限于此。
在附图中，为了清晰起见，夸大了层、膜、面板、区域等的厚度。在附图中，为了 理解和便于描述，夸大了一些层和区域的厚度。将理解的是，当例如层、膜、区域或基底的 组件被称作“在”另一组件“上”时，所述组件可以直接在所述另一组件上，或者也可以存在中间组件。
另外，在说明书中，除非明确地描述为相反的，否则词语“包括”将被理解为意指包括 所述组件，但是不排除任何其它组件。此外，在说明书中，“在......上”意指位于目标组件上 方或者下方，而不意指必须位于基于重力方向的顶部上。
为更进一步阐述本发明为达成预定发明目的所采取的技术手段及功效，以下结合附 图及较佳实施例，对依据本发明提出的一种阵列基板的制造方法，其具体实施方式、结构、 特征及其功效，详细说明如后。
图1为范例性的在非晶硅层中具有多出的尾端在阵列基板中横截面示意图。请参照 图1，一种显示面板10，包括：一第一基底110；多条栅极层120，形成于所述第一基底 110上；一栅极绝缘层130，形成于所述第一基底110上，并覆盖该些栅极层120；一非晶 硅层140，形成于所述栅极绝缘层130上；多条源极层150，形成于所述非晶硅层140上； 以及一钝化层170，形成于所述栅极绝缘层130上，并覆盖该些源极层150及所述非晶硅层 140上；其中所述非晶硅层140的边缘尾端140B突出部分对主动开关组件将会造成漏电流 效果。
图2a至图2i本发明一实施例的显示面板制造方法的横截面示意图。请参照图2e及图2h，一种阵列基板20，包括：一第一基底110；多条栅极层120，形成于所述第一基底 110上；一栅极绝缘层130，形成于所述第一基底110上，并覆盖该些栅极层120；一非晶 硅层140、140A，形成于所述栅极绝缘层130上，并透过惰性气体或氮离子体与蚀刻而形成 一凹槽140C；多条源极层150、150A，形成于所述非晶硅层140、140A上；以及一感光性 光阻层160、160A、160B，形成于该些源极层150、150A上；其中所述感光性光阻层160、 160A、160B可包住该些源极层150、150A及所述非晶硅层140、140A。
请参照图2h，在一实施例中，所述惰性气体可为氦气、氖气、氩气、氪气、氙气或 氡气。
请参照图2h，在一实施例中，所述氮离子体中的氮元素为氮族元素及其化合物所提 供。
请参照图2h，在一实施例中，所述栅绝缘层130的材料为氮化硅，氧化硅，氮氧化硅，氧化铝，或氧化铪。
请参照图2a至图2h，一种阵列基板20的制造方法，包括：提供一第一基底110；将一栅极层120形成于所述第一基底110上；将一栅极绝缘层130形成于所述第一基底110 上，并覆盖所述栅极层120；将一非晶硅层140形成于所述栅极绝缘层130上；将一金属层 150形成于所述非晶硅层140上；将一感光性光阻层160形成于所述金属层150上；将所述 非晶硅层140透过惰性气体或氮离子体进行蚀刻而形成一凹槽140C；进而形成一源极层 150和一漏极层150；剥离所述感光性光阻层160；以及将一钝化层170形成于所述源极层 150上；其中在第一次干刻后对所述感光性光阻层160进行烘烤制程，使感光性光阻层160 发生一定程度的流淌，产生一保护层，以便覆盖非主动开关沟道区域的金属层150，有效防 止金属层150被第二次湿刻造成金属层150线宽差异过大。
请参照图2b，在一实施例中，所述制造方法，所述将一感光性光阻层160形成于该些源极层150上的步骤包括：涂布所述感光性光阻层160，使其膜厚d1≥2.5μm；通过光罩 进行曝光处理，同时减小主动开关沟道处对应的所述感光性光阻层160C的膜厚d2，并在所 述主动开关的沟道处形成一个凹槽160C，使得所述凹槽的膜厚d2≤0.5μm。
请参照图2a至图2h，在一实施例中，所述制造方法，所述将所述非晶硅层140透过惰性气体或氮离子体与蚀刻而形成一凹槽140C的步骤包括：进行第一次湿蚀刻包括：对所述金属层150进行第一次湿蚀刻，并蚀刻掉未被所述感光性光阻层160所涵盖的所述金属层150；进行第一次干蚀刻包括：对所述非晶硅层140进行蚀刻，蚀刻掉未被所述感光性光阻层160所涵盖的所述非晶硅层140；其中对所述感光性光阻层160进行一烘烤制程，将使部分所述感光性光阻层160转变成具有液体型态，而部分所述具有液体型态的感光性光阻160用来包住所述金属层150及所述非晶硅层140；进行第二次干蚀刻包括：对所述感光性光阻层160C的主动开关沟道处进行灰化，并蚀刻掉所述感光性光阻层160的所述凹槽160C，暴露出部分所述金属层150；进行第二次湿蚀刻包括：对主动开关沟道处的暴露出的部分所述金属层150B、150C进行蚀刻，形成所述源极层150和所述漏极层150，并暴露出部分所述 非晶硅层140；以及进行第三次干蚀刻包括：透过惰性气体或氮离子体，蚀刻暴露出的部分 所述非晶硅层140，使所述非晶硅层形成一凹槽140C。
请参照图2h，在一实施例中，所述制造方法，所述惰性气体可为氦气、氖气、氩 气、氪气、氙气或氡气。
请参照图2h，在一实施例中，所述制造方法，所述氮离子体中的氮元素为氮族元素及其化合物所提供。
在一实施例中，所述制造方法，所述光罩为灰阶光罩或半色调光罩。
多灰阶光罩，可分为灰色光罩(Gray-tone mask)和半色调光罩(Half tone mask)2种。灰 色光罩是制作出曝光机分辨率以下的微缝，再藉由此微缝部位遮住一部份的光源，以达成半 曝光的效果。另一方面，半色调光罩是利用「半透过」的膜，来进行半曝光。因为以上两种 方式皆是在1次的曝光过程后即可呈现出「曝光部分」「半曝光部分」及「未曝光部分」的 3种的曝光层次，故在显影后能够形成2种厚度的光阻(藉由利用这样的光阻厚度差异、便 可以较一般少的片数下将图形转写至面板基板上，并达成面板生产效率的提升)。若为半色 调光罩则光罩成本会略高于一般光罩。
图3为本发明一实施例一种阵列基板的制造方法流程图。请参照图3，在流程S310中，提供一第一基底。
请参照图3，在流程S320中，将一栅极层形成于所述第一基底上。
请参照图3，在流程S330中，将一栅极绝缘层形成于所述第一基底上，并覆盖所述栅极层。
请参照图3，在流程S340中，将一非晶硅层形成于所述栅极绝缘层上。
请参照图3，在流程S350中，将一金属层形成于所述非晶硅层上。
请参照图3，在流程S360中，将一感光性光阻层形成于所述金属层上，涂布所述感光性光阻层，使其膜厚≥2.5μm；通过光罩进行曝光处理，同时减小主动开关沟道处对应的所述感光性光阻层的膜厚，并在所述主动开关的沟道处形成一个凹槽，使得所述凹槽的膜厚 ≤0.5μm。
请参照图3，在流程S370中，将所述非晶硅层透过惰性气体或氮离子体进行蚀刻而形成一凹槽，并形成源极层和漏极层，将进行第一次湿蚀刻、第一次干蚀刻、第二次干蚀刻、第二次湿蚀刻及第三次干蚀刻。
请参照图3，在流程S380中，剥离所述感光性光阻层，将一钝化层形成于所述源极层上。
图3a是本发明一实施例一种非晶硅层在阵列基板的制造方法流程图。请参照图3a， 在流程S371中，进行第一次湿蚀刻包括：对所述金属层进行第一次湿蚀刻，并蚀刻掉未被 所述感光性光阻层所涵盖的所述金属层。
请参照图3a，在流程S372中，进行第一次干蚀刻包括：对所述非晶硅层进行蚀刻，蚀刻掉未被所述感光性光阻层所涵盖的所述非晶硅层。
请参照图3a，在流程S373中，对所述感光性光阻层进行一烘烤制程，使感光性光阻层发生一定程度的流淌，以便覆盖非主动开关沟道区域的金属层。
请参照图3a，在流程S374中，进行第二次干蚀刻包括：对所述感光性光阻层的主动开关沟道处进行灰化，并蚀刻掉所述感光性光阻层的所述凹槽，暴露出部分所述金属层。
请参照图3a，在流程S375中，进行第二次湿蚀刻包括：对主动开关沟道处的暴露出的部分所述金属层进行蚀刻，形成所述源极层和所述漏极层，并暴露出部分所述非晶硅层。
请参照图3a，在流程S376中，进行第三次干蚀刻包括：透过惰性气体或氮离子体，蚀刻暴露出的部分所述非晶硅层，使所述非晶硅层形成一凹槽。
在一实施例中，一种阵列基板20的制造方法，包括：提供一第一基底110；将一栅极层120形成于所述第一基底110上；将一栅极绝缘层130形成于所述第一基底110上，并 覆盖所述栅极层120；将一非晶硅层140形成于所述栅极绝缘层130上；将一金属层150形 成于所述非晶硅层140上；将一感光性光阻层160形成于所述金属层150上；将所述非晶硅 层140透过惰性气体或氮离子体进行蚀刻而形成一凹槽140C，并形成源极层150和漏极层 150；以及剥离所述感光性光阻层160；将一钝化层170形成于所述源极层150上；其中所 述将所述非晶硅层140透过惰性气体或氮离子体进行蚀刻而形成一凹槽140C的步骤包括进 行第一次湿蚀刻、第一次干蚀刻、第二次干蚀刻、第二次湿蚀刻及第三次干蚀刻；其中所述 光罩为灰阶光罩或半色调光罩。
在一实施例中，一种显示面板的制造方法，包括：提供一第一基底110；提供一第二基底(图未示)，与所述第一基底110相对设置；以及将包括所述的阵列基板20的制造方法。
请参照图2h及图2i，在本发明一实施例中，一种显示面板30，包括：一阵列基板20，包括：一阵列基板20，包括：一第一基底110；多条栅极层120，形成于所述第一基底 110上；一栅极绝缘层130，形成于所述第一基底110上，并覆盖所述栅极层120；一非晶 硅层140，形成于所述栅极绝缘层130上，其中，所述非晶硅层140具有一凹槽140C；一 源极层150及一漏极层150，形成于所述非晶硅层140上；一钝化层170，形成于所述栅极 绝缘层130上，并覆盖所述源极层150，所述漏极层150及所述非晶硅层140上；一对向基 板(图未示)，包括：一第二基底(图未示)；所述阵列基板20与所述对向基板对向设置，其中 该些光间隔物(图未示)位于所述对向基板以及所述阵列基板20之间；一透明电极层(图未 示)，设置在所述第二基底上。
请参照图2h，在一实施例中，所述惰性气体可为氦气、氖气、氩气、氪气、氙气或 氡气。
请参照图2h，在一实施例中，所述氮离子体中的氮元素为氮族元素及其化合物所提 供。
请参照图2h，在一实施例中，所述栅绝缘层130的材料为氮化硅，氧化硅，氮氧化硅，氧化铝，或氧化铪。
请参照图2i，在本发明一实施例中，一种显示装置，包括：一控制部件(举例：一多频段天线)(图未示)，还包括所述的显示面板30〔举例:QLED(Quantum Dots Light-Emitting Diode)面板或OLED(Organic Light-Emitting Diode)面板或LCD(LiquidCrystal Display)面板〕。
本发明可以减小由于源极层湿蚀刻的线宽差异较大与非晶硅层线宽差异较小差异引 起的非晶硅层边缘尾端突出部分，较小的边缘尾端突出部分对抑制主动开关组件漏电流有明 显效果。
“在一些实施例中”及“在各种实施例中”等用语被重复地使用。所述用语通常不是指相同的实施例；但它亦可以是指相同的实施例。“包含”、“具有”及“包括”等用词是 同义词，除非其前后文意显示出其它意思。
以上所述，仅是本发明的实施例而已，并非对本发明作任何形式上的限制，虽然本发明已以具体实施例揭露如上，然而并非用以限定本发明，任何熟悉本专业的技术人员，在不脱离本发明技术方案范围内，当可利用上述揭示的技术内容作出些许更动或修饰为等同变 化的等效实施例，但凡是未脱离本发明技术方案的内容，依据本发明的技术实质对以上实施 例所作的任何简单修改、等同变化与修饰，均仍属于本发明技术方案的范围内。

Claims (10)

1.一种阵列基板的制造方法，其特征在于，包括：
提供一第一基底；
将一栅极层形成于所述第一基底上；
将一栅极绝缘层形成于所述第一基底上，并覆盖所述栅极层；
将一非晶硅层形成于所述栅极绝缘层上；
将一金属层形成于所述非晶硅层上；
将一感光性光阻层形成于所述金属层上；
将所述非晶硅层透过惰性气体或氮离子体进行蚀刻而形成一凹槽；
进而形成一源极层和一漏极层；
剥离所述感光性光阻层；以及
将一钝化层形成于所述源极层上；
其中，在所述感光性光阻层进行一烘烤制程，使感光性光阻层发生一定程度的流淌，产生一保护层，以覆盖非主动开关沟道区域的金属层。
2.如权利要求1所述的阵列基板的制造方法，其特征在于，所述将一感光性光阻层形成于所述金属层上的步骤包括：
涂布所述感光性光阻层，使其膜厚≥2.5μm；
通过光罩进行曝光处理，同时减小主动开关沟道处对应的所述感光性光阻层的膜厚，并在所述主动开关的沟道处形成一个凹槽，使得所述凹槽的膜厚≤0.5μm。
3.如权利要求1所述的阵列基板的制造方法，其特征在于，所述将所述非晶硅层透过惰性气体或氮离子体进行蚀刻而形成一凹槽的步骤包括：
进行第一次湿蚀刻包括：
对所述金属层进行第一次湿蚀刻，并蚀刻掉未被所述感光性光阻层所涵盖的所述金属层。
4.如权利要求3所述的阵列基板的制造方法，其特征在于，所述将所述非晶硅层透过惰性气体或氮离子体进行蚀刻而形成一凹槽的步骤包括：
进行第一次干蚀刻包括：
对所述非晶硅层进行蚀刻，蚀刻掉未被所述感光性光阻层所涵盖的所述非晶硅层；
以及对所述感光性光阻层进行一烘烤制程，用来包住所述金属层；以及
进行第二次干蚀刻包括：
对所述感光性光阻层的主动开关沟道处进行灰化，并蚀刻掉所述感光性光阻层的所述凹槽，暴露出部分所述金属层。
5.如权利要求4所述的阵列基板的制造方法，其特征在于，所述将所述非晶硅层透过惰性气体或氮离子体进行蚀刻而形成一凹槽的步骤包括：
进行第二次湿蚀刻包括：
对主动开关沟道处的暴露出的部分所述金属层进行蚀刻，形成所述源极层和所述漏极层，并暴露出部分所述非晶硅层。
6.如权利要求5所述的阵列基板的制造方法，其特征在于，所述将所述非晶硅层透过惰性气体或氮离子体进行蚀刻而形成一凹槽的步骤包括：
进行第三次干蚀刻包括：
透过惰性气体或氮离子体，蚀刻暴露出的部分所述非晶硅层，使所述非晶硅层形成一凹槽。
7.如权利要求4所述的阵列基板的制造方法，其特征在于，所述惰性气体为氦气、氖气、氩气、氪气、氙气或氡气。
8.如权利要求4所述的阵列基板的制造方法，其特征在于，所述氮离子体中的氮元素为氮族元素及其化合物所提供。
9.如权利要求1所述的阵列基板的制造方法，其特征在于，所述栅绝缘层的材料为氮化硅，氧化硅，氮氧化硅，氧化铝，或氧化铪。
10.一种阵列基板的制造方法，其特征在于，包括：
提供一第一基底；
将一栅极层形成于所述第一基底上；
将一栅极绝缘层形成于所述第一基底上，并覆盖所述栅极层；
将一非晶硅层形成于所述栅极绝缘层上；
将一金属层形成于所述非晶硅层上；
将一感光性光阻层形成于所述金属层上；
将所述非晶硅层透过惰性气体或氮离子体进行蚀刻而形成一凹槽，并形成源极层和漏极层；
剥离所述感光性光阻层；以及
将一钝化层形成于所述源极层上；
其中，所述将所述非晶硅层透过惰性气体或氮离子体进行蚀刻而形成一凹槽的步骤包括进行第一次湿蚀刻、第一次干蚀刻、第二次干蚀刻、第二次湿蚀刻及第三次干蚀刻；其中所述光罩为灰阶光罩或半色调光罩。
CN201710833667.3A 2017-09-15 2017-09-15 阵列基板的制造方法 Active CN107658267B (zh)

Priority Applications (3)

Application Number Priority Date Filing Date Title
CN201710833667.3A CN107658267B (zh) 2017-09-15 2017-09-15 阵列基板的制造方法
US16/068,423 US10453963B2 (en) 2017-09-15 2018-01-22 Array substrate manufacturing method
PCT/CN2018/073601 WO2019052108A1 (zh) 2017-09-15 2018-01-22 阵列基板的制造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201710833667.3A CN107658267B (zh) 2017-09-15 2017-09-15 阵列基板的制造方法

Publications (2)

Publication Number Publication Date
CN107658267A true CN107658267A (zh) 2018-02-02
CN107658267B CN107658267B (zh) 2020-11-06

Family

ID=61129946

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201710833667.3A Active CN107658267B (zh) 2017-09-15 2017-09-15 阵列基板的制造方法

Country Status (3)

Country Link
US (1) US10453963B2 (zh)
CN (1) CN107658267B (zh)
WO (1) WO2019052108A1 (zh)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110429061A (zh) * 2019-08-19 2019-11-08 京东方科技集团股份有限公司 一种显示基板及其制作方法、显示装置
WO2020047957A1 (zh) * 2018-09-03 2020-03-12 重庆惠科金渝光电科技有限公司 一种阵列基板的制造方法、阵列基板及显示面板
CN114496737A (zh) * 2020-11-12 2022-05-13 长鑫存储技术有限公司 半导体器件及其制造方法

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107591415B (zh) * 2017-08-29 2021-08-06 惠科股份有限公司 一种阵列基板及其制造方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101211119A (zh) * 2006-12-25 2008-07-02 上海广电Nec液晶显示器有限公司 液晶显示装置制造方法以及在此方法中使用的掩模
CN101369539A (zh) * 2007-08-17 2009-02-18 株式会社半导体能源研究所 显示装置的制造方法
CN104934439A (zh) * 2015-04-28 2015-09-23 深圳市华星光电技术有限公司 Tft基板的制作方法及其结构

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20010046141A (ko) * 1999-11-10 2001-06-05 구본준 박막 트랜지스터 및 배선 제조방법
TWI330407B (en) * 2007-08-13 2010-09-11 Au Optronics Corp Method of manufacturing thin film transistor and display device applied with the same
JP5421550B2 (ja) * 2008-06-06 2014-02-19 株式会社ジャパンディスプレイ 表示装置

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101211119A (zh) * 2006-12-25 2008-07-02 上海广电Nec液晶显示器有限公司 液晶显示装置制造方法以及在此方法中使用的掩模
CN101369539A (zh) * 2007-08-17 2009-02-18 株式会社半导体能源研究所 显示装置的制造方法
CN104934439A (zh) * 2015-04-28 2015-09-23 深圳市华星光电技术有限公司 Tft基板的制作方法及其结构

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2020047957A1 (zh) * 2018-09-03 2020-03-12 重庆惠科金渝光电科技有限公司 一种阵列基板的制造方法、阵列基板及显示面板
US11152403B2 (en) 2018-09-03 2021-10-19 Chongqing Hkc Optoelectronics Technology Co., Ltd. Method for manufacturing array substrate, array substrate and display panel
CN110429061A (zh) * 2019-08-19 2019-11-08 京东方科技集团股份有限公司 一种显示基板及其制作方法、显示装置
CN110429061B (zh) * 2019-08-19 2022-12-20 京东方科技集团股份有限公司 一种显示基板及其制作方法、显示装置
CN114496737A (zh) * 2020-11-12 2022-05-13 长鑫存储技术有限公司 半导体器件及其制造方法

Also Published As

Publication number Publication date
US20190157460A1 (en) 2019-05-23
CN107658267B (zh) 2020-11-06
WO2019052108A1 (zh) 2019-03-21
US10453963B2 (en) 2019-10-22

Similar Documents

Publication Publication Date Title
US20220384531A1 (en) Display substrate and manufacturing method therefor, and display panel and display device
US11075230B2 (en) Thin film transistor, manufacturing method thereof, array substrate and display device
CN109300840B (zh) 显示基板及其制造方法、显示装置
CN107634035A (zh) 阵列基板的制造方法
CN107658267A (zh) 阵列基板的制造方法
US8895334B2 (en) Thin film transistor array substrate and method for manufacturing the same and electronic device
US12068330B2 (en) Touch array substrate and manufacturing method thereof
US10192993B2 (en) Thin film transfer, manufacturing method thereof, array substrate and manufacturing method thereof
KR101900170B1 (ko) 어레이 기판의 제조 방법, 어레이 기판 및 디스플레이 디바이스
EP2709159B1 (en) Fabricating method of thin film transistor, fabricating method of array substrate and display device
WO2015000255A1 (zh) 阵列基板、显示装置及阵列基板的制造方法
EP3252802B1 (en) Thin film transistor manufacturing method and array substrate manufacturing method
KR101630103B1 (ko) 어레이 기판, 그 제조 방법 및 어레이 기판을 포함하는 디스플레이 장치
US20170110587A1 (en) Array substrate and manufacturing method thereof, display panel, display device
US11315963B2 (en) Display substrate and method for preparing the same, and display device
KR101788488B1 (ko) 박막 트랜지스터 어레이 기판의 제조방법
CN103515375B (zh) 阵列基板及其制造方法、以及显示装置
US20210408063A1 (en) Array substrate and method of manufacturing same
US10957721B1 (en) Manufacturing method for CMOS LTPS TFT substrate
US10957713B2 (en) LTPS TFT substrate and manufacturing method thereof
US6558992B2 (en) Method to fabricate flat panel display
EP3163620B1 (en) Low temperature poly-silicon thin film transistor array substrate and manufacturing method therefor and display device
CN107134497B (zh) 薄膜晶体管及其制造方法、显示基板
US20110068333A1 (en) Pixel structure and method for manufacturing the same
US20240298505A1 (en) Display panel, display motherboard and display device

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant