JP6001336B2 - 薄膜トランジスタ及びアレイ基板の製造方法 - Google Patents
薄膜トランジスタ及びアレイ基板の製造方法 Download PDFInfo
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- 238000004519 manufacturing process Methods 0.000 title claims description 52
- 238000000034 method Methods 0.000 title claims description 44
- 239000000758 substrate Substances 0.000 title claims description 34
- 239000010409 thin film Substances 0.000 title claims description 30
- 239000004065 semiconductor Substances 0.000 claims description 25
- 238000000059 patterning Methods 0.000 claims description 20
- 238000002161 passivation Methods 0.000 claims description 16
- 239000000463 material Substances 0.000 claims description 11
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 32
- 238000010586 diagram Methods 0.000 description 9
- 238000011161 development Methods 0.000 description 3
- 239000004973 liquid crystal related substance Substances 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000000969 carrier Substances 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000002474 experimental method Methods 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910000838 Al alloy Inorganic materials 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
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Description
本実施例は、薄膜トランジスタ(TFT)の製造方法を提供する。図2A〜2Eに示すように、該方法は以下のステップを備える。
該ステップでは、ゲート電極202は、通常のパターニング法によって、形成されたゲート金属層をパターニングすることで形成される。ベース基板201は、ガラス基板、プラスチック基板、石英基板等であってもよい。配線層はソース・ドレイン電極を形成するために用いられる。ゲート金属層及び配線層はそれぞれ異なる材料を用いてもよい。材料として、例えば、アルミニウム、アルミニウム合金、銅、銅合金等の導電材料であってもよい。
該マスク206は、薄膜トランジスタのソース電極を形成するためのソース領域207Aと、薄膜トランジスタのドレイン電極を形成するためのドレイン領域207Bとを有し、ソース領域207Aとドレイン領域207Bとの間に、薄膜トランジスタのチャンネル領域208に対応するスリット209を有する。該スリット209の幅Lは露光装置の分解能より小さい。
本実施例は、アレイ基板の製造方法を提供する。該方法は以下のステップを備える。
ステップ1:図3Aに示すように、実施例1の方法で基板301にTFTを製造する。該TFTは、ゲート電極302、ゲート絶縁層303、ソース電極304A、ドレイン電極304B及び活性層305を備える。そして、活性層305にパッシベーション層306を形成する。
該TFTは、例えば画素のスイッチング素子に用いられる。
ステップ2:図3Bに示すように、前記TFTのドレイン電極304Bを露出するように、前記パッシベーション層306及び対応する活性層305にビアホール307を形成する。
ステップ3:図3Cに示すように、前記パッシベーション層306及び前記ビアホール307に画素電極308を形成する。画素電極308は該ビアホール307を介してドレイン電極304Bに電気的に接続される。
本実施例に係るアレイ基板の製造方法は、実施例1の方法でTFTを製造する。TFTを製造する工程において、ソース・ドレイン電極の形成及び活性層のパターニングに一つのマスクを共用したので、TFTの製造コストが低減されるとともに、該TFTを用いたアレイ基板の製造コストも低減された。
本実施例は、トップゲートのボトムコンタクト構造のTFTの製造方法を提供する。図4Aに示すように、該方法は以下のステップを備える。
ステップ1:基板401にソース電極402A及びドレイン電極402Bを形成する。
ステップ2:ソース電極402A及びドレイン電極402Bが形成されたベース基板401に、パターニングされた活性層403を形成する。ソース・ドレイン電極及びパターニングされた活性層の形成は、実施例1に記載のソース・ドレイン電極及びパターニングされた活性層の形成方法を用いる。この方法に関して、既に実施例1に詳しく説明したので、ここで言及しない。
ステップ3:パターニングされた活性層403に、ゲート絶縁層404及びゲート電極405をこの順に形成する。同様に、ここで、通常のパターニング技術によってゲート電極を形成してもよい。
本実施例は、アレイ基板の製造方法を提供する。図4Bに示すように、該方法は以下のステップを備える。
ステップ1:実施例3に記載の方法で基板401にトップゲートのボトムコンタクト構造のTFTを製造する。該TFTは、基板401に、下から上へとソース電極402A、ドレイン電極402B、活性層403、ゲート絶縁層404及びゲート電極405をこの順に備える。そして、該TFTにパッシベーション層406を形成する。該TFTは画素のスイッチング素子に用いられる。
ステップ2:該TFTのドレイン電極402Bを露光するように、パッシベーション層406及び対応するゲート絶縁層404、活性層403にビアホール407を形成する。
ステップ3:パッシベーション層406及びビアホール407に画素電極408を形成する。画素電極408は該ビアホール407を介してドレイン電極402Bに電気的に接続される。
本実施例は表示装置を提供し、製造工程において、上記の実施例1又は3に記載の方法で、例えば画素のスイッチング素子とする薄膜トランジスタ製造する。該表示装置は、例えば、液晶ディスプレイ、有機EL発光ディスプレイ及び電子ペーパーディスプレイ等を含む。
12、202、302、405 ゲート電極
13、203、303、404 ゲート絶縁層
14A、210A、304A、402A ソース電極
14B、210B、304B、402B ドレイン電極
15、214、305、403 活性層
204 配線層
205 フォトレジスト層
206 マスク
207A ソース領域
207B ドレイン領域
208 チャンネル領域
209 スリット
211 半導体層
212 第二のフォトレジスト層
213 ハーフ露光領域
306、406 パッシベーション層
307、407 ビアホール
308、408 画素電極
Claims (6)
- 薄膜トランジスタの製造方法であって、
ソース電極及びドレイン電極を製造する工程において、互いに間隔を空けたソース電極及びドレイン電極を形成するように、露光装置及びマスクによって、通常の露光量より大きい第一の露光量で配線層に対してパターニングする工程と、
前記パターニング工程を行った後の配線層に半導体層を形成する工程と、
活性層を形成するように、前記露光装置及び前記マスクによって、前記第一の露光量より小さい第二の露光量で前記半導体層に対してパターニングする工程と、を備え、
前記マスクは、前記ソース電極を形成するためのソース領域と、前記ドレイン電極を形成するためのドレイン領域と、前記ソース領域と前記ドレイン領域との間のスリットとを有し、前記スリットの幅は露光装置の分解能より小さいことを特徴とする薄膜トランジスタの製造方法。 - 前記ソース電極及びドレイン電極を形成する前に、さらに
ベース基板にゲート電極を形成する工程と、
前記ゲート電極が形成された基板にゲート絶縁層を形成する工程と、を備え、
前記ゲート絶縁層に、前記ソース電極及びドレイン電極が形成されることを特徴とする請求項1に記載の薄膜トランジスタの製造方法。 - 前記活性層にゲート絶縁層を形成する工程と、
前記ゲート絶縁層にゲート電極を形成する工程と、をさらに備えることを特徴とする請求項1に記載の薄膜トランジスタの製造方法。 - 前記露光装置の分解能が4μmである場合、前記マスクのスリットの幅が1.7μm〜3.5μmであることを特徴とする請求項1〜3のいずれか1項に記載の薄膜トランジスタの製造方法。
- 前記半導体層の材料は、非結晶シリコン、有機半導体材料、酸化物半導体材料及び低温多結晶シリコンのいずれか1種であることを特徴とする請求項1〜4のいずれか1項に記載の薄膜トランジスタの製造方法。
- アレイ基板の製造方法であって、
請求項1〜5のいずれか1項に記載の薄膜トランジスタの製造方法で製造された薄膜トランジスタにパッシベーション層を形成する工程と、
前記薄膜トランジスタの前記ドレイン電極を露光するように、前記パッシベーション層にビアホールを形成する工程と、
前記パッシベーション層上及び前記ビアホールに画素電極を形成する工程と、を備えることを特徴とするアレイ基板の製造方法。
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CN102832254B (zh) * | 2012-09-10 | 2016-04-06 | 京东方科技集团股份有限公司 | 一种阵列基板及其制造方法、显示面板 |
FR2998580B1 (fr) | 2012-11-26 | 2016-10-21 | Institut De Rech Pour Le Developpement Ird | Marqueurs moleculaires et methodes pour l'identification des genotypes de palmier dattier |
CN103107202B (zh) * | 2013-01-23 | 2016-04-27 | 深圳市华星光电技术有限公司 | 一种薄膜晶体管结构、液晶显示装置和一种制造方法 |
US8912542B2 (en) | 2013-01-23 | 2014-12-16 | Shenzhen China Star Optoelectronics Technology Co., Ltd. | TFT structure and LCD device |
CN105206626B (zh) * | 2015-11-09 | 2018-11-20 | 深圳市华星光电技术有限公司 | 阵列基板及其制备方法、显示装置 |
CN105720063B (zh) | 2016-04-13 | 2019-02-15 | 京东方科技集团股份有限公司 | 阵列基板及其制备方法、传感器和探测设备 |
CN107170756B (zh) * | 2017-05-24 | 2020-11-06 | 京东方科技集团股份有限公司 | 阵列基板、显示装置以及制备阵列基板的方法 |
CN107331619A (zh) * | 2017-06-28 | 2017-11-07 | 京东方科技集团股份有限公司 | 薄膜晶体管及其制作方法、显示装置、曝光装置 |
CN108933179B (zh) | 2018-07-05 | 2020-06-16 | 深圳市华星光电半导体显示技术有限公司 | 一种薄膜晶体管及其制作方法 |
CN109541829B (zh) * | 2018-12-19 | 2021-08-24 | 惠科股份有限公司 | 掩膜版、液晶面板和液晶显示装置 |
US11121257B2 (en) | 2019-02-22 | 2021-09-14 | Boe Technology Group Co., Ltd. | Thin film transistor, pixel structure, display device and manufacturing method |
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JP2012253350A (ja) | 2012-12-20 |
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