WO2015123975A1 - 阵列基板及制备方法、显示面板 - Google Patents

阵列基板及制备方法、显示面板 Download PDF

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Publication number
WO2015123975A1
WO2015123975A1 PCT/CN2014/084530 CN2014084530W WO2015123975A1 WO 2015123975 A1 WO2015123975 A1 WO 2015123975A1 CN 2014084530 W CN2014084530 W CN 2014084530W WO 2015123975 A1 WO2015123975 A1 WO 2015123975A1
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Prior art keywords
thin film
film transistor
drain
electrode
patterning process
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PCT/CN2014/084530
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English (en)
French (fr)
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蒋学兵
林琳
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京东方科技集团股份有限公司
合肥鑫晟光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 合肥鑫晟光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US14/435,913 priority Critical patent/US9947691B2/en
Publication of WO2015123975A1 publication Critical patent/WO2015123975A1/zh

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    • G—PHYSICS
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    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
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    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
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Definitions

  • At least one embodiment of the present invention relates to an array substrate, a method of fabricating the same, and a display panel. Background technique
  • Thin film Transistor (TFT) leakage path mainly includes leakage of liquid crystal capacitor and leakage of TFT.
  • the former is leaked from the pixel electrode to the common electrode, and the latter is leaked from the pixel electrode to the data line. Therefore, the latter leakage and data line
  • the voltage is related.
  • the leakage current conduction mechanism of the TFT device itself is mainly the hole current formed by the channel thermionic emission. For example, the leakage current of the amorphous silicon product is greatly increased under the condition of illumination.
  • Indium Gallium Zinc Oxide is a new generation of materials for TFT active layers.
  • IGZO transistors are smaller in size first, which makes the device thinner and lighter. Secondly, it is completely transparent and insensitive to visible light. Increase the aperture ratio of components, increase brightness, and reduce power consumption.
  • IGZO carrier mobility is 5 to 10 times that of amorphous silicon, and the threshold voltage drift is almost the same, which is 20 to 50 times higher than amorphous silicon material. Therefore, the on-state current characteristics are good and the progress is very obvious. . In the main performance parameters of the panel, the IGZO panel has a comprehensive improvement over the amorphous silicon TFT panel.
  • the oxide TFT In order to reduce the optical contact area of the oxide active layer (e.g., the IGZO active layer) and to reduce the photoleakage current, the oxide TFT generally has a light-shielding structure. As shown in FIG. 1 and FIG. 2, the gate line 102 is located below the oxide active layer 104, the source 106 and the drain 107, such that the gate line 102 blocks the formation in the channel between the source 106 and the drain 107.
  • the oxide active layer 104 can effectively reduce the probability of electron-hole pairs generated during illumination, and therefore the leakage current (off-state current) is less affected by illumination. Summary of the invention
  • At least one embodiment of the present invention provides an array substrate, a method of fabricating the same, and a display panel to reduce leakage current when the TFT is turned off.
  • At least one embodiment of the present invention provides an array substrate, including: a substrate substrate, disposed on a gate line, a data line, and a plurality of pixel units on the base substrate, each of the pixel units including a first thin film transistor, a pixel electrode, and at least one second thin film transistor connected in series with the first thin film transistor, the pixel An electrode is connected to a drain of the second thin film transistor, a source of the second thin film transistor is connected to a drain of the first thin film transistor, and a source of the first thin film transistor is connected to the data line.
  • At least one embodiment of the present invention also provides a display panel comprising the above array substrate.
  • At least one embodiment of the present invention also provides a method of fabricating an array substrate, the method comprising: forming a gate line, a data line, and a plurality of pixel units on the base substrate by a patterning process.
  • Each of the pixel units includes a first thin film transistor, a pixel electrode, and at least one second thin film transistor connected in series with the first thin film transistor, the pixel electrode being connected to a drain of the second thin film transistor, the A source of the second thin film transistor is connected to a drain of the first thin film transistor, and a source of the first thin film transistor is connected to the data line.
  • 1 is a schematic top plan view of an oxide TFT array substrate
  • FIG. 2 is a schematic cross-sectional view of the oxide TFT array substrate shown in FIG. 1 taken along the line A-A';
  • FIG. 3 is a schematic top plan view of an oxide TFT array substrate according to an embodiment of the present invention
  • FIG. 4 is a cross-sectional view of the oxide TFT array substrate along the grid line taken along line A-A' of the embodiment of the present invention
  • FIG. 5 is a schematic structural view of a method for fabricating an oxide TFT array substrate according to an embodiment of the present invention.
  • FIG. 6 is a schematic structural view of a second fabrication process of a method for fabricating an oxide TFT array substrate according to an embodiment of the present invention
  • FIG. 7 is a schematic structural diagram of a third patterning process of a method for fabricating an oxide TFT array substrate according to an embodiment of the present invention
  • FIG. 8 is a schematic structural diagram of a fourth patterning process of a method for fabricating an oxide TFT array substrate according to an embodiment of the present invention
  • FIG. 9 is a schematic structural diagram of a fifth patterning process of a method for fabricating an oxide TFT array substrate according to an embodiment of the present invention.
  • FIG. 10 is a schematic structural diagram of a sixth patterning process of a method for fabricating an oxide TFT array substrate according to an embodiment of the present invention.
  • 11( a ) to 11 ( h ) are schematic diagrams showing a manufacturing process of an oxide TFT array substrate according to an embodiment of the present invention (halftone mask technology);
  • FIG. 12 is a schematic circuit diagram of an oxide TFT array substrate according to an embodiment of the present invention.
  • 100 a base substrate; 101: a common electrode layer; 102: a gate line/gate; 103: a common electrode line; 104: a first oxide active layer; 105: a data line; 106: a first source; a first drain; 108: a slit on the pixel electrode; 109: a pixel electrode; 110: a gate insulating layer; 111: an etch barrier; 112: a passivation layer; 20: a pixel unit; 200: a substrate; : common electrode layer; 202: gate line/gate; 203: common electrode line; 204: first oxide active layer; 204': second oxide active layer; 205: data line; 206: first source 206;: second source; 207: first drain; 207,: second drain; 208: pixel electrode layer; 209: slit on the pixel electrode layer; 210: gate insulating layer; 211: engraved Etch barrier; 212: passivation layer.
  • the inventors of the present application have noted that in the oxide TFT of the light-shielding structure shown in FIGS. 1 and 2, the source 106 and the drain 107 are in direct contact with the oxide active layer 104, which causes the oxide to be active.
  • the probability that holes in the layer 104 flow into the source 106 and the drain 107, and electrons of the source 106 and the drain 107 flow into the active layer 104 increases, thereby enhancing "drain ⁇ oxide active layer ⁇ source" This leakage path is not conducive to maintaining the stored charge, resulting in a drop in panel quality.
  • the structure of the TFT array substrate is specifically described by taking the structure of an advanced Dimension Switch (ADS) type oxide TFT array substrate as an example.
  • ADS advanced Dimension Switch
  • the first oxide TFT described in at least one embodiment of the present invention is a raw oxide TFT, the first source and the first drain are a source and a drain of the original oxide TFT; and the second oxide TFT is In at least one embodiment, the dummy oxide TFT is provided, and the second source and the second drain are sources and drains of the dummy oxide TFT.
  • the array substrate includes a first oxide TFT and a second oxide TFT.
  • the embodiment of the present invention is not limited thereto.
  • the array substrate of the embodiment of the present invention may further include Two or more second oxide TFTs.
  • At least one embodiment of the present invention provides an oxide TFT array substrate, including: a substrate substrate 200, a gate line 202, a data line 205 disposed on the substrate substrate 200, and A plurality of pixel units 20.
  • Each of the pixel units 20 includes a first oxide TFT and a pixel electrode 208, each of the pixel units 20 further including at least one second oxide TFT in series with the first oxide TFT.
  • the pixel electrode 208 is connected to the second drain 207', the second source 206' is connected to the first drain 207, and the first source 206 is connected to the data line 205.
  • the second oxide TFT is added to the array substrate including only the first oxide TFT.
  • the effect of the added second oxide TFT is that: the second oxide TFT increases the off-state resistance between the pixel electrode 208 and the data line 205, and suppresses the first oxidation.
  • the holes in the active layer 204 flow into the first drain 207, and the electrons of the first drain 207 flow into the first oxide active layer 204, thereby effectively suppressing the "drain ⁇ oxide active layer ⁇
  • the source's leakage path enhances the display quality of the panel.
  • the second oxide TFT provided in series with the first oxide TFT can increase the off-state resistance (Rofn+Roa ⁇ Rofn) of the TFT to reduce leakage current.
  • an oxide active layer of the first and second oxide thin film transistors is disposed on the base substrate, and a source and a drain of the first oxide thin film transistor And a source and a drain of the second oxide thin film transistor are respectively disposed on the oxide active layer of the first and second oxide thin film transistors, a drain of the second oxide thin film transistor and the pixel
  • the pixel electrodes extending to the drain of the second oxide thin film transistor in the cell are connected.
  • the array substrate may be a bottom gate structure oxide TFT array substrate, which may include: a substrate substrate 200; a gate line 202 disposed on the substrate substrate 200; and a gate insulating layer 210 disposed over the gate line 202 a first oxide active layer pattern 204 and a second oxide active layer pattern 204' disposed over the gate line 202 on the gate insulating layer 210; disposed in the first oxide active layer pattern 204 And an etch barrier layer pattern 211 over the second oxide active layer pattern 204'; the first source pattern 206, the first drain pattern 207, and the second disposed over the etch barrier layer pattern 211
  • the source pattern 206' and the second drain pattern 207', the first source pattern 206 and the first drain pattern 207 pass through the via holes on the etch barrier pattern 211 and the active layer of the first oxide TFT
  • the pattern 204 is connected, and the second source pattern 206' and the second drain pattern 207' are connected to the active layer pattern 204' of the second oxide TFT through via holes on the
  • the etch barrier layer 211 is provided with via holes for preventing contact between the source and the drain and the oxide active layer.
  • the etch barrier layer 211 is used to prevent the oxide active layer in the channel formed between the source and the drain in the process of forming the source and the drain from being etched during the process of fabricating the oxide TFT array substrate;
  • the etch stop layer 211 covers at least the channel between the first source 206 and the first drain 207, the second source 206' and the second drain 207', and exemplarily shows the source/drain in FIG.
  • Other regions of the gate 202 outside the region where the pole is in contact with the oxide active layer cover the etch stop layer 211. In the actual preparation process, the pattern of the etch barrier layer 211 can be visually processed.
  • the etch stop layer may not be disposed, but the same function as the etch barrier layer may be achieved by, for example, a source/drain transition layer.
  • the source/drain transition layer may be made of elements such as B and Si. Made of doped semiconductor material. There is no limit here.
  • the bottom gate structure of the ADS type oxide TFT array substrate is described as an example.
  • the embodiment of the present invention is not limited to the TFT array substrate of the bottom gate structure, and is also applicable to a TFT array substrate such as a top gate structure.
  • the top gate structure oxide TFT array substrate may include: a base substrate; a first oxide active layer pattern and a second oxide active layer pattern disposed on the base substrate; disposed on the first oxide active layer pattern and the second oxide active layer pattern An upper etch barrier pattern; the first source pattern, the first drain pattern, the second source pattern, and the second drain pattern disposed above the etch barrier layer pattern, the first source The pole pattern and the first drain pattern are connected to the active layer pattern of the first oxide TFT through via holes on the etch barrier pattern, and the second source pattern and the second drain pattern pass through the etch barrier pattern a via hole connected to the active layer pattern of the second oxide TFT; a gate insulating layer disposed over the source and drain; a gate line disposed above the gate insulating layer; Above the grid line A passivation layer, the passivation layer is provided with
  • the array substrate may further include: a common electrode 201 and a common electrode line 203 disposed on the base substrate 200, and the common electrode line 203 is connected to the common electrode 201.
  • the common electrode 201 and the pixel electrode 208 may be disposed in different layers, and the pixel electrode 208 or the common electrode 201 in a relatively upper layer includes a slit-like structure, and the common layer in the lower layer
  • the electrode 201 or the pixel electrode 208 includes a slit-like structure or a plate-like structure.
  • the pixel electrode is in the opposite upper layer and the common electrode is in the opposite lower layer.
  • the pixel electrode and the common electrode may each include a slit-like structure, or a pixel electrode.
  • the slit-like structure is included, and the common electrode includes a plate-like structure.
  • the pixel electrodes 208 may be disposed in the same layer, and the pixel electrode 208 and the common electrode 201 each include a slit-like structure.
  • the TFT array substrate structure described above based on FIGS. 3 and 4 is only described by taking an ADS type oxide TFT array substrate as an example, but the embodiment of the present invention is not limited to the ADS type oxide TFT array substrate.
  • the examples are not specifically limited.
  • the oxide active layer is an indium gallium oxide.
  • the embodiment of the present invention is not limited thereto.
  • the oxide active layer may also be indium oxide (IZO), oxidized (ZnO), or the like.
  • an oxide TFT array substrate has a second oxide TFT added to the array substrate including only the first oxide TFT, and the second oxide TFT increases the pixel electrode and the data line.
  • the off-state resistance between the two can suppress the leakage path of the "drain-oxide active layer-source" and improve the display quality of the panel.
  • the second oxide TFT is placed in series with the first oxide TFT. possible to increase the off-resistance of the TFT (R. ffl + Roffi> Roffi) , reduce leakage current.
  • the above embodiment is merely an example of an array substrate using an oxide TFT, but the embodiment of the present invention is not limited thereto, but is applicable to any that can be suppressed by connecting at least two TFTs in series.
  • a polysilicon TFT such as a low temperature polysilicon (LTPS) type TFT or a high temperature polysilicon (HTPS) type TFT may also be used because both the polysilicon TFT and the oxide TFT have high electron mobility. The rate is thus more advantageous for achieving a series connection between TFTs.
  • the array substrate is made of a polysilicon TFT, the structure of the array substrate is similar to that of the array substrate for the oxide TFT provided in the above embodiments, and the repeated description is omitted.
  • the present invention further provides a display panel including the above TFT array substrate.
  • the display panel may be a liquid crystal display panel, an organic light emitting diode display panel, a touch panel, or the like.
  • At least one embodiment of the present invention also provides a method of fabricating a TFT array substrate.
  • the preparation method will be described by taking an oxide TFT array substrate as an example.
  • the method comprises: by a patterning process, on a substrate basis A gate line 202, a data line 205, and a plurality of pixel units 20 are formed on the board; each of the pixel units 20 includes a first oxide thin film transistor and a pixel electrode 208, each of the pixel units 20 further including at least one a second oxide thin film transistor in series with the first oxide thin film transistor; the pixel electrode 208 is connected to the second drain 207 ′, and the second source 206 ′ is connected to the first drain 207 The first source 206 is connected to the data line 205.
  • a pattern including an active layer of the first oxide thin film transistor and an active layer of the second oxide thin film transistor may be formed on the base substrate, Forming a source and a drain including a first oxide thin film transistor and a second oxide on a base substrate formed with a pattern including an active layer of the first oxide thin film transistor and an active layer of the second oxide thin film transistor a pattern of a source and a drain of the thin film transistor, and a base substrate formed with a pattern including a source and a drain of the first oxide thin film transistor and a source and a drain of the second oxide thin film transistor A pattern including a pixel electrode extending to a drain of the second oxide thin film transistor and connected to a drain of the second oxide thin film transistor.
  • the preparation method may further include: forming a pattern including an etch barrier layer on the base substrate.
  • the embodiment of the present invention is described in detail by taking a preparation method of a bottom gate type ADS type oxide TFT array substrate as an example, and the method can be as follows.
  • the patterning process provided by the embodiments of the present invention includes main processes such as exposure, development, etching, and ashing.
  • a pattern including the common electrode 201, the gate line 202, and the common electrode line 203 is formed on the base substrate 200 by the first patterning process.
  • a gate metal layer film is first formed on the base substrate 200, and then a photoresist is formed on the base substrate 200 coated with the gate metal layer film.
  • a photoresist retention region (including a photoresist portion remaining region and a photoresist completely reserved region) is formed.
  • a photoresist completely removed region corresponds to a region of the common electrode 201, the gate line 202, and the common electrode line 203; the photoresist completely removed region corresponds to the pixel unit 20 The area outside the resist retention area.
  • the etch process is used to remove the gate metal layer film in the completely removed region of the photoresist and the ITO film under the gate metal layer film, and then the photoresist in the photoresist remaining region is removed by ashing process but lithography
  • the photoresist completely retains a portion of the thickness of the photoresist, and then etching is performed again to remove the gate metal layer film corresponding to the remaining portion of the original photoresist portion to expose it.
  • the lower ITO film finally removes the remaining photoresist to form a pattern of the common electrode 201, the gate line 202, and the common electrode line 203 as shown in Figs. 11(a) to (h). As shown in FIG. 5, the pattern of the gate lines 202 is exposed to form the gate lines 202.
  • a pattern including a gate insulating layer 210, a first oxide active layer 204, and a second oxide active layer 204' is formed on the substrate substrate 200 subjected to the first patterning process by a second patterning process.
  • the pattern of the oxide active layer is above the gate line 202.
  • a gate insulating layer film and an oxide active layer film are first coated on the substrate substrate 200 subjected to the first patterning process. Then, a photoresist is formed on the base substrate 200 coated with the gate insulating film and the oxide active layer film. After the photoresist is exposed and developed by the mask, a photoresist completely reserved region and a photoresist completely removed region are formed.
  • the photoresist completely reserved region corresponds to a region of the active layer 204 of the first oxide TFT and the active layer 204' of the second oxide TFT; the photoresist completely removed region corresponds to the pixel unit 20
  • the oxide active layer film on the completely removed region of the photoresist is removed by an etching process, and the photoresist in the completely remaining region of the photoresist is removed by an ashing process, as shown in FIG. 6, the first oxide is exposed.
  • a pattern of the active layer 204 of the TFT and the active layer 204' of the second oxide TFT forms a gate insulating layer 210 and an oxide active layer.
  • a pattern including the etch stop layer 211 is formed on the base substrate 200 subjected to the second patterning process by the third patterning process.
  • an etch barrier film is first coated on the substrate substrate 200 subjected to the second patterning process, and then formed on the substrate substrate 200 coated with the etch barrier film.
  • Photoresist After the photoresist is exposed and developed by the mask, a photoresist completely reserved region and a photoresist completely removed region are formed.
  • the photoresist completely retaining region corresponds to a region of the etch barrier layer 211; and the photoresist completely removed region corresponds to a region of the pixel unit 20 other than the photoresist completely reserved region.
  • the etch barrier film on the completely removed region of the photoresist is removed by an etching process, and the photoresist in the completely remaining region of the photoresist is removed by an ashing process. As shown in FIG. 7, the etch barrier layer 211 is exposed. The pattern forms an etch stop layer 211.
  • the substrate is first subjected to the third patterning process.
  • a source/drain metal layer film is coated on the substrate 200, and then a photoresist is formed on the base substrate 200 coated with the active metal leakage layer film.
  • the photoresist is exposed and developed by using a mask, a photoresist completely reserved region and a photoresist completely removed region are formed.
  • the photoresist completely retaining region corresponds to a region of the data line 205, the first source 206, the first drain 207, the second source 206', and the second drain 207'; the photoresist completely removed region corresponds to In the pixel unit 20, in addition to the photoresist completely reserved region, the photoresist in the photoresist completely reserved region is removed by the ashing process, and the data line 205 and the first source 206 are formed as shown in FIG. a pattern of the first drain 207, the second source 206', and the second drain 207'. As shown in FIG. 8, the source and drain patterns are exposed to form a source and a drain.
  • a passivation layer film is first coated on the substrate substrate 200 subjected to the fourth patterning process, and then a photolithography is formed on the substrate substrate 200 coated with the passivation layer film. gum.
  • a photoresist completely reserved region and a photoresist completely removed region are formed.
  • the fully removed regions include gate lead vias and data line lead vias.
  • the passivation layer film on the completely removed region of the photoresist is removed by an etching process, and the photoresist in the completely remaining region of the photoresist is removed by an ashing process. As shown in FIG. 8, a pattern of the passivation layer 207 is formed. , the gate lead via and the data line lead via, the gate lead via and the data line lead via are not shown.
  • a transparent conductive layer film is first coated on the base substrate 200 subjected to the fifth patterning process, and then a photolithography is formed on the base substrate 200 coated with the transparent conductive layer film. gum.
  • a photoresist completely reserved region and a photoresist completely removed region are formed; the photoresist completely reserved region corresponds to a region of the pixel electrode 208; the photoresist is completely removed.
  • the area corresponds to an area of the pixel unit 20 other than the completely reserved area of the photoresist. Removing the photoresist from the completely removed area by an etching process a conductive film of the conductive layer, and then removing the photoresist in the completely reserved region of the photoresist by using an ashing process, as shown in the figure
  • the pixel electrode 208 having the slit 209 is formed.
  • the bottom gate structure oxide TFT array substrate provided by the embodiment of the present invention can be easily changed into a top gate structure oxide TFT array substrate, for example, a bottom gate structure oxide TFT array substrate structure is prepared.
  • the method steps for preparing the top gate structure oxide TFT array substrate may include:
  • a transparent conductive film, an oxide active layer film is first coated on the base substrate. Then, a photoresist is formed on the underlying substrate coated with the transparent conductive film and the oxide active layer film. After the photoresist is exposed and developed by the mask, a fully-retained area of the photoresist and a completely removed area of the photoresist are formed.
  • the photoresist completely retaining region corresponds to a region of the active layer of the first oxide TFT and the active layer of the second oxide TFT; the photoresist completely removed region corresponds to the lithography in the pixel unit
  • the glue completely retains the area outside the area.
  • the oxide active layer film on the completely removed region of the photoresist is removed by an etching process, and the photoresist in the completely remaining region of the photoresist is removed by an ashing process to form a common electrode and a first oxide TFT.
  • an etch barrier film is first coated on the substrate substrate subjected to the first patterning process, and then a lithography is formed on the substrate substrate coated with the etch barrier film. gum.
  • a photoresist completely reserved region and a photoresist completely removed region are formed.
  • the photoresist completely retaining region corresponds to the region of the etch barrier layer; the photoresist completely removed region corresponds to the photoresist cell completely remaining region in the pixel unit to reuse the ashing process to remove the photoresist
  • the photoresist is completely preserved to form a pattern of etch barrier layers.
  • the substrate is first subjected to the second patterning process.
  • a source and a drain metal layer film are coated on the substrate, and then a photoresist is formed on the base substrate on which the active or drain metal layer film is applied.
  • a photoresist completely reserved region and a photoresist completely removed region are formed.
  • the photoresist completely retains a region corresponding to the data line, the first source, the first drain, the second source, and the second drain; the photoresist completely removed region corresponds to the pixel unit The area where the photoresist completely remains outside the area.
  • the source and drain metal layer films on the completely removed region of the photoresist are removed by an etching process, and the photoresist in the completely remaining region of the photoresist is removed by an ashing process to form a data line, a first source, and a first A pattern of the drain, the second source, and the second drain.
  • a gate insulating layer film and a gate metal layer film are first coated on a substrate substrate subjected to a third patterning process. Then, a photoresist is formed on the substrate coated with the gate insulating film and the gate metal film. After the photoresist is exposed and developed by the mask, a photoresist completely reserved region and a photoresist completely removed region are formed. The photoresist completely retains a region corresponding to the gate metal layer film; the photoresist completely removed region corresponds to a region of the pixel unit other than the photoresist completely reserved region.
  • the gate metal film on the completely removed region of the photoresist is removed by an etching process, and the photoresist in the completely remaining region of the photoresist is removed by an ashing process to form a pattern of the gate insulating layer, the gate line and the common electrode line. .
  • a passivation layer film is first coated on a substrate substrate subjected to a fourth patterning process, and then a photoresist is formed on the substrate substrate coated with the passivation layer film.
  • a photoresist completely reserved region and a photoresist completely removed region are formed.
  • the removed regions include gate line via vias and data line lead vias.
  • the passivation layer film on the completely removed region of the photoresist is removed by an etching process, and the photoresist in the completely remaining region of the photoresist is removed by an ashing process to form a passivation layer pattern, a gate line via and Data line lead via.
  • a transparent conductive layer film is first coated on the substrate substrate subjected to the fifth patterning process, and then a photoresist is formed on the substrate substrate coated with the transparent conductive layer film. After the photoresist is exposed and developed by the mask, a photoresist completely reserved region and a photoresist completely removed region are formed. The photoresist completely retains a region corresponding to the pixel electrode; the photoresist completely removed region corresponds to a region of the pixel unit other than the photoresist completely reserved region.
  • the transparent conductive layer film on the completely removed region of the photoresist is removed by an etching process, and the photoresist in the completely remaining region of the photoresist is removed by an ashing process to form a pixel electrode having a slit.
  • the method for fabricating the oxide TFT array substrate described in the embodiments of the present invention is described by way of an exemplary six-time patterning process, but it should not be construed that limiting the embodiment of the present invention can only be achieved by using six patterning processes.
  • the number of other different patterning processes, which enables the array substrate to further include the second oxide TFT, is also within the scope of the present invention.
  • a method for fabricating an oxide TFT array substrate provided by an embodiment of the present invention, wherein a second oxide TFT is disposed on the array substrate, and the second oxide is added on the basis of the array substrate including only the first oxide TFT
  • the TFT, the second oxide TFT increases the off-state resistance between the pixel electrode and the data line, and can suppress the leakage path of the “drain ⁇ oxide active layer ⁇ source” to improve the display quality of the panel;
  • the second oxide TFT disposed in series with the first oxide TFT can increase the off-state resistance of the TFT ( R.ffl + Ro ffi > R. ffl ) to reduce leakage current.
  • the oxide TFT when the oxide TFT is turned on, the signal is transmitted from the active layer of the first oxide TFT to the first drain, then to the second source, and is transmitted to the second drain through the active layer of the second oxide TFT.
  • the pole is then transmitted to the pixel electrode through the passivation layer via hole on the pixel electrode, and finally a transverse electric field can be formed in the liquid crystal cell for the liquid crystal to be deflected.
  • the liquid crystal deflection angle can be controlled to affect the panel transmittance.
  • the above embodiment is described by taking the preparation method of the oxide TFT array substrate as an example, but the embodiment of the present invention is not limited thereto, but is applicable to any combination of at least two TFTs.
  • a polysilicon TFT such as a low temperature polysilicon (LTPS) type TFT or a high temperature polysilicon (HTPS) type TFT may also be used because both the polysilicon TFT and the oxide TFT have high electron mobility. The rate is thus more advantageous for achieving a series connection between TFTs.
  • the preparation method thereof is the same as the oxide TFT array substrate provided by the above embodiments. The preparation method is similar, and the repetition will not be described again.
  • the array substrate and the preparation method and the display panel provided by at least one embodiment of the present invention are provided with a second thin film transistor connected in series with the first thin film transistor, which increases the off-state resistance between the pixel electrode and the data line, and can be reduced.
  • the off-state leakage current of the thin film transistor can improve the picture flicker, crosstalk, and afterimage of the display panel, thereby improving display performance.

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Abstract

一种阵列基板及其制作方法、显示面板，该阵列基板包括：衬底基板(200)，所述衬底基板(200)上的栅线(202)、数据线(205)以及多个像素单元(20)。每个所述像素单元(20)包括第一薄膜晶体管、像素电极(208)以及至少一个与第一薄膜晶体管串联的第二薄膜晶体管。所述像素电极(208)与第二薄膜晶体管的漏极(207')相连，所述第二薄膜晶体管的源极(206')与所述第一薄膜晶体管的漏极(207)相连，所述第一薄膜晶体管的源极(206)与所述数据线(205)相连。该阵列基板能够减小在薄膜晶体管关断时的漏电流。

Description

阵列基板及制备方法、 显示面板 技术领域
本发明至少一个实施例涉及一种阵列基板及其制作方法、 显示面板。 背景技术
薄膜晶体管（ Thin Film Transistor, TFT )漏电路径主要有液晶电容漏电 和 TFT漏电， 前者是由像素电极漏电至公共电极， 后者由像素电极漏电至数 据线， 因此后者的漏电会与数据线上的电压有关。 TFT器件本身的漏电流导 电机制主要是沟道热离子发射形成的空穴电流， 例如， 非晶硅产品的漏电流 会在光照的条件下大大增加。
铟镓辞氧化物（Indium Gallium Zinc Oxide, IGZO )是新一代用于 TFT 有源层的材料， IGZO 晶体管首先尺寸更小， 这可以使设备更轻薄， 其次全 透明， 对可见光不敏感， 能够大大增加元件的开口率， 提高亮度， 降低功耗。 此外， 电子迁移率方面， IGZO载流子迁移率是非晶硅的 5 ~ 10倍， 临界电 压飘移几乎一致， 比非晶硅材料提升了 20~50倍， 因此开态电流特性良好， 进步非常明显。 在面板的主要性能参数上， IGZO面板比非晶硅 TFT面板有 了全面的提升。
为了减少氧化物有源层（例如， IGZO有源层） 的光接触面积， 减小光 致漏电流， 氧化物 TFT—般釆用遮光型结构。 如图 1、 图 2所示， 栅线 102 位于氧化物有源层 104、 源极 106和漏极 107的下方， 这样栅线 102遮挡住 了源极 106和漏极 107之间的沟道内形成的氧化物有源层 104， 从而能够有 效降低光照时电子空穴对产生的概率， 因此漏电流（关态电流）受光照的影 响较小。 发明内容
本发明至少一个实施例提供一种阵列基板及制备方法、 显示面板， 以减 小在 TFT关断时的漏电流。
本发明至少一个实施例提供一种阵列基板， 其包括： 衬底基板， 设置于 所述衬底基板上的栅线、 数据线以及多个像素单元， 每个所述像素单元包括 第一薄膜晶体管、 像素电极以及至少一个与第一薄膜晶体管串联的第二薄膜 晶体管， 所述像素电极与所述第二薄膜晶体管的漏极相连， 所述第二薄膜晶 体管的源极与所述第一薄膜晶体管的漏极相连， 所述第一薄膜晶体管的源极 与所述数据线相连。
本发明至少一个实施例还提供了一种显示面板， 所述显示面板包括上述 的阵列基板。
本发明至少一个实施例还提供了一种阵列基板的制备方法，该方法包括： 通过构图工艺， 在所述衬底基板上形成栅线、 数据线以及多个像素单元。 每 个所述像素单元包括第一薄膜晶体管、 像素电极以及至少一个与所述第一薄 膜晶体管串联的第二薄膜晶体管， 所述像素电极与所述第二薄膜晶体管的漏 极相连， 所述第二薄膜晶体管的源极与所述第一薄膜晶体管的漏极相连， 所 述第一薄膜晶体管的源极与所述数据线相连。 附图说明
为了更清楚地说明本发明实施例的技术方案， 下面将对实施例的附图作 简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例， 而非对本发明的限制。
图 1为一种氧化物 TFT阵列基板的俯视结构示意图；
图 2为图 1所示的氧化物 TFT阵列基板沿栅线上的 A-A'向剖视结构示意 图；
图 3为本发明实施例提供的氧化物 TFT阵列基板的俯视结构示意图； 图 4为本发明实施例提供的氧化物 TFT阵列基板沿栅线上的 A-A'向剖视 结构示意图；
图 5为本发明实施例提供的氧化物 TFT阵列基板的制作方法的第一次构 图工艺后的结构示意图；
图 6为本发明实施例提供的氧化物 TFT阵列基板的制作方法的第二次构 图工艺后的结构示意图；
图 7为本发明实施例提供的氧化物 TFT阵列基板的制作方法的第三次构 图工艺后的结构示意图； 图 8为本发明实施例提供的氧化物 TFT阵列基板的制作方法的第四次构 图工艺后的结构示意图；
图 9为本发明实施例提供的氧化物 TFT阵列基板的制作方法的第五次构 图工艺后的结构示意图；
图 10为本发明实施例提供的氧化物 TFT阵列基板的制作方法的第六次 构图工艺后的结构示意图；
图 11 ( a )到图 11 ( h )为本发明实施例提供的氧化物 TFT阵列基板的 制作流程示意图 （半色调掩模技术） ；
图 12为本发明实施例提供的氧化物 TFT阵列基板电路原理图。
附图标记说明：
100:衬底基板； 101 :公共电极层； 102: 栅线 /栅极； 103: 公共电极线； 104: 第一氧化物有源层； 105: 数据线； 106: 第一源极； 107: 第一漏极； 108: 像素电极上的狭缝； 109: 像素电极； 110: 栅绝缘层； 111 : 刻蚀阻挡 层； 112: 钝化层； 20: 像素单元； 200:衬底基板； 201 :公共电极层； 202: 栅线 /栅极； 203: 公共电极线； 204: 第一氧化物有源层； 204': 第二氧化物 有源层； 205: 数据线； 206: 第一源极； 206，： 第二源极； 207: 第一漏极； 207，： 第二漏极； 208: 像素电极层； 209: 像素电极层上的狭缝； 210: 栅绝 缘层； 211 : 刻蚀阻挡层； 212: 钝化层。 具体实施方式
为使本发明实施例的目的、 技术方案和优点更加清楚， 下面将结合本发 明实施例的附图， 对本发明实施例的技术方案进行清楚、 完整地描述。显然， 所描述的实施例是本发明的一部分实施例， 而不是全部的实施例。 基于所描 述的本发明的实施例， 本领域普通技术人员在无需创造性劳动的前提下所获 得的所有其他实施例， 都属于本发明保护的范围。
除非另外定义， 本公开使用的技术术语或者科学术语应当为本发明所属 领域内具有一般技能的人士所理解的通常意义。 本公开中使用的 "第一" 、 "第二" 以及类似的词语并不表示任何顺序、 数量或者重要性， 而只是用来 区分不同的组成部分。 同样， "一个" 、 "一" 或者 "该" 等类似词语也不 表示数量限制， 而是表示存在至少一个。 "包括" 或者 "包含" 等类似的词 语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物 件及其等同， 而不排除其他元件或者物件。 "连接" 或者 "相连" 等类似的 词语并非限定于物理的或者机械的连接， 而是可以包括电性的连接， 不管是 直接的还是间接的。 "上" 、 "下" 、 "左" 、 "右" 等仅用于表示相对位 置关系， 当被描述对象的绝对位置改变后， 则该相对位置关系也可能相应地 改变。
本申请的发明人注意到， 在图 1和图 2所示的遮光型结构的氧化物 TFT 中， 源极 106和漏极 107直接与氧化物有源层 104接触， 这样会导致氧化物 有源层 104内空穴流入源极 106和漏极 107， 以及源极 106和漏极 107的电 子流入有源层 104中的几率增大， 从而加强 "漏极→氧化物有源层→源极" 这一漏电路径， 不利于保持已存储的电荷， 导致面板画质下降。
本发明至少一个实施例示例性地， 以高级超维场转换 （Advanced Dimension Switch, ADS )型的氧化物 TFT阵列基板的结构为例， 具体描述 该 TFT阵列基板的结构。
本发明至少一个实施例中所述的第一氧化物 TFT为原氧化物 TFT，所述 第一源极和第一漏极为原氧化物 TFT的源极和漏极； 第二氧化物 TFT为本 发明至少一个实施例所提供的虚拟氧化物 TFT， 所述第二源极和第二漏极为 虚拟氧化物 TFT的源极和漏极。以下实施例的附图中仅示出了阵列基板包括 一个第一氧化物 TFT和一个第二氧化物 TFT， 但本发明实施例不局限于此， 例如，本发明实施例的阵列基板还可以包括两个或两个以上第二氧化物 TFT。
如图 3、 4所示， 本发明至少一个实施例提供了一种氧化物 TFT阵列基 板， 其包括： 衬底基板 200， 设置于所述衬底基板 200上的栅线 202、数据线 205以及多个像素单元 20。 每个所述像素单元 20包括第一氧化物 TFT和像 素电极 208， 每个所述像素单元 20还包括至少一个与第一氧化物 TFT串联 的第二氧化物 TFT。 所述像素电极 208与所述第二漏极 207'相连， 所述第二 源极 206'与所述第一漏极 207相连， 所述第一源极 206与所述数据线 205相 连。
上述氧化物 TFT阵列基板， 在只包括第一氧化物 TFT的阵列基板的基 础上， 增加第二氧化物 TFT。 增加的第二氧化物 TFT的作用在于： 该第二氧 化物 TFT增加了像素电极 208与数据线 205之间关态电阻，能抑制第一氧化 物有源层 204内的空穴流入第一漏极 207， 以及第一漏极 207的电子流入第 一氧化物有源层 204中的几率，从而有效抑制 "漏极→氧化物有源层→源极" 的漏电路径， 提升面板的显示品质。 如图 12所示， 与第一氧化物 TFT串联 设置的第二氧化物 TFT能够增大 TFT的关态电阻（Rofn+Roa^ Rofn ) ， 减小 漏电流。
在一个实施例提供的阵列基板中， 所述第一和第二氧化物薄膜晶体管的 氧化物有源层设置在所述衬底基板上， 所述第一氧化物薄膜晶体管的源极和 漏极以及第二氧化物薄膜晶体管的源极和漏极分别设置在所述第一和第二氧 化物薄膜晶体管的氧化物有源层上， 所述第二氧化物薄膜晶体管的漏极与所 述像素单元中延伸至所述第二氧化物薄膜晶体管的漏极的所述像素电极相 连。
例如，上述阵列基板可以为底栅结构氧化物 TFT阵列基板，其可以包括： 衬底基板 200;设置在衬底基板 200上的栅线 202;设置在所述栅线 202上方 的栅绝缘层 210; 设置在所述栅绝缘层 210上位于栅线 202上方的第一氧化 物有源层图案 204和第二氧化物有源层图案 204'; 设置在所述第一氧化物有 源层图案 204和第二氧化物有源层图案 204'上方的刻蚀阻挡层图案 211 ; 设 置在所述刻蚀阻挡层图案 211上方的所述第一源极图案 206、 第一漏极图案 207、 第二源极图案 206'和第二漏极图案 207'， 所述第一源极图案 206和第 一漏极图案 207通过刻蚀阻挡层图案 211上的过孔与第一氧化物 TFT的有源 层图案 204相连， 所述第二源极图案 206'和第二漏极图案 207'通过刻蚀阻挡 层图案 211上的过孔与所述第二氧化物 TFT的有源层图案 204'相连；设置在 所述源极和漏极上方的钝化层 212， 所述钝化层 212设有过孔； 所述第二漏 极 207'与像素单元 20中延伸至所述第二漏极 207'的像素电极层 208相连。
需要说明的是， 所述刻蚀阻挡层 211设有过孔， 以用于防止源极、 漏极 与氧化物有源层之间的接触。该刻蚀阻挡层 211在制作氧化物 TFT阵列基板 过程中， 用于防止形成源极和漏极的过程中源极和漏极之间形成的沟道内的 氧化物有源层被刻蚀； 刻蚀阻挡层 211 至少覆盖第一源极 206 和第一漏极 207、 第二源极 206'和第二漏极 207'之间的沟道， 图 4中示例性地示出除源 极 /漏极与氧化物有源层接触的区域外的栅极 202 的其它区域都覆盖刻蚀阻 挡层 211。 在实际的制备过程中， 刻蚀阻挡层 211的图案可视实际制作工艺 和要求而定， 本发明实施例对此不作具体限定。 此外， 本发明实施例中也可 以不设置刻蚀阻挡层， 而是通过例如源漏过渡层实现与刻蚀阻挡层相同的功 能， 例如， 该源漏过渡层可以由 B、 Si等元素的重掺杂半导体材料制成。 此 处不做限定。
需要说明的是， 上述基于图 3、 4所描述的 TFT阵列基板的结构仅是以
ADS型氧化物 TFT阵列基板的底栅结构为例进行说明， 但本发明实施例并 不限于底栅结构的 TFT阵列基板， 同样适用于顶栅结构等 TFT阵列基板。
本领域所属技术人员很容易得出本发明实施例所提供的底栅结构氧化物 TFT阵列基板可以轻易改为顶栅结构氧化物 TFT阵列基板， 例如， 顶栅结构 氧化物 TFT阵列基板可以包括： 衬底基板； 设置在衬底基板上的第一氧化物 有源层图案和第二氧化物有源层图案； 设置在所述第一氧化物有源层图案和 第二氧化物有源层图案上方的刻蚀阻挡层图案； 设置在所述刻蚀阻挡层图案 上方的所述第一源极图案、 第一漏极图案、 第二源极图案和第二漏极图案， 所述第一源极图案和第一漏极图案通过刻蚀阻挡层图案上的过孔与第一氧化 物 TFT的有源层图案相连，所述第二源极图案和第二漏极图案通过刻蚀阻挡 层图案上的过孔与所述第二氧化物 TFT的有源层图案相连；设置在所述源极 和漏极上方的栅绝缘层； 设置在所述栅绝缘层上方的栅线； 设置在所述栅线 上方的钝化层， 所述钝化层设有过孔； 所述第二漏极与像素单元中延伸至所 述第二漏极的像素电极层相连。 当然， 本发明实施例所提供的氧化物 TFT阵 列基板结构并不局限于本实施例中的所提供的氧化物 TFT阵列基板结构，在 此不再赘述。
在一个实施例中， 所述阵列基板还可以包括： 设置在衬底基板 200上公 共电极 201和公共电极线 203， 所述公共电极线 203与所述公共电极 201相 连。
在不同实施例中，所述公共电极 201和所述像素电极 208可以异层设置， 处于相对上层的所述像素电极 208或所述公共电极 201包括狭缝状结构， 处 于相对下层的所述公共电极 201或所述像素电极 208包括狭缝状结构或板状 结构， 例如， 像素电极处于相对上层， 公共电极处于相对下层， 此时像素电 极和公共电极可以均包括狭缝状结构， 或者像素电极包括狭缝状结构， 而公 共电极包括板状结构。 或者， 在一个实施例中， 所述公共电极 201和所述像 素电极 208可以同层设置， 所述像素电极 208和所述公共电极 201均包括狭 缝状结构。
此外， 需要说明的是， 上述基于图 3、 4所描述的 TFT阵列基板结构仅 是以 ADS型氧化物 TFT阵列基板为例进行说明， 但本发明实施例并不限于 ADS型氧化物 TFT阵列基板， 同样适用于例如扭曲向列 （ Twisted Nematic, TN )型的第一源极 206、第一漏极 207和第一氧化物 TFT的有源层 204直接 接触的 TFT阵列基板， 在此本发明实施例不作具体限定。
在一个实施例中， 所述氧化物有源层为铟镓辞氧化物。 但本发明实施例 不限于此， 例如， 氧化物有源层还可以为氧化铟辞（IZO ) 、 氧化辞（ZnO ) 等。
本发明实施例提供的一种氧化物 TFT阵列基板，由于在只包括第一氧化 物 TFT的阵列基板的基础上， 增加第二氧化物 TFT， 该第二氧化物 TFT增 加了像素电极与数据线之间的关态电阻， 能够抑制 "漏极—氧化物有源层— 源极" 的漏电路径， 提升面板的显示品质； 另一个角度， 与第一氧化物 TFT 串联设置的第二氧化物 TFT能够增大 TFT的关态电阻（R。ffl+Roffi> Roffi ) ， 减小漏电流。
需要注意的是，上述实施例仅是以釆用氧化物 TFT的阵列基板为例进行 说明， 但本发明的实施例并不限于此， 而是适用于任何可以通过将至少两个 TFT串联以抑制 "漏极→有源层→源极" 的漏电路径的情形。 例如， 在本发 明的实施例中， 还可以釆用多晶硅 TFT, 例如低温多晶硅（LTPS )型 TFT 或高温多晶硅（HTPS )型 TFT， 这是因为多晶硅 TFT与氧化物 TFT都具有 较高的电子迁移率， 因而更有利于实现 TFT间的串联。 当阵列基板釆用多晶 硅 TFT时， 其结构与上述实施例提供的釆用氧化物 TFT的阵列基板的结构 类似， 重复之处不再赘述。
基于上述氧化物 TFT阵列基板，本发明至少一个实施例还提供了一种显 示面板， 该显示面板包括上述 TFT阵列基板。 例如， 该显示面板可以是液晶 显示面板、 有机发光二极体显示面板、 触控面板等。
基于上述 TFT阵列基板（例如， 氧化物 TFT阵列基板） ， 本发明至少 一个实施例还提供了一种 TFT阵列基板的制备方法。 以下以氧化物 TFT阵 列基板为例对该制备方法进行说明。 该方法包括： 通过构图工艺， 在衬底基 板上形成栅线 202、 数据线 205、 以及多个像素单元 20; 每个所述像素单元 20包括第一氧化物薄膜晶体管和像素电极 208，每个所述像素单元 20还包括 至少一个与所述第一氧化物薄膜晶体管串联的第二氧化物薄膜晶体管； 所述 像素电极 208与所述第二漏极 207'相连， 所述第二源极 206'与所述第一漏极 207相连， 所述第一源极 206与所述数据线 205相连。
在一个实施例提供的所述氧化物 TFT阵列基板的制备方法中，可以在衬 底基板上形成包括第一氧化物薄膜晶体管的有源层以及第二氧化物薄膜晶体 管的有源层的图案， 在形成有包括第一氧化物薄膜晶体管的有源层以及第二 氧化物薄膜晶体管的有源层的图案的衬底基板上形成包括第一氧化物薄膜晶 体管的源极和漏极以及第二氧化物薄膜晶体管的源极和漏极的图案， 以及在 形成有包括第一氧化物薄膜晶体管的源极和漏极以及第二氧化物薄膜晶体管 的源极和漏极的图案的衬底基板上形成包括像素电极的图案， 使所述像素电 极延伸至所述第二氧化物薄膜晶体管的漏极并与所述第二氧化物薄膜晶体管 的漏极相连。 在一个实施例中， 所述制备方法还可以包括： 在衬底基板上形 成包括刻蚀阻挡层的图案。
例如， 本发明实施例以底栅型 ADS型氧化物 TFT阵列基板的制备方法 为例进行详细描述， 该方法可以如下所述。 需要说明的是， 本发明实施例提 供的构图工艺包括曝光、 显影、 刻蚀、 灰化等主要工艺。
Sl、 通过第一次构图工艺， 在衬底基板 200上形成包括公共电极 201、 栅线 202和公共电极线 203的图案。
例如，在第一次构图工艺过程中，首先在衬底基板 200上栅金属层薄膜， 然后在涂布有栅金属层薄膜的衬底基板 200上形成光刻胶。 如图 11 ( a )到 ( h )所示， 利用半色调掩模板对光刻胶进行曝光、 显影后， 形成光刻胶保留 区域（包括光刻胶部分保留区域、 光刻胶完全保留区域）和光刻胶完全去除 区域； 所述光刻胶保留区域对应公共电极 201、 栅线 202和公共电极线 203 的区域；所述光刻胶完全去除区域对应所述像素单元 20中的除所述光刻胶保 留区域以外的区域。 利用刻蚀工艺去除掉光刻胶完全去除区域中的栅金属层 薄膜和该栅金属层薄膜下的 ITO薄膜， 再利用灰化工艺剥离掉光刻胶部分保 留区域的光刻胶但在光刻胶完全保留区域中保留部分厚度的光刻胶， 然后再 次进行蚀刻以去除对应于原光刻胶部分保留区域中的栅金属层薄膜以露出其 下的 ITO薄膜， 最后去除剩余的光刻胶， 形成如图 11 ( a )到（h )所示的公 共电极 201、栅线 202和公共电极线 203的图案。如图 5所示， 露出栅线 202 的图案， 形成栅线 202。
52、 通过第二次构图工艺， 在经过第一次构图工艺的衬底基板 200上形 成包括栅绝缘层 210、 第一氧化物有源层 204和第二氧化物有源层 204'的图 案。 例如， 所述氧化物有源层的图案位于栅线 202上方。
例如， 在第二次构图工艺的过程中， 首先在经过第一次构图工艺的衬底 基板 200上涂布栅绝缘层薄膜和氧化物有源层薄膜。 然后在涂布有栅绝缘层 薄膜和氧化物有源层薄膜的衬底基板 200上形成光刻胶。 利用掩模板对光刻 胶进行曝光、 显影后， 形成光刻胶完全保留区域和光刻胶完全去除区域。 所 述光刻胶完全保留区域对应第一氧化物 TFT的有源层 204和第二氧化物 TFT 的有源层 204'的区域； 所述光刻胶完全去除区域对应所述像素单元 20中除 所述光刻胶完全保留区域以外的区域。 利用刻蚀工艺去除掉光刻胶完全去除 区域上的氧化物有源层薄膜， 再利用灰化工艺剥离掉光刻胶完全保留区域的 光刻胶， 如图 6所示， 露出第一氧化物 TFT的有源层 204和第二氧化物 TFT 的有源层 204'的图案， 形成栅绝缘层 210和氧化物有源层。
53、 通过第三次构图工艺， 在经过第二次构图工艺的衬底基板 200上形 成包括刻蚀阻挡层 211的图案。
例如， 在第三次构图工艺的过程中， 首先在经过第二次构图工艺的衬底 基板 200上涂布刻蚀阻挡层薄膜， 然后在涂布有刻蚀阻挡层薄膜的衬底基板 200 形成光刻胶。 利用掩模板对光刻胶进行曝光、 显影后， 形成光刻胶完全 保留区域和光刻胶完全去除区域。 所述光刻胶完全保留区域对应刻蚀阻挡层 211的区域； 所述光刻胶完全去除区域对应所述像素单元 20中除所述光刻胶 完全保留区域以外的区域。 利用刻蚀工艺去除掉光刻胶完全去除区域上的刻 蚀阻挡层薄膜， 再利用灰化工艺剥离掉光刻胶完全保留区域的光刻胶， 如图 7所示， 露出刻蚀阻挡层 211的图案， 形成刻蚀阻挡层 211。
54、 通过第四次构图工艺， 在经过第三次构图工艺的衬底基板 200上形 成包括数据线 205、 第一源极 206、 第一漏极 207、 第二源极 206'和第二漏极 207，的图案。
例如， 在第四次构图工艺的过程中， 首先在经过第三次构图工艺的衬底 基板 200上涂布源漏金属层薄膜， 然后在涂布有源漏金属层薄膜的衬底基板 200 形成光刻胶。 利用掩模板对光刻胶进行曝光、 显影后， 形成光刻胶完全 保留区域和光刻胶完全去除区域。所述光刻胶完全保留区域对应数据线 205、 第一源极 206、 第一漏极 207、 第二源极 206'和第二漏极 207'的区域； 所述 光刻胶完全去除区域对应所述像素单元 20 中除所述光刻胶完全保留区域以 再利用灰化工艺剥离掉光刻胶完全保留区域的光刻胶， 形成如图 3所示的数 据线 205、 第一源极 206、 第一漏极 207、 第二源极 206'和第二漏极 207'的图 案。 如图 8所示， 露出源极、 漏极的图案， 形成源极、 漏极。
S5、 通过第五次构图工艺， 在经过第四次构图工艺的衬底基板 200上形 成包括钝化层 212的图案。
例如， 在第五次构图工艺的过程中， 首先在经过第四次构图工艺的衬底 基板 200上涂布钝化层薄膜， 然后在涂布有钝化层薄膜的衬底基板 200形成 光刻胶。 利用掩模板对光刻胶进行曝光、 显影后， 形成光刻胶完全保留区域 和光刻胶完全去除区域。 所述光刻胶完全保留区域对应钝化层 212的区域； 所述光刻胶完全去除区域对应所述像素单元 20 中除所述光刻胶完全保留区 域以外的区域， 例如所述光刻胶完全去除区域包括栅线引线过孔和数据线引 线过孔。 利用刻蚀工艺去除掉光刻胶完全去除区域上的钝化层薄膜， 再利用 灰化工艺剥离掉光刻胶完全保留区域的光刻胶，如图 8所示，形成钝化层 207 的图案、 栅线引线过孔和数据线引线过孔， 栅线引线过孔和数据线引线过孔 图中未示出。
S6、 通过第六次构图工艺， 在经过第五次构图工艺的衬底基板 200上形 成包括像素电极 208的图案， 所述像素电极 208延伸至所述第二漏极 207'并 与所述第二漏极 207'相连。
例如， 在第六次构图工艺的过程中， 首先在经过第五次构图工艺的衬底 基板 200上涂布透明导电层薄膜， 然后在涂布有透明导电层薄膜的衬底基板 200 形成光刻胶。 利用掩模板对光刻胶进行曝光、 显影后， 形成光刻胶完全 保留区域和光刻胶完全去除区域； 所述光刻胶完全保留区域对应像素电极 208的区域； 所述光刻胶完全去除区域对应所述像素单元 20中除所述光刻胶 完全保留区域以外的区域。 利用刻蚀工艺去除掉光刻胶完全去除区域上的透 明导电层薄膜， 再利用灰化工艺剥离掉光刻胶完全保留区域的光刻胶， 如图
10所示， 形成具有狭缝 209的像素电极 208。
本领域所属技术人员很容易得出本发明实施例所提供的底栅结构氧化物 TFT阵列基板可以轻易改为顶栅结构氧化物 TFT阵列基板， 例如， 与底栅结 构氧化物 TFT阵列基板结构制备方法步骤不同， 顶栅结构氧化物 TFT阵列 基板制备方法可以包括：
sr、 通过第一次构图工艺， 在衬底基板上形成包括第一氧化物有源层、 第二氧化物有源层和公共电极的图案。
例如， 在第一次构图工艺的过程中， 首先在衬底基板上涂布透明导电薄 膜、 氧化物有源层薄膜。 然后在涂布有透明导电薄膜、 氧化物有源层薄膜的 衬底基板上形成光刻胶。 利用掩模板对光刻胶进行曝光、 显影后， 形成光刻 胶完全保留区域和光刻胶完全去除区域。 所述光刻胶完全保留区域对应第一 氧化物 TFT的有源层和第二氧化物 TFT的有源层的区域； 所述光刻胶完全 去除区域对应所述像素单元中除所述光刻胶完全保留区域以外的区域。 利用 刻蚀工艺去除掉光刻胶完全去除区域上的氧化物有源层薄膜， 再利用灰化工 艺剥离掉光刻胶完全保留区域的光刻胶， 形成公共电极、 第一氧化物 TFT的 有源层和第二氧化物 TFT的有源层的图案。
S2，、通过第二次构图工艺，在经过第一次构图工艺的衬底基板上形成包 括刻蚀阻挡层的图案。
例如， 在第二次构图工艺的过程中， 首先在经过第一次构图工艺的衬底 基板上涂布刻蚀阻挡层薄膜， 然后在涂布有刻蚀阻挡层薄膜的衬底基板形成 光刻胶。 利用掩模板对光刻胶进行曝光、 显影后， 形成光刻胶完全保留区域 和光刻胶完全去除区域。 所述光刻胶完全保留区域对应刻蚀阻挡层的区域； 所述光刻胶完全去除区域对应所述像素单元中除所述光刻胶完全保留区域以 再利用灰化工艺剥离掉光刻胶完全保留区域的光刻胶， 形成刻蚀阻挡层的图 案。
S3，、通过第三次构图工艺，在经过第二次构图工艺的衬底基板上形成包 括数据线、 第一源极、 第一漏极、 第二源极和第二漏极的图案。
例如， 在第三次构图工艺的过程中， 首先在经过第二次构图工艺的衬底 基板上涂布源、 漏金属层薄膜， 然后在涂布有源、 漏金属层薄膜的衬底基板 形成光刻胶。 利用掩模板对光刻胶进行曝光、 显影后， 形成光刻胶完全保留 区域和光刻胶完全去除区域。 所述光刻胶完全保留区域对应数据线、 第一源 极、 第一漏极、 第二源极和第二漏极的区域； 所述光刻胶完全去除区域对应 所述像素单元中除所述光刻胶完全保留区域以外的区域。 利用刻蚀工艺去除 掉光刻胶完全去除区域上的源、 漏金属层薄膜， 再利用灰化工艺剥离掉光刻 胶完全保留区域的光刻胶， 形成数据线、 第一源极、 第一漏极、 第二源极和 第二漏极的图案。
S4，、通过第四次构图工艺，在经过第三次构图工艺的衬底基板上形成包 括栅绝缘层、 栅线、 和公共电极线的图案。
例如， 在第四次构图工艺的过程中， 首先在经过第三次构图工艺的衬底 基板上涂布栅绝缘层薄膜和栅金属层薄膜。 然后在涂布有栅绝缘层薄膜和栅 金属层薄膜的衬底基板上形成光刻胶。 利用掩模板对光刻胶进行曝光、 显影 后， 形成光刻胶完全保留区域和光刻胶完全去除区域。 所述光刻胶完全保留 区域对应栅金属层薄膜的区域； 所述光刻胶完全去除区域对应所述像素单元 中除所述光刻胶完全保留区域以外的区域。 利用刻蚀工艺去除掉光刻胶完全 去除区域上的栅金属层薄膜， 再利用灰化工艺剥离掉光刻胶完全保留区域的 光刻胶， 形成栅绝缘层、 栅线和公共电极线的图案。
S5，、通过第五次构图工艺，在经过第四次构图工艺的衬底基板上形成包 括钝化层的图案。
例如， 在第五次构图工艺的过程中， 首先在经过第四次构图工艺的衬底 基板上涂布钝化层薄膜， 然后在涂布有钝化层薄膜的衬底基板形成光刻胶。 利用掩模板对光刻胶进行曝光、 显影后， 形成光刻胶完全保留区域和光刻胶 完全去除区域。 所述光刻胶完全保留区域对应钝化层的区域； 所述光刻胶完 全去除区域对应所述像素单元中除所述光刻胶完全保留区域以外的区域， 例 如， 所述光刻胶完全去除区域包括栅线引线过孔和数据线引线过孔。 利用刻 蚀工艺去除掉光刻胶完全去除区域上的钝化层薄膜， 再利用灰化工艺剥离掉 光刻胶完全保留区域的光刻胶， 形成钝化层的图案、 栅线引线过孔和数据线 引线过孔。
S6，、通过第六次构图工艺，在经过第五次构图工艺的衬底基板上形成包 括像素电极的图案。
例如， 在第六次构图工艺的过程中， 首先在经过第五次构图工艺的衬底 基板上涂布透明导电层薄膜， 然后在涂布有透明导电层薄膜的衬底基板形成 光刻胶。 利用掩模板对光刻胶进行曝光、 显影后， 形成光刻胶完全保留区域 和光刻胶完全去除区域。 所述光刻胶完全保留区域对应像素电极的区域； 所 述光刻胶完全去除区域对应所述像素单元中除所述光刻胶完全保留区域以外 的区域。 利用刻蚀工艺去除掉光刻胶完全去除区域上的透明导电层薄膜， 再 利用灰化工艺剥离掉光刻胶完全保留区域的光刻胶， 形成具有狭缝的像素电 极。
需要说明的是，本发明实施例描述的氧化物 TFT阵列基板的制备方法仅 以示例性的六次构图工艺进行描述， 但不能理解为限制本发明实施例仅能釆 用六次构图工艺实现。 其它不同构图工艺次数， 能够使所述阵列基板还包括 第二氧化物 TFT的制备方法， 也属于本发明的保护范围。 本发明实施例提供 的一种氧化物 TFT 阵列基板的制作方法， 在阵列基板上设置有第二氧化物 TFT, 由于在只包括第一氧化物 TFT的阵列基板的基础上， 增加第二氧化物 TFT, 该第二氧化物 TFT增加了像素电极与数据线之间的关态电阻， 能够抑 制 "漏极→氧化物有源层→源极" 的漏电路径， 提升面板的显示品质； 另一 个角度， 与第一氧化物 TFT串联设置的第二氧化物 TFT能够增大 TFT的关 态电阻（R。ffl+Roffi> R。ffl ) ， 减小漏电流。 此外， 当氧化物 TFT开启时， 信 号由第一氧化物 TFT的有源层传至第一漏极，接着传至第二源极， 经第二氧 化物 TFT的有源层传至第二漏极，再通过像素电极上的钝化层过孔传送至像 素电极， 最终可在液晶盒内形成横向电场，供液晶偏转， 通过控制数据信号， 可控制液晶偏转角度， 影响面板透过率。
需要注意的是，上述实施例仅是以釆用氧化物 TFT阵列基板的制备方法 为例进行说明， 但本发明的实施例并不限于此， 而是适用于任何可以通过将 至少两个 TFT串联以抑制 "漏极→有源层→源极"的漏电路径的情形。例如， 在本发明的实施例中， 还可以釆用多晶硅 TFT， 例如低温多晶硅（ LTPS )型 TFT或高温多晶硅 ( HTPS )型 TFT， 这是因为多晶硅 TFT与氧化物 TFT都 具有较高的电子迁移率， 因而更有利于实现 TFT间的串联。 当阵列基板釆用 多晶硅 TFT时， 其制备方法与上述实施例提供的釆用氧化物 TFT阵列基板 的制备方法类似， 重复之处不再赘述。
本发明至少一个实施例提供的阵列基板及制备方法、 显示面板中， 设置 有与第一薄膜晶体管串联的第二薄膜晶体管， 这增加了像素电极与数据线之 间的关态电阻， 能够减小薄膜晶体管的关态漏电流， 从而可改善显示面板的 画面闪烁、 串扰和残像等现象， 提高显示性能。
以上实施方式仅用于说明本发明， 而并非对本发明的限制， 有关技术领 域的普通技术人员， 在不脱离本发明的精神和范围的情况下， 还可以做出各 种变化和变型， 因此所有等同的技术方案也属于本发明的范畴， 本发明的专 利保护范围应由权利要求限定。
本申请要求于 2014年 2月 19日递交的中国专利申请第 201410057337.6 号的优先权， 在此全文引用上述中国专利申请公开的内容以作为本申请的一 部分。

Claims

权利要求书
1、 一种阵列基板， 包括： 衬底基板， 设置于所述衬底基板上的栅线、 数 据线以及多个像素单元，
其中， 每个所述像素单元包括第一薄膜晶体管、 像素电极以及至少一个 与第一薄膜晶体管串联的第二薄膜晶体管，
所述像素电极与所述第二薄膜晶体管的漏极相连， 所述第二薄膜晶体管 的源极与所述第一薄膜晶体管的漏极相连， 所述第一薄膜晶体管的源极与所 述数据线相连。
2、根据权利要求 1所述的阵列基板， 其中， 所述第一和第二薄膜晶体管 为氧化物薄膜晶体管或多晶硅薄膜晶体管。
3、 根据权利要求 1或 2所述的阵列基板， 其中，
所述第一和第二薄膜晶体管的有源层设置在所述衬底基板上； 所述第一薄膜晶体管的源极和漏极以及第二薄膜晶体管的源极和漏极分 别设置在所述第一和第二薄膜晶体管的有源层上；
所述第二薄膜晶体管的漏极与所述像素单元中延伸至所述第二薄膜晶体 管的漏极的所述像素电极相连。
4、 根据权利要求 1-3任一所述的阵列基板， 其中，
所述栅线设置在所述衬底基板上；
栅绝缘层和所述第一和第二薄膜晶体管的有源层设置在所述栅线上； 刻蚀阻挡层设置在所述栅绝缘层和所述第一和第二薄膜晶体管的有源层 上；
所述第一薄膜晶体管的源极和漏极、 第二薄膜晶体管的源极和漏极设置 在所述刻蚀阻挡层上方；
钝化层设置在所述第一薄膜晶体管的源极和漏极、 第二薄膜晶体管的源 极和漏极上；
所述第二薄膜晶体管的漏极与所述像素单元中延伸至所述第二薄膜晶体 管的漏极的所述像素电极相连。
5、 根据权利要求 1-3任一所述的阵列基板， 其中，
所述第一和第二薄膜晶体管的有源层设置在所述衬底基板上； 刻蚀阻挡层设置在所述第一和第二薄膜晶体管的有源层上； 所述第一薄膜晶体管的源极和漏极、 第二薄膜晶体管的源极和漏极设置 在所述刻蚀阻挡层上方；
栅绝缘层设置在所述第一薄膜晶体管的源极和漏极、 第二薄膜晶体管的 源极和漏极上；
所述栅线设置在所述栅绝缘层上；
钝化层设置在所述栅线上；
所述第二薄膜晶体管的漏极与所述像素单元中延伸至所述第二薄膜晶体 管的漏极的所述像素电极相连。
6、 根据权利要求 1-5任一所述的阵列基板， 其中， 所述阵列基板上还设 置有公共电极和公共电极线， 所述公共电极与所述公共电极线相连。
7、 根据权利要求 6所述的阵列基板， 其中，
所述公共电极和所述像素电极异层设置， 处于相对上层的所述像素电极 或所述公共电极包括狭缝状结构， 处于相对下层的所述公共电极或所述像素 电极包括狭缝状结构或板状结构； 或
所述公共电极和所述像素电极同层设置， 所述像素电极和所述公共电极 均包括狭缝状结构。
8、 根据权利要求 3-5任一所述的阵列基板， 其中， 所述有源层为铟镓辞 氧化物、 氧化铟辞、 氧化辞或多晶硅。
9、 一种显示面板， 包括权利要求 1-8任一项所述的阵列基板。
10、 一种阵列基板的制备方法， 包括：
通过构图工艺， 在衬底基板上形成栅线、 数据线以及多个像素单元， 其中， 每个所述像素单元包括第一薄膜晶体管、 像素电极以及至少一个 与所述第一薄膜晶体管串联的第二薄膜晶体管， 所述像素电极与所述第二薄 膜晶体管的漏极相连， 所述第二薄膜晶体管的源极与所述第一薄膜晶体管的 漏极相连， 所述第一薄膜晶体管的源极与所述数据线相连。
11、根据权利要求 10所述的方法， 其中， 所述第一和第二薄膜晶体管为 氧化物薄膜晶体管或多晶硅薄膜晶体管。
12、 根据权利要求 10或 11所述的方法， 其中，
在所述衬底基板上形成包括所述第一薄膜晶体管的有源层以及所述第二 薄膜晶体管的有源层的图案；
在形成有包括所述第一薄膜晶体管的有源层以及所述第二薄膜晶体管的 有源层的图案的衬底基板上形成包括所述第一薄膜晶体管的源极和漏极以及 所述第二薄膜晶体管的源极和漏极的图案；
在形成有包括所述第一薄膜晶体管的源极和漏极以及所述第二薄膜晶体 管的源极和漏极的图案的衬底基板上形成包括像素电极的图案， 使所述像素 电极延伸至所述第二薄膜晶体管的漏极并与所述第二薄膜晶体管的漏极相 连。
13、 根据权利要求 10-12任一所述的方法， 其中，
通过第一次构图工艺， 在衬底基板上形成包括栅线的图案；
通过第二次构图工艺， 在经过第一次构图工艺的衬底基板上形成包括栅 绝缘层、 第一薄膜晶体管的有源层、 以及第二薄膜晶体管的有源层的图案， 所述有源层的图案位于栅线上方；
通过第三次构图工艺， 在经过第二次构图工艺的衬底基板上形成包括刻 蚀阻挡层的图案；
通过第四次构图工艺， 在经过第三次构图工艺的衬底基板上形成包括数 据线、 第一薄膜晶体管的源极和漏极、 以及第二薄膜晶体管的源极和漏极的 图案；
通过第五次构图工艺， 在经过第四次构图工艺的衬底基板上形成包括钝 化层的图案；
通过第六次构图工艺， 在经过第五次构图工艺的衬底基板上形成包括像 素电极的图案， 所述像素电极延伸至所述第二薄膜晶体管的漏极并与所述第 二薄膜晶体管的漏极相连。
14、 根据权利要求 10-12任一所述的方法， 其中，
通过第一次构图工艺， 在衬底基板上形成包括第一薄膜晶体管的有源层 和第二薄膜晶体管的有源层的图案；
通过第二次构图工艺， 在经过第一次构图工艺的衬底基板上形成包括刻 蚀阻挡层的图案；
通过第三次构图工艺， 在经过第二次构图工艺的衬底基板上形成包括数 据线、 第一薄膜晶体管的源极和漏极、 以及第二薄膜晶体管的源极和漏极的 图案；
通过第四次构图工艺， 在经过第三次构图工艺的衬底基板上形成包括栅 绝缘层和栅线的图案， 所述栅线的图案位于有源层的上方；
通过第五次构图工艺， 在经过第四次构图工艺的衬底基板上形成包括钝 化层的图案；
通过第六次构图工艺， 在经过第五次构图工艺的衬底基板上形成包括像 素电极的图案， 所述像素电极延伸至所述第二薄膜晶体管的漏极并与所述第 二薄膜晶体管的漏极相连。
15、 根据权利要求 13或 14所述的方法， 在形成所述栅线的图案的同一 构图工艺中， 还包括： 与栅线同步地形成公共电极线。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113192980A (zh) * 2018-03-21 2021-07-30 福建华佳彩有限公司 一种阵列基板结构、显示装置及阵列基板结构的制备方法

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103811503A (zh) 2014-02-19 2014-05-21 合肥鑫晟光电科技有限公司 阵列基板及制备方法、显示面板
CN104218095B (zh) 2014-09-01 2016-05-25 京东方科技集团股份有限公司 一种薄膜晶体管及其制备方法、阵列基板和显示装置
CN104966696B (zh) * 2015-05-06 2017-11-28 深圳市华星光电技术有限公司 Tft基板的制作方法及其结构
CN105304497B (zh) 2015-09-30 2021-05-14 京东方科技集团股份有限公司 一种薄膜晶体管、阵列基板及相关制作方法
US20200212227A1 (en) * 2016-08-17 2020-07-02 Boe Technology Group Co., Ltd. Thin film transistor, manufacturing method thereof, array substrate, display device
WO2018090496A1 (zh) * 2016-11-17 2018-05-24 华为技术有限公司 一种阵列基板及其制备方法、液晶显示面板
US10212009B2 (en) * 2017-03-06 2019-02-19 Blackberry Limited Modulation for a data bit stream
CN107577365B (zh) * 2017-08-24 2021-01-26 京东方科技集团股份有限公司 一种触控显示基板、装置及驱动方法
US10665622B2 (en) * 2018-07-17 2020-05-26 Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd. Manufacturing method of array substrate and array substrate
CN109564916B (zh) * 2018-10-12 2022-06-28 京东方科技集团股份有限公司 用于电子器件的基板、显示装置、制造用于电子器件的基板的方法
JP2021039291A (ja) * 2019-09-05 2021-03-11 株式会社ジャパンディスプレイ 半導体装置

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08204207A (ja) * 1995-01-28 1996-08-09 Semiconductor Energy Lab Co Ltd アクティブマトリクス表示装置
US6841827B2 (en) * 2001-08-03 2005-01-11 Sanyo Electric Co., Ltd. Semiconductor memory device
US20080006827A1 (en) * 2006-07-06 2008-01-10 Samsung Electronics Co., Ltd. Making thin film transistors on display panels
CN102473736A (zh) * 2009-09-01 2012-05-23 夏普株式会社 半导体装置、有源矩阵基板以及显示装置
CN102484136A (zh) * 2009-08-28 2012-05-30 夏普株式会社 半导体装置、有源矩阵基板以及显示装置
CN103529608A (zh) * 2012-07-04 2014-01-22 乐金显示有限公司 用于液晶显示设备的阵列基板及其制造方法
CN103811503A (zh) * 2014-02-19 2014-05-21 合肥鑫晟光电科技有限公司 阵列基板及制备方法、显示面板
CN203707132U (zh) * 2014-02-19 2014-07-09 合肥鑫晟光电科技有限公司 阵列基板、显示面板

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2834756B2 (ja) * 1989-01-18 1998-12-14 シャープ株式会社 表示電極基板
TW345654B (en) 1995-02-15 1998-11-21 Handotai Energy Kenkyusho Kk Active matrix display device
JP3527034B2 (ja) * 1996-09-20 2004-05-17 株式会社半導体エネルギー研究所 半導体装置
US6420758B1 (en) * 1998-11-17 2002-07-16 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device having an impurity region overlapping a gate electrode
TW517260B (en) * 1999-05-15 2003-01-11 Semiconductor Energy Lab Semiconductor device and method for its fabrication
TW543206B (en) * 1999-06-28 2003-07-21 Semiconductor Energy Lab EL display device and electronic device
JP4831885B2 (ja) * 2001-04-27 2011-12-07 株式会社半導体エネルギー研究所 半導体装置の作製方法
US6862052B2 (en) * 2001-12-14 2005-03-01 Samsung Electronics Co., Ltd. Liquid crystal display, thin film transistor array panel for liquid crystal display and manufacturing method thereof
CN1822385B (zh) * 2005-01-31 2013-02-06 株式会社半导体能源研究所 显示装置及含有其的电子设备
KR100688971B1 (ko) * 2006-02-16 2007-03-08 삼성전자주식회사 디스플레이장치
KR100747491B1 (ko) * 2006-02-20 2007-08-08 삼성전자주식회사 디스플레이장치
KR20070122317A (ko) * 2006-06-26 2007-12-31 삼성전자주식회사 액정 모듈, 액정 모듈의 구동 방법 및 액정표시장치
US8723260B1 (en) * 2009-03-12 2014-05-13 Rf Micro Devices, Inc. Semiconductor radio frequency switch with body contact
CN103187423B (zh) 2013-02-04 2016-03-23 合肥京东方光电科技有限公司 一种氧化物薄膜晶体管阵列基板及其制作方法、显示面板
KR102100927B1 (ko) * 2013-08-05 2020-05-15 삼성전자주식회사 트랜지스터와 그 제조방법 및 트랜지스터를 포함하는 전자소자

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08204207A (ja) * 1995-01-28 1996-08-09 Semiconductor Energy Lab Co Ltd アクティブマトリクス表示装置
US6841827B2 (en) * 2001-08-03 2005-01-11 Sanyo Electric Co., Ltd. Semiconductor memory device
US20080006827A1 (en) * 2006-07-06 2008-01-10 Samsung Electronics Co., Ltd. Making thin film transistors on display panels
CN102484136A (zh) * 2009-08-28 2012-05-30 夏普株式会社 半导体装置、有源矩阵基板以及显示装置
CN102473736A (zh) * 2009-09-01 2012-05-23 夏普株式会社 半导体装置、有源矩阵基板以及显示装置
CN103529608A (zh) * 2012-07-04 2014-01-22 乐金显示有限公司 用于液晶显示设备的阵列基板及其制造方法
CN103811503A (zh) * 2014-02-19 2014-05-21 合肥鑫晟光电科技有限公司 阵列基板及制备方法、显示面板
CN203707132U (zh) * 2014-02-19 2014-07-09 合肥鑫晟光电科技有限公司 阵列基板、显示面板

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113192980A (zh) * 2018-03-21 2021-07-30 福建华佳彩有限公司 一种阵列基板结构、显示装置及阵列基板结构的制备方法
CN113192980B (zh) * 2018-03-21 2023-06-16 福建华佳彩有限公司 一种阵列基板结构、显示装置及阵列基板结构的制备方法

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